BIT9 296 drivers/char/pcmcia/synclink_cs.c #define IRQ_TXREPEAT BIT9 // tx message repeat BIT9 2640 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c u16tmp |= BIT9; BIT9 101 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define ALGO_TRACE_SW_EXEC BIT9 BIT9 367 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_36M BIT9 BIT9 718 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR9 BIT9 BIT9 399 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ BIT9 428 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */ BIT9 102 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define ALGO_TRACE_SW_EXEC BIT9 BIT9 431 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_RATE_ADAPTIVE = BIT9, BIT9 24 drivers/staging/rtl8723bs/hal/odm_DIG.c PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 enable CCX */ BIT9 160 drivers/staging/rtl8723bs/hal/odm_RegDefine11N.h #define ODM_BIT_CCK_RPT_FORMAT_11N BIT9 BIT9 70 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_RATE_ADAPTIVE BIT9 BIT9 617 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_36M BIT9 BIT9 795 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BDOK BIT9 /* Beacon Queue DMA OK Interrup */ BIT9 811 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_C2HCMD BIT9 BIT9 843 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_CPWM2 BIT9 BIT9 866 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_TXFOVW BIT9 BIT9 894 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_CPWM2 BIT9 BIT9 919 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_TXFOVW BIT9 BIT9 948 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ BIT9 977 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */ BIT9 1042 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_AICV BIT9 /* Accept ICV error packet */ BIT9 217 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ BIT9 246 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */ BIT9 53 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_RATE_ADAPTIVE BIT9 /* ODM_BB_RATE_ADAPTIVE */ BIT9 563 drivers/tty/synclink.c #define MISCSTATUS_DSR_LATCHED BIT9 BIT9 586 drivers/tty/synclink.c #define SICR_DSR_ACTIVE BIT9 BIT9 588 drivers/tty/synclink.c #define SICR_DSR (BIT9|BIT8) BIT9 1596 drivers/tty/synclink.c usc_OutDmaReg( info, CDIR, BIT9 | BIT1 ); BIT9 1705 drivers/tty/synclink.c else if ( (DmaVector&(BIT10|BIT9)) == BIT10) BIT9 4694 drivers/tty/synclink.c RegValue |= BIT9; BIT9 4696 drivers/tty/synclink.c RegValue |= ( BIT12 | BIT10 | BIT9 ); BIT9 4769 drivers/tty/synclink.c RegValue |= BIT9 | BIT8; BIT9 4771 drivers/tty/synclink.c RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); BIT9 4940 drivers/tty/synclink.c case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; BIT9 4942 drivers/tty/synclink.c case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; BIT9 5098 drivers/tty/synclink.c case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break; BIT9 5099 drivers/tty/synclink.c case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break; BIT9 416 drivers/tty/synclink_gt.c #define IRQ_RXIDLE BIT9 /* HDLC */ BIT9 417 drivers/tty/synclink_gt.c #define IRQ_RXBREAK BIT9 /* async */ BIT9 4123 drivers/tty/synclink_gt.c val |= BIT9; BIT9 4163 drivers/tty/synclink_gt.c val |= BIT9; BIT9 4286 drivers/tty/synclink_gt.c case HDLC_CRC_16_CCITT: val |= BIT9; break; BIT9 4287 drivers/tty/synclink_gt.c case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; BIT9 4359 drivers/tty/synclink_gt.c case HDLC_CRC_16_CCITT: val |= BIT9; break; BIT9 4360 drivers/tty/synclink_gt.c case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; BIT9 5003 drivers/tty/synclink_gt.c if (!(*(src+1) & (BIT9 + BIT8))) {