BIT8              297 drivers/char/pcmcia/synclink_cs.c #define IRQ_TXFIFO      BIT8	// transmit pool ready
BIT8              100 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define		ALGO_TRACE_SW_DETAIL			BIT8
BIT8              366 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define	RRSR_24M			BIT8
BIT8              717 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR8			BIT8
BIT8              400 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define	IMR_CPWM_8723B			BIT8	/*  CPU power Mode exchange INT Status, Write 1 clear */
BIT8              429 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define	IMR_RXFOVW_8723B		BIT8	/*  Receive FIFO Overflow */
BIT8              101 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define ALGO_TRACE_SW_DETAIL			BIT8
BIT8              430 drivers/staging/rtl8723bs/hal/odm.h 	ODM_BB_PWR_TRAIN		= BIT8,
BIT8              456 drivers/staging/rtl8723bs/hal/odm.h 	ODM_RTL8723B	=	BIT8,
BIT8              539 drivers/staging/rtl8723bs/hal/odm.h 	ODM_WIFI_DISPLAY = BIT8,
BIT8               24 drivers/staging/rtl8723bs/hal/odm_DIG.c 	PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7);	/* 0x890[9:8]=3			enable CCX */
BIT8               69 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_PWR_TRAIN			BIT8
BIT8              167 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);
BIT8              169 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);
BIT8              750 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 		u2tmp = RegRfMod_BW | BIT8;
BIT8              616 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_24M				BIT8
BIT8              796 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_HIGHDOK				BIT8		/*  High Queue DMA OK Interrupt */
BIT8              812 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_CPWM				BIT8
BIT8              844 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_CPWM					BIT8
BIT8              867 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_RXFOVW				BIT8
BIT8              895 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_CPWM					BIT8
BIT8              920 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_RXFOVW				BIT8
BIT8              949 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_CPWM_88E				BIT8			/*  CPU power Mode exchange INT Status, Write 1 clear */
BIT8              978 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_RXFOVW_88E				BIT8			/*  Receive FIFO Overflow */
BIT8             1043 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_ACRC32				BIT8		/*  Accept CRC32 error packet */
BIT8              218 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define	IMR_CPWM_8723B					BIT8			/*  CPU power Mode exchange INT Status, Write 1 clear */
BIT8              247 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define	IMR_RXFOVW_8723B					BIT8			/*  Receive FIFO Overflow */
BIT8               52 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_PWR_TRAIN		BIT8 /* ODM_BB_PWR_TRAIN */
BIT8              502 drivers/tty/synclink.c #define RXSTATUS_SHORT_FRAME		BIT8
BIT8              503 drivers/tty/synclink.c #define RXSTATUS_CODE_VIOLATION		BIT8
BIT8              564 drivers/tty/synclink.c #define MISCSTATUS_DSR			BIT8
BIT8              587 drivers/tty/synclink.c #define SICR_DSR_INACTIVE		BIT8
BIT8              588 drivers/tty/synclink.c #define SICR_DSR			(BIT9|BIT8)
BIT8             1640 drivers/tty/synclink.c 	usc_OutDmaReg(info, CDIR, BIT8 | BIT0 );
BIT8             4769 drivers/tty/synclink.c 		RegValue |= BIT9 | BIT8;
BIT8             4771 drivers/tty/synclink.c 		RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
BIT8             4938 drivers/tty/synclink.c 		case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
BIT8             4942 drivers/tty/synclink.c 		case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break;
BIT8             4989 drivers/tty/synclink.c 	info->mbre_bit = BIT8;
BIT8             4990 drivers/tty/synclink.c 	outw( BIT8, info->io_base );			/* set Master Bus Enable (DCAR) */
BIT8             5096 drivers/tty/synclink.c 	case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break;
BIT8             5097 drivers/tty/synclink.c 	case HDLC_PREAMBLE_PATTERN_ONES:  RegValue |= BIT8; break;
BIT8             5099 drivers/tty/synclink.c 	case HDLC_PREAMBLE_PATTERN_01:    RegValue |= BIT9 | BIT8; break;
BIT8             6040 drivers/tty/synclink.c 		if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1))
BIT8             7238 drivers/tty/synclink.c 		if ( status & (BIT8 | BIT3 | BIT1) ) {
BIT8              418 drivers/tty/synclink_gt.c #define IRQ_RXOVER  BIT8
BIT8             2349 drivers/tty/synclink_gt.c 			if (gsr & (BIT8 << i))
BIT8             4125 drivers/tty/synclink_gt.c 			val |= BIT8;
BIT8             4165 drivers/tty/synclink_gt.c 			val |= BIT8;
BIT8             4214 drivers/tty/synclink_gt.c 	if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
BIT8             4287 drivers/tty/synclink_gt.c 	case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
BIT8             4360 drivers/tty/synclink_gt.c 	case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
BIT8             5003 drivers/tty/synclink_gt.c 			if (!(*(src+1) & (BIT9 + BIT8))) {