BIT7 298 drivers/char/pcmcia/synclink_cs.c #define IRQ_RXEOM BIT7 // receive message end BIT7 678 drivers/char/pcmcia/synclink_cs.c #define CMD_RXFIFO BIT7 // release current rx FIFO BIT7 927 drivers/char/pcmcia/synclink_cs.c if (status & (BIT7 + BIT6)) { BIT7 928 drivers/char/pcmcia/synclink_cs.c if (status & BIT7) BIT7 939 drivers/char/pcmcia/synclink_cs.c if (status & BIT7) BIT7 1235 drivers/char/pcmcia/synclink_cs.c if (gis & BIT7) { BIT7 1476 drivers/char/pcmcia/synclink_cs.c info->read_status_mask |= BIT7 | BIT6; BIT7 1478 drivers/char/pcmcia/synclink_cs.c info->ignore_status_mask |= BIT7 | BIT6; BIT7 3163 drivers/char/pcmcia/synclink_cs.c val |= BIT7 | BIT6; BIT7 3575 drivers/char/pcmcia/synclink_cs.c if (read_reg(info, CHB + VSTR) & BIT7) BIT7 3654 drivers/char/pcmcia/synclink_cs.c if (!(status & BIT7) || (status & BIT4)) BIT7 7 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.h #define BT_INFO_8192E_2ANT_B_FTP BIT7 BIT7 7 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.h #define BT_INFO_8723B_1ANT_B_FTP BIT7 BIT7 10 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.h #define BT_INFO_8723B_2ANT_B_FTP BIT7 BIT7 8 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.h #define BT_INFO_8821A_1ANT_B_FTP BIT7 BIT7 8 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.h #define BT_INFO_8821A_2ANT_B_FTP BIT7 BIT7 99 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define ALGO_TRACE_SW BIT7 BIT7 365 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_18M BIT7 BIT7 32 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ BIT7 93 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \ BIT7 152 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \ BIT7 213 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \ BIT7 218 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ BIT7 282 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \ BIT7 285 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \ BIT7 401 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ BIT7 499 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \ BIT7 540 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \ BIT7 573 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \ BIT7 578 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ BIT7 639 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \ BIT7 642 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \ BIT7 137 drivers/scsi/dc395x.h #define DATAOUT BIT7 BIT7 716 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR7 BIT7 BIT7 410 drivers/staging/rtl8192e/rtllib.h #define FC_QOS_BIT BIT7 BIT7 401 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ BIT7 8 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.h #define BT_INFO_8723B_1ANT_B_FTP BIT7 BIT7 8 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.h #define BT_INFO_8723B_2ANT_B_FTP BIT7 BIT7 100 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define ALGO_TRACE_SW BIT7 BIT7 18 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */ BIT7 18 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */ BIT7 18 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */ BIT7 429 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_PWR_SAVE = BIT7, BIT7 492 drivers/staging/rtl8723bs/hal/odm.h ODM_RF_RX_D = BIT7, BIT7 538 drivers/staging/rtl8723bs/hal/odm.h ODM_WIFI_DIRECT = BIT7, BIT7 25 drivers/staging/rtl8723bs/hal/odm_DIG.c PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /* 0xc0c[7]= 1 max power among all RX ants */ BIT7 122 drivers/staging/rtl8723bs/hal/odm_NoiseMonitor.c reg_c50 &= ~BIT7; BIT7 129 drivers/staging/rtl8723bs/hal/odm_NoiseMonitor.c reg_c58 &= ~BIT7; BIT7 68 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_PWR_SAVE BIT7 BIT7 4323 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1) & BIT7; BIT7 745 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c u2tmp = RegRfMod_BW | BIT7; BIT7 773 drivers/staging/rtl8723bs/hal/sdio_halinit.c if (rtw_read8(padapter, REG_MCUFWDL) & BIT7) { BIT7 563 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HSIMR_PDN_INT_EN BIT7 BIT7 572 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HSISR_PDNINT BIT7 BIT7 615 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_18M BIT7 BIT7 797 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_TBDOK BIT7 /* Transmit Beacon OK interrup */ BIT7 845 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_HIGHDOK BIT7 /* High Queue DMA OK Interrupt */ BIT7 896 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_HIGHDOK BIT7 /* High Queue DMA OK Interrupt */ BIT7 950 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ BIT7 1044 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet (Rx beacon, probe rsp) */ BIT7 1574 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_TXBCNERR_MSK BIT7 BIT7 1600 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_TXBCNERR BIT7 BIT7 1691 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PARTNO_92D_NIC (BIT7|BIT6) BIT7 1714 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL_8192EU_HW_GPIO_WPS_BIT BIT7 BIT7 1715 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL_8188E_HW_GPIO_WPS_BIT BIT7 BIT7 53 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]= 0*/ \ BIT7 94 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ BIT7 114 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ BIT7 129 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ BIT7 134 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ BIT7 162 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]= 0 TSF in 40M*/\ BIT7 163 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ BIT7 192 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\ BIT7 201 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\ BIT7 211 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \ BIT7 219 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ BIT7 51 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_PWR_SAVE BIT7 /* ODM_BB_PWR_SAVE */ BIT7 504 drivers/tty/synclink.c #define RXSTATUS_EXITED_HUNT BIT7 BIT7 544 drivers/tty/synclink.c #define TXSTATUS_PREAMBLE_SENT BIT7 BIT7 565 drivers/tty/synclink.c #define MISCSTATUS_DCD_LATCHED BIT7 BIT7 589 drivers/tty/synclink.c #define SICR_DCD_ACTIVE BIT7 BIT7 591 drivers/tty/synclink.c #define SICR_DCD (BIT7|BIT6) BIT7 625 drivers/tty/synclink.c #define TXSTATUS_PREAMBLE_SENT BIT7 BIT7 2900 drivers/tty/synclink.c usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7)); BIT7 2902 drivers/tty/synclink.c usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7)); BIT7 5138 drivers/tty/synclink.c usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6)); BIT7 5177 drivers/tty/synclink.c usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6)); BIT7 7547 drivers/tty/synclink.c return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ; BIT7 419 drivers/tty/synclink_gt.c #define IRQ_DSR BIT7 BIT7 2855 drivers/tty/synclink_gt.c val |= BIT7; BIT7 2857 drivers/tty/synclink_gt.c val &= ~BIT7; BIT7 4120 drivers/tty/synclink_gt.c val |= BIT7; BIT7 4271 drivers/tty/synclink_gt.c val |= BIT7; BIT7 4388 drivers/tty/synclink_gt.c val |= BIT7; /* 100, txclk = DPLL Input */ BIT7 4411 drivers/tty/synclink_gt.c val = BIT7; break; BIT7 4414 drivers/tty/synclink_gt.c val = BIT7 + BIT6; break; BIT7 4538 drivers/tty/synclink_gt.c val |= BIT7 + BIT6 + BIT5; /* 1110 */ BIT7 415 drivers/tty/synclinkmp.c #define TXINTE BIT7 BIT7 421 drivers/tty/synclinkmp.c #define UDRN BIT7 BIT7 434 drivers/tty/synclinkmp.c #define EOM BIT7 BIT7 2580 drivers/tty/synclinkmp.c if (timerstatus0 & (BIT7 | BIT6)) BIT7 2584 drivers/tty/synclinkmp.c if (timerstatus1 & (BIT7 | BIT6)) BIT7 4560 drivers/tty/synclinkmp.c case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ BIT7 4561 drivers/tty/synclinkmp.c case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ BIT7 4562 drivers/tty/synclinkmp.c case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */ BIT7 55 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); BIT7 62 drivers/video/fbdev/via/dvi.c BIT5 + BIT6 + BIT7); BIT7 453 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR91, VIACR, 0, BIT7); BIT7 466 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7); BIT7 471 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR11, VIACR, 0, BIT7); BIT7 945 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); BIT7 1669 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); BIT7 1676 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); BIT7 2034 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7); BIT7 2042 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7); BIT7 376 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); BIT7 388 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7); BIT7 611 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); BIT7 620 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); BIT7 627 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7); BIT7 639 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); BIT7 663 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); BIT7 672 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); BIT7 682 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0, BIT7); BIT7 694 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); BIT7 746 drivers/video/fbdev/via/lcd.c BIT7 + BIT2 + BIT1 + BIT0); BIT7 138 drivers/video/fbdev/via/via_utility.c viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); BIT7 148 drivers/video/fbdev/via/via_utility.c viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7); BIT7 193 drivers/video/fbdev/via/via_utility.c viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); BIT7 203 drivers/video/fbdev/via/via_utility.c viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);