BIT6 299 drivers/char/pcmcia/synclink_cs.c #define IRQ_EXITHUNT BIT6 // receive frame start BIT6 300 drivers/char/pcmcia/synclink_cs.c #define IRQ_RXTIME BIT6 // rx char timeout BIT6 307 drivers/char/pcmcia/synclink_cs.c #define XFW BIT6 // transmit FIFO write enable BIT6 679 drivers/char/pcmcia/synclink_cs.c #define CMD_RXRESET BIT6 // receiver reset BIT6 927 drivers/char/pcmcia/synclink_cs.c if (status & (BIT7 + BIT6)) { BIT6 941 drivers/char/pcmcia/synclink_cs.c else if (status & BIT6) BIT6 1476 drivers/char/pcmcia/synclink_cs.c info->read_status_mask |= BIT7 | BIT6; BIT6 1478 drivers/char/pcmcia/synclink_cs.c info->ignore_status_mask |= BIT7 | BIT6; BIT6 2184 drivers/char/pcmcia/synclink_cs.c set_reg_bits(info, CHA+DAFO, BIT6); BIT6 2186 drivers/char/pcmcia/synclink_cs.c clear_reg_bits(info, CHA+DAFO, BIT6); BIT6 3157 drivers/char/pcmcia/synclink_cs.c val |= BIT6; BIT6 3160 drivers/char/pcmcia/synclink_cs.c val |= BIT6; BIT6 3163 drivers/char/pcmcia/synclink_cs.c val |= BIT7 | BIT6; BIT6 3247 drivers/char/pcmcia/synclink_cs.c clear_reg_bits(info, CHA + CCR0, BIT6); BIT6 3414 drivers/char/pcmcia/synclink_cs.c val |= BIT6; BIT6 3597 drivers/char/pcmcia/synclink_cs.c val &= ~BIT6; BIT6 3599 drivers/char/pcmcia/synclink_cs.c val |= BIT6; BIT6 3656 drivers/char/pcmcia/synclink_cs.c else if (status & BIT6) BIT6 8 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.h #define BT_INFO_8192E_2ANT_B_A2DP BIT6 BIT6 691 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c real_byte5 &= ~BIT6; BIT6 8 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.h #define BT_INFO_8723B_1ANT_B_A2DP BIT6 BIT6 11 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.h #define BT_INFO_8723B_2ANT_B_A2DP BIT6 BIT6 840 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c real_byte5 &= ~BIT6; BIT6 9 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.h #define BT_INFO_8821A_1ANT_B_A2DP BIT6 BIT6 9 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.h #define BT_INFO_8821A_2ANT_B_A2DP BIT6 BIT6 98 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define ALGO_TRACE_FW_EXEC BIT6 BIT6 364 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_12M BIT6 BIT6 285 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \ BIT6 420 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \ BIT6 444 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \ BIT6 642 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \ BIT6 138 drivers/scsi/dc395x.h #define DATAIN BIT6 BIT6 180 drivers/scsi/dc395x.h #define EN_ATN_STOP BIT6 BIT6 715 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR6 BIT6 BIT6 6452 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c ctrl = BIT(15) | BIT6 | ((pparm->algorithm) << 2) | pparm->keyid; BIT6 660 drivers/staging/rtl8723bs/core/rtw_wlan_util.c ret = (dvobj->cam_cache[cam_id].ctrl&BIT6)?true:false; BIT6 402 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */ BIT6 1330 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c realByte5 &= ~BIT6; BIT6 9 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.h #define BT_INFO_8723B_1ANT_B_A2DP BIT6 BIT6 9 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.h #define BT_INFO_8723B_2ANT_B_A2DP BIT6 BIT6 99 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define ALGO_TRACE_FW_EXEC BIT6 BIT6 19 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ BIT6 19 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ BIT6 19 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ BIT6 428 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_ANT_DIV = BIT6, BIT6 491 drivers/staging/rtl8723bs/hal/odm.h ODM_RF_RX_C = BIT6, BIT6 537 drivers/staging/rtl8723bs/hal/odm.h ODM_AD_HOC = BIT6, BIT6 551 drivers/staging/rtl8723bs/hal/odm.h ODM_WM_AC = BIT6, BIT6 67 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_ANT_DIV BIT6 BIT6 230 drivers/staging/rtl8723bs/include/hal_com_phycfg.h #define LOAD_RF_TXPWR_LMT_PARA_FILE BIT6 BIT6 562 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HSIMR_RON_INT_EN BIT6 BIT6 571 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HSISR_RON_INT BIT6 BIT6 614 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_12M BIT6 BIT6 798 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ BIT6 846 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ BIT6 897 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ BIT6 951 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */ BIT6 1009 drivers/staging/rtl8723bs/include/hal_com_reg.h #define StopBecon BIT6 BIT6 1045 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet (Data) */ BIT6 1573 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_TXBCNOK_MSK BIT6 BIT6 1599 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_TXBCNOK BIT6 BIT6 1691 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PARTNO_92D_NIC (BIT7|BIT6) BIT6 57 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \ BIT6 64 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\ BIT6 75 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\ BIT6 163 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ BIT6 212 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \ BIT6 220 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */ BIT6 50 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_ANT_DIV BIT6 /* ODM_BB_ANT_DIV */ BIT6 215 drivers/staging/rtl8723bs/os_dep/os_intfs.c static int rtw_load_phy_file = (BIT2 | BIT6); BIT6 505 drivers/tty/synclink.c #define RXSTATUS_IDLE_RECEIVED BIT6 BIT6 545 drivers/tty/synclink.c #define TXSTATUS_IDLE_SENT BIT6 BIT6 566 drivers/tty/synclink.c #define MISCSTATUS_DCD BIT6 BIT6 590 drivers/tty/synclink.c #define SICR_DCD_INACTIVE BIT6 BIT6 591 drivers/tty/synclink.c #define SICR_DCD (BIT7|BIT6) BIT6 626 drivers/tty/synclink.c #define TXSTATUS_IDLE_SENT BIT6 BIT6 5138 drivers/tty/synclink.c usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6)); BIT6 5177 drivers/tty/synclink.c usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6)); BIT6 5847 drivers/tty/synclink.c RegValue |= BIT6; BIT6 5904 drivers/tty/synclink.c RegValue |= BIT6; BIT6 6183 drivers/tty/synclink.c Control &= ~(BIT6); BIT6 6185 drivers/tty/synclink.c Control |= BIT6; BIT6 7197 drivers/tty/synclink.c while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) { BIT6 420 drivers/tty/synclink_gt.c #define IRQ_CTS BIT6 BIT6 1387 drivers/tty/synclink_gt.c value |= BIT6; BIT6 1389 drivers/tty/synclink_gt.c value &= ~BIT6; BIT6 3981 drivers/tty/synclink_gt.c wr_reg32(info, RDCSR, BIT6); BIT6 3994 drivers/tty/synclink_gt.c wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); BIT6 4291 drivers/tty/synclink_gt.c val |= BIT6; BIT6 4383 drivers/tty/synclink_gt.c val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ BIT6 4385 drivers/tty/synclink_gt.c val |= BIT6; /* 010, txclk = BRG */ BIT6 4414 drivers/tty/synclink_gt.c val = BIT7 + BIT6; break; BIT6 4415 drivers/tty/synclink_gt.c default: val = BIT6; // NRZ encodings BIT6 4468 drivers/tty/synclink_gt.c tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; BIT6 4471 drivers/tty/synclink_gt.c } else if (!(tcr & BIT6)) { BIT6 4538 drivers/tty/synclink_gt.c val |= BIT7 + BIT6 + BIT5; /* 1110 */ BIT6 4541 drivers/tty/synclink_gt.c val |= BIT6; /* 0100 */ BIT6 416 drivers/tty/synclinkmp.c #define RXINTE BIT6 BIT6 422 drivers/tty/synclinkmp.c #define IDLE BIT6 BIT6 435 drivers/tty/synclinkmp.c #define PMP BIT6 BIT6 436 drivers/tty/synclinkmp.c #define SHRT BIT6 BIT6 2580 drivers/tty/synclinkmp.c if (timerstatus0 & (BIT7 | BIT6)) BIT6 2584 drivers/tty/synclinkmp.c if (timerstatus1 & (BIT7 | BIT6)) BIT6 4424 drivers/tty/synclinkmp.c RegValue=BIT6; BIT6 4433 drivers/tty/synclinkmp.c RegValue=BIT6; BIT6 4561 drivers/tty/synclinkmp.c case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ BIT6 4589 drivers/tty/synclinkmp.c RegValue |= BIT6; BIT6 4591 drivers/tty/synclinkmp.c RegValue |= BIT6 + BIT5; BIT6 4602 drivers/tty/synclinkmp.c RegValue |= BIT6; BIT6 4604 drivers/tty/synclinkmp.c RegValue |= BIT6 + BIT5; BIT6 4906 drivers/tty/synclinkmp.c status |= BIT6; BIT6 4908 drivers/tty/synclinkmp.c if (status & (BIT6+BIT5+BIT3+BIT2)) { BIT6 4912 drivers/tty/synclinkmp.c if (status & BIT6) BIT6 5089 drivers/tty/synclinkmp.c write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); BIT6 55 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); BIT6 62 drivers/video/fbdev/via/dvi.c BIT5 + BIT6 + BIT7); BIT6 421 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); BIT6 1669 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); BIT6 1676 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); BIT6 1680 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); BIT6 2033 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); BIT6 2035 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); BIT6 2041 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); BIT6 2043 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); BIT6 376 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); BIT6 611 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); BIT6 620 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); BIT6 633 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6); BIT6 639 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); BIT6 663 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); BIT6 672 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); BIT6 688 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0, BIT6); BIT6 694 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);