BIT5 680 drivers/char/pcmcia/synclink_cs.c #define CMD_RXFIFO_READ BIT5 BIT5 908 drivers/char/pcmcia/synclink_cs.c if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5)) BIT5 3001 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); BIT5 3128 drivers/char/pcmcia/synclink_cs.c val |= BIT5; BIT5 3153 drivers/char/pcmcia/synclink_cs.c val |= BIT5; BIT5 3216 drivers/char/pcmcia/synclink_cs.c val |= BIT5; BIT5 3490 drivers/char/pcmcia/synclink_cs.c val |= BIT5; BIT5 3533 drivers/char/pcmcia/synclink_cs.c val |= BIT5; BIT5 3658 drivers/char/pcmcia/synclink_cs.c else if (!(status & BIT5)) { BIT5 3689 drivers/char/pcmcia/synclink_cs.c if (status & BIT5) BIT5 3693 drivers/char/pcmcia/synclink_cs.c *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR; BIT5 9 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.h #define BT_INFO_8192E_2ANT_B_HID BIT5 BIT5 684 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c if ((byte1 & BIT4) && !(byte1 & BIT5)) { BIT5 688 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c real_byte1 |= BIT5; BIT5 690 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c real_byte5 |= BIT5; BIT5 9 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.h #define BT_INFO_8723B_1ANT_B_HID BIT5 BIT5 12 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.h #define BT_INFO_8723B_2ANT_B_HID BIT5 BIT5 833 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c if (byte1 & BIT4 && !(byte1 & BIT5)) { BIT5 837 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c real_byte1 |= BIT5; BIT5 839 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c real_byte5 |= BIT5; BIT5 10 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.h #define BT_INFO_8821A_1ANT_B_HID BIT5 BIT5 10 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.h #define BT_INFO_8821A_2ANT_B_HID BIT5 BIT5 97 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define ALGO_TRACE_FW_DETAIL BIT5 BIT5 363 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_9M BIT5 BIT5 262 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \ BIT5 383 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \ BIT5 416 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \ BIT5 466 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \ BIT5 619 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \ BIT5 134 drivers/scsi/dc395x.h #define SRB_ERROR BIT5 BIT5 139 drivers/scsi/dc395x.h #define RESIDUAL_VALID BIT5 BIT5 179 drivers/scsi/dc395x.h #define EN_TAG_QUEUEING BIT5 BIT5 635 drivers/scsi/dc395x.h #define LUN_CHECK BIT5 BIT5 714 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR5 BIT5 BIT5 2607 drivers/staging/rtl8723bs/core/rtw_mlme.c if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT5)) BIT5 2617 drivers/staging/rtl8723bs/core/rtw_mlme.c if (TEST_FLAG(pregistrypriv->stbc_cap, BIT5)) BIT5 2636 drivers/staging/rtl8723bs/core/rtw_mlme.c if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) { BIT5 403 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */ BIT5 1320 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c if (byte1&BIT4 && !(byte1&BIT5)) { BIT5 1327 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c realByte1 |= BIT5; BIT5 1329 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c realByte5 |= BIT5; BIT5 10 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.h #define BT_INFO_8723B_1ANT_B_HID BIT5 BIT5 10 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.h #define BT_INFO_8723B_2ANT_B_HID BIT5 BIT5 98 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define ALGO_TRACE_FW_DETAIL BIT5 BIT5 1394 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5))); BIT5 427 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_CCK_PD = BIT5, BIT5 490 drivers/staging/rtl8723bs/hal/odm.h ODM_RF_RX_B = BIT5, BIT5 536 drivers/staging/rtl8723bs/hal/odm.h ODM_CLIENT_MODE = BIT5, BIT5 550 drivers/staging/rtl8723bs/hal/odm.h ODM_WM_AUTO = BIT5, BIT5 66 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_CCK_PD BIT5 BIT5 229 drivers/staging/rtl8723bs/include/hal_com_phycfg.h #define LOAD_RF_TXPWR_TRACK_PARA_FILE BIT5 BIT5 531 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CmdEEPROM_En BIT5 /* EEPROM enable when set 1 */ BIT5 539 drivers/staging/rtl8723bs/include/hal_com_reg.h #define GPIOSEL_ENBT BIT5 BIT5 561 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HSIMR_SPS_OCP_INT_EN BIT5 BIT5 570 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HSISR_SPS_OCP_INT BIT5 BIT5 613 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_9M BIT5 BIT5 735 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CAM_USEDK BIT5 BIT5 799 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_TBDER BIT5 /* For 92C, Transmit Beacon Error Interrupt */ BIT5 847 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */ BIT5 898 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */ BIT5 952 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */ BIT5 1010 drivers/staging/rtl8723bs/include/hal_com_reg.h #define StopHigh BIT5 BIT5 1047 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_APWRMGT BIT5 /* Accept power management packet */ BIT5 1572 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_RXFOVW_MSK BIT5 BIT5 1598 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_RXFOVW BIT5 BIT5 1692 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PARTNO_92D_NIC_REMARK (BIT5|BIT4) BIT5 47 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital , 1:isolation*/ \ BIT5 76 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital , 1:isolation*/ \ BIT5 151 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ BIT5 182 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/ \ BIT5 182 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define BIT_BCN_PORT_SEL BIT5 BIT5 221 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */ BIT5 49 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_CCK_PD BIT5 /* ODM_BB_CCK_PD */ BIT5 490 drivers/tty/synclink.c #define RECEIVE_STATUS BIT5 BIT5 506 drivers/tty/synclink.c #define RXSTATUS_BREAK_RECEIVED BIT5 BIT5 507 drivers/tty/synclink.c #define RXSTATUS_ABORT_RECEIVED BIT5 BIT5 546 drivers/tty/synclink.c #define TXSTATUS_ABORT_SENT BIT5 BIT5 567 drivers/tty/synclink.c #define MISCSTATUS_CTS_LATCHED BIT5 BIT5 592 drivers/tty/synclink.c #define SICR_CTS_ACTIVE BIT5 BIT5 594 drivers/tty/synclink.c #define SICR_CTS (BIT5|BIT4) BIT5 627 drivers/tty/synclink.c #define TXSTATUS_ABORT_SENT BIT5 BIT5 5845 drivers/tty/synclink.c RegValue |= BIT5; BIT5 5902 drivers/tty/synclink.c RegValue |= BIT5; BIT5 7103 drivers/tty/synclink.c if ( !(status & BIT4) && (status & BIT5) ) { BIT5 7197 drivers/tty/synclink.c while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) { BIT5 7212 drivers/tty/synclink.c if ( status & (BIT5 | BIT1) ) BIT5 421 drivers/tty/synclink_gt.c #define IRQ_DCD BIT5 BIT5 2199 drivers/tty/synclink_gt.c if (status & (BIT5 + BIT4)) { BIT5 2224 drivers/tty/synclink_gt.c if (status & (BIT5 + BIT4 + BIT3)) { BIT5 4131 drivers/tty/synclink_gt.c case 7: val |= BIT5; break; BIT5 4132 drivers/tty/synclink_gt.c case 8: val |= BIT5 + BIT4; break; BIT5 4171 drivers/tty/synclink_gt.c case 7: val |= BIT5; break; BIT5 4172 drivers/tty/synclink_gt.c case 8: val |= BIT5 + BIT4; break; BIT5 4295 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; BIT5 4297 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; BIT5 4383 drivers/tty/synclink_gt.c val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ BIT5 4390 drivers/tty/synclink_gt.c val |= BIT5; /* 001, txclk = RXC Input */ BIT5 4468 drivers/tty/synclink_gt.c tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; BIT5 4473 drivers/tty/synclink_gt.c tcr &= ~(BIT5 + BIT4); BIT5 4535 drivers/tty/synclink_gt.c val |= BIT5; /* 0010 */ BIT5 4538 drivers/tty/synclink_gt.c val |= BIT7 + BIT6 + BIT5; /* 1110 */ BIT5 4944 drivers/tty/synclink_gt.c info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; BIT5 437 drivers/tty/synclinkmp.c #define PE BIT5 BIT5 438 drivers/tty/synclinkmp.c #define ABT BIT5 BIT5 2578 drivers/tty/synclinkmp.c if (timerstatus0 & (BIT5 | BIT4)) BIT5 2582 drivers/tty/synclinkmp.c if (timerstatus1 & (BIT5 | BIT4)) BIT5 4396 drivers/tty/synclinkmp.c case 6: RegValue |= BIT5 + BIT3; break; BIT5 4397 drivers/tty/synclinkmp.c case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; BIT5 4559 drivers/tty/synclinkmp.c case HDLC_ENCODING_NRZI: RegValue |= BIT5; break; BIT5 4560 drivers/tty/synclinkmp.c case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ BIT5 4591 drivers/tty/synclinkmp.c RegValue |= BIT6 + BIT5; BIT5 4604 drivers/tty/synclinkmp.c RegValue |= BIT6 + BIT5; BIT5 4908 drivers/tty/synclinkmp.c if (status & (BIT6+BIT5+BIT3+BIT2)) { BIT5 4914 drivers/tty/synclinkmp.c else if (status & BIT5) BIT5 5192 drivers/tty/synclinkmp.c lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3); BIT5 5197 drivers/tty/synclinkmp.c lcr1_brdr_value |= BIT5 + BIT4 + BIT3; BIT5 5200 drivers/tty/synclinkmp.c lcr1_brdr_value |= BIT5 + BIT4; BIT5 5203 drivers/tty/synclinkmp.c lcr1_brdr_value |= BIT5 + BIT3; BIT5 5206 drivers/tty/synclinkmp.c lcr1_brdr_value |= BIT5; BIT5 62 drivers/video/fbdev/via/dvi.c BIT5 + BIT6 + BIT7); BIT5 66 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); BIT5 396 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); BIT5 408 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); BIT5 1696 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); BIT5 1702 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); BIT5 1713 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); BIT5 1717 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); BIT5 1720 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); BIT5 1725 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); BIT5 1728 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); BIT5 2065 drivers/video/fbdev/via/hw.c p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); BIT5 1114 drivers/video/fbdev/via/viafbdev.c (viafb_read_reg(VIASR, SR2A) & BIT5) >> 4 | BIT5 1156 drivers/video/fbdev/via/viafbdev.c reg_val << 4, BIT5);