BIT4 681 drivers/char/pcmcia/synclink_cs.c #define CMD_START_TIMER BIT4 BIT4 3001 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); BIT4 3088 drivers/char/pcmcia/synclink_cs.c val |= BIT4; BIT4 3091 drivers/char/pcmcia/synclink_cs.c val |= BIT4 | BIT2; BIT4 3094 drivers/char/pcmcia/synclink_cs.c val |= BIT4 | BIT3; BIT4 3130 drivers/char/pcmcia/synclink_cs.c val |= BIT4; BIT4 3497 drivers/char/pcmcia/synclink_cs.c val |= BIT4; BIT4 3654 drivers/char/pcmcia/synclink_cs.c if (!(status & BIT7) || (status & BIT4)) BIT4 2645 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c u8tmp |= BIT4; BIT4 3070 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c if (!(coex_sta->bt_info_ext & BIT4)) BIT4 10 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.h #define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4 BIT4 684 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c if ((byte1 & BIT4) && !(byte1 & BIT5)) { BIT4 687 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c real_byte1 &= ~BIT4; BIT4 3193 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c if (coex_sta->bt_info_ext & BIT4) { BIT4 10 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.h #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4 BIT4 4069 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c if (!(coex_sta->bt_info_ext & BIT4)) BIT4 13 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.h #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4 BIT4 833 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c if (byte1 & BIT4 && !(byte1 & BIT5)) { BIT4 836 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c real_byte1 &= ~BIT4; BIT4 11 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.h #define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4 BIT4 11 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.h #define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4 BIT4 96 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define ALGO_TRACE_FW BIT4 BIT4 108 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define WIFI_P2P_GC_CONNECTED BIT4 BIT4 362 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_6M BIT4 BIT4 99 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \ BIT4 161 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \ BIT4 279 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \ BIT4 375 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \ BIT4 386 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \ BIT4 404 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \ BIT4 416 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \ BIT4 475 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \ BIT4 479 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \ BIT4 482 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \ BIT4 488 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \ BIT4 508 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \ BIT4 511 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \ BIT4 520 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \ BIT4 529 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \ BIT4 552 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \ BIT4 555 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \ BIT4 563 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \ BIT4 636 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \ BIT4 133 drivers/scsi/dc395x.h #define PARITY_ERROR BIT4 BIT4 140 drivers/scsi/dc395x.h #define ENABLE_TIMER BIT4 BIT4 178 drivers/scsi/dc395x.h #define WIDE_NEGO_STATE BIT4 BIT4 634 drivers/scsi/dc395x.h #define NO_SEEK BIT4 BIT4 713 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR4 BIT4 BIT4 1396 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); BIT4 1457 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c BIT4, 0x1); BIT4 26 drivers/staging/rtl8192e/rtl8192e/rtl_pci.c tmp |= BIT4; BIT4 2602 drivers/staging/rtl8723bs/core/rtw_mlme.c if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT4)) BIT4 2622 drivers/staging/rtl8723bs/core/rtw_mlme.c if (TEST_FLAG(pregistrypriv->stbc_cap, BIT4)) BIT4 2632 drivers/staging/rtl8723bs/core/rtw_mlme.c if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) { BIT4 404 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */ BIT4 1320 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c if (byte1&BIT4 && !(byte1&BIT5)) { BIT4 1326 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c realByte1 &= ~BIT4; BIT4 11 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.h #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4 BIT4 11 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.h #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4 BIT4 97 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define ALGO_TRACE_FW BIT4 BIT4 109 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define WIFI_P2P_GC_CONNECTED BIT4 BIT4 16 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ BIT4 16 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ BIT4 16 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ BIT4 1707 drivers/staging/rtl8723bs/hal/hal_com.c if (value & BIT4) { BIT4 426 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_RSSI_MONITOR = BIT4, BIT4 489 drivers/staging/rtl8723bs/hal/odm.h ODM_RF_RX_A = BIT4, BIT4 535 drivers/staging/rtl8723bs/hal/odm.h ODM_AP_MODE = BIT4, BIT4 549 drivers/staging/rtl8723bs/hal/odm.h ODM_WM_N5G = BIT4, BIT4 65 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_RSSI_MONITOR BIT4 BIT4 701 drivers/staging/rtl8723bs/hal/sdio_halinit.c if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode) BIT4 228 drivers/staging/rtl8723bs/include/hal_com_phycfg.h #define LOAD_RF_PARA_FILE BIT4 BIT4 532 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CmdEERPOMSEL BIT4 /* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ BIT4 533 drivers/staging/rtl8723bs/include/hal_com_reg.h #define Cmd9346CR_9356SEL BIT4 BIT4 612 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_6M BIT4 BIT4 637 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT4 BIT4 800 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BKDOK BIT4 /* AC_BK DMA OK Interrupt */ BIT4 848 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */ BIT4 899 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */ BIT4 953 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */ BIT4 1011 drivers/staging/rtl8723bs/include/hal_com_reg.h #define StopMgt BIT4 BIT4 1048 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_ADD3 BIT4 /* Accept address 3 match packet */ BIT4 1571 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_TXFOVW_MSK BIT4 BIT4 1597 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_TXFOVW BIT4 BIT4 1692 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PARTNO_92D_NIC_REMARK (BIT5|BIT4) BIT4 45 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ BIT4 48 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \ BIT4 54 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ BIT4 83 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ BIT4 84 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ BIT4 85 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ BIT4 87 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ BIT4 97 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ BIT4 98 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ BIT4 104 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ BIT4 107 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ BIT4 118 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ BIT4 119 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ BIT4 126 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ BIT4 161 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ BIT4 191 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\ BIT4 200 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\ BIT4 222 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */ BIT4 48 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_RSSI_MONITOR BIT4 /* ODM_BB_RSSI_MONITOR */ BIT4 491 drivers/tty/synclink.c #define RECEIVE_DATA BIT4 BIT4 508 drivers/tty/synclink.c #define RXSTATUS_RXBOUND BIT4 BIT4 547 drivers/tty/synclink.c #define TXSTATUS_EOF_SENT BIT4 BIT4 548 drivers/tty/synclink.c #define TXSTATUS_EOM_SENT BIT4 BIT4 568 drivers/tty/synclink.c #define MISCSTATUS_CTS BIT4 BIT4 593 drivers/tty/synclink.c #define SICR_CTS_INACTIVE BIT4 BIT4 594 drivers/tty/synclink.c #define SICR_CTS (BIT5|BIT4) BIT4 628 drivers/tty/synclink.c #define TXSTATUS_EOF BIT4 BIT4 4660 drivers/tty/synclink.c RegValue |= BIT4; BIT4 4932 drivers/tty/synclink.c RegValue |= BIT4; /* enable BRG1 */ BIT4 5842 drivers/tty/synclink.c RegValue |= BIT4 | BIT3 | BIT2; BIT4 5899 drivers/tty/synclink.c RegValue |= BIT4 | BIT3 | BIT2; BIT4 6040 drivers/tty/synclink.c if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1)) BIT4 6188 drivers/tty/synclink.c Control &= ~(BIT4); BIT4 6190 drivers/tty/synclink.c Control |= BIT4; BIT4 7103 drivers/tty/synclink.c if ( !(status & BIT4) && (status & BIT5) ) { BIT4 7197 drivers/tty/synclink.c while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) { BIT4 384 drivers/tty/synclink_gt.c #define MASK_OVERRUN BIT4 BIT4 422 drivers/tty/synclink_gt.c #define IRQ_RI BIT4 BIT4 2199 drivers/tty/synclink_gt.c if (status & (BIT5 + BIT4)) { BIT4 2224 drivers/tty/synclink_gt.c if (status & (BIT5 + BIT4 + BIT3)) { BIT4 4130 drivers/tty/synclink_gt.c case 6: val |= BIT4; break; BIT4 4132 drivers/tty/synclink_gt.c case 8: val |= BIT5 + BIT4; break; BIT4 4170 drivers/tty/synclink_gt.c case 6: val |= BIT4; break; BIT4 4172 drivers/tty/synclink_gt.c case 8: val |= BIT5 + BIT4; break; BIT4 4296 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; BIT4 4297 drivers/tty/synclink_gt.c case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; BIT4 4395 drivers/tty/synclink_gt.c val |= BIT4; /* 100, rxclk = DPLL */ BIT4 4468 drivers/tty/synclink_gt.c tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; BIT4 4473 drivers/tty/synclink_gt.c tcr &= ~(BIT5 + BIT4); BIT4 4546 drivers/tty/synclink_gt.c val |= BIT4; BIT4 423 drivers/tty/synclinkmp.c #define SYNCD BIT4 BIT4 424 drivers/tty/synclinkmp.c #define FLGD BIT4 BIT4 439 drivers/tty/synclinkmp.c #define FRME BIT4 BIT4 440 drivers/tty/synclinkmp.c #define RBIT BIT4 BIT4 2578 drivers/tty/synclinkmp.c if (timerstatus0 & (BIT5 | BIT4)) BIT4 2582 drivers/tty/synclinkmp.c if (timerstatus1 & (BIT5 | BIT4)) BIT4 4395 drivers/tty/synclinkmp.c case 7: RegValue |= BIT4 + BIT2; break; BIT4 4397 drivers/tty/synclinkmp.c case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; BIT4 4528 drivers/tty/synclinkmp.c RegValue |= BIT4; BIT4 4530 drivers/tty/synclinkmp.c RegValue |= BIT4; BIT4 4576 drivers/tty/synclinkmp.c RegValue |= BIT4; BIT4 5089 drivers/tty/synclinkmp.c write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); BIT4 5192 drivers/tty/synclinkmp.c lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3); BIT4 5197 drivers/tty/synclinkmp.c lcr1_brdr_value |= BIT5 + BIT4 + BIT3; BIT4 5200 drivers/tty/synclinkmp.c lcr1_brdr_value |= BIT5 + BIT4; BIT4 61 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + BIT4 326 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); BIT4 347 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); BIT4 947 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); BIT4 1713 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); BIT4 1717 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); BIT4 1720 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); BIT4 1725 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); BIT4 1728 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); BIT4 2061 drivers/video/fbdev/via/hw.c BIT4); BIT4 844 drivers/video/fbdev/via/lcd.c bdual = BIT4; BIT4 848 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0); BIT4 1117 drivers/video/fbdev/via/viafbdev.c (viafb_read_reg(VIASR, SR2A) & BIT4) >> 3 | BIT4 1162 drivers/video/fbdev/via/viafbdev.c reg_val << 3, BIT4);