BIT31 3427 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c ret_bitmap = ratr_bitmap & (~(BIT31|BIT21)); BIT31 740 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR31 BIT31 BIT31 257 drivers/staging/emxx_udc/emxx_udc.h #define EPN_EN BIT31 BIT31 357 drivers/staging/emxx_udc/emxx_udc.h #define ARBITER_CTR BIT31 /* RW */ BIT31 20 drivers/staging/rtl8192e/rtl8192e/rtl_cam.c ulcommand |= BIT31|BIT30; BIT31 122 drivers/staging/rtl8192e/rtl8192e/rtl_cam.c TargetCommand |= BIT31|BIT16; BIT31 356 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c (pra->upper_rssi_threshold_ratr & (~BIT31)) | BIT31 357 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c ((bshort_gi_enabled) ? BIT31 : 0); BIT31 360 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c (pra->middle_rssi_threshold_ratr & (~BIT31)) | BIT31 361 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c ((bshort_gi_enabled) ? BIT31 : 0); BIT31 365 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | BIT31 366 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c ((bshort_gi_enabled) ? BIT31 : 0); BIT31 369 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | BIT31 370 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c ((bshort_gi_enabled) ? BIT31 : 0); BIT31 373 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c (pra->ping_rssi_ratr & (~BIT31)) | BIT31 374 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c ((bshort_gi_enabled) ? BIT31 : 0); BIT31 239 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c rt_global_debug_component &= BIT31; BIT31 1274 drivers/staging/rtl8192e/rtllib.h #define RF_CHANGE_BY_SW BIT31 BIT31 337 drivers/staging/rtl8723bs/core/rtw_efuse.c efuseValue |= (BIT21|BIT31); BIT31 385 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ BIT31 904 drivers/staging/rtl8723bs/hal/odm_DIG.c PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); BIT31 906 drivers/staging/rtl8723bs/hal/odm_DIG.c PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); BIT31 86 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_INIT BIT31 BIT31 853 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0); BIT31 754 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CAM_POLLINIG BIT31 BIT31 773 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BCNDMAINT6 BIT31 /* Beacon DMA Interrupt 6 */ BIT31 821 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_TIMEOUT2 BIT31 BIT31 872 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_TIMEOUT2 BIT31 BIT31 1020 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_APPFCS BIT31 /* WMAC append FCS after pauload */ BIT31 278 drivers/staging/rtl8723bs/include/hal_intf.h #define RF_CHANGE_BY_SW BIT31 BIT31 203 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */