BIT30 739 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR30 BIT30 BIT30 258 drivers/staging/emxx_udc/emxx_udc.h #define EPN_BUF_TYPE BIT30 BIT30 259 drivers/staging/emxx_udc/emxx_udc.h #define EPN_BUF_SINGLE BIT30 BIT30 20 drivers/staging/rtl8192e/rtl8192e/rtl_cam.c ulcommand |= BIT31|BIT30; BIT30 1275 drivers/staging/rtl8192e/rtllib.h #define RF_CHANGE_BY_HW BIT30 BIT30 386 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ BIT30 161 drivers/staging/rtl8723bs/hal/odm_DIG.c if (value32 & BIT30) BIT30 85 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_COMMON BIT30 BIT30 853 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0); BIT30 774 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BCNDMAINT5 BIT30 /* Beacon DMA Interrupt 5 */ BIT30 822 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_TIMEOUT1 BIT30 BIT30 873 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_TIMEOUT1 BIT30 BIT30 934 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */ BIT30 1021 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_APP_MIC BIT30 /* MACRX will retain the MIC at the bottom of the packet. */ BIT30 277 drivers/staging/rtl8723bs/include/hal_intf.h #define RF_CHANGE_BY_HW BIT30 BIT30 204 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ BIT30 5695 drivers/tty/synclink.c info->misc_ctrl_value |= BIT30; BIT30 5706 drivers/tty/synclink.c info->misc_ctrl_value &= ~BIT30; BIT30 5172 drivers/tty/synclinkmp.c info->misc_ctrl_value |= BIT30; BIT30 5183 drivers/tty/synclinkmp.c info->misc_ctrl_value &= ~BIT30;