BIT3 314 drivers/char/pcmcia/synclink_cs.c #define PVR_AUTOCTS BIT3 BIT3 682 drivers/char/pcmcia/synclink_cs.c #define CMD_TXFIFO BIT3 // release current tx FIFO BIT3 1192 drivers/char/pcmcia/synclink_cs.c if (gis & (BIT3 | BIT2)) BIT3 3085 drivers/char/pcmcia/synclink_cs.c val |= BIT3; BIT3 3094 drivers/char/pcmcia/synclink_cs.c val |= BIT4 | BIT3; BIT3 3225 drivers/char/pcmcia/synclink_cs.c set_reg_bits(info, CHA + PVR, BIT3); BIT3 3227 drivers/char/pcmcia/synclink_cs.c clear_reg_bits(info, CHA + PVR, BIT3); BIT3 3262 drivers/char/pcmcia/synclink_cs.c clear_reg_bits(info, CHA + MODE, BIT3); BIT3 3279 drivers/char/pcmcia/synclink_cs.c set_reg_bits(info, CHA + MODE, BIT3); BIT3 3495 drivers/char/pcmcia/synclink_cs.c val |= BIT3; BIT3 3539 drivers/char/pcmcia/synclink_cs.c set_reg_bits(info, CHA + MODE, BIT3); BIT3 3544 drivers/char/pcmcia/synclink_cs.c set_reg_bits(info, CHA + PVR, BIT3); BIT3 3546 drivers/char/pcmcia/synclink_cs.c clear_reg_bits(info, CHA + PVR, BIT3); BIT3 3561 drivers/char/pcmcia/synclink_cs.c set_reg_bits(info, CHA + CCR1, BIT3); BIT3 3563 drivers/char/pcmcia/synclink_cs.c clear_reg_bits(info, CHA + CCR1, BIT3); BIT3 3054 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c if ((coex_sta->bt_info_ext & BIT3)) { BIT3 11 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.h #define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3 BIT3 3180 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c if (coex_sta->bt_info_ext & BIT3) { BIT3 11 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.h #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3 BIT3 4060 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c if ((coex_sta->bt_info_ext & BIT3)) { BIT3 14 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.h #define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3 BIT3 2775 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c if ((coex_sta->bt_info_ext & BIT3) && !wifi_under_5g) { BIT3 12 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.h #define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3 BIT3 12 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.h #define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3 BIT3 95 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define ALGO_TRACE BIT3 BIT3 107 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define WIFI_P2P_GO_CONNECTED BIT3 BIT3 361 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_11M BIT3 BIT3 496 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define WOW_UWF BIT3 /* Unicast Wakeup frame. */ BIT3 35 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ BIT3 105 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \ BIT3 110 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ BIT3 176 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \ BIT3 202 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ BIT3 386 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \ BIT3 404 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \ BIT3 475 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \ BIT3 479 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \ BIT3 488 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \ BIT3 499 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \ BIT3 511 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \ BIT3 520 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \ BIT3 540 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \ BIT3 552 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \ BIT3 82 drivers/scsi/dc395x.h #define UNIT_RETRY BIT3 BIT3 132 drivers/scsi/dc395x.h #define UNDER_RUN BIT3 BIT3 177 drivers/scsi/dc395x.h #define WIDE_NEGO_DONE BIT3 BIT3 633 drivers/scsi/dc395x.h #define ACTIVE_NEGATION BIT3 BIT3 712 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR3 BIT3 BIT3 113 drivers/staging/rtl8192e/rtllib.h #define RT_RF_OFF_LEVL_HALT_NIC BIT3 BIT3 405 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */ BIT3 3610 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c if (pCoexSta->btInfoExt & BIT3) { BIT3 12 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.h #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3 BIT3 3431 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c if ((pCoexSta->btInfoExt & BIT3)) { BIT3 12 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.h #define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3 BIT3 96 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define ALGO_TRACE BIT3 BIT3 108 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define WIFI_P2P_GO_CONNECTED BIT3 BIT3 17 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ BIT3 104 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c if ((cond1 & BIT3) != 0) /* APA */ BIT3 17 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ BIT3 104 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c if ((cond1 & BIT3) != 0) /* APA */ BIT3 17 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ BIT3 110 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c if ((cond1 & BIT3) != 0) /* APA */ BIT3 1392 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3))); BIT3 425 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_FA_CNT = BIT3, BIT3 488 drivers/staging/rtl8723bs/hal/odm.h ODM_RF_TX_D = BIT3, BIT3 534 drivers/staging/rtl8723bs/hal/odm.h ODM_POWERSAVE = BIT3, BIT3 548 drivers/staging/rtl8723bs/hal/odm.h ODM_WM_N24G = BIT3, BIT3 38 drivers/staging/rtl8723bs/hal/odm_DynamicBBPowerSaving.c pDM_PSTable->RegC70 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xc70, bMaskDWord)&BIT3)>>3; BIT3 66 drivers/staging/rtl8723bs/hal/odm_DynamicBBPowerSaving.c PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, 0); /* RegC70[3]= 1'b0 */ BIT3 74 drivers/staging/rtl8723bs/hal/odm_DynamicBBPowerSaving.c PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, pDM_PSTable->RegC70); BIT3 64 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_FA_CNT BIT3 BIT3 2526 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ BIT3 2534 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ BIT3 2544 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ BIT3 2552 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ BIT3 2561 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ BIT3 2569 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ BIT3 227 drivers/staging/rtl8723bs/include/hal_com_phycfg.h #define LOAD_BB_MP_PARA_FILE BIT3 BIT3 611 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_11M BIT3 BIT3 636 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL92C_WOL_DEAUTH_EVENT BIT3 BIT3 762 drivers/staging/rtl8723bs/include/hal_com_reg.h #define WOW_UWF BIT3 /* Unicast Wakeup frame. */ BIT3 801 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BEDOK BIT3 /* AC_BE DMA OK Interrupt */ BIT3 849 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_VIDOK BIT3 /* AC_VI DMA OK Interrupt */ BIT3 900 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_VIDOK BIT3 /* AC_VI DMA OK Interrupt */ BIT3 954 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ BIT3 1012 drivers/staging/rtl8723bs/include/hal_com_reg.h #define StopBK BIT3 BIT3 1049 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_AB BIT3 /* Accept broadcast packet */ BIT3 1570 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_RXERR_MSK BIT3 BIT3 1596 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_RXERR BIT3 BIT3 1673 drivers/staging/rtl8723bs/include/hal_com_reg.h #define WL_HWROF_EN BIT3 /* Enable GPIO[9] as WiFi RF HW PDn source */ BIT3 1683 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 BIT3 1693 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PARTNO_SINGLE_BAND_VS BIT3 BIT3 1695 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2) BIT3 15 drivers/staging/rtl8723bs/include/hal_intf.h RTW_GSPI = BIT3, BIT3 48 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \ BIT3 54 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ BIT3 63 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\ BIT3 83 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ BIT3 84 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ BIT3 87 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ BIT3 94 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ BIT3 98 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ BIT3 104 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ BIT3 114 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ BIT3 118 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ BIT3 223 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */ BIT3 72 drivers/staging/rtl8723bs/include/rtw_ht.h #define LDPC_HT_CAP_TX BIT3 BIT3 77 drivers/staging/rtl8723bs/include/rtw_ht.h #define STBC_HT_CAP_TX BIT3 BIT3 47 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_BB_FA_CNT BIT3 /* ODM_BB_FA_CNT */ BIT3 492 drivers/tty/synclink.c #define TRANSMIT_STATUS BIT3 BIT3 509 drivers/tty/synclink.c #define RXSTATUS_CRC_ERROR BIT3 BIT3 510 drivers/tty/synclink.c #define RXSTATUS_FRAMING_ERROR BIT3 BIT3 549 drivers/tty/synclink.c #define TXSTATUS_CRC_SENT BIT3 BIT3 569 drivers/tty/synclink.c #define MISCSTATUS_RCC_UNDERRUN BIT3 BIT3 595 drivers/tty/synclink.c #define SICR_RCC_UNDERFLOW BIT3 BIT3 629 drivers/tty/synclink.c #define TXSTATUS_CRC_SENT BIT3 BIT3 1450 drivers/tty/synclink.c usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 )); BIT3 1608 drivers/tty/synclink.c if ( status & BIT3 ) { BIT3 4983 drivers/tty/synclink.c usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3)); BIT3 5370 drivers/tty/synclink.c usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 ); BIT3 5459 drivers/tty/synclink.c usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 ); BIT3 5565 drivers/tty/synclink.c usc_OutDmaReg( info, TDIAR, BIT2|BIT3 ); BIT3 5842 drivers/tty/synclink.c RegValue |= BIT4 | BIT3 | BIT2; BIT3 5899 drivers/tty/synclink.c RegValue |= BIT4 | BIT3 | BIT2; BIT3 6040 drivers/tty/synclink.c if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1)) BIT3 7238 drivers/tty/synclink.c if ( status & (BIT8 | BIT3 | BIT1) ) { BIT3 1979 drivers/tty/synclink_gt.c if (status & BIT3) { BIT3 2224 drivers/tty/synclink_gt.c if (status & (BIT5 + BIT4 + BIT3)) { BIT3 2706 drivers/tty/synclink_gt.c wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); BIT3 4136 drivers/tty/synclink_gt.c val |= BIT3; BIT3 4218 drivers/tty/synclink_gt.c val |= BIT3; BIT3 4393 drivers/tty/synclink_gt.c val |= BIT3; /* 010, rxclk = BRG */ BIT3 4506 drivers/tty/synclink_gt.c if (status & BIT3) BIT3 4548 drivers/tty/synclink_gt.c val |= BIT3; BIT3 4565 drivers/tty/synclink_gt.c val |= BIT3; BIT3 4567 drivers/tty/synclink_gt.c val &= ~BIT3; BIT3 425 drivers/tty/synclinkmp.c #define CCTS BIT3 BIT3 441 drivers/tty/synclinkmp.c #define OVRN BIT3 BIT3 1512 drivers/tty/synclinkmp.c RegValue |= BIT3; BIT3 1514 drivers/tty/synclinkmp.c RegValue &= ~BIT3; BIT3 2565 drivers/tty/synclinkmp.c if (status & BIT3 << shift) BIT3 2574 drivers/tty/synclinkmp.c if (dmastatus & BIT3 << shift) BIT3 4396 drivers/tty/synclinkmp.c case 6: RegValue |= BIT5 + BIT3; break; BIT3 4397 drivers/tty/synclinkmp.c case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; BIT3 4571 drivers/tty/synclinkmp.c RegValue |= BIT3; BIT3 4733 drivers/tty/synclinkmp.c if (!(status & BIT3)) BIT3 4908 drivers/tty/synclinkmp.c if (status & (BIT6+BIT5+BIT3+BIT2)) { BIT3 4916 drivers/tty/synclinkmp.c else if (status & BIT3) BIT3 5192 drivers/tty/synclinkmp.c lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3); BIT3 5197 drivers/tty/synclinkmp.c lcr1_brdr_value |= BIT5 + BIT4 + BIT3; BIT3 5203 drivers/tty/synclinkmp.c lcr1_brdr_value |= BIT5 + BIT3; BIT3 345 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT3 370 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT3 377 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT3 456 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CRD2, VIACR, 0, BIT3); BIT3 957 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3); BIT3 420 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3); BIT3 432 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3); BIT3 520 drivers/video/fbdev/via/lcd.c BIT0 + BIT1 + BIT2 + BIT3); BIT3 617 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR6A, VIACR, 0, BIT3); BIT3 665 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); BIT3 760 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); BIT3 761 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);