BIT28             737 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR28		BIT28
BIT28             289 drivers/staging/emxx_udc/emxx_udc.h #define EPN_OPID			BIT28		/* R */
BIT28            1277 drivers/staging/rtl8192e/rtllib.h #define RF_CHANGE_BY_IPS BIT28
BIT28             388 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define	IMR_GTINT4_8723B		BIT28	/*  When GTIMER4 expires, this bit is set to 1 */
BIT28             284 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c 			u8  cCond  = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             318 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c 				cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             321 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c 					cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             553 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c 			u8  cCond  = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             586 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c 				cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             589 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c 					cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             255 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c 			u8  cCond  = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             286 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c 				cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             289 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c 					cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             286 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c 			u8  cCond  = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             320 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c 				cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             323 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c 					cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
BIT28             104 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 			PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32);
BIT28             121 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 			PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00);
BIT28             527 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 		!(regEAC & BIT28) &&
BIT28             639 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 		!(regEAC & BIT28) &&
BIT28             852 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 		!(regEAC & BIT28) &&
BIT28             963 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 		!(regEAC & BIT28) &&
BIT28              70 drivers/staging/rtl8723bs/hal/odm_DynamicBBPowerSaving.c 			PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0); /* Reg818[28]= 1'b0 */
BIT28              71 drivers/staging/rtl8723bs/hal/odm_DynamicBBPowerSaving.c 			PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x1); /* Reg818[28]= 1'b1 */
BIT28              77 drivers/staging/rtl8723bs/hal/odm_DynamicBBPowerSaving.c 			PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0);
BIT28             776 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BCNDMAINT3			BIT28		/*  Beacon DMA Interrupt 3 */
BIT28             824 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_GTINT4				BIT28
BIT28             875 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_GTINT4				BIT28
BIT28             936 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_GTINT4_88E				BIT28		/*  When GTIMER4 expires, this bit is set to 1 */
BIT28            1023 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_APP_PHYST_RXFF		BIT28	/*  PHY Status is appended before RX packet in RXFF */
BIT28            1589 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_MCU_ERR_MSK			BIT28
BIT28            1615 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_MCU_ERR				BIT28
BIT28             275 drivers/staging/rtl8723bs/include/hal_intf.h #define RF_CHANGE_BY_IPS	BIT28
BIT28             206 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define	IMR_GTINT4_8723B					BIT28		/*  When GTIMER4 expires, this bit is set to 1 */