BIT27 736 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR27 BIT27 BIT27 290 drivers/staging/emxx_udc/emxx_udc.h #define EPN_OUT_NOTKN BIT27 /* R */ BIT27 389 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ BIT27 411 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */ BIT27 744 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ BIT27 1068 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ BIT27 869 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); BIT27 777 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BCNDMAINT2 BIT27 /* Beacon DMA Interrupt 2 */ BIT27 825 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_GTINT3 BIT27 BIT27 876 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_GTINT3 BIT27 BIT27 937 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ BIT27 960 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ BIT27 1024 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_APP_BA_SSN BIT27 /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ BIT27 1586 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_CTWEND_MSK BIT27 BIT27 1612 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_CTWEND BIT27 BIT27 207 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ BIT27 229 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */