BIT2 301 drivers/char/pcmcia/synclink_cs.c #define IRQ_DCD BIT2 // carrier detect status change BIT2 308 drivers/char/pcmcia/synclink_cs.c #define CEC BIT2 // command executing BIT2 313 drivers/char/pcmcia/synclink_cs.c #define PVR_RI BIT2 BIT2 690 drivers/char/pcmcia/synclink_cs.c while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) { BIT2 1192 drivers/char/pcmcia/synclink_cs.c if (gis & (BIT3 | BIT2)) BIT2 1239 drivers/char/pcmcia/synclink_cs.c if (pis & BIT2) BIT2 2925 drivers/char/pcmcia/synclink_cs.c val |= BIT2; BIT2 2997 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0); BIT2 3068 drivers/char/pcmcia/synclink_cs.c val |= BIT2; BIT2 3091 drivers/char/pcmcia/synclink_cs.c val |= BIT4 | BIT2; BIT2 3151 drivers/char/pcmcia/synclink_cs.c val |= BIT2 | BIT1; BIT2 3493 drivers/char/pcmcia/synclink_cs.c val |= BIT2; /* Parity enable */ BIT2 3602 drivers/char/pcmcia/synclink_cs.c val |= BIT2; BIT2 3604 drivers/char/pcmcia/synclink_cs.c val &= ~BIT2; BIT2 12 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.h #define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2 BIT2 12 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.h #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2 BIT2 15 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.h #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2 BIT2 13 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.h #define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2 BIT2 13 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.h #define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2 BIT2 89 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define INTF_NOTIFY BIT2 BIT2 94 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define ALGO_BT_MONITOR BIT2 BIT2 106 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define WIFI_HS_CONNECTED BIT2 BIT2 360 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_5_5M BIT2 BIT2 495 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define WOW_MAGIC BIT2 /* Magic packet */ BIT2 26 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \ BIT2 130 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \ BIT2 199 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \ BIT2 205 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \ BIT2 386 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \ BIT2 523 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \ BIT2 81 drivers/scsi/dc395x.h #define FORMATING_MEDIA BIT2 BIT2 87 drivers/scsi/dc395x.h #define ASPI_SUPPORT BIT2 BIT2 123 drivers/scsi/dc395x.h #define RESET_DONE BIT2 BIT2 131 drivers/scsi/dc395x.h #define OVER_RUN BIT2 BIT2 141 drivers/scsi/dc395x.h #define RESET_DEV0 BIT2 BIT2 176 drivers/scsi/dc395x.h #define WIDE_NEGO_ENABLE BIT2 BIT2 632 drivers/scsi/dc395x.h #define RST_SCSI_BUS BIT2 BIT2 711 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR2 BIT2 BIT2 406 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */ BIT2 13 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.h #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2 BIT2 13 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.h #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2 BIT2 90 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define INTF_NOTIFY BIT2 BIT2 95 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define ALGO_BT_MONITOR BIT2 BIT2 107 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define WIFI_HS_CONNECTED BIT2 BIT2 20 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ BIT2 102 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c if ((cond1 & BIT2) != 0) /* ALNA */ BIT2 20 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ BIT2 102 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c if ((cond1 & BIT2) != 0) /* ALNA */ BIT2 20 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ BIT2 108 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c if ((cond1 & BIT2) != 0) /* ALNA */ BIT2 424 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_DYNAMIC_TXPWR = BIT2, BIT2 487 drivers/staging/rtl8723bs/hal/odm.h ODM_RF_TX_C = BIT2, BIT2 533 drivers/staging/rtl8723bs/hal/odm.h ODM_SCAN = BIT2, BIT2 547 drivers/staging/rtl8723bs/hal/odm.h ODM_WM_A = BIT2, BIT2 63 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_DYNAMIC_TXPWR BIT2 BIT2 330 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c while (u1bTmp & BIT2) { BIT2 343 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2)); BIT2 633 drivers/staging/rtl8723bs/include/drv_types.h #define DF_IO_BIT BIT2 BIT2 226 drivers/staging/rtl8723bs/include/hal_com_phycfg.h #define LOAD_BB_PG_PARA_FILE BIT2 BIT2 610 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_5_5M BIT2 BIT2 635 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL92C_WOL_DISASSOC_EVENT BIT2 BIT2 727 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BW_OPMODE_20MHZ BIT2 BIT2 761 drivers/staging/rtl8723bs/include/hal_com_reg.h #define WOW_MAGIC BIT2 /* Magic packet */ BIT2 802 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_VIDOK BIT2 /* AC_VI DMA OK Interrupt */ BIT2 850 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */ BIT2 901 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */ BIT2 955 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */ BIT2 1013 drivers/staging/rtl8723bs/include/hal_com_reg.h #define StopBE BIT2 BIT2 1050 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_AM BIT2 /* Accept multicast packet */ BIT2 1569 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_TXERR_MSK BIT2 BIT2 1595 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_TXERR BIT2 BIT2 1672 drivers/staging/rtl8723bs/include/hal_com_reg.h #define WL_FUNC_EN BIT2 /* WiFi function enable */ BIT2 1684 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 BIT2 1695 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2) BIT2 1713 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL_8192C_HW_GPIO_WPS_BIT BIT2 BIT2 14 drivers/staging/rtl8723bs/include/hal_intf.h RTW_SDIO = BIT2, BIT2 48 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \ BIT2 105 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ BIT2 183 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \ BIT2 208 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \ BIT2 210 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \ BIT2 224 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */ BIT2 71 drivers/staging/rtl8723bs/include/rtw_ht.h #define LDPC_HT_TEST_TX_ENABLE BIT2 BIT2 76 drivers/staging/rtl8723bs/include/rtw_ht.h #define STBC_HT_TEST_TX_ENABLE BIT2 BIT2 81 drivers/staging/rtl8723bs/include/rtw_ht.h #define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target supports it or not */ BIT2 328 drivers/staging/rtl8723bs/include/rtw_mlme.h RTW_ROAM_ACTIVE = BIT2, BIT2 46 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_DYNAMIC_TXPWR BIT2 /* ODM_BB_DYNAMIC_TXPWR */ BIT2 215 drivers/staging/rtl8723bs/os_dep/os_intfs.c static int rtw_load_phy_file = (BIT2 | BIT6); BIT2 493 drivers/tty/synclink.c #define TRANSMIT_DATA BIT2 BIT2 511 drivers/tty/synclink.c #define RXSTATUS_ABORT BIT2 BIT2 512 drivers/tty/synclink.c #define RXSTATUS_PARITY_ERROR BIT2 BIT2 550 drivers/tty/synclink.c #define TXSTATUS_ALL_SENT BIT2 BIT2 570 drivers/tty/synclink.c #define MISCSTATUS_DPLL_NO_SYNC BIT2 BIT2 596 drivers/tty/synclink.c #define SICR_DPLL_NO_SYNC BIT2 BIT2 630 drivers/tty/synclink.c #define TXSTATUS_ALL_SENT BIT2 BIT2 1651 drivers/tty/synclink.c if ( status & BIT2 ) { BIT2 5370 drivers/tty/synclink.c usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 ); BIT2 5459 drivers/tty/synclink.c usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 ); BIT2 5565 drivers/tty/synclink.c usc_OutDmaReg( info, TDIAR, BIT2|BIT3 ); BIT2 5842 drivers/tty/synclink.c RegValue |= BIT4 | BIT3 | BIT2; BIT2 5899 drivers/tty/synclink.c RegValue |= BIT4 | BIT3 | BIT2; BIT2 7197 drivers/tty/synclink.c while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) { BIT2 219 drivers/tty/synclink_gt.c #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) BIT2 1999 drivers/tty/synclink_gt.c if (status & BIT2) { BIT2 2269 drivers/tty/synclink_gt.c wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ BIT2 3895 drivers/tty/synclink_gt.c wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); BIT2 3944 drivers/tty/synclink_gt.c wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ BIT2 3969 drivers/tty/synclink_gt.c wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ BIT2 3991 drivers/tty/synclink_gt.c wr_reg32(info, RDCSR, (BIT2 + BIT0)); BIT2 3994 drivers/tty/synclink_gt.c wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); BIT2 4011 drivers/tty/synclink_gt.c (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); BIT2 4040 drivers/tty/synclink_gt.c wr_reg32(info, TDCSR, BIT2 + BIT0); BIT2 4055 drivers/tty/synclink_gt.c wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ BIT2 4260 drivers/tty/synclink_gt.c val = BIT2; BIT2 4397 drivers/tty/synclink_gt.c val |= BIT2; /* 001, rxclk = TXC Input */ BIT2 4508 drivers/tty/synclink_gt.c if (status & BIT2) BIT2 4550 drivers/tty/synclink_gt.c val |= BIT2; BIT2 4569 drivers/tty/synclink_gt.c val |= BIT2; BIT2 4571 drivers/tty/synclink_gt.c val &= ~BIT2; BIT2 426 drivers/tty/synclinkmp.c #define CDCD BIT2 BIT2 442 drivers/tty/synclinkmp.c #define CRCE BIT2 BIT2 2563 drivers/tty/synclinkmp.c if (status & BIT2 << shift) BIT2 2572 drivers/tty/synclinkmp.c if (dmastatus & BIT2 << shift) BIT2 4395 drivers/tty/synclinkmp.c case 7: RegValue |= BIT4 + BIT2; break; BIT2 4397 drivers/tty/synclinkmp.c case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; BIT2 4532 drivers/tty/synclinkmp.c RegValue |= BIT2 + BIT1; BIT2 4736 drivers/tty/synclinkmp.c if ( !(status & BIT2)) BIT2 4894 drivers/tty/synclinkmp.c status &= ~BIT2; BIT2 4908 drivers/tty/synclinkmp.c if (status & (BIT6+BIT5+BIT3+BIT2)) { BIT2 335 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2); BIT2 338 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2); BIT2 345 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT2 370 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT2 377 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT2 949 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); BIT2 2058 drivers/video/fbdev/via/hw.c p_gfx_dpa_setting->DVP0ClockDri_S, BIT2); BIT2 345 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); BIT2 520 drivers/video/fbdev/via/lcd.c BIT0 + BIT1 + BIT2 + BIT3); BIT2 563 drivers/video/fbdev/via/lcd.c BIT0 + BIT1 + BIT2); BIT2 746 drivers/video/fbdev/via/lcd.c BIT7 + BIT2 + BIT1 + BIT0); BIT2 1118 drivers/video/fbdev/via/viafbdev.c (viafb_read_reg(VIASR, SR1E) & BIT2) >> 2; BIT2 1164 drivers/video/fbdev/via/viafbdev.c reg_val << 2, BIT2);