BIT17             375 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define	RRSR_MCS5			BIT17
BIT17             726 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR17		BIT17
BIT17             143 drivers/staging/emxx_udc/emxx_udc.h #define EP9_INT				BIT17
BIT17             170 drivers/staging/emxx_udc/emxx_udc.h #define EP9_EN				BIT17
BIT17             192 drivers/staging/emxx_udc/emxx_udc.h #define EP0_OVERSEL			BIT17
BIT17             211 drivers/staging/emxx_udc/emxx_udc.h #define EP0_PERR_NAK			BIT17
BIT17             267 drivers/staging/emxx_udc/emxx_udc.h #define EPN_OVERSEL			BIT17
BIT17             300 drivers/staging/emxx_udc/emxx_udc.h #define EPN_OUT_FULL			BIT17		/* R */
BIT17             421 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define	IMR_BCNDOK4_8723B		BIT17	/*  Beacon Queue DMA OK Interrup 4 */
BIT17            1725 drivers/staging/rtl8723bs/hal/hal_com.c 			PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target);
BIT17            1397 drivers/staging/rtl8723bs/hal/odm.c 		PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03);
BIT17             440 drivers/staging/rtl8723bs/hal/odm.h 	ODM_MAC_EARLY_MODE		= BIT17,
BIT17              79 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_EARLY_MODE			BIT17
BIT17             625 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_MCS5				BIT17
BIT17             787 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_TIMEOUT2			BIT17		/*  Timeout interrupt 2 */
BIT17             835 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_BCNDOK1				BIT17
BIT17             861 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_BCNDOK5				BIT17
BIT17             886 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_BCNDOK1				BIT17
BIT17             912 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_BCNDOK5				BIT17
BIT17             970 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BCNDOK4_88E			BIT17		/*  Beacon Queue DMA OK Interrup 4 */
BIT17            1034 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_BM_DATA_EN			BIT17	/*  Broadcast data packet interrupt enable. */
BIT17            1576 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_C2HCMD_MSK			BIT17
BIT17            1602 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_C2HCMD				BIT17
BIT17            1675 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BT_HWPDN_SL			BIT17	/*  BT HW PDn polarity control */
BIT17             239 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define	IMR_BCNDOK4_8723B					BIT17		/*  Beacon Queue DMA OK Interrupt 4 */
BIT17              62 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_MAC_EARLY_MODE		BIT17/* ODM_MAC_EARLY_MODE */
BIT17            2353 drivers/tty/synclink_gt.c 			if (gsr & (BIT17 << (i*2)))