BIT16             374 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define	RRSR_MCS4			BIT16
BIT16            2428 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define	ODM_BIT_CCK_RPT_FORMAT_11AC	BIT16
BIT16             725 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR16		BIT16
BIT16              89 drivers/staging/emxx_udc/emxx_udc.h #define TEST_FORCE_ENABLE		(BIT18 + BIT16)
BIT16             144 drivers/staging/emxx_udc/emxx_udc.h #define EP8_INT				BIT16
BIT16             171 drivers/staging/emxx_udc/emxx_udc.h #define EP8_EN				BIT16
BIT16             193 drivers/staging/emxx_udc/emxx_udc.h #define EP0_AUTO			BIT16
BIT16             212 drivers/staging/emxx_udc/emxx_udc.h #define EP0_PERR_NAK_INT		BIT16
BIT16             230 drivers/staging/emxx_udc/emxx_udc.h #define EP0_STATUS_RW_BIT	(BIT16 | BIT15 | BIT11 | 0xFF)
BIT16             233 drivers/staging/emxx_udc/emxx_udc.h #define EP0_PERR_NAK_EN			BIT16
BIT16             268 drivers/staging/emxx_udc/emxx_udc.h #define EPN_AUTO			BIT16
BIT16             301 drivers/staging/emxx_udc/emxx_udc.h #define EPN_OUT_EMPTY			BIT16		/* R */
BIT16             122 drivers/staging/rtl8192e/rtl8192e/rtl_cam.c 		TargetCommand |= BIT31|BIT16;
BIT16             394 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define	IMR_BCNDERR0_8723B		BIT16	/*  Beacon Queue DMA OK0 */
BIT16             422 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define	IMR_BCNDOK3_8723B		BIT16	/*  Beacon Queue DMA OK Interrup 3 */
BIT16            1725 drivers/staging/rtl8723bs/hal/hal_com.c 			PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target);
BIT16            1397 drivers/staging/rtl8723bs/hal/odm.c 		PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03);
BIT16             439 drivers/staging/rtl8723bs/hal/odm.h 	ODM_MAC_EDCA_TURBO		= BIT16,
BIT16              78 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_EDCA_TURBO			BIT16
BIT16             624 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_MCS4				BIT16
BIT16             752 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CAM_WRITE				BIT16
BIT16             788 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_TIMEOUT1			BIT16		/*  Timeout interrupt 1 */
BIT16             836 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_BCNDOK0				BIT16
BIT16             862 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_BCNDOK4				BIT16
BIT16             887 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_BCNDOK0				BIT16
BIT16             913 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_BCNDOK4				BIT16
BIT16             942 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BCNDERR0_88E			BIT16		/*  Beacon Queue DMA Error 0 */
BIT16             971 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BCNDOK3_88E			BIT16		/*  Beacon Queue DMA OK Interrup 3 */
BIT16            1035 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_UC_DATA_EN			BIT16	/*  Unicast data packet interrupt enable. */
BIT16            1575 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_BCNERLY_INT_MSK		BIT16
BIT16            1601 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_BCNERLY_INT			BIT16
BIT16            1674 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BT_HWPDN_EN			BIT16	/*  Enable GPIO[11] as BT HW PDn source */
BIT16             212 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define	IMR_BCNDERR0_8723B				BIT16		/*  Beacon Queue DMA OK0 */
BIT16             240 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define	IMR_BCNDOK3_8723B					BIT16		/*  Beacon Queue DMA OK Interrupt 3 */
BIT16              61 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_MAC_EDCA_TURBO		BIT16/* ODM_MAC_EDCA_TURBO */
BIT16            2351 drivers/tty/synclink_gt.c 			if (gsr & (BIT16 << (i*2)))