BIT15             290 drivers/char/pcmcia/synclink_cs.c #define IRQ_BREAK_ON    BIT15   // rx break detected
BIT15             373 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define	RRSR_MCS3			BIT15
BIT15             724 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR15		BIT15
BIT15             116 drivers/staging/emxx_udc/emxx_udc.h #define SOF_STATUS			BIT15
BIT15             145 drivers/staging/emxx_udc/emxx_udc.h #define EP7_INT				BIT15
BIT15             172 drivers/staging/emxx_udc/emxx_udc.h #define EP7_EN				BIT15
BIT15             213 drivers/staging/emxx_udc/emxx_udc.h #define EP0_OUT_NAK_INT			BIT15
BIT15             230 drivers/staging/emxx_udc/emxx_udc.h #define EP0_STATUS_RW_BIT	(BIT16 | BIT15 | BIT11 | 0xFF)
BIT15             234 drivers/staging/emxx_udc/emxx_udc.h #define EP0_OUT_NAK_EN			BIT15
BIT15             115 drivers/staging/rtl8192e/rtl8192e/rtl_cam.c 		usConfig |= BIT15 | (KeyType<<2);
BIT15             117 drivers/staging/rtl8192e/rtl8192e/rtl_cam.c 		usConfig |= BIT15 | (KeyType<<2) | KeyIndex;
BIT15             395 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define	IMR_HSISR_IND_ON_INT_8723B	BIT15	/*  HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
BIT15             423 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define	IMR_BCNDOK2_8723B		BIT15	/*  Beacon Queue DMA OK Interrup 2 */
BIT15            1725 drivers/staging/rtl8723bs/hal/hal_com.c 			PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target);
BIT15              76 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_CFO_TRACKING		BIT15
BIT15             623 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_MCS3				BIT15
BIT15             733 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CAM_VALID				BIT15
BIT15             789 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_TXFOVW				BIT15		/*  Transmit FIFO Overflow */
BIT15             807 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_TSF_BIT32_TOGGLE	BIT15
BIT15             837 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_HSISR_IND_ON			BIT15
BIT15             888 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_HSISR_IND			BIT15
BIT15             943 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_HSISR_IND_ON_INT_88E	BIT15		/*  HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
BIT15             972 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BCNDOK2_88E			BIT15		/*  Beacon Queue DMA OK Interrup 2 */
BIT15            1036 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_RSVD_BIT15			BIT15	/*  Reserved */
BIT15             213 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define	IMR_HSISR_IND_ON_INT_8723B		BIT15		/*  HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
BIT15             241 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define	IMR_BCNDOK2_8723B					BIT15		/*  Beacon Queue DMA OK Interrupt 2 */
BIT15             557 drivers/tty/synclink.c #define MISCSTATUS_RXC_LATCHED		BIT15
BIT15             577 drivers/tty/synclink.c #define SICR_RXC_ACTIVE			BIT15
BIT15             579 drivers/tty/synclink.c #define SICR_RXC			(BIT15|BIT14)
BIT15             634 drivers/tty/synclink.c #define DICR_MASTER		BIT15
BIT15            1839 drivers/tty/synclink.c 	usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
BIT15            4643 drivers/tty/synclink.c 			RegValue |= BIT15;
BIT15            4645 drivers/tty/synclink.c 			RegValue |= BIT15 | BIT14;
BIT15            4687 drivers/tty/synclink.c 	case HDLC_ENCODING_BIPHASE_MARK:       RegValue |= BIT15; break;
BIT15            4688 drivers/tty/synclink.c 	case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 | BIT13; break;
BIT15            4689 drivers/tty/synclink.c 	case HDLC_ENCODING_BIPHASE_LEVEL:      RegValue |= BIT15 | BIT14; break;
BIT15            4690 drivers/tty/synclink.c 	case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
BIT15            4762 drivers/tty/synclink.c 	case HDLC_ENCODING_BIPHASE_MARK:       RegValue |= BIT15; break;
BIT15            4763 drivers/tty/synclink.c 	case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 | BIT13; break;
BIT15            4764 drivers/tty/synclink.c 	case HDLC_ENCODING_BIPHASE_LEVEL:      RegValue |= BIT15 | BIT14; break;
BIT15            4765 drivers/tty/synclink.c 	case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
BIT15             218 drivers/tty/synclink_gt.c #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
BIT15            2111 drivers/tty/synclink_gt.c 			set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
BIT15            4212 drivers/tty/synclink_gt.c 	val = BIT15 + BIT14 + BIT0;
BIT15            4264 drivers/tty/synclink_gt.c 		val |= BIT15 + BIT13;
BIT15            4267 drivers/tty/synclink_gt.c 	case MGSL_MODE_BISYNC:   val |= BIT15; break;
BIT15            4339 drivers/tty/synclink_gt.c 		val |= BIT15 + BIT13;
BIT15            4342 drivers/tty/synclink_gt.c 	case MGSL_MODE_BISYNC:   val |= BIT15; break;
BIT15            4448 drivers/tty/synclink_gt.c 	wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);