BIT12             293 drivers/char/pcmcia/synclink_cs.c #define IRQ_UNDERRUN    BIT12	// transmit data underrun
BIT12             370 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define	RRSR_MCS0			BIT12
BIT12             721 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR12		BIT12
BIT12             117 drivers/staging/emxx_udc/emxx_udc.h #define UFRAME				(BIT14 + BIT13 + BIT12)
BIT12             148 drivers/staging/emxx_udc/emxx_udc.h #define EP4_INT				BIT12
BIT12             175 drivers/staging/emxx_udc/emxx_udc.h #define EP4_EN				BIT12
BIT12             216 drivers/staging/emxx_udc/emxx_udc.h #define EP0_OUT_EMPTY			BIT12
BIT12             358 drivers/staging/emxx_udc/emxx_udc.h #define MCYCLE_RST			BIT12		/* RW */
BIT12             394 drivers/staging/emxx_udc/emxx_udc.h #define DIRPD				BIT12		/* RW */
BIT12             397 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define	IMR_ATIMEND_8723B		BIT12	/*  CTWidnow End or ATIM Window End */
BIT12             434 drivers/staging/rtl8723bs/hal/odm.h 	ODM_BB_RXHP			= BIT12,
BIT12             941 drivers/staging/rtl8723bs/hal/odm_DIG.c 		PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
BIT12              73 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_DYNAMIC_PRICCA		BIT12
BIT12             620 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_MCS0				BIT12
BIT12             792 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_RXFOVW				BIT12		/*  Receive FIFO Overflow */
BIT12             808 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_BcnInt_E				BIT12
BIT12             840 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_ATIM_CTW_END		BIT12
BIT12             891 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_CTW_END				BIT12
BIT12             916 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_ATIMEND				BIT12
BIT12             945 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_ATIMEND_88E			BIT12		/*  CTWidnow End or ATIM Window End */
BIT12            1039 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_ACF					BIT12	/*  Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */
BIT12             215 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define	IMR_ATIMEND_8723B				BIT12		/*  CTWidnow End or ATIM Window End */
BIT12              56 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_RXHP				BIT12/* ODM_BB_RXHP */
BIT12             560 drivers/tty/synclink.c #define MISCSTATUS_TXC			BIT12
BIT12             581 drivers/tty/synclink.c #define SICR_TXC_INACTIVE		BIT12
BIT12             582 drivers/tty/synclink.c #define SICR_TXC			(BIT13|BIT12)
BIT12            1844 drivers/tty/synclink.c 	usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
BIT12            4620 drivers/tty/synclink.c 				(unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
BIT12            4654 drivers/tty/synclink.c 		RegValue |= BIT12;
BIT12            4696 drivers/tty/synclink.c 		RegValue |= ( BIT12 | BIT10 | BIT9 );
BIT12            4771 drivers/tty/synclink.c 		RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
BIT12            5096 drivers/tty/synclink.c 	case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break;
BIT12            6942 drivers/tty/synclink.c 	usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
BIT12             413 drivers/tty/synclink_gt.c #define IRQ_TXIDLE  BIT12
BIT12            4278 drivers/tty/synclink_gt.c 	case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
BIT12            4279 drivers/tty/synclink_gt.c 	case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
BIT12            4280 drivers/tty/synclink_gt.c 	case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
BIT12            4281 drivers/tty/synclink_gt.c 	case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
BIT12            4351 drivers/tty/synclink_gt.c 	case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
BIT12            4352 drivers/tty/synclink_gt.c 	case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
BIT12            4353 drivers/tty/synclink_gt.c 	case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
BIT12            4354 drivers/tty/synclink_gt.c 	case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;