BIT11 294 drivers/char/pcmcia/synclink_cs.c #define IRQ_TIMER BIT11 // timer interrupt BIT11 369 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_54M BIT11 BIT11 720 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR11 BIT11 BIT11 149 drivers/staging/emxx_udc/emxx_udc.h #define EP3_INT BIT11 BIT11 176 drivers/staging/emxx_udc/emxx_udc.h #define EP3_EN BIT11 BIT11 217 drivers/staging/emxx_udc/emxx_udc.h #define EP0_IN_NAK_INT BIT11 BIT11 230 drivers/staging/emxx_udc/emxx_udc.h #define EP0_STATUS_RW_BIT (BIT16 | BIT15 | BIT11 | 0xFF) BIT11 236 drivers/staging/emxx_udc/emxx_udc.h #define EP0_IN_NAK_EN BIT11 BIT11 270 drivers/staging/emxx_udc/emxx_udc.h #define EPN_IPIDCLR BIT11 BIT11 333 drivers/staging/emxx_udc/emxx_udc.h #define EPN_STOP_MODE BIT11 BIT11 281 drivers/staging/rtl8723bs/core/rtw_efuse.c rtw_write16(padapter, 0x34, rtw_read16(padapter, 0x34) & (~BIT11)); BIT11 347 drivers/staging/rtl8723bs/core/rtw_efuse.c rtw_write16(padapter, 0x34, rtw_read16(padapter, 0x34) | (BIT11)); BIT11 426 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ BIT11 433 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_PSD = BIT11, BIT11 230 drivers/staging/rtl8723bs/hal/odm_DIG.c PHY_SetBBReg(pDM_Odm->Adapter, REG_RD_CTRL, BIT11, 1); /* stop counting if EDCCA is asserted */ BIT11 162 drivers/staging/rtl8723bs/hal/odm_RegDefine11N.h #define ODM_BIT_BB_ATC_11N BIT11 BIT11 72 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_PSD BIT11 BIT11 65 drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11); BIT11 619 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_54M BIT11 BIT11 793 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_RDU BIT11 /* Receive Descriptor Unavailable */ BIT11 809 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_TXERR BIT11 BIT11 841 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_HISRE_IND BIT11 /* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */ BIT11 864 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_TXERR BIT11 BIT11 917 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_TXERR BIT11 BIT11 946 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ BIT11 975 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_TXERR_88E BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ BIT11 1040 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_ADF BIT11 /* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */ BIT11 244 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ BIT11 55 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_PSD BIT11/* ODM_BB_PSD */ BIT11 543 drivers/tty/synclink.c #define TCSR_UNDERWAIT BIT11 BIT11 561 drivers/tty/synclink.c #define MISCSTATUS_RI_LATCHED BIT11 BIT11 583 drivers/tty/synclink.c #define SICR_RI_ACTIVE BIT11 BIT11 585 drivers/tty/synclink.c #define SICR_RI (BIT11|BIT10) BIT11 4899 drivers/tty/synclink.c RegValue |= BIT11; BIT11 5091 drivers/tty/synclink.c case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break; BIT11 5092 drivers/tty/synclink.c case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; BIT11 414 drivers/tty/synclink_gt.c #define IRQ_TXUNDER BIT11 /* HDLC */ BIT11 4276 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; BIT11 4277 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; BIT11 4280 drivers/tty/synclink_gt.c case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; BIT11 4281 drivers/tty/synclink_gt.c case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; BIT11 4349 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; BIT11 4350 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; BIT11 4353 drivers/tty/synclink_gt.c case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; BIT11 4354 drivers/tty/synclink_gt.c case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;