BIT10 295 drivers/char/pcmcia/synclink_cs.c #define IRQ_CTS BIT10 // CTS status change BIT10 368 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_48M BIT10 BIT10 719 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR10 BIT10 BIT10 91 drivers/staging/emxx_udc/emxx_udc.h #define INT_SEL BIT10 BIT10 150 drivers/staging/emxx_udc/emxx_udc.h #define EP2_INT BIT10 BIT10 177 drivers/staging/emxx_udc/emxx_udc.h #define EP2_EN BIT10 BIT10 218 drivers/staging/emxx_udc/emxx_udc.h #define EP0_IN_DATA BIT10 BIT10 271 drivers/staging/emxx_udc/emxx_udc.h #define EPN_OPIDCLR BIT10 BIT10 303 drivers/staging/emxx_udc/emxx_udc.h #define EPN_IPID BIT10 /* R */ BIT10 334 drivers/staging/emxx_udc/emxx_udc.h #define EPN_DEND_SET BIT10 BIT10 398 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ BIT10 427 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ BIT10 432 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_PATH_DIV = BIT10, BIT10 24 drivers/staging/rtl8723bs/hal/odm_DIG.c PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 enable CCX */ BIT10 71 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_PATH_DIV BIT10 BIT10 65 drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11); BIT10 71 drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10); BIT10 618 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_48M BIT10 BIT10 794 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_ATIMEND BIT10 /* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */ BIT10 810 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_RXERR BIT10 BIT10 842 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_C2HCMD BIT10 BIT10 865 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_RXERR BIT10 BIT10 893 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_C2HCMD BIT10 BIT10 918 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_RXERR BIT10 BIT10 947 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ BIT10 976 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_RXERR_88E BIT10 /* Rx Error Flag INT Status, Write 1 clear */ BIT10 1041 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_RSVD_BIT10 BIT10 /* Reserved */ BIT10 216 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ BIT10 245 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ BIT10 54 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_PATH_DIV BIT10/* ODM_BB_PATH_DIV */ BIT10 562 drivers/tty/synclink.c #define MISCSTATUS_RI BIT10 BIT10 584 drivers/tty/synclink.c #define SICR_RI_INACTIVE BIT10 BIT10 585 drivers/tty/synclink.c #define SICR_RI (BIT11|BIT10) BIT10 1705 drivers/tty/synclink.c else if ( (DmaVector&(BIT10|BIT9)) == BIT10) BIT10 4696 drivers/tty/synclink.c RegValue |= ( BIT12 | BIT10 | BIT9 ); BIT10 4771 drivers/tty/synclink.c RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); BIT10 4895 drivers/tty/synclink.c RegValue |= BIT10; BIT10 5090 drivers/tty/synclink.c case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break; BIT10 5092 drivers/tty/synclink.c case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; BIT10 415 drivers/tty/synclink_gt.c #define IRQ_RXDATA BIT10 BIT10 2108 drivers/tty/synclink_gt.c if (count == info->rbuf_fill_level || (reg & BIT10)) { BIT10 4275 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZB: val |= BIT10; break; BIT10 4277 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; BIT10 4279 drivers/tty/synclink_gt.c case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; BIT10 4281 drivers/tty/synclink_gt.c case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; BIT10 4348 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZB: val |= BIT10; break; BIT10 4350 drivers/tty/synclink_gt.c case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; BIT10 4352 drivers/tty/synclink_gt.c case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; BIT10 4354 drivers/tty/synclink_gt.c case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;