BIT1 302 drivers/char/pcmcia/synclink_cs.c #define IRQ_OVERRUN BIT1 // receive frame overflow BIT1 309 drivers/char/pcmcia/synclink_cs.c #define CTS BIT1 // CTS state BIT1 312 drivers/char/pcmcia/synclink_cs.c #define PVR_DSR BIT1 BIT1 683 drivers/char/pcmcia/synclink_cs.c #define CMD_TXEOM BIT1 // transmit end message BIT1 1185 drivers/char/pcmcia/synclink_cs.c if (gis & (BIT1 | BIT0)) { BIT1 1237 drivers/char/pcmcia/synclink_cs.c if (pis & BIT1) BIT1 2997 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0); BIT1 3132 drivers/char/pcmcia/synclink_cs.c val |= BIT1; BIT1 3151 drivers/char/pcmcia/synclink_cs.c val |= BIT2 | BIT1; BIT1 3577 drivers/char/pcmcia/synclink_cs.c if (read_reg(info, CHB + STAR) & BIT1) BIT1 3039 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c if ((coex_sta->bt_info_ext & BIT1)) { BIT1 13 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.h #define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1 BIT1 2382 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1); BIT1 3167 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c if (coex_sta->bt_info_ext & BIT1) { BIT1 13 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.h #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1 BIT1 3571 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1); BIT1 4045 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c if ((coex_sta->bt_info_ext & BIT1)) { BIT1 16 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.h #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1 BIT1 2761 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c if (coex_sta->bt_info_ext & BIT1) { BIT1 14 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.h #define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1 BIT1 4028 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.c if ((coex_sta->bt_info_ext & BIT1)) { BIT1 14 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.h #define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1 BIT1 93 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define ALGO_WIFI_RSSI_STATE BIT1 BIT1 105 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define WIFI_AP_CONNECTED BIT1 BIT1 359 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_2M BIT1 BIT1 494 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define WOW_WOMEN BIT1 /* WoW function on or off. */ BIT1 29 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \ BIT1 57 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ BIT1 66 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ BIT1 69 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \ BIT1 170 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ BIT1 173 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ BIT1 253 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ BIT1 259 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ BIT1 288 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ BIT1 294 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \ BIT1 392 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \ BIT1 423 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ BIT1 426 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ BIT1 429 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ BIT1 435 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ BIT1 456 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ BIT1 459 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ BIT1 462 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \ BIT1 494 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \ BIT1 505 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \ BIT1 535 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \ BIT1 546 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \ BIT1 607 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ BIT1 613 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ BIT1 645 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ BIT1 651 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \ BIT1 80 drivers/scsi/dc395x.h #define UNIT_INFO_CHANGED BIT1 BIT1 86 drivers/scsi/dc395x.h #define SCSI_SUPPORT BIT1 BIT1 122 drivers/scsi/dc395x.h #define RESET_DETECT BIT1 BIT1 130 drivers/scsi/dc395x.h #define ABORTION BIT1 BIT1 142 drivers/scsi/dc395x.h #define ABORT_DEV BIT1 BIT1 175 drivers/scsi/dc395x.h #define SYNC_NEGO_DONE BIT1 BIT1 631 drivers/scsi/dc395x.h #define GREATER_1G BIT1 BIT1 710 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR1 BIT1 BIT1 1820 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff; BIT1 2595 drivers/staging/rtl8723bs/core/rtw_mlme.c phtpriv->sgi_40m = TEST_FLAG(pregistrypriv->short_gi, BIT1) ? true : false; BIT1 407 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */ BIT1 2661 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp|BIT0|BIT1); BIT1 3597 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c if (pCoexSta->btInfoExt & BIT1) { BIT1 14 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.h #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1 BIT1 2835 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp|BIT0|BIT1); BIT1 3421 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c if ((pCoexSta->btInfoExt & BIT1)) { BIT1 14 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.h #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1 BIT1 94 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define ALGO_WIFI_RSSI_STATE BIT1 BIT1 106 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define WIFI_AP_CONNECTED BIT1 BIT1 100 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c if ((cond1 & BIT1) != 0) /* GPA */ BIT1 100 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c if ((cond1 & BIT1) != 0) /* GPA */ BIT1 106 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c if ((cond1 & BIT1) != 0) /* GPA */ BIT1 423 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_RA_MASK = BIT1, BIT1 486 drivers/staging/rtl8723bs/hal/odm.h ODM_RF_TX_B = BIT1, BIT1 532 drivers/staging/rtl8723bs/hal/odm.h ODM_LINK = BIT1, BIT1 546 drivers/staging/rtl8723bs/hal/odm.h ODM_WM_G = BIT1, BIT1 53 drivers/staging/rtl8723bs/hal/odm_DIG.c PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0); BIT1 54 drivers/staging/rtl8723bs/hal/odm_DIG.c PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1); BIT1 93 drivers/staging/rtl8723bs/hal/odm_DIG.h ODM_RESUME_DIG = BIT1 BIT1 98 drivers/staging/rtl8723bs/hal/odm_DIG.h ODM_RESUME_CCKPD = BIT1 BIT1 62 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_RA_MASK BIT1 BIT1 2119 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1); BIT1 2122 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1); BIT1 530 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1)); BIT1 1527 drivers/staging/rtl8723bs/hal/sdio_halinit.c while (!(mstatus & BIT1) && trycnt > 1) { BIT1 1585 drivers/staging/rtl8723bs/hal/sdio_halinit.c while (mstatus & BIT1 && trycnt > 1) { BIT1 1592 drivers/staging/rtl8723bs/hal/sdio_halinit.c if (mstatus & BIT1) { BIT1 632 drivers/staging/rtl8723bs/include/drv_types.h #define DF_RX_BIT BIT1 BIT1 225 drivers/staging/rtl8723bs/include/hal_com_phycfg.h #define LOAD_BB_PARA_FILE BIT1 BIT1 609 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_2M BIT1 BIT1 634 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 BIT1 728 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BW_OPMODE_5G BIT1 BIT1 760 drivers/staging/rtl8723bs/include/hal_com_reg.h #define WOW_WOMEN BIT1 /* WoW function on or off. */ BIT1 803 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_VODOK BIT1 /* AC_VO DMA Interrupt */ BIT1 814 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_OCPINT BIT1 BIT1 851 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_RDU BIT1 /* Receive Descriptor Unavailable */ BIT1 869 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_OCPINT BIT1 BIT1 902 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_RDU BIT1 /* Receive Descriptor Unavailable */ BIT1 922 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_OCPINT BIT1 BIT1 956 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */ BIT1 1014 drivers/staging/rtl8723bs/include/hal_com_reg.h #define StopVI BIT1 BIT1 1051 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_APM BIT1 /* Accept physical match packet */ BIT1 1568 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_AVAL_MSK BIT1 BIT1 1594 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_AVAL BIT1 BIT1 1634 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HCI_RESUME_PWR_RDY BIT1 BIT1 1671 drivers/staging/rtl8723bs/include/hal_com_reg.h #define WL_HWPDN_SL BIT1 /* WiFi HW PDn polarity control */ BIT1 1685 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 BIT1 1694 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PARTNO_SINGLE_BAND_VS_REMARK BIT1 BIT1 1696 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0) BIT1 13 drivers/staging/rtl8723bs/include/hal_intf.h RTW_USB = BIT1, BIT1 39 drivers/staging/rtl8723bs/include/hal_phy.h #define ANT_DETECT_BY_RSSI BIT1 BIT1 50 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ BIT1 58 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ BIT1 59 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ BIT1 60 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ BIT1 62 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ BIT1 71 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ BIT1 73 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ BIT1 74 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ BIT1 89 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ BIT1 96 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ BIT1 109 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ BIT1 116 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ BIT1 147 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ BIT1 149 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ BIT1 164 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ BIT1 166 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ BIT1 180 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/ \ BIT1 188 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */ \ BIT1 202 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\ BIT1 206 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \ BIT1 225 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */ BIT1 37 drivers/staging/rtl8723bs/include/rtw_cmd.h RTW_CMDF_WAIT_ACK = BIT1, BIT1 70 drivers/staging/rtl8723bs/include/rtw_ht.h #define LDPC_HT_ENABLE_TX BIT1 BIT1 75 drivers/staging/rtl8723bs/include/rtw_ht.h #define STBC_HT_ENABLE_TX BIT1 BIT1 80 drivers/staging/rtl8723bs/include/rtw_ht.h #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */ BIT1 327 drivers/staging/rtl8723bs/include/rtw_mlme.h RTW_ROAM_ON_RESUME = BIT1, BIT1 45 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_RA_MASK BIT1 /* ODM_BB_RA_MASK */ BIT1 130 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_PCI_ASPM_OSC_DISABLE BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */ BIT1 494 drivers/tty/synclink.c #define IO_PIN BIT1 BIT1 513 drivers/tty/synclink.c #define RXSTATUS_OVERRUN BIT1 BIT1 551 drivers/tty/synclink.c #define TXSTATUS_UNDERRUN BIT1 BIT1 571 drivers/tty/synclink.c #define MISCSTATUS_BRG1_ZERO BIT1 BIT1 597 drivers/tty/synclink.c #define SICR_BRG1_ZERO BIT1 BIT1 631 drivers/tty/synclink.c #define TXSTATUS_UNDERRUN BIT1 BIT1 636 drivers/tty/synclink.c #define DICR_RECEIVE BIT1 BIT1 1596 drivers/tty/synclink.c usc_OutDmaReg( info, CDIR, BIT9 | BIT1 ); BIT1 5167 drivers/tty/synclink.c usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); BIT1 5230 drivers/tty/synclink.c usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); BIT1 5371 drivers/tty/synclink.c usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); BIT1 5460 drivers/tty/synclink.c usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); BIT1 6040 drivers/tty/synclink.c if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1)) BIT1 6244 drivers/tty/synclink.c (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); BIT1 7197 drivers/tty/synclink.c while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) { BIT1 7212 drivers/tty/synclink.c if ( status & (BIT5 | BIT1) ) BIT1 7238 drivers/tty/synclink.c if ( status & (BIT8 | BIT3 | BIT1) ) { BIT1 220 drivers/tty/synclink_gt.c #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) BIT1 381 drivers/tty/synclink_gt.c #define MASK_PARITY BIT1 BIT1 1847 drivers/tty/synclink_gt.c status = *(p + 1) & (BIT1 + BIT0); BIT1 1849 drivers/tty/synclink_gt.c if (status & BIT1) BIT1 1856 drivers/tty/synclink_gt.c if (status & BIT1) BIT1 2034 drivers/tty/synclink_gt.c if (status & BIT1) { BIT1 3866 drivers/tty/synclink_gt.c wr_reg32(info, RDCSR, BIT1); BIT1 3879 drivers/tty/synclink_gt.c wr_reg32(info, TDCSR, BIT1); BIT1 3943 drivers/tty/synclink_gt.c val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ BIT1 3968 drivers/tty/synclink_gt.c val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ BIT1 4001 drivers/tty/synclink_gt.c wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); BIT1 4011 drivers/tty/synclink_gt.c (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); BIT1 4054 drivers/tty/synclink_gt.c val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ BIT1 4400 drivers/tty/synclink_gt.c val |= BIT1 + BIT0; BIT1 4510 drivers/tty/synclink_gt.c if (status & BIT1) BIT1 4552 drivers/tty/synclink_gt.c val |= BIT1; BIT1 4668 drivers/tty/synclink_gt.c status &= ~BIT1; BIT1 4679 drivers/tty/synclink_gt.c } else if (status & BIT1) { BIT1 4723 drivers/tty/synclink_gt.c *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; BIT1 4965 drivers/tty/synclink_gt.c (unsigned short)(rd_reg16(info, TCR) | BIT1)); BIT1 417 drivers/tty/synclinkmp.c #define TXRDYE BIT1 BIT1 427 drivers/tty/synclinkmp.c #define BRKD BIT1 BIT1 428 drivers/tty/synclinkmp.c #define ABTD BIT1 BIT1 429 drivers/tty/synclinkmp.c #define GAPD BIT1 BIT1 2561 drivers/tty/synclinkmp.c if (status & BIT1 << shift) BIT1 2570 drivers/tty/synclinkmp.c if (dmastatus & BIT1 << shift) BIT1 4014 drivers/tty/synclinkmp.c write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); BIT1 4032 drivers/tty/synclinkmp.c write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); BIT1 4287 drivers/tty/synclinkmp.c while( info->tx_count && (read_reg(info,SR0) & BIT1) ) { BIT1 4381 drivers/tty/synclinkmp.c RegValue |= BIT1; BIT1 4400 drivers/tty/synclinkmp.c RegValue |= BIT1; BIT1 4415 drivers/tty/synclinkmp.c RegValue |= (BIT1 + BIT0); BIT1 4532 drivers/tty/synclinkmp.c RegValue |= BIT2 + BIT1; BIT1 4739 drivers/tty/synclinkmp.c testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7> BIT1 4764 drivers/tty/synclinkmp.c EnableBit = BIT1 << (info->port_num*2); BIT1 45 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); BIT1 52 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); BIT1 325 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); BIT1 335 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2); BIT1 338 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2); BIT1 345 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT1 346 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); BIT1 363 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); BIT1 370 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT1 377 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT1 949 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); BIT1 960 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); BIT1 2063 drivers/video/fbdev/via/hw.c p_gfx_dpa_setting->DVP0DataDri_S, BIT1); BIT1 345 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); BIT1 520 drivers/video/fbdev/via/lcd.c BIT0 + BIT1 + BIT2 + BIT3); BIT1 563 drivers/video/fbdev/via/lcd.c BIT0 + BIT1 + BIT2); BIT1 608 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); BIT1 652 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); BIT1 654 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); BIT1 674 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); BIT1 746 drivers/video/fbdev/via/lcd.c BIT7 + BIT2 + BIT1 + BIT0); BIT1 170 drivers/video/fbdev/via/via_utility.c viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1); BIT1 1115 drivers/video/fbdev/via/viafbdev.c (viafb_read_reg(VIASR, SR1B) & BIT1) >> 1; BIT1 1158 drivers/video/fbdev/via/viafbdev.c reg_val << 1, BIT1);