BIT0 303 drivers/char/pcmcia/synclink_cs.c #define IRQ_RXFIFO BIT0 // receive pool full BIT0 311 drivers/char/pcmcia/synclink_cs.c #define PVR_DTR BIT0 BIT0 684 drivers/char/pcmcia/synclink_cs.c #define CMD_TXRESET BIT0 // transmit reset BIT0 1185 drivers/char/pcmcia/synclink_cs.c if (gis & (BIT1 | BIT0)) { BIT0 2997 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0); BIT0 3011 drivers/char/pcmcia/synclink_cs.c val = read_reg(info, CHA + MODE) | BIT0; BIT0 3064 drivers/char/pcmcia/synclink_cs.c val |= BIT0; BIT0 3134 drivers/char/pcmcia/synclink_cs.c val |= BIT0; BIT0 3410 drivers/char/pcmcia/synclink_cs.c val |= BIT0; BIT0 3488 drivers/char/pcmcia/synclink_cs.c val |= BIT0; /* 7 bits */ BIT0 419 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c h2c_parameter[0] |= BIT0; /* trigger */ BIT0 786 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c h2c_parameter[0] |= BIT0; BIT0 1114 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c h2c_parameter[0] |= BIT0; /* function enable */ BIT0 2650 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c u8tmp |= BIT0; BIT0 2654 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c u8tmp |= BIT0; BIT0 2767 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate"); BIT0 14 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.h #define BT_INFO_8192E_2ANT_B_CONNECTION BIT0 BIT0 463 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c h2c_parameter[1] |= BIT0; BIT0 637 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c h2c_parameter[0] |= BIT0; /* function enable */ BIT0 2382 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1); BIT0 2570 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c (bt_info_ext & BIT0) ? "Basic rate" : "EDR rate"); BIT0 14 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.h #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0 BIT0 17 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.h (((_BT_INFO_EXT_&BIT0)) ? true : false) BIT0 335 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c h2c_parameter[0] |= BIT0; /* trigger */ BIT0 754 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c h2c_parameter[1] |= BIT0; BIT0 992 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c h2c_parameter[0] |= BIT0; /* function enable */ BIT0 3571 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1); BIT0 3725 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c (bt_info_ext & BIT0) ? "Basic rate" : "EDR rate"); BIT0 17 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.h #define BT_INFO_8723B_2ANT_B_CONNECTION BIT0 BIT0 398 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c h2c_parameter[0] |= BIT0; /* trigger */ BIT0 655 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c h2c_parameter[1] |= BIT0; BIT0 787 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c h2c_parameter[0] |= BIT0; /* function enable */ BIT0 2218 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c (bt_info_ext & BIT0) ? BIT0 15 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.h #define BT_INFO_8821A_1ANT_B_CONNECTION BIT0 BIT0 18 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.h (((_BT_INFO_EXT_&BIT0)) ? true : false) BIT0 331 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.c h2c_parameter[0] |= BIT0; /* trigger */ BIT0 711 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.c h2c_parameter[1] |= BIT0; BIT0 968 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.c h2c_parameter[0] |= BIT0; /* function enable */ BIT0 3726 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.c (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate"); BIT0 15 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.h #define BT_INFO_8821A_2ANT_B_CONNECTION BIT0 BIT0 88 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define INTF_INIT BIT0 BIT0 92 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define ALGO_BT_RSSI_STATE BIT0 BIT0 104 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h #define WIFI_STA_CONNECTED BIT0 BIT0 358 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RRSR_1M BIT0 BIT0 493 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define WOW_PMEN BIT0 /* Power management Enable. */ BIT0 38 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ BIT0 41 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, BIT0 51 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ BIT0 96 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \ BIT0 155 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \ BIT0 181 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ BIT0 247 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ BIT0 294 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \ BIT0 371 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ BIT0 389 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \ BIT0 395 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \ BIT0 398 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ BIT0 407 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ BIT0 410 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \ BIT0 413 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ BIT0 432 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ BIT0 452 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ BIT0 470 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ BIT0 491 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \ BIT0 502 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \ BIT0 526 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \ BIT0 532 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \ BIT0 543 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \ BIT0 549 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ BIT0 570 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ BIT0 601 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ BIT0 651 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \ BIT0 79 drivers/scsi/dc395x.h #define UNIT_ALLOCATED BIT0 BIT0 85 drivers/scsi/dc395x.h #define DASD_SUPPORT BIT0 BIT0 121 drivers/scsi/dc395x.h #define RESET_DEV BIT0 BIT0 126 drivers/scsi/dc395x.h #define ABORT_DEV_ BIT0 BIT0 129 drivers/scsi/dc395x.h #define SRB_OK BIT0 BIT0 143 drivers/scsi/dc395x.h #define AUTO_REQSENSE BIT0 BIT0 174 drivers/scsi/dc395x.h #define SYNC_NEGO_ENABLE BIT0 BIT0 630 drivers/scsi/dc395x.h #define MORE2_DRV BIT0 BIT0 709 drivers/scsi/lpfc/lpfc_hw4.h #define LPFC_SLI4_INTR0 BIT0 BIT0 2596 drivers/staging/rtl8723bs/core/rtw_mlme.c phtpriv->sgi_20m = TEST_FLAG(pregistrypriv->short_gi, BIT0) ? true : false; BIT0 103 drivers/staging/rtl8723bs/core/rtw_odm.c (BIT0 << i) & dbg_comp ? '+' : ' ', BIT0 142 drivers/staging/rtl8723bs/core/rtw_odm.c (BIT0 << i) & ability ? '+' : ' ', i, BIT0 408 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define IMR_ROK_8723B BIT0 /* Receive DMA OK */ BIT0 323 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c H2C_Parameter[0] |= BIT0; /* trigger */ BIT0 816 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c H2C_Parameter[1] |= BIT0; BIT0 997 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c H2C_Parameter[0] |= BIT0; /* function enable */ BIT0 1192 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c if (u1Tmp & BIT0) { BIT0 2661 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp|BIT0|BIT1); BIT0 2937 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c (btInfoExt&BIT0) ? "Basic rate" : "EDR rate" BIT0 15 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.h #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0 BIT0 18 drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.h (((_BT_INFO_EXT_&BIT0)) ? true : false) BIT0 271 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c H2C_Parameter[0] |= BIT0; /* trigger */ BIT0 731 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c H2C_Parameter[1] |= BIT0; BIT0 1105 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c H2C_Parameter[0] |= BIT0; /* function enable */ BIT0 2835 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp|BIT0|BIT1); BIT0 3030 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c (btInfoExt&BIT0) ? "Basic rate" : "EDR rate" BIT0 15 drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.h #define BT_INFO_8723B_2ANT_B_CONNECTION BIT0 BIT0 89 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define INTF_INIT BIT0 BIT0 93 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define ALGO_BT_RSSI_STATE BIT0 BIT0 105 drivers/staging/rtl8723bs/hal/HalBtcOutSrc.h #define WIFI_STA_CONNECTED BIT0 BIT0 98 drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c if ((cond1 & BIT0) != 0) /* GLNA */ BIT0 98 drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c if ((cond1 & BIT0) != 0) /* GLNA */ BIT0 104 drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c if ((cond1 & BIT0) != 0) /* GLNA */ BIT0 422 drivers/staging/rtl8723bs/hal/odm.h ODM_BB_DIG = BIT0, BIT0 485 drivers/staging/rtl8723bs/hal/odm.h ODM_RF_TX_A = BIT0, BIT0 531 drivers/staging/rtl8723bs/hal/odm.h ODM_NO_LINK = BIT0, BIT0 545 drivers/staging/rtl8723bs/hal/odm.h ODM_WM_B = BIT0, BIT0 92 drivers/staging/rtl8723bs/hal/odm_DIG.h ODM_PAUSE_DIG = BIT0, BIT0 97 drivers/staging/rtl8723bs/hal/odm_DIG.h ODM_PAUSE_CCKPD = BIT0, BIT0 340 drivers/staging/rtl8723bs/hal/odm_HWConfig.c pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; BIT0 374 drivers/staging/rtl8723bs/hal/odm_HWConfig.c OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0; BIT0 61 drivers/staging/rtl8723bs/hal/odm_debug.h #define ODM_COMP_DIG BIT0 BIT0 93 drivers/staging/rtl8723bs/hal/odm_reg.h #define BIT_FA_RESET BIT0 BIT0 530 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1)); BIT0 631 drivers/staging/rtl8723bs/include/drv_types.h #define DF_TX_BIT BIT0 BIT0 224 drivers/staging/rtl8723bs/include/hal_com_phycfg.h #define LOAD_MAC_PARA_FILE BIT0 BIT0 560 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HSIMR_GPIO12_0_INT_EN BIT0 BIT0 569 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HSISR_GPIO12_0_INT BIT0 BIT0 608 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RRSR_1M BIT0 BIT0 633 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 BIT0 759 drivers/staging/rtl8723bs/include/hal_com_reg.h #define WOW_PMEN BIT0 /* Power management Enable. */ BIT0 804 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_ROK BIT0 /* Receive DMA OK Interrupt */ BIT0 815 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_WLANOFF BIT0 BIT0 852 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PHIMR_ROK BIT0 /* Receive DMA OK Interrupt */ BIT0 903 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UHIMR_ROK BIT0 /* Receive DMA OK Interrupt */ BIT0 957 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IMR_ROK_88E BIT0 /* Receive DMA OK */ BIT0 1015 drivers/staging/rtl8723bs/include/hal_com_reg.h #define StopVO BIT0 BIT0 1052 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RCR_AAP BIT0 /* Accept all unicast packet */ BIT0 1567 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HIMR_RX_REQUEST_MSK BIT0 BIT0 1593 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SDIO_HISR_RX_REQUEST BIT0 BIT0 1635 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HCI_SUS_CTRL BIT0 BIT0 1670 drivers/staging/rtl8723bs/include/hal_com_reg.h #define WL_HWPDN_EN BIT0 /* Enable GPIO[9] as WiFi HW PDn source */ BIT0 1686 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 BIT0 1696 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0) BIT0 94 drivers/staging/rtl8723bs/include/hal_data.h #define DYNAMIC_FUNC_BT BIT0 BIT0 12 drivers/staging/rtl8723bs/include/hal_intf.h RTW_PCIE = BIT0, BIT0 38 drivers/staging/rtl8723bs/include/hal_phy.h #define ANT_DETECT_BY_SINGLE_TONE BIT0 BIT0 44 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ BIT0 49 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \ BIT0 51 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \ BIT0 52 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \ BIT0 55 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ BIT0 56 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \ BIT0 61 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ BIT0 72 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \ BIT0 77 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\ BIT0 88 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ BIT0 95 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ BIT0 106 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ BIT0 108 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ BIT0 115 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ BIT0 117 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ BIT0 128 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ BIT0 145 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ BIT0 166 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ BIT0 173 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/ \ BIT0 174 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ BIT0 175 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \ BIT0 176 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ BIT0 177 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \ BIT0 178 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ BIT0 185 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \ BIT0 186 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/ \ BIT0 189 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\ BIT0 190 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\ BIT0 193 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/ \ BIT0 194 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */ BIT0 207 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \ BIT0 209 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \ BIT0 213 drivers/staging/rtl8723bs/include/hal_pwr_seq.h {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ BIT0 226 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define IMR_ROK_8723B BIT0 /* Receive DMA OK */ BIT0 36 drivers/staging/rtl8723bs/include/rtw_cmd.h RTW_CMDF_DIRECTLY = BIT0, BIT0 69 drivers/staging/rtl8723bs/include/rtw_ht.h #define LDPC_HT_ENABLE_RX BIT0 BIT0 74 drivers/staging/rtl8723bs/include/rtw_ht.h #define STBC_HT_ENABLE_RX BIT0 BIT0 79 drivers/staging/rtl8723bs/include/rtw_ht.h #define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */ BIT0 326 drivers/staging/rtl8723bs/include/rtw_mlme.h RTW_ROAM_ON_EXPIRED = BIT0, BIT0 44 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h #define DYNAMIC_BB_DIG BIT0 /* ODM_BB_DIG */ BIT0 129 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_PCI_ASPM_OSC_ENABLE BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */ BIT0 495 drivers/tty/synclink.c #define MISC BIT0 BIT0 514 drivers/tty/synclink.c #define RXSTATUS_DATA_AVAILABLE BIT0 BIT0 552 drivers/tty/synclink.c #define TXSTATUS_FIFO_EMPTY BIT0 BIT0 572 drivers/tty/synclink.c #define MISCSTATUS_BRG0_ZERO BIT0 BIT0 598 drivers/tty/synclink.c #define SICR_BRG0_ZERO BIT0 BIT0 632 drivers/tty/synclink.c #define TXSTATUS_FIFO_EMPTY BIT0 BIT0 635 drivers/tty/synclink.c #define DICR_TRANSMIT BIT0 BIT0 1640 drivers/tty/synclink.c usc_OutDmaReg(info, CDIR, BIT8 | BIT0 ); BIT0 5167 drivers/tty/synclink.c usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); BIT0 5230 drivers/tty/synclink.c usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); BIT0 5236 drivers/tty/synclink.c usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); BIT0 5566 drivers/tty/synclink.c usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) ); BIT0 6244 drivers/tty/synclink.c (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); BIT0 6253 drivers/tty/synclink.c usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); BIT0 214 drivers/tty/synclink_gt.c #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) BIT0 221 drivers/tty/synclink_gt.c #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) BIT0 382 drivers/tty/synclink_gt.c #define MASK_FRAMING BIT0 BIT0 424 drivers/tty/synclink_gt.c #define IRQ_MASTER BIT0 BIT0 1847 drivers/tty/synclink_gt.c status = *(p + 1) & (BIT1 + BIT0); BIT0 1851 drivers/tty/synclink_gt.c else if (status & BIT0) BIT0 1858 drivers/tty/synclink_gt.c else if (status & BIT0) BIT0 2071 drivers/tty/synclink_gt.c if (status & BIT0) { BIT0 3870 drivers/tty/synclink_gt.c if (!(rd_reg32(info, RDCSR) & BIT0)) BIT0 3883 drivers/tty/synclink_gt.c if (!(rd_reg32(info, TDCSR) & BIT0)) BIT0 3991 drivers/tty/synclink_gt.c wr_reg32(info, RDCSR, (BIT2 + BIT0)); BIT0 3994 drivers/tty/synclink_gt.c wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); BIT0 4040 drivers/tty/synclink_gt.c wr_reg32(info, TDCSR, BIT2 + BIT0); BIT0 4139 drivers/tty/synclink_gt.c val |= BIT0; BIT0 4176 drivers/tty/synclink_gt.c val |= BIT0; BIT0 4212 drivers/tty/synclink_gt.c val = BIT15 + BIT14 + BIT0; BIT0 4301 drivers/tty/synclink_gt.c val |= BIT0; BIT0 4364 drivers/tty/synclink_gt.c val |= BIT0; BIT0 4400 drivers/tty/synclink_gt.c val |= BIT1 + BIT0; BIT0 4448 drivers/tty/synclink_gt.c wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); BIT0 4512 drivers/tty/synclink_gt.c if (status & BIT0) BIT0 4554 drivers/tty/synclink_gt.c val |= BIT0; BIT0 4676 drivers/tty/synclink_gt.c if (framesize < (2 + crc_size) || status & BIT0) { BIT0 4800 drivers/tty/synclink_gt.c if (count && (rd_reg32(info, TDCSR) & BIT0)) BIT0 4843 drivers/tty/synclink_gt.c if (reg_value & BIT0) BIT0 418 drivers/tty/synclinkmp.c #define RXRDYE BIT0 BIT0 430 drivers/tty/synclinkmp.c #define BRKE BIT0 BIT0 431 drivers/tty/synclinkmp.c #define IDLD BIT0 BIT0 2148 drivers/tty/synclinkmp.c while((status = read_reg(info,CST0)) & BIT0) BIT0 2559 drivers/tty/synclinkmp.c if (status & BIT0 << shift) BIT0 2568 drivers/tty/synclinkmp.c if (dmastatus & BIT0 << shift) BIT0 4014 drivers/tty/synclinkmp.c write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); BIT0 4017 drivers/tty/synclinkmp.c info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); BIT0 4032 drivers/tty/synclinkmp.c write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); BIT0 4402 drivers/tty/synclinkmp.c RegValue |= BIT0; BIT0 4415 drivers/tty/synclinkmp.c RegValue |= (BIT1 + BIT0); BIT0 4440 drivers/tty/synclinkmp.c info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); BIT0 4617 drivers/tty/synclinkmp.c info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); BIT0 4619 drivers/tty/synclinkmp.c info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2)); BIT0 4743 drivers/tty/synclinkmp.c testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6> BIT0 4758 drivers/tty/synclinkmp.c RegValue &= ~BIT0; BIT0 4760 drivers/tty/synclinkmp.c RegValue |= BIT0; BIT0 45 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); BIT0 52 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); BIT0 335 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2); BIT0 338 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2); BIT0 345 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT0 363 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); BIT0 370 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT0 377 drivers/video/fbdev/via/dvi.c BIT0 + BIT1 + BIT2 + BIT3); BIT0 395 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); BIT0 396 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); BIT0 408 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); BIT0 421 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); BIT0 462 drivers/video/fbdev/via/dvi.c viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0); BIT0 472 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR47, VIACR, 0, BIT0); BIT0 949 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); BIT0 986 drivers/video/fbdev/via/hw.c reg_mask = reg_mask | (BIT0 << j); BIT0 987 drivers/video/fbdev/via/hw.c get_bit = (timing_value & (BIT0 << bit_num)); BIT0 1667 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); BIT0 1681 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); BIT0 1688 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); BIT0 345 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); BIT0 520 drivers/video/fbdev/via/lcd.c BIT0 + BIT1 + BIT2 + BIT3); BIT0 563 drivers/video/fbdev/via/lcd.c BIT0 + BIT1 + BIT2); BIT0 585 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); BIT0 652 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); BIT0 654 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); BIT0 661 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR91, VIACR, 0, BIT0); BIT0 670 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CRD3, VIACR, 0, BIT0); BIT0 746 drivers/video/fbdev/via/lcd.c BIT7 + BIT2 + BIT1 + BIT0); BIT0 846 drivers/video/fbdev/via/lcd.c bdithering = BIT0; BIT0 848 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0); BIT0 152 drivers/video/fbdev/via/via_utility.c viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); BIT0 169 drivers/video/fbdev/via/via_utility.c viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); BIT0 207 drivers/video/fbdev/via/via_utility.c viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);