BIT 124 arch/arc/include/asm/cache.h #define ARC_IO_COH_ENABLE_BIT BIT(0) BIT 126 arch/arc/include/asm/cache.h #define ARC_IO_COH_PARTIAL_BIT BIT(0) BIT 218 arch/arc/include/asm/pgtable.h #define PGDIR_SIZE BIT(PGDIR_SHIFT) /* vaddr span, not PDG sz */ BIT 221 arch/arc/include/asm/pgtable.h #define PTRS_PER_PTE BIT(BITS_FOR_PTE) BIT 222 arch/arc/include/asm/pgtable.h #define PTRS_PER_PGD BIT(BITS_FOR_PGD) BIT 45 arch/arc/kernel/mcip.c gfrc_halt_mask |= BIT(cpu); BIT 66 arch/arc/kernel/mcip.c mcip_mask |= BIT(cpu); BIT 307 arch/arc/kernel/perf_event.c read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx)); BIT 325 arch/arc/kernel/perf_event.c write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx)); BIT 327 arch/arc/kernel/perf_event.c read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~BIT(idx)); BIT 423 arch/arc/kernel/perf_event.c write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx)); BIT 431 arch/arc/kernel/perf_event.c read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx)); BIT 445 arch/arc/kernel/perf_event.c active_ints &= ~BIT(idx); BIT 55 arch/arc/plat-eznps/include/plat/ctop.h #define HW_COMPLY_KRN_NOT_D_CACHED BIT(28) BIT 59 arch/arc/plat-eznps/include/plat/ctop.h #define NPS_CRG_SYNC_BIT BIT(0) BIT 63 arch/arc/plat-eznps/include/plat/ctop.h #define NPS_GIM_UART_LINE BIT(7) BIT 64 arch/arc/plat-eznps/include/plat/ctop.h #define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE BIT(10) BIT 65 arch/arc/plat-eznps/include/plat/ctop.h #define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE BIT(11) BIT 66 arch/arc/plat-eznps/include/plat/ctop.h #define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE BIT(25) BIT 67 arch/arc/plat-eznps/include/plat/ctop.h #define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE BIT(26) BIT 249 arch/arm/common/sa1111.c return BIT(irqd_to_hwirq(d) & 31); BIT 413 arch/arm/common/sa1111.c writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) | BIT 414 arch/arm/common/sa1111.c BIT(IRQ_S1_READY_NINT & 31), BIT 499 arch/arm/common/sa1111.c return BIT(offset); BIT 501 arch/arm/common/sa1111.c return BIT(offset - 4); BIT 503 arch/arm/common/sa1111.c return BIT(offset - 10); BIT 32 arch/arm/include/asm/cpufeature.h return num < 32 ? elf_hwcap & BIT(num) : elf_hwcap2 & BIT(num - 32); BIT 91 arch/arm/include/asm/cti.h val |= BIT(chan); BIT 95 arch/arm/include/asm/cti.h val |= BIT(chan); BIT 133 arch/arm/include/asm/cti.h val |= BIT(cti->trig_out_for_irq); BIT 78 arch/arm/include/asm/hardware/cache-l2x0.h #define L2X0_EVENT_CNT_CTRL_ENABLE BIT(0) BIT 91 arch/arm/include/asm/hardware/cache-l2x0.h #define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20) BIT 92 arch/arm/include/asm/hardware/cache-l2x0.h #define L2C_AUX_CTRL_PARITY_ENABLE BIT(21) BIT 93 arch/arm/include/asm/hardware/cache-l2x0.h #define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22) BIT 106 arch/arm/include/asm/hardware/cache-l2x0.h #define L210_AUX_CTRL_WRAP_DISABLE BIT(12) BIT 107 arch/arm/include/asm/hardware/cache-l2x0.h #define L210_AUX_CTRL_WA_OVERRIDE BIT(23) BIT 108 arch/arm/include/asm/hardware/cache-l2x0.h #define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24) BIT 110 arch/arm/include/asm/hardware/cache-l2x0.h #define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) BIT 113 arch/arm/include/asm/hardware/cache-l2x0.h #define L220_AUX_CTRL_NS_LOCKDOWN BIT(26) BIT 114 arch/arm/include/asm/hardware/cache-l2x0.h #define L220_AUX_CTRL_NS_INT_CTRL BIT(27) BIT 116 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */ BIT 117 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */ BIT 118 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */ BIT 119 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) BIT 120 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16) BIT 121 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */ BIT 122 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_NS_LOCKDOWN BIT(26) BIT 123 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_NS_INT_CTRL BIT(27) BIT 124 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_DATA_PREFETCH BIT(28) BIT 125 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_INSTR_PREFETCH BIT(29) BIT 126 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */ BIT 135 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23) BIT 136 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24) BIT 137 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27) BIT 138 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28) BIT 139 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29) BIT 140 arch/arm/include/asm/hardware/cache-l2x0.h #define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30) BIT 700 arch/arm/kernel/perf_event_v7.c #define ARMV7_EXCLUDE_PL1 BIT(31) BIT 701 arch/arm/kernel/perf_event_v7.c #define ARMV7_EXCLUDE_USER BIT(30) BIT 702 arch/arm/kernel/perf_event_v7.c #define ARMV7_INCLUDE_HYP BIT(27) BIT 707 arch/arm/kernel/perf_event_v7.c #define ARMV7_SDER_SUNIDEN BIT(1) /* Permit non-invasive debug */ BIT 736 arch/arm/kernel/perf_event_v7.c return pmnc & BIT(ARMV7_IDX_TO_COUNTER(idx)); BIT 793 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter))); BIT 799 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter))); BIT 805 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter))); BIT 811 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); BIT 814 arch/arm/kernel/perf_event_v7.c asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter))); BIT 1322 arch/arm/kernel/perf_event_v7.c #define PMRESRn_EN BIT(31) BIT 84 arch/arm/kernel/traps.c if (instruction & BIT(reg)) { BIT 28 arch/arm/mach-actions/platsmp.c #define OWL_SPS_PG_CTL_PWR_CPU2 BIT(5) BIT 29 arch/arm/mach-actions/platsmp.c #define OWL_SPS_PG_CTL_PWR_CPU3 BIT(6) BIT 30 arch/arm/mach-actions/platsmp.c #define OWL_SPS_PG_CTL_ACK_CPU2 BIT(21) BIT 31 arch/arm/mach-actions/platsmp.c #define OWL_SPS_PG_CTL_ACK_CPU3 BIT(22) BIT 97 arch/arm/mach-at91/pm.c { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, BIT 20 arch/arm/mach-bcm/bcm63xx_pmb.c #define PLL_PWR_ON BIT(8) BIT 21 arch/arm/mach-bcm/bcm63xx_pmb.c #define PLL_LDO_PWR_ON BIT(9) BIT 22 arch/arm/mach-bcm/bcm63xx_pmb.c #define PLL_CLAMP_ON BIT(10) BIT 23 arch/arm/mach-bcm/bcm63xx_pmb.c #define CPU_RESET_N(x) BIT(13 + (x)) BIT 24 arch/arm/mach-bcm/bcm63xx_pmb.c #define NEON_RESET_N BIT(15) BIT 31 arch/arm/mach-bcm/bcm63xx_pmb.c #define MEM_PWR_OK BIT(0) BIT 32 arch/arm/mach-bcm/bcm63xx_pmb.c #define MEM_PWR_ON BIT(1) BIT 33 arch/arm/mach-bcm/bcm63xx_pmb.c #define MEM_CLAMP_ON BIT(2) BIT 34 arch/arm/mach-bcm/bcm63xx_pmb.c #define MEM_PWR_OK_STATUS BIT(4) BIT 35 arch/arm/mach-bcm/bcm63xx_pmb.c #define MEM_PWR_ON_STATUS BIT(5) BIT 40 arch/arm/mach-bcm/bcm63xx_pmb.c #define CLAMP_ON BIT(15) BIT 34 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_MAN_CLKEN_MASK = BIT(0), BIT 35 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_MAN_RESET_CNTL_MASK = BIT(1), BIT 36 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_MAN_MEM_PWR_MASK = BIT(4), BIT 37 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_RESERVED_1_MASK = BIT(5), BIT 38 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_MAN_ISO_CNTL_MASK = BIT(6), BIT 39 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_MANUAL_CONTROL_MASK = BIT(7), BIT 40 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_PWR_DN_REQ_MASK = BIT(9), BIT 41 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_PWR_UP_REQ_MASK = BIT(10), BIT 42 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_BLK_RST_ASSERT_MASK = BIT(12), BIT 43 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_PWR_OFF_STATE_MASK = BIT(25), BIT 44 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_PWR_ON_STATE_MASK = BIT(26), BIT 45 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_DPG_PWR_STATE_MASK = BIT(28), BIT 46 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_MEM_PWR_STATE_MASK = BIT(29), BIT 47 arch/arm/mach-bcm/platsmp-brcmstb.c ZONE_RESET_STATE_MASK = BIT(31), BIT 132 arch/arm/mach-bcm/platsmp-brcmstb.c val |= BIT(cpu_logical_map(cpu)); BIT 134 arch/arm/mach-bcm/platsmp-brcmstb.c val &= ~BIT(cpu_logical_map(cpu)); BIT 38 arch/arm/mach-berlin/platsmp.c val &= ~BIT(cpu_logical_map(cpu)); BIT 40 arch/arm/mach-berlin/platsmp.c val |= BIT(cpu_logical_map(cpu)); BIT 112 arch/arm/mach-berlin/platsmp.c val &= ~BIT(cpu_logical_map(cpu)); BIT 1114 arch/arm/mach-davinci/board-da850-evm.c val |= BIT(8); BIT 1119 arch/arm/mach-davinci/board-da850-evm.c val &= ~BIT(8); BIT 82 arch/arm/mach-davinci/board-dm355-evm.c .mask_chipsel = BIT(14), BIT 432 arch/arm/mach-davinci/board-dm355-evm.c dm355_init_spi0(BIT(0), dm355_evm_spi_info, BIT 76 arch/arm/mach-davinci/board-dm355-leopard.c .mask_chipsel = BIT(14), BIT 269 arch/arm/mach-davinci/board-dm355-leopard.c dm355_init_spi0(BIT(0), dm355_leopard_spi_info, BIT 144 arch/arm/mach-davinci/board-dm365-evm.c .mask_chipsel = BIT(14), BIT 290 arch/arm/mach-davinci/board-dm365-evm.c return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0)); BIT 299 arch/arm/mach-davinci/board-dm365-evm.c return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1)); BIT 661 arch/arm/mach-davinci/board-dm365-evm.c led->mask = BIT(i); BIT 709 arch/arm/mach-davinci/board-dm365-evm.c if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) { BIT 711 arch/arm/mach-davinci/board-dm365-evm.c mux |= BIT(7); BIT 722 arch/arm/mach-davinci/board-dm365-evm.c resets = BIT(3) | BIT(2) | BIT(1) | BIT(0); BIT 736 arch/arm/mach-davinci/board-dm365-evm.c mux |= BIT(6) | BIT(5) | BIT(3); BIT 747 arch/arm/mach-davinci/board-dm365-evm.c resets &= ~BIT(3); BIT 750 arch/arm/mach-davinci/board-dm365-evm.c resets &= ~BIT(1); BIT 754 arch/arm/mach-davinci/board-dm365-evm.c resets &= ~BIT(2); BIT 759 arch/arm/mach-davinci/board-dm365-evm.c resets &= ~BIT(0); BIT 827 arch/arm/mach-davinci/board-dm365-evm.c dm365_init_spi0(BIT(0), dm365_evm_spi_info, BIT 615 arch/arm/mach-davinci/board-dm644x-evm.c return (status < 0) ? status : !(status & BIT(1)); BIT 622 arch/arm/mach-davinci/board-dm644x-evm.c return (status < 0) ? status : status & BIT(6 + 8); BIT 159 arch/arm/mach-davinci/board-dm646x-evm.c #define DM646X_EVM_ATA_RST BIT(0) BIT 160 arch/arm/mach-davinci/board-dm646x-evm.c #define DM646X_EVM_ATA_PWD BIT(1) BIT 463 arch/arm/mach-davinci/board-dm646x-evm.c #define VCH2CLK_SYSCLK8 (BIT(9)) BIT 464 arch/arm/mach-davinci/board-dm646x-evm.c #define VCH2CLK_AUXCLK (BIT(9) | BIT(8)) BIT 466 arch/arm/mach-davinci/board-dm646x-evm.c #define VCH3CLK_SYSCLK8 (BIT(13)) BIT 467 arch/arm/mach-davinci/board-dm646x-evm.c #define VCH3CLK_AUXCLK (BIT(14) | BIT(13)) BIT 469 arch/arm/mach-davinci/board-dm646x-evm.c #define VIDCH2CLK (BIT(10)) BIT 470 arch/arm/mach-davinci/board-dm646x-evm.c #define VIDCH3CLK (BIT(11)) BIT 471 arch/arm/mach-davinci/board-dm646x-evm.c #define VIDCH1CLK (BIT(4)) BIT 472 arch/arm/mach-davinci/board-dm646x-evm.c #define TVP7002_INPUT (BIT(4)) BIT 473 arch/arm/mach-davinci/board-dm646x-evm.c #define TVP5147_INPUT (~BIT(4)) BIT 474 arch/arm/mach-davinci/board-dm646x-evm.c #define VPIF_INPUT_ONE_CHANNEL (BIT(5)) BIT 475 arch/arm/mach-davinci/board-dm646x-evm.c #define VPIF_INPUT_TWO_CHANNEL (~BIT(5)) BIT 533 arch/arm/mach-davinci/board-mityomapl138.c val |= BIT(8); BIT 537 arch/arm/mach-davinci/board-mityomapl138.c val &= ~BIT(8); BIT 56 arch/arm/mach-davinci/board-omapl138-hawk.c val &= ~BIT(8); BIT 14 arch/arm/mach-davinci/clock.h #define PLLCTL_PLLEN BIT(0) BIT 15 arch/arm/mach-davinci/clock.h #define PLLCTL_PLLPWRDN BIT(1) BIT 16 arch/arm/mach-davinci/clock.h #define PLLCTL_PLLRST BIT(3) BIT 17 arch/arm/mach-davinci/clock.h #define PLLCTL_PLLDIS BIT(4) BIT 18 arch/arm/mach-davinci/clock.h #define PLLCTL_PLLENSRC BIT(5) BIT 19 arch/arm/mach-davinci/clock.h #define PLLCTL_CLKMODE BIT(8) BIT 43 arch/arm/mach-davinci/clock.h #define PLLDIV_EN BIT(15) BIT 51 arch/arm/mach-davinci/davinci.h #define VPSS_MUXSEL_EXTCLK_ENABLE BIT(1) BIT 52 arch/arm/mach-davinci/davinci.h #define VPSS_VENCCLKEN_ENABLE BIT(3) BIT 53 arch/arm/mach-davinci/davinci.h #define VPSS_DACCLKEN_ENABLE BIT(4) BIT 54 arch/arm/mach-davinci/davinci.h #define VPSS_PLLC2SYSCLK5_ENABLE BIT(5) BIT 90 arch/arm/mach-davinci/dm355.c if (chipselect_mask & BIT(0)) BIT 92 arch/arm/mach-davinci/dm355.c if (chipselect_mask & BIT(1)) BIT 254 arch/arm/mach-davinci/dm365.c if (chipselect_mask & BIT(0)) BIT 256 arch/arm/mach-davinci/dm365.c if (chipselect_mask & BIT(1)) BIT 410 arch/arm/mach-davinci/dm644x.c #define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0) BIT 411 arch/arm/mach-davinci/dm644x.c #define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1) BIT 412 arch/arm/mach-davinci/dm644x.c #define DM644X_VPSS_VENCLKEN BIT(3) BIT 413 arch/arm/mach-davinci/dm644x.c #define DM644X_VPSS_DACCLKEN BIT(4) BIT 202 arch/arm/mach-davinci/psc.h #define MDCTL_LRST BIT(8) BIT 203 arch/arm/mach-davinci/psc.h #define MDCTL_FORCE BIT(31) BIT 204 arch/arm/mach-davinci/psc.h #define PDCTL_NEXT BIT(0) BIT 205 arch/arm/mach-davinci/psc.h #define PDCTL_EPCGOOD BIT(8) BIT 53 arch/arm/mach-dove/pm.h #define PMU_SW_RST_VIDEO_MASK BIT(16) BIT 54 arch/arm/mach-dove/pm.h #define PMU_SW_RST_GPU_MASK BIT(18) BIT 56 arch/arm/mach-dove/pm.h #define PMU_PWR_GPU_PWR_DWN_MASK BIT(2) BIT 57 arch/arm/mach-dove/pm.h #define PMU_PWR_VPU_PWR_DWN_MASK BIT(3) BIT 59 arch/arm/mach-dove/pm.h #define PMU_ISO_VIDEO_MASK BIT(0) BIT 60 arch/arm/mach-dove/pm.h #define PMU_ISO_GPU_MASK BIT(1) BIT 24 arch/arm/mach-exynos/mcpm-exynos.c #define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9) BIT 25 arch/arm/mach-exynos/mcpm-exynos.c #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29) BIT 26 arch/arm/mach-exynos/mcpm-exynos.c #define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30) BIT 80 arch/arm/mach-exynos/suspend.c { 73, BIT(1) }, /* RTC alarm */ BIT 81 arch/arm/mach-exynos/suspend.c { 74, BIT(2) }, /* RTC tick */ BIT 86 arch/arm/mach-exynos/suspend.c { 44, BIT(1) }, /* RTC alarm */ BIT 87 arch/arm/mach-exynos/suspend.c { 45, BIT(2) }, /* RTC tick */ BIT 92 arch/arm/mach-exynos/suspend.c { 43, BIT(1) }, /* RTC alarm */ BIT 93 arch/arm/mach-exynos/suspend.c { 44, BIT(2) }, /* RTC tick */ BIT 288 arch/arm/mach-exynos/suspend.c pmu_raw_writel(exynos_irqwake_intmask & ~BIT(31), S5P_WAKEUP_MASK); BIT 22 arch/arm/mach-footbridge/ebsa285.c #define XBUS_AMBER_L BIT(0) BIT 23 arch/arm/mach-footbridge/ebsa285.c #define XBUS_GREEN_L BIT(1) BIT 24 arch/arm/mach-footbridge/ebsa285.c #define XBUS_RED_L BIT(2) BIT 25 arch/arm/mach-footbridge/ebsa285.c #define XBUS_TOGGLE BIT(7) BIT 95 arch/arm/mach-footbridge/ebsa285.c led->mask = BIT(i); BIT 116 arch/arm/mach-imx/cpu-imx5.c #define DBGEN BIT(16) BIT 170 arch/arm/mach-ixp4xx/common-pci.c addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | BIT 195 arch/arm/mach-ixp4xx/common-pci.c return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL; BIT 197 arch/arm/mach-ixp4xx/common-pci.c return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL; BIT 230 arch/arm/mach-ixp4xx/common-pci.c return (0xf & ~BIT(n)) << 4; BIT 232 arch/arm/mach-ixp4xx/common-pci.c return (0xf & ~(BIT(n) | BIT(n+1))) << 4; BIT 456 arch/arm/mach-ixp4xx/goramo_mlr.c u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0; BIT 89 arch/arm/mach-ixp4xx/include/mach/io.h byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; BIT 114 arch/arm/mach-ixp4xx/include/mach/io.h byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; BIT 157 arch/arm/mach-ixp4xx/include/mach/io.h byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; BIT 182 arch/arm/mach-ixp4xx/include/mach/io.h byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; BIT 250 arch/arm/mach-ixp4xx/include/mach/io.h byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; BIT 269 arch/arm/mach-ixp4xx/include/mach/io.h byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; BIT 301 arch/arm/mach-ixp4xx/include/mach/io.h byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; BIT 321 arch/arm/mach-ixp4xx/include/mach/io.h byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; BIT 50 arch/arm/mach-meson/platsmp.c val |= BIT(cpu); BIT 52 arch/arm/mach-meson/platsmp.c val &= ~BIT(cpu); BIT 55 arch/arm/mach-meson/platsmp.c val |= BIT(0); BIT 185 arch/arm/mach-meson/platsmp.c ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), BIT 268 arch/arm/mach-meson/platsmp.c ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), BIT 332 arch/arm/mach-meson/platsmp.c ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), BIT 382 arch/arm/mach-meson/platsmp.c ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), BIT 69 arch/arm/mach-mvebu/coherency.c #define CPU_CONFIG_SHARED_L2 BIT(16) BIT 25 arch/arm/mach-mvebu/cpu-reset.c #define CPU_RESET_ASSERT BIT(0) BIT 37 arch/arm/mach-mvebu/pm-board.c reg &= ~BIT(pic_raw_gpios[i]); BIT 38 arch/arm/mach-mvebu/pm-board.c reg |= BIT(pic_raw_gpios[0]); BIT 44 arch/arm/mach-mvebu/pm-board.c ackcmd |= BIT(pic_raw_gpios[i]); BIT 30 arch/arm/mach-mvebu/pm.c #define SDRAM_CONFIG_SR_MODE_BIT BIT(24) BIT 49 arch/arm/mach-mvebu/pmsu.c #define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18) BIT 50 arch/arm/mach-mvebu/pmsu.c #define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16) BIT 51 arch/arm/mach-mvebu/pmsu.c #define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20) BIT 55 arch/arm/mach-mvebu/pmsu.c #define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0) BIT 58 arch/arm/mach-mvebu/pmsu.c #define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16) BIT 59 arch/arm/mach-mvebu/pmsu.c #define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17) BIT 60 arch/arm/mach-mvebu/pmsu.c #define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20) BIT 61 arch/arm/mach-mvebu/pmsu.c #define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21) BIT 62 arch/arm/mach-mvebu/pmsu.c #define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22) BIT 63 arch/arm/mach-mvebu/pmsu.c #define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24) BIT 64 arch/arm/mach-mvebu/pmsu.c #define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25) BIT 67 arch/arm/mach-mvebu/pmsu.c #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE BIT(1) BIT 68 arch/arm/mach-mvebu/pmsu.c #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK BIT(17) BIT 74 arch/arm/mach-mvebu/pmsu.c #define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20) BIT 78 arch/arm/mach-mvebu/pmsu.c #define PMSU_POWERDOWN_DELAY_PMU BIT(1) BIT 85 arch/arm/mach-mvebu/pmsu.c #define MPCORE_RESET_CTL_L2 BIT(0) BIT 86 arch/arm/mach-mvebu/pmsu.c #define MPCORE_RESET_CTL_DEBUG BIT(16) BIT 222 arch/arm/mach-mvebu/pmsu.c PMSU_PREPARE_DEEP_IDLE = BIT(0), BIT 223 arch/arm/mach-mvebu/pmsu.c PMSU_PREPARE_SNOOP_DISABLE = BIT(1), BIT 82 arch/arm/mach-omap1/i2c.c #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) BIT 95 arch/arm/mach-omap2/clockdomain.h #define _CLKDM_FLAG_HWSUP_ENABLED BIT(0) BIT 235 arch/arm/mach-omap2/control.h #define OMAP36XX_GPIO_IO_PWRDNZ BIT(6) BIT 375 arch/arm/mach-omap2/control.h #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) BIT 376 arch/arm/mach-omap2/control.h #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) BIT 377 arch/arm/mach-omap2/control.h #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) BIT 378 arch/arm/mach-omap2/control.h #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) BIT 379 arch/arm/mach-omap2/control.h #define AM35XX_USBOTGSS_INT_CLR BIT(4) BIT 380 arch/arm/mach-omap2/control.h #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) BIT 381 arch/arm/mach-omap2/control.h #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) BIT 382 arch/arm/mach-omap2/control.h #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) BIT 385 arch/arm/mach-omap2/control.h #define AM35XX_USBOTGSS_SW_RST BIT(0) BIT 386 arch/arm/mach-omap2/control.h #define AM35XX_CPGMACSS_SW_RST BIT(1) BIT 387 arch/arm/mach-omap2/control.h #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) BIT 388 arch/arm/mach-omap2/control.h #define AM35XX_HECC_SW_RST BIT(3) BIT 389 arch/arm/mach-omap2/control.h #define AM35XX_VPFE_PCLK_SW_RST BIT(4) BIT 410 arch/arm/mach-omap2/control.h #define AM33XX_SGX_MASK BIT(29) BIT 55 arch/arm/mach-omap2/cpuidle34xx.c #define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0) BIT 17 arch/arm/mach-omap2/i2c.c #define I2C_EN BIT(15) BIT 28 arch/arm/mach-omap2/msdi.c #define MSDI_CON_POW_MASK BIT(11) BIT 350 arch/arm/mach-omap2/omap-mpuss-lowpower.c reg |= BIT(24) | BIT(25); BIT 130 arch/arm/mach-omap2/omap-smp.c acr_mask = BIT(0); BIT 113 arch/arm/mach-omap2/omap-wakeupgen.c val &= ~BIT(bit_number); BIT 126 arch/arm/mach-omap2/omap-wakeupgen.c val |= BIT(bit_number); BIT 623 arch/arm/mach-omap2/omap-wakeupgen.c val |= BIT(5); BIT 197 arch/arm/mach-omap2/omap4-common.c if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) { BIT 38 arch/arm/mach-omap2/omap_device.h #define OMAP_DEVICE_SUSPENDED BIT(0) BIT 3366 arch/arm/mach-omap2/omap_hwmod.c if (data->cfg->midlemodes & BIT(SYSC_IDLE_FORCE)) BIT 3368 arch/arm/mach-omap2/omap_hwmod.c if (data->cfg->midlemodes & BIT(SYSC_IDLE_NO)) BIT 3370 arch/arm/mach-omap2/omap_hwmod.c if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART)) BIT 3372 arch/arm/mach-omap2/omap_hwmod.c if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART_WKUP)) BIT 3375 arch/arm/mach-omap2/omap_hwmod.c if (data->cfg->sidlemodes & BIT(SYSC_IDLE_FORCE)) BIT 3377 arch/arm/mach-omap2/omap_hwmod.c if (data->cfg->sidlemodes & BIT(SYSC_IDLE_NO)) BIT 3379 arch/arm/mach-omap2/omap_hwmod.c if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART)) BIT 3381 arch/arm/mach-omap2/omap_hwmod.c if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART_WKUP)) BIT 40 arch/arm/mach-omap2/omap_hwmod_reset.c #define OMAP_RTC_STATUS_BUSY BIT(0) BIT 281 arch/arm/mach-omap2/pdata-quirks.c rx51_secure_update_aux_cr(BIT(6), 0); BIT 1053 arch/arm/mach-omap2/powerdomain.c if (pwrdm_states & BIT(req_state)) BIT 1065 arch/arm/mach-omap2/powerdomain.c while (!(pwrdm_states & BIT(new_pwrst))) { BIT 1080 arch/arm/mach-omap2/powerdomain.c while (!(pwrdm_states & BIT(new_pwrst))) { BIT 53 arch/arm/mach-omap2/powerdomain.h #define PWRDM_HAS_HDWR_SAR BIT(0) BIT 54 arch/arm/mach-omap2/powerdomain.h #define PWRDM_HAS_MPU_QUIRK BIT(1) BIT 55 arch/arm/mach-omap2/powerdomain.h #define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2) BIT 30 arch/arm/mach-omap2/prm.h #define PRM_HAS_IO_WAKEUP BIT(0) BIT 31 arch/arm/mach-omap2/prm.h #define PRM_HAS_VOLTAGE BIT(1) BIT 425 arch/arm/mach-omap2/soc.h #define OMAP3_HAS_L2CACHE BIT(0) BIT 426 arch/arm/mach-omap2/soc.h #define OMAP3_HAS_IVA BIT(1) BIT 427 arch/arm/mach-omap2/soc.h #define OMAP3_HAS_SGX BIT(2) BIT 428 arch/arm/mach-omap2/soc.h #define OMAP3_HAS_NEON BIT(3) BIT 429 arch/arm/mach-omap2/soc.h #define OMAP3_HAS_ISP BIT(4) BIT 430 arch/arm/mach-omap2/soc.h #define OMAP3_HAS_192MHZ_CLK BIT(5) BIT 431 arch/arm/mach-omap2/soc.h #define OMAP3_HAS_IO_WAKEUP BIT(6) BIT 432 arch/arm/mach-omap2/soc.h #define OMAP3_HAS_SDRC BIT(7) BIT 433 arch/arm/mach-omap2/soc.h #define OMAP3_HAS_IO_CHAIN_CTRL BIT(8) BIT 434 arch/arm/mach-omap2/soc.h #define OMAP4_HAS_PERF_SILICON BIT(9) BIT 12 arch/arm/mach-omap2/ti81xx-restart.c #define TI81XX_GLOBAL_RST_COLD BIT(1) BIT 51 arch/arm/mach-omap2/vc.c .sa = BIT(0), BIT 52 arch/arm/mach-omap2/vc.c .rav = BIT(1), BIT 53 arch/arm/mach-omap2/vc.c .rac = BIT(2), BIT 54 arch/arm/mach-omap2/vc.c .racen = BIT(3), BIT 55 arch/arm/mach-omap2/vc.c .cmd = BIT(4), BIT 65 arch/arm/mach-omap2/vc.c .sa = BIT(0), BIT 66 arch/arm/mach-omap2/vc.c .rav = BIT(2), BIT 67 arch/arm/mach-omap2/vc.c .rac = BIT(3), BIT 68 arch/arm/mach-omap2/vc.c .racen = BIT(4), BIT 69 arch/arm/mach-omap2/vc.c .cmd = BIT(1), BIT 59 arch/arm/mach-omap2/vc.h #define OMAP_VC_CHANNEL_DEFAULT BIT(0) BIT 60 arch/arm/mach-omap2/vc.h #define OMAP_VC_CHANNEL_CFG_MUTANT BIT(1) BIT 65 arch/arm/mach-prima2/rstc.c #define SIRFSOC_SYS_RST_BIT BIT(31) BIT 70 arch/arm/mach-pxa/irq.c icmr &= ~BIT(irq & 0x1f); BIT 80 arch/arm/mach-pxa/irq.c icmr |= BIT(irq & 0x1f); BIT 463 arch/arm/mach-pxa/lubbock.c lubbock_set_misc_wr(BIT(4), 0); BIT 465 arch/arm/mach-pxa/lubbock.c lubbock_set_misc_wr(BIT(4), BIT(4)); BIT 610 arch/arm/mach-pxa/lubbock.c led->mask = BIT(i); BIT 698 arch/arm/mach-pxa/mainstone.c led->mask = BIT(i); BIT 55 arch/arm/mach-pxa/pxa_cplds_irqs.c unsigned int bit = BIT(cplds_irq); BIT 65 arch/arm/mach-pxa/pxa_cplds_irqs.c unsigned int set, bit = BIT(cplds_irq); BIT 27 arch/arm/mach-qcom/platsmp.c #define PLL_CLAMP BIT(8) BIT 28 arch/arm/mach-qcom/platsmp.c #define CORE_PWRD_UP BIT(7) BIT 29 arch/arm/mach-qcom/platsmp.c #define COREPOR_RST BIT(5) BIT 30 arch/arm/mach-qcom/platsmp.c #define CORE_RST BIT(4) BIT 31 arch/arm/mach-qcom/platsmp.c #define L2DT_SLP BIT(3) BIT 32 arch/arm/mach-qcom/platsmp.c #define CLAMP BIT(0) BIT 39 arch/arm/mach-qcom/platsmp.c #define BHS_EN BIT(0) BIT 47 arch/arm/mach-rockchip/platsmp.c return !(val & BIT(pd)); BIT 66 arch/arm/mach-rockchip/platsmp.c u32 val = (on) ? 0 : BIT(pd); BIT 85 arch/arm/mach-rockchip/platsmp.c ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); BIT 65 arch/arm/mach-rockchip/pm.c #define GRF_SIDDQ BIT(13) BIT 117 arch/arm/mach-rockchip/pm.c mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) | BIT 118 arch/arm/mach-rockchip/pm.c BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) | BIT 119 arch/arm/mach-rockchip/pm.c BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) | BIT 120 arch/arm/mach-rockchip/pm.c BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) | BIT 121 arch/arm/mach-rockchip/pm.c BIT(PMU_SCU_EN); BIT 123 arch/arm/mach-rockchip/pm.c mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP); BIT 127 arch/arm/mach-rockchip/pm.c mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) | BIT 128 arch/arm/mach-rockchip/pm.c BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | BIT 129 arch/arm/mach-rockchip/pm.c BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); BIT 132 arch/arm/mach-rockchip/pm.c mode_set |= BIT(PMU_OSC_24M_DIS); BIT 134 arch/arm/mach-rockchip/pm.c mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) | BIT 135 arch/arm/mach-rockchip/pm.c BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA); BIT 158 arch/arm/mach-rockchip/pm.c mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN); BIT 45 arch/arm/mach-rockchip/pm.h #define SGRF_PCLK_WDT_GATE BIT(6) BIT 46 arch/arm/mach-rockchip/pm.h #define SGRF_PCLK_WDT_GATE_WRITE BIT(22) BIT 47 arch/arm/mach-rockchip/pm.h #define SGRF_FAST_BOOT_EN BIT(8) BIT 48 arch/arm/mach-rockchip/pm.h #define SGRF_FAST_BOOT_EN_WRITE BIT(24) BIT 51 arch/arm/mach-rockchip/pm.h #define SGRF_DAPDEVICEEN BIT(0) BIT 52 arch/arm/mach-rockchip/pm.h #define SGRF_DAPDEVICEEN_WRITE BIT(16) BIT 55 arch/arm/mach-rockchip/pm.h #define PMU_ARMINT_WAKEUP_EN BIT(0) BIT 56 arch/arm/mach-rockchip/pm.h #define PMU_GPIOINT_WAKEUP_EN BIT(3) BIT 102 arch/arm/mach-rpc/irq.c BIT(irq)); BIT 110 arch/arm/mach-rpc/irq.c BIT(irq - 8)); BIT 118 arch/arm/mach-rpc/irq.c BIT(irq - 16)); BIT 125 arch/arm/mach-rpc/irq.c BIT(irq - 64)); BIT 225 arch/arm/mach-s3c24xx/common.c s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; BIT 226 arch/arm/mach-s3c24xx/common.c s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); BIT 175 arch/arm/mach-s3c64xx/common.c s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; BIT 176 arch/arm/mach-s3c64xx/common.c s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); BIT 471 arch/arm/mach-sa1100/generic.c PWER |= BIT(gpio); BIT 473 arch/arm/mach-sa1100/generic.c PWER &= ~BIT(gpio); BIT 480 arch/arm/mach-sa1100/generic.c if (BIT(irq) != IC_RTCAlrm) BIT 42 arch/arm/mach-shmobile/platsmp-apmu.c #define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */ BIT 43 arch/arm/mach-shmobile/platsmp-apmu.c #define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */ BIT 44 arch/arm/mach-shmobile/platsmp-apmu.c #define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */ BIT 49 arch/arm/mach-shmobile/platsmp-apmu.c writel_relaxed(BIT(bit), p + WUPCR_OFFS); BIT 29 arch/arm/mach-shmobile/pm-rcar-gen2.c #define SBAR_BAREN BIT(4) /* SBAR is valid */ BIT 35 arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c #define REGULATOR_IRQ_MASK BIT(2) /* IRQ2, active low */ BIT 13 arch/arm/mach-socfpga/l2_cache.c #define A10_MPU_CTRL_L2_ECC_EN BIT(0) BIT 17 arch/arm/mach-socfpga/l2_cache.c #define A10_SYSMGR_ECC_INTMASK_CLR_L2 BIT(0) BIT 21 arch/arm/mach-socfpga/l2_cache.c #define A10_SYSMGR_MPU_CLEAR_L2_ECC (BIT(31) | BIT(15)) BIT 45 arch/arm/mach-socfpga/ocram.c #define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0)) BIT 46 arch/arm/mach-socfpga/ocram.c #define ALTR_A10_ECC_INITA BIT(16) BIT 49 arch/arm/mach-socfpga/ocram.c #define ALTR_A10_ECC_INITCOMPLETEA BIT(0) BIT 50 arch/arm/mach-socfpga/ocram.c #define ALTR_A10_ECC_INITCOMPLETEB BIT(8) BIT 53 arch/arm/mach-socfpga/ocram.c #define ALTR_A10_ECC_SERRINTEN BIT(0) BIT 56 arch/arm/mach-socfpga/ocram.c #define ALTR_A10_ECC_SERRPENA BIT(0) BIT 57 arch/arm/mach-socfpga/ocram.c #define ALTR_A10_ECC_DERRPENA BIT(8) BIT 63 arch/arm/mach-socfpga/ocram.c #define A10_SYSMGR_ECC_INTMASK_OCRAM BIT(1) BIT 39 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(n) BIT(n) BIT 41 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7 BIT(4) BIT 42 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15 BIT(0) BIT 44 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_CTRL_REG1_ACINACTM BIT(0) BIT 46 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_STATUS_STANDBYWFI(n) BIT(16 + (n)) BIT 47 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_STATUS_STANDBYWFIL2 BIT(0) BIT 49 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_RST_CTRL_DBG_SOC_RST BIT(24) BIT 50 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_RST_CTRL_ETM_RST(n) BIT(20 + (n)) BIT 52 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_RST_CTRL_DBG_RST(n) BIT(16 + (n)) BIT 54 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_RST_CTRL_H_RST BIT(12) BIT 55 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_RST_CTRL_L2_RST BIT(8) BIT 56 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_RST_CTRL_CX_RST(n) BIT(4 + (n)) BIT 57 arch/arm/mach-sunxi/mc_smp.c #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n) BIT 61 arch/arm/mach-sunxi/mc_smp.c #define PRCM_CPU_PO_RST_CTRL_CORE(n) BIT(n) BIT 65 arch/arm/mach-sunxi/mc_smp.c #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I BIT(0) BIT 66 arch/arm/mach-sunxi/mc_smp.c #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I BIT(4) BIT 67 arch/arm/mach-sunxi/mc_smp.c #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n) BIT 73 arch/arm/mach-sunxi/mc_smp.c #define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n) BIT(n) BIT 93 arch/arm/mach-sunxi/platsmp.c writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); BIT 97 arch/arm/mach-sunxi/platsmp.c writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); BIT 106 arch/arm/mach-sunxi/platsmp.c writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); BIT 114 arch/arm/mach-sunxi/platsmp.c writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); BIT 177 arch/arm/mach-sunxi/platsmp.c writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); BIT 181 arch/arm/mach-sunxi/platsmp.c writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); BIT 120 arch/arm/mach-tegra/pm.c BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id))); BIT 121 arch/arm/mach-tegra/pm.c *cpu_in_lp2 &= ~BIT(phy_cpu_id); BIT 135 arch/arm/mach-tegra/pm.c BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); BIT 136 arch/arm/mach-tegra/pm.c *cpu_in_lp2 |= BIT(phy_cpu_id); BIT 72 arch/arm/mach-vexpress/spc.c #define SYSCFG_START BIT(31) BIT 165 arch/arm/mach-vexpress/spc.c mask = BIT(cpu); BIT 45 arch/arm/mach-zx/zx296702-pm-domain.c tmp &= ~BIT(zpd->bit); BIT 50 arch/arm/mach-zx/zx296702-pm-domain.c tmp &= ~BIT(zpd->bit); BIT 51 arch/arm/mach-zx/zx296702-pm-domain.c writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_ISOEN); BIT 55 arch/arm/mach-zx/zx296702-pm-domain.c tmp &= ~BIT(zpd->bit); BIT 60 arch/arm/mach-zx/zx296702-pm-domain.c tmp &= ~BIT(zpd->bit); BIT 61 arch/arm/mach-zx/zx296702-pm-domain.c writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_PWRDN); BIT 63 arch/arm/mach-zx/zx296702-pm-domain.c tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit); BIT 81 arch/arm/mach-zx/zx296702-pm-domain.c tmp &= ~BIT(zpd->bit); BIT 84 arch/arm/mach-zx/zx296702-pm-domain.c tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit); BIT 93 arch/arm/mach-zx/zx296702-pm-domain.c tmp &= ~BIT(zpd->bit); BIT 94 arch/arm/mach-zx/zx296702-pm-domain.c writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_RSTEN); BIT 98 arch/arm/mach-zx/zx296702-pm-domain.c tmp &= ~BIT(zpd->bit); BIT 103 arch/arm/mach-zx/zx296702-pm-domain.c tmp &= ~BIT(zpd->bit); BIT 104 arch/arm/mach-zx/zx296702-pm-domain.c writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_CLKEN); BIT 20 arch/arm/mach-zynq/pm.c #define DDRC_CLOCKSTOP_MASK BIT(23) BIT 21 arch/arm/mach-zynq/pm.c #define DDRC_SELFREFRESH_MASK BIT(12) BIT 24 arch/arm/mm/cache-feroceon-l2.c #define L2_WRITETHROUGH_KIRKWOOD BIT(4) BIT 597 arch/arm/mm/cache-l2x0.c set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); BIT 603 arch/arm/mm/cache-l2x0.c set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); BIT 629 arch/arm/mm/cache-l2x0.c if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO)) BIT 632 arch/arm/mm/cache-l2x0.c if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3))) BIT 740 arch/arm/mm/cache-l2x0.c set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); BIT 751 arch/arm/mm/cache-l2x0.c set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); BIT 26 arch/arm/mm/cache-tauros2.c #define CCR_L2C_PREFETCH_DISABLE BIT(24) BIT 27 arch/arm/mm/cache-tauros2.c #define CCR_L2C_ECC_ENABLE BIT(23) BIT 28 arch/arm/mm/cache-tauros2.c #define CCR_L2C_WAY7_4_DISABLE BIT(21) BIT 29 arch/arm/mm/cache-tauros2.c #define CCR_L2C_BURST8_ENABLE BIT(20) BIT 20 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCC_BST BIT(20) /* UCWG burst read */ BIT 21 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCC_ACT BIT(19) /* Inst-Data separate */ BIT 22 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCC_WTG BIT(18) /* WT gathering on */ BIT 23 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCC_PRD BIT(17) /* enable pre-fetch */ BIT 24 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCC_ON BIT(0) /* enable cache */ BIT 42 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCOQM_CE BIT(15) /* notify completion */ BIT 49 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCOPPQSEF_FE BIT(1) BIT 50 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCOPPQSEF_OE BIT(0) BIT 52 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCOLPQS_EF BIT(2) BIT 53 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCOLPQS_EST BIT(1) BIT 54 arch/arm/mm/cache-uniphier.c #define UNIPHIER_SSCOLPQS_QST BIT(0) BIT 151 arch/arm/mm/proc-v7-bugs.c if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6))) BIT 157 arch/arm/mm/proc-v7-bugs.c if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0))) BIT 125 arch/arm/plat-omap/debug-leds.c led->mask = BIT(i); BIT 498 arch/arm/plat-samsung/gpio-samsung.c if (ourchip->bitmap_gpio_int & BIT(offset)) BIT 216 arch/arm64/crypto/ghash-ce-glue.c u64 carry = be64_to_cpu(k->a) & BIT(63) ? 1 : 0; BIT 92 arch/arm64/include/asm/arm_dsu_pmu.h write_sysreg_s(BIT(counter), CLUSTERPMCNTENCLR_EL1); BIT 98 arch/arm64/include/asm/arm_dsu_pmu.h write_sysreg_s(BIT(counter), CLUSTERPMCNTENSET_EL1); BIT 104 arch/arm64/include/asm/arm_dsu_pmu.h write_sysreg_s(BIT(counter), CLUSTERPMINTENSET_EL1); BIT 110 arch/arm64/include/asm/arm_dsu_pmu.h write_sysreg_s(BIT(counter), CLUSTERPMINTENCLR_EL1); BIT 113 arch/arm64/include/asm/cache.h if (!(ctr & BIT(CTR_IDC_SHIFT))) { BIT 118 arch/arm64/include/asm/cache.h ctr |= BIT(CTR_IDC_SHIFT); BIT 218 arch/arm64/include/asm/cpufeature.h #define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0)) BIT 219 arch/arm64/include/asm/cpufeature.h #define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1)) BIT 225 arch/arm64/include/asm/cpufeature.h #define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2)) BIT 240 arch/arm64/include/asm/cpufeature.h #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4)) BIT 242 arch/arm64/include/asm/cpufeature.h #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5)) BIT 223 arch/arm64/include/asm/kvm_emulate.h const unsigned long overlap = BIT(24) | BIT(21); BIT 255 arch/arm64/include/asm/memory.h #define __is_lm_address(addr) (!(((u64)addr) & BIT(vabits_actual - 1))) BIT 7 arch/arm64/include/asm/preempt.h #define PREEMPT_NEED_RESCHED BIT(32) BIT 217 arch/arm64/include/asm/sysreg.h #define SYS_PAR_EL1_F BIT(0) BIT 486 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_DSSBS (BIT(44)) BIT 487 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_ENIA (BIT(31)) BIT 488 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_ENIB (BIT(30)) BIT 489 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_ENDA (BIT(27)) BIT 490 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_EE (BIT(25)) BIT 491 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_IESB (BIT(21)) BIT 492 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_WXN (BIT(19)) BIT 493 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_ENDB (BIT(13)) BIT 494 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_I (BIT(12)) BIT 495 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_SA (BIT(3)) BIT 496 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_C (BIT(2)) BIT 497 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_A (BIT(1)) BIT 498 arch/arm64/include/asm/sysreg.h #define SCTLR_ELx_M (BIT(0)) BIT 504 arch/arm64/include/asm/sysreg.h #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ BIT 505 arch/arm64/include/asm/sysreg.h (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ BIT 506 arch/arm64/include/asm/sysreg.h (BIT(29))) BIT 515 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_UCI (BIT(26)) BIT 516 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_E0E (BIT(24)) BIT 517 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_SPAN (BIT(23)) BIT 518 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_NTWE (BIT(18)) BIT 519 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_NTWI (BIT(16)) BIT 520 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_UCT (BIT(15)) BIT 521 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_DZE (BIT(14)) BIT 522 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_UMA (BIT(9)) BIT 523 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_SED (BIT(8)) BIT 524 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_ITD (BIT(7)) BIT 525 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_CP15BEN (BIT(5)) BIT 526 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_SA0 (BIT(4)) BIT 528 arch/arm64/include/asm/sysreg.h #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ BIT 529 arch/arm64/include/asm/sysreg.h (BIT(29))) BIT 735 arch/arm64/include/asm/sysreg.h #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ BIT 736 arch/arm64/include/asm/sysreg.h #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ BIT 741 arch/arm64/include/asm/sysreg.h #define SYS_MPIDR_SAFE_VAL (BIT(31)) BIT 667 arch/arm64/kernel/cpu_errata.c bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT); BIT 785 arch/arm64/kernel/cpu_errata.c MIDR_FIXED(0x4, BIT(8)), BIT 924 arch/arm64/kernel/cpufeature.c return ctr & BIT(CTR_IDC_SHIFT); BIT 935 arch/arm64/kernel/cpufeature.c if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) BIT 949 arch/arm64/kernel/cpufeature.c return ctr & BIT(CTR_DIC_SHIFT); BIT 1185 arch/arm64/kernel/cpufeature.c if (instr & BIT(PSTATE_Imm_shift)) BIT 2044 arch/arm64/kernel/cpufeature.c elf_hwcap |= BIT(num); BIT 2051 arch/arm64/kernel/cpufeature.c return elf_hwcap & BIT(num); BIT 25 arch/arm64/kernel/insn.c #define AARCH64_INSN_SF_BIT BIT(31) BIT 26 arch/arm64/kernel/insn.c #define AARCH64_INSN_N_BIT BIT(22) BIT 27 arch/arm64/kernel/insn.c #define AARCH64_INSN_LSL_12 BIT(22) BIT 236 arch/arm64/kernel/insn.c mask = BIT(26) - 1; BIT 240 arch/arm64/kernel/insn.c mask = BIT(19) - 1; BIT 244 arch/arm64/kernel/insn.c mask = BIT(16) - 1; BIT 248 arch/arm64/kernel/insn.c mask = BIT(14) - 1; BIT 252 arch/arm64/kernel/insn.c mask = BIT(12) - 1; BIT 256 arch/arm64/kernel/insn.c mask = BIT(9) - 1; BIT 260 arch/arm64/kernel/insn.c mask = BIT(7) - 1; BIT 265 arch/arm64/kernel/insn.c mask = BIT(6) - 1; BIT 269 arch/arm64/kernel/insn.c mask = BIT(6) - 1; BIT 777 arch/arm64/kernel/insn.c imm_type = BIT(0); BIT 780 arch/arm64/kernel/insn.c imm_type = BIT(1); BIT 791 arch/arm64/kernel/insn.c imm_target = BIT(0); BIT 794 arch/arm64/kernel/insn.c imm_target = BIT(1); BIT 805 arch/arm64/kernel/insn.c imm_policy = BIT(0); BIT 873 arch/arm64/kernel/insn.c if (imm & ~(BIT(24) - 1)) BIT 1537 arch/arm64/kernel/insn.c u64 emask = BIT(tmp) - 1; BIT 1561 arch/arm64/kernel/insn.c imms &= BIT(6) - 1; BIT 124 arch/arm64/kernel/kaslr.c offset = BIT(VA_BITS_MIN - 3) + (seed & mask); BIT 205 arch/arm64/kernel/module.c imm_mask = (BIT(lsb + len) - 1) >> lsb; BIT 241 arch/arm64/kernel/module.c insn &= ~BIT(31); BIT 397 arch/arm64/kernel/perf_event.c return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx)); BIT 515 arch/arm64/kernel/perf_event.c write_sysreg(BIT(counter), pmcntenset_el0); BIT 523 arch/arm64/kernel/perf_event.c u32 counter_bits = BIT(ARMV8_IDX_TO_COUNTER(idx)); BIT 526 arch/arm64/kernel/perf_event.c counter_bits |= BIT(ARMV8_IDX_TO_COUNTER(idx - 1)); BIT 541 arch/arm64/kernel/perf_event.c write_sysreg(BIT(counter), pmcntenclr_el0); BIT 550 arch/arm64/kernel/perf_event.c u32 counter_bits = BIT(ARMV8_IDX_TO_COUNTER(idx)); BIT 553 arch/arm64/kernel/perf_event.c counter_bits |= BIT(ARMV8_IDX_TO_COUNTER(idx - 1)); BIT 568 arch/arm64/kernel/perf_event.c write_sysreg(BIT(counter), pmintenset_el1); BIT 580 arch/arm64/kernel/perf_event.c write_sysreg(BIT(counter), pmintenclr_el1); BIT 583 arch/arm64/kernel/perf_event.c write_sysreg(BIT(counter), pmovsclr_el0); BIT 475 arch/arm64/kernel/traps.c val &= ~BIT(CTR_DIC_SHIFT); BIT 102 arch/arm64/kvm/hyp/debug-sr.c if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) BIT 107 arch/arm64/kvm/hyp/debug-sr.c if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT))) BIT 32 arch/arm64/kvm/va_layout.c hyp_va_msb = idmap_addr & BIT(vabits_actual - 1); BIT 33 arch/arm64/kvm/va_layout.c hyp_va_msb ^= BIT(vabits_actual - 1); BIT 44 arch/arm64/kvm/va_layout.c va_mask = BIT(vabits_actual - 1) - 1; BIT 310 arch/arm64/mm/init.c const s64 linear_region_size = BIT(vabits_actual - 1); BIT 38 arch/arm64/mm/mmu.c #define NO_BLOCK_MAPPINGS BIT(0) BIT 39 arch/arm64/mm/mmu.c #define NO_CONT_MAPPINGS BIT(1) BIT 55 arch/c6x/include/asm/clock.h #define PLLPREDIV_EN BIT(15) BIT 59 arch/c6x/include/asm/clock.h #define PLLCTL_PLLEN BIT(0) BIT 60 arch/c6x/include/asm/clock.h #define PLLCTL_PLLPWRDN BIT(1) BIT 61 arch/c6x/include/asm/clock.h #define PLLCTL_PLLRST BIT(3) BIT 62 arch/c6x/include/asm/clock.h #define PLLCTL_PLLDIS BIT(4) BIT 63 arch/c6x/include/asm/clock.h #define PLLCTL_PLLENSRC BIT(5) BIT 64 arch/c6x/include/asm/clock.h #define PLLCTL_CLKMODE BIT(8) BIT 67 arch/c6x/include/asm/clock.h #define PLLCMD_GOSTAT BIT(0) BIT 70 arch/c6x/include/asm/clock.h #define PLLSTAT_GOSTAT BIT(0) BIT 73 arch/c6x/include/asm/clock.h #define PLLDIV_EN BIT(15) BIT 97 arch/c6x/include/asm/clock.h #define ALWAYS_ENABLED BIT(1) BIT 98 arch/c6x/include/asm/clock.h #define CLK_PLL BIT(2) /* PLL-derived clock */ BIT 99 arch/c6x/include/asm/clock.h #define PRE_PLL BIT(3) /* source is before PLL mult/div */ BIT 100 arch/c6x/include/asm/clock.h #define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */ BIT 101 arch/c6x/include/asm/clock.h #define FIXED_RATE_PLL BIT(5) /* fixed output rate PLL */ BIT 117 arch/c6x/include/asm/clock.h #define PLL_HAS_PRE BIT(0) BIT 118 arch/c6x/include/asm/clock.h #define PLL_HAS_MUL BIT(1) BIT 119 arch/c6x/include/asm/clock.h #define PLL_HAS_POST BIT(2) BIT 94 arch/csky/abiv1/inc/abi/ckmmu.h cpwcr("cpcr29", pgd | BIT(0)); BIT 99 arch/csky/abiv1/inc/abi/ckmmu.h return cprcr("cpcr29") & ~BIT(0); BIT 106 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<28, 15>", pgd | BIT(0)); BIT 108 arch/csky/abiv2/inc/abi/ckmmu.h mtcr("cr<29, 15>", pgd | BIT(0)); BIT 113 arch/csky/abiv2/inc/abi/ckmmu.h return mfcr("cr<29, 15>") & ~BIT(0); BIT 912 arch/csky/kernel/perf_event.c cpwcr(HPOFSR, ~BIT(hwc->idx) & cprcr(HPOFSR)); BIT 942 arch/csky/kernel/perf_event.c cpwcr(HPCR, BIT(31) | BIT(30) | BIT(1)); BIT 998 arch/csky/kernel/perf_event.c csky_pmu.hpcr = BIT(2); BIT 1000 arch/csky/kernel/perf_event.c csky_pmu.hpcr = BIT(3); BIT 1002 arch/csky/kernel/perf_event.c csky_pmu.hpcr = BIT(2) | BIT(3); BIT 1004 arch/csky/kernel/perf_event.c csky_pmu.hpcr |= BIT(1) | BIT(0); BIT 1018 arch/csky/kernel/perf_event.c cpwcr(HPCR, BIT(1)); BIT 1039 arch/csky/kernel/perf_event.c cpwcr(HPINTENR, BIT(idx) | cprcr(HPINTENR)); BIT 1040 arch/csky/kernel/perf_event.c cpwcr(HPCNTENR, BIT(idx) | cprcr(HPCNTENR)); BIT 1053 arch/csky/kernel/perf_event.c cpwcr(HPINTENR, ~BIT(idx) & cprcr(HPINTENR)); BIT 1054 arch/csky/kernel/perf_event.c cpwcr(HPCNTENR, ~BIT(idx) & cprcr(HPCNTENR)); BIT 1134 arch/csky/kernel/perf_event.c if (!(cprcr(HPOFSR) & BIT(idx))) BIT 48 arch/m68k/hp300/time.c #define CLKSR_INT1 BIT(0) BIT 145 arch/m68k/mac/misc.c #define RTC_FLG_READ BIT(7) BIT 146 arch/m68k/mac/misc.c #define RTC_FLG_WRITE_PROTECT BIT(7) BIT 395 arch/m68k/mac/via.c #define VIA_TIMER_1_INT BIT(6) BIT 98 arch/mips/ath25/ar2315.c ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq)); BIT 103 arch/mips/ath25/ar2315.c ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0); BIT 101 arch/mips/ath25/ar5312.c ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); BIT 107 arch/mips/ath25/ar5312.c ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); BIT 32 arch/mips/bmips/setup.c #define RELO_NORMAL_VEC BIT(18) BIT 35 arch/mips/bmips/setup.c #define BCM6328_TP1_DISABLED BIT(9) BIT 20 arch/mips/generic/board-sead3.c #define SEAD_CONFIG_GIC_PRESENT BIT(1) BIT 17 arch/mips/include/asm/dsemul.h #define BD_EMUFRAME_NONE ((int)BIT(31)) BIT 50 arch/mips/include/asm/ip32/crime.h #define MACE_VID_IN1_INT BIT(0) BIT 51 arch/mips/include/asm/ip32/crime.h #define MACE_VID_IN2_INT BIT(1) BIT 52 arch/mips/include/asm/ip32/crime.h #define MACE_VID_OUT_INT BIT(2) BIT 53 arch/mips/include/asm/ip32/crime.h #define MACE_ETHERNET_INT BIT(3) BIT 54 arch/mips/include/asm/ip32/crime.h #define MACE_SUPERIO_INT BIT(4) BIT 55 arch/mips/include/asm/ip32/crime.h #define MACE_MISC_INT BIT(5) BIT 56 arch/mips/include/asm/ip32/crime.h #define MACE_AUDIO_INT BIT(6) BIT 57 arch/mips/include/asm/ip32/crime.h #define MACE_PCI_BRIDGE_INT BIT(7) BIT 58 arch/mips/include/asm/ip32/crime.h #define MACEPCI_SCSI0_INT BIT(8) BIT 59 arch/mips/include/asm/ip32/crime.h #define MACEPCI_SCSI1_INT BIT(9) BIT 60 arch/mips/include/asm/ip32/crime.h #define MACEPCI_SLOT0_INT BIT(10) BIT 61 arch/mips/include/asm/ip32/crime.h #define MACEPCI_SLOT1_INT BIT(11) BIT 62 arch/mips/include/asm/ip32/crime.h #define MACEPCI_SLOT2_INT BIT(12) BIT 63 arch/mips/include/asm/ip32/crime.h #define MACEPCI_SHARED0_INT BIT(13) BIT 64 arch/mips/include/asm/ip32/crime.h #define MACEPCI_SHARED1_INT BIT(14) BIT 65 arch/mips/include/asm/ip32/crime.h #define MACEPCI_SHARED2_INT BIT(15) BIT 66 arch/mips/include/asm/ip32/crime.h #define CRIME_GBE0_INT BIT(16) BIT 67 arch/mips/include/asm/ip32/crime.h #define CRIME_GBE1_INT BIT(17) BIT 68 arch/mips/include/asm/ip32/crime.h #define CRIME_GBE2_INT BIT(18) BIT 69 arch/mips/include/asm/ip32/crime.h #define CRIME_GBE3_INT BIT(19) BIT 70 arch/mips/include/asm/ip32/crime.h #define CRIME_CPUERR_INT BIT(20) BIT 71 arch/mips/include/asm/ip32/crime.h #define CRIME_MEMERR_INT BIT(21) BIT 72 arch/mips/include/asm/ip32/crime.h #define CRIME_RE_EMPTY_E_INT BIT(22) BIT 73 arch/mips/include/asm/ip32/crime.h #define CRIME_RE_FULL_E_INT BIT(23) BIT 74 arch/mips/include/asm/ip32/crime.h #define CRIME_RE_IDLE_E_INT BIT(24) BIT 75 arch/mips/include/asm/ip32/crime.h #define CRIME_RE_EMPTY_L_INT BIT(25) BIT 76 arch/mips/include/asm/ip32/crime.h #define CRIME_RE_FULL_L_INT BIT(26) BIT 77 arch/mips/include/asm/ip32/crime.h #define CRIME_RE_IDLE_L_INT BIT(27) BIT 78 arch/mips/include/asm/ip32/crime.h #define CRIME_SOFT0_INT BIT(28) BIT 79 arch/mips/include/asm/ip32/crime.h #define CRIME_SOFT1_INT BIT(29) BIT 80 arch/mips/include/asm/ip32/crime.h #define CRIME_SOFT2_INT BIT(30) BIT 82 arch/mips/include/asm/ip32/crime.h #define CRIME_VICE_INT BIT(31) BIT 26 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_MASTER_ABORT BIT(31) BIT 27 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_TARGET_ABORT BIT(30) BIT 28 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29) BIT 29 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_RETRY_ERR BIT(28) BIT 30 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_ILLEGAL_CMD BIT(27) BIT 31 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_SYSTEM_ERR BIT(26) BIT 32 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_INTERRUPT_TEST BIT(25) BIT 33 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_PARITY_ERR BIT(24) BIT 34 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_OVERRUN BIT(23) BIT 35 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_RSVD BIT(22) BIT 36 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_MEMORY_ADDR BIT(21) BIT 37 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_CONFIG_ADDR BIT(20) BIT 38 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19) BIT 39 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18) BIT 40 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17) BIT 41 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16) BIT 42 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_SIG_TABORT BIT(4) BIT 47 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_FBB BIT(1) BIT 48 arch/mips/include/asm/ip32/mace.h #define MACEPCI_ERROR_66MHZ BIT(0) BIT 50 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_INT(x) BIT(x) BIT 52 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_SERR_ENA BIT(8) BIT 53 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_ARB_N6 BIT(9) BIT 54 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_PARITY_ERR BIT(10) BIT 55 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_MRMRA_ENA BIT(11) BIT 56 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_ARB_N3 BIT(12) BIT 57 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_ARB_N4 BIT(13) BIT 58 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_ARB_N5 BIT(14) BIT 59 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_PARK_LIU BIT(15) BIT 60 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_INV_INT(x) BIT(16+x) BIT 62 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_OVERRUN_INT BIT(24) BIT 63 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_PARITY_INT BIT(25) BIT 64 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_SERR_INT BIT(26) BIT 65 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_IT_INT BIT(27) BIT 66 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_RE_INT BIT(28) BIT 67 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_DPED_INT BIT(29) BIT 68 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_TAR_INT BIT(30) BIT 69 arch/mips/include/asm/ip32/mace.h #define MACEPCI_CONTROL_MAR_INT BIT(31) BIT 152 arch/mips/include/asm/ip32/mace.h #define MACEPAR_CONTEXT_LASTFLAG BIT(63) BIT 163 arch/mips/include/asm/ip32/mace.h #define MACEPAR_CTLSTAT_DIRECTION BIT(0) BIT 165 arch/mips/include/asm/ip32/mace.h #define MACEPAR_CTLSTAT_ENABLE BIT(1) BIT 167 arch/mips/include/asm/ip32/mace.h #define MACEPAR_CTLSTAT_RESET BIT(2) BIT 168 arch/mips/include/asm/ip32/mace.h #define MACEPAR_CTLSTAT_CTXB_VALID BIT(3) BIT 169 arch/mips/include/asm/ip32/mace.h #define MACEPAR_CTLSTAT_CTXA_VALID BIT(4) BIT 171 arch/mips/include/asm/ip32/mace.h #define MACEPAR_DIAG_CTXINUSE BIT(0) BIT 173 arch/mips/include/asm/ip32/mace.h #define MACEPAR_DIAG_DMACTIVE BIT(1) BIT 186 arch/mips/include/asm/ip32/mace.h #define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */ BIT 187 arch/mips/include/asm/ip32/mace.h #define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */ BIT 188 arch/mips/include/asm/ip32/mace.h #define MACEISA_NIC_DEASSERT BIT(2) BIT 189 arch/mips/include/asm/ip32/mace.h #define MACEISA_NIC_DATA BIT(3) BIT 190 arch/mips/include/asm/ip32/mace.h #define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */ BIT 191 arch/mips/include/asm/ip32/mace.h #define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */ BIT 192 arch/mips/include/asm/ip32/mace.h #define MACEISA_DP_RAM_ENABLE BIT(6) BIT 196 arch/mips/include/asm/ip32/mace.h #define MACEISA_AUDIO_SW_INT BIT(0) BIT 197 arch/mips/include/asm/ip32/mace.h #define MACEISA_AUDIO_SC_INT BIT(1) BIT 198 arch/mips/include/asm/ip32/mace.h #define MACEISA_AUDIO1_DMAT_INT BIT(2) BIT 199 arch/mips/include/asm/ip32/mace.h #define MACEISA_AUDIO1_OF_INT BIT(3) BIT 200 arch/mips/include/asm/ip32/mace.h #define MACEISA_AUDIO2_DMAT_INT BIT(4) BIT 201 arch/mips/include/asm/ip32/mace.h #define MACEISA_AUDIO2_MERR_INT BIT(5) BIT 202 arch/mips/include/asm/ip32/mace.h #define MACEISA_AUDIO3_DMAT_INT BIT(6) BIT 203 arch/mips/include/asm/ip32/mace.h #define MACEISA_AUDIO3_MERR_INT BIT(7) BIT 204 arch/mips/include/asm/ip32/mace.h #define MACEISA_RTC_INT BIT(8) BIT 205 arch/mips/include/asm/ip32/mace.h #define MACEISA_KEYB_INT BIT(9) BIT 206 arch/mips/include/asm/ip32/mace.h #define MACEISA_KEYB_POLL_INT BIT(10) BIT 207 arch/mips/include/asm/ip32/mace.h #define MACEISA_MOUSE_INT BIT(11) BIT 208 arch/mips/include/asm/ip32/mace.h #define MACEISA_MOUSE_POLL_INT BIT(12) BIT 209 arch/mips/include/asm/ip32/mace.h #define MACEISA_TIMER0_INT BIT(13) BIT 210 arch/mips/include/asm/ip32/mace.h #define MACEISA_TIMER1_INT BIT(14) BIT 211 arch/mips/include/asm/ip32/mace.h #define MACEISA_TIMER2_INT BIT(15) BIT 212 arch/mips/include/asm/ip32/mace.h #define MACEISA_PARALLEL_INT BIT(16) BIT 213 arch/mips/include/asm/ip32/mace.h #define MACEISA_PAR_CTXA_INT BIT(17) BIT 214 arch/mips/include/asm/ip32/mace.h #define MACEISA_PAR_CTXB_INT BIT(18) BIT 215 arch/mips/include/asm/ip32/mace.h #define MACEISA_PAR_MERR_INT BIT(19) BIT 216 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL1_INT BIT(20) BIT 217 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL1_TDMAT_INT BIT(21) BIT 218 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL1_TDMAPR_INT BIT(22) BIT 219 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL1_TDMAME_INT BIT(23) BIT 220 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL1_RDMAT_INT BIT(24) BIT 221 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL1_RDMAOR_INT BIT(25) BIT 222 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL2_INT BIT(26) BIT 223 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL2_TDMAT_INT BIT(27) BIT 224 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL2_TDMAPR_INT BIT(28) BIT 225 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL2_TDMAME_INT BIT(29) BIT 226 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL2_RDMAT_INT BIT(30) BIT 227 arch/mips/include/asm/ip32/mace.h #define MACEISA_SERIAL2_RDMAOR_INT BIT(31) BIT 253 arch/mips/include/asm/ip32/mace.h #define MACEI2C_RESET BIT(0) BIT 254 arch/mips/include/asm/ip32/mace.h #define MACEI2C_FAST BIT(1) BIT 255 arch/mips/include/asm/ip32/mace.h #define MACEI2C_DATA_OVERRIDE BIT(2) BIT 256 arch/mips/include/asm/ip32/mace.h #define MACEI2C_CLOCK_OVERRIDE BIT(3) BIT 257 arch/mips/include/asm/ip32/mace.h #define MACEI2C_DATA_STATUS BIT(4) BIT 258 arch/mips/include/asm/ip32/mace.h #define MACEI2C_CLOCK_STATUS BIT(5) BIT 171 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG1_SOFT_RST BIT(31) BIT 172 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG1_RX_RST BIT(19) BIT 173 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG1_TX_RST BIT(18) BIT 174 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG1_LOOPBACK BIT(8) BIT 175 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG1_RX_EN BIT(2) BIT 176 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG1_TX_EN BIT(0) BIT 179 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG2_IF_1000 BIT(9) BIT 180 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG2_IF_10_100 BIT(8) BIT 181 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5) BIT 182 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG2_LEN_CHECK BIT(4) BIT 183 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2) BIT 184 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MAC_CFG2_FDX BIT(0) BIT 198 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_INLINE_CHKSUM_ENG BIT(27) BIT 266 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16) BIT 267 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25) BIT 305 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) BIT 337 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) BIT 338 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) BIT 339 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) BIT 346 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) BIT 347 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) BIT 348 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) BIT 350 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) BIT 377 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) BIT 378 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) BIT 379 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) BIT 386 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) BIT 387 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) BIT 388 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) BIT 415 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) BIT 416 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) BIT 417 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) BIT 424 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) BIT 425 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) BIT 426 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) BIT 428 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) BIT 429 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) BIT 430 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) BIT 465 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) BIT 466 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) BIT 467 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) BIT 474 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) BIT 475 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) BIT 476 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) BIT 478 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5) BIT 479 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6) BIT 480 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7) BIT 483 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12) BIT 484 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13) BIT 485 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14) BIT 486 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15) BIT 487 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16) BIT 488 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17) BIT 489 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18) BIT 490 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19) BIT 492 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1) BIT 493 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_ETH_XMII_GIGE BIT(25) BIT 499 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) BIT 500 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) BIT 501 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) BIT 554 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) BIT 555 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_ETHSW BIT(12) BIT 556 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_TIMER4 BIT(10) BIT 557 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_TIMER3 BIT(9) BIT 558 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_TIMER2 BIT(8) BIT 559 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_DMA BIT(7) BIT 560 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_OHCI BIT(6) BIT 561 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_PERFC BIT(5) BIT 562 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_WDOG BIT(4) BIT 563 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_UART BIT(3) BIT 564 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_GPIO BIT(2) BIT 565 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_ERROR BIT(1) BIT 566 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define MISC_INT_TIMER BIT(0) BIT 568 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_EXTERNAL BIT(28) BIT 569 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_FULL_CHIP BIT(24) BIT 570 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_CPU_NMI BIT(21) BIT 571 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_CPU_COLD BIT(20) BIT 572 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_DMA BIT(19) BIT 573 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_SLIC BIT(18) BIT 574 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_STEREO BIT(17) BIT 575 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_DDR BIT(16) BIT 576 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_GE1_MAC BIT(13) BIT 577 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_GE1_PHY BIT(12) BIT 578 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) BIT 579 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_GE0_MAC BIT(9) BIT 580 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_GE0_PHY BIT(8) BIT 581 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_USB_OHCI_DLL BIT(6) BIT 582 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_USB_HOST BIT(5) BIT 583 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_USB_PHY BIT(4) BIT 584 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_PCI_BUS BIT(1) BIT 585 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_RESET_PCI_CORE BIT(0) BIT 587 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR7240_RESET_USB_HOST BIT(5) BIT 588 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR7240_RESET_OHCI_DLL BIT(3) BIT 590 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_RESET_GE1_MDIO BIT(23) BIT 591 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_RESET_GE0_MDIO BIT(22) BIT 592 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) BIT 593 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_RESET_PCIE_PHY BIT(7) BIT 594 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_RESET_PCIE BIT(6) BIT 595 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_RESET_USB_HOST BIT(5) BIT 596 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_RESET_USB_PHY BIT(4) BIT 597 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_RESET_USBSUS_OVERRIDE BIT(3) BIT 599 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_RESET_AMBA2WMAC BIT(22) BIT 600 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_RESET_USBSUS_OVERRIDE BIT(10) BIT 601 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_RESET_USB_HOST BIT(5) BIT 602 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_RESET_USB_PHY BIT(4) BIT 604 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_RESET_GE1_MDIO BIT(23) BIT 605 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_RESET_GE0_MDIO BIT(22) BIT 606 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_RESET_GE1_MAC BIT(13) BIT 607 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_RESET_WMAC BIT(11) BIT 608 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_RESET_GE0_MAC BIT(9) BIT 609 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_RESET_USB_HOST BIT(5) BIT 610 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_RESET_USB_PHY BIT(4) BIT 611 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) BIT 613 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_HOST BIT(31) BIT 614 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_SLIC BIT(30) BIT 615 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_HDMA BIT(29) BIT 616 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_EXTERNAL BIT(28) BIT 617 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_RTC BIT(27) BIT 618 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_PCIE_EP_INT BIT(26) BIT 619 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_CHKSUM_ACC BIT(25) BIT 620 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_FULL_CHIP BIT(24) BIT 621 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_GE1_MDIO BIT(23) BIT 622 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_GE0_MDIO BIT(22) BIT 623 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_CPU_NMI BIT(21) BIT 624 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_CPU_COLD BIT(20) BIT 625 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_HOST_RESET_INT BIT(19) BIT 626 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_PCIE_EP BIT(18) BIT 627 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_UART1 BIT(17) BIT 628 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_DDR BIT(16) BIT 629 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) BIT 630 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_NANDF BIT(14) BIT 631 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_GE1_MAC BIT(13) BIT 632 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) BIT 633 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_USB_PHY_ANALOG BIT(11) BIT 634 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_HOST_DMA_INT BIT(10) BIT 635 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_GE0_MAC BIT(9) BIT 636 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_ETH_SWITCH BIT(8) BIT 637 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_PCIE_PHY BIT(7) BIT 638 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_PCIE BIT(6) BIT 639 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_USB_HOST BIT(5) BIT 640 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_USB_PHY BIT(4) BIT 641 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) BIT 642 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_LUT BIT(2) BIT 643 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_MBOX BIT(1) BIT 644 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_RESET_I2S BIT(0) BIT 646 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_USB_EXT_PWR BIT(29) BIT 647 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_EXTERNAL BIT(28) BIT 648 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_RTC BIT(27) BIT 649 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_FULL_CHIP BIT(24) BIT 650 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_GE1_MDIO BIT(23) BIT 651 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_GE0_MDIO BIT(22) BIT 652 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_CPU_NMI BIT(21) BIT 653 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_CPU_COLD BIT(20) BIT 654 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_DDR BIT(16) BIT 655 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) BIT 656 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_GE1_MAC BIT(13) BIT 657 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) BIT 658 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_USB_PHY_ANALOG BIT(11) BIT 659 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_GE0_MAC BIT(9) BIT 660 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_ETH_SWITCH BIT(8) BIT 661 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_PCIE_PHY BIT(7) BIT 662 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_PCIE BIT(6) BIT 663 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_USB_HOST BIT(5) BIT 664 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_USB_PHY BIT(4) BIT 665 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) BIT 667 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_HOST BIT(31) BIT 668 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_SLIC BIT(30) BIT 669 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_HDMA BIT(29) BIT 670 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_EXTERNAL BIT(28) BIT 671 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_RTC BIT(27) BIT 672 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_PCIE_EP_INT BIT(26) BIT 673 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_CHKSUM_ACC BIT(25) BIT 674 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_FULL_CHIP BIT(24) BIT 675 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_GE1_MDIO BIT(23) BIT 676 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_GE0_MDIO BIT(22) BIT 677 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_CPU_NMI BIT(21) BIT 678 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_CPU_COLD BIT(20) BIT 679 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_HOST_RESET_INT BIT(19) BIT 680 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_PCIE_EP BIT(18) BIT 681 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_UART1 BIT(17) BIT 682 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_DDR BIT(16) BIT 683 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) BIT 684 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_NANDF BIT(14) BIT 685 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_GE1_MAC BIT(13) BIT 686 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_SGMII_ANALOG BIT(12) BIT 687 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_USB_PHY_ANALOG BIT(11) BIT 688 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_HOST_DMA_INT BIT(10) BIT 689 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_GE0_MAC BIT(9) BIT 690 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_SGMII BIT(8) BIT 691 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_PCIE_PHY BIT(7) BIT 692 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_PCIE BIT(6) BIT 693 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_USB_HOST BIT(5) BIT 694 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_USB_PHY BIT(4) BIT 695 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) BIT 696 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_LUT BIT(2) BIT 697 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_MBOX BIT(1) BIT 698 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_RESET_I2S BIT(0) BIT 700 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_EXTERNAL BIT(28) BIT 701 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_FULL_CHIP BIT(24) BIT 702 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_GE1_MDIO BIT(23) BIT 703 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_GE0_MDIO BIT(22) BIT 704 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_CPU_NMI BIT(21) BIT 705 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_CPU_COLD BIT(20) BIT 706 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_DMA BIT(19) BIT 707 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_DDR BIT(16) BIT 708 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_GE1_MAC BIT(13) BIT 709 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_SGMII_ANALOG BIT(12) BIT 710 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_USB_PHY_ANALOG BIT(11) BIT 711 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_GE0_MAC BIT(9) BIT 712 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_SGMII BIT(8) BIT 713 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_USB_HOST BIT(5) BIT 714 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_USB_PHY BIT(4) BIT 715 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_USBSUS_OVERRIDE BIT(3) BIT 716 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_SWITCH_ANALOG BIT(2) BIT 717 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_RESET_SWITCH BIT(0) BIT 719 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) BIT 720 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_BOOTSTRAP_EEPBUSY BIT(4) BIT 721 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) BIT 723 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) BIT 724 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) BIT 725 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) BIT 726 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) BIT 727 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) BIT 728 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) BIT 729 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) BIT 730 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) BIT 731 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) BIT 732 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_PCIE_RC BIT(6) BIT 733 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) BIT 734 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) BIT 735 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) BIT 736 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) BIT 737 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_BOOTSTRAP_DDR1 BIT(0) BIT 739 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) BIT 740 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) BIT 741 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) BIT 742 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) BIT 743 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) BIT 744 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_BOOTSTRAP_DDR1 BIT(0) BIT 746 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) BIT 748 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) BIT 750 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) BIT 751 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) BIT 752 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) BIT 753 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) BIT 754 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) BIT 755 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) BIT 756 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) BIT 757 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) BIT 758 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) BIT 768 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) BIT 769 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) BIT 770 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) BIT 771 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) BIT 772 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) BIT 773 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) BIT 774 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) BIT 775 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) BIT 776 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) BIT 786 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_WMAC_MISC BIT(0) BIT 787 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_WMAC_TX BIT(1) BIT 788 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) BIT 789 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_WMAC_RXHP BIT(3) BIT 790 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_PCIE_RC1 BIT(4) BIT 791 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) BIT 792 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) BIT 793 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) BIT 794 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) BIT 795 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_PCIE_RC2 BIT(12) BIT 796 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) BIT 797 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) BIT 798 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) BIT 799 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) BIT 800 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_USB1 BIT(24) BIT 801 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_EXT_INT_USB2 BIT(28) BIT 817 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_WMAC_MISC BIT(0) BIT 818 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_WMAC_TX BIT(1) BIT 819 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_WMAC_RXLP BIT(2) BIT 820 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_WMAC_RXHP BIT(3) BIT 821 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_PCIE_RC1 BIT(4) BIT 822 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) BIT 823 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) BIT 824 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) BIT 825 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) BIT 826 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_PCIE_RC2 BIT(12) BIT 827 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) BIT 828 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) BIT 829 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) BIT 830 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) BIT 831 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_USB1 BIT(24) BIT 832 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_EXT_INT_USB2 BIT(28) BIT 899 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ BIT 901 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ BIT 904 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ BIT 905 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ BIT 906 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) BIT 1003 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) BIT 1021 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) BIT 1025 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) BIT 1026 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) BIT 1027 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) BIT 1028 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) BIT 1029 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_GPIO_FUNC_UART_EN BIT(8) BIT 1030 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) BIT 1031 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) BIT 1033 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) BIT 1034 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_SPI_EN BIT(18) BIT 1035 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) BIT 1036 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) BIT 1037 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) BIT 1038 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) BIT 1039 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) BIT 1040 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) BIT 1041 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) BIT 1042 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) BIT 1043 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) BIT 1044 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) BIT 1045 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) BIT 1046 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) BIT 1047 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) BIT 1048 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_UART_EN BIT(1) BIT 1049 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) BIT 1051 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) BIT 1052 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) BIT 1053 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) BIT 1054 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) BIT 1055 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_GPIO_FUNC_I2S1_EN BIT(18) BIT 1056 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_GPIO_FUNC_I2S0_EN BIT(17) BIT 1057 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_GPIO_FUNC_SLIC_EN BIT(16) BIT 1058 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) BIT 1059 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_GPIO_FUNC_UART_EN BIT(8) BIT 1060 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) BIT 1062 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) BIT 1063 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) BIT 1064 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) BIT 1065 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) BIT 1066 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_I2SO_EN BIT(26) BIT 1067 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) BIT 1068 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) BIT 1069 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) BIT 1070 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_SPI_EN BIT(18) BIT 1071 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) BIT 1072 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) BIT 1073 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) BIT 1074 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) BIT 1075 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) BIT 1076 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) BIT 1077 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) BIT 1078 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) BIT 1079 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_UART_EN BIT(1) BIT 1080 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) BIT 1082 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) BIT 1083 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) BIT 1084 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) BIT 1085 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) BIT 1086 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) BIT 1087 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) BIT 1088 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) BIT 1089 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) BIT 1090 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) BIT 1102 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9) BIT 1103 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8) BIT 1104 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7) BIT 1105 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6) BIT 1106 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5) BIT 1107 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4) BIT 1108 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3) BIT 1109 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1) BIT 1193 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_RGMII_GE0 BIT(0) BIT 1194 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_MII_GE0 BIT(1) BIT 1195 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_GMII_GE0 BIT(2) BIT 1196 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) BIT 1197 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) BIT 1198 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) BIT 1199 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) BIT 1200 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) BIT 1201 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_RMII_GE0 BIT(9) BIT 1203 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) BIT 1210 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) BIT 1211 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_MII_GMAC0 BIT(1) BIT 1212 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) BIT 1213 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) BIT 1214 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) BIT 1215 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) BIT 1216 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) BIT 1217 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) BIT 1218 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) BIT 1219 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) BIT 1220 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) BIT 1221 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) BIT 1222 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) BIT 1223 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_RXD_DELAY BIT(14) BIT 1226 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define AR934X_ETH_CFG_RDV_DELAY BIT(16) BIT 1235 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) BIT 1236 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) BIT 1237 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) BIT 1238 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) BIT 1247 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_RGMII_EN BIT(0) BIT 1248 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_MII_GE0 BIT(1) BIT 1249 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_GMII_GE0 BIT(2) BIT 1250 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3) BIT 1251 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4) BIT 1252 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5) BIT 1253 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_GE0_SGMII BIT(6) BIT 1254 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_RMII_GE0 BIT(10) BIT 1255 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11) BIT 1256 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12) BIT 1259 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_ETH_CFG_RDV_DELAY BIT(16) BIT 1267 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) BIT 1281 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_ETH_CFG_RGMII_EN BIT(0) BIT 1282 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_ETH_CFG_GE0_SGMII BIT(6) BIT 1283 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) BIT 1284 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) BIT 1285 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) BIT 1286 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) BIT 1287 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) BIT 1294 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_RESET_RX_CLK_N BIT(0) BIT 1295 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_RESET_TX_CLK_N BIT(1) BIT 1296 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_RESET_RX_125M_N BIT(2) BIT 1297 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_RESET_TX_125M_N BIT(3) BIT 1298 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4) BIT 1304 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_SERDES_PLL_BW BIT(8) BIT 1305 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) BIT 1306 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) BIT 1307 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) BIT 1308 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) BIT 1309 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) BIT 1315 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12) BIT 1316 arch/mips/include/asm/mach-ath79/ar71xx_regs.h #define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15) BIT 21 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_DATA_RX_CSR BIT(8) BIT 22 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_DATA_TX_CSR BIT(9) BIT 36 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_CS_DMA_EN BIT(6) BIT 37 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_CS_TX_READY_ORIDE BIT(7) BIT 38 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_CS_RX_READY_ORIDE BIT(8) BIT 39 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_CS_TX_READY BIT(9) BIT 40 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_CS_RX_BREAK BIT(10) BIT 41 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_CS_TX_BREAK BIT(11) BIT 42 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_CS_HOST_INT BIT(12) BIT 43 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_CS_HOST_INT_EN BIT(13) BIT 44 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_CS_TX_BUSY BIT(14) BIT 45 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_CS_RX_BUSY BIT(15) BIT 52 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_INT_RX_VALID BIT(0) BIT 53 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_INT_TX_READY BIT(1) BIT 54 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_INT_RX_FRAMING_ERR BIT(2) BIT 55 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_INT_RX_OFLOW_ERR BIT(3) BIT 56 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_INT_TX_OFLOW_ERR BIT(4) BIT 57 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_INT_RX_PARITY_ERR BIT(5) BIT 58 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_INT_RX_BREAK_ON BIT(6) BIT 59 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_INT_RX_BREAK_OFF BIT(7) BIT 60 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_INT_RX_FULL BIT(8) BIT 61 arch/mips/include/asm/mach-ath79/ar933x_uart.h #define AR933X_UART_INT_TX_EMPTY BIT(9) BIT 1429 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h #define OTP_6328_REG3_TP1_DISABLED BIT(9) BIT 28 arch/mips/include/asm/mach-jz4740/timer.h #define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10) BIT 29 arch/mips/include/asm/mach-jz4740/timer.h #define JZ_TIMER_IRQ_FULL(x) BIT(x) BIT 31 arch/mips/include/asm/mach-jz4740/timer.h #define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9) BIT 32 arch/mips/include/asm/mach-jz4740/timer.h #define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8) BIT 33 arch/mips/include/asm/mach-jz4740/timer.h #define JZ_TIMER_CTRL_PWM_ENABLE BIT(7) BIT 45 arch/mips/include/asm/mach-jz4740/timer.h #define JZ_TIMER_CTRL_SRC_EXT BIT(2) BIT 46 arch/mips/include/asm/mach-jz4740/timer.h #define JZ_TIMER_CTRL_SRC_RTC BIT(1) BIT 47 arch/mips/include/asm/mach-jz4740/timer.h #define JZ_TIMER_CTRL_SRC_PCLK BIT(0) BIT 57 arch/mips/include/asm/mach-jz4740/timer.h writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); BIT 62 arch/mips/include/asm/mach-jz4740/timer.h writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); BIT 67 arch/mips/include/asm/mach-jz4740/timer.h return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer); BIT 72 arch/mips/include/asm/mach-jz4740/timer.h writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET); BIT 77 arch/mips/include/asm/mach-jz4740/timer.h writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR); BIT 101 arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h #define PMU_PPE BIT(13) BIT 13 arch/mips/include/asm/mach-lantiq/xway/xway_dma.h #define LTQ_DMA_OWN BIT(31) /* owner bit */ BIT 14 arch/mips/include/asm/mach-lantiq/xway/xway_dma.h #define LTQ_DMA_C BIT(30) /* complete bit */ BIT 15 arch/mips/include/asm/mach-lantiq/xway/xway_dma.h #define LTQ_DMA_SOP BIT(29) /* start of packet */ BIT 16 arch/mips/include/asm/mach-lantiq/xway/xway_dma.h #define LTQ_DMA_EOP BIT(28) /* end of packet */ BIT 19 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_DC_EN BIT(31) BIT 20 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_DC_RST BIT(30) BIT 21 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_CPU_EN BIT(25) BIT 22 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_CPU_RST BIT(24) BIT 23 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_DDR_EN BIT(19) BIT 24 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_DDR_RST BIT(18) BIT 25 arch/mips/include/asm/mach-loongson32/regs-clk.h #define RST_DC_EN BIT(5) BIT 26 arch/mips/include/asm/mach-loongson32/regs-clk.h #define RST_DC BIT(4) BIT 27 arch/mips/include/asm/mach-loongson32/regs-clk.h #define RST_DDR_EN BIT(3) BIT 28 arch/mips/include/asm/mach-loongson32/regs-clk.h #define RST_DDR BIT(2) BIT 29 arch/mips/include/asm/mach-loongson32/regs-clk.h #define RST_CPU_EN BIT(1) BIT 30 arch/mips/include/asm/mach-loongson32/regs-clk.h #define RST_CPU BIT(0) BIT 50 arch/mips/include/asm/mach-loongson32/regs-clk.h #define PLL_VALID BIT(31) BIT 56 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_DC_EN BIT(31) BIT 58 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_CAM_EN BIT(23) BIT 60 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_CPU_EN BIT(15) BIT 62 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_DC_SEL_EN BIT(5) BIT 63 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_DC_SEL BIT(4) BIT 64 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_CAM_SEL_EN BIT(3) BIT 65 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_CAM_SEL BIT(2) BIT 66 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_CPU_SEL_EN BIT(1) BIT 67 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_CPU_SEL BIT(0) BIT 19 arch/mips/include/asm/mach-loongson32/regs-mux.h #define UART0_USE_PWM23 BIT(28) BIT 20 arch/mips/include/asm/mach-loongson32/regs-mux.h #define UART0_USE_PWM01 BIT(27) BIT 21 arch/mips/include/asm/mach-loongson32/regs-mux.h #define UART1_USE_LCD0_5_6_11 BIT(26) BIT 22 arch/mips/include/asm/mach-loongson32/regs-mux.h #define I2C2_USE_CAN1 BIT(25) BIT 23 arch/mips/include/asm/mach-loongson32/regs-mux.h #define I2C1_USE_CAN0 BIT(24) BIT 24 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND3_USE_UART5 BIT(23) BIT 25 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND3_USE_UART4 BIT(22) BIT 26 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND3_USE_UART1_DAT BIT(21) BIT 27 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND3_USE_UART1_CTS BIT(20) BIT 28 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND3_USE_PWM23 BIT(19) BIT 29 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND3_USE_PWM01 BIT(18) BIT 30 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND2_USE_UART5 BIT(17) BIT 31 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND2_USE_UART4 BIT(16) BIT 32 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND2_USE_UART1_DAT BIT(15) BIT 33 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND2_USE_UART1_CTS BIT(14) BIT 34 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND2_USE_PWM23 BIT(13) BIT 35 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND2_USE_PWM01 BIT(12) BIT 36 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND1_USE_UART5 BIT(11) BIT 37 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND1_USE_UART4 BIT(10) BIT 38 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND1_USE_UART1_DAT BIT(9) BIT 39 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND1_USE_UART1_CTS BIT(8) BIT 40 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND1_USE_PWM23 BIT(7) BIT 41 arch/mips/include/asm/mach-loongson32/regs-mux.h #define NAND1_USE_PWM01 BIT(6) BIT 42 arch/mips/include/asm/mach-loongson32/regs-mux.h #define GMAC1_USE_UART1 BIT(4) BIT 43 arch/mips/include/asm/mach-loongson32/regs-mux.h #define GMAC1_USE_UART0 BIT(3) BIT 44 arch/mips/include/asm/mach-loongson32/regs-mux.h #define LCD_USE_UART0_DAT BIT(2) BIT 45 arch/mips/include/asm/mach-loongson32/regs-mux.h #define LCD_USE_UART15 BIT(1) BIT 46 arch/mips/include/asm/mach-loongson32/regs-mux.h #define LCD_USE_UART0 BIT(0) BIT 49 arch/mips/include/asm/mach-loongson32/regs-mux.h #define USB_RESET BIT(31) BIT 50 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SPI1_CS_USE_PWM01 BIT(24) BIT 51 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SPI1_USE_CAN BIT(23) BIT 52 arch/mips/include/asm/mach-loongson32/regs-mux.h #define DISABLE_DDR_CONFSPACE BIT(20) BIT 53 arch/mips/include/asm/mach-loongson32/regs-mux.h #define DDR32TO16EN BIT(16) BIT 54 arch/mips/include/asm/mach-loongson32/regs-mux.h #define GMAC1_SHUT BIT(13) BIT 55 arch/mips/include/asm/mach-loongson32/regs-mux.h #define GMAC0_SHUT BIT(12) BIT 56 arch/mips/include/asm/mach-loongson32/regs-mux.h #define USB_SHUT BIT(11) BIT 57 arch/mips/include/asm/mach-loongson32/regs-mux.h #define UART1_3_USE_CAN1 BIT(5) BIT 58 arch/mips/include/asm/mach-loongson32/regs-mux.h #define UART1_2_USE_CAN0 BIT(4) BIT 59 arch/mips/include/asm/mach-loongson32/regs-mux.h #define GMAC1_USE_TXCLK BIT(3) BIT 60 arch/mips/include/asm/mach-loongson32/regs-mux.h #define GMAC0_USE_TXCLK BIT(2) BIT 61 arch/mips/include/asm/mach-loongson32/regs-mux.h #define GMAC1_USE_PWM23 BIT(1) BIT 62 arch/mips/include/asm/mach-loongson32/regs-mux.h #define GMAC0_USE_PWM01 BIT(0) BIT 69 arch/mips/include/asm/mach-loongson32/regs-mux.h #define ADC_SHUT BIT(25) BIT 70 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SDIO_SHUT BIT(24) BIT 71 arch/mips/include/asm/mach-loongson32/regs-mux.h #define DMA2_SHUT BIT(23) BIT 72 arch/mips/include/asm/mach-loongson32/regs-mux.h #define DMA1_SHUT BIT(22) BIT 73 arch/mips/include/asm/mach-loongson32/regs-mux.h #define DMA0_SHUT BIT(21) BIT 74 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SPI1_SHUT BIT(20) BIT 75 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SPI0_SHUT BIT(19) BIT 76 arch/mips/include/asm/mach-loongson32/regs-mux.h #define I2C2_SHUT BIT(18) BIT 77 arch/mips/include/asm/mach-loongson32/regs-mux.h #define I2C1_SHUT BIT(17) BIT 78 arch/mips/include/asm/mach-loongson32/regs-mux.h #define I2C0_SHUT BIT(16) BIT 79 arch/mips/include/asm/mach-loongson32/regs-mux.h #define AC97_SHUT BIT(15) BIT 80 arch/mips/include/asm/mach-loongson32/regs-mux.h #define I2S_SHUT BIT(14) BIT 81 arch/mips/include/asm/mach-loongson32/regs-mux.h #define UART3_SHUT BIT(13) BIT 82 arch/mips/include/asm/mach-loongson32/regs-mux.h #define UART2_SHUT BIT(12) BIT 83 arch/mips/include/asm/mach-loongson32/regs-mux.h #define UART1_SHUT BIT(11) BIT 84 arch/mips/include/asm/mach-loongson32/regs-mux.h #define UART0_SHUT BIT(10) BIT 85 arch/mips/include/asm/mach-loongson32/regs-mux.h #define CAN1_SHUT BIT(9) BIT 86 arch/mips/include/asm/mach-loongson32/regs-mux.h #define CAN0_SHUT BIT(8) BIT 87 arch/mips/include/asm/mach-loongson32/regs-mux.h #define ECC_SHUT BIT(7) BIT 88 arch/mips/include/asm/mach-loongson32/regs-mux.h #define GMAC_SHUT BIT(6) BIT 89 arch/mips/include/asm/mach-loongson32/regs-mux.h #define USBHOST_SHUT BIT(5) BIT 90 arch/mips/include/asm/mach-loongson32/regs-mux.h #define USBOTG_SHUT BIT(4) BIT 91 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SDRAM_SHUT BIT(3) BIT 92 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SRAM_SHUT BIT(2) BIT 93 arch/mips/include/asm/mach-loongson32/regs-mux.h #define CAM_SHUT BIT(1) BIT 94 arch/mips/include/asm/mach-loongson32/regs-mux.h #define LCD_SHUT BIT(0) BIT 100 arch/mips/include/asm/mach-loongson32/regs-mux.h #define USBHOST_RSTN BIT(31) BIT 102 arch/mips/include/asm/mach-loongson32/regs-mux.h #define AC97_EN BIT(25) BIT 104 arch/mips/include/asm/mach-loongson32/regs-mux.h #define ADC_DMA_EN BIT(22) BIT 105 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SDIO_USE_SPI1 BIT(17) BIT 106 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SDIO_USE_SPI0 BIT(16) BIT 18 arch/mips/include/asm/mach-loongson32/regs-pwm.h #define CNT_RST BIT(7) BIT 19 arch/mips/include/asm/mach-loongson32/regs-pwm.h #define INT_SR BIT(6) BIT 20 arch/mips/include/asm/mach-loongson32/regs-pwm.h #define INT_EN BIT(5) BIT 21 arch/mips/include/asm/mach-loongson32/regs-pwm.h #define PWM_SINGLE BIT(4) BIT 22 arch/mips/include/asm/mach-loongson32/regs-pwm.h #define PWM_OE BIT(3) BIT 23 arch/mips/include/asm/mach-loongson32/regs-pwm.h #define CNT_EN BIT(0) BIT 16 arch/mips/include/asm/mach-loongson32/regs-rtc.h #define RTC_EXTCLK_OK (BIT(5) | BIT(8)) BIT 17 arch/mips/include/asm/mach-loongson32/regs-rtc.h #define RTC_EXTCLK_EN BIT(8) BIT 31 arch/mips/include/asm/mach-ralink/mt7620.h #define SYSCFG0_XTAL_FREQ_SEL BIT(6) BIT 39 arch/mips/include/asm/mach-ralink/mt7620.h #define CLKCFG0_PERI_CLK_SEL BIT(4) BIT 57 arch/mips/include/asm/mach-ralink/mt7620.h #define CPLL_CFG0_SW_CFG BIT(31) BIT 60 arch/mips/include/asm/mach-ralink/mt7620.h #define CPLL_CFG0_LC_CURFCK BIT(15) BIT 61 arch/mips/include/asm/mach-ralink/mt7620.h #define CPLL_CFG0_BYPASS_REF_CLK BIT(14) BIT 65 arch/mips/include/asm/mach-ralink/mt7620.h #define CPLL_CFG1_CPU_AUX1 BIT(25) BIT 66 arch/mips/include/asm/mach-ralink/mt7620.h #define CPLL_CFG1_CPU_AUX0 BIT(24) BIT 36 arch/mips/include/asm/mach-ralink/rt288x.h #define RT2880_GPIO_MODE_I2C BIT(0) BIT 37 arch/mips/include/asm/mach-ralink/rt288x.h #define RT2880_GPIO_MODE_UART0 BIT(1) BIT 38 arch/mips/include/asm/mach-ralink/rt288x.h #define RT2880_GPIO_MODE_SPI BIT(2) BIT 39 arch/mips/include/asm/mach-ralink/rt288x.h #define RT2880_GPIO_MODE_UART1 BIT(3) BIT 40 arch/mips/include/asm/mach-ralink/rt288x.h #define RT2880_GPIO_MODE_JTAG BIT(4) BIT 41 arch/mips/include/asm/mach-ralink/rt288x.h #define RT2880_GPIO_MODE_MDIO BIT(5) BIT 42 arch/mips/include/asm/mach-ralink/rt288x.h #define RT2880_GPIO_MODE_SDRAM BIT(6) BIT 43 arch/mips/include/asm/mach-ralink/rt288x.h #define RT2880_GPIO_MODE_PCI BIT(7) BIT 45 arch/mips/include/asm/mach-ralink/rt288x.h #define CLKCFG_SRAM_CS_N_WDT BIT(9) BIT 147 arch/mips/include/asm/mach-ralink/rt305x.h #define RT3352_CLKCFG0_XTAL_SEL BIT(20) BIT 148 arch/mips/include/asm/mach-ralink/rt305x.h #define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) BIT 149 arch/mips/include/asm/mach-ralink/rt305x.h #define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) BIT 150 arch/mips/include/asm/mach-ralink/rt305x.h #define RT3352_RSTCTRL_UHST BIT(22) BIT 151 arch/mips/include/asm/mach-ralink/rt305x.h #define RT3352_RSTCTRL_UDEV BIT(25) BIT 152 arch/mips/include/asm/mach-ralink/rt305x.h #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) BIT 93 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) BIT 101 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10) BIT 102 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8) BIT 103 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7) BIT 104 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_SYSCFG1_PCI_66M_MODE BIT(6) BIT 105 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2) BIT 107 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21) BIT 108 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20) BIT 109 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19) BIT 110 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18) BIT 198 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27) BIT 199 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_FLASH BIT(26) BIT 200 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_UDEV BIT(25) BIT 201 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_PCI BIT(24) BIT 202 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_PCIE BIT(23) BIT 203 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_UHST BIT(22) BIT 204 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_FE BIT(21) BIT 205 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_WLAN BIT(20) BIT 206 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_UART1 BIT(29) BIT 207 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_SPI BIT(18) BIT 208 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_I2S BIT(17) BIT 209 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_I2C BIT(16) BIT 210 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_NAND BIT(15) BIT 211 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_DMA BIT(14) BIT 212 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_PIO BIT(13) BIT 213 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_UART BIT(12) BIT 214 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_PCM BIT(11) BIT 215 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_MC BIT(10) BIT 216 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_INTC BIT(9) BIT 217 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_TIMER BIT(8) BIT 218 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_RSTCTRL_SYS BIT(0) BIT 220 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_SYSCTL BIT(0) BIT 221 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_TIMER0 BIT(1) BIT 222 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_TIMER1 BIT(2) BIT 223 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_IA BIT(3) BIT 224 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_PCM BIT(4) BIT 225 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_UART0 BIT(5) BIT 226 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_PIO BIT(6) BIT 227 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_DMA BIT(7) BIT 228 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_NAND BIT(8) BIT 229 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_PERFC BIT(9) BIT 230 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_I2S BIT(10) BIT 231 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_UART1 BIT(12) BIT 232 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_UHST BIT(18) BIT 233 arch/mips/include/asm/mach-ralink/rt3883.h #define RT3883_INTC_INT_UDEV BIT(19) BIT 166 arch/mips/include/asm/mips-cm.h #define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1) BIT 167 arch/mips/include/asm/mips-cm.h #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0) BIT 188 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN BIT(0) BIT 193 arch/mips/include/asm/mips-cm.h #define CM_GCR_GIC_BASE_GICEN BIT(0) BIT 198 arch/mips/include/asm/mips-cm.h #define CM_GCR_CPC_BASE_CPCEN BIT(0) BIT 214 arch/mips/include/asm/mips-cm.h #define CM_GCR_REGn_MASK_CCAOVREN BIT(4) BIT 215 arch/mips/include/asm/mips-cm.h #define CM_GCR_REGn_MASK_DROPL2 BIT(2) BIT 224 arch/mips/include/asm/mips-cm.h #define CM_GCR_GIC_STATUS_EX BIT(0) BIT 228 arch/mips/include/asm/mips-cm.h #define CM_GCR_CPC_STATUS_EX BIT(0) BIT 232 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_CONFIG_BYPASS BIT(20) BIT 244 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_PFT_CONTROL_PFTEN BIT(8) BIT 249 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8) BIT 254 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2SM_COP_PRESENT BIT(31) BIT 261 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2SM_COP_RUNNING BIT(5) BIT 288 arch/mips/include/asm/mips-cm.h #define CM3_GCR_Cx_COHERENCE_COHEN BIT(0) BIT 298 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_OTHER_CLUSTER_EN BIT(31) /* CM >= 3.5 */ BIT 299 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_OTHER_GIC_EN BIT(30) /* CM >= 3.5 */ BIT 321 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET BIT(31) BIT 322 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_RESET_EXT_BASE_UEB BIT(30) BIT 325 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0) BIT 97 arch/mips/include/asm/mips-cpc.h #define CPC_PWRUP_CTL_CM_PWRUP BIT(0) BIT 104 arch/mips/include/asm/mips-cpc.h #define CPC_SYS_CONFIG_BE_IMMEDIATE BIT(2) BIT 105 arch/mips/include/asm/mips-cpc.h #define CPC_SYS_CONFIG_BE_STATUS BIT(1) BIT 106 arch/mips/include/asm/mips-cpc.h #define CPC_SYS_CONFIG_BE BIT(0) BIT 118 arch/mips/include/asm/mips-cpc.h #define CPC_Cx_STAT_CONF_PWRUPE BIT(23) BIT 131 arch/mips/include/asm/mips-cpc.h #define CPC_Cx_STAT_CONF_CLKGAT_IMPL BIT(17) BIT 132 arch/mips/include/asm/mips-cpc.h #define CPC_Cx_STAT_CONF_PWRDN_IMPL BIT(16) BIT 133 arch/mips/include/asm/mips-cpc.h #define CPC_Cx_STAT_CONF_EJTAG_PROBE BIT(15) BIT 118 arch/mips/include/asm/mips-gic.h __raw_writeq(BIT(intr % 64), addr); \ BIT 121 arch/mips/include/asm/mips-gic.h __raw_writel(BIT(intr % 32), addr); \ BIT 143 arch/mips/include/asm/mips-gic.h _val &= ~BIT(intr % 32); \ BIT 165 arch/mips/include/asm/mips-gic.h #define GIC_CONFIG_COUNTSTOP BIT(28) BIT 194 arch/mips/include/asm/mips-gic.h #define GIC_WEDGE_RW BIT(31) BIT 211 arch/mips/include/asm/mips-gic.h #define GIC_MAP_PIN_MAP_TO_PIN BIT(31) BIT 212 arch/mips/include/asm/mips-gic.h #define GIC_MAP_PIN_MAP_TO_NMI BIT(30) BIT 220 arch/mips/include/asm/mips-gic.h #define GIC_VX_CTL_FDC_ROUTABLE BIT(4) BIT 221 arch/mips/include/asm/mips-gic.h #define GIC_VX_CTL_SWINT_ROUTABLE BIT(3) BIT 222 arch/mips/include/asm/mips-gic.h #define GIC_VX_CTL_PERFCNT_ROUTABLE BIT(2) BIT 223 arch/mips/include/asm/mips-gic.h #define GIC_VX_CTL_TIMER_ROUTABLE BIT(1) BIT 224 arch/mips/include/asm/mips-gic.h #define GIC_VX_CTL_EIC BIT(0) BIT 20 arch/mips/jz4740/timer.c writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); BIT 26 arch/mips/jz4740/timer.c writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); BIT 1062 arch/mips/kernel/cpu-probe.c c->guest.conf |= BIT(1); BIT 1090 arch/mips/kernel/cpu-probe.c c->guest.conf |= BIT(2); BIT 1101 arch/mips/kernel/cpu-probe.c c->guest.conf |= BIT(3); BIT 1138 arch/mips/kernel/cpu-probe.c c->guest.conf |= BIT(4); BIT 1153 arch/mips/kernel/cpu-probe.c c->guest.conf |= BIT(5); BIT 1176 arch/mips/kernel/cpu-probe.c c->guest.conf |= BIT(6); BIT 59 arch/mips/kernel/jump_label.c WARN_ON((offset >= BIT(25)) || BIT 60 arch/mips/kernel/jump_label.c (offset < -(long)BIT(25))); BIT 205 arch/mips/kernel/module.c offset |= (offset & BIT(bits - 1)) ? ~mask : 0; BIT 210 arch/mips/kernel/module.c se_bits = (offset & BIT(bits - 1)) ? ~0ul : 0; BIT 590 arch/mips/kernel/smp-bmips.c set_c0_brcm_bus_pll(BIT(22)); BIT 594 arch/mips/kernel/smp-bmips.c clear_c0_brcm_bus_pll(BIT(22)); BIT 597 arch/mips/kernel/smp-bmips.c clear_c0_brcm_reset(BIT(16)); BIT 626 arch/mips/kernel/smp-bmips.c clear_c0_brcm_config_0(BIT(21)); BIT 629 arch/mips/kernel/smp-bmips.c set_c0_brcm_config_0(BIT(23)); BIT 630 arch/mips/kernel/smp-bmips.c set_c0_brcm_cmt_ctrl(BIT(15)); BIT 635 arch/mips/kernel/smp-bmips.c set_c0_brcm_config(BIT(17) | BIT(21)); BIT 653 arch/mips/kernel/smp-bmips.c set_c0_brcm_config(BIT(27)); BIT 2523 arch/mips/kvm/emulate.c if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) { BIT 132 arch/mips/kvm/entry.c kscratch_mask &= ~BIT(pgd_reg); BIT 138 arch/mips/kvm/entry.c kscratch_mask &= ~BIT(scratch_vcpu[1]); BIT 145 arch/mips/kvm/entry.c kscratch_mask &= ~BIT(scratch_tmp[1]); BIT 89 arch/mips/lantiq/irq.c ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset), BIT 107 arch/mips/lantiq/irq.c ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset), BIT 109 arch/mips/lantiq/irq.c ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR); BIT 125 arch/mips/lantiq/irq.c ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR); BIT 147 arch/mips/lantiq/irq.c ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) | BIT(offset), BIT 214 arch/mips/lantiq/irq.c ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i), BIT 217 arch/mips/lantiq/irq.c ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i), BIT 234 arch/mips/lantiq/irq.c ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i), BIT 88 arch/mips/lantiq/xway/clk.c if (ltq_cgu_r32(CGU_SYS) & BIT(0)) BIT 96 arch/mips/lantiq/xway/clk.c if (ltq_cgu_r32(CGU_SYS) & BIT(2)) BIT 32 arch/mips/lantiq/xway/dma.c #define DMA_DESCPT BIT(3) /* descriptor complete irq */ BIT 33 arch/mips/lantiq/xway/dma.c #define DMA_TX BIT(8) /* TX channel direction */ BIT 34 arch/mips/lantiq/xway/dma.c #define DMA_CHAN_ON BIT(0) /* channel on / off bit */ BIT 35 arch/mips/lantiq/xway/dma.c #define DMA_PDEN BIT(6) /* enable packet drop */ BIT 36 arch/mips/lantiq/xway/dma.c #define DMA_CHAN_RST BIT(1) /* channel on / off bit */ BIT 37 arch/mips/lantiq/xway/dma.c #define DMA_RESET BIT(0) /* channel on / off bit */ BIT 39 arch/mips/lantiq/xway/dma.c #define DMA_POLL BIT(31) /* turn on channel polling */ BIT 40 arch/mips/lantiq/xway/dma.c #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ BIT 41 arch/mips/lantiq/xway/dma.c #define DMA_2W_BURST BIT(1) /* 2 word burst length */ BIT 44 arch/mips/lantiq/xway/dma.c #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ BIT 42 arch/mips/lantiq/xway/gptu.c #define CON_CNT BIT(2) BIT 43 arch/mips/lantiq/xway/gptu.c #define CON_EDGE_ANY (BIT(7) | BIT(6)) BIT 44 arch/mips/lantiq/xway/gptu.c #define CON_SYNC BIT(8) BIT 45 arch/mips/lantiq/xway/gptu.c #define CON_CLK_INT BIT(10) BIT 48 arch/mips/lantiq/xway/gptu.c #define RUN_SEN BIT(0) BIT 49 arch/mips/lantiq/xway/gptu.c #define RUN_RL BIT(2) BIT 52 arch/mips/lantiq/xway/gptu.c #define CLC_RMC BIT(8) BIT 54 arch/mips/lantiq/xway/gptu.c #define CLC_SUSPEND BIT(4) BIT 56 arch/mips/lantiq/xway/gptu.c #define CLC_DISABLE BIT(0) BIT 106 arch/mips/lantiq/xway/gptu.c gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN); BIT 116 arch/mips/lantiq/xway/gptu.c gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN); BIT 88 arch/mips/lantiq/xway/sysctrl.c #define PMU_USB0_P BIT(0) BIT 89 arch/mips/lantiq/xway/sysctrl.c #define PMU_ASE_SDIO BIT(2) /* ASE special */ BIT 90 arch/mips/lantiq/xway/sysctrl.c #define PMU_PCI BIT(4) BIT 91 arch/mips/lantiq/xway/sysctrl.c #define PMU_DMA BIT(5) BIT 92 arch/mips/lantiq/xway/sysctrl.c #define PMU_USB0 BIT(6) BIT 93 arch/mips/lantiq/xway/sysctrl.c #define PMU_ASC0 BIT(7) BIT 94 arch/mips/lantiq/xway/sysctrl.c #define PMU_EPHY BIT(7) /* ase */ BIT 95 arch/mips/lantiq/xway/sysctrl.c #define PMU_USIF BIT(7) /* from vr9 until grx390 */ BIT 96 arch/mips/lantiq/xway/sysctrl.c #define PMU_SPI BIT(8) BIT 97 arch/mips/lantiq/xway/sysctrl.c #define PMU_DFE BIT(9) BIT 98 arch/mips/lantiq/xway/sysctrl.c #define PMU_EBU BIT(10) BIT 99 arch/mips/lantiq/xway/sysctrl.c #define PMU_STP BIT(11) BIT 100 arch/mips/lantiq/xway/sysctrl.c #define PMU_GPT BIT(12) BIT 101 arch/mips/lantiq/xway/sysctrl.c #define PMU_AHBS BIT(13) /* vr9 */ BIT 102 arch/mips/lantiq/xway/sysctrl.c #define PMU_FPI BIT(14) BIT 103 arch/mips/lantiq/xway/sysctrl.c #define PMU_AHBM BIT(15) BIT 104 arch/mips/lantiq/xway/sysctrl.c #define PMU_SDIO BIT(16) /* danube, ar9, vr9 */ BIT 105 arch/mips/lantiq/xway/sysctrl.c #define PMU_ASC1 BIT(17) BIT 106 arch/mips/lantiq/xway/sysctrl.c #define PMU_PPE_QSB BIT(18) BIT 107 arch/mips/lantiq/xway/sysctrl.c #define PMU_PPE_SLL01 BIT(19) BIT 108 arch/mips/lantiq/xway/sysctrl.c #define PMU_DEU BIT(20) BIT 109 arch/mips/lantiq/xway/sysctrl.c #define PMU_PPE_TC BIT(21) BIT 110 arch/mips/lantiq/xway/sysctrl.c #define PMU_PPE_EMA BIT(22) BIT 111 arch/mips/lantiq/xway/sysctrl.c #define PMU_PPE_DPLUM BIT(23) BIT 112 arch/mips/lantiq/xway/sysctrl.c #define PMU_PPE_DP BIT(23) BIT 113 arch/mips/lantiq/xway/sysctrl.c #define PMU_PPE_DPLUS BIT(24) BIT 114 arch/mips/lantiq/xway/sysctrl.c #define PMU_USB1_P BIT(26) BIT 115 arch/mips/lantiq/xway/sysctrl.c #define PMU_USB1 BIT(27) BIT 116 arch/mips/lantiq/xway/sysctrl.c #define PMU_SWITCH BIT(28) BIT 117 arch/mips/lantiq/xway/sysctrl.c #define PMU_PPE_TOP BIT(29) BIT 118 arch/mips/lantiq/xway/sysctrl.c #define PMU_GPHY BIT(30) BIT 119 arch/mips/lantiq/xway/sysctrl.c #define PMU_PCIE_CLK BIT(31) BIT 121 arch/mips/lantiq/xway/sysctrl.c #define PMU1_PCIE_PHY BIT(0) /* vr9-specific,moved in ar10/grx390 */ BIT 122 arch/mips/lantiq/xway/sysctrl.c #define PMU1_PCIE_CTL BIT(1) BIT 123 arch/mips/lantiq/xway/sysctrl.c #define PMU1_PCIE_PDI BIT(4) BIT 124 arch/mips/lantiq/xway/sysctrl.c #define PMU1_PCIE_MSI BIT(5) BIT 125 arch/mips/lantiq/xway/sysctrl.c #define PMU1_CKE BIT(6) BIT 126 arch/mips/lantiq/xway/sysctrl.c #define PMU1_PCIE1_CTL BIT(17) BIT 127 arch/mips/lantiq/xway/sysctrl.c #define PMU1_PCIE1_PDI BIT(20) BIT 128 arch/mips/lantiq/xway/sysctrl.c #define PMU1_PCIE1_MSI BIT(21) BIT 129 arch/mips/lantiq/xway/sysctrl.c #define PMU1_PCIE2_CTL BIT(25) BIT 130 arch/mips/lantiq/xway/sysctrl.c #define PMU1_PCIE2_PDI BIT(26) BIT 131 arch/mips/lantiq/xway/sysctrl.c #define PMU1_PCIE2_MSI BIT(27) BIT 133 arch/mips/lantiq/xway/sysctrl.c #define PMU_ANALOG_USB0_P BIT(0) BIT 134 arch/mips/lantiq/xway/sysctrl.c #define PMU_ANALOG_USB1_P BIT(1) BIT 135 arch/mips/lantiq/xway/sysctrl.c #define PMU_ANALOG_PCIE0_P BIT(8) BIT 136 arch/mips/lantiq/xway/sysctrl.c #define PMU_ANALOG_PCIE1_P BIT(9) BIT 137 arch/mips/lantiq/xway/sysctrl.c #define PMU_ANALOG_PCIE2_P BIT(10) BIT 138 arch/mips/lantiq/xway/sysctrl.c #define PMU_ANALOG_DSL_AFE BIT(16) BIT 139 arch/mips/lantiq/xway/sysctrl.c #define PMU_ANALOG_DCDC_2V5 BIT(17) BIT 140 arch/mips/lantiq/xway/sysctrl.c #define PMU_ANALOG_DCDC_1VX BIT(18) BIT 141 arch/mips/lantiq/xway/sysctrl.c #define PMU_ANALOG_DCDC_1V0 BIT(19) BIT 51 arch/mips/mm/c-r4k.c #define R4K_HIT BIT(0) BIT 52 arch/mips/mm/c-r4k.c #define R4K_INDEX BIT(1) BIT 285 arch/mips/mm/init.c maar_align = BIT(MIPS_MAAR_ADDR_SHIFT + 4); BIT 248 arch/mips/mti-malta/malta-dtshim.c sc_cfg |= BIT(MSC01_SC_CFG_GICENA_SHF); BIT 32 arch/mips/mti-malta/malta-setup.c #define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7) BIT 53 arch/mips/net/ebpf_jit.c #define EBPF_SAVE_S0 BIT(0) BIT 54 arch/mips/net/ebpf_jit.c #define EBPF_SAVE_S1 BIT(1) BIT 55 arch/mips/net/ebpf_jit.c #define EBPF_SAVE_S2 BIT(2) BIT 56 arch/mips/net/ebpf_jit.c #define EBPF_SAVE_S3 BIT(3) BIT 57 arch/mips/net/ebpf_jit.c #define EBPF_SAVE_S4 BIT(4) BIT 58 arch/mips/net/ebpf_jit.c #define EBPF_SAVE_RA BIT(5) BIT 59 arch/mips/net/ebpf_jit.c #define EBPF_SEEN_FP BIT(6) BIT 60 arch/mips/net/ebpf_jit.c #define EBPF_SEEN_TC BIT(7) BIT 61 arch/mips/net/ebpf_jit.c #define EBPF_TCC_IN_V1 BIT(8) BIT 88 arch/mips/net/ebpf_jit.c #define OFFSETS_B_CONV BIT(31) BIT 1447 arch/mips/net/ebpf_jit.c (mem_off >= BIT(8) || mem_off < -BIT(8))) { BIT 89 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define SATA_RST_N BIT(0) /* Active low reset sata_core phy */ BIT 90 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define SataCtlReserve0 BIT(1) BIT 91 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define M_CSYSREQ BIT(2) /* AXI master low power, not used */ BIT 92 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define S_CSYSREQ BIT(3) /* AXI slave low power, not used */ BIT 93 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_CP_DET BIT(8) /* Reserved, bring in from pad */ BIT 94 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_MP_SW BIT(9) /* Mech Switch */ BIT 95 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_DISABLE BIT(10) /* disable p0 */ BIT 96 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_ACT_LED_EN BIT(11) /* Active LED enable */ BIT 97 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_IRST_HARD_SYNTH BIT(12) /* PHY hard synth reset */ BIT 98 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_IRST_HARD_TXRX BIT(13) /* PHY lane hard reset */ BIT 99 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_IRST_POR BIT(14) /* PHY power on reset*/ BIT 100 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_IPDTXL BIT(15) /* PHY Tx lane dis/power down */ BIT 101 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_IPDRXL BIT(16) /* PHY Rx lane dis/power down */ BIT 102 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_IPDIPDMSYNTH BIT(17) /* PHY synthesizer dis/porwer down */ BIT 103 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_CP_POD_EN BIT(18) /* CP_POD enable */ BIT 104 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_AT_BYPASS BIT(19) /* P0 address translation by pass */ BIT 105 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_CP_DET BIT(20) /* Reserved,Cold Detect */ BIT 106 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_MP_SW BIT(21) /* Mech Switch */ BIT 107 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_DISABLE BIT(22) /* disable p1 */ BIT 108 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_ACT_LED_EN BIT(23) /* Active LED enable */ BIT 109 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_IRST_HARD_SYNTH BIT(24) /* PHY hard synth reset */ BIT 110 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_IRST_HARD_TXRX BIT(25) /* PHY lane hard reset */ BIT 111 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_IRST_POR BIT(26) /* PHY power on reset*/ BIT 112 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_IPDTXL BIT(27) /* PHY Tx lane dis/porwer down */ BIT 113 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_IPDRXL BIT(28) /* PHY Rx lane dis/porwer down */ BIT 114 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_IPDIPDMSYNTH BIT(29) /* PHY synthesizer dis/porwer down */ BIT 115 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_CP_POD_EN BIT(30) BIT 116 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_AT_BYPASS BIT(31) /* P1 address translation by pass */ BIT 119 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define M_CACTIVE BIT(0) /* m_cactive, not used */ BIT 120 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define S_CACTIVE BIT(1) /* s_cactive, not used */ BIT 121 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_PHY_READY BIT(8) /* phy is ready */ BIT 122 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_CP_POD BIT(9) /* Cold PowerOn */ BIT 123 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_SLUMBER BIT(10) /* power mode slumber */ BIT 124 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_PATIAL BIT(11) /* power mode patial */ BIT 125 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_PHY_SIG_DET BIT(12) /* phy dignal detect */ BIT 126 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P0_PHY_CALI BIT(13) /* phy calibration done */ BIT 127 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_PHY_READY BIT(16) /* phy is ready */ BIT 128 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_CP_POD BIT(17) /* Cold PowerOn */ BIT 129 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_SLUMBER BIT(18) /* power mode slumber */ BIT 130 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_PATIAL BIT(19) /* power mode patial */ BIT 131 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_PHY_SIG_DET BIT(20) /* phy dignal detect */ BIT 132 arch/mips/netlogic/xlp/ahci-init-xlp2.c #define P1_PHY_CALI BIT(21) /* phy calibration done */ BIT 73 arch/mips/netlogic/xlp/ahci-init.c #define SATA_RST_N BIT(0) BIT 74 arch/mips/netlogic/xlp/ahci-init.c #define PHY0_RESET_N BIT(16) BIT 75 arch/mips/netlogic/xlp/ahci-init.c #define PHY1_RESET_N BIT(17) BIT 76 arch/mips/netlogic/xlp/ahci-init.c #define PHY2_RESET_N BIT(18) BIT 77 arch/mips/netlogic/xlp/ahci-init.c #define PHY3_RESET_N BIT(19) BIT 78 arch/mips/netlogic/xlp/ahci-init.c #define M_CSYSREQ BIT(2) BIT 79 arch/mips/netlogic/xlp/ahci-init.c #define S_CSYSREQ BIT(3) BIT 82 arch/mips/netlogic/xlp/ahci-init.c #define P0_PHY_READY BIT(4) BIT 83 arch/mips/netlogic/xlp/ahci-init.c #define P1_PHY_READY BIT(5) BIT 84 arch/mips/netlogic/xlp/ahci-init.c #define P2_PHY_READY BIT(6) BIT 85 arch/mips/netlogic/xlp/ahci-init.c #define P3_PHY_READY BIT(7) BIT 50 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_VAUXRST BIT(0) BIT 51 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_VCCRST BIT(1) BIT 54 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_RTUNEREQ BIT(20) BIT 55 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_MS_CSYSREQ BIT(21) BIT 56 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_XS_CSYSREQ BIT(22) BIT 57 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_RETENABLEN BIT(23) BIT 58 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_TX2RX BIT(24) BIT 59 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_XHCIREV BIT(25) BIT 60 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_ECCDIS BIT(26) BIT 66 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_PRESET BIT(0) BIT 67 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_ATERESET BIT(1) BIT 68 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_LOOPEN BIT(2) BIT 69 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_TESTPDHSP BIT(3) BIT 70 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_TESTPDSSP BIT(4) BIT 71 arch/mips/netlogic/xlp/usb-init-xlp2.c #define XLPII_TESTBURNIN BIT(5) BIT 354 arch/mips/pci/pci-ar2315.c ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0); BIT 360 arch/mips/pci/pci-ar2315.c u32 m = BIT(d->hwirq); BIT 370 arch/mips/pci/pci-ar2315.c ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq)); BIT 41 arch/mips/pci/pci-ar71xx.c #define AR71XX_PCI_INT_CORE BIT(4) BIT 42 arch/mips/pci/pci-ar71xx.c #define AR71XX_PCI_INT_DEV2 BIT(2) BIT 43 arch/mips/pci/pci-ar71xx.c #define AR71XX_PCI_INT_DEV1 BIT(1) BIT 44 arch/mips/pci/pci-ar71xx.c #define AR71XX_PCI_INT_DEV0 BIT(0) BIT 22 arch/mips/pci/pci-ar724x.c #define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) BIT 24 arch/mips/pci/pci-ar724x.c #define AR724X_PCI_RESET_LINK_UP BIT(0) BIT 26 arch/mips/pci/pci-ar724x.c #define AR724X_PCI_INT_DEV0 BIT(14) BIT 35 arch/mips/pci/pci-mt7620.c #define PDRV_SW_SET BIT(31) BIT 36 arch/mips/pci/pci-mt7620.c #define LC_CKDRVPD BIT(19) BIT 37 arch/mips/pci/pci-mt7620.c #define LC_CKDRVOHZ BIT(18) BIT 38 arch/mips/pci/pci-mt7620.c #define LC_CKDRVHZ BIT(17) BIT 39 arch/mips/pci/pci-mt7620.c #define LC_CKTEST BIT(16) BIT 43 arch/mips/pci/pci-mt7620.c #define PCIRST BIT(1) BIT 46 arch/mips/pci/pci-mt7620.c #define PCIINT2 BIT(20) BIT 60 arch/mips/pci/pci-mt7620.c #define PCIE_LINK_UP_ST BIT(0) BIT 65 arch/mips/pci/pci-mt7620.c #define RALINK_PCIE0_CLK_EN BIT(26) BIT 261 arch/mips/pci/pci-mt7620.c rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE); BIT 30 arch/mips/pci/pci-rt3883.c #define RT3883_PCICFG_PCIRST BIT(1) BIT 50 arch/mips/pci/pci-rt3883.c #define RT3883_PCI_MODE_PCI BIT(0) BIT 51 arch/mips/pci/pci-rt3883.c #define RT3883_PCI_MODE_PCIE BIT(1) BIT 149 arch/mips/pci/pci-rt3883.c pending &= ~BIT(bit); BIT 161 arch/mips/pci/pci-rt3883.c rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA); BIT 174 arch/mips/pci/pci-rt3883.c rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA); BIT 326 arch/mips/pci/pci-rt3883.c t &= ~BIT(31); BIT 338 arch/mips/pci/pci-rt3883.c t |= BIT(31); BIT 383 arch/mips/pci/pci-rt3883.c rpc->pcie_ready = t & BIT(0); BIT 54 arch/mips/pic32/pic32mzda/config.c return pic32_conf_modify_atomic(PIC32_CFGCON2, BIT(31), BIT(31)); BIT 59 arch/mips/pic32/pic32mzda/config.c return pic32_conf_modify_atomic(PIC32_CFGCON2, BIT(31), 0); BIT 64 arch/mips/pic32/pic32mzda/config.c u32 mask = mode ? BIT(30) : 0; BIT 66 arch/mips/pic32/pic32mzda/config.c return pic32_conf_modify_atomic(PIC32_CFGCON2, BIT(30), mask); BIT 17 arch/mips/pic32/pic32mzda/early_console.c #define UART_ENABLE BIT(15) BIT 18 arch/mips/pic32/pic32mzda/early_console.c #define UART_ENABLE_RX BIT(12) BIT 19 arch/mips/pic32/pic32mzda/early_console.c #define UART_ENABLE_TX BIT(10) BIT 20 arch/mips/pic32/pic32mzda/early_console.c #define UART_TX_FULL BIT(9) BIT 16 arch/mips/ralink/ill_acc.c #define ILL_INT_STATUS BIT(31) BIT 17 arch/mips/ralink/ill_acc.c #define ILL_ACC_WRITE BIT(30) BIT 21 arch/mips/ralink/irq.c #define INTC_INT_GLOBAL BIT(31) BIT 71 arch/mips/ralink/irq.c rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE); BIT 76 arch/mips/ralink/irq.c rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE); BIT 24 arch/mips/ralink/mt7620.c #define PMU_SW_SET BIT(28) BIT 25 arch/mips/ralink/mt7620.c #define A_DCDC_EN BIT(24) BIT 26 arch/mips/ralink/mt7620.c #define A_SSC_PERI BIT(19) BIT 27 arch/mips/ralink/mt7620.c #define A_SSC_GEN BIT(18) BIT 36 arch/mips/ralink/mt7620.c #define DIG_SW_SEL BIT(25) BIT 24 arch/mips/ralink/mt7621.c #define CPU_CLK_SEL (BIT(30) | BIT(31)) BIT 22 arch/mips/ralink/reset.c #define RSTCTL_RESET_PCI BIT(26) BIT 23 arch/mips/ralink/reset.c #define RSTCTL_RESET_SYSTEM BIT(0) BIT 34 arch/mips/ralink/reset.c val |= BIT(id); BIT 49 arch/mips/ralink/reset.c val &= ~BIT(id); BIT 21 arch/mips/ralink/timer.c #define TMRSTAT_TMR0INT BIT(0) BIT 23 arch/mips/ralink/timer.c #define TMR0CTL_ENABLE BIT(7) BIT 24 arch/mips/ralink/timer.c #define TMR0CTL_MODE_PERIODIC BIT(4) BIT 27 arch/mips/ralink/timer.c #define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER)) BIT 1015 arch/powerpc/platforms/512x/clock-commonclk.c DID_REG_PSC = BIT(0), BIT 1016 arch/powerpc/platforms/512x/clock-commonclk.c DID_REG_PSCFIFO = BIT(1), BIT 1017 arch/powerpc/platforms/512x/clock-commonclk.c DID_REG_NFC = BIT(2), BIT 1018 arch/powerpc/platforms/512x/clock-commonclk.c DID_REG_CAN = BIT(3), BIT 1019 arch/powerpc/platforms/512x/clock-commonclk.c DID_REG_I2C = BIT(4), BIT 1020 arch/powerpc/platforms/512x/clock-commonclk.c DID_REG_DIU = BIT(5), BIT 1021 arch/powerpc/platforms/512x/clock-commonclk.c DID_REG_VIU = BIT(6), BIT 1022 arch/powerpc/platforms/512x/clock-commonclk.c DID_REG_FEC = BIT(7), BIT 1023 arch/powerpc/platforms/512x/clock-commonclk.c DID_REG_USB = BIT(8), BIT 1024 arch/powerpc/platforms/512x/clock-commonclk.c DID_REG_PATA = BIT(9), BIT 99 arch/riscv/include/asm/pgtable.h #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) BIT 13 arch/s390/include/asm/ctl_reg.h #define CR0_CLOCK_COMPARATOR_SIGN BIT(63 - 10) BIT 14 arch/s390/include/asm/ctl_reg.h #define CR0_EMERGENCY_SIGNAL_SUBMASK BIT(63 - 49) BIT 15 arch/s390/include/asm/ctl_reg.h #define CR0_EXTERNAL_CALL_SUBMASK BIT(63 - 50) BIT 16 arch/s390/include/asm/ctl_reg.h #define CR0_CLOCK_COMPARATOR_SUBMASK BIT(63 - 52) BIT 17 arch/s390/include/asm/ctl_reg.h #define CR0_CPU_TIMER_SUBMASK BIT(63 - 53) BIT 18 arch/s390/include/asm/ctl_reg.h #define CR0_SERVICE_SIGNAL_SUBMASK BIT(63 - 54) BIT 19 arch/s390/include/asm/ctl_reg.h #define CR0_UNUSED_56 BIT(63 - 56) BIT 20 arch/s390/include/asm/ctl_reg.h #define CR0_INTERRUPT_KEY_SUBMASK BIT(63 - 57) BIT 21 arch/s390/include/asm/ctl_reg.h #define CR0_MEASUREMENT_ALERT_SUBMASK BIT(63 - 58) BIT 23 arch/s390/include/asm/ctl_reg.h #define CR2_GUARDED_STORAGE BIT(63 - 59) BIT 25 arch/s390/include/asm/ctl_reg.h #define CR14_UNUSED_32 BIT(63 - 32) BIT 26 arch/s390/include/asm/ctl_reg.h #define CR14_UNUSED_33 BIT(63 - 33) BIT 27 arch/s390/include/asm/ctl_reg.h #define CR14_CHANNEL_REPORT_SUBMASK BIT(63 - 35) BIT 28 arch/s390/include/asm/ctl_reg.h #define CR14_RECOVERY_SUBMASK BIT(63 - 36) BIT 29 arch/s390/include/asm/ctl_reg.h #define CR14_DEGRADATION_SUBMASK BIT(63 - 37) BIT 30 arch/s390/include/asm/ctl_reg.h #define CR14_EXTERNAL_DAMAGE_SUBMASK BIT(63 - 38) BIT 31 arch/s390/include/asm/ctl_reg.h #define CR14_WARNING_SUBMASK BIT(63 - 39) BIT 23 arch/s390/include/asm/nmi.h #define MCCK_CODE_SYSTEM_DAMAGE BIT(63) BIT 24 arch/s390/include/asm/nmi.h #define MCCK_CODE_EXT_DAMAGE BIT(63 - 5) BIT 25 arch/s390/include/asm/nmi.h #define MCCK_CODE_CP BIT(63 - 9) BIT 26 arch/s390/include/asm/nmi.h #define MCCK_CODE_CPU_TIMER_VALID BIT(63 - 46) BIT 27 arch/s390/include/asm/nmi.h #define MCCK_CODE_PSW_MWP_VALID BIT(63 - 20) BIT 28 arch/s390/include/asm/nmi.h #define MCCK_CODE_PSW_IA_VALID BIT(63 - 23) BIT 29 arch/s390/include/asm/nmi.h #define MCCK_CODE_CR_VALID BIT(63 - 29) BIT 30 arch/s390/include/asm/nmi.h #define MCCK_CODE_GS_VALID BIT(63 - 36) BIT 31 arch/s390/include/asm/nmi.h #define MCCK_CODE_FC_VALID BIT(63 - 43) BIT 27 arch/s390/include/asm/processor.h #define _CIF_MCCK_PENDING BIT(CIF_MCCK_PENDING) BIT 28 arch/s390/include/asm/processor.h #define _CIF_ASCE_PRIMARY BIT(CIF_ASCE_PRIMARY) BIT 29 arch/s390/include/asm/processor.h #define _CIF_ASCE_SECONDARY BIT(CIF_ASCE_SECONDARY) BIT 30 arch/s390/include/asm/processor.h #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY) BIT 31 arch/s390/include/asm/processor.h #define _CIF_FPU BIT(CIF_FPU) BIT 32 arch/s390/include/asm/processor.h #define _CIF_IGNORE_IRQ BIT(CIF_IGNORE_IRQ) BIT 33 arch/s390/include/asm/processor.h #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT) BIT 34 arch/s390/include/asm/processor.h #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST) BIT 35 arch/s390/include/asm/processor.h #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU) BIT 18 arch/s390/include/asm/ptrace.h #define _PIF_SYSCALL BIT(PIF_SYSCALL) BIT 19 arch/s390/include/asm/ptrace.h #define _PIF_PER_TRAP BIT(PIF_PER_TRAP) BIT 20 arch/s390/include/asm/ptrace.h #define _PIF_SYSCALL_RESTART BIT(PIF_SYSCALL_RESTART) BIT 21 arch/s390/include/asm/ptrace.h #define _PIF_GUEST_FAULT BIT(PIF_GUEST_FAULT) BIT 25 arch/s390/include/asm/setup.h #define MACHINE_FLAG_VM BIT(0) BIT 26 arch/s390/include/asm/setup.h #define MACHINE_FLAG_KVM BIT(1) BIT 27 arch/s390/include/asm/setup.h #define MACHINE_FLAG_LPAR BIT(2) BIT 28 arch/s390/include/asm/setup.h #define MACHINE_FLAG_DIAG9C BIT(3) BIT 29 arch/s390/include/asm/setup.h #define MACHINE_FLAG_ESOP BIT(4) BIT 30 arch/s390/include/asm/setup.h #define MACHINE_FLAG_IDTE BIT(5) BIT 31 arch/s390/include/asm/setup.h #define MACHINE_FLAG_DIAG44 BIT(6) BIT 32 arch/s390/include/asm/setup.h #define MACHINE_FLAG_EDAT1 BIT(7) BIT 33 arch/s390/include/asm/setup.h #define MACHINE_FLAG_EDAT2 BIT(8) BIT 34 arch/s390/include/asm/setup.h #define MACHINE_FLAG_TOPOLOGY BIT(10) BIT 35 arch/s390/include/asm/setup.h #define MACHINE_FLAG_TE BIT(11) BIT 36 arch/s390/include/asm/setup.h #define MACHINE_FLAG_TLB_LC BIT(12) BIT 37 arch/s390/include/asm/setup.h #define MACHINE_FLAG_VX BIT(13) BIT 38 arch/s390/include/asm/setup.h #define MACHINE_FLAG_TLB_GUEST BIT(14) BIT 39 arch/s390/include/asm/setup.h #define MACHINE_FLAG_NX BIT(15) BIT 40 arch/s390/include/asm/setup.h #define MACHINE_FLAG_GS BIT(16) BIT 41 arch/s390/include/asm/setup.h #define MACHINE_FLAG_SCC BIT(17) BIT 43 arch/s390/include/asm/setup.h #define LPP_MAGIC BIT(31) BIT 85 arch/s390/include/asm/thread_info.h #define _TIF_NOTIFY_RESUME BIT(TIF_NOTIFY_RESUME) BIT 86 arch/s390/include/asm/thread_info.h #define _TIF_SIGPENDING BIT(TIF_SIGPENDING) BIT 87 arch/s390/include/asm/thread_info.h #define _TIF_NEED_RESCHED BIT(TIF_NEED_RESCHED) BIT 88 arch/s390/include/asm/thread_info.h #define _TIF_UPROBE BIT(TIF_UPROBE) BIT 89 arch/s390/include/asm/thread_info.h #define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE) BIT 90 arch/s390/include/asm/thread_info.h #define _TIF_PATCH_PENDING BIT(TIF_PATCH_PENDING) BIT 91 arch/s390/include/asm/thread_info.h #define _TIF_ISOLATE_BP BIT(TIF_ISOLATE_BP) BIT 92 arch/s390/include/asm/thread_info.h #define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST) BIT 94 arch/s390/include/asm/thread_info.h #define _TIF_31BIT BIT(TIF_31BIT) BIT 95 arch/s390/include/asm/thread_info.h #define _TIF_SINGLE_STEP BIT(TIF_SINGLE_STEP) BIT 97 arch/s390/include/asm/thread_info.h #define _TIF_SYSCALL_TRACE BIT(TIF_SYSCALL_TRACE) BIT 98 arch/s390/include/asm/thread_info.h #define _TIF_SYSCALL_AUDIT BIT(TIF_SYSCALL_AUDIT) BIT 99 arch/s390/include/asm/thread_info.h #define _TIF_SECCOMP BIT(TIF_SECCOMP) BIT 100 arch/s390/include/asm/thread_info.h #define _TIF_SYSCALL_TRACEPOINT BIT(TIF_SYSCALL_TRACEPOINT) BIT 52 arch/sh/boards/board-sh7757lcr.c #define GBECONT_RMII1 BIT(17) BIT 53 arch/sh/boards/board-sh7757lcr.c #define GBECONT_RMII0 BIT(16) BIT 45 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */ BIT 46 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */ BIT 47 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */ BIT 48 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */ BIT 49 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */ BIT 50 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */ BIT 51 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */ BIT 52 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */ BIT 53 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */ BIT 54 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */ BIT 55 arch/sh/drivers/pci/pci-sh4.h #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */ BIT 20 arch/sh/include/mach-sdk7786/mach/fpga.h #define NMISR_MAN_NMI BIT(0) BIT 21 arch/sh/include/mach-sdk7786/mach/fpga.h #define NMISR_AUX_NMI BIT(1) BIT 25 arch/sh/include/mach-sdk7786/mach/fpga.h #define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */ BIT 26 arch/sh/include/mach-sdk7786/mach/fpga.h #define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */ BIT 42 arch/sh/include/mach-sdk7786/mach/fpga.h #define PCIECR_PCIEMUX1 BIT(15) BIT 43 arch/sh/include/mach-sdk7786/mach/fpga.h #define PCIECR_PCIEMUX0 BIT(14) BIT 44 arch/sh/include/mach-sdk7786/mach/fpga.h #define PCIECR_PRST4 BIT(12) /* slot 4 card present */ BIT 45 arch/sh/include/mach-sdk7786/mach/fpga.h #define PCIECR_PRST3 BIT(11) /* slot 3 card present */ BIT 46 arch/sh/include/mach-sdk7786/mach/fpga.h #define PCIECR_PRST2 BIT(10) /* slot 2 card present */ BIT 47 arch/sh/include/mach-sdk7786/mach/fpga.h #define PCIECR_PRST1 BIT(9) /* slot 1 card present */ BIT 48 arch/sh/include/mach-sdk7786/mach/fpga.h #define PCIECR_CLKEN BIT(4) /* oscillator enable */ BIT 56 arch/sh/include/mach-sdk7786/mach/fpga.h #define LCLASR_FRAMEN BIT(15) BIT 71 arch/sh/include/mach-sdk7786/mach/fpga.h #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */ BIT 72 arch/sh/include/mach-sdk7786/mach/fpga.h #define SCBR_I2CCEN BIT(1) /* CPU I2C master enable */ BIT 75 arch/sh/include/mach-sdk7786/mach/fpga.h #define PWRCR_SCISEL0 BIT(0) BIT 76 arch/sh/include/mach-sdk7786/mach/fpga.h #define PWRCR_SCISEL1 BIT(1) BIT 77 arch/sh/include/mach-sdk7786/mach/fpga.h #define PWRCR_SCIEN BIT(2) /* Serial port enable */ BIT 78 arch/sh/include/mach-sdk7786/mach/fpga.h #define PWRCR_PDWNACK BIT(5) /* Power down acknowledge */ BIT 79 arch/sh/include/mach-sdk7786/mach/fpga.h #define PWRCR_PDWNREQ BIT(7) /* Power down request */ BIT 80 arch/sh/include/mach-sdk7786/mach/fpga.h #define PWRCR_INT2 BIT(11) /* INT2 connection to power manager */ BIT 81 arch/sh/include/mach-sdk7786/mach/fpga.h #define PWRCR_BUPINIT BIT(13) /* DDR backup initialize */ BIT 82 arch/sh/include/mach-sdk7786/mach/fpga.h #define PWRCR_BKPRST BIT(15) /* Backup power reset */ BIT 1003 arch/sparc/include/asm/hypervisor.h #define HV_CCB_QUERY_CMD BIT(1) BIT 1005 arch/sparc/include/asm/hypervisor.h #define HV_CCB_ARG0_TYPE_PRIMARY BIT(4) BIT 1006 arch/sparc/include/asm/hypervisor.h #define HV_CCB_ARG0_TYPE_SECONDARY BIT(5) BIT 1008 arch/sparc/include/asm/hypervisor.h #define HV_CCB_ARG0_PRIVILEGED BIT(6) BIT 1009 arch/sparc/include/asm/hypervisor.h #define HV_CCB_ALL_OR_NOTHING BIT(7) BIT 1010 arch/sparc/include/asm/hypervisor.h #define HV_CCB_QUEUE_INFO BIT(8) BIT 1012 arch/sparc/include/asm/hypervisor.h #define HV_CCB_VA_SECONDARY BIT(13) BIT 1014 arch/sparc/include/asm/hypervisor.h #define HV_CCB_VA_PRIVILEGED BIT(14) BIT 1015 arch/sparc/include/asm/hypervisor.h #define HV_CCB_VA_READ_ADI_DISABLE BIT(15) /* DAX2 only */ BIT 56 arch/sparc/include/asm/mmu_64.h #define CTX_FIRST_VERSION BIT(CTX_VERSION_SHIFT) BIT 38 arch/sparc/include/asm/timer_64.h #define TICK_PRIV_BIT BIT(63) BIT 39 arch/sparc/include/asm/timer_64.h #define TICKCMP_IRQ_BIT BIT(63) BIT 8 arch/um/drivers/vhost_user.h #define VHOST_USER_FLAG_REPLY BIT(2) BIT 9 arch/um/drivers/vhost_user.h #define VHOST_USER_FLAG_NEED_REPLY BIT(3) BIT 18 arch/um/drivers/vhost_user.h #define VHOST_USER_VRING_POLL_MASK BIT(8) BIT 252 arch/x86/events/amd/iommu.c reg |= BIT(31); BIT 258 arch/x86/events/amd/iommu.c reg |= BIT(31); BIT 264 arch/x86/events/amd/iommu.c reg |= BIT(31); BIT 798 arch/x86/events/intel/core.c #define BDW_L3_MISS_LOCAL BIT(26) BIT 505 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | BIT 506 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C6_RES), BIT 508 arch/x86/events/intel/cstate.c .pkg_events = BIT(PERF_CSTATE_PKG_C3_RES) | BIT 509 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C6_RES) | BIT 510 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C7_RES), BIT 514 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | BIT 515 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C6_RES) | BIT 516 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C7_RES), BIT 518 arch/x86/events/intel/cstate.c .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | BIT 519 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C3_RES) | BIT 520 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C6_RES) | BIT 521 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C7_RES), BIT 525 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | BIT 526 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C6_RES) | BIT 527 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C7_RES), BIT 529 arch/x86/events/intel/cstate.c .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | BIT 530 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C3_RES) | BIT 531 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C6_RES) | BIT 532 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C7_RES) | BIT 533 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C8_RES) | BIT 534 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C9_RES) | BIT 535 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C10_RES), BIT 539 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | BIT 540 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C3_RES) | BIT 541 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C6_RES) | BIT 542 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C7_RES), BIT 544 arch/x86/events/intel/cstate.c .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | BIT 545 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C3_RES) | BIT 546 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C6_RES) | BIT 547 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C7_RES) | BIT 548 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C8_RES) | BIT 549 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C9_RES) | BIT 550 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C10_RES), BIT 554 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C6_RES) | BIT 555 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C7_RES), BIT 557 arch/x86/events/intel/cstate.c .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | BIT 558 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C3_RES) | BIT 559 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C6_RES) | BIT 560 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C7_RES) | BIT 561 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C8_RES) | BIT 562 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C9_RES) | BIT 563 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C10_RES), BIT 567 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | BIT 568 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C6_RES), BIT 570 arch/x86/events/intel/cstate.c .pkg_events = BIT(PERF_CSTATE_PKG_C6_RES), BIT 576 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C6_RES), BIT 578 arch/x86/events/intel/cstate.c .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | BIT 579 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C3_RES) | BIT 580 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C6_RES), BIT 586 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | BIT 587 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C3_RES) | BIT 588 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C6_RES), BIT 590 arch/x86/events/intel/cstate.c .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | BIT 591 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C3_RES) | BIT 592 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C6_RES) | BIT 593 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_PKG_C10_RES), BIT 54 arch/x86/events/intel/pt.c PT_CAP(cr3_filtering, 0, CPUID_EBX, BIT(0)), BIT 55 arch/x86/events/intel/pt.c PT_CAP(psb_cyc, 0, CPUID_EBX, BIT(1)), BIT 56 arch/x86/events/intel/pt.c PT_CAP(ip_filtering, 0, CPUID_EBX, BIT(2)), BIT 57 arch/x86/events/intel/pt.c PT_CAP(mtc, 0, CPUID_EBX, BIT(3)), BIT 58 arch/x86/events/intel/pt.c PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)), BIT 59 arch/x86/events/intel/pt.c PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)), BIT 60 arch/x86/events/intel/pt.c PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)), BIT 61 arch/x86/events/intel/pt.c PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)), BIT 62 arch/x86/events/intel/pt.c PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)), BIT 63 arch/x86/events/intel/pt.c PT_CAP(output_subsys, 0, CPUID_ECX, BIT(3)), BIT 64 arch/x86/events/intel/pt.c PT_CAP(payloads_lip, 0, CPUID_ECX, BIT(31)), BIT 225 arch/x86/events/intel/pt.c if (reg & BIT(14)) BIT 319 arch/x86/events/intel/pt.c if (requested && (!(allowed & BIT(requested)))) BIT 325 arch/x86/events/intel/pt.c if (requested && (!(allowed & BIT(requested)))) BIT 347 arch/x86/events/intel/pt.c if (!(allowed & BIT(requested))) BIT 490 arch/x86/events/intel/pt.c if (event->attr.config & BIT(0)) { BIT 675 arch/x86/events/intel/rapl.c .events = BIT(PERF_RAPL_PP0) | BIT 676 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_PKG) | BIT 677 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_PP1), BIT 682 arch/x86/events/intel/rapl.c .events = BIT(PERF_RAPL_PP0) | BIT 683 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_PKG) | BIT 684 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_RAM), BIT 689 arch/x86/events/intel/rapl.c .events = BIT(PERF_RAPL_PP0) | BIT 690 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_PKG) | BIT 691 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_RAM) | BIT 692 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_PP1), BIT 697 arch/x86/events/intel/rapl.c .events = BIT(PERF_RAPL_PP0) | BIT 698 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_PKG) | BIT 699 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_RAM), BIT 704 arch/x86/events/intel/rapl.c .events = BIT(PERF_RAPL_PKG) | BIT 705 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_RAM), BIT 710 arch/x86/events/intel/rapl.c .events = BIT(PERF_RAPL_PP0) | BIT 711 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_PKG) | BIT 712 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_RAM) | BIT 713 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_PP1) | BIT 714 arch/x86/events/intel/rapl.c BIT(PERF_RAPL_PSYS), BIT 40 arch/x86/events/probe.c avail |= BIT(bit); BIT 77 arch/x86/include/asm/amd_nb.h #define AMD_NB_GART BIT(0) BIT 78 arch/x86/include/asm/amd_nb.h #define AMD_NB_L3_INDEX_DISABLE BIT(1) BIT 79 arch/x86/include/asm/amd_nb.h #define AMD_NB_L3_PARTITIONING BIT(2) BIT 372 arch/x86/include/asm/elf.h ALIGN_VA_32 = BIT(0), BIT 373 arch/x86/include/asm/elf.h ALIGN_VA_64 = BIT(1), BIT 22 arch/x86/include/asm/hyperv-tlfs.h #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) BIT 48 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_MSR_VP_RUNTIME_AVAILABLE BIT(0) BIT 50 arch/x86/include/asm/hyperv-tlfs.h #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) BIT 55 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_MSR_SYNIC_AVAILABLE BIT(2) BIT 60 arch/x86/include/asm/hyperv-tlfs.h #define HV_MSR_SYNTIMER_AVAILABLE BIT(3) BIT 65 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_MSR_APIC_ACCESS_AVAILABLE BIT(4) BIT 67 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_MSR_HYPERCALL_AVAILABLE BIT(5) BIT 69 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_MSR_VP_INDEX_AVAILABLE BIT(6) BIT 71 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_MSR_RESET_AVAILABLE BIT(7) BIT 77 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_MSR_STAT_PAGES_AVAILABLE BIT(8) BIT 79 arch/x86/include/asm/hyperv-tlfs.h #define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) BIT 81 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_MSR_GUEST_IDLE_AVAILABLE BIT(10) BIT 86 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_ACCESS_FREQUENCY_MSRS BIT(11) BIT 88 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) BIT 96 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_CREATE_PARTITIONS BIT(0) BIT 97 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_ACCESS_PARTITION_ID BIT(1) BIT 98 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_ACCESS_MEMORY_POOL BIT(2) BIT 99 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_ADJUST_MESSAGE_BUFFERS BIT(3) BIT 100 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_POST_MESSAGES BIT(4) BIT 101 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_SIGNAL_EVENTS BIT(5) BIT 102 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_CREATE_PORT BIT(6) BIT 103 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_CONNECT_PORT BIT(7) BIT 104 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_ACCESS_STATS BIT(8) BIT 105 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_DEBUGGING BIT(11) BIT 106 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_CPU_POWER_MANAGEMENT BIT(12) BIT 114 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_MWAIT_AVAILABLE BIT(0) BIT 116 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) BIT 118 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) BIT 120 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) BIT 125 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4) BIT 127 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) BIT 129 arch/x86/include/asm/hyperv-tlfs.h #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) BIT 131 arch/x86/include/asm/hyperv-tlfs.h #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) BIT 133 arch/x86/include/asm/hyperv-tlfs.h #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) BIT 144 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) BIT 147 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) BIT 152 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) BIT 157 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) BIT 159 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) BIT 165 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) BIT 170 arch/x86/include/asm/hyperv-tlfs.h #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) BIT 175 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) BIT 178 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) BIT 181 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) BIT 188 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_NO_NONARCH_CORESHARING BIT(18) BIT 191 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) BIT 192 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) BIT 193 arch/x86/include/asm/hyperv-tlfs.h #define HV_X64_NESTED_MSR_BITMAP BIT(19) BIT 393 arch/x86/include/asm/hyperv-tlfs.h #define HV_FLUSH_ALL_PROCESSORS BIT(0) BIT 394 arch/x86/include/asm/hyperv-tlfs.h #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) BIT 395 arch/x86/include/asm/hyperv-tlfs.h #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) BIT 396 arch/x86/include/asm/hyperv-tlfs.h #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) BIT 404 arch/x86/include/asm/hyperv-tlfs.h #define HV_HYPERCALL_FAST_BIT BIT(16) BIT 743 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) BIT 744 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) BIT 745 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) BIT 746 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) BIT 747 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) BIT 748 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) BIT 749 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) BIT 750 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) BIT 751 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) BIT 752 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) BIT 753 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) BIT 754 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) BIT 755 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) BIT 756 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) BIT 757 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) BIT 758 arch/x86/include/asm/hyperv-tlfs.h #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) BIT 18 arch/x86/include/asm/imr.h #define IMR_ESRAM_FLUSH BIT(31) BIT 19 arch/x86/include/asm/imr.h #define IMR_CPU_SNOOP BIT(30) /* Applicable only to write */ BIT 20 arch/x86/include/asm/imr.h #define IMR_RMU BIT(29) BIT 21 arch/x86/include/asm/imr.h #define IMR_VC1_SAI_ID3 BIT(15) BIT 22 arch/x86/include/asm/imr.h #define IMR_VC1_SAI_ID2 BIT(14) BIT 23 arch/x86/include/asm/imr.h #define IMR_VC1_SAI_ID1 BIT(13) BIT 24 arch/x86/include/asm/imr.h #define IMR_VC1_SAI_ID0 BIT(12) BIT 25 arch/x86/include/asm/imr.h #define IMR_VC0_SAI_ID3 BIT(11) BIT 26 arch/x86/include/asm/imr.h #define IMR_VC0_SAI_ID2 BIT(10) BIT 27 arch/x86/include/asm/imr.h #define IMR_VC0_SAI_ID1 BIT(9) BIT 28 arch/x86/include/asm/imr.h #define IMR_VC0_SAI_ID0 BIT(8) BIT 29 arch/x86/include/asm/imr.h #define IMR_CPU_0 BIT(1) /* SMM mode */ BIT 30 arch/x86/include/asm/imr.h #define IMR_CPU BIT(0) /* Non SMM mode */ BIT 1423 arch/x86/include/asm/kvm_host.h #define KVM_MMU_ROOT_CURRENT BIT(0) BIT 1424 arch/x86/include/asm/kvm_host.h #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) BIT 225 arch/x86/include/asm/mce.h MCP_TIMESTAMP = BIT(0), /* log time stamp */ BIT 226 arch/x86/include/asm/mce.h MCP_UC = BIT(1), /* log uncorrected errors */ BIT 227 arch/x86/include/asm/mce.h MCP_DONTLOG = BIT(2), /* only clear, don't log */ BIT 45 arch/x86/include/asm/msr-index.h #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ BIT 47 arch/x86/include/asm/msr-index.h #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ BIT 49 arch/x86/include/asm/msr-index.h #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ BIT 52 arch/x86/include/asm/msr-index.h #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ BIT 65 arch/x86/include/asm/msr-index.h #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) BIT 66 arch/x86/include/asm/msr-index.h #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) BIT 83 arch/x86/include/asm/msr-index.h #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ BIT 84 arch/x86/include/asm/msr-index.h #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ BIT 85 arch/x86/include/asm/msr-index.h #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ BIT 86 arch/x86/include/asm/msr-index.h #define ARCH_CAP_SSB_NO BIT(4) /* BIT 91 arch/x86/include/asm/msr-index.h #define ARCH_CAP_MDS_NO BIT(5) /* BIT 96 arch/x86/include/asm/msr-index.h #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* BIT 103 arch/x86/include/asm/msr-index.h #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ BIT 104 arch/x86/include/asm/msr-index.h #define ARCH_CAP_TAA_NO BIT(8) /* BIT 110 arch/x86/include/asm/msr-index.h #define L1D_FLUSH BIT(0) /* BIT 119 arch/x86/include/asm/msr-index.h #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ BIT 120 arch/x86/include/asm/msr-index.h #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ BIT 124 arch/x86/include/asm/msr-index.h #define RNGDS_MITG_DIS BIT(0) BIT 161 arch/x86/include/asm/msr-index.h #define RTIT_CTL_TRACEEN BIT(0) BIT 162 arch/x86/include/asm/msr-index.h #define RTIT_CTL_CYCLEACC BIT(1) BIT 163 arch/x86/include/asm/msr-index.h #define RTIT_CTL_OS BIT(2) BIT 164 arch/x86/include/asm/msr-index.h #define RTIT_CTL_USR BIT(3) BIT 165 arch/x86/include/asm/msr-index.h #define RTIT_CTL_PWR_EVT_EN BIT(4) BIT 166 arch/x86/include/asm/msr-index.h #define RTIT_CTL_FUP_ON_PTW BIT(5) BIT 167 arch/x86/include/asm/msr-index.h #define RTIT_CTL_FABRIC_EN BIT(6) BIT 168 arch/x86/include/asm/msr-index.h #define RTIT_CTL_CR3EN BIT(7) BIT 169 arch/x86/include/asm/msr-index.h #define RTIT_CTL_TOPA BIT(8) BIT 170 arch/x86/include/asm/msr-index.h #define RTIT_CTL_MTC_EN BIT(9) BIT 171 arch/x86/include/asm/msr-index.h #define RTIT_CTL_TSC_EN BIT(10) BIT 172 arch/x86/include/asm/msr-index.h #define RTIT_CTL_DISRETC BIT(11) BIT 173 arch/x86/include/asm/msr-index.h #define RTIT_CTL_PTW_EN BIT(12) BIT 174 arch/x86/include/asm/msr-index.h #define RTIT_CTL_BRANCH_EN BIT(13) BIT 190 arch/x86/include/asm/msr-index.h #define RTIT_STATUS_FILTEREN BIT(0) BIT 191 arch/x86/include/asm/msr-index.h #define RTIT_STATUS_CONTEXTEN BIT(1) BIT 192 arch/x86/include/asm/msr-index.h #define RTIT_STATUS_TRIGGEREN BIT(2) BIT 193 arch/x86/include/asm/msr-index.h #define RTIT_STATUS_BUFFOVF BIT(3) BIT 194 arch/x86/include/asm/msr-index.h #define RTIT_STATUS_ERROR BIT(4) BIT 195 arch/x86/include/asm/msr-index.h #define RTIT_STATUS_STOPPED BIT(5) BIT 22 arch/x86/include/asm/mwait.h #define MWAITX_ECX_TIMER_ENABLE BIT(1) BIT 1259 arch/x86/include/asm/pgtable.h __ptr |= BIT(bit); BIT 1266 arch/x86/include/asm/pgtable.h __ptr &= ~BIT(bit); BIT 10 arch/x86/include/asm/realmode.h #define TH_FLAGS_SME_ACTIVE BIT(TH_FLAGS_SME_ACTIVE_BIT) BIT 111 arch/x86/include/asm/set_memory.h decoy_addr = (pfn << PAGE_SHIFT) + (PAGE_OFFSET ^ BIT(63)); BIT 151 arch/x86/include/asm/svm.h #define SVM_NESTED_CTL_NP_ENABLE BIT(0) BIT 152 arch/x86/include/asm/svm.h #define SVM_NESTED_CTL_SEV_ENABLE BIT(1) BIT 28 arch/x86/include/asm/vmware.h #define VMWARE_HYPERVISOR_HB BIT(0) BIT 29 arch/x86/include/asm/vmware.h #define VMWARE_HYPERVISOR_OUT BIT(1) BIT 516 arch/x86/kernel/amd_nb.c if (val & BIT(2)) BIT 522 arch/x86/kernel/cpu/amd.c if (!(val & BIT(24))) BIT 652 arch/x86/kernel/cpu/amd.c if (c->x86_power & BIT(12)) BIT 839 arch/x86/kernel/cpu/amd.c if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) BIT 848 arch/x86/kernel/cpu/amd.c if (cpuid_ecx(1) & BIT(30)) { BIT 315 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[0] = sc0 = !(val & BIT(0)); BIT 316 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[1] = sc1 = !(val & BIT(4)); BIT 319 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[0] = sc0 += !(val & BIT(1)); BIT 320 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[1] = sc1 += !(val & BIT(5)); BIT 323 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9)); BIT 324 arch/x86/kernel/cpu/cacheinfo.c l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13)); BIT 378 arch/x86/kernel/cpu/cacheinfo.c idx |= BIT(30); BIT 398 arch/x86/kernel/cpu/cacheinfo.c reg |= BIT(31); BIT 1019 arch/x86/kernel/cpu/common.c #define NO_SPECULATION BIT(0) BIT 1020 arch/x86/kernel/cpu/common.c #define NO_MELTDOWN BIT(1) BIT 1021 arch/x86/kernel/cpu/common.c #define NO_SSB BIT(2) BIT 1022 arch/x86/kernel/cpu/common.c #define NO_L1TF BIT(3) BIT 1023 arch/x86/kernel/cpu/common.c #define NO_MDS BIT(4) BIT 1024 arch/x86/kernel/cpu/common.c #define MSBDS_ONLY BIT(5) BIT 1025 arch/x86/kernel/cpu/common.c #define NO_SWAPGS BIT(6) BIT 1026 arch/x86/kernel/cpu/common.c #define NO_ITLB_MULTIHIT BIT(7) BIT 1027 arch/x86/kernel/cpu/common.c #define NO_SPECTRE_V2 BIT(8) BIT 1101 arch/x86/kernel/cpu/common.c #define SRBDS BIT(0) BIT 227 arch/x86/kernel/cpu/hygon.c if (!(val & BIT(24))) BIT 280 arch/x86/kernel/cpu/hygon.c if (c->x86_power & BIT(12)) BIT 47 arch/x86/kernel/cpu/match.c !(BIT(c->x86_stepping) & m->steppings)) BIT 225 arch/x86/kernel/cpu/mce/amd.c per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); BIT 247 arch/x86/kernel/cpu/mce/amd.c high |= BIT(0); BIT 260 arch/x86/kernel/cpu/mce/amd.c if ((low & BIT(5)) && !((high >> 5) & 0x3)) BIT 261 arch/x86/kernel/cpu/mce/amd.c high |= BIT(5); BIT 344 arch/x86/kernel/cpu/mce/amd.c return msr_high_bits & BIT(28); BIT 484 arch/x86/kernel/cpu/mce/amd.c if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank))) BIT 612 arch/x86/kernel/cpu/mce/amd.c need_toggle = !(hwcr & BIT(18)); BIT 614 arch/x86/kernel/cpu/mce/amd.c wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); BIT 683 arch/x86/kernel/cpu/mce/amd.c if (tmp & BIT(0)) { BIT 697 arch/x86/kernel/cpu/mce/amd.c if (!(tmp & BIT(0))) { BIT 703 arch/x86/kernel/cpu/mce/amd.c lgcy_mmio_hole_en = tmp & BIT(1); BIT 844 arch/x86/kernel/cpu/mce/amd.c hashed_bit &= BIT(0); BIT 846 arch/x86/kernel/cpu/mce/amd.c if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) BIT 847 arch/x86/kernel/cpu/mce/amd.c ret_addr ^= BIT(intlv_addr_bit); BIT 527 arch/x86/kernel/cpu/mce/core.c return (m->status & 0xef80) == BIT(7) || BIT 528 arch/x86/kernel/cpu/mce/core.c (m->status & 0xef00) == BIT(8) || BIT 311 arch/x86/kernel/cpu/mce/inject.c enable ? (l |= BIT(18)) : (l &= ~BIT(18)); BIT 444 arch/x86/kernel/cpu/mce/inject.c if (val & BIT(27)) BIT 450 arch/x86/kernel/cpu/mce/inject.c val |= BIT(27); BIT 134 arch/x86/kernel/cpu/microcode/core.c if (native_cpuid_ecx(1) & BIT(31)) BIT 223 arch/x86/kernel/cpu/resctrl/internal.h #define RFTYPE_INFO BIT(0) BIT 224 arch/x86/kernel/cpu/resctrl/internal.h #define RFTYPE_BASE BIT(1) BIT 228 arch/x86/kernel/cpu/resctrl/internal.h #define RFTYPE_CTRL BIT(RF_CTRLSHIFT) BIT 229 arch/x86/kernel/cpu/resctrl/internal.h #define RFTYPE_MON BIT(RF_MONSHIFT) BIT 230 arch/x86/kernel/cpu/resctrl/internal.h #define RFTYPE_TOP BIT(RF_TOPSHIFT) BIT 231 arch/x86/kernel/cpu/resctrl/internal.h #define RFTYPE_RES_CACHE BIT(8) BIT 232 arch/x86/kernel/cpu/resctrl/internal.h #define RFTYPE_RES_MB BIT(9) BIT 2718 arch/x86/kernel/cpu/resctrl/rdtgroup.c files = RFTYPE_BASE | BIT(RF_CTRLSHIFT + rtype); BIT 40 arch/x86/kernel/cpu/vmware.c #define CPUID_VMWARE_FEATURES_ECX_VMMCALL BIT(0) BIT 41 arch/x86/kernel/cpu/vmware.c #define CPUID_VMWARE_FEATURES_ECX_VMCALL BIT(1) BIT 756 arch/x86/kernel/fpu/xstate.c xfeatures_mask &= ~BIT(i); BIT 618 arch/x86/kernel/quirks.c if (val & BIT(0)) { BIT 619 arch/x86/kernel/quirks.c val &= ~BIT(0); BIT 42 arch/x86/kernel/vsmp_64.c if (cap & ctl & BIT(8)) { BIT 43 arch/x86/kernel/vsmp_64.c ctl &= ~BIT(8); BIT 3046 arch/x86/kvm/mmu.c #define SET_SPTE_WRITE_PROTECTED_PT BIT(0) BIT 3047 arch/x86/kvm/mmu.c #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1) BIT 455 arch/x86/kvm/x86.c vcpu->arch.dr6 &= ~BIT(12); BIT 115 arch/x86/kvm/x86.h static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) | BIT 116 arch/x86/kvm/x86.h BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) | BIT 117 arch/x86/kvm/x86.h BIT(PF_VECTOR) | BIT(AC_VECTOR); BIT 765 arch/x86/lib/insn-eval.c if (!(desc.type & BIT(3))) BIT 504 arch/x86/mm/mem_encrypt_identity.c #define AMD_SME_BIT BIT(0) BIT 505 arch/x86/mm/mem_encrypt_identity.c #define AMD_SEV_BIT BIT(1) BIT 513 arch/x86/mm/mem_encrypt_identity.c feature_mask = (ecx & BIT(31)) ? AMD_SEV_BIT : AMD_SME_BIT; BIT 637 arch/x86/mm/pti.c if (cpuid_ecx(0x1) & BIT(17)) { BIT 133 arch/x86/net/bpf_jit_comp.c return (1 << reg) & (BIT(BPF_REG_5) | BIT 134 arch/x86/net/bpf_jit_comp.c BIT(AUX_REG) | BIT 135 arch/x86/net/bpf_jit_comp.c BIT(BPF_REG_7) | BIT 136 arch/x86/net/bpf_jit_comp.c BIT(BPF_REG_8) | BIT 137 arch/x86/net/bpf_jit_comp.c BIT(BPF_REG_9) | BIT 138 arch/x86/net/bpf_jit_comp.c BIT(BPF_REG_AX)); BIT 149 arch/x86/net/bpf_jit_comp.c (1 << reg) & (BIT(BPF_REG_1) | BIT 150 arch/x86/net/bpf_jit_comp.c BIT(BPF_REG_2) | BIT 151 arch/x86/net/bpf_jit_comp.c BIT(BPF_REG_FP)); BIT 672 arch/x86/pci/fixup.c #define AMD_141b_MMIO_BASE_RE_MASK BIT(0) BIT 673 arch/x86/pci/fixup.c #define AMD_141b_MMIO_BASE_WE_MASK BIT(1) BIT 62 arch/x86/platform/intel-quark/imr.c #define IMR_LOCK BIT(31) BIT 202 arch/x86/platform/intel/iosf_mbi.c #define PUNIT_SEMAPHORE_BIT BIT(0) BIT 203 arch/x86/platform/intel/iosf_mbi.c #define PUNIT_SEMAPHORE_ACQUIRE BIT(1) BIT 33 arch/x86/platform/ts5500/ts5500.c #define TS5500_SRAM BIT(0) /* SRAM option */ BIT 34 arch/x86/platform/ts5500/ts5500.c #define TS5500_RS485 BIT(1) /* RS-485 option */ BIT 35 arch/x86/platform/ts5500/ts5500.c #define TS5500_ADC BIT(2) /* A/D converter option */ BIT 36 arch/x86/platform/ts5500/ts5500.c #define TS5500_RS485_RTS BIT(6) /* RTS for RS-485 */ BIT 37 arch/x86/platform/ts5500/ts5500.c #define TS5500_RS485_AUTO BIT(7) /* Automatic RS-485 */ BIT 41 arch/x86/platform/ts5500/ts5500.c #define TS5500_ERESET BIT(0) /* External Reset option */ BIT 42 arch/x86/platform/ts5500/ts5500.c #define TS5500_ITR BIT(1) /* Indust. Temp. Range option */ BIT 46 arch/x86/platform/ts5500/ts5500.c #define TS5500_LED BIT(0) /* LED flag */ BIT 47 arch/x86/platform/ts5500/ts5500.c #define TS5500_JP1 BIT(1) /* Automatic CMOS */ BIT 48 arch/x86/platform/ts5500/ts5500.c #define TS5500_JP2 BIT(2) /* Enable Serial Console */ BIT 49 arch/x86/platform/ts5500/ts5500.c #define TS5500_JP3 BIT(3) /* Write Enable Drive A */ BIT 50 arch/x86/platform/ts5500/ts5500.c #define TS5500_JP4 BIT(4) /* Fast Console (115K baud) */ BIT 51 arch/x86/platform/ts5500/ts5500.c #define TS5500_JP5 BIT(5) /* User Jumper */ BIT 52 arch/x86/platform/ts5500/ts5500.c #define TS5500_JP6 BIT(6) /* Console on COM1 (req. JP2) */ BIT 53 arch/x86/platform/ts5500/ts5500.c #define TS5500_JP7 BIT(7) /* Undocumented (Unused) */ BIT 57 arch/x86/platform/ts5500/ts5500.c #define TS5500_ADC_CONV_BUSY BIT(0) BIT 278 arch/xtensa/kernel/hw_breakpoint.c if (regs->debugcause & BIT(DEBUGCAUSE_IBREAK_BIT)) { BIT 288 arch/xtensa/kernel/hw_breakpoint.c } else if (regs->debugcause & BIT(DEBUGCAUSE_DBREAK_BIT)) { BIT 456 arch/xtensa/kernel/setup.c if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT)) BIT 458 arch/xtensa/kernel/setup.c if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT)) BIT 226 arch/xtensa/kernel/traps.c BIT(XCHAL_PROFILING_INTERRUPT))); BIT 82 block/blk-mq-debugfs.c if (!(flags & BIT(i))) BIT 426 crypto/testmgr.c #define SGDIVS_HAVE_FLUSHES BIT(0) BIT 427 crypto/testmgr.c #define SGDIVS_HAVE_NOSIMD BIT(1) BIT 29 drivers/acpi/acpi_apd.c #define ACPI_APD_SYSFS BIT(0) BIT 30 drivers/acpi/acpi_apd.c #define ACPI_APD_PM BIT(1) BIT 26 drivers/acpi/acpi_extlog.c #define FLAG_OS_OPTIN BIT(0) BIT 43 drivers/acpi/acpi_lpss.c #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) BIT 45 drivers/acpi/acpi_lpss.c #define LPSS_RESETS_RESET_FUNC BIT(0) BIT 46 drivers/acpi/acpi_lpss.c #define LPSS_RESETS_RESET_APB BIT(1) BIT 48 drivers/acpi/acpi_lpss.c #define LPSS_GENERAL_LTR_MODE_SW BIT(2) BIT 49 drivers/acpi/acpi_lpss.c #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) BIT 52 drivers/acpi/acpi_lpss.c #define LPSS_LTR_SNOOP_REQ BIT(15) BIT 60 drivers/acpi/acpi_lpss.c #define LPSS_TX_INT_MASK BIT(1) BIT 65 drivers/acpi/acpi_lpss.c #define LPSS_CLK BIT(0) BIT 66 drivers/acpi/acpi_lpss.c #define LPSS_CLK_GATE BIT(1) BIT 67 drivers/acpi/acpi_lpss.c #define LPSS_CLK_DIVIDER BIT(2) BIT 68 drivers/acpi/acpi_lpss.c #define LPSS_LTR BIT(3) BIT 69 drivers/acpi/acpi_lpss.c #define LPSS_SAVE_CTX BIT(4) BIT 70 drivers/acpi/acpi_lpss.c #define LPSS_NO_D3_DELAY BIT(5) BIT 120 drivers/acpi/acpi_lpss.c #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) BIT 124 drivers/acpi/acpi_lpss.c #define LPSS_UART_CPR_AFCE BIT(4) BIT 931 drivers/acpi/acpi_lpss.c #define LPSS_GPIODEF0_DMA1_D3 BIT(2) BIT 932 drivers/acpi/acpi_lpss.c #define LPSS_GPIODEF0_DMA2_D3 BIT(3) BIT 934 drivers/acpi/acpi_lpss.c #define LPSS_GPIODEF0_DMA_LLP BIT(13) BIT 34 drivers/acpi/acpi_tad.c #define ACPI_TAD_AC_WAKE BIT(0) BIT 35 drivers/acpi/acpi_tad.c #define ACPI_TAD_DC_WAKE BIT(1) BIT 36 drivers/acpi/acpi_tad.c #define ACPI_TAD_RT BIT(2) BIT 37 drivers/acpi/acpi_tad.c #define ACPI_TAD_RT_IN_MS BIT(3) BIT 38 drivers/acpi/acpi_tad.c #define ACPI_TAD_S4_S5__GWS BIT(4) BIT 39 drivers/acpi/acpi_tad.c #define ACPI_TAD_AC_S4_WAKE BIT(5) BIT 40 drivers/acpi/acpi_tad.c #define ACPI_TAD_AC_S5_WAKE BIT(6) BIT 41 drivers/acpi/acpi_tad.c #define ACPI_TAD_DC_S4_WAKE BIT(7) BIT 42 drivers/acpi/acpi_tad.c #define ACPI_TAD_DC_S5_WAKE BIT(8) BIT 1949 drivers/acpi/acpi_video.c input->evbit[0] = BIT(EV_KEY); BIT 34 drivers/acpi/apei/einj.c #define ACPI5_VENDOR_BIT BIT(31) BIT 39 drivers/acpi/nfit/intel.c return BIT(NVDIMM_SECURITY_OVERWRITE); BIT 19 drivers/acpi/pmic/intel_pmic_bxtwc.c #define VR_MODE_AUTO BIT(0) BIT 20 drivers/acpi/pmic/intel_pmic_bxtwc.c #define VR_MODE_NORMAL BIT(1) BIT 21 drivers/acpi/pmic/intel_pmic_bxtwc.c #define VR_MODE_SWITCH BIT(2) BIT 22 drivers/acpi/pmic/intel_pmic_bxtwc.c #define VR_MODE_ECO (BIT(0)|BIT(1)) BIT 23 drivers/acpi/pmic/intel_pmic_bxtwc.c #define VSWITCH2_OUTPUT BIT(5) BIT 24 drivers/acpi/pmic/intel_pmic_bxtwc.c #define VSWITCH1_OUTPUT BIT(4) BIT 25 drivers/acpi/pmic/intel_pmic_bxtwc.c #define VUSBPHY_CHARGE BIT(1) BIT 171 drivers/acpi/pmic/intel_pmic_bxtwc.c .bit = BIT(2), BIT 176 drivers/acpi/pmic/intel_pmic_bxtwc.c .bit = BIT(0), BIT 353 drivers/acpi/pmic/intel_pmic_bxtwc.c u8 mask = BIT(bit); BIT 367 drivers/acpi/pmic/intel_pmic_bxtwc.c u8 mask = BIT(bit), val = enable << bit; BIT 15 drivers/acpi/pmic/intel_pmic_crc.c #define PWR_SOURCE_SELECT BIT(1) BIT 196 drivers/acpi/pmic/intel_pmic_crc.c *value = (data & PWR_SOURCE_SELECT) && (data & BIT(bit)) ? 1 : 0; BIT 209 drivers/acpi/pmic/intel_pmic_crc.c data |= PWR_SOURCE_SELECT | BIT(bit); BIT 211 drivers/acpi/pmic/intel_pmic_crc.c data &= ~BIT(bit); BIT 171 drivers/acpi/pmic/intel_pmic_xpower.c *value = (data & BIT(bit)) ? 1 : 0; BIT 196 drivers/acpi/pmic/intel_pmic_xpower.c data |= BIT(bit); BIT 198 drivers/acpi/pmic/intel_pmic_xpower.c data &= ~BIT(bit); BIT 34 drivers/acpi/pmic/tps68470_pmic.c #define S_IO_I2C_EN (BIT(0) | BIT(1)) BIT 46 drivers/acpi/pmic/tps68470_pmic.c .bitmask = BIT(0), BIT 52 drivers/acpi/pmic/tps68470_pmic.c .bitmask = BIT(0), BIT 58 drivers/acpi/pmic/tps68470_pmic.c .bitmask = BIT(0), BIT 64 drivers/acpi/pmic/tps68470_pmic.c .bitmask = BIT(0), BIT 70 drivers/acpi/pmic/tps68470_pmic.c .bitmask = BIT(0), BIT 126 drivers/acpi/pmic/tps68470_pmic.c .bitmask = BIT(0) | BIT(1), BIT 178 drivers/acpi/pmic/tps68470_pmic.c .bitmask = BIT(0), BIT 1111 drivers/acpi/processor_idle.c #define ACPI_LPI_STATE_FLAGS_ENABLED BIT(0) BIT 274 drivers/acpi/processor_perflib.c if (!(hi & BIT(31))) BIT 28 drivers/amba/tegra-ahb.c #define PRIORITY_SELECT_USB BIT(6) BIT 29 drivers/amba/tegra-ahb.c #define PRIORITY_SELECT_USB2 BIT(18) BIT 30 drivers/amba/tegra-ahb.c #define PRIORITY_SELECT_USB3 BIT(17) BIT 33 drivers/amba/tegra-ahb.c #define ENB_FAST_REARBITRATE BIT(2) BIT 34 drivers/amba/tegra-ahb.c #define DONT_SPLIT_AHB_WR BIT(7) BIT 52 drivers/amba/tegra-ahb.c #define IMMEDIATE BIT(18) BIT 63 drivers/amba/tegra-ahb.c #define PREFETCH_ENB BIT(31) BIT 74 drivers/amba/tegra-ahb.c #define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17) BIT 37 drivers/ata/ahci_brcm.c #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14) BIT 39 drivers/ata/ahci_brcm.c #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0) BIT 40 drivers/ata/ahci_brcm.c #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1) BIT 41 drivers/ata/ahci_brcm.c #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2) BIT 42 drivers/ata/ahci_brcm.c #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3) BIT 43 drivers/ata/ahci_brcm.c #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14) BIT 79 drivers/ata/ahci_brcm.c BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(0), BIT 134 drivers/ata/ahci_brcm.c if (priv->port_mask & BIT(i)) BIT 202 drivers/ata/ahci_brcm.c if (priv->port_mask & BIT(i)) BIT 211 drivers/ata/ahci_brcm.c if (priv->port_mask & BIT(i)) BIT 35 drivers/ata/ahci_da850.c val &= ~BIT(0); BIT 62 drivers/ata/ahci_imx.c IMX8QM_PHY_APB_RSTN_0 = BIT(0), BIT 63 drivers/ata/ahci_imx.c IMX8QM_PHY_MODE_SATA = BIT(19), BIT 65 drivers/ata/ahci_imx.c IMX8QM_PHY_PIPE_RSTN_0 = BIT(24), BIT 66 drivers/ata/ahci_imx.c IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0 = BIT(25), BIT 67 drivers/ata/ahci_imx.c IMX8QM_PHY_PIPE_RSTN_1 = BIT(26), BIT 68 drivers/ata/ahci_imx.c IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1 = BIT(27), BIT 69 drivers/ata/ahci_imx.c IMX8QM_STTS0_LANE0_TX_PLL_LOCK = BIT(4), BIT 70 drivers/ata/ahci_imx.c IMX8QM_MISC_IOB_RXENA = BIT(0), BIT 71 drivers/ata/ahci_imx.c IMX8QM_MISC_IOB_TXENA = BIT(1), BIT 72 drivers/ata/ahci_imx.c IMX8QM_MISC_PHYX1_EPCS_SEL = BIT(12), BIT 73 drivers/ata/ahci_imx.c IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 = BIT(24), BIT 74 drivers/ata/ahci_imx.c IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 = BIT(25), BIT 75 drivers/ata/ahci_imx.c IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 = BIT(28), BIT 76 drivers/ata/ahci_imx.c IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 = BIT(29), BIT 77 drivers/ata/ahci_imx.c IMX8QM_SATA_CTRL_RESET_N = BIT(12), BIT 78 drivers/ata/ahci_imx.c IMX8QM_SATA_CTRL_EPCS_PHYRESET_N = BIT(7), BIT 79 drivers/ata/ahci_imx.c IMX8QM_CTRL_BUTTON_RST_N = BIT(21), BIT 80 drivers/ata/ahci_imx.c IMX8QM_CTRL_POWER_UP_RST_N = BIT(23), BIT 81 drivers/ata/ahci_imx.c IMX8QM_CTRL_LTSSM_ENABLE = BIT(4), BIT 24 drivers/ata/ahci_mtk.c #define SYS_CFG_SATA_EN BIT(31) BIT 93 drivers/ata/ahci_mvebu.c reg |= BIT(6); BIT 26 drivers/ata/ahci_st.c #define ST_AHCI_OOBR_WE BIT(31) BIT 95 drivers/ata/ahci_sunxi.c sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); BIT 98 drivers/ata/ahci_sunxi.c (0x5 << 24) | BIT(23) | BIT(18)); BIT 102 drivers/ata/ahci_sunxi.c sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); BIT 103 drivers/ata/ahci_sunxi.c sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); BIT 28 drivers/ata/ahci_tegra.c #define SATA_CONFIGURATION_0_EN_FPCI BIT(0) BIT 29 drivers/ata/ahci_tegra.c #define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31) BIT 34 drivers/ata/ahci_tegra.c #define T_SATA0_CFG_1_IO_SPACE BIT(0) BIT 35 drivers/ata/ahci_tegra.c #define T_SATA0_CFG_1_MEMORY_SPACE BIT(1) BIT 36 drivers/ata/ahci_tegra.c #define T_SATA0_CFG_1_BUS_MASTER BIT(2) BIT 37 drivers/ata/ahci_tegra.c #define T_SATA0_CFG_1_SERR BIT(8) BIT 48 drivers/ata/ahci_tegra.c #define SATA_INTR_MASK_IP_INT_MASK BIT(16) BIT 58 drivers/ata/ahci_tegra.c #define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23) BIT 59 drivers/ata/ahci_tegra.c #define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22) BIT 70 drivers/ata/ahci_tegra.c #define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11) BIT 71 drivers/ata/ahci_tegra.c #define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24) BIT 78 drivers/ata/ahci_tegra.c #define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13) BIT 79 drivers/ata/ahci_tegra.c #define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14) BIT 80 drivers/ata/ahci_tegra.c #define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26) BIT 81 drivers/ata/ahci_tegra.c #define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17) BIT 82 drivers/ata/ahci_tegra.c #define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30) BIT 91 drivers/ata/ahci_tegra.c #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12) BIT 126 drivers/ata/ahci_tegra.c #define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17) BIT 127 drivers/ata/ahci_tegra.c #define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13) BIT 128 drivers/ata/ahci_tegra.c #define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15) BIT 131 drivers/ata/ahci_tegra.c #define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7) BIT 134 drivers/ata/ahci_tegra.c #define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14) BIT 203 drivers/ata/ahci_tegra.c writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); BIT 500 drivers/ata/libahci_platform.c mask_port_map |= BIT(port); BIT 2247 drivers/ata/libata-core.c if (ap->sector_buf[ATA_LOG_NCQ_PRIO_OFFSET] & BIT(3)) { BIT 245 drivers/ata/pata_bk3710.c iowrite16(BIT(15), base + BK3710_IDETIMP); BIT 78 drivers/ata/pata_ftide010.c #define FTIDE010_UDMA_TIMING_MODE_56 BIT(7) BIT 81 drivers/ata/pata_ftide010.c #define FTIDE010_CLK_MOD_DEV0_CLK_SEL BIT(0) BIT 82 drivers/ata/pata_ftide010.c #define FTIDE010_CLK_MOD_DEV1_CLK_SEL BIT(1) BIT 84 drivers/ata/pata_ftide010.c #define FTIDE010_CLK_MOD_DEV0_UDMA_EN BIT(4) BIT 85 drivers/ata/pata_ftide010.c #define FTIDE010_CLK_MOD_DEV1_UDMA_EN BIT(5) BIT 96 drivers/ata/sata_gemini.c #define GEMINI_SATA_STATUS_BIST_DONE BIT(5) BIT 97 drivers/ata/sata_gemini.c #define GEMINI_SATA_STATUS_BIST_OK BIT(4) BIT 98 drivers/ata/sata_gemini.c #define GEMINI_SATA_STATUS_PHY_READY BIT(0) BIT 100 drivers/ata/sata_gemini.c #define GEMINI_SATA_CTRL_PHY_BIST_EN BIT(14) BIT 101 drivers/ata/sata_gemini.c #define GEMINI_SATA_CTRL_PHY_FORCE_IDLE BIT(13) BIT 102 drivers/ata/sata_gemini.c #define GEMINI_SATA_CTRL_PHY_FORCE_READY BIT(12) BIT 103 drivers/ata/sata_gemini.c #define GEMINI_SATA_CTRL_PHY_AFE_LOOP_EN BIT(10) BIT 104 drivers/ata/sata_gemini.c #define GEMINI_SATA_CTRL_PHY_DIG_LOOP_EN BIT(9) BIT 105 drivers/ata/sata_gemini.c #define GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN BIT(4) BIT 106 drivers/ata/sata_gemini.c #define GEMINI_SATA_CTRL_ATAPI_EN BIT(3) BIT 107 drivers/ata/sata_gemini.c #define GEMINI_SATA_CTRL_BUS_WITH_20 BIT(2) BIT 108 drivers/ata/sata_gemini.c #define GEMINI_SATA_CTRL_SLAVE_EN BIT(1) BIT 109 drivers/ata/sata_gemini.c #define GEMINI_SATA_CTRL_EN BIT(0) BIT 37 drivers/ata/sata_rcar.c #define ATAPI_CONTROL1_ISM BIT(16) BIT 38 drivers/ata/sata_rcar.c #define ATAPI_CONTROL1_DTA32M BIT(11) BIT 39 drivers/ata/sata_rcar.c #define ATAPI_CONTROL1_RESET BIT(7) BIT 40 drivers/ata/sata_rcar.c #define ATAPI_CONTROL1_DESE BIT(3) BIT 41 drivers/ata/sata_rcar.c #define ATAPI_CONTROL1_RW BIT(2) BIT 42 drivers/ata/sata_rcar.c #define ATAPI_CONTROL1_STOP BIT(1) BIT 43 drivers/ata/sata_rcar.c #define ATAPI_CONTROL1_START BIT(0) BIT 46 drivers/ata/sata_rcar.c #define ATAPI_STATUS_SATAINT BIT(11) BIT 47 drivers/ata/sata_rcar.c #define ATAPI_STATUS_DNEND BIT(6) BIT 48 drivers/ata/sata_rcar.c #define ATAPI_STATUS_DEVTRM BIT(5) BIT 49 drivers/ata/sata_rcar.c #define ATAPI_STATUS_DEVINT BIT(4) BIT 50 drivers/ata/sata_rcar.c #define ATAPI_STATUS_ERR BIT(2) BIT 51 drivers/ata/sata_rcar.c #define ATAPI_STATUS_NEND BIT(1) BIT 52 drivers/ata/sata_rcar.c #define ATAPI_STATUS_ACT BIT(0) BIT 55 drivers/ata/sata_rcar.c #define ATAPI_INT_ENABLE_SATAINT BIT(11) BIT 56 drivers/ata/sata_rcar.c #define ATAPI_INT_ENABLE_DNEND BIT(6) BIT 57 drivers/ata/sata_rcar.c #define ATAPI_INT_ENABLE_DEVTRM BIT(5) BIT 58 drivers/ata/sata_rcar.c #define ATAPI_INT_ENABLE_DEVINT BIT(4) BIT 59 drivers/ata/sata_rcar.c #define ATAPI_INT_ENABLE_ERR BIT(2) BIT 60 drivers/ata/sata_rcar.c #define ATAPI_INT_ENABLE_NEND BIT(1) BIT 61 drivers/ata/sata_rcar.c #define ATAPI_INT_ENABLE_ACT BIT(0) BIT 72 drivers/ata/sata_rcar.c #define SATAPHYADDR_PHYRATEMODE BIT(10) BIT 73 drivers/ata/sata_rcar.c #define SATAPHYADDR_PHYCMD_READ BIT(9) BIT 74 drivers/ata/sata_rcar.c #define SATAPHYADDR_PHYCMD_WRITE BIT(8) BIT 77 drivers/ata/sata_rcar.c #define SATAPHYACCEN_PHYLANE BIT(0) BIT 80 drivers/ata/sata_rcar.c #define SATAPHYRESET_PHYRST BIT(1) BIT 81 drivers/ata/sata_rcar.c #define SATAPHYRESET_PHYSRES BIT(0) BIT 84 drivers/ata/sata_rcar.c #define SATAPHYACK_PHYACK BIT(0) BIT 100 drivers/ata/sata_rcar.c #define SATAINTSTAT_SERR BIT(3) BIT 101 drivers/ata/sata_rcar.c #define SATAINTSTAT_ATA BIT(0) BIT 104 drivers/ata/sata_rcar.c #define SATAINTMASK_SERRMSK BIT(3) BIT 105 drivers/ata/sata_rcar.c #define SATAINTMASK_ERRMSK BIT(2) BIT 106 drivers/ata/sata_rcar.c #define SATAINTMASK_ERRCRTMSK BIT(1) BIT 107 drivers/ata/sata_rcar.c #define SATAINTMASK_ATAMSK BIT(0) BIT 121 drivers/ata/sata_rcar.c #define SATA_RCAR_DTEND BIT(0) BIT 141 drivers/ata/sata_rcar.c #define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */ BIT 142 drivers/ata/sata_rcar.c #define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */ BIT 540 drivers/ata/sata_via.c pci_write_config_byte(pdev, 0x52, tmp8 | BIT(2)); BIT 25 drivers/auxdisplay/ht16k33.c #define REG_SYSTEM_SETUP_OSC_ON BIT(0) BIT 28 drivers/auxdisplay/ht16k33.c #define REG_DISPLAY_SETUP_ON BIT(0) BIT 31 drivers/auxdisplay/ht16k33.c #define REG_ROWINT_SET_INT_EN BIT(0) BIT 32 drivers/auxdisplay/ht16k33.c #define REG_ROWINT_SET_INT_ACT_HIGH BIT(1) BIT 273 drivers/auxdisplay/ht16k33.c new_state[col] & BIT(row)); BIT 1199 drivers/auxdisplay/panel.c bitval = BIT(bit); BIT 1451 drivers/auxdisplay/panel.c im |= BIT(in); BIT 1456 drivers/auxdisplay/panel.c om |= BIT(out); BIT 34 drivers/base/firmware_loader/firmware.h FW_OPT_UEVENT = BIT(0), BIT 35 drivers/base/firmware_loader/firmware.h FW_OPT_NOWAIT = BIT(1), BIT 36 drivers/base/firmware_loader/firmware.h FW_OPT_USERHELPER = BIT(2), BIT 37 drivers/base/firmware_loader/firmware.h FW_OPT_NO_WARN = BIT(3), BIT 38 drivers/base/firmware_loader/firmware.h FW_OPT_NOCACHE = BIT(4), BIT 39 drivers/base/firmware_loader/firmware.h FW_OPT_NOFALLBACK = BIT(5), BIT 26 drivers/base/power/power.h #define WAKE_IRQ_DEDICATED_ALLOCATED BIT(0) BIT 27 drivers/base/power/power.h #define WAKE_IRQ_DEDICATED_MANAGED BIT(1) BIT 68 drivers/bcma/driver_chipcommon_pmu.c BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT)); BIT 81 drivers/bcma/driver_gpio.c u32 val = bcma_chipco_gpio_in(cc, BIT(gpio)); BIT 83 drivers/bcma/driver_gpio.c bcma_chipco_gpio_polarity(cc, BIT(gpio), val); BIT 84 drivers/bcma/driver_gpio.c bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio)); BIT 93 drivers/bcma/driver_gpio.c bcma_chipco_gpio_intmask(cc, BIT(gpio), 0); BIT 227 drivers/bcma/driver_mips.c else if (cc->status & BIT(5)) BIT 379 drivers/bcma/host_pci.c coremask = BIT(core->core_index) << 8; BIT 98 drivers/block/zram/zram_drv.c return zram->table[index].flags & BIT(flag); BIT 104 drivers/block/zram/zram_drv.c zram->table[index].flags |= BIT(flag); BIT 110 drivers/block/zram/zram_drv.c zram->table[index].flags &= ~BIT(flag); BIT 126 drivers/block/zram/zram_drv.c return zram->table[index].flags & (BIT(ZRAM_FLAG_SHIFT) - 1); BIT 707 drivers/bluetooth/btmrvl_sdio.c if (len & BIT(0)) { BIT 717 drivers/bluetooth/btmrvl_sdio.c len &= ~BIT(0); BIT 51 drivers/bluetooth/btmrvl_sdio.h #define HOST_POWER_UP BIT(1) BIT 52 drivers/bluetooth/btmrvl_sdio.h #define HOST_CMD53_FIN BIT(2) BIT 55 drivers/bluetooth/btmrvl_sdio.h #define HIM_ENABLE (BIT(0) | BIT(1)) BIT 57 drivers/bluetooth/btmrvl_sdio.h #define UP_LD_HOST_INT_STATUS BIT(0) BIT 58 drivers/bluetooth/btmrvl_sdio.h #define DN_LD_HOST_INT_STATUS BIT(1) BIT 60 drivers/bluetooth/btmrvl_sdio.h #define DN_LD_CARD_RDY BIT(0) BIT 61 drivers/bluetooth/btmrvl_sdio.h #define CARD_IO_READY BIT(3) BIT 62 drivers/bluetooth/btmtksdio.c #define C_INT_EN_SET BIT(0) BIT 63 drivers/bluetooth/btmtksdio.c #define C_INT_EN_CLR BIT(1) BIT 64 drivers/bluetooth/btmtksdio.c #define C_FW_OWN_REQ_SET BIT(8) /* For write */ BIT 65 drivers/bluetooth/btmtksdio.c #define C_COM_DRV_OWN BIT(8) /* For read */ BIT 66 drivers/bluetooth/btmtksdio.c #define C_FW_OWN_REQ_CLR BIT(9) BIT 69 drivers/bluetooth/btmtksdio.c #define SDIO_RE_INIT_EN BIT(0) BIT 70 drivers/bluetooth/btmtksdio.c #define SDIO_INT_CTL BIT(2) BIT 73 drivers/bluetooth/btmtksdio.c #define C_INT_CLR_CTRL BIT(1) BIT 78 drivers/bluetooth/btmtksdio.c #define FW_OWN_BACK_INT BIT(0) BIT 79 drivers/bluetooth/btmtksdio.c #define RX_DONE_INT BIT(1) BIT 80 drivers/bluetooth/btmtksdio.c #define TX_EMPTY BIT(2) BIT 81 drivers/bluetooth/btmtksdio.c #define TX_FIFO_OVERFLOW BIT(8) BIT 45 drivers/bluetooth/btmtkuart.c #define BTMTKUART_FLAG_STANDALONE_HW BIT(0) BIT 770 drivers/bluetooth/btrtl.c *flow_control = !!(entry->data[12] & BIT(2)); BIT 717 drivers/bluetooth/hci_ldisc.c unsigned long valid_flags = BIT(HCI_UART_RAW_DEVICE) | BIT 718 drivers/bluetooth/hci_ldisc.c BIT(HCI_UART_RESET_ON_INIT) | BIT 719 drivers/bluetooth/hci_ldisc.c BIT(HCI_UART_CREATE_AMP) | BIT 720 drivers/bluetooth/hci_ldisc.c BIT(HCI_UART_INIT_PENDING) | BIT 721 drivers/bluetooth/hci_ldisc.c BIT(HCI_UART_EXT_CONFIG) | BIT 722 drivers/bluetooth/hci_ldisc.c BIT(HCI_UART_VND_DETECT); BIT 374 drivers/bus/brcmstb_gisb.c if (!(gdev->valid_mask & BIT(i))) BIT 46 drivers/bus/hisi_lpc.c #define LPC_REG_STARTUP_SIGNAL_START BIT(0) BIT 48 drivers/bus/hisi_lpc.c #define LPC_REG_OP_STATUS_IDLE BIT(0) BIT 49 drivers/bus/hisi_lpc.c #define LPC_REG_OP_STATUS_FINISHED BIT(1) BIT 52 drivers/bus/hisi_lpc.c #define LPC_REG_CMD_OP BIT(0) /* 0: read, 1: write */ BIT 53 drivers/bus/hisi_lpc.c #define LPC_REG_CMD_SAMEADDR BIT(3) BIT 43 drivers/bus/imx-weim.c .wcr_bcm = BIT(0), BIT 327 drivers/bus/moxtet.c moxtet->irq.exists |= BIT(first + i); BIT 603 drivers/bus/moxtet.c if (hw >= MOXTET_NIRQS || !(moxtet->irq.exists & BIT(hw))) { BIT 628 drivers/bus/moxtet.c if (irq >= MOXTET_NIRQS || !(moxtet->irq.exists & BIT(irq))) BIT 645 drivers/bus/moxtet.c moxtet->irq.masked |= BIT(d->hwirq); BIT 652 drivers/bus/moxtet.c moxtet->irq.masked &= ~BIT(d->hwirq); BIT 687 drivers/bus/moxtet.c if (!(buf[pos[i].idx + 1] & BIT(4 + pos[i].bit))) BIT 730 drivers/bus/moxtet.c if (moxtet->irq.exists & BIT(i)) { BIT 752 drivers/bus/moxtet.c if (moxtet->irq.exists & BIT(i)) BIT 72 drivers/bus/mvebu-mbus.c #define WIN_CTRL_ENABLE BIT(0) BIT 74 drivers/bus/mvebu-mbus.c #define WIN_CTRL_SYNCBARRIER BIT(1) BIT 97 drivers/bus/mvebu-mbus.c #define DDR_SIZE_ENABLED BIT(0) BIT 137 drivers/bus/omap_l3_noc.c (m_req_info & BIT(0)) ? "Opcode Fetch" : "Data Access", BIT 138 drivers/bus/omap_l3_noc.c (m_req_info & BIT(1)) ? "Supervisor" : "User", BIT 139 drivers/bus/omap_l3_noc.c (m_req_info & BIT(3)) ? "Debug" : "Functional"); BIT 28 drivers/bus/qcom-ebi2.c #define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1) BIT 29 drivers/bus/qcom-ebi2.c #define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3) BIT 30 drivers/bus/qcom-ebi2.c #define EBI2_CS2_ENABLE_MASK BIT(4) BIT 31 drivers/bus/qcom-ebi2.c #define EBI2_CS3_ENABLE_MASK BIT(5) BIT 32 drivers/bus/qcom-ebi2.c #define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7) BIT 33 drivers/bus/qcom-ebi2.c #define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9) BIT 262 drivers/bus/qcom-ebi2.c slowcfg |= BIT(xp->shift); BIT 264 drivers/bus/qcom-ebi2.c fastcfg |= BIT(xp->shift); BIT 67 drivers/bus/sunxi-rsb.c #define RSB_CTRL_START_TRANS BIT(7) BIT 68 drivers/bus/sunxi-rsb.c #define RSB_CTRL_ABORT_TRANS BIT(6) BIT 69 drivers/bus/sunxi-rsb.c #define RSB_CTRL_GLOBAL_INT_ENB BIT(1) BIT 70 drivers/bus/sunxi-rsb.c #define RSB_CTRL_SOFT_RST BIT(0) BIT 78 drivers/bus/sunxi-rsb.c #define RSB_INTS_TRANS_ERR_ACK BIT(16) BIT 81 drivers/bus/sunxi-rsb.c #define RSB_INTS_LOAD_BSY BIT(2) BIT 82 drivers/bus/sunxi-rsb.c #define RSB_INTS_TRANS_ERR BIT(1) BIT 83 drivers/bus/sunxi-rsb.c #define RSB_INTS_TRANS_OVER BIT(0) BIT 86 drivers/bus/sunxi-rsb.c #define RSB_LCR_SCL_STATE BIT(5) BIT 87 drivers/bus/sunxi-rsb.c #define RSB_LCR_SDA_STATE BIT(4) BIT 88 drivers/bus/sunxi-rsb.c #define RSB_LCR_SCL_CTL BIT(3) BIT 89 drivers/bus/sunxi-rsb.c #define RSB_LCR_SCL_CTL_EN BIT(2) BIT 90 drivers/bus/sunxi-rsb.c #define RSB_LCR_SDA_CTL BIT(1) BIT 91 drivers/bus/sunxi-rsb.c #define RSB_LCR_SDA_CTL_EN BIT(0) BIT 94 drivers/bus/sunxi-rsb.c #define RSB_DMCR_DEVICE_START BIT(31) BIT 19 drivers/bus/tegra-gmi.c #define TEGRA_GMI_CONFIG_GO BIT(31) BIT 20 drivers/bus/tegra-gmi.c #define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30) BIT 21 drivers/bus/tegra-gmi.c #define TEGRA_GMI_MUX_MODE BIT(28) BIT 22 drivers/bus/tegra-gmi.c #define TEGRA_GMI_RDY_BEFORE_DATA BIT(24) BIT 23 drivers/bus/tegra-gmi.c #define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23) BIT 24 drivers/bus/tegra-gmi.c #define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22) BIT 25 drivers/bus/tegra-gmi.c #define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21) BIT 26 drivers/bus/tegra-gmi.c #define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20) BIT 886 drivers/bus/ti-sysc.c ddata->cfg.sysc_val & BIT(regbits->clkact_shift))) BIT 906 drivers/bus/ti-sysc.c ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) BIT 907 drivers/bus/ti-sysc.c reg |= BIT(regbits->enwkup_shift); BIT 936 drivers/bus/ti-sysc.c ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { BIT 949 drivers/bus/ti-sysc.c if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) BIT 951 drivers/bus/ti-sysc.c else if (idlemodes & BIT(SYSC_IDLE_SMART)) BIT 953 drivers/bus/ti-sysc.c else if (idlemodes & BIT(SYSC_IDLE_FORCE)) BIT 1017 drivers/bus/ti-sysc.c ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) BIT 1415 drivers/bus/ti-sysc.c val |= BIT(5); BIT 1442 drivers/bus/ti-sysc.c val |= BIT(15); BIT 1444 drivers/bus/ti-sysc.c val &= ~BIT(15); BIT 1462 drivers/bus/ti-sysc.c u32 val = BIT(31); /* THALIA_INT_BYPASS */ BIT 1616 drivers/bus/ti-sysc.c sysc_mask = BIT(ddata->cap->regbits->srst_shift); BIT 147 drivers/bus/ts-nbus.c *val |= BIT(i); BIT 16 drivers/bus/uniphier-system-bus.c #define UNIPHIER_SBC_BASE_BE BIT(0) /* bank_enable */ BIT 100 drivers/char/hw_random/amd-rng.c rnen |= BIT(7); /* RNG on */ BIT 104 drivers/char/hw_random/amd-rng.c rnen |= BIT(7); /* PMIO enable */ BIT 116 drivers/char/hw_random/amd-rng.c rnen &= ~BIT(7); /* RNG off */ BIT 29 drivers/char/hw_random/exynos-trng.c #define EXYNOS_TRNG_CTRL_RNGEN BIT(31) BIT 17 drivers/char/hw_random/hisi-rng.c #define RNG_SEED_SEL BIT(2) BIT 18 drivers/char/hw_random/hisi-rng.c #define RNG_RING_EN BIT(1) BIT 19 drivers/char/hw_random/hisi-rng.c #define RNG_EN BIT(0) BIT 28 drivers/char/hw_random/ks-sa-rng.c #define SA_CMD_STATUS_REG_TRNG_ENABLE BIT(3) BIT 31 drivers/char/hw_random/ks-sa-rng.c #define TRNG_CNTL_REG_TRNG_ENABLE BIT(10) BIT 34 drivers/char/hw_random/ks-sa-rng.c #define TRNG_STATUS_REG_READY BIT(0) BIT 37 drivers/char/hw_random/ks-sa-rng.c #define TRNG_INTACK_REG_READY BIT(0) BIT 28 drivers/char/hw_random/mtk-rng.c #define RNG_EN BIT(0) BIT 29 drivers/char/hw_random/mtk-rng.c #define RNG_READY BIT(31) BIT 22 drivers/char/hw_random/pic32-rng.c #define TRNGEN BIT(8) BIT 23 drivers/char/hw_random/pic32-rng.c #define PRNGEN BIT(9) BIT 24 drivers/char/hw_random/pic32-rng.c #define PRNGCONT BIT(10) BIT 25 drivers/char/hw_random/pic32-rng.c #define TRNGMOD BIT(11) BIT 26 drivers/char/hw_random/pic32-rng.c #define SEEDLOAD BIT(12) BIT 25 drivers/char/hw_random/st-rng.c #define ST_RNG_STATUS_BAD_SEQUENCE BIT(0) BIT 26 drivers/char/hw_random/st-rng.c #define ST_RNG_STATUS_BAD_ALTERNANCE BIT(1) BIT 27 drivers/char/hw_random/st-rng.c #define ST_RNG_STATUS_FIFO_FULL BIT(5) BIT 20 drivers/char/hw_random/stm32-rng.c #define RNG_CR_RNGEN BIT(2) BIT 21 drivers/char/hw_random/stm32-rng.c #define RNG_CR_CED BIT(5) BIT 24 drivers/char/hw_random/stm32-rng.c #define RNG_SR_SEIS BIT(6) BIT 25 drivers/char/hw_random/stm32-rng.c #define RNG_SR_CEIS BIT(5) BIT 26 drivers/char/hw_random/stm32-rng.c #define RNG_SR_DRDY BIT(0) BIT 41 drivers/char/hw_random/xgene-rng.c #define MONOBIT_FAIL_MASK BIT(7) BIT 42 drivers/char/hw_random/xgene-rng.c #define POKER_FAIL_MASK BIT(6) BIT 43 drivers/char/hw_random/xgene-rng.c #define LONG_RUN_FAIL_MASK BIT(5) BIT 44 drivers/char/hw_random/xgene-rng.c #define RUN_FAIL_MASK BIT(4) BIT 45 drivers/char/hw_random/xgene-rng.c #define NOISE_FAIL_MASK BIT(3) BIT 46 drivers/char/hw_random/xgene-rng.c #define STUCK_OUT_MASK BIT(2) BIT 47 drivers/char/hw_random/xgene-rng.c #define SHUTDOWN_OFLO_MASK BIT(1) BIT 48 drivers/char/hw_random/xgene-rng.c #define READY_MASK BIT(0) BIT 60 drivers/char/hw_random/xgene-rng.c ((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10))) BIT 62 drivers/char/hw_random/xgene-rng.c ((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8))) BIT 64 drivers/char/hw_random/xgene-rng.c ((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7))) BIT 66 drivers/char/hw_random/xgene-rng.c ((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6))) BIT 68 drivers/char/hw_random/xgene-rng.c ((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5))) BIT 70 drivers/char/hw_random/xgene-rng.c ((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4))) BIT 72 drivers/char/hw_random/xgene-rng.c ((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3))) BIT 74 drivers/char/hw_random/xgene-rng.c ((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2))) BIT 76 drivers/char/hw_random/xgene-rng.c ((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1))) BIT 29 drivers/char/ipmi/kcs_bmc.c #define KCS_STATUS_CMD_DAT BIT(3) BIT 30 drivers/char/ipmi/kcs_bmc.c #define KCS_STATUS_SMS_ATN BIT(2) BIT 31 drivers/char/ipmi/kcs_bmc.c #define KCS_STATUS_IBF BIT(1) BIT 32 drivers/char/ipmi/kcs_bmc.c #define KCS_STATUS_OBF BIT(0) BIT 31 drivers/char/ipmi/kcs_bmc_aspeed.c #define LPC_HICR0_LPC3E BIT(7) BIT 32 drivers/char/ipmi/kcs_bmc_aspeed.c #define LPC_HICR0_LPC2E BIT(6) BIT 33 drivers/char/ipmi/kcs_bmc_aspeed.c #define LPC_HICR0_LPC1E BIT(5) BIT 35 drivers/char/ipmi/kcs_bmc_aspeed.c #define LPC_HICR2_IBFIF3 BIT(3) BIT 36 drivers/char/ipmi/kcs_bmc_aspeed.c #define LPC_HICR2_IBFIF2 BIT(2) BIT 37 drivers/char/ipmi/kcs_bmc_aspeed.c #define LPC_HICR2_IBFIF1 BIT(1) BIT 39 drivers/char/ipmi/kcs_bmc_aspeed.c #define LPC_HICR4_LADR12AS BIT(7) BIT 40 drivers/char/ipmi/kcs_bmc_aspeed.c #define LPC_HICR4_KCSENBL BIT(2) BIT 57 drivers/char/ipmi/kcs_bmc_aspeed.c #define LPC_HICRB_IBFIF4 BIT(1) BIT 58 drivers/char/ipmi/kcs_bmc_aspeed.c #define LPC_HICRB_LPC4E BIT(0) BIT 40 drivers/char/ipmi/kcs_bmc_npcm7xx.c #define KCS_CTL_IBFIE BIT(0) BIT 45 drivers/char/ipmi/kcs_bmc_npcm7xx.c #define KCS_IE_IRQE BIT(0) BIT 46 drivers/char/ipmi/kcs_bmc_npcm7xx.c #define KCS_IE_HIRQE BIT(3) BIT 160 drivers/char/tpm/tpm.h TPM_CHIP_FLAG_TPM2 = BIT(1), BIT 161 drivers/char/tpm/tpm.h TPM_CHIP_FLAG_IRQ = BIT(2), BIT 162 drivers/char/tpm/tpm.h TPM_CHIP_FLAG_VIRTUAL = BIT(3), BIT 163 drivers/char/tpm/tpm.h TPM_CHIP_FLAG_HAVE_TIMEOUTS = BIT(4), BIT 164 drivers/char/tpm/tpm.h TPM_CHIP_FLAG_ALWAYS_POWERED = BIT(5), BIT 283 drivers/char/tpm/tpm.h TPM_BUF_OVERFLOW = BIT(0), BIT 434 drivers/char/tpm/tpm.h return (rc & BIT(7)) ? rc & 0xff : rc; BIT 19 drivers/char/tpm/tpm2-cmd.c TPM2_OA_USER_WITH_AUTH = BIT(6), BIT 23 drivers/char/tpm/tpm2-cmd.c TPM2_SA_CONTINUE_SESSION = BIT(0), BIT 36 drivers/char/tpm/tpm_crb.c CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0), BIT 37 drivers/char/tpm/tpm_crb.c CRB_LOC_CTRL_RELINQUISH = BIT(1), BIT 41 drivers/char/tpm/tpm_crb.c CRB_LOC_STATE_LOC_ASSIGNED = BIT(1), BIT 42 drivers/char/tpm/tpm_crb.c CRB_LOC_STATE_TPM_REG_VALID_STS = BIT(7), BIT 46 drivers/char/tpm/tpm_crb.c CRB_CTRL_REQ_CMD_READY = BIT(0), BIT 47 drivers/char/tpm/tpm_crb.c CRB_CTRL_REQ_GO_IDLE = BIT(1), BIT 51 drivers/char/tpm/tpm_crb.c CRB_CTRL_STS_ERROR = BIT(0), BIT 52 drivers/char/tpm/tpm_crb.c CRB_CTRL_STS_TPM_IDLE = BIT(1), BIT 56 drivers/char/tpm/tpm_crb.c CRB_START_INVOKE = BIT(0), BIT 60 drivers/char/tpm/tpm_crb.c CRB_CANCEL_INVOKE = BIT(0), BIT 88 drivers/char/tpm/tpm_crb.c CRB_DRV_STS_COMPLETE = BIT(0), BIT 84 drivers/char/tpm/tpm_tis_core.h TPM_TIS_ITPM_WORKAROUND = BIT(0), BIT 26 drivers/char/tpm/tpm_vtpm_proxy.c #define VTPM_PROXY_REQ_COMPLETE_FLAG BIT(0) BIT 38 drivers/char/tpm/tpm_vtpm_proxy.c #define STATE_OPENED_FLAG BIT(0) BIT 39 drivers/char/tpm/tpm_vtpm_proxy.c #define STATE_WAIT_RESPONSE_FLAG BIT(1) /* waiting for emulator response */ BIT 40 drivers/char/tpm/tpm_vtpm_proxy.c #define STATE_REGISTERED_FLAG BIT(2) BIT 41 drivers/char/tpm/tpm_vtpm_proxy.c #define STATE_DRIVER_COMMAND BIT(3) /* sending a driver specific command */ BIT 27 drivers/clk/actions/owl-gate.c reg |= BIT(gate_hw->bit_idx); BIT 29 drivers/clk/actions/owl-gate.c reg &= ~BIT(gate_hw->bit_idx); BIT 60 drivers/clk/actions/owl-gate.c reg ^= BIT(gate_hw->bit_idx); BIT 62 drivers/clk/actions/owl-gate.c return !!(reg & BIT(gate_hw->bit_idx)); BIT 24 drivers/clk/actions/owl-mux.c parent &= BIT(mux_hw->width) - 1; BIT 119 drivers/clk/actions/owl-pll.c return !!(reg & BIT(pll_hw->bit_idx)); BIT 130 drivers/clk/actions/owl-pll.c reg |= BIT(pll_hw->bit_idx); BIT 132 drivers/clk/actions/owl-pll.c reg &= ~BIT(pll_hw->bit_idx); BIT 575 drivers/clk/actions/owl-s700.c [RESET_DE] = { CMU_DEVRST0, BIT(0) }, BIT 576 drivers/clk/actions/owl-s700.c [RESET_LCD0] = { CMU_DEVRST0, BIT(1) }, BIT 577 drivers/clk/actions/owl-s700.c [RESET_DSI] = { CMU_DEVRST0, BIT(2) }, BIT 578 drivers/clk/actions/owl-s700.c [RESET_CSI] = { CMU_DEVRST0, BIT(13) }, BIT 579 drivers/clk/actions/owl-s700.c [RESET_SI] = { CMU_DEVRST0, BIT(14) }, BIT 580 drivers/clk/actions/owl-s700.c [RESET_I2C0] = { CMU_DEVRST1, BIT(0) }, BIT 581 drivers/clk/actions/owl-s700.c [RESET_I2C1] = { CMU_DEVRST1, BIT(1) }, BIT 582 drivers/clk/actions/owl-s700.c [RESET_I2C2] = { CMU_DEVRST1, BIT(2) }, BIT 583 drivers/clk/actions/owl-s700.c [RESET_I2C3] = { CMU_DEVRST1, BIT(3) }, BIT 584 drivers/clk/actions/owl-s700.c [RESET_SPI0] = { CMU_DEVRST1, BIT(4) }, BIT 585 drivers/clk/actions/owl-s700.c [RESET_SPI1] = { CMU_DEVRST1, BIT(5) }, BIT 586 drivers/clk/actions/owl-s700.c [RESET_SPI2] = { CMU_DEVRST1, BIT(6) }, BIT 587 drivers/clk/actions/owl-s700.c [RESET_SPI3] = { CMU_DEVRST1, BIT(7) }, BIT 588 drivers/clk/actions/owl-s700.c [RESET_UART0] = { CMU_DEVRST1, BIT(8) }, BIT 589 drivers/clk/actions/owl-s700.c [RESET_UART1] = { CMU_DEVRST1, BIT(9) }, BIT 590 drivers/clk/actions/owl-s700.c [RESET_UART2] = { CMU_DEVRST1, BIT(10) }, BIT 591 drivers/clk/actions/owl-s700.c [RESET_UART3] = { CMU_DEVRST1, BIT(11) }, BIT 592 drivers/clk/actions/owl-s700.c [RESET_UART4] = { CMU_DEVRST1, BIT(12) }, BIT 593 drivers/clk/actions/owl-s700.c [RESET_UART5] = { CMU_DEVRST1, BIT(13) }, BIT 594 drivers/clk/actions/owl-s700.c [RESET_UART6] = { CMU_DEVRST1, BIT(14) }, BIT 595 drivers/clk/actions/owl-s700.c [RESET_KEY] = { CMU_DEVRST1, BIT(24) }, BIT 596 drivers/clk/actions/owl-s700.c [RESET_GPIO] = { CMU_DEVRST1, BIT(25) }, BIT 597 drivers/clk/actions/owl-s700.c [RESET_AUDIO] = { CMU_DEVRST1, BIT(29) }, BIT 690 drivers/clk/actions/owl-s900.c [RESET_DMAC] = { CMU_DEVRST0, BIT(0) }, BIT 691 drivers/clk/actions/owl-s900.c [RESET_SRAMI] = { CMU_DEVRST0, BIT(1) }, BIT 692 drivers/clk/actions/owl-s900.c [RESET_DDR_CTL_PHY] = { CMU_DEVRST0, BIT(2) }, BIT 693 drivers/clk/actions/owl-s900.c [RESET_NANDC0] = { CMU_DEVRST0, BIT(3) }, BIT 694 drivers/clk/actions/owl-s900.c [RESET_SD0] = { CMU_DEVRST0, BIT(4) }, BIT 695 drivers/clk/actions/owl-s900.c [RESET_SD1] = { CMU_DEVRST0, BIT(5) }, BIT 696 drivers/clk/actions/owl-s900.c [RESET_PCM1] = { CMU_DEVRST0, BIT(6) }, BIT 697 drivers/clk/actions/owl-s900.c [RESET_DE] = { CMU_DEVRST0, BIT(7) }, BIT 698 drivers/clk/actions/owl-s900.c [RESET_LVDS] = { CMU_DEVRST0, BIT(8) }, BIT 699 drivers/clk/actions/owl-s900.c [RESET_SD2] = { CMU_DEVRST0, BIT(9) }, BIT 700 drivers/clk/actions/owl-s900.c [RESET_DSI] = { CMU_DEVRST0, BIT(10) }, BIT 701 drivers/clk/actions/owl-s900.c [RESET_CSI0] = { CMU_DEVRST0, BIT(11) }, BIT 702 drivers/clk/actions/owl-s900.c [RESET_BISP_AXI] = { CMU_DEVRST0, BIT(12) }, BIT 703 drivers/clk/actions/owl-s900.c [RESET_CSI1] = { CMU_DEVRST0, BIT(13) }, BIT 704 drivers/clk/actions/owl-s900.c [RESET_GPIO] = { CMU_DEVRST0, BIT(15) }, BIT 705 drivers/clk/actions/owl-s900.c [RESET_EDP] = { CMU_DEVRST0, BIT(16) }, BIT 706 drivers/clk/actions/owl-s900.c [RESET_AUDIO] = { CMU_DEVRST0, BIT(17) }, BIT 707 drivers/clk/actions/owl-s900.c [RESET_PCM0] = { CMU_DEVRST0, BIT(18) }, BIT 708 drivers/clk/actions/owl-s900.c [RESET_HDE] = { CMU_DEVRST0, BIT(21) }, BIT 709 drivers/clk/actions/owl-s900.c [RESET_GPU3D_PA] = { CMU_DEVRST0, BIT(22) }, BIT 710 drivers/clk/actions/owl-s900.c [RESET_IMX] = { CMU_DEVRST0, BIT(23) }, BIT 711 drivers/clk/actions/owl-s900.c [RESET_SE] = { CMU_DEVRST0, BIT(24) }, BIT 712 drivers/clk/actions/owl-s900.c [RESET_NANDC1] = { CMU_DEVRST0, BIT(25) }, BIT 713 drivers/clk/actions/owl-s900.c [RESET_SD3] = { CMU_DEVRST0, BIT(26) }, BIT 714 drivers/clk/actions/owl-s900.c [RESET_GIC] = { CMU_DEVRST0, BIT(27) }, BIT 715 drivers/clk/actions/owl-s900.c [RESET_GPU3D_PB] = { CMU_DEVRST0, BIT(28) }, BIT 716 drivers/clk/actions/owl-s900.c [RESET_DDR_CTL_PHY_AXI] = { CMU_DEVRST0, BIT(29) }, BIT 717 drivers/clk/actions/owl-s900.c [RESET_CMU_DDR] = { CMU_DEVRST0, BIT(30) }, BIT 718 drivers/clk/actions/owl-s900.c [RESET_DMM] = { CMU_DEVRST0, BIT(31) }, BIT 719 drivers/clk/actions/owl-s900.c [RESET_USB2HUB] = { CMU_DEVRST1, BIT(0) }, BIT 720 drivers/clk/actions/owl-s900.c [RESET_USB2HSIC] = { CMU_DEVRST1, BIT(1) }, BIT 721 drivers/clk/actions/owl-s900.c [RESET_HDMI] = { CMU_DEVRST1, BIT(2) }, BIT 722 drivers/clk/actions/owl-s900.c [RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) }, BIT 723 drivers/clk/actions/owl-s900.c [RESET_UART6] = { CMU_DEVRST1, BIT(4) }, BIT 724 drivers/clk/actions/owl-s900.c [RESET_UART0] = { CMU_DEVRST1, BIT(5) }, BIT 725 drivers/clk/actions/owl-s900.c [RESET_UART1] = { CMU_DEVRST1, BIT(6) }, BIT 726 drivers/clk/actions/owl-s900.c [RESET_UART2] = { CMU_DEVRST1, BIT(7) }, BIT 727 drivers/clk/actions/owl-s900.c [RESET_SPI0] = { CMU_DEVRST1, BIT(8) }, BIT 728 drivers/clk/actions/owl-s900.c [RESET_SPI1] = { CMU_DEVRST1, BIT(9) }, BIT 729 drivers/clk/actions/owl-s900.c [RESET_SPI2] = { CMU_DEVRST1, BIT(10) }, BIT 730 drivers/clk/actions/owl-s900.c [RESET_SPI3] = { CMU_DEVRST1, BIT(11) }, BIT 731 drivers/clk/actions/owl-s900.c [RESET_I2C0] = { CMU_DEVRST1, BIT(12) }, BIT 732 drivers/clk/actions/owl-s900.c [RESET_I2C1] = { CMU_DEVRST1, BIT(13) }, BIT 733 drivers/clk/actions/owl-s900.c [RESET_USB3] = { CMU_DEVRST1, BIT(14) }, BIT 734 drivers/clk/actions/owl-s900.c [RESET_UART3] = { CMU_DEVRST1, BIT(15) }, BIT 735 drivers/clk/actions/owl-s900.c [RESET_UART4] = { CMU_DEVRST1, BIT(16) }, BIT 736 drivers/clk/actions/owl-s900.c [RESET_UART5] = { CMU_DEVRST1, BIT(17) }, BIT 737 drivers/clk/actions/owl-s900.c [RESET_I2C2] = { CMU_DEVRST1, BIT(18) }, BIT 738 drivers/clk/actions/owl-s900.c [RESET_I2C3] = { CMU_DEVRST1, BIT(19) }, BIT 739 drivers/clk/actions/owl-s900.c [RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) }, BIT 740 drivers/clk/actions/owl-s900.c [RESET_CHIPID] = { CMU_DEVRST1, BIT(21) }, BIT 741 drivers/clk/actions/owl-s900.c [RESET_I2C4] = { CMU_DEVRST1, BIT(22) }, BIT 742 drivers/clk/actions/owl-s900.c [RESET_I2C5] = { CMU_DEVRST1, BIT(23) }, BIT 743 drivers/clk/actions/owl-s900.c [RESET_CPU_SCNT] = { CMU_DEVRST1, BIT(30) } BIT 54 drivers/clk/at91/at91sam9x5.c .cmd = BIT(12), BIT 43 drivers/clk/at91/clk-audio-pll.c #define AUDIO_PLL_DIV_FRAC BIT(22) BIT 34 drivers/clk/at91/clk-i2s-mux.c return (val & BIT(mux->bus_id)) >> mux->bus_id; BIT 42 drivers/clk/at91/clk-i2s-mux.c BIT(mux->bus_id), index << mux->bus_id); BIT 19 drivers/clk/at91/clk-sam9x60-pll.c #define PMC_PLL_CTRL0_ENPLL BIT(28) BIT 20 drivers/clk/at91/clk-sam9x60-pll.c #define PMC_PLL_CTRL0_ENPLLCK BIT(29) BIT 21 drivers/clk/at91/clk-sam9x60-pll.c #define PMC_PLL_CTRL0_ENLOCK BIT(31) BIT 29 drivers/clk/at91/clk-sam9x60-pll.c #define PMC_PLL_ACR_UTMIVR BIT(12) BIT 30 drivers/clk/at91/clk-sam9x60-pll.c #define PMC_PLL_ACR_UTMIBG BIT(13) BIT 34 drivers/clk/at91/clk-sam9x60-pll.c #define PMC_PLL_UPDT_UPDATE BIT(8) BIT 63 drivers/clk/at91/clk-sam9x60-pll.c return !!(status & BIT(id)); BIT 98 drivers/clk/at91/dt-compat.c .cmd = BIT(12), BIT 55 drivers/clk/at91/sam9x60.c .cmd = BIT(31), BIT 33 drivers/clk/at91/sama5d2.c .cmd = BIT(12), BIT 33 drivers/clk/at91/sama5d4.c .cmd = BIT(12), BIT 435 drivers/clk/at91/sckc.c .cr_rcen = BIT(0), BIT 436 drivers/clk/at91/sckc.c .cr_osc32en = BIT(1), BIT 437 drivers/clk/at91/sckc.c .cr_osc32byp = BIT(2), BIT 438 drivers/clk/at91/sckc.c .cr_oscsel = BIT(3), BIT 456 drivers/clk/at91/sckc.c .cr_osc32en = BIT(1), BIT 457 drivers/clk/at91/sckc.c .cr_osc32byp = BIT(2), BIT 458 drivers/clk/at91/sckc.c .cr_oscsel = BIT(24), BIT 567 drivers/clk/at91/sckc.c .cr_oscsel = BIT(3), BIT 187 drivers/clk/axis/clk-artpec6.c muxreg &= ~BIT(i); BIT 196 drivers/clk/axis/clk-artpec6.c muxreg |= BIT(i); BIT 45 drivers/clk/axs10x/pll_clock.c (((reg) & (BIT(12))) ? 1 : 0) BIT 47 drivers/clk/axs10x/pll_clock.c (((reg) & (BIT(13))) ? 1 : 0) BIT 49 drivers/clk/axs10x/pll_clock.c (((reg) & (BIT(14))) ? 1 : 0) BIT 66 drivers/clk/axs10x/pll_clock.c #define PLL_LOCK BIT(0) BIT 67 drivers/clk/axs10x/pll_clock.c #define PLL_ERROR BIT(1) BIT 121 drivers/clk/bcm/clk-bcm2835.c # define CM_ENABLE BIT(4) BIT 122 drivers/clk/bcm/clk-bcm2835.c # define CM_KILL BIT(5) BIT 124 drivers/clk/bcm/clk-bcm2835.c # define CM_GATE BIT(CM_GATE_BIT) BIT 125 drivers/clk/bcm/clk-bcm2835.c # define CM_BUSY BIT(7) BIT 126 drivers/clk/bcm/clk-bcm2835.c # define CM_BUSYD BIT(8) BIT 127 drivers/clk/bcm/clk-bcm2835.c # define CM_FRAC BIT(9) BIT 149 drivers/clk/bcm/clk-bcm2835.c # define CM_PLL_ANARST BIT(8) BIT 150 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLA_HOLDPER BIT(7) BIT 151 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLA_LOADPER BIT(6) BIT 152 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLA_HOLDCORE BIT(5) BIT 153 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLA_LOADCORE BIT(4) BIT 154 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLA_HOLDCCP2 BIT(3) BIT 155 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLA_LOADCCP2 BIT(2) BIT 156 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLA_HOLDDSI0 BIT(1) BIT 157 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLA_LOADDSI0 BIT(0) BIT 160 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLC_HOLDPER BIT(7) BIT 161 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLC_LOADPER BIT(6) BIT 162 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLC_HOLDCORE2 BIT(5) BIT 163 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLC_LOADCORE2 BIT(4) BIT 164 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLC_HOLDCORE1 BIT(3) BIT 165 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLC_LOADCORE1 BIT(2) BIT 166 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLC_HOLDCORE0 BIT(1) BIT 167 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLC_LOADCORE0 BIT(0) BIT 170 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLD_HOLDPER BIT(7) BIT 171 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLD_LOADPER BIT(6) BIT 172 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLD_HOLDCORE BIT(5) BIT 173 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLD_LOADCORE BIT(4) BIT 174 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLD_HOLDDSI1 BIT(3) BIT 175 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLD_LOADDSI1 BIT(2) BIT 176 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLD_HOLDDSI0 BIT(1) BIT 177 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLD_LOADDSI0 BIT(0) BIT 180 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLH_LOADRCAL BIT(2) BIT 181 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLH_LOADAUX BIT(1) BIT 182 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLH_LOADPIX BIT(0) BIT 185 drivers/clk/bcm/clk-bcm2835.c # define CM_LOCK_FLOCKH BIT(12) BIT 186 drivers/clk/bcm/clk-bcm2835.c # define CM_LOCK_FLOCKD BIT(11) BIT 187 drivers/clk/bcm/clk-bcm2835.c # define CM_LOCK_FLOCKC BIT(10) BIT 188 drivers/clk/bcm/clk-bcm2835.c # define CM_LOCK_FLOCKB BIT(9) BIT 189 drivers/clk/bcm/clk-bcm2835.c # define CM_LOCK_FLOCKA BIT(8) BIT 200 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLB_HOLDARM BIT(1) BIT 201 drivers/clk/bcm/clk-bcm2835.c # define CM_PLLB_LOADARM BIT(0) BIT 208 drivers/clk/bcm/clk-bcm2835.c # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) BIT 209 drivers/clk/bcm/clk-bcm2835.c # define A2W_PLL_CTRL_PWRDN BIT(16) BIT 238 drivers/clk/bcm/clk-bcm2835.c # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) BIT 239 drivers/clk/bcm/clk-bcm2835.c # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) BIT 240 drivers/clk/bcm/clk-bcm2835.c # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) BIT 241 drivers/clk/bcm/clk-bcm2835.c # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) BIT 242 drivers/clk/bcm/clk-bcm2835.c # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) BIT 243 drivers/clk/bcm/clk-bcm2835.c # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) BIT 244 drivers/clk/bcm/clk-bcm2835.c # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) BIT 245 drivers/clk/bcm/clk-bcm2835.c # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) BIT 255 drivers/clk/bcm/clk-bcm2835.c #define A2W_PLL_CHANNEL_DISABLE BIT(8) BIT 294 drivers/clk/bcm/clk-bcm2835.c #define SOC_BCM2835 BIT(0) BIT 295 drivers/clk/bcm/clk-bcm2835.c #define SOC_BCM2711 BIT(1) BIT 453 drivers/clk/bcm/clk-bcm2835.c .fb_prediv_mask = BIT(14), BIT 463 drivers/clk/bcm/clk-bcm2835.c .fb_prediv_mask = BIT(11), BIT 943 drivers/clk/bcm/clk-bcm2835.c maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; BIT 1115 drivers/clk/bcm/clk-bcm2835.c if (!(BIT(parent_idx) & data->set_rate_parent)) { BIT 1146 drivers/clk/bcm/clk-bcm2835.c maxdiv = BIT(data->int_bits) - 1; BIT 2119 drivers/clk/bcm/clk-bcm2835.c .set_rate_parent = BIT(7), BIT 251 drivers/clk/bcm/clk-iproc-pll.c val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift); BIT 253 drivers/clk/bcm/clk-iproc-pll.c val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift)); BIT 275 drivers/clk/bcm/clk-iproc-pll.c val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift)); BIT 277 drivers/clk/bcm/clk-iproc-pll.c val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift); BIT 719 drivers/clk/bcm/clk-iproc-pll.c val |= BIT(ctrl->sw_ctrl.shift); BIT 30 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_AON BIT(0) BIT 33 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_PLL_ASIU BIT(1) BIT 36 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2) BIT 43 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_NEEDS_READ_BACK BIT(3) BIT 49 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4) BIT 55 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_EMBED_PWRCTRL BIT(5) BIT 61 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6) BIT 68 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_MCLK_DIV_BY_2 BIT(7) BIT 76 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_PLL_USER_MODE_ON BIT(8) BIT 81 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_PLL_RESET_ACTIVE_LOW BIT(9) BIT 86 drivers/clk/bcm/clk-iproc.h #define IPROC_CLK_PLL_CALC_PARAM BIT(10) BIT 23 drivers/clk/bcm/clk-raspberrypi.c #define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0) BIT 24 drivers/clk/bcm/clk-raspberrypi.c #define RPI_FIRMWARE_STATE_WAIT_BIT BIT(1) BIT 35 drivers/clk/berlin/berlin2-avpll.c #define VCO_RESET BIT(0) BIT 36 drivers/clk/berlin/berlin2-avpll.c #define VCO_POWERUP BIT(1) BIT 57 drivers/clk/berlin/berlin2-avpll.c #define VCO_KVCOEXT_ENABLE BIT(17) BIT 60 drivers/clk/berlin/berlin2-avpll.c #define VCO_V2IEXT_ENABLE BIT(22) BIT 71 drivers/clk/berlin/berlin2-avpll.c #define VCO_CLKDET_ENABLE BIT(26) BIT 87 drivers/clk/berlin/berlin2-avpll.c #define VCO_LOAD_CAP BIT(18) BIT 88 drivers/clk/berlin/berlin2-avpll.c #define VCO_CALIBRATION_START BIT(19) BIT 92 drivers/clk/berlin/berlin2-avpll.c #define VCO_POWERUP_CH1 BIT(20) BIT 103 drivers/clk/berlin/berlin2-avpll.c #define VCO_DPLL_CH1_ENABLE BIT(17) BIT 286 drivers/clk/berlin/berlin2-avpll.c if (reg & BIT(2)) BIT 300 drivers/clk/berlin/berlin2-avpll.c if (reg & BIT(2)) BIT 11 drivers/clk/berlin/berlin2-avpll.h #define BERLIN2_AVPLL_BIT_QUIRK BIT(0) BIT 12 drivers/clk/berlin/berlin2-avpll.h #define BERLIN2_AVPLL_SCRAMBLE_QUIRK BIT(1) BIT 93 drivers/clk/berlin/berlin2-div.c reg |= BIT(map->gate_shift); BIT 112 drivers/clk/berlin/berlin2-div.c reg &= ~BIT(map->gate_shift); BIT 131 drivers/clk/berlin/berlin2-div.c reg &= ~BIT(map->pll_switch_shift); BIT 133 drivers/clk/berlin/berlin2-div.c reg |= BIT(map->pll_switch_shift); BIT 162 drivers/clk/berlin/berlin2-div.c reg &= BIT(map->pll_switch_shift); BIT 13 drivers/clk/berlin/berlin2-div.h #define BERLIN2_DIV_HAS_GATE BIT(0) BIT 14 drivers/clk/berlin/berlin2-div.h #define BERLIN2_DIV_HAS_MUX BIT(1) BIT 26 drivers/clk/clk-aspeed.c #define AST2500_HPLL_BYPASS_EN BIT(20) BIT 27 drivers/clk/clk-aspeed.c #define AST2400_HPLL_PROGRAMMED BIT(18) BIT 28 drivers/clk/clk-aspeed.c #define AST2400_HPLL_BYPASS_EN BIT(17) BIT 30 drivers/clk/clk-aspeed.c #define UART_DIV13_EN BIT(12) BIT 32 drivers/clk/clk-aspeed.c #define CLKIN_25MHZ_EN BIT(23) BIT 33 drivers/clk/clk-aspeed.c #define AST2400_CLK_SOURCE_SEL BIT(18) BIT 186 drivers/clk/clk-aspeed.c u32 clk = BIT(gate->clock_idx); BIT 187 drivers/clk/clk-aspeed.c u32 rst = BIT(gate->reset_idx); BIT 212 drivers/clk/clk-aspeed.c u32 clk = BIT(gate->clock_idx); BIT 213 drivers/clk/clk-aspeed.c u32 rst = BIT(gate->reset_idx); BIT 252 drivers/clk/clk-aspeed.c u32 clk = BIT(gate->clock_idx); BIT 300 drivers/clk/clk-aspeed.c return regmap_update_bits(ar->map, reg, BIT(bit), 0); BIT 315 drivers/clk/clk-aspeed.c return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit)); BIT 335 drivers/clk/clk-aspeed.c return !!(val & BIT(bit)); BIT 29 drivers/clk/clk-ast2600.c #define UART_DIV13_EN BIT(12) BIT 162 drivers/clk/clk-ast2600.c if (val & BIT(24)) { BIT 181 drivers/clk/clk-ast2600.c if (val & BIT(20)) { BIT 199 drivers/clk/clk-ast2600.c return BIT(idx % 32); BIT 452 drivers/clk/clk-ast2600.c if (val & BIT(31)) BIT 517 drivers/clk/clk-ast2600.c regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10)); BIT 634 drivers/clk/clk-ast2600.c if (val & BIT(16)) BIT 640 drivers/clk/clk-ast2600.c if (chip_id & BIT(16)) BIT 22 drivers/clk/clk-axi-clkgen.c #define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1) BIT 23 drivers/clk/clk-axi-clkgen.c #define AXI_CLKGEN_V2_RESET_ENABLE BIT(0) BIT 25 drivers/clk/clk-axi-clkgen.c #define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29) BIT 26 drivers/clk/clk-axi-clkgen.c #define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28) BIT 28 drivers/clk/clk-axi-clkgen.c #define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16) BIT 41 drivers/clk/clk-axi-clkgen.c #define MMCM_CLKOUT_NOCOUNT BIT(6) BIT 43 drivers/clk/clk-axi-clkgen.c #define MMCM_CLK_DIV_NOCOUNT BIT(12) BIT 239 drivers/clk/clk-cdce925.c nn = n * BIT(p); BIT 694 drivers/clk/clk-cdce925.c regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); BIT 697 drivers/clk/clk-cdce925.c regmap_update_bits(data->regmap, 0x02, BIT(7), 0); BIT 70 drivers/clk/clk-gate.c reg = BIT(gate->bit_idx + 16); BIT 72 drivers/clk/clk-gate.c reg |= BIT(gate->bit_idx); BIT 77 drivers/clk/clk-gate.c reg |= BIT(gate->bit_idx); BIT 79 drivers/clk/clk-gate.c reg &= ~BIT(gate->bit_idx); BIT 111 drivers/clk/clk-gate.c reg ^= BIT(gate->bit_idx); BIT 113 drivers/clk/clk-gate.c reg &= BIT(gate->bit_idx); BIT 29 drivers/clk/clk-gemini.c #define PLL_OSC_SEL BIT(30) BIT 40 drivers/clk/clk-gemini.c #define PCI_CLK_66MHZ BIT(18) BIT 43 drivers/clk/clk-gemini.c #define PCI_CLKRUN_EN BIT(16) BIT 46 drivers/clk/clk-gemini.c #define SECURITY_CLK_SEL BIT(29) BIT 49 drivers/clk/clk-gemini.c #define PCI_DLL_BYPASS BIT(31) BIT 231 drivers/clk/clk-gemini.c BIT(GEMINI_RESET_CPU1) | BIT(id)); BIT 257 drivers/clk/clk-gemini.c return !!(val & BIT(id)); BIT 18 drivers/clk/clk-hi655x.c #define HI655X_CLK_SET BIT(6) BIT 36 drivers/clk/clk-hsdk-pll.c #define CGU_PLL_CTRL_PD BIT(0) BIT 37 drivers/clk/clk-hsdk-pll.c #define CGU_PLL_CTRL_BYPASS BIT(1) BIT 39 drivers/clk/clk-hsdk-pll.c #define CGU_PLL_STATUS_LOCK BIT(0) BIT 40 drivers/clk/clk-hsdk-pll.c #define CGU_PLL_STATUS_ERR BIT(1) BIT 59 drivers/clk/clk-max77686.c .clk_enable_mask = BIT(MAX77686_CLK_AP), BIT 64 drivers/clk/clk-max77686.c .clk_enable_mask = BIT(MAX77686_CLK_CP), BIT 69 drivers/clk/clk-max77686.c .clk_enable_mask = BIT(MAX77686_CLK_PMIC), BIT 78 drivers/clk/clk-max77686.c .clk_enable_mask = BIT(MAX77802_CLK_32K_AP), BIT 83 drivers/clk/clk-max77686.c .clk_enable_mask = BIT(MAX77802_CLK_32K_CP), BIT 28 drivers/clk/clk-max9485.c #define MAX9485_DOUBLE BIT(4) BIT 29 drivers/clk/clk-max9485.c #define MAX9485_CLKOUT1_ENABLE BIT(5) BIT 30 drivers/clk/clk-max9485.c #define MAX9485_CLKOUT2_ENABLE BIT(6) BIT 31 drivers/clk/clk-max9485.c #define MAX9485_MCLK_ENABLE BIT(7) BIT 297 drivers/clk/clk-milbeaut.c u32 write_en = BIT(fls(mux->mask) - 1); BIT 417 drivers/clk/clk-milbeaut.c u32 write_en = BIT(divider->width - 1); BIT 225 drivers/clk/clk-mux.c u32 mask = BIT(width) - 1; BIT 239 drivers/clk/clk-mux.c u32 mask = BIT(width) - 1; BIT 29 drivers/clk/clk-nomadik.c #define SRC_CR_T0_ENSEL BIT(15) BIT 30 drivers/clk/clk-nomadik.c #define SRC_CR_T1_ENSEL BIT(17) BIT 31 drivers/clk/clk-nomadik.c #define SRC_CR_T2_ENSEL BIT(19) BIT 32 drivers/clk/clk-nomadik.c #define SRC_CR_T3_ENSEL BIT(21) BIT 33 drivers/clk/clk-nomadik.c #define SRC_CR_T4_ENSEL BIT(23) BIT 34 drivers/clk/clk-nomadik.c #define SRC_CR_T5_ENSEL BIT(25) BIT 35 drivers/clk/clk-nomadik.c #define SRC_CR_T6_ENSEL BIT(27) BIT 36 drivers/clk/clk-nomadik.c #define SRC_CR_T7_ENSEL BIT(29) BIT 38 drivers/clk/clk-nomadik.c #define SRC_XTALCR_XTALTIMEN BIT(20) BIT 39 drivers/clk/clk-nomadik.c #define SRC_XTALCR_SXTALDIS BIT(19) BIT 40 drivers/clk/clk-nomadik.c #define SRC_XTALCR_MXTALSTAT BIT(2) BIT 41 drivers/clk/clk-nomadik.c #define SRC_XTALCR_MXTALEN BIT(1) BIT 42 drivers/clk/clk-nomadik.c #define SRC_XTALCR_MXTALOVER BIT(0) BIT 44 drivers/clk/clk-nomadik.c #define SRC_PLLCR_PLLTIMEN BIT(29) BIT 45 drivers/clk/clk-nomadik.c #define SRC_PLLCR_PLL2EN BIT(28) BIT 46 drivers/clk/clk-nomadik.c #define SRC_PLLCR_PLL1STAT BIT(2) BIT 47 drivers/clk/clk-nomadik.c #define SRC_PLLCR_PLL1EN BIT(1) BIT 48 drivers/clk/clk-nomadik.c #define SRC_PLLCR_PLL1OVER BIT(0) BIT 372 drivers/clk/clk-nomadik.c sclk->clkbit = BIT(id & 0x1f); BIT 471 drivers/clk/clk-nomadik.c u32 mask = BIT(i & 0x1f); BIT 30 drivers/clk/clk-npcm7xx.c #define PLLCON_LOKI BIT(31) BIT 31 drivers/clk/clk-npcm7xx.c #define PLLCON_LOKS BIT(30) BIT 34 drivers/clk/clk-npcm7xx.c #define PLLCON_PWDEN BIT(12) BIT 56 drivers/clk/clk-oxnas.c return val & BIT(std->bit); BIT 63 drivers/clk/clk-oxnas.c regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit)); BIT 72 drivers/clk/clk-oxnas.c regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit)); BIT 1139 drivers/clk/clk-qoriq.c #define PLL_KILL BIT(31) BIT 31 drivers/clk/clk-si514.c #define SI514_RESET_RST BIT(7) BIT 33 drivers/clk/clk-si514.c #define SI514_CONTROL_FCAL BIT(0) BIT 34 drivers/clk/clk-si514.c #define SI514_CONTROL_OE BIT(2) BIT 199 drivers/clk/clk-si514.c settings->m_frac = (u32)m & (BIT(29) - 1); BIT 209 drivers/clk/clk-si514.c u32 d = settings->hs_div * BIT(settings->ls_div_bits); BIT 113 drivers/clk/clk-si5341.c #define SI5341_OUT_CFG_PDN BIT(0) BIT 114 drivers/clk/clk-si5341.c #define SI5341_OUT_CFG_OE BIT(1) BIT 115 drivers/clk/clk-si5341.c #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2) BIT 333 drivers/clk/clk-si5341.c while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) { BIT 412 drivers/clk/clk-si5341.c if (!(val & BIT(index))) BIT 419 drivers/clk/clk-si5341.c if (!(val & BIT(index))) BIT 427 drivers/clk/clk-si5341.c return !(val & BIT(index)); BIT 434 drivers/clk/clk-si5341.c u8 mask = BIT(index); BIT 452 drivers/clk/clk-si5341.c u8 mask = BIT(index); BIT 530 drivers/clk/clk-si5341.c SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0); BIT 703 drivers/clk/clk-si5341.c else if (r_div >= BIT(24)) BIT 704 drivers/clk/clk-si5341.c r_div = BIT(24) - 1; BIT 34 drivers/clk/clk-si544.c #define SI544_CONTROL_RESET BIT(7) BIT 35 drivers/clk/clk-si544.c #define SI544_CONTROL_MS_ICAL2 BIT(3) BIT 37 drivers/clk/clk-si544.c #define SI544_OE_STATE_ODC_OE BIT(0) BIT 280 drivers/clk/clk-si544.c u32 d = settings->hs_div * BIT(settings->ls_div_bits); BIT 424 drivers/clk/clk-stm32f4.c if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) BIT 436 drivers/clk/clk-stm32f4.c if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) BIT 622 drivers/clk/clk-stm32f4.c bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx)); BIT 908 drivers/clk/clk-stm32f4.c writel(val | BIT(16), base + STM32F4_RCC_BDCR); BIT 909 drivers/clk/clk-stm32f4.c writel(val & ~BIT(16), base + STM32F4_RCC_BDCR); BIT 934 drivers/clk/clk-stm32f4.c bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx)); BIT 178 drivers/clk/clk-stm32h7.c bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy)); BIT 201 drivers/clk/clk-stm32h7.c bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy)); BIT 1162 drivers/clk/clk-stm32h7.c #define PWR_CR_DBP BIT(8) BIT 461 drivers/clk/clk-stm32mp1.c writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR); BIT 550 drivers/clk/clk-stm32mp1.c mgate->mask = BIT(cfg->mgate->nbr_clk++); BIT 738 drivers/clk/clk-stm32mp1.c #define PLL_ON BIT(0) BIT 739 drivers/clk/clk-stm32mp1.c #define PLL_RDY BIT(1) BIT 747 drivers/clk/clk-stm32mp1.c #define FRACLE BIT(16) BIT 14 drivers/clk/clk-tango4.c #define DIV_BYPASS BIT(23) BIT 465 drivers/clk/clk-u300.c val |= BIT(sclk->res_bit); BIT 481 drivers/clk/clk-u300.c val &= ~BIT(sclk->res_bit); BIT 550 drivers/clk/clk-u300.c val &= BIT(sclk->en_bit); BIT 49 drivers/clk/clk-versaclock5.c #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) BIT 50 drivers/clk/clk-versaclock5.c #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6) BIT 51 drivers/clk/clk-versaclock5.c #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3) BIT 52 drivers/clk/clk-versaclock5.c #define VC5_PRIM_SRC_SHDN_SP BIT(1) BIT 53 drivers/clk/clk-versaclock5.c #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0) BIT 59 drivers/clk/clk-versaclock5.c #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7) BIT 63 drivers/clk/clk-versaclock5.c #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7) BIT 74 drivers/clk/clk-versaclock5.c #define VC5_OUT_DIV_CONTROL_RESET BIT(7) BIT 75 drivers/clk/clk-versaclock5.c #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3) BIT 76 drivers/clk/clk-versaclock5.c #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2) BIT 77 drivers/clk/clk-versaclock5.c #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1) BIT 78 drivers/clk/clk-versaclock5.c #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0) BIT 81 drivers/clk/clk-versaclock5.c #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1) BIT 92 drivers/clk/clk-versaclock5.c #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0) BIT 98 drivers/clk/clk-versaclock5.c #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5) BIT 105 drivers/clk/clk-versaclock5.c #define VC5_MUX_IN_XIN BIT(0) BIT 106 drivers/clk/clk-versaclock5.c #define VC5_MUX_IN_CLKIN BIT(1) BIT 116 drivers/clk/clk-versaclock5.c #define VC5_HAS_INTERNAL_XTAL BIT(0) BIT 118 drivers/clk/clk-versaclock5.c #define VC5_HAS_PFD_FREQ_DBL BIT(1) BIT 437 drivers/clk/clk-versaclock5.c div_frc *= BIT(24) - 1; BIT 84 drivers/clk/clk-vt8500.c en_val |= BIT(cdev->en_bit); BIT 100 drivers/clk/clk-vt8500.c en_val &= ~BIT(cdev->en_bit); BIT 109 drivers/clk/clk-vt8500.c u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit)); BIT 121 drivers/clk/clk-vt8500.c if ((cdev->div_mask == 0x3F) && (div & BIT(5))) BIT 219 drivers/clk/clk-vt8500.c #define CLK_INIT_GATED BIT(0) BIT 220 drivers/clk/clk-vt8500.c #define CLK_INIT_DIVISOR BIT(1) BIT 233 drivers/clk/clk-xgene.c #define XGENE_CLK_PMD_SCALE_INVERTED BIT(0) BIT 362 drivers/clk/clk-xgene.c fd->mask = (BIT(width) - 1) << shift; BIT 405 drivers/clk/clk-xgene.c denom = BIT(XGENE_CLK_PMD_WIDTH); BIT 23 drivers/clk/davinci/da8xx-cfgchip.c #define DA8XX_GATE_CLOCK_IS_DIV4P5 BIT(1) BIT 57 drivers/clk/davinci/pll-dm365.c .ocsrc_mask = BIT(4), BIT 120 drivers/clk/davinci/pll-dm365.c .ocsrc_mask = BIT(4), BIT 61 drivers/clk/davinci/pll.c #define PLLCTL_PLLEN BIT(0) BIT 62 drivers/clk/davinci/pll.c #define PLLCTL_PLLPWRDN BIT(1) BIT 63 drivers/clk/davinci/pll.c #define PLLCTL_PLLRST BIT(3) BIT 64 drivers/clk/davinci/pll.c #define PLLCTL_PLLDIS BIT(4) BIT 65 drivers/clk/davinci/pll.c #define PLLCTL_PLLENSRC BIT(5) BIT 66 drivers/clk/davinci/pll.c #define PLLCTL_CLKMODE BIT(8) BIT 73 drivers/clk/davinci/pll.c #define PLLCMD_GOSET BIT(0) BIT 74 drivers/clk/davinci/pll.c #define PLLSTAT_GOSTAT BIT(0) BIT 613 drivers/clk/davinci/pll.c oscdiv |= BIT(DIV_ENABLE_SHIFT); BIT 17 drivers/clk/davinci/pll.h #define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */ BIT 18 drivers/clk/davinci/pll.h #define PLL_HAS_PREDIV BIT(1) /* has prediv before PLL */ BIT 19 drivers/clk/davinci/pll.h #define PLL_PREDIV_ALWAYS_ENABLED BIT(2) /* don't clear DEN bit */ BIT 20 drivers/clk/davinci/pll.h #define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */ BIT 21 drivers/clk/davinci/pll.h #define PLL_HAS_POSTDIV BIT(4) /* has postdiv after PLL */ BIT 22 drivers/clk/davinci/pll.h #define PLL_POSTDIV_ALWAYS_ENABLED BIT(5) /* don't clear DEN bit */ BIT 23 drivers/clk/davinci/pll.h #define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */ BIT 24 drivers/clk/davinci/pll.h #define PLL_HAS_EXTCLKSRC BIT(7) /* has selectable bypass */ BIT 25 drivers/clk/davinci/pll.h #define PLL_PLLM_2X BIT(8) /* PLLM value is 2x (DM365) */ BIT 26 drivers/clk/davinci/pll.h #define PLL_PREDIV_FIXED8 BIT(9) /* DM355 quirk */ BIT 51 drivers/clk/davinci/pll.h #define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */ BIT 52 drivers/clk/davinci/pll.h #define SYSCLK_ALWAYS_ENABLED BIT(1) /* Or bad things happen */ BIT 53 drivers/clk/davinci/pll.h #define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */ BIT 52 drivers/clk/davinci/psc.c #define MDSTAT_MCKOUT BIT(12) BIT 54 drivers/clk/davinci/psc.c #define MDCTL_FORCE BIT(31) BIT 55 drivers/clk/davinci/psc.c #define MDCTL_LRESET BIT(8) BIT 56 drivers/clk/davinci/psc.c #define PDCTL_EPCGOOD BIT(8) BIT 57 drivers/clk/davinci/psc.c #define PDCTL_NEXT BIT(0) BIT 126 drivers/clk/davinci/psc.c regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd)); BIT 129 drivers/clk/davinci/psc.c epcpr & BIT(lpsc->pd), 0, 0); BIT 134 drivers/clk/davinci/psc.c regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd)); BIT 138 drivers/clk/davinci/psc.c !(ptstat & BIT(lpsc->pd)), 0, 0); BIT 15 drivers/clk/davinci/psc.h #define LPSC_ALWAYS_ENABLED BIT(0) /* never disable this clock */ BIT 16 drivers/clk/davinci/psc.h #define LPSC_SET_RATE_PARENT BIT(1) /* propagate set_rate to parent clock */ BIT 17 drivers/clk/davinci/psc.h #define LPSC_FORCE BIT(2) /* requires MDCTL FORCE bit */ BIT 18 drivers/clk/davinci/psc.h #define LPSC_LOCAL_RESET BIT(3) /* acts as reset provider */ BIT 112 drivers/clk/hisilicon/clk-hisi-phase.c phase->mask = (BIT(clks->width) - 1) << clks->shift; BIT 158 drivers/clk/hisilicon/clk.c u32 mask = BIT(clks[i].width) - 1; BIT 141 drivers/clk/hisilicon/clkdivider-hi6220.c div->mask = mask_bit ? BIT(mask_bit) : 0; BIT 41 drivers/clk/hisilicon/clkgate-separated.c reg = BIT(sclk->bit_idx); BIT 58 drivers/clk/hisilicon/clkgate-separated.c reg = BIT(sclk->bit_idx); BIT 72 drivers/clk/hisilicon/clkgate-separated.c reg &= BIT(sclk->bit_idx); BIT 57 drivers/clk/hisilicon/reset.c writel(reg | BIT(bit), rstc->membase + offset); BIT 78 drivers/clk/hisilicon/reset.c writel(reg & ~BIT(bit), rstc->membase + offset); BIT 172 drivers/clk/imx/clk-busy.c busy->mux.mask = BIT(width) - 1; BIT 19 drivers/clk/imx/clk-composite-7ulp.c #define PCG_FRAC_MASK BIT(3) BIT 90 drivers/clk/imx/clk-fixup-mux.c fixup_mux->mux.mask = BIT(width) - 1; BIT 23 drivers/clk/imx/clk-frac-pll.c #define PLL_LOCK_STATUS BIT(31) BIT 24 drivers/clk/imx/clk-frac-pll.c #define PLL_PD_MASK BIT(19) BIT 25 drivers/clk/imx/clk-frac-pll.c #define PLL_BYPASS_MASK BIT(14) BIT 26 drivers/clk/imx/clk-frac-pll.c #define PLL_NEWDIV_VAL BIT(12) BIT 27 drivers/clk/imx/clk-frac-pll.c #define PLL_NEWDIV_ACK BIT(11) BIT 262 drivers/clk/imx/clk-imx6q.c #define CCSR_PLL3_SW_CLK_SEL BIT(0) BIT 390 drivers/clk/imx/clk-imx6q.c #define PLL_ENABLE BIT(13) BIT 392 drivers/clk/imx/clk-imx6q.c #define PFD0_CLKGATE BIT(7) BIT 393 drivers/clk/imx/clk-imx6q.c #define PFD1_CLKGATE BIT(15) BIT 394 drivers/clk/imx/clk-imx6q.c #define PFD2_CLKGATE BIT(23) BIT 395 drivers/clk/imx/clk-imx6q.c #define PFD3_CLKGATE BIT(31) BIT 572 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_hw_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); BIT 573 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_hw_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); BIT 575 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); BIT 576 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); BIT 256 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LVDS1_OUT] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12)); BIT 257 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); BIT 220 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LVDS1_OUT] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12)); BIT 221 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LVDS2_OUT] = imx_clk_hw_gate_exclusive("lvds2_out", "lvds2_sel", base + 0x160, 11, BIT(13)); BIT 222 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); BIT 223 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); BIT 498 drivers/clk/imx/clk-imx7d.c hws[IMX7D_LVDS1_OUT_CLK] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x170, 5, BIT(6)); BIT 18 drivers/clk/imx/clk-lpcg-scu.c #define CLK_GATE_SCU_LPCG_HW_SEL BIT(0) BIT 19 drivers/clk/imx/clk-lpcg-scu.c #define CLK_GATE_SCU_LPCG_SW_SEL BIT(1) BIT 18 drivers/clk/imx/clk-pll14xx.c #define LOCK_STATUS BIT(31) BIT 19 drivers/clk/imx/clk-pll14xx.c #define LOCK_SEL_MASK BIT(29) BIT 20 drivers/clk/imx/clk-pll14xx.c #define CLKE_MASK BIT(11) BIT 21 drivers/clk/imx/clk-pll14xx.c #define RST_MASK BIT(9) BIT 22 drivers/clk/imx/clk-pll14xx.c #define BYPASS_MASK BIT(4) BIT 21 drivers/clk/imx/clk-pllv1.c #define MFN_SIGN (BIT(MFN_BITS - 1)) BIT 92 drivers/clk/imx/clk-pllv1.c mfn_abs = BIT(MFN_BITS) - mfn; BIT 20 drivers/clk/imx/clk-pllv4.c #define PLL_VLD BIT(24) BIT 21 drivers/clk/imx/clk-pllv4.c #define PLL_EN BIT(0) BIT 32 drivers/clk/imx/clk-sccg-pll.c #define PLL_LOCK_MASK BIT(31) BIT 33 drivers/clk/imx/clk-sccg-pll.c #define PLL_PD_MASK BIT(7) BIT 64 drivers/clk/imx/clk-sccg-pll.c #define SSCG_PLL_BYPASS1_MASK BIT(5) BIT 65 drivers/clk/imx/clk-sccg-pll.c #define SSCG_PLL_BYPASS2_MASK BIT(4) BIT 251 drivers/clk/imx/clk-vf610.c clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10)); BIT 12 drivers/clk/imx/clk.c #define CCDR_MMDC_CH0_MASK BIT(17) BIT 13 drivers/clk/imx/clk.c #define CCDR_MMDC_CH1_MASK BIT(16) BIT 38 drivers/clk/ingenic/cgu.c return !!(readl(cgu->base + info->reg) & BIT(info->bit)) BIT 59 drivers/clk/ingenic/cgu.c clkgr |= BIT(info->bit); BIT 61 drivers/clk/ingenic/cgu.c clkgr &= ~BIT(info->bit); BIT 97 drivers/clk/ingenic/cgu.c !!(ctl & BIT(pll_info->bypass_bit)); BIT 217 drivers/clk/ingenic/cgu.c ctl &= ~BIT(pll_info->bypass_bit); BIT 218 drivers/clk/ingenic/cgu.c ctl |= BIT(pll_info->enable_bit); BIT 225 drivers/clk/ingenic/cgu.c if (ctl & BIT(pll_info->stable_bit)) BIT 250 drivers/clk/ingenic/cgu.c ctl &= ~BIT(pll_info->enable_bit); BIT 269 drivers/clk/ingenic/cgu.c return !!(ctl & BIT(pll_info->enable_bit)); BIT 493 drivers/clk/ingenic/cgu.c reg &= ~BIT(clk_info->div.stop_bit); BIT 497 drivers/clk/ingenic/cgu.c reg |= BIT(clk_info->div.ce_bit); BIT 506 drivers/clk/ingenic/cgu.c if (!(reg & BIT(clk_info->div.busy_bit))) BIT 146 drivers/clk/ingenic/cgu.h CGU_CLK_EXT = BIT(0), BIT 147 drivers/clk/ingenic/cgu.h CGU_CLK_PLL = BIT(1), BIT 148 drivers/clk/ingenic/cgu.h CGU_CLK_GATE = BIT(2), BIT 149 drivers/clk/ingenic/cgu.h CGU_CLK_MUX = BIT(3), BIT 150 drivers/clk/ingenic/cgu.h CGU_CLK_MUX_GLITCHFREE = BIT(4), BIT 151 drivers/clk/ingenic/cgu.h CGU_CLK_DIV = BIT(5), BIT 152 drivers/clk/ingenic/cgu.h CGU_CLK_FIXDIV = BIT(6), BIT 153 drivers/clk/ingenic/cgu.h CGU_CLK_CUSTOM = BIT(7), BIT 29 drivers/clk/ingenic/jz4725b-cgu.c #define LCR_SLEEP BIT(0) BIT 42 drivers/clk/ingenic/jz4770-cgu.c #define OPCR_SPENDH BIT(5) /* UHC PHY suspend */ BIT 45 drivers/clk/ingenic/jz4770-cgu.c #define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */ BIT 53 drivers/clk/ingenic/jz4780-cgu.c #define USBPCR_USB_MODE BIT(31) BIT 55 drivers/clk/ingenic/jz4780-cgu.c #define USBPCR_COMMONONN BIT(25) BIT 56 drivers/clk/ingenic/jz4780-cgu.c #define USBPCR_VBUSVLDEXT BIT(24) BIT 57 drivers/clk/ingenic/jz4780-cgu.c #define USBPCR_VBUSVLDEXTSEL BIT(23) BIT 58 drivers/clk/ingenic/jz4780-cgu.c #define USBPCR_POR BIT(22) BIT 59 drivers/clk/ingenic/jz4780-cgu.c #define USBPCR_OTG_DISABLE BIT(20) BIT 64 drivers/clk/ingenic/jz4780-cgu.c #define USBPCR_TXPREEMPHTUNE BIT(6) BIT 78 drivers/clk/ingenic/jz4780-cgu.c #define USBPCR1_USB_SEL BIT(28) BIT 79 drivers/clk/ingenic/jz4780-cgu.c #define USBPCR1_WORD_IF0 BIT(19) BIT 80 drivers/clk/ingenic/jz4780-cgu.c #define USBPCR1_WORD_IF1 BIT(18) BIT 83 drivers/clk/ingenic/jz4780-cgu.c #define USBRDT_VBFIL_LD_EN BIT(25) BIT 14 drivers/clk/ingenic/pm.c #define LCR_LOW_POWER_MODE BIT(0) BIT 70 drivers/clk/ingenic/tcu.c regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit)); BIT 81 drivers/clk/ingenic/tcu.c regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit)); BIT 92 drivers/clk/ingenic/tcu.c return !(value & BIT(info->gate_bit)); BIT 110 drivers/clk/ingenic/tcu.c regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit)); BIT 123 drivers/clk/ingenic/tcu.c regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit)); BIT 149 drivers/clk/ingenic/tcu.c TCU_TCSR_PARENT_CLOCK_MASK, BIT(idx)); BIT 288 drivers/clk/ingenic/tcu.c regmap_update_bits(tcu->map, info->tcsr_reg, 0xffff, BIT(parent)); BIT 32 drivers/clk/keystone/gate.c #define MDSTAT_MCKOUT BIT(12) BIT 34 drivers/clk/keystone/gate.c #define MDCTL_FORCE BIT(31) BIT 35 drivers/clk/keystone/gate.c #define MDCTL_LRESET BIT(8) BIT 36 drivers/clk/keystone/gate.c #define PDCTL_NEXT BIT(0) BIT 28 drivers/clk/keystone/sci-clk.c #define SCI_CLK_SSC_ENABLE BIT(0) BIT 29 drivers/clk/keystone/sci-clk.c #define SCI_CLK_ALLOW_FREQ_CHANGE BIT(1) BIT 30 drivers/clk/keystone/sci-clk.c #define SCI_CLK_INPUT_TERMINATION BIT(2) BIT 13 drivers/clk/mediatek/clk-apmixed.c #define REF2USB_TX_EN BIT(0) BIT 14 drivers/clk/mediatek/clk-apmixed.c #define REF2USB_TX_LPF_EN BIT(1) BIT 15 drivers/clk/mediatek/clk-apmixed.c #define REF2USB_TX_OUT_EN BIT(2) BIT 68 drivers/clk/mediatek/clk-cpumux.c cpumux->mask = BIT(mux->mux_width) - 1; BIT 25 drivers/clk/mediatek/clk-gate.c val &= BIT(cg->bit); BIT 37 drivers/clk/mediatek/clk-gate.c val &= BIT(cg->bit); BIT 46 drivers/clk/mediatek/clk-gate.c regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); BIT 53 drivers/clk/mediatek/clk-gate.c regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); BIT 59 drivers/clk/mediatek/clk-gate.c u32 cgbit = BIT(cg->bit); BIT 67 drivers/clk/mediatek/clk-gate.c u32 cgbit = BIT(cg->bit); BIT 916 drivers/clk/mediatek/clk-mt2701.c #define CON0_MT8590_RST_BAR BIT(27) BIT 1164 drivers/clk/mediatek/clk-mt2712.c #define CON0_MT2712_RST_BAR BIT(24) BIT 1181 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0), BIT 1183 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0), BIT 1185 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0), BIT 1187 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0), BIT 1188 drivers/clk/mediatek/clk-mt6779.c (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0, BIT 1190 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0), BIT 1191 drivers/clk/mediatek/clk-mt6779.c (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24, BIT 1193 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0), BIT 1195 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0), BIT 1197 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0), BIT 1199 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0), BIT 1200 drivers/clk/mediatek/clk-mt6779.c (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24, BIT 1202 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0), BIT 1203 drivers/clk/mediatek/clk-mt6779.c (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24, BIT 1205 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0), BIT 1207 drivers/clk/mediatek/clk-mt6779.c PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0), BIT 612 drivers/clk/mediatek/clk-mt6797.c #define CON0_MT6797_RST_BAR BIT(24) BIT 22 drivers/clk/mediatek/clk-mt7622.c #define CON0_MT7622_RST_BAR BIT(27) BIT 22 drivers/clk/mediatek/clk-mt7629.c #define CON0_MT7629_RST_BAR BIT(24) BIT 594 drivers/clk/mediatek/clk-mt8135.c #define CON0_MT8135_RST_BAR BIT(27) BIT 1023 drivers/clk/mediatek/clk-mt8173.c #define CON0_MT8173_RST_BAR BIT(24) BIT 1125 drivers/clk/mediatek/clk-mt8183.c HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, BIT 1128 drivers/clk/mediatek/clk-mt8183.c HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, BIT 1131 drivers/clk/mediatek/clk-mt8183.c HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, BIT 1134 drivers/clk/mediatek/clk-mt8183.c HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, BIT 1137 drivers/clk/mediatek/clk-mt8183.c HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, BIT 1147 drivers/clk/mediatek/clk-mt8183.c HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, BIT 734 drivers/clk/mediatek/clk-mt8516.c #define CON0_MT8516_RST_BAR BIT(27) BIT 169 drivers/clk/mediatek/clk-mtk.c mux->mask = BIT(mc->mux_width) - 1; BIT 205 drivers/clk/mediatek/clk-mtk.h #define HAVE_RST_BAR BIT(0) BIT 206 drivers/clk/mediatek/clk-mtk.h #define PLL_AO BIT(1) BIT 23 drivers/clk/mediatek/clk-mux.c u32 mask = BIT(mux->data->gate_shift); BIT 32 drivers/clk/mediatek/clk-mux.c u32 mask = BIT(mux->data->gate_shift); BIT 42 drivers/clk/mediatek/clk-mux.c BIT(mux->data->gate_shift)); BIT 50 drivers/clk/mediatek/clk-mux.c BIT(mux->data->gate_shift)); BIT 60 drivers/clk/mediatek/clk-mux.c return (val & BIT(mux->data->gate_shift)) == 0; BIT 121 drivers/clk/mediatek/clk-mux.c BIT(mux->data->upd_shift)); BIT 19 drivers/clk/mediatek/clk-pll.c #define CON0_BASE_EN BIT(0) BIT 20 drivers/clk/mediatek/clk-pll.c #define CON0_PWR_ON BIT(0) BIT 21 drivers/clk/mediatek/clk-pll.c #define CON0_ISO_EN BIT(1) BIT 22 drivers/clk/mediatek/clk-pll.c #define PCW_CHG_MASK BIT(31) BIT 24 drivers/clk/mediatek/clk-pll.c #define AUDPLL_TUNER_EN BIT(31) BIT 94 drivers/clk/mediatek/clk-pll.c r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); BIT 107 drivers/clk/mediatek/clk-pll.c r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); BIT 46 drivers/clk/mediatek/reset.c BIT(id % 32), ~0); BIT 55 drivers/clk/mediatek/reset.c BIT(id % 32), 0); BIT 949 drivers/clk/meson/axg-audio.c regmap_update_bits(rst->map, offset, BIT(bit), BIT 950 drivers/clk/meson/axg-audio.c assert ? BIT(bit) : 0); BIT 966 drivers/clk/meson/axg-audio.c return !!(val & BIT(bit)); BIT 27 drivers/clk/meson/clk-mpll.h #define CLK_MESON_MPLL_ROUND_CLOSEST BIT(0) BIT 28 drivers/clk/meson/clk-mpll.h #define CLK_MESON_MPLL_SPREAD_SPECTRUM BIT(1) BIT 30 drivers/clk/meson/clk-pll.h #define CLK_MESON_PLL_ROUND_CLOSEST BIT(0) BIT 18 drivers/clk/meson/clk-regmap.c return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), BIT 19 drivers/clk/meson/clk-regmap.c set ? BIT(gate->bit_idx) : 0); BIT 40 drivers/clk/meson/clk-regmap.c val ^= BIT(gate->bit_idx); BIT 42 drivers/clk/meson/clk-regmap.c val &= BIT(gate->bit_idx); BIT 27 drivers/clk/meson/meson-aoclk.c BIT(rstc->data->reset[id])); BIT 3562 drivers/clk/meson/meson8b.c BIT(reset->bit_idx), BIT(reset->bit_idx)); BIT 3565 drivers/clk/meson/meson8b.c BIT(reset->bit_idx), 0); BIT 22 drivers/clk/microchip/clk-core.c #define OSC_SWEN BIT(0) BIT 42 drivers/clk/microchip/clk-core.c #define PB_DIV_READY BIT(11) BIT 43 drivers/clk/microchip/clk-core.c #define PB_DIV_ENABLE BIT(15) BIT 50 drivers/clk/microchip/clk-core.c #define REFO_ACTIVE BIT(8) BIT 51 drivers/clk/microchip/clk-core.c #define REFO_DIVSW_EN BIT(9) BIT 52 drivers/clk/microchip/clk-core.c #define REFO_OE BIT(12) BIT 53 drivers/clk/microchip/clk-core.c #define REFO_ON BIT(15) BIT 64 drivers/clk/microchip/clk-core.c #define SLEW_BUSY BIT(0) BIT 65 drivers/clk/microchip/clk-core.c #define SLEW_DOWNEN BIT(1) BIT 66 drivers/clk/microchip/clk-core.c #define SLEW_UPEN BIT(2) BIT 99 drivers/clk/microchip/clk-pic32mzda.c .lock_mask = BIT(7), BIT 112 drivers/clk/microchip/clk-pic32mzda.c .enable_mask = BIT(1), BIT 113 drivers/clk/microchip/clk-pic32mzda.c .status_mask = BIT(4), BIT 142 drivers/clk/microchip/clk-pic32mzda.c if (readl(cd->core.iobase) & BIT(2)) BIT 8 drivers/clk/mmp/clk.h #define APBC_NO_BUS_CTRL BIT(0) BIT 9 drivers/clk/mmp/clk.h #define APBC_POWER_CTRL BIT(1) BIT 108 drivers/clk/mmp/clk.h #define MMP_CLK_GATE_NEED_DELAY BIT(0) BIT 29 drivers/clk/mvebu/ap-cpu-clk.c #define APN806_CLUSTER_NUM_MASK BIT(APN806_CLUSTER_NUM_OFFSET) BIT 195 drivers/clk/mvebu/ap-cpu-clk.c BIT(clk->pll_regs->ratio_offset), BIT 196 drivers/clk/mvebu/ap-cpu-clk.c BIT(clk->pll_regs->ratio_offset)); BIT 198 drivers/clk/mvebu/ap-cpu-clk.c stable_bit = BIT(clk->pll_regs->ratio_state_offset + BIT 209 drivers/clk/mvebu/ap-cpu-clk.c BIT(clk->pll_regs->ratio_offset), 0); BIT 24 drivers/clk/mvebu/armada-370.c #define SARL_A370_SSCG_ENABLE BIT(10) BIT 373 drivers/clk/mvebu/armada-37xx-periph.c return !!(val & BIT(ARMADA_37XX_NB_DFS_EN)); BIT 17 drivers/clk/mvebu/armada-37xx-xtal.c #define XTAL_MODE BIT(31) BIT 38 drivers/clk/mvebu/armada-39x.c #define SARH_A390_REFCLK_FREQ BIT(0) BIT 84 drivers/clk/mvebu/clk-corediv.c u32 enable_mask = BIT(desc->fieldbit) << soc_desc->enable_bit_offset; BIT 100 drivers/clk/mvebu/clk-corediv.c reg |= (BIT(desc->fieldbit) << soc_desc->enable_bit_offset); BIT 119 drivers/clk/mvebu/clk-corediv.c reg &= ~(BIT(desc->fieldbit) << soc_desc->enable_bit_offset); BIT 173 drivers/clk/mvebu/clk-corediv.c reg = readl(corediv->reg) | BIT(desc->fieldbit); BIT 205 drivers/clk/mvebu/clk-corediv.c .ratio_reload = BIT(8), BIT 221 drivers/clk/mvebu/clk-corediv.c .ratio_reload = BIT(8), BIT 234 drivers/clk/mvebu/clk-corediv.c .ratio_reload = BIT(8), BIT 246 drivers/clk/mvebu/clk-corediv.c .ratio_reload = BIT(10), BIT 40 drivers/clk/mvebu/cp110-system-controller.c #define NF_CLOCK_SEL_400_MASK BIT(0) BIT 126 drivers/clk/mvebu/cp110-system-controller.c BIT(gate->bit_idx), BIT(gate->bit_idx)); BIT 136 drivers/clk/mvebu/cp110-system-controller.c BIT(gate->bit_idx), 0); BIT 146 drivers/clk/mvebu/cp110-system-controller.c return val & BIT(gate->bit_idx); BIT 32 drivers/clk/mvebu/dove-divider.c DIV_CTRL1_N_RESET_MASK = BIT(10), BIT 146 drivers/clk/mvebu/dove-divider.c load = BIT(dc->div_bit_load); BIT 23 drivers/clk/nxp/clk-lpc18xx-ccu.c #define LPC18XX_CCU_RUN BIT(0) BIT 24 drivers/clk/nxp/clk-lpc18xx-ccu.c #define LPC18XX_CCU_AUTO BIT(1) BIT 25 drivers/clk/nxp/clk-lpc18xx-ccu.c #define LPC18XX_CCU_DIV BIT(5) BIT 26 drivers/clk/nxp/clk-lpc18xx-ccu.c #define LPC18XX_CCU_DIVSTAT BIT(27) BIT 29 drivers/clk/nxp/clk-lpc18xx-ccu.c #define CCU_BRANCH_IS_BUS BIT(0) BIT 30 drivers/clk/nxp/clk-lpc18xx-ccu.c #define CCU_BRANCH_HAVE_DIV2 BIT(1) BIT 33 drivers/clk/nxp/clk-lpc18xx-cgu.c #define LPC18XX_PLL1_CTRL_FBSEL BIT(6) BIT 34 drivers/clk/nxp/clk-lpc18xx-cgu.c #define LPC18XX_PLL1_CTRL_DIRECT BIT(7) BIT 40 drivers/clk/nxp/clk-lpc18xx-cgu.c #define LPC18XX_PLL0_STAT_LOCK BIT(0) BIT 41 drivers/clk/nxp/clk-lpc18xx-cgu.c #define LPC18XX_PLL0_CTRL_PD BIT(0) BIT 42 drivers/clk/nxp/clk-lpc18xx-cgu.c #define LPC18XX_PLL0_CTRL_BYPASS BIT(1) BIT 43 drivers/clk/nxp/clk-lpc18xx-cgu.c #define LPC18XX_PLL0_CTRL_DIRECTI BIT(2) BIT 44 drivers/clk/nxp/clk-lpc18xx-cgu.c #define LPC18XX_PLL0_CTRL_DIRECTO BIT(3) BIT 45 drivers/clk/nxp/clk-lpc18xx-cgu.c #define LPC18XX_PLL0_CTRL_CLKEN BIT(4) BIT 49 drivers/clk/nxp/clk-lpc18xx-cgu.c #define LPC18XX_PLL0_MSEL_MAX BIT(15) BIT 20 drivers/clk/nxp/clk-lpc18xx-creg.c #define LPC18XX_CREG_CREG0_EN1KHZ BIT(0) BIT 21 drivers/clk/nxp/clk-lpc18xx-creg.c #define LPC18XX_CREG_CREG0_EN32KHZ BIT(1) BIT 22 drivers/clk/nxp/clk-lpc18xx-creg.c #define LPC18XX_CREG_CREG0_RESET32KHZ BIT(2) BIT 23 drivers/clk/nxp/clk-lpc18xx-creg.c #define LPC18XX_CREG_CREG0_PD32KHZ BIT(3) BIT 18 drivers/clk/nxp/clk-lpc32xx.c #define PLL_CTRL_ENABLE BIT(16) BIT 19 drivers/clk/nxp/clk-lpc32xx.c #define PLL_CTRL_BYPASS BIT(15) BIT 20 drivers/clk/nxp/clk-lpc32xx.c #define PLL_CTRL_DIRECT BIT(14) BIT 21 drivers/clk/nxp/clk-lpc32xx.c #define PLL_CTRL_FEEDBACK BIT(13) BIT 22 drivers/clk/nxp/clk-lpc32xx.c #define PLL_CTRL_POSTDIV (BIT(12)|BIT(11)) BIT 23 drivers/clk/nxp/clk-lpc32xx.c #define PLL_CTRL_PREDIV (BIT(10)|BIT(9)) BIT 25 drivers/clk/nxp/clk-lpc32xx.c #define PLL_CTRL_LOCK BIT(0) BIT 721 drivers/clk/nxp/clk-lpc32xx.c return (val == (BIT(7) | BIT(0)) || BIT 722 drivers/clk/nxp/clk-lpc32xx.c val == (BIT(8) | BIT(1))); BIT 738 drivers/clk/nxp/clk-lpc32xx.c if (hclk_div == 0x0 || hclk_div == (BIT(1) | BIT(0))) BIT 887 drivers/clk/nxp/clk-lpc32xx.c u32 mask = BIT(clk->bit_idx); BIT 896 drivers/clk/nxp/clk-lpc32xx.c u32 mask = BIT(clk->bit_idx); BIT 909 drivers/clk/nxp/clk-lpc32xx.c is_set = val & BIT(clk->bit_idx); BIT 1223 drivers/clk/nxp/clk-lpc32xx.c LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)), BIT 1254 drivers/clk/nxp/clk-lpc32xx.c LPC32XX_DEFINE_CLK(DDRAM, HCLKDIV_CTRL, 0x0, BIT(8) | BIT(7), BIT 1255 drivers/clk/nxp/clk-lpc32xx.c 0x0, BIT(8) | BIT(7), 0x0, BIT(1) | BIT(0), clk_ddram_ops), BIT 1334 drivers/clk/nxp/clk-lpc32xx.c LPC32XX_DEFINE_CLK(SD_GATE, MS_CTRL, BIT(5) | BIT(9), BIT(5) | BIT(9), BIT 1335 drivers/clk/nxp/clk-lpc32xx.c 0x0, BIT(5) | BIT(9), 0x0, 0x0, clk_mask_ops), BIT 1343 drivers/clk/nxp/clk-lpc32xx.c BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0), BIT 1344 drivers/clk/nxp/clk-lpc32xx.c BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0), BIT 1347 drivers/clk/nxp/clk-lpc32xx.c BIT(2) | BIT(0), BIT(2) | BIT(0), 0x0, BIT 1348 drivers/clk/nxp/clk-lpc32xx.c BIT(0), BIT(1), BIT(2) | BIT(1), clk_mask_ops), BIT 1350 drivers/clk/nxp/clk-lpc32xx.c BIT(1), BIT(2) | BIT(1), 0x0, BIT(1), BIT 1351 drivers/clk/nxp/clk-lpc32xx.c BIT(2) | BIT(0), BIT(2) | BIT(0), clk_mask_ops), BIT 1371 drivers/clk/nxp/clk-lpc32xx.c BIT(24), 0x0, BIT(24), BIT(4), 0, clk_usb_ops), BIT 1373 drivers/clk/nxp/clk-lpc32xx.c 0x0, 0x0, 0x0, BIT(3), 0, clk_usb_ops), BIT 1375 drivers/clk/nxp/clk-lpc32xx.c 0x0, BIT(23), BIT(23), BIT(2), 0, clk_usb_i2c_ops), BIT 1377 drivers/clk/nxp/clk-lpc32xx.c BIT(22), 0x0, BIT(22), BIT(1), BIT(0), clk_usb_ops), BIT 1379 drivers/clk/nxp/clk-lpc32xx.c BIT(21), 0x0, BIT(21), BIT(0), BIT(1), clk_usb_ops), BIT 1483 drivers/clk/nxp/clk-lpc32xx.c val |= BIT(__ffs(div_mask)); BIT 1535 drivers/clk/nxp/clk-lpc32xx.c lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf0, BIT(0)); BIT 1536 drivers/clk/nxp/clk-lpc32xx.c lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf00, BIT(2)); BIT 1537 drivers/clk/nxp/clk-lpc32xx.c lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_MS_CTRL, 0xf, BIT(5) | BIT(9)); BIT 17 drivers/clk/pistachio/clk-pll.c #define PLL_STATUS_LOCK BIT(0) BIT 28 drivers/clk/pistachio/clk-pll.c #define PLL_INT_CTRL1_PD BIT(24) BIT 29 drivers/clk/pistachio/clk-pll.c #define PLL_INT_CTRL1_DSMPD BIT(25) BIT 30 drivers/clk/pistachio/clk-pll.c #define PLL_INT_CTRL1_FOUTPOSTDIVPD BIT(26) BIT 31 drivers/clk/pistachio/clk-pll.c #define PLL_INT_CTRL1_FOUTVCOPD BIT(27) BIT 40 drivers/clk/pistachio/clk-pll.c #define PLL_INT_CTRL2_BYPASS BIT(28) BIT 43 drivers/clk/pistachio/clk-pll.c #define PLL_FRAC_CTRL3_PD BIT(0) BIT 44 drivers/clk/pistachio/clk-pll.c #define PLL_FRAC_CTRL3_DACPD BIT(1) BIT 45 drivers/clk/pistachio/clk-pll.c #define PLL_FRAC_CTRL3_DSMPD BIT(2) BIT 46 drivers/clk/pistachio/clk-pll.c #define PLL_FRAC_CTRL3_FOUTPOSTDIVPD BIT(3) BIT 47 drivers/clk/pistachio/clk-pll.c #define PLL_FRAC_CTRL3_FOUT4PHASEPD BIT(4) BIT 48 drivers/clk/pistachio/clk-pll.c #define PLL_FRAC_CTRL3_FOUTVCOPD BIT(5) BIT 51 drivers/clk/pistachio/clk-pll.c #define PLL_FRAC_CTRL4_BYPASS BIT(28) BIT 661 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 679 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 697 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 710 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 728 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 741 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 754 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 772 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 790 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 808 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 826 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 844 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 862 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 880 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 898 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 916 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 934 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 952 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 969 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 982 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 995 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1013 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1026 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1039 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1052 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1070 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1088 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1106 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1123 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1136 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1154 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1172 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1190 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1207 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1225 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1243 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1261 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1279 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1297 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1310 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1328 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1346 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1364 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1377 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1395 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1413 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1431 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1449 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1467 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1485 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1503 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 1516 drivers/clk/qcom/camcc-sdm845.c .enable_mask = BIT(0), BIT 16 drivers/clk/qcom/clk-alpha-pll.c # define PLL_OUTCTRL BIT(0) BIT 17 drivers/clk/qcom/clk-alpha-pll.c # define PLL_BYPASSNL BIT(1) BIT 18 drivers/clk/qcom/clk-alpha-pll.c # define PLL_RESET_N BIT(2) BIT 19 drivers/clk/qcom/clk-alpha-pll.c # define PLL_OFFLINE_REQ BIT(7) BIT 24 drivers/clk/qcom/clk-alpha-pll.c # define PLL_VOTE_FSM_ENA BIT(20) BIT 25 drivers/clk/qcom/clk-alpha-pll.c # define PLL_FSM_ENA BIT(20) BIT 26 drivers/clk/qcom/clk-alpha-pll.c # define PLL_VOTE_FSM_RESET BIT(21) BIT 27 drivers/clk/qcom/clk-alpha-pll.c # define PLL_UPDATE BIT(22) BIT 28 drivers/clk/qcom/clk-alpha-pll.c # define PLL_UPDATE_BYPASS BIT(23) BIT 29 drivers/clk/qcom/clk-alpha-pll.c # define PLL_OFFLINE_ACK BIT(28) BIT 30 drivers/clk/qcom/clk-alpha-pll.c # define ALPHA_PLL_ACK_LATCH BIT(29) BIT 31 drivers/clk/qcom/clk-alpha-pll.c # define PLL_ACTIVE_FLAG BIT(30) BIT 32 drivers/clk/qcom/clk-alpha-pll.c # define PLL_LOCK_DET BIT(31) BIT 42 drivers/clk/qcom/clk-alpha-pll.c # define PLL_ALPHA_EN BIT(24) BIT 43 drivers/clk/qcom/clk-alpha-pll.c # define PLL_ALPHA_MODE BIT(25) BIT 612 drivers/clk/qcom/clk-alpha-pll.c if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) BIT 645 drivers/clk/qcom/clk-alpha-pll.c if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) BIT 689 drivers/clk/qcom/clk-alpha-pll.c if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { BIT 690 drivers/clk/qcom/clk-alpha-pll.c alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; BIT 976 drivers/clk/qcom/clk-alpha-pll.c ctl &= BIT(pll->width) - 1; BIT 1201 drivers/clk/qcom/clk-alpha-pll.c val &= BIT(pll->width) - 1; BIT 1308 drivers/clk/qcom/clk-alpha-pll.c (BIT(pll->width) - 1) << pll->post_div_shift, BIT 61 drivers/clk/qcom/clk-alpha-pll.h #define SUPPORTS_OFFLINE_REQ BIT(0) BIT 62 drivers/clk/qcom/clk-alpha-pll.h #define SUPPORTS_FSM_MODE BIT(2) BIT 63 drivers/clk/qcom/clk-alpha-pll.h #define SUPPORTS_DYNAMIC_UPDATE BIT(3) BIT 25 drivers/clk/qcom/clk-branch.c return !!(val & BIT(br->hwcg_bit)); BIT 35 drivers/clk/qcom/clk-branch.c val &= BIT(br->halt_bit); BIT 42 drivers/clk/qcom/clk-branch.c #define BRANCH_CLK_OFF BIT(31) BIT 29 drivers/clk/qcom/clk-branch.h #define BRANCH_VOTED BIT(7) /* Delay on disable */ BIT 15 drivers/clk/qcom/clk-hfpll.c #define PLL_OUTCTRL BIT(0) BIT 16 drivers/clk/qcom/clk-hfpll.c #define PLL_BYPASSNL BIT(1) BIT 17 drivers/clk/qcom/clk-hfpll.c #define PLL_RESET_N BIT(2) BIT 78 drivers/clk/qcom/clk-hfpll.c } while (!(val & BIT(hd->lock_bit))); BIT 214 drivers/clk/qcom/clk-hfpll.c if (!(status & BIT(hd->lock_bit))) { BIT 92 drivers/clk/qcom/clk-krait.c u32 mask = BIT(d->width) - 1; BIT 110 drivers/clk/qcom/clk-krait.c u32 mask = BIT(d->width) - 1; BIT 20 drivers/clk/qcom/clk-pll.c #define PLL_OUTCTRL BIT(0) BIT 21 drivers/clk/qcom/clk-pll.c #define PLL_BYPASSNL BIT(1) BIT 22 drivers/clk/qcom/clk-pll.c #define PLL_RESET_N BIT(2) BIT 105 drivers/clk/qcom/clk-pll.c config &= BIT(pll->post_div_width) - 1; BIT 191 drivers/clk/qcom/clk-pll.c if (val & BIT(pll->status_bit)) BIT 60 drivers/clk/qcom/clk-rcg.c bank &= BIT(rcg->mux_sel_bit); BIT 109 drivers/clk/qcom/clk-rcg.c md &= BIT(mn->width) - 1; BIT 116 drivers/clk/qcom/clk-rcg.c ns &= BIT(p->pre_div_width) - 1; BIT 124 drivers/clk/qcom/clk-rcg.c mask = BIT(p->pre_div_width) - 1; BIT 136 drivers/clk/qcom/clk-rcg.c mask_w = BIT(mn->width) - 1; BIT 152 drivers/clk/qcom/clk-rcg.c ns &= BIT(mn->width) - 1; BIT 167 drivers/clk/qcom/clk-rcg.c mask = BIT(mn->width) - 1; BIT 174 drivers/clk/qcom/clk-rcg.c n &= BIT(mn->width) - 1; BIT 187 drivers/clk/qcom/clk-rcg.c mask |= BIT(mn->mnctr_en_bit); BIT 191 drivers/clk/qcom/clk-rcg.c val |= BIT(mn->mnctr_en_bit); BIT 228 drivers/clk/qcom/clk-rcg.c ns |= BIT(mn->mnctr_reset_bit); BIT 259 drivers/clk/qcom/clk-rcg.c ns &= ~BIT(mn->mnctr_reset_bit); BIT 283 drivers/clk/qcom/clk-rcg.c reg ^= BIT(rcg->mux_sel_bit); BIT 487 drivers/clk/qcom/clk-rcg.c mask = BIT(mn->mnctr_reset_bit); BIT 671 drivers/clk/qcom/clk-rcg.c int pre_div_max = BIT(rcg->p.pre_div_width); BIT 696 drivers/clk/qcom/clk-rcg.c int pre_div_max = BIT(rcg->p.pre_div_width); BIT 750 drivers/clk/qcom/clk-rcg.c u32 gfm = BIT(10); BIT 769 drivers/clk/qcom/clk-rcg.c u32 gfm = BIT(10); BIT 778 drivers/clk/qcom/clk-rcg.c u32 gfm = BIT(10); BIT 23 drivers/clk/qcom/clk-rcg2.c #define CMD_UPDATE BIT(0) BIT 24 drivers/clk/qcom/clk-rcg2.c #define CMD_ROOT_EN BIT(1) BIT 25 drivers/clk/qcom/clk-rcg2.c #define CMD_DIRTY_CFG BIT(4) BIT 26 drivers/clk/qcom/clk-rcg2.c #define CMD_DIRTY_N BIT(5) BIT 27 drivers/clk/qcom/clk-rcg2.c #define CMD_DIRTY_M BIT(6) BIT 28 drivers/clk/qcom/clk-rcg2.c #define CMD_DIRTY_D BIT(7) BIT 29 drivers/clk/qcom/clk-rcg2.c #define CMD_ROOT_OFF BIT(31) BIT 38 drivers/clk/qcom/clk-rcg2.c #define CFG_HW_CLK_CTRL_MASK BIT(20) BIT 52 drivers/clk/qcom/clk-rcg2.c #define SE_CMD_DFS_EN BIT(0) BIT 173 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; BIT 184 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; BIT 274 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; BIT 291 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; BIT 417 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; BIT 462 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; BIT 515 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; BIT 538 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; BIT 571 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; BIT 596 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; BIT 675 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; BIT 963 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; BIT 983 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; BIT 1059 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; BIT 1067 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; BIT 27 drivers/clk/qcom/clk-regmap-divider.c val &= BIT(divider->width) - 1; BIT 53 drivers/clk/qcom/clk-regmap-divider.c (BIT(divider->width) - 1) << divider->shift, BIT 66 drivers/clk/qcom/clk-regmap-divider.c div &= BIT(divider->width) - 1; BIT 15 drivers/clk/qcom/clk-regmap-mux-div.c #define CMD_RCGR_UPDATE BIT(0) BIT 16 drivers/clk/qcom/clk-regmap-mux-div.c #define CMD_RCGR_DIRTY_CFG BIT(4) BIT 17 drivers/clk/qcom/clk-regmap-mux-div.c #define CMD_RCGR_ROOT_OFF BIT(31) BIT 30 drivers/clk/qcom/clk-regmap-mux-div.c mask = ((BIT(md->hid_width) - 1) << md->hid_shift) | BIT 31 drivers/clk/qcom/clk-regmap-mux-div.c ((BIT(md->src_width) - 1) << md->src_shift); BIT 74 drivers/clk/qcom/clk-regmap-mux-div.c s &= BIT(md->src_width) - 1; BIT 78 drivers/clk/qcom/clk-regmap-mux-div.c d &= BIT(md->hid_width) - 1; BIT 100 drivers/clk/qcom/clk-regmap-mux-div.c max_div = BIT(md->hid_width) - 1; BIT 137 drivers/clk/qcom/clk-regmap-mux-div.c max_div = BIT(md->hid_width) - 1; BIT 82 drivers/clk/qcom/clk-rpmh.c .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ BIT 83 drivers/clk/qcom/clk-rpmh.c BIT(RPMH_ACTIVE_ONLY_STATE) | \ BIT 84 drivers/clk/qcom/clk-rpmh.c BIT(RPMH_SLEEP_STATE)), \ BIT 101 drivers/clk/qcom/clk-rpmh.c .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ BIT 102 drivers/clk/qcom/clk-rpmh.c BIT(RPMH_ACTIVE_ONLY_STATE)), \ BIT 127 drivers/clk/qcom/clk-rpmh.c .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \ BIT 142 drivers/clk/qcom/clk-rpmh.c return (c->last_sent_aggr_state & BIT(state)) BIT 143 drivers/clk/qcom/clk-rpmh.c != (c->aggr_state & BIT(state)); BIT 159 drivers/clk/qcom/clk-rpmh.c if (cmd_state & BIT(state)) BIT 22 drivers/clk/qcom/clk-spmi-pmic-div.c #define REG_EN_MASK BIT(7) BIT 19 drivers/clk/qcom/common.h #define PLL_VOTE_FSM_ENA BIT(20) BIT 20 drivers/clk/qcom/common.h #define PLL_VOTE_FSM_RESET BIT(21) BIT 263 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 276 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 290 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 326 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 345 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 381 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 399 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 417 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 435 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 453 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 471 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 490 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 508 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 526 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 539 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 557 drivers/clk/qcom/dispcc-sdm845.c .enable_mask = BIT(0), BIT 119 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 182 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(1), BIT 209 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(4), BIT 281 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 298 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1324 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1378 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(12), BIT 1395 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(17), BIT 1411 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1428 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1445 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1462 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1479 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1496 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1513 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1530 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1547 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1564 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1581 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1598 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1615 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1632 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1649 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1666 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1683 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1700 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1718 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(15), BIT 1734 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1751 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1768 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1785 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1802 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1819 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1836 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1853 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1870 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1887 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1904 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1921 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1938 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1955 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1972 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 1989 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2006 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2023 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2041 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(10), BIT 2058 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(3), BIT 2075 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(4), BIT 2092 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(5), BIT 2110 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2127 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(1), BIT 2144 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(2), BIT 2162 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2179 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2196 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2213 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2230 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2247 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2264 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2280 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2297 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2314 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2331 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2348 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2365 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2382 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2399 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2416 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2433 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2450 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2467 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2483 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2501 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(13), BIT 2517 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2534 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2551 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2568 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2585 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2602 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2619 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2635 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2652 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2668 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2684 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2700 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2717 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2733 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2750 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2766 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2783 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2800 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2817 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2834 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2850 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2867 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2884 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2901 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2918 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2935 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2952 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2969 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 2986 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3003 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3020 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3036 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3052 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3069 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3086 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3103 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3119 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3135 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3152 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3169 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3185 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3202 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3219 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 3235 drivers/clk/qcom/gcc-apq8084.c .enable_mask = BIT(0), BIT 198 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 215 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 250 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 280 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 322 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 353 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 398 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 429 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 467 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 498 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 529 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 623 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(14), BIT 641 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(10), BIT 657 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 673 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 691 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 708 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(1), BIT 725 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(2), BIT 741 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 759 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(17), BIT 775 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 791 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 807 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 823 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 840 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(8), BIT 856 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 872 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 888 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 904 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 922 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(5), BIT 938 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 954 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 970 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1005 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1021 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1037 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1093 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1110 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1127 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1162 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1179 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1196 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1219 drivers/clk/qcom/gcc-ipq4019.c (BIT(pll_vco->refclkdiv_width) - 1); BIT 1221 drivers/clk/qcom/gcc-ipq4019.c (BIT(pll_vco->fdbkdiv_width) - 1); BIT 1285 drivers/clk/qcom/gcc-ipq4019.c mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift; BIT 1313 drivers/clk/qcom/gcc-ipq4019.c cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); BIT 1361 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 1393 drivers/clk/qcom/gcc-ipq4019.c cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); BIT 1553 drivers/clk/qcom/gcc-ipq4019.c .enable_mask = BIT(0), BIT 46 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(0), BIT 73 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 100 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(8), BIT 205 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(14), BIT 362 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 378 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 413 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 429 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 464 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 480 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 515 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 531 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 566 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 582 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 617 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 633 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 681 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 697 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 730 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 746 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 779 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 795 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 828 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 844 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 877 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 893 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 926 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 942 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 960 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 975 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 990 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1005 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1020 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1035 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1076 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 1092 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 1125 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 1141 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 1174 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 1190 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 1208 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1242 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(10), BIT 1288 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 1303 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 1336 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 1351 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 1369 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1384 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1419 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 1434 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 1452 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1467 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1481 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(2), BIT 1497 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(3), BIT 1511 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(8), BIT 1525 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 1539 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(7), BIT 1555 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(6), BIT 1581 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 1597 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 1613 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1626 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1639 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1652 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1673 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 1689 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 1705 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1718 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1731 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1744 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1765 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 1781 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 1797 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1810 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1823 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1836 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1862 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(7), BIT 1878 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1894 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1910 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1925 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1938 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1951 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1964 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 1999 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 2015 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 2031 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 2069 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 2085 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 2101 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 2139 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 2155 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 2173 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 2203 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(11), BIT 2219 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(9), BIT 2235 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 2251 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 2266 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 2279 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(8), BIT 2335 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(1), BIT 2352 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(4), BIT 2407 drivers/clk/qcom/gcc-ipq806x.c .enable_mask = BIT(1), BIT 2424 drivers/clk/qcom/gcc-ipq806x.c .enable_mask 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drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2292 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2309 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2326 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2344 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(8), BIT 2361 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2378 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2395 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2412 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2429 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2446 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2464 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2481 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2498 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2515 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2532 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2549 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2567 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2584 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2601 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2618 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2635 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2652 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2669 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2687 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2704 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2721 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2738 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2755 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2772 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2789 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2807 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2824 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2841 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2858 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2875 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2892 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2909 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2926 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2943 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2960 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2977 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 2994 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3011 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3028 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3045 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3062 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3079 drivers/clk/qcom/gcc-ipq8074.c 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drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3368 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3385 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3402 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3419 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3436 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3453 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3470 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3487 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3504 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3521 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3538 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3555 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3572 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3589 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3606 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3623 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3640 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3657 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3674 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3691 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3708 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3725 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3742 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3759 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3776 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3793 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3810 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3827 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3844 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3861 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3878 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3895 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3912 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3929 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3946 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3963 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3980 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 3997 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 4014 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 4031 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 4048 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 4065 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 4082 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 4099 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 4116 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 4133 drivers/clk/qcom/gcc-ipq8074.c .enable_mask = BIT(0), BIT 4150 drivers/clk/qcom/gcc-ipq8074.c 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BIT 2685 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2700 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2713 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2726 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2739 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2754 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2769 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2784 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2799 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2814 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2828 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(2), BIT 2844 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(3), BIT 2872 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(7), BIT 2888 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2904 drivers/clk/qcom/gcc-msm8960.c .enable_mask = BIT(4), BIT 2934 drivers/clk/qcom/gcc-msm8960.c .enable_mask = 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BIT 1548 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1565 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1582 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1599 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1616 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1633 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1650 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1667 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1684 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1701 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1719 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(10), BIT 1736 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(3), BIT 1753 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(4), BIT 1770 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(5), BIT 1788 drivers/clk/qcom/gcc-msm8974.c .enable_mask = BIT(0), BIT 1805 drivers/clk/qcom/gcc-msm8974.c .enable_mask = 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drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2087 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2102 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2117 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2132 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2147 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2162 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2177 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2192 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2207 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2222 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2237 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2253 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(13), BIT 2268 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2283 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2298 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2314 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(10), BIT 2329 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2342 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2357 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2372 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2387 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2402 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2417 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2432 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2447 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2463 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2478 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2493 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2508 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2523 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2539 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2554 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2569 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2584 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2599 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2615 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2630 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2645 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2660 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2675 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2702 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2730 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2743 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2755 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2771 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2787 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2803 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2830 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2845 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2860 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2872 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2884 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2899 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2914 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2929 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2944 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2958 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2973 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 2988 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3002 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3016 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3031 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3046 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3060 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3074 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3088 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3102 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3116 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3130 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3144 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3158 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3172 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3186 drivers/clk/qcom/gcc-msm8996.c .enable_mask = BIT(0), BIT 3637 drivers/clk/qcom/gcc-msm8996.c regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); BIT 143 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 204 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(1), BIT 265 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(2), BIT 326 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(3), BIT 387 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(4), BIT 1173 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1186 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1204 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1222 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1235 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1248 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(22), BIT 1261 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1274 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(17), BIT 1287 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1305 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1323 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1341 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1359 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1377 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1395 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1413 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1431 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1449 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1467 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1485 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1503 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(16), BIT 1516 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1534 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1552 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1570 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(15), BIT 1583 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1601 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1619 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1637 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1655 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1673 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1691 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1709 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1727 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1745 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1763 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1781 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1799 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(14), BIT 1812 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1830 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1848 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1866 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1884 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1902 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1920 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1938 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1951 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1964 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1977 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 1990 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(21), BIT 2008 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2021 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2039 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2052 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2071 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2084 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2097 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2110 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2123 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2141 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2154 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2167 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2180 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2193 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2211 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2229 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2242 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2255 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(13), BIT 2268 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2281 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2299 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2312 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2330 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2343 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2356 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2374 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2387 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2405 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2418 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2431 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2444 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2457 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2470 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2483 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2501 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2519 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2532 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2550 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2563 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2575 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2589 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2603 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2617 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2631 drivers/clk/qcom/gcc-msm8998.c .enable_mask = BIT(0), BIT 2991 drivers/clk/qcom/gcc-msm8998.c ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); BIT 293 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(23), BIT 310 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 327 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 343 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(1), BIT 357 drivers/clk/qcom/gcc-qcs404.c .alpha_en_mask = BIT(24), BIT 389 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(5), BIT 417 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(7), BIT 1238 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(14), BIT 1256 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(1), BIT 1269 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1286 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1299 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1317 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1330 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(10), BIT 1343 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1356 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1369 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1387 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1405 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1423 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1441 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1459 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1477 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1495 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1513 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1531 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1549 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1567 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1585 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1603 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1621 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(20), BIT 1634 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1652 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1670 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1688 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(7), BIT 1701 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1714 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(1), BIT 1727 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(2), BIT 1740 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1753 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1771 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1789 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1802 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1815 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1828 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(2), BIT 1841 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(3), BIT 1854 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(9), BIT 1872 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1890 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1908 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1926 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(13), BIT 1939 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(4), BIT 1952 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1965 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1978 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 1996 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2014 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2032 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2050 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2068 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2086 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2104 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2117 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2135 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(27), BIT 2153 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(11), BIT 2166 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(18), BIT 2179 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(28), BIT 2197 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(22), BIT 2210 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2224 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2238 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2256 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2269 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(8), BIT 2283 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2296 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2309 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2322 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(21), BIT 2335 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2348 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2366 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2384 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2397 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2410 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2428 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(12), BIT 2441 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2458 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2471 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2489 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2502 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2520 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2538 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2551 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2568 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2581 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2594 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2612 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 2625 drivers/clk/qcom/gcc-qcs404.c .enable_mask = BIT(0), BIT 158 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 195 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(1), BIT 232 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(4), BIT 985 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1002 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1019 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1032 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(22), BIT 1045 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1058 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(17), BIT 1071 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1089 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1107 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1125 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1143 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1161 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1179 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1197 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1215 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1233 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1251 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(15), BIT 1264 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1282 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1300 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1318 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1336 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1354 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1372 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1390 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1408 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1426 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1444 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(10), BIT 1457 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1474 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1490 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1503 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1521 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1539 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1557 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1570 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1583 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(4), BIT 1600 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(3), BIT 1617 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1631 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1649 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(1), BIT 1666 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1683 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1696 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1708 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1720 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1732 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1744 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1757 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1775 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1788 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(13), BIT 1801 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1814 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1832 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1845 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1858 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1871 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1889 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1907 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1920 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1938 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1951 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1969 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 1982 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2000 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2018 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2031 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2044 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2057 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2075 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2093 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2111 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2124 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2142 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2160 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2173 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2186 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2204 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2217 drivers/clk/qcom/gcc-sdm660.c .enable_mask = BIT(0), BIT 2447 drivers/clk/qcom/gcc-sdm660.c ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); BIT 158 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 173 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(4), BIT 1021 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1036 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1056 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1074 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1092 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1110 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1130 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(10), BIT 1145 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1159 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1172 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1188 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(3), BIT 1201 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(4), BIT 1214 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(5), BIT 1227 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1245 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1263 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(21), BIT 1281 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1299 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1314 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1328 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1340 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(18), BIT 1356 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(19), BIT 1373 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1387 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1405 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1423 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1443 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1456 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(15), BIT 1472 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(16), BIT 1489 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1502 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1515 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1528 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1546 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1561 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1573 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(17), BIT 1588 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1601 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1614 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1627 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1645 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(3), BIT 1665 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(2), BIT 1678 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1691 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(1), BIT 1703 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(4), BIT 1721 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1734 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(5), BIT 1747 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(29), BIT 1767 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(28), BIT 1780 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1793 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(27), BIT 1805 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(30), BIT 1822 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(26), BIT 1835 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(25), BIT 1848 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1866 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1884 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1904 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1917 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1932 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(13), BIT 1947 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1962 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1977 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 1990 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2003 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2021 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(10), BIT 2039 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(11), BIT 2057 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(12), BIT 2075 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(13), BIT 2093 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(14), BIT 2111 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(15), BIT 2129 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(16), BIT 2147 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(17), BIT 2165 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(22), BIT 2183 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(23), BIT 2201 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(24), BIT 2219 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(25), BIT 2237 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(26), BIT 2255 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(27), BIT 2273 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(28), BIT 2291 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(29), BIT 2309 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(6), BIT 2324 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(7), BIT 2337 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(20), BIT 2352 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(21), BIT 2365 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2378 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2396 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2409 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2427 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2445 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2458 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2471 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2491 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2506 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2524 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2539 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2559 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2576 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2588 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2600 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2615 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2633 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2648 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2663 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2683 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2703 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2720 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2732 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2744 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2759 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2777 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2795 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2813 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2826 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2844 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2862 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2875 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2888 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2906 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2923 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2936 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2949 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2967 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2984 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 2999 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3012 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3030 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3048 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3068 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3082 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3095 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3111 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3124 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3142 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3158 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(22), BIT 3174 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 3188 drivers/clk/qcom/gcc-sdm845.c .enable_mask = BIT(0), BIT 47 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 92 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(7), BIT 112 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(9), BIT 1123 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1138 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1157 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 1176 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1195 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 1212 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1229 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1248 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(10), BIT 1267 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1281 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1294 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1308 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1322 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1339 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1356 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(21), BIT 1374 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1391 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(22), BIT 1406 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1419 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1438 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1452 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1465 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1479 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1493 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1506 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1523 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1542 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1555 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1572 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1589 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1608 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1623 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1636 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1649 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1662 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1675 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1690 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1705 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1718 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1735 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1752 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(3), BIT 1771 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(2), BIT 1784 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1797 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 1811 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(4), BIT 1826 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1839 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(5), BIT 1852 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(29), BIT 1871 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(28), BIT 1884 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1897 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(27), BIT 1911 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(30), BIT 1926 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(26), BIT 1939 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(25), BIT 1952 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1969 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 1988 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2001 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2014 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(13), BIT 2029 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2044 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2059 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2074 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2089 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2102 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2115 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2132 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(10), BIT 2149 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(11), BIT 2166 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(12), BIT 2183 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(13), BIT 2200 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(14), BIT 2217 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(15), BIT 2234 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(16), BIT 2251 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(17), BIT 2268 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(22), BIT 2285 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(23), BIT 2302 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(24), BIT 2319 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(25), BIT 2336 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(26), BIT 2353 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(27), BIT 2370 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(4), BIT 2387 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(5), BIT 2404 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(6), BIT 2421 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(7), BIT 2438 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(8), BIT 2455 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(9), BIT 2472 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(6), BIT 2487 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(7), BIT 2500 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(20), BIT 2515 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(21), BIT 2528 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(2), BIT 2543 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 2556 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2569 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2586 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2599 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2616 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2634 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2647 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2660 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2679 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2694 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2713 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 2730 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2745 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2764 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 2783 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2802 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 2821 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2840 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 2857 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2872 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2887 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2906 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 2925 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2944 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 2963 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 2982 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 3001 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3020 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(1), BIT 3037 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3054 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3071 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3084 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3101 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3118 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3131 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3144 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3161 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3178 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3191 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3208 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3231 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3245 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3258 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3271 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 3285 drivers/clk/qcom/gcc-sm8150.c .enable_mask = BIT(0), BIT 18 drivers/clk/qcom/gdsc.c #define PWR_ON_MASK BIT(31) BIT 22 drivers/clk/qcom/gdsc.c #define SW_OVERRIDE_MASK BIT(2) BIT 23 drivers/clk/qcom/gdsc.c #define HW_CONTROL_MASK BIT(1) BIT 24 drivers/clk/qcom/gdsc.c #define SW_COLLAPSE_MASK BIT(0) BIT 25 drivers/clk/qcom/gdsc.c #define GMEM_CLAMP_IO_MASK BIT(0) BIT 26 drivers/clk/qcom/gdsc.c #define GMEM_RESET_MASK BIT(4) BIT 29 drivers/clk/qcom/gdsc.c #define GDSC_POWER_UP_COMPLETE BIT(16) BIT 30 drivers/clk/qcom/gdsc.c #define GDSC_POWER_DOWN_COMPLETE BIT(15) BIT 38 drivers/clk/qcom/gdsc.c #define RETAIN_MEM BIT(14) BIT 39 drivers/clk/qcom/gdsc.c #define RETAIN_PERIPH BIT(13) BIT 39 drivers/clk/qcom/gdsc.h #define PWRSTS_OFF BIT(0) BIT 40 drivers/clk/qcom/gdsc.h #define PWRSTS_RET BIT(1) BIT 41 drivers/clk/qcom/gdsc.h #define PWRSTS_ON BIT(2) BIT 45 drivers/clk/qcom/gdsc.h #define VOTABLE BIT(0) BIT 46 drivers/clk/qcom/gdsc.h #define CLAMP_IO BIT(1) BIT 47 drivers/clk/qcom/gdsc.h #define HW_CTRL BIT(2) BIT 48 drivers/clk/qcom/gdsc.h #define SW_RESET BIT(3) BIT 49 drivers/clk/qcom/gdsc.h #define AON_RESET BIT(4) BIT 50 drivers/clk/qcom/gdsc.h #define POLL_CFG_GDSCR BIT(5) BIT 51 drivers/clk/qcom/gdsc.h #define ALWAYS_ON BIT(6) BIT 98 drivers/clk/qcom/gpucc-sdm845.c .enable_mask = BIT(0), BIT 116 drivers/clk/qcom/gpucc-sdm845.c .enable_mask = BIT(0), BIT 47 drivers/clk/qcom/lcc-ipq806x.c .vco_mask = BIT(17) | BIT(16), BIT 49 drivers/clk/qcom/lcc-ipq806x.c .pre_div_mask = BIT(19), BIT 51 drivers/clk/qcom/lcc-ipq806x.c .post_div_mask = BIT(21) | BIT(20), BIT 52 drivers/clk/qcom/lcc-ipq806x.c .mn_ena_mask = BIT(22), BIT 53 drivers/clk/qcom/lcc-ipq806x.c .main_output_mask = BIT(23), BIT 130 drivers/clk/qcom/lcc-ipq806x.c .enable_mask = BIT(9), BIT 151 drivers/clk/qcom/lcc-ipq806x.c .enable_mask = BIT(17), BIT 182 drivers/clk/qcom/lcc-ipq806x.c .enable_mask = BIT(15), BIT 244 drivers/clk/qcom/lcc-ipq806x.c .enable_mask = BIT(9), BIT 261 drivers/clk/qcom/lcc-ipq806x.c .enable_mask = BIT(11), BIT 324 drivers/clk/qcom/lcc-ipq806x.c .enable_mask = BIT(9), BIT 345 drivers/clk/qcom/lcc-ipq806x.c .enable_mask = BIT(12), BIT 383 drivers/clk/qcom/lcc-ipq806x.c .enable_mask = BIT(11), BIT 113 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(9), BIT 134 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(17), BIT 151 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(15), BIT 167 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(15), BIT 219 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(9), \ BIT 240 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(21), \ BIT 271 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(19), \ BIT 363 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(9), BIT 380 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(11), BIT 431 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(9), BIT 452 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(10), BIT 469 drivers/clk/qcom/lcc-mdm9615.c .enable_mask = BIT(12), BIT 111 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(9), BIT 132 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(17), BIT 149 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(15), BIT 165 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(15), BIT 217 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(9), \ BIT 238 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(21), \ BIT 269 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(19), \ BIT 361 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(9), BIT 378 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(11), BIT 429 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(9), BIT 450 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(10), BIT 467 drivers/clk/qcom/lcc-msm8960.c .enable_mask = BIT(12), BIT 22 drivers/clk/qcom/lpasscc-sdm845.c .enable_mask = BIT(0), BIT 35 drivers/clk/qcom/lpasscc-sdm845.c .enable_mask = BIT(0), BIT 49 drivers/clk/qcom/lpasscc-sdm845.c .enable_mask = BIT(0), BIT 63 drivers/clk/qcom/lpasscc-sdm845.c .enable_mask = BIT(0), BIT 77 drivers/clk/qcom/lpasscc-sdm845.c .enable_mask = BIT(0), BIT 232 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 259 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(1), BIT 1104 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1119 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1136 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1153 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1170 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1187 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1204 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1221 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1238 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1255 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1271 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1288 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1304 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1321 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1338 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1355 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1372 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1389 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1406 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1423 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1440 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1457 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1473 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1490 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1507 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1524 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1541 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1557 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1574 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1591 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1608 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1625 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1642 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1659 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1676 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1693 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1710 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1727 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1744 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1761 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1777 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1793 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1810 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1827 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1844 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1861 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1877 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1894 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1911 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1928 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1945 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1962 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1979 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 1996 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2013 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2030 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2047 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2064 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2081 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2098 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2115 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2132 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2149 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2166 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2183 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2200 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2217 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2234 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2251 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2268 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2285 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2302 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2319 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2336 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2353 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2370 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2387 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2404 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2421 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2438 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2455 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2472 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2489 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2506 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2523 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2540 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2557 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2574 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2591 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2608 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2626 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2643 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2660 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2677 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2694 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2711 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2728 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2745 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2762 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2779 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2796 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2813 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2830 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2847 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2864 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2881 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2898 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2915 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2932 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2949 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2966 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2981 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 2998 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 3015 drivers/clk/qcom/mmcc-apq8084.c .enable_mask = BIT(0), BIT 3038 drivers/clk/qcom/mmcc-apq8084.c .mn_ena_mask = BIT(24), BIT 3039 drivers/clk/qcom/mmcc-apq8084.c .main_output_mask = BIT(0), BIT 3052 drivers/clk/qcom/mmcc-apq8084.c .mn_ena_mask = BIT(24), BIT 3053 drivers/clk/qcom/mmcc-apq8084.c .main_output_mask = BIT(0), BIT 3054 drivers/clk/qcom/mmcc-apq8084.c .aux_output_mask = BIT(1), BIT 147 drivers/clk/qcom/mmcc-msm8960.c .pre_div_mask = BIT(19), BIT 150 drivers/clk/qcom/mmcc-msm8960.c .mn_ena_mask = BIT(22), BIT 151 drivers/clk/qcom/mmcc-msm8960.c .main_output_mask = BIT(23), BIT 192 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 207 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 241 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 256 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 290 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 305 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 345 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 360 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 376 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(8), BIT 409 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 424 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 440 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(8), BIT 473 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 488 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 504 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(8), BIT 613 drivers/clk/qcom/mmcc-msm8960.c .s_mask = BIT(25), BIT 615 drivers/clk/qcom/mmcc-msm8960.c .s2_mask = BIT(13), BIT 618 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(26), BIT 630 drivers/clk/qcom/mmcc-msm8960.c .s_mask = BIT(8), BIT 632 drivers/clk/qcom/mmcc-msm8960.c .s2_mask = BIT(9), BIT 635 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(10), BIT 647 drivers/clk/qcom/mmcc-msm8960.c .s_mask = BIT(12), BIT 649 drivers/clk/qcom/mmcc-msm8960.c .s2_mask = BIT(12), BIT 652 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(13), BIT 664 drivers/clk/qcom/mmcc-msm8960.c .s_mask = BIT(0), BIT 666 drivers/clk/qcom/mmcc-msm8960.c .s2_mask = BIT(1), BIT 669 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 681 drivers/clk/qcom/mmcc-msm8960.c .s_mask = BIT(4), BIT 683 drivers/clk/qcom/mmcc-msm8960.c .s2_mask = BIT(5), BIT 686 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(6), BIT 725 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 742 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 758 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(9), BIT 774 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(11), BIT 835 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 850 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 895 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 910 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 996 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 1018 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1074 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 1089 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1105 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(13), BIT 1153 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 1168 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1201 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 1216 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1281 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 1296 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1312 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1328 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(6), BIT 1380 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 1395 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1443 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 1461 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(8), BIT 1477 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(10), BIT 1493 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1509 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(12), BIT 1525 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(14), BIT 1541 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(16), BIT 1557 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(11), BIT 1614 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 1629 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1665 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 1680 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1733 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 1748 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 1764 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(12), BIT 1780 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(24), BIT 1795 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(21), BIT 1810 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(22), BIT 1823 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(25), BIT 1838 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(23), BIT 1853 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(25), BIT 1868 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(19), BIT 1881 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(18), BIT 1896 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(23), BIT 1911 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(24), BIT 1926 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(12), BIT 1941 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(26), BIT 1956 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(25), BIT 1969 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(24), BIT 1982 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(7), BIT 1995 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(9), BIT 2010 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(18), BIT 2023 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(17), BIT 2038 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(22), BIT 2067 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 2083 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 2115 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 2131 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 2154 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 2170 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 2193 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 2209 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 2232 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 2247 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 2270 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 2285 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 2317 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 2332 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 2364 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 2379 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(0), BIT 2397 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(19), BIT 2412 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(2), BIT 2427 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(3), BIT 2442 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(14), BIT 2457 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(4), BIT 2470 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(5), BIT 2485 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(6), BIT 2498 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(21), BIT 2511 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(10), BIT 2524 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(12), BIT 2539 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(15), BIT 2552 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(25), BIT 2565 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(1), BIT 2580 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(11), BIT 2593 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(13), BIT 2606 drivers/clk/qcom/mmcc-msm8960.c .enable_mask = BIT(16), BIT 197 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 224 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(1), BIT 938 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 954 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 971 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 987 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1004 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1021 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1038 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1055 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1071 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1088 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1105 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1122 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1139 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1155 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1172 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1189 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1206 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1223 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1239 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1256 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1273 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1290 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1307 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1324 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1341 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1358 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1375 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1391 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1408 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1425 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1442 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1458 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1474 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1491 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1508 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1525 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1542 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1559 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1575 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1592 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1609 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1626 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1642 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1658 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1675 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1692 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1709 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1725 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1741 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1758 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1774 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1791 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1808 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1825 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1842 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1859 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1876 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1893 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1910 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1927 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1943 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1960 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1977 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 1994 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2011 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2028 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2045 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2061 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2078 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2095 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2112 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2129 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2145 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2162 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2179 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2196 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2213 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2229 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2245 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2261 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2277 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2294 drivers/clk/qcom/mmcc-msm8974.c .enable_mask = BIT(0), BIT 2317 drivers/clk/qcom/mmcc-msm8974.c .mn_ena_mask = BIT(24), BIT 2318 drivers/clk/qcom/mmcc-msm8974.c .main_output_mask = BIT(0), BIT 2331 drivers/clk/qcom/mmcc-msm8974.c .mn_ena_mask = BIT(24), BIT 2332 drivers/clk/qcom/mmcc-msm8974.c .main_output_mask = BIT(0), BIT 2333 drivers/clk/qcom/mmcc-msm8974.c .aux_output_mask = BIT(1), BIT 265 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 295 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(1), BIT 1233 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1248 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1263 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1278 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1292 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1307 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1322 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1337 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1352 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1367 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1382 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1397 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1412 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1427 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1442 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1457 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1472 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1487 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1502 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1517 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1532 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1547 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1562 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1577 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1592 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1607 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1622 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1637 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1652 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1667 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1682 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1697 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1712 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1727 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1742 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1757 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1772 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1787 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1802 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1817 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1832 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1847 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1862 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1877 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1892 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1907 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1922 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1937 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1952 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1967 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1982 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 1997 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2012 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2027 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2042 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2057 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2072 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2087 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2102 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2117 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2132 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2147 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2162 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2177 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2192 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2207 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2222 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2237 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2252 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2267 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2282 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2297 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2312 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2327 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2342 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2357 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2372 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2387 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2402 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2417 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2432 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2447 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2462 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2477 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2492 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2507 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2522 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2537 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2552 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2567 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2582 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2597 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2612 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2627 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2642 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2657 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2672 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2687 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2702 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2717 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2732 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2747 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2762 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2777 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2792 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2807 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2822 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2837 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2852 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2867 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 2882 drivers/clk/qcom/mmcc-msm8996.c .enable_mask = BIT(0), BIT 3361 drivers/clk/qcom/mmcc-msm8996.c regmap_update_bits(regmap, 0x50d8, BIT(31), 0); BIT 3363 drivers/clk/qcom/mmcc-msm8996.c regmap_update_bits(regmap, 0x5054, BIT(15), 0); BIT 31 drivers/clk/qcom/reset.c mask = BIT(map->bit); BIT 45 drivers/clk/qcom/reset.c mask = BIT(map->bit); BIT 27 drivers/clk/qcom/turingcc-qcs404.c .enable_mask = BIT(0), BIT 40 drivers/clk/qcom/turingcc-qcs404.c .enable_mask = BIT(0), BIT 53 drivers/clk/qcom/turingcc-qcs404.c .enable_mask = BIT(0), BIT 66 drivers/clk/qcom/turingcc-qcs404.c .enable_mask = BIT(0), BIT 79 drivers/clk/qcom/turingcc-qcs404.c .enable_mask = BIT(0), BIT 93 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 106 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 119 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 132 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 145 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 158 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 176 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 189 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 207 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 220 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 233 drivers/clk/qcom/videocc-sdm845.c .enable_mask = BIT(0), BIT 22 drivers/clk/renesas/clk-div6.c #define CPG_DIV6_CKSTP BIT(8) BIT 140 drivers/clk/renesas/clk-div6.c (BIT(clock->src_width) - 1); BIT 160 drivers/clk/renesas/clk-div6.c mask = ~((BIT(clock->src_width) - 1) << clock->src_shift); BIT 79 drivers/clk/renesas/clk-mstp.c u32 bitmask = BIT(clock->bit_index); BIT 140 drivers/clk/renesas/clk-mstp.c return !(value & BIT(clock->bit_index)); BIT 34 drivers/clk/renesas/clk-r8a73a4.c #define CLK_ENABLE_ON_INIT BIT(0) BIT 100 drivers/clk/renesas/clk-r8a73a4.c if (value & BIT(20)) BIT 108 drivers/clk/renesas/clk-r8a73a4.c if (value & BIT(7)) BIT 30 drivers/clk/renesas/clk-r8a7740.c #define CLK_ENABLE_ON_INIT BIT(0) BIT 73 drivers/clk/renesas/clk-r8a7740.c switch (cpg_mode & (BIT(2) | BIT(1))) { BIT 74 drivers/clk/renesas/clk-r8a7740.c case BIT(1) | BIT(2): BIT 79 drivers/clk/renesas/clk-r8a7740.c case BIT(2): BIT 91 drivers/clk/renesas/clk-r8a7740.c if (cpg_mode & BIT(1)) BIT 113 drivers/clk/renesas/clk-r8a7740.c if (value & BIT(7)) BIT 118 drivers/clk/renesas/clk-r8a7740.c if (!(value & BIT(6))) BIT 89 drivers/clk/renesas/clk-r8a7778.c BUG_ON(!(mode & BIT(19))); BIT 91 drivers/clk/renesas/clk-r8a7778.c cpg_mode_rates = (!!(mode & BIT(18)) << 2) | BIT 92 drivers/clk/renesas/clk-r8a7778.c (!!(mode & BIT(12)) << 1) | BIT 93 drivers/clk/renesas/clk-r8a7778.c (!!(mode & BIT(11))); BIT 94 drivers/clk/renesas/clk-r8a7778.c cpg_mode_divs = (!!(mode & BIT(2)) << 1) | BIT 95 drivers/clk/renesas/clk-r8a7778.c (!!(mode & BIT(1))); BIT 53 drivers/clk/renesas/clk-r8a7779.c #define CPG_CLK_CONFIG_INDEX(md) (((md) & (BIT(2)|BIT(1))) >> 1) BIT 81 drivers/clk/renesas/clk-r8a7779.c #define CPG_PLLA_MULT_INDEX(md) (((md) & (BIT(12)|BIT(11))) >> 11) BIT 29 drivers/clk/renesas/clk-rcar-gen2.c #define CPG_FRQCRB_KICK BIT(31) BIT 265 drivers/clk/renesas/clk-rcar-gen2.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ BIT 266 drivers/clk/renesas/clk-rcar-gen2.c (((md) & BIT(13)) >> 12) | \ BIT 267 drivers/clk/renesas/clk-rcar-gen2.c (((md) & BIT(19)) >> 19)) BIT 344 drivers/clk/renesas/clk-rcar-gen2.c div = cpg_mode & BIT(18) ? 36 : 24; BIT 347 drivers/clk/renesas/clk-rcar-gen2.c div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) BIT 38 drivers/clk/renesas/clk-sh73a0.c #define CLK_ENABLE_ON_INIT BIT(0) BIT 111 drivers/clk/renesas/clk-sh73a0.c if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { BIT 115 drivers/clk/renesas/clk-sh73a0.c if (readl(enable_reg) & BIT(20)) BIT 220 drivers/clk/renesas/r8a7743-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ BIT 221 drivers/clk/renesas/r8a7743-cpg-mssr.c (((md) & BIT(13)) >> 12) | \ BIT 222 drivers/clk/renesas/r8a7743-cpg-mssr.c (((md) & BIT(19)) >> 19)) BIT 201 drivers/clk/renesas/r8a7745-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ BIT 202 drivers/clk/renesas/r8a7745-cpg-mssr.c (((md) & BIT(13)) >> 13)) BIT 184 drivers/clk/renesas/r8a77470-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ BIT 185 drivers/clk/renesas/r8a77470-cpg-mssr.c (((md) & BIT(13)) >> 13)) BIT 268 drivers/clk/renesas/r8a774a1-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ BIT 269 drivers/clk/renesas/r8a774a1-cpg-mssr.c (((md) & BIT(13)) >> 11) | \ BIT 270 drivers/clk/renesas/r8a774a1-cpg-mssr.c (((md) & BIT(19)) >> 18) | \ BIT 271 drivers/clk/renesas/r8a774a1-cpg-mssr.c (((md) & BIT(17)) >> 17)) BIT 254 drivers/clk/renesas/r8a774c0-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) BIT 235 drivers/clk/renesas/r8a7790-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ BIT 236 drivers/clk/renesas/r8a7790-cpg-mssr.c (((md) & BIT(13)) >> 12) | \ BIT 237 drivers/clk/renesas/r8a7790-cpg-mssr.c (((md) & BIT(19)) >> 19)) BIT 233 drivers/clk/renesas/r8a7791-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ BIT 234 drivers/clk/renesas/r8a7791-cpg-mssr.c (((md) & BIT(13)) >> 12) | \ BIT 235 drivers/clk/renesas/r8a7791-cpg-mssr.c (((md) & BIT(19)) >> 19)) BIT 179 drivers/clk/renesas/r8a7792-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ BIT 180 drivers/clk/renesas/r8a7792-cpg-mssr.c (((md) & BIT(13)) >> 12) | \ BIT 181 drivers/clk/renesas/r8a7792-cpg-mssr.c (((md) & BIT(19)) >> 19)) BIT 211 drivers/clk/renesas/r8a7794-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ BIT 212 drivers/clk/renesas/r8a7794-cpg-mssr.c (((md) & BIT(13)) >> 13)) BIT 311 drivers/clk/renesas/r8a7795-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ BIT 312 drivers/clk/renesas/r8a7795-cpg-mssr.c (((md) & BIT(13)) >> 11) | \ BIT 313 drivers/clk/renesas/r8a7795-cpg-mssr.c (((md) & BIT(19)) >> 18) | \ BIT 314 drivers/clk/renesas/r8a7795-cpg-mssr.c (((md) & BIT(17)) >> 17)) BIT 282 drivers/clk/renesas/r8a7796-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ BIT 283 drivers/clk/renesas/r8a7796-cpg-mssr.c (((md) & BIT(13)) >> 11) | \ BIT 284 drivers/clk/renesas/r8a7796-cpg-mssr.c (((md) & BIT(19)) >> 18) | \ BIT 285 drivers/clk/renesas/r8a7796-cpg-mssr.c (((md) & BIT(17)) >> 17)) BIT 284 drivers/clk/renesas/r8a77965-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ BIT 285 drivers/clk/renesas/r8a77965-cpg-mssr.c (((md) & BIT(13)) >> 11) | \ BIT 286 drivers/clk/renesas/r8a77965-cpg-mssr.c (((md) & BIT(19)) >> 18) | \ BIT 287 drivers/clk/renesas/r8a77965-cpg-mssr.c (((md) & BIT(17)) >> 17)) BIT 189 drivers/clk/renesas/r8a77970-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ BIT 190 drivers/clk/renesas/r8a77970-cpg-mssr.c (((md) & BIT(13)) >> 12) | \ BIT 191 drivers/clk/renesas/r8a77970-cpg-mssr.c (((md) & BIT(19)) >> 19)) BIT 200 drivers/clk/renesas/r8a77980-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ BIT 201 drivers/clk/renesas/r8a77980-cpg-mssr.c (((md) & BIT(13)) >> 13)) BIT 259 drivers/clk/renesas/r8a77990-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) BIT 198 drivers/clk/renesas/r8a77995-cpg-mssr.c #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) BIT 659 drivers/clk/renesas/r9a06g032-clocks.c writel(div | BIT(31), reg); BIT 22 drivers/clk/renesas/rcar-gen2-cpg.c #define CPG_FRQCRB_KICK BIT(31) BIT 263 drivers/clk/renesas/rcar-gen2-cpg.c #define SD_SKIP_FIRST BIT(0) /* Skip first clock in SD table */ BIT 326 drivers/clk/renesas/rcar-gen2-cpg.c div = cpg_mode & BIT(18) ? 36 : 24; BIT 354 drivers/clk/renesas/rcar-gen2-cpg.c div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ? BIT 32 drivers/clk/renesas/rcar-gen3-cpg.c #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ BIT 90 drivers/clk/renesas/rcar-gen3-cpg.c #define CPG_FRQCRB_KICK BIT(31) BIT 215 drivers/clk/renesas/rcar-gen3-cpg.c #define CPG_SD_STP_HCK BIT(9) BIT 216 drivers/clk/renesas/rcar-gen3-cpg.c #define CPG_SD_STP_CK BIT(8) BIT 375 drivers/clk/renesas/rcar-gen3-cpg.c #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ BIT 376 drivers/clk/renesas/rcar-gen3-cpg.c #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ BIT 377 drivers/clk/renesas/rcar-gen3-cpg.c #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ BIT 640 drivers/clk/renesas/rcar-gen3-cpg.c if (cpg_mode & BIT(28)) BIT 649 drivers/clk/renesas/rcar-gen3-cpg.c if (cpg_mode & BIT(core->offset)) { BIT 25 drivers/clk/renesas/rcar-usb2-clock-sel.c #define CLKSET0_INTCLK_EN BIT(11) BIT 26 drivers/clk/renesas/rcar-usb2-clock-sel.c #define CLKSET0_PRIVATE BIT(0) BIT 171 drivers/clk/renesas/renesas-cpg-mssr.c u32 bitmask = BIT(bit); BIT 241 drivers/clk/renesas/renesas-cpg-mssr.c return !(value & BIT(clock->index % 32)); BIT 441 drivers/clk/renesas/renesas-cpg-mssr.c priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); BIT 575 drivers/clk/renesas/renesas-cpg-mssr.c u32 bitmask = BIT(bit); BIT 596 drivers/clk/renesas/renesas-cpg-mssr.c u32 bitmask = BIT(bit); BIT 610 drivers/clk/renesas/renesas-cpg-mssr.c u32 bitmask = BIT(bit); BIT 624 drivers/clk/renesas/renesas-cpg-mssr.c u32 bitmask = BIT(bit); BIT 184 drivers/clk/rockchip/clk-half-divider.c mux->mask = BIT(mux_width) - 1; BIT 58 drivers/clk/rockchip/clk-inverter.c reg &= ~BIT(inv_clock->shift); BIT 33 drivers/clk/rockchip/clk-mmc-phase.c #define ROCKCHIP_MMC_DELAY_SEL BIT(10) BIT 99 drivers/clk/rockchip/clk-pll.c if (val & BIT(pll->lock_shift)) BIT 580 drivers/clk/rockchip/clk-pll.c #define RK3399_PLLCON2_LOCK_STATUS BIT(31) BIT 581 drivers/clk/rockchip/clk-pll.c #define RK3399_PLLCON3_PWRDOWN BIT(0) BIT 61 drivers/clk/rockchip/clk.c mux->mask = BIT(mux_width) - 1; BIT 281 drivers/clk/rockchip/clk.c frac_mux->mask = BIT(child->mux_width) - 1; BIT 46 drivers/clk/rockchip/clk.h #define BOOST_BUSY_STATE BIT(8) BIT 293 drivers/clk/rockchip/clk.h #define ROCKCHIP_PLL_SYNC_RATE BIT(0) BIT 365 drivers/clk/rockchip/clk.h #define ROCKCHIP_DDRCLK_SIP BIT(0) BIT 375 drivers/clk/rockchip/clk.h #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0) BIT 853 drivers/clk/rockchip/clk.h #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) BIT 32 drivers/clk/rockchip/softrst.c writel(BIT(offset) | (BIT(offset) << 16), BIT 41 drivers/clk/rockchip/softrst.c writel(reg | BIT(offset), softrst->reg_base + (bank * 4)); BIT 59 drivers/clk/rockchip/softrst.c writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); BIT 67 drivers/clk/rockchip/softrst.c writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4)); BIT 672 drivers/clk/samsung/clk-exynos5250.c { SRC_TOP3, 0, BIT(4) }, /* MUX mout_aclk200_disp1_sub */ BIT 673 drivers/clk/samsung/clk-exynos5250.c { SRC_TOP3, 0, BIT(6) }, /* MUX mout_aclk300_disp1_sub */ BIT 1231 drivers/clk/samsung/clk-exynos5420.c { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ BIT 1232 drivers/clk/samsung/clk-exynos5420.c { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ BIT 1233 drivers/clk/samsung/clk-exynos5420.c { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ BIT 1254 drivers/clk/samsung/clk-exynos5420.c { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ BIT 1264 drivers/clk/samsung/clk-exynos5420.c { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */ BIT 1279 drivers/clk/samsung/clk-exynos5420.c { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ BIT 1302 drivers/clk/samsung/clk-exynos5420.c { SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */ BIT 1316 drivers/clk/samsung/clk-exynos5420.c { SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */ BIT 72 drivers/clk/samsung/clk-pll.c tmp |= BIT(pll->enable_offs); BIT 79 drivers/clk/samsung/clk-pll.c } while (!(tmp & BIT(pll->lock_offs))); BIT 90 drivers/clk/samsung/clk-pll.c tmp &= ~BIT(pll->enable_offs); BIT 244 drivers/clk/samsung/clk-pll.c if (tmp & BIT(pll->enable_offs)) { BIT 248 drivers/clk/samsung/clk-pll.c } while (!(tmp & BIT(pll->lock_offs))); BIT 360 drivers/clk/samsung/clk-pll.c if (pll_con0 & BIT(pll->enable_offs)) { BIT 364 drivers/clk/samsung/clk-pll.c } while (!(tmp & BIT(pll->lock_offs))); BIT 397 drivers/clk/samsung/clk-pll.c #define PLL45XX_ENABLE BIT(31) BIT 398 drivers/clk/samsung/clk-pll.c #define PLL45XX_LOCKED BIT(29) BIT 543 drivers/clk/samsung/clk-pll.c #define PLL46XX_ENABLE BIT(31) BIT 544 drivers/clk/samsung/clk-pll.c #define PLL46XX_LOCKED BIT(29) BIT 545 drivers/clk/samsung/clk-pll.c #define PLL46XX_VSEL BIT(27) BIT 843 drivers/clk/samsung/clk-pll.c pll_en &= ~BIT(bit); BIT 845 drivers/clk/samsung/clk-pll.c pll_en |= BIT(bit); BIT 850 drivers/clk/samsung/clk-pll.c if (enable && (pll_en_orig & BIT(bit))) BIT 42 drivers/clk/samsung/clk-pll.h ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s))) BIT 30 drivers/clk/sirf/atlas6.h #define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1) BIT 31 drivers/clk/sirf/atlas6.h #define SIRFSOC_USBPHY_PLL_BYPASS BIT(2) BIT 32 drivers/clk/sirf/atlas6.h #define SIRFSOC_USBPHY_PLL_LOCK BIT(3) BIT 363 drivers/clk/sirf/clk-atlas7.c u32 nr = (regfreq >> 16 & (BIT(3) - 1)) + 1; BIT 364 drivers/clk/sirf/clk-atlas7.c u32 nf = (regfreq & (BIT(9) - 1)) + 1; BIT 365 drivers/clk/sirf/clk-atlas7.c u32 ssdiv = regssc >> 8 & (BIT(12) - 1); BIT 366 drivers/clk/sirf/clk-atlas7.c u32 ssdepth = regssc >> 20 & (BIT(2) - 1); BIT 367 drivers/clk/sirf/clk-atlas7.c u32 ssmod = regssc & (BIT(8) - 1); BIT 493 drivers/clk/sirf/clk-atlas7.c return !!(clkc_readl(reg) & BIT(0)); BIT 503 drivers/clk/sirf/clk-atlas7.c val = clkc_readl(reg) | BIT(0); BIT 515 drivers/clk/sirf/clk-atlas7.c val = clkc_readl(reg) & ~BIT(0); BIT 528 drivers/clk/sirf/clk-atlas7.c if (droff & BIT(0)) BIT 1210 drivers/clk/sirf/clk-atlas7.c return !!(clkc_readl(reg) & BIT(clk->bit)); BIT 1222 drivers/clk/sirf/clk-atlas7.c clkc_writel(BIT(clk->bit), reg); BIT 1224 drivers/clk/sirf/clk-atlas7.c clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_CLR); BIT 1226 drivers/clk/sirf/clk-atlas7.c clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_SLVRDY_SET); BIT 1242 drivers/clk/sirf/clk-atlas7.c clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_SET); BIT 1244 drivers/clk/sirf/clk-atlas7.c BIT(clk->idle_bit)) && (i++ < 100)) { BIT 1252 drivers/clk/sirf/clk-atlas7.c clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_CLR); BIT 1257 drivers/clk/sirf/clk-atlas7.c clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_SLVRDY_CLR); BIT 1259 drivers/clk/sirf/clk-atlas7.c clkc_writel(BIT(clk->bit), reg); BIT 81 drivers/clk/sirf/clk-common.c if (clkc_readl(regcfg2) & BIT(2)) { BIT 87 drivers/clk/sirf/clk-common.c u32 nf = (cfg0 & (BIT(13) - 1)) + 1; BIT 88 drivers/clk/sirf/clk-common.c u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; BIT 89 drivers/clk/sirf/clk-common.c u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; BIT 108 drivers/clk/sirf/clk-common.c if (nf > BIT(13)) BIT 109 drivers/clk/sirf/clk-common.c nf = BIT(13); BIT 116 drivers/clk/sirf/clk-common.c if (nr > BIT(6)) BIT 117 drivers/clk/sirf/clk-common.c nr = BIT(6); BIT 138 drivers/clk/sirf/clk-common.c if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) BIT 145 drivers/clk/sirf/clk-common.c BUG_ON((fin % MHZ) || nr > BIT(6)); BIT 156 drivers/clk/sirf/clk-common.c while (!(clkc_readl(reg) & BIT(6))) BIT 306 drivers/clk/sirf/clk-common.c WARN_ON((cfg & (BIT(3) - 1)) > 4); BIT 308 drivers/clk/sirf/clk-common.c return cfg & (BIT(3) - 1); BIT 321 drivers/clk/sirf/clk-common.c cfg &= ~(BIT(3) - 1); BIT 324 drivers/clk/sirf/clk-common.c while (clkc_readl(clk->regofs) & BIT(3)) BIT 339 drivers/clk/sirf/clk-common.c if (cfg & BIT(24)) { BIT 346 drivers/clk/sirf/clk-common.c u32 wait = (cfg >> 16) & (BIT(4) - 1); BIT 347 drivers/clk/sirf/clk-common.c u32 hold = (cfg >> 20) & (BIT(4) - 1); BIT 366 drivers/clk/sirf/clk-common.c if (ratio > BIT(bits + 1)) BIT 367 drivers/clk/sirf/clk-common.c ratio = BIT(bits + 1); BIT 387 drivers/clk/sirf/clk-common.c if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) BIT 396 drivers/clk/sirf/clk-common.c reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); BIT 397 drivers/clk/sirf/clk-common.c reg |= (wait << 16) | (hold << 20) | BIT(25); BIT 401 drivers/clk/sirf/clk-common.c while (clkc_readl(clk->regofs) & BIT(25)) BIT 645 drivers/clk/sirf/clk-common.c return !!(clkc_readl(reg) & BIT(bit)); BIT 660 drivers/clk/sirf/clk-common.c val = clkc_readl(reg) | BIT(bit); BIT 677 drivers/clk/sirf/clk-common.c val = clkc_readl(reg) & ~BIT(bit); BIT 24 drivers/clk/sirf/prima2.h #define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1) BIT 25 drivers/clk/sirf/prima2.h #define SIRFSOC_USBPHY_PLL_BYPASS BIT(2) BIT 26 drivers/clk/sirf/prima2.h #define SIRFSOC_USBPHY_PLL_LOCK BIT(3) BIT 49 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 51 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); BIT 53 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 55 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); BIT 57 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 59 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 61 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 63 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), 0, 0); BIT 65 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(18), 0, 0); BIT 67 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 69 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE); BIT 754 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 756 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); BIT 758 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); BIT 760 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); BIT 762 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); BIT 764 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); BIT 766 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); BIT 768 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); BIT 770 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); BIT 772 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); BIT 774 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); BIT 776 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); BIT 778 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); BIT 780 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0); BIT 827 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); BIT 829 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); BIT 831 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 833 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); BIT 835 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); BIT 837 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); BIT 839 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); BIT 841 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); BIT 843 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); BIT 845 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); BIT 847 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); BIT 849 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); BIT 851 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); BIT 853 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); BIT 855 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); BIT 857 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); BIT 859 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); BIT 861 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); BIT 863 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); BIT 865 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); BIT 867 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); BIT 869 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); BIT 871 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); BIT 873 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); BIT 875 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); BIT 877 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0); BIT 879 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0); BIT 881 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0); BIT 883 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0); BIT 885 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0); BIT 887 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0); BIT 889 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0); BIT 891 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); BIT 893 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); BIT 895 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 897 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); BIT 899 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); BIT 901 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); BIT 903 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); BIT 905 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); BIT 907 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); BIT 909 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); BIT 911 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); BIT 913 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); BIT 915 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); BIT 917 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); BIT 919 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); BIT 921 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); BIT 923 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); BIT 925 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); BIT 927 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); BIT 929 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); BIT 931 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); BIT 933 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); BIT 935 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); BIT 937 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); BIT 939 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); BIT 941 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0); BIT 943 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0); BIT 945 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0); BIT 947 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0); BIT 949 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0); BIT 951 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0); BIT 953 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0); BIT 955 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), 0, 0); BIT 957 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(4), 0, 0); BIT 959 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(6), 0, 0); BIT 961 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(9), 0, 0); BIT 963 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); BIT 965 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); BIT 967 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 969 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); BIT 971 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); BIT 973 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); BIT 975 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); BIT 977 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); BIT 979 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); BIT 981 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); BIT 983 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); BIT 985 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); BIT 987 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); BIT 989 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); BIT 991 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); BIT 993 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); BIT 995 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); BIT 997 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); BIT 999 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0); BIT 1225 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(0), 0, 0); BIT 1227 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(1), 0, 0); BIT 1229 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(2), 0, 0); BIT 1231 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(3), 0, 0); BIT 1233 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(4), 0, 0); BIT 1235 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(5), 0, 0); BIT 1237 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(6), 0, 0); BIT 1239 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(10), 0, 0); BIT 1241 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(11), 0, 0); BIT 1243 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(12), 0, 0); BIT 1245 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(13), 0, 0); BIT 1247 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(14), 0, 0); BIT 1249 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(15), 0, 0); BIT 1251 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(16), CLK_IGNORE_UNUSED, 0); BIT 1253 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(17), 0, 0); BIT 1255 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(18), 0, 0); BIT 1257 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(19), 0, 0); BIT 1259 drivers/clk/sprd/sc9860-clk.c 0x0, 0x100, BIT(20), 0, 0); BIT 1386 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(0), 0, 0); BIT 1388 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(1), 0, 0); BIT 1390 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), 0, 0); BIT 1392 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(3), 0, 0); BIT 1394 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(4), 0, 0); BIT 1396 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(5), 0, 0); BIT 1398 drivers/clk/sprd/sc9860-clk.c BIT(0), 0, 0); BIT 1400 drivers/clk/sprd/sc9860-clk.c BIT(1), 0, 0); BIT 1402 drivers/clk/sprd/sc9860-clk.c BIT(2), 0, 0); BIT 1404 drivers/clk/sprd/sc9860-clk.c BIT(8), 0, 0); BIT 1406 drivers/clk/sprd/sc9860-clk.c BIT(9), 0, 0); BIT 1408 drivers/clk/sprd/sc9860-clk.c BIT(10), 0, 0); BIT 1461 drivers/clk/sprd/sc9860-clk.c BIT(16), 0, 0); BIT 1463 drivers/clk/sprd/sc9860-clk.c BIT(16), 0, 0); BIT 1494 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(0), 0, 0); BIT 1496 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(1), 0, 0); BIT 1498 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), 0, 0); BIT 1500 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(3), 0, 0); BIT 1502 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(4), 0, 0); BIT 1504 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(5), 0, 0); BIT 1506 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(6), 0, 0); BIT 1508 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(7), 0, 0); BIT 1510 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(8), 0, 0); BIT 1512 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(9), 0, 0); BIT 1514 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(10), 0, 0); BIT 1516 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(11), 0, 0); BIT 1518 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(12), 0, 0); BIT 1520 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(13), 0, 0); BIT 1522 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(14), 0, 0); BIT 1524 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(15), 0, 0); BIT 1526 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(16), 0, 0); BIT 1528 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(17), 0, 0); BIT 1530 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(18), 0, 0); BIT 1532 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(19), 0, 0); BIT 1534 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(20), 0, 0); BIT 1536 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(21), 0, 0); BIT 1538 drivers/clk/sprd/sc9860-clk.c BIT(0), 0, 0); BIT 1540 drivers/clk/sprd/sc9860-clk.c BIT(1), 0, 0); BIT 1542 drivers/clk/sprd/sc9860-clk.c BIT(2), 0, 0); BIT 1544 drivers/clk/sprd/sc9860-clk.c BIT(3), 0, 0); BIT 1546 drivers/clk/sprd/sc9860-clk.c BIT(4), 0, 0); BIT 1548 drivers/clk/sprd/sc9860-clk.c BIT(5), 0, 0); BIT 1550 drivers/clk/sprd/sc9860-clk.c BIT(6), 0, 0); BIT 1552 drivers/clk/sprd/sc9860-clk.c BIT(7), 0, 0); BIT 1554 drivers/clk/sprd/sc9860-clk.c BIT(8), 0, 0); BIT 1556 drivers/clk/sprd/sc9860-clk.c BIT(9), 0, 0); BIT 1558 drivers/clk/sprd/sc9860-clk.c BIT(10), 0, 0); BIT 1560 drivers/clk/sprd/sc9860-clk.c BIT(11), 0, 0); BIT 1562 drivers/clk/sprd/sc9860-clk.c BIT(12), 0, 0); BIT 1564 drivers/clk/sprd/sc9860-clk.c BIT(13), 0, 0); BIT 1566 drivers/clk/sprd/sc9860-clk.c BIT(14), 0, 0); BIT 1568 drivers/clk/sprd/sc9860-clk.c BIT(15), 0, 0); BIT 1570 drivers/clk/sprd/sc9860-clk.c BIT(16), 0, 0); BIT 1572 drivers/clk/sprd/sc9860-clk.c BIT(17), 0, 0); BIT 1574 drivers/clk/sprd/sc9860-clk.c BIT(18), 0, 0); BIT 1576 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(0), 0, 0); BIT 1578 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(1), 0, 0); BIT 1580 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), 0, 0); BIT 1582 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(3), 0, 0); BIT 1584 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(4), 0, 0); BIT 1586 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(5), 0, 0); BIT 1588 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(6), 0, 0); BIT 1590 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(7), 0, 0); BIT 1592 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(8), 0, 0); BIT 1594 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(9), 0, 0); BIT 1744 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(0), 0, 0); BIT 1746 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(1), 0, 0); BIT 1748 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), 0, 0); BIT 1750 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(3), 0, 0); BIT 1752 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(4), 0, 0); BIT 1754 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(5), 0, 0); BIT 1756 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(6), 0, 0); BIT 1758 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(7), 0, 0); BIT 1760 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(8), 0, 0); BIT 1762 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(9), 0, 0); BIT 1764 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(10), 0, 0); BIT 1766 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(13), 0, 0); BIT 1768 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(14), 0, 0); BIT 1770 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(15), 0, 0); BIT 1772 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(16), 0, 0); BIT 1774 drivers/clk/sprd/sc9860-clk.c BIT(0), 0, 0); BIT 1776 drivers/clk/sprd/sc9860-clk.c BIT(1), 0, 0); BIT 1778 drivers/clk/sprd/sc9860-clk.c BIT(2), 0, 0); BIT 1780 drivers/clk/sprd/sc9860-clk.c BIT(3), 0, 0); BIT 1782 drivers/clk/sprd/sc9860-clk.c BIT(4), 0, 0); BIT 1784 drivers/clk/sprd/sc9860-clk.c BIT(5), 0, 0); BIT 1786 drivers/clk/sprd/sc9860-clk.c BIT(6), 0, 0); BIT 1788 drivers/clk/sprd/sc9860-clk.c BIT(7), 0, 0); BIT 1790 drivers/clk/sprd/sc9860-clk.c BIT(8), 0, 0); BIT 1792 drivers/clk/sprd/sc9860-clk.c BIT(9), 0, 0); BIT 1794 drivers/clk/sprd/sc9860-clk.c BIT(10), 0, 0); BIT 1796 drivers/clk/sprd/sc9860-clk.c BIT(11), 0, 0); BIT 1798 drivers/clk/sprd/sc9860-clk.c BIT(12), 0, 0); BIT 1800 drivers/clk/sprd/sc9860-clk.c BIT(13), 0, 0); BIT 1802 drivers/clk/sprd/sc9860-clk.c BIT(14), 0, 0); BIT 1804 drivers/clk/sprd/sc9860-clk.c BIT(15), 0, 0); BIT 1885 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); BIT 1887 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); BIT 1889 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); BIT 1891 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); BIT 1893 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); BIT 1895 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); BIT 1897 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); BIT 1899 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); BIT 1901 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); BIT 1903 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); BIT 1905 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); BIT 1907 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); BIT 1909 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); BIT 1911 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); BIT 1913 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); BIT 1915 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); BIT 1917 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); BIT 1919 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); BIT 1921 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); BIT 1923 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); BIT 1925 drivers/clk/sprd/sc9860-clk.c 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); BIT 164 drivers/clk/st/clk-flexgen.c reg &= ~BIT(config->bit_idx); BIT 224 drivers/clk/st/clk-flexgen.c fgxbar->mux.mask = BIT(6) - 1; BIT 29 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 63 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 67 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x00c, BIT(31)), BIT 80 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 82 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14), BIT 97 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 112 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 125 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 151 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 169 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(14), BIT 182 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 184 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14), BIT 200 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 212 drivers/clk/sunxi-ng/ccu-sun4i-a10.c static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0); BIT 291 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x05c, BIT(31), 0); BIT 294 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(0), 0); BIT 296 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(1), 0); BIT 298 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(2), 0); BIT 300 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(3), 0); BIT 302 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(4), 0); BIT 304 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(5), 0); BIT 306 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(6), 0); BIT 308 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(7), 0); BIT 310 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(8), 0); BIT 312 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(9), 0); BIT 314 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(10), 0); BIT 316 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(11), 0); BIT 318 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(12), 0); BIT 320 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(13), 0); BIT 322 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(14), CLK_IS_CRITICAL); BIT 325 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(16), 0); BIT 327 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(17), 0); BIT 329 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(18), 0); BIT 331 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(20), 0); BIT 333 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(21), 0); BIT 335 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(22), 0); BIT 337 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(23), 0); BIT 339 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(24), 0); BIT 342 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(25), 0); BIT 345 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(26), 0); BIT 348 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x060, BIT(28), 0); BIT 351 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(0), 0); BIT 353 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(1), 0); BIT 355 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(2), 0); BIT 357 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(3), 0); BIT 359 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(4), 0); BIT 361 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(5), 0); BIT 363 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(8), 0); BIT 365 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(9), 0); BIT 368 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(10), 0); BIT 370 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(11), 0); BIT 372 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(12), 0); BIT 374 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(13), 0); BIT 376 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(14), 0); BIT 378 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(15), 0); BIT 381 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(17), 0); BIT 383 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(18), 0); BIT 385 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x064, BIT(20), 0); BIT 388 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x068, BIT(0), 0); BIT 390 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x068, BIT(1), 0); BIT 392 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x068, BIT(2), 0); BIT 394 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x068, BIT(3), 0); BIT 397 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x068, BIT(4), 0); BIT 399 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x068, BIT(5), 0); BIT 401 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x068, BIT(6), 0); BIT 403 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x068, BIT(7), 0); BIT 406 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x068, BIT(8), 0); BIT 408 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x068, BIT(10), 0); BIT 411 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(0), 0); BIT 413 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(1), 0); BIT 415 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(2), 0); BIT 418 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(3), 0); BIT 420 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(4), 0); BIT 422 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(5), 0); BIT 424 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(6), 0); BIT 426 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(7), 0); BIT 429 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(15), 0); BIT 431 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(16), 0); BIT 433 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(17), 0); BIT 435 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(18), 0); BIT 437 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(19), 0); BIT 439 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(20), 0); BIT 441 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(21), 0); BIT 443 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(22), 0); BIT 445 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x06c, BIT(23), 0); BIT 453 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 461 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 468 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 481 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 494 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 507 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 520 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 527 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 534 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 541 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 548 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 556 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 566 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 573 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 581 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 588 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 594 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 597 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 601 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 606 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 626 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT); BIT 630 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x0cc, BIT(6), 0); BIT 632 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x0cc, BIT(7), 0); BIT 634 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x0cc, BIT(8), 0); BIT 642 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(31), /* gate */ BIT 647 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 651 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 654 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(0), 0); BIT 656 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(1), 0); BIT 658 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(2), 0); BIT 660 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(3), 0); BIT 662 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(4), 0); BIT 664 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(5), 0); BIT 666 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(6), 0); BIT 670 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(15), CLK_IS_CRITICAL); BIT 672 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(24), 0); BIT 674 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(25), 0); BIT 676 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(26), 0); BIT 678 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(27), 0); BIT 680 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(28), 0); BIT 682 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x100, BIT(29), 0); BIT 687 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x104, 0, 4, 24, 2, BIT(31), 0); BIT 690 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x108, 0, 4, 24, 2, BIT(31), 0); BIT 693 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x10c, 0, 4, 24, 2, BIT(31), 0); BIT 696 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x110, 0, 4, 24, 2, BIT(31), 0); BIT 700 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x114, 0, 4, 24, 2, BIT(31), 0); BIT 705 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 707 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 714 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x120, 0, 4, 24, 2, BIT(31), 0); BIT 719 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x128, 24, 1, BIT(31), 0); BIT 728 drivers/clk/sunxi-ng/ccu-sun4i-a10.c BIT(15), /* gate */ BIT 732 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x128, 0, 4, BIT(31), 0); BIT 736 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x12c, 0, 4, 24, 2, BIT(31), BIT 741 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x12c, 11, 1, BIT(15), BIT 746 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x130, 0, 4, 24, 2, BIT(31), BIT 751 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x130, 11, 1, BIT(15), BIT 759 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x134, 0, 5, 24, 3, BIT(31), 0); BIT 763 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x138, 0, 5, 24, 3, BIT(31), 0); BIT 765 drivers/clk/sunxi-ng/ccu-sun4i-a10.c static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0); BIT 768 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x140, BIT(31), CLK_SET_RATE_PARENT); BIT 770 drivers/clk/sunxi-ng/ccu-sun4i-a10.c static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0); BIT 774 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x148, 0, 4, 24, 1, BIT(31), 0); BIT 777 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x150, 0, 4, 24, 2, BIT(31), BIT 784 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x154, 0, 4, 24, 2, BIT(31), BIT 793 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x154, 0, 4, 24, 3, BIT(31), BIT 799 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x15c, 0, 4, 16, 2, 24, 2, BIT(31), BIT 804 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x15c, 0, 4, 16, 2, 24, 2, BIT(31), BIT 807 drivers/clk/sunxi-ng/ccu-sun4i-a10.c static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0); BIT 813 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 0x17c, 0, 4, 24, 2, BIT(31), BIT 822 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 841 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .enable = BIT(31), BIT 1384 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 1385 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_USB_PHY1] = { 0x0cc, BIT(1) }, BIT 1386 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_USB_PHY2] = { 0x0cc, BIT(2) }, BIT 1387 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_GPS] = { 0x0d0, BIT(0) }, BIT 1388 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_DE_BE0] = { 0x104, BIT(30) }, BIT 1389 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_DE_BE1] = { 0x108, BIT(30) }, BIT 1390 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_DE_FE0] = { 0x10c, BIT(30) }, BIT 1391 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_DE_FE1] = { 0x110, BIT(30) }, BIT 1392 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_DE_MP] = { 0x114, BIT(30) }, BIT 1393 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_TVE0] = { 0x118, BIT(29) }, BIT 1394 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_TCON0] = { 0x118, BIT(30) }, BIT 1395 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_TVE1] = { 0x11c, BIT(29) }, BIT 1396 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_TCON1] = { 0x11c, BIT(30) }, BIT 1397 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_CSI0] = { 0x134, BIT(30) }, BIT 1398 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_CSI1] = { 0x138, BIT(30) }, BIT 1399 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_VE] = { 0x13c, BIT(0) }, BIT 1400 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_ACE] = { 0x148, BIT(16) }, BIT 1401 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_LVDS] = { 0x14c, BIT(0) }, BIT 1402 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_GPU] = { 0x154, BIT(30) }, BIT 1403 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_HDMI_H] = { 0x170, BIT(0) }, BIT 1404 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_HDMI_SYS] = { 0x170, BIT(1) }, BIT 1405 drivers/clk/sunxi-ng/ccu-sun4i-a10.c [RST_HDMI_AUDIO_DMA] = { 0x170, BIT(2) }, BIT 27 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .enable = BIT(31), BIT 28 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .lock = BIT(28), BIT 65 drivers/clk/sunxi-ng/ccu-sun50i-a64.c pll_audio_sdm_table, BIT(24), BIT 66 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x284, BIT(31), BIT 67 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 68 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(28), /* lock */ BIT 77 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(24), /* frac enable */ BIT 78 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(25), /* frac select */ BIT 81 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 82 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(28), /* lock */ BIT 89 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(24), /* frac enable */ BIT 90 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(25), /* frac select */ BIT 93 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 94 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(28), /* lock */ BIT 102 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 103 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(28), /* lock */ BIT 107 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .enable = BIT(31), BIT 108 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .lock = BIT(28), BIT 121 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .enable = BIT(31), BIT 122 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .lock = BIT(28), BIT 140 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(24), /* frac enable */ BIT 141 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(25), /* frac select */ BIT 144 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 145 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(28), /* lock */ BIT 152 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(24), /* frac enable */ BIT 153 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(25), /* frac select */ BIT 156 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 157 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(28), /* lock */ BIT 174 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .enable = BIT(31) | BIT(23) | BIT(22), BIT 175 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .lock = BIT(28), BIT 190 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(24), /* frac enable */ BIT 191 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(25), /* frac select */ BIT 194 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 195 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(28), /* lock */ BIT 202 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(24), /* frac enable */ BIT 203 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(25), /* frac select */ BIT 206 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 207 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(28), /* lock */ BIT 214 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 215 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(28), /* lock */ BIT 293 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(1), 0); BIT 295 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(5), 0); BIT 297 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(6), 0); BIT 299 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(8), 0); BIT 301 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(9), 0); BIT 303 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(10), 0); BIT 305 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(13), 0); BIT 307 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(14), 0); BIT 309 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(17), 0); BIT 311 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(18), 0); BIT 313 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(19), 0); BIT 315 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(20), 0); BIT 317 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(21), 0); BIT 319 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(23), 0); BIT 321 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(24), 0); BIT 323 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(25), 0); BIT 325 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(28), 0); BIT 327 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x060, BIT(29), 0); BIT 330 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x064, BIT(0), 0); BIT 332 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x064, BIT(3), 0); BIT 334 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x064, BIT(4), 0); BIT 336 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x064, BIT(5), 0); BIT 338 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x064, BIT(8), 0); BIT 340 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x064, BIT(11), 0); BIT 342 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x064, BIT(12), 0); BIT 344 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x064, BIT(20), 0); BIT 346 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x064, BIT(21), 0); BIT 348 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x064, BIT(22), 0); BIT 351 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x068, BIT(0), 0); BIT 353 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x068, BIT(1), 0); BIT 355 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x068, BIT(5), 0); BIT 357 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x068, BIT(8), 0); BIT 359 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x068, BIT(12), 0); BIT 361 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x068, BIT(13), 0); BIT 363 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x068, BIT(14), 0); BIT 366 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x06c, BIT(0), 0); BIT 368 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x06c, BIT(1), 0); BIT 370 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x06c, BIT(2), 0); BIT 372 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x06c, BIT(5), 0); BIT 374 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x06c, BIT(16), 0); BIT 376 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x06c, BIT(17), 0); BIT 378 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x06c, BIT(18), 0); BIT 380 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x06c, BIT(19), 0); BIT 382 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x06c, BIT(20), 0); BIT 385 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x070, BIT(7), 0); BIT 395 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .enable = BIT(31), BIT 413 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 434 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 443 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 452 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 461 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 468 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 475 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 482 drivers/clk/sunxi-ng/ccu-sun50i-a64.c BIT(31), /* gate */ BIT 488 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 491 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 494 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 497 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 500 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x0cc, BIT(8), 0); BIT 502 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x0cc, BIT(9), 0); BIT 504 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x0cc, BIT(10), 0); BIT 506 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x0cc, BIT(11), 0); BIT 508 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x0cc, BIT(16), 0); BIT 510 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x0cc, BIT(17), 0); BIT 517 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x100, BIT(0), 0); BIT 519 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x100, BIT(1), 0); BIT 521 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x100, BIT(2), 0); BIT 523 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x100, BIT(3), 0); BIT 527 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x104, 0, 4, 24, 3, BIT(31), BIT 533 drivers/clk/sunxi-ng/ccu-sun50i-a64.c tcon0_table, 0x118, 24, 3, BIT(31), BIT 539 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .enable = BIT(31), BIT 553 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x124, 0, 4, 24, 3, BIT(31), 0); BIT 556 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x130, BIT(31), 0); BIT 560 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x134, 16, 4, 24, 3, BIT(31), 0); BIT 564 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x134, 0, 5, 8, 3, BIT(15), 0); BIT 567 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 570 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x140, BIT(31), CLK_SET_RATE_PARENT); BIT 573 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x140, BIT(30), CLK_SET_RATE_PARENT); BIT 576 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x144, BIT(31), 0); BIT 580 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 583 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x154, BIT(31), 0); BIT 588 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); BIT 594 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT); BIT 597 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 855 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 856 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_USB_PHY1] = { 0x0cc, BIT(1) }, BIT 857 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_USB_HSIC] = { 0x0cc, BIT(2) }, BIT 859 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_DRAM] = { 0x0f4, BIT(31) }, BIT 860 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_MBUS] = { 0x0fc, BIT(31) }, BIT 862 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, BIT 863 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_CE] = { 0x2c0, BIT(5) }, BIT 864 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_DMA] = { 0x2c0, BIT(6) }, BIT 865 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, BIT 866 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, BIT 867 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, BIT 868 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_NAND] = { 0x2c0, BIT(13) }, BIT 869 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, BIT 870 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, BIT 871 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_TS] = { 0x2c0, BIT(18) }, BIT 872 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, BIT 873 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, BIT 874 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, BIT 875 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_OTG] = { 0x2c0, BIT(23) }, BIT 876 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, BIT 877 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, BIT 878 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, BIT 879 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, BIT 881 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_VE] = { 0x2c4, BIT(0) }, BIT 882 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, BIT 883 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, BIT 884 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, BIT 885 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_CSI] = { 0x2c4, BIT(8) }, BIT 886 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, BIT 887 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, BIT 888 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_DE] = { 0x2c4, BIT(12) }, BIT 889 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_GPU] = { 0x2c4, BIT(20) }, BIT 890 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, BIT 891 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, BIT 892 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_DBG] = { 0x2c4, BIT(31) }, BIT 894 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, BIT 896 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, BIT 897 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, BIT 898 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_THS] = { 0x2d0, BIT(8) }, BIT 899 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, BIT 900 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, BIT 901 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, BIT 903 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, BIT 904 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, BIT 905 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, BIT 906 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_SCR] = { 0x2d8, BIT(5) }, BIT 907 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_UART0] = { 0x2d8, BIT(16) }, BIT 908 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_UART1] = { 0x2d8, BIT(17) }, BIT 909 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_UART2] = { 0x2d8, BIT(18) }, BIT 910 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_UART3] = { 0x2d8, BIT(19) }, BIT 911 drivers/clk/sunxi-ng/ccu-sun50i-a64.c [RST_BUS_UART4] = { 0x2d8, BIT(20) }, BIT 927 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .enable = BIT(31), BIT 928 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .lock = BIT(28), BIT 95 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c 0x11c, BIT(0), 0); BIT 97 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c 0x12c, BIT(0), 0); BIT 99 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c 0x13c, BIT(0), 0); BIT 101 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c 0x18c, BIT(0), 0); BIT 103 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c 0x19c, BIT(0), 0); BIT 105 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c 0x1cc, BIT(0), 0); BIT 107 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c 0x1ec, BIT(0), 0); BIT 116 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c BIT(31), /* gate */ BIT 131 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c BIT(31), /* gate */ BIT 169 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c [RST_R_APB1_TIMER] = { 0x11c, BIT(16) }, BIT 170 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c [RST_R_APB1_TWD] = { 0x12c, BIT(16) }, BIT 171 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c [RST_R_APB1_PWM] = { 0x13c, BIT(16) }, BIT 172 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c [RST_R_APB2_UART] = { 0x18c, BIT(16) }, BIT 173 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c [RST_R_APB2_I2C] = { 0x19c, BIT(16) }, BIT 174 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c [RST_R_APB1_IR] = { 0x1cc, BIT(16) }, BIT 175 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c [RST_R_APB1_W1] = { 0x1ec, BIT(16) }, BIT 37 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 38 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 51 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 52 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 66 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 67 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 83 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 84 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 100 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 101 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 119 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 120 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 137 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 138 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 155 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 156 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 170 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 171 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 185 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 186 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 207 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 208 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .lock = BIT(28), BIT 262 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 269 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 273 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x60c, BIT(0), 0); BIT 282 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 286 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x62c, BIT(0), 0); BIT 292 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 296 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x67c, BIT(0), 0); BIT 304 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31),/* gate */ BIT 308 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x68c, BIT(0), 0); BIT 314 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 318 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x69c, BIT(0), 0); BIT 324 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31),/* gate */ BIT 328 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x6bc, BIT(0), 0); BIT 334 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 338 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x6cc, BIT(0), 0); BIT 341 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x70c, BIT(0), 0); BIT 344 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x71c, BIT(0), 0); BIT 347 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x72c, BIT(0), 0); BIT 350 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x73c, BIT(0), 0); BIT 352 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0); BIT 355 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x78c, BIT(0), 0); BIT 358 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x79c, BIT(0), 0); BIT 360 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0); BIT 362 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0); BIT 378 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x804, BIT(0), 0); BIT 380 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x804, BIT(1), 0); BIT 382 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x804, BIT(2), 0); BIT 384 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x804, BIT(3), 0); BIT 386 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x804, BIT(5), 0); BIT 388 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x804, BIT(8), 0); BIT 390 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x804, BIT(11), 0); BIT 393 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0x80c, BIT(0), CLK_IS_CRITICAL); BIT 402 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31),/* gate */ BIT 409 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31),/* gate */ BIT 412 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0); BIT 420 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 428 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 436 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 440 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); BIT 441 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0); BIT 442 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0); BIT 444 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0); BIT 445 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0); BIT 446 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0); BIT 447 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0); BIT 449 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0); BIT 450 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0); BIT 451 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0); BIT 452 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0); BIT 454 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", 0x93c, BIT(0), 0); BIT 455 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2", 0x93c, BIT(1), 0); BIT 461 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31),/* gate */ BIT 468 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31),/* gate */ BIT 471 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0); BIT 472 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0); BIT 474 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0); BIT 481 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31),/* gate */ BIT 484 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0); BIT 491 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31),/* gate */ BIT 494 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0); BIT 496 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0); BIT 500 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 513 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 526 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 539 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 551 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa1c, BIT(0), 0); BIT 552 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa1c, BIT(1), 0); BIT 553 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa1c, BIT(2), 0); BIT 554 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa1c, BIT(3), 0); BIT 557 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 569 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0); BIT 572 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 584 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0); BIT 587 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 599 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0); BIT 608 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0); BIT 609 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0); BIT 611 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0); BIT 613 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0); BIT 614 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc12M", 0xa7c, BIT(29), 0); BIT 615 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0); BIT 616 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0xa7c, BIT(26), 0); BIT 618 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0); BIT 619 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0); BIT 620 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0); BIT 621 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_xhci_clk, "bus-xhci", "ahb3", 0xa8c, BIT(5), 0); BIT 622 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0); BIT 623 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0); BIT 629 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0xab0, BIT(31), 0); BIT 631 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0xab0, BIT(30), 0); BIT 636 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 641 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 645 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0xabc, BIT(0), 0); BIT 652 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 655 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0); BIT 664 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .enable = BIT(31), BIT 684 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0); BIT 687 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0xb5c, BIT(0), 0); BIT 695 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 699 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0xb7c, BIT(0), 0); BIT 710 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 714 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 0xb9c, BIT(0), 0); BIT 716 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(csi_cci_clk, "csi-cci", "osc24M", 0xc00, BIT(0), 0); BIT 725 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 734 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 737 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0); BIT 743 drivers/clk/sunxi-ng/ccu-sun50i-h6.c BIT(31), /* gate */ BIT 746 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0); BIT 1071 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_MBUS] = { 0x540, BIT(30) }, BIT 1073 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_DE] = { 0x60c, BIT(16) }, BIT 1074 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) }, BIT 1075 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_GPU] = { 0x67c, BIT(16) }, BIT 1076 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_CE] = { 0x68c, BIT(16) }, BIT 1077 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_VE] = { 0x69c, BIT(16) }, BIT 1078 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_EMCE] = { 0x6bc, BIT(16) }, BIT 1079 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_VP9] = { 0x6cc, BIT(16) }, BIT 1080 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_DMA] = { 0x70c, BIT(16) }, BIT 1081 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_MSGBOX] = { 0x71c, BIT(16) }, BIT 1082 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) }, BIT 1083 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_HSTIMER] = { 0x73c, BIT(16) }, BIT 1084 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_DBG] = { 0x78c, BIT(16) }, BIT 1085 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_PSI] = { 0x79c, BIT(16) }, BIT 1086 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_PWM] = { 0x7ac, BIT(16) }, BIT 1087 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_IOMMU] = { 0x7bc, BIT(16) }, BIT 1088 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_DRAM] = { 0x80c, BIT(16) }, BIT 1089 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_NAND] = { 0x82c, BIT(16) }, BIT 1090 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_MMC0] = { 0x84c, BIT(16) }, BIT 1091 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_MMC1] = { 0x84c, BIT(17) }, BIT 1092 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_MMC2] = { 0x84c, BIT(18) }, BIT 1093 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_UART0] = { 0x90c, BIT(16) }, BIT 1094 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_UART1] = { 0x90c, BIT(17) }, BIT 1095 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_UART2] = { 0x90c, BIT(18) }, BIT 1096 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_UART3] = { 0x90c, BIT(19) }, BIT 1097 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_I2C0] = { 0x91c, BIT(16) }, BIT 1098 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_I2C1] = { 0x91c, BIT(17) }, BIT 1099 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_I2C2] = { 0x91c, BIT(18) }, BIT 1100 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_I2C3] = { 0x91c, BIT(19) }, BIT 1101 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_SCR0] = { 0x93c, BIT(16) }, BIT 1102 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_SCR1] = { 0x93c, BIT(17) }, BIT 1103 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_SPI0] = { 0x96c, BIT(16) }, BIT 1104 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_SPI1] = { 0x96c, BIT(17) }, BIT 1105 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_EMAC] = { 0x97c, BIT(16) }, BIT 1106 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_TS] = { 0x9bc, BIT(16) }, BIT 1107 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_IR_TX] = { 0x9cc, BIT(16) }, BIT 1108 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_THS] = { 0x9fc, BIT(16) }, BIT 1109 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_I2S0] = { 0xa1c, BIT(16) }, BIT 1110 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_I2S1] = { 0xa1c, BIT(17) }, BIT 1111 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_I2S2] = { 0xa1c, BIT(18) }, BIT 1112 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_I2S3] = { 0xa1c, BIT(19) }, BIT 1113 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_SPDIF] = { 0xa2c, BIT(16) }, BIT 1114 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_DMIC] = { 0xa4c, BIT(16) }, BIT 1115 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) }, BIT 1117 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_USB_PHY0] = { 0xa70, BIT(30) }, BIT 1118 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_USB_PHY1] = { 0xa74, BIT(30) }, BIT 1119 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_USB_PHY3] = { 0xa7c, BIT(30) }, BIT 1120 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_USB_HSIC] = { 0xa7c, BIT(28) }, BIT 1122 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_OHCI0] = { 0xa8c, BIT(16) }, BIT 1123 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_OHCI3] = { 0xa8c, BIT(19) }, BIT 1124 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_EHCI0] = { 0xa8c, BIT(20) }, BIT 1125 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_XHCI] = { 0xa8c, BIT(21) }, BIT 1126 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_EHCI3] = { 0xa8c, BIT(23) }, BIT 1127 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_OTG] = { 0xa8c, BIT(24) }, BIT 1128 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_PCIE] = { 0xabc, BIT(16) }, BIT 1130 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_PCIE_POWERUP] = { 0xabc, BIT(17) }, BIT 1132 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_HDMI] = { 0xb1c, BIT(16) }, BIT 1133 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) }, BIT 1134 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) }, BIT 1135 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) }, BIT 1136 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) }, BIT 1137 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_CSI] = { 0xc2c, BIT(16) }, BIT 1138 drivers/clk/sunxi-ng/ccu-sun50i-h6.c [RST_BUS_HDCP] = { 0xc4c, BIT(16) }, BIT 1190 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val |= BIT(29); BIT 1201 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val &= ~BIT(0); BIT 1222 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val &= ~(GENMASK(21, 16) | BIT(0)); BIT 1231 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val |= BIT(24); BIT 27 drivers/clk/sunxi-ng/ccu-sun5i.c .enable = BIT(31), BIT 61 drivers/clk/sunxi-ng/ccu-sun5i.c .enable = BIT(31), BIT 70 drivers/clk/sunxi-ng/ccu-sun5i.c 0x00c, BIT(31)), BIT 82 drivers/clk/sunxi-ng/ccu-sun5i.c .enable = BIT(31), BIT 84 drivers/clk/sunxi-ng/ccu-sun5i.c .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14), BIT 99 drivers/clk/sunxi-ng/ccu-sun5i.c .enable = BIT(31), BIT 114 drivers/clk/sunxi-ng/ccu-sun5i.c .enable = BIT(31), BIT 141 drivers/clk/sunxi-ng/ccu-sun5i.c .enable = BIT(31), BIT 156 drivers/clk/sunxi-ng/ccu-sun5i.c .enable = BIT(31), BIT 158 drivers/clk/sunxi-ng/ccu-sun5i.c .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14), BIT 172 drivers/clk/sunxi-ng/ccu-sun5i.c static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0); BIT 239 drivers/clk/sunxi-ng/ccu-sun5i.c 0x05c, BIT(0), 0); BIT 242 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(0), 0); BIT 244 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(1), 0); BIT 246 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(2), 0); BIT 248 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(5), 0); BIT 250 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(6), 0); BIT 252 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(7), 0); BIT 254 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(8), 0); BIT 256 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(9), 0); BIT 258 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(10), 0); BIT 260 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(13), 0); BIT 262 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(14), CLK_IS_CRITICAL); BIT 264 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(17), 0); BIT 266 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(18), 0); BIT 268 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(20), 0); BIT 270 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(21), 0); BIT 272 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(22), 0); BIT 274 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(26), 0); BIT 276 drivers/clk/sunxi-ng/ccu-sun5i.c 0x060, BIT(28), 0); BIT 279 drivers/clk/sunxi-ng/ccu-sun5i.c 0x064, BIT(0), 0); BIT 281 drivers/clk/sunxi-ng/ccu-sun5i.c 0x064, BIT(2), 0); BIT 283 drivers/clk/sunxi-ng/ccu-sun5i.c 0x064, BIT(4), 0); BIT 285 drivers/clk/sunxi-ng/ccu-sun5i.c 0x064, BIT(8), 0); BIT 287 drivers/clk/sunxi-ng/ccu-sun5i.c 0x064, BIT(11), 0); BIT 289 drivers/clk/sunxi-ng/ccu-sun5i.c 0x064, BIT(12), 0); BIT 291 drivers/clk/sunxi-ng/ccu-sun5i.c 0x064, BIT(14), 0); BIT 293 drivers/clk/sunxi-ng/ccu-sun5i.c 0x064, BIT(19), 0); BIT 295 drivers/clk/sunxi-ng/ccu-sun5i.c 0x064, BIT(20), 0); BIT 298 drivers/clk/sunxi-ng/ccu-sun5i.c 0x068, BIT(0), 0); BIT 300 drivers/clk/sunxi-ng/ccu-sun5i.c 0x068, BIT(1), 0); BIT 302 drivers/clk/sunxi-ng/ccu-sun5i.c 0x068, BIT(3), 0); BIT 304 drivers/clk/sunxi-ng/ccu-sun5i.c 0x068, BIT(5), 0); BIT 306 drivers/clk/sunxi-ng/ccu-sun5i.c 0x068, BIT(6), 0); BIT 308 drivers/clk/sunxi-ng/ccu-sun5i.c 0x068, BIT(10), 0); BIT 311 drivers/clk/sunxi-ng/ccu-sun5i.c 0x06c, BIT(0), 0); BIT 313 drivers/clk/sunxi-ng/ccu-sun5i.c 0x06c, BIT(1), 0); BIT 315 drivers/clk/sunxi-ng/ccu-sun5i.c 0x06c, BIT(2), 0); BIT 317 drivers/clk/sunxi-ng/ccu-sun5i.c 0x06c, BIT(16), 0); BIT 319 drivers/clk/sunxi-ng/ccu-sun5i.c 0x06c, BIT(17), 0); BIT 321 drivers/clk/sunxi-ng/ccu-sun5i.c 0x06c, BIT(18), 0); BIT 323 drivers/clk/sunxi-ng/ccu-sun5i.c 0x06c, BIT(19), 0); BIT 331 drivers/clk/sunxi-ng/ccu-sun5i.c BIT(31), /* gate */ BIT 338 drivers/clk/sunxi-ng/ccu-sun5i.c BIT(31), /* gate */ BIT 345 drivers/clk/sunxi-ng/ccu-sun5i.c BIT(31), /* gate */ BIT 352 drivers/clk/sunxi-ng/ccu-sun5i.c BIT(31), /* gate */ BIT 359 drivers/clk/sunxi-ng/ccu-sun5i.c BIT(31), /* gate */ BIT 366 drivers/clk/sunxi-ng/ccu-sun5i.c BIT(31), /* gate */ BIT 373 drivers/clk/sunxi-ng/ccu-sun5i.c BIT(31), /* gate */ BIT 380 drivers/clk/sunxi-ng/ccu-sun5i.c BIT(31), /* gate */ BIT 387 drivers/clk/sunxi-ng/ccu-sun5i.c BIT(31), /* gate */ BIT 394 drivers/clk/sunxi-ng/ccu-sun5i.c BIT(31), /* gate */ BIT 400 drivers/clk/sunxi-ng/ccu-sun5i.c 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 405 drivers/clk/sunxi-ng/ccu-sun5i.c 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 410 drivers/clk/sunxi-ng/ccu-sun5i.c .enable = BIT(31), BIT 425 drivers/clk/sunxi-ng/ccu-sun5i.c 0x0cc, BIT(6), 0); BIT 427 drivers/clk/sunxi-ng/ccu-sun5i.c 0x0cc, BIT(8), 0); BIT 429 drivers/clk/sunxi-ng/ccu-sun5i.c 0x0cc, BIT(9), 0); BIT 434 drivers/clk/sunxi-ng/ccu-sun5i.c 0x0d0, 0, 3, 24, 2, BIT(31), 0); BIT 437 drivers/clk/sunxi-ng/ccu-sun5i.c 0x100, BIT(0), 0); BIT 439 drivers/clk/sunxi-ng/ccu-sun5i.c 0x100, BIT(1), 0); BIT 441 drivers/clk/sunxi-ng/ccu-sun5i.c 0x100, BIT(3), 0); BIT 443 drivers/clk/sunxi-ng/ccu-sun5i.c 0x100, BIT(5), 0); BIT 445 drivers/clk/sunxi-ng/ccu-sun5i.c 0x100, BIT(25), 0); BIT 447 drivers/clk/sunxi-ng/ccu-sun5i.c 0x100, BIT(26), 0); BIT 449 drivers/clk/sunxi-ng/ccu-sun5i.c 0x100, BIT(29), 0); BIT 451 drivers/clk/sunxi-ng/ccu-sun5i.c 0x100, BIT(31), 0); BIT 456 drivers/clk/sunxi-ng/ccu-sun5i.c 0x104, 0, 4, 24, 2, BIT(31), 0); BIT 459 drivers/clk/sunxi-ng/ccu-sun5i.c 0x10c, 0, 4, 24, 2, BIT(31), 0); BIT 464 drivers/clk/sunxi-ng/ccu-sun5i.c 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 468 drivers/clk/sunxi-ng/ccu-sun5i.c 0x12c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 471 drivers/clk/sunxi-ng/ccu-sun5i.c 0x12c, 11, 1, BIT(15), CLK_SET_RATE_PARENT); BIT 478 drivers/clk/sunxi-ng/ccu-sun5i.c 0x134, 0, 5, 24, 3, BIT(31), 0); BIT 481 drivers/clk/sunxi-ng/ccu-sun5i.c 0x13c, BIT(31), CLK_SET_RATE_PARENT); BIT 484 drivers/clk/sunxi-ng/ccu-sun5i.c 0x140, BIT(31), CLK_SET_RATE_PARENT); BIT 487 drivers/clk/sunxi-ng/ccu-sun5i.c 0x144, BIT(31), 0); BIT 493 drivers/clk/sunxi-ng/ccu-sun5i.c 0x150, 0, 4, 24, 2, BIT(31), BIT 500 drivers/clk/sunxi-ng/ccu-sun5i.c 0x154, 0, 4, 24, 3, BIT(31), 0); BIT 504 drivers/clk/sunxi-ng/ccu-sun5i.c 0x15c, 0, 4, 16, 2, 24, 2, BIT(31), CLK_IS_CRITICAL); BIT 507 drivers/clk/sunxi-ng/ccu-sun5i.c 0x160, BIT(31), 0); BIT 735 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 736 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_USB_PHY1] = { 0x0cc, BIT(1) }, BIT 738 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_GPS] = { 0x0d0, BIT(30) }, BIT 740 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_DE_BE] = { 0x104, BIT(30) }, BIT 742 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_DE_FE] = { 0x10c, BIT(30) }, BIT 744 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_TVE] = { 0x118, BIT(29) }, BIT 745 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_LCD] = { 0x118, BIT(30) }, BIT 747 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_CSI] = { 0x134, BIT(30) }, BIT 749 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_VE] = { 0x13c, BIT(0) }, BIT 751 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_GPU] = { 0x154, BIT(30) }, BIT 753 drivers/clk/sunxi-ng/ccu-sun5i.c [RST_IEP] = { 0x160, BIT(30) }, BIT 36 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 37 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 63 drivers/clk/sunxi-ng/ccu-sun6i-a31.c pll_audio_sdm_table, BIT(24), BIT 64 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x284, BIT(31), BIT 65 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 66 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 73 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(24), /* frac enable */ BIT 74 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(25), /* frac select */ BIT 77 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 78 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 85 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(24), /* frac enable */ BIT 86 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(25), /* frac select */ BIT 89 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 90 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 98 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 99 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 106 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 107 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 115 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(24), /* frac enable */ BIT 116 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(25), /* frac select */ BIT 119 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 120 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 127 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(24), /* frac enable */ BIT 128 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(25), /* frac select */ BIT 131 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 132 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 151 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31) | BIT(23) | BIT(22), /* gate */ BIT 152 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 159 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(24), /* frac enable */ BIT 160 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(25), /* frac select */ BIT 163 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 164 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 171 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(24), /* frac enable */ BIT 172 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(25), /* frac select */ BIT 175 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 176 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(28), /* lock */ BIT 248 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(1), 0); BIT 250 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(5), 0); BIT 252 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(6), 0); BIT 254 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(8), 0); BIT 256 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(9), 0); BIT 258 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(10), 0); BIT 260 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(11), 0); BIT 262 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(12), 0); BIT 264 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(13), 0); BIT 266 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(14), 0); BIT 268 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(17), 0); BIT 270 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(18), 0); BIT 272 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(19), 0); BIT 274 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(20), 0); BIT 276 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(21), 0); BIT 278 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(22), 0); BIT 280 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(23), 0); BIT 282 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(24), 0); BIT 284 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(26), 0); BIT 286 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(27), 0); BIT 288 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(29), 0); BIT 290 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(30), 0); BIT 292 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x060, BIT(31), 0); BIT 295 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(0), 0); BIT 297 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(4), 0); BIT 299 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(5), 0); BIT 301 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(8), 0); BIT 303 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(11), 0); BIT 305 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(12), 0); BIT 307 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(13), 0); BIT 309 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(14), 0); BIT 311 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(15), 0); BIT 313 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(18), 0); BIT 315 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(20), 0); BIT 317 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(23), 0); BIT 319 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(24), 0); BIT 321 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(25), 0); BIT 323 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x064, BIT(26), 0); BIT 326 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x068, BIT(0), 0); BIT 328 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x068, BIT(1), 0); BIT 330 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x068, BIT(4), 0); BIT 332 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x068, BIT(5), 0); BIT 334 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x068, BIT(12), 0); BIT 336 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x068, BIT(13), 0); BIT 339 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x06c, BIT(0), 0); BIT 341 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x06c, BIT(1), 0); BIT 343 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x06c, BIT(2), 0); BIT 345 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x06c, BIT(3), 0); BIT 347 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x06c, BIT(16), 0); BIT 349 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x06c, BIT(17), 0); BIT 351 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x06c, BIT(18), 0); BIT 353 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x06c, BIT(19), 0); BIT 355 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x06c, BIT(20), 0); BIT 357 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x06c, BIT(21), 0); BIT 365 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 373 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 381 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 394 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 407 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 420 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 432 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 439 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 446 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 453 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 459 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 466 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 472 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 474 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 477 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 480 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x0cc, BIT(8), 0); BIT 482 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x0cc, BIT(9), 0); BIT 484 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x0cc, BIT(10), 0); BIT 486 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x0cc, BIT(16), 0); BIT 488 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x0cc, BIT(17), 0); BIT 490 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x0cc, BIT(18), 0); BIT 499 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 508 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(0), 0); BIT 510 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(1), 0); BIT 512 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(3), 0); BIT 514 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(16), 0); BIT 516 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(17), 0); BIT 518 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(18), 0); BIT 520 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(19), 0); BIT 522 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(24), 0); BIT 524 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(25), 0); BIT 526 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(26), 0); BIT 528 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(27), 0); BIT 530 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x100, BIT(28), 0); BIT 536 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x104, 0, 4, 24, 3, BIT(31), 0); BIT 538 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x108, 0, 4, 24, 3, BIT(31), 0); BIT 540 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x10c, 0, 4, 24, 3, BIT(31), 0); BIT 542 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x110, 0, 4, 24, 3, BIT(31), 0); BIT 547 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x114, 0, 4, 24, 3, BIT(31), 0); BIT 553 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 555 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 561 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x12c, 0, 4, 24, 3, BIT(31), BIT 564 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x130, 0, 4, 24, 3, BIT(31), BIT 571 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x134, 16, 4, 24, 3, BIT(31), 0); BIT 577 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .enable = BIT(15), BIT 590 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .enable = BIT(15), BIT 603 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x13c, 16, 3, BIT(31), 0); BIT 606 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x140, BIT(31), CLK_SET_RATE_PARENT); BIT 608 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x144, BIT(31), 0); BIT 610 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x148, BIT(31), CLK_SET_RATE_PARENT); BIT 613 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x150, 0, 4, 24, 2, BIT(31), BIT 616 drivers/clk/sunxi-ng/ccu-sun6i-a31.c static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0); BIT 618 drivers/clk/sunxi-ng/ccu-sun6i-a31.c static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0); BIT 626 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 633 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 637 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x168, 16, 3, 24, 2, BIT(31), BIT 641 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(15), CLK_SET_RATE_PARENT); BIT 644 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(15), 0); BIT 647 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x180, 0, 3, 24, 2, BIT(31), 0); BIT 649 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x184, 0, 3, 24, 2, BIT(31), 0); BIT 651 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x188, 0, 3, 24, 2, BIT(31), 0); BIT 653 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 0x18c, 0, 3, 24, 2, BIT(31), 0); BIT 663 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .enable = BIT(31), BIT 682 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .enable = BIT(31), BIT 701 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .enable = BIT(31), BIT 722 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 729 drivers/clk/sunxi-ng/ccu-sun6i-a31.c BIT(31), /* gate */ BIT 743 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .enable = BIT(31), BIT 764 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .enable = BIT(31), BIT 785 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .enable = BIT(31), BIT 1149 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 1150 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_USB_PHY1] = { 0x0cc, BIT(1) }, BIT 1151 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_USB_PHY2] = { 0x0cc, BIT(2) }, BIT 1153 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) }, BIT 1154 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_SS] = { 0x2c0, BIT(5) }, BIT 1155 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_DMA] = { 0x2c0, BIT(6) }, BIT 1156 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_MMC0] = { 0x2c0, BIT(8) }, BIT 1157 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_MMC1] = { 0x2c0, BIT(9) }, BIT 1158 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_MMC2] = { 0x2c0, BIT(10) }, BIT 1159 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_MMC3] = { 0x2c0, BIT(11) }, BIT 1160 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_NAND1] = { 0x2c0, BIT(12) }, BIT 1161 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_NAND0] = { 0x2c0, BIT(13) }, BIT 1162 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_SDRAM] = { 0x2c0, BIT(14) }, BIT 1163 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_EMAC] = { 0x2c0, BIT(17) }, BIT 1164 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_TS] = { 0x2c0, BIT(18) }, BIT 1165 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) }, BIT 1166 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_SPI0] = { 0x2c0, BIT(20) }, BIT 1167 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_SPI1] = { 0x2c0, BIT(21) }, BIT 1168 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_SPI2] = { 0x2c0, BIT(22) }, BIT 1169 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_SPI3] = { 0x2c0, BIT(23) }, BIT 1170 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_OTG] = { 0x2c0, BIT(24) }, BIT 1171 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) }, BIT 1172 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) }, BIT 1173 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) }, BIT 1174 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) }, BIT 1175 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) }, BIT 1177 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_VE] = { 0x2c4, BIT(0) }, BIT 1178 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_LCD0] = { 0x2c4, BIT(4) }, BIT 1179 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_LCD1] = { 0x2c4, BIT(5) }, BIT 1180 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_CSI] = { 0x2c4, BIT(8) }, BIT 1181 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_HDMI] = { 0x2c4, BIT(11) }, BIT 1182 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_BE0] = { 0x2c4, BIT(12) }, BIT 1183 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_BE1] = { 0x2c4, BIT(13) }, BIT 1184 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_FE0] = { 0x2c4, BIT(14) }, BIT 1185 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_FE1] = { 0x2c4, BIT(15) }, BIT 1186 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_MP] = { 0x2c4, BIT(18) }, BIT 1187 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_GPU] = { 0x2c4, BIT(20) }, BIT 1188 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_DEU0] = { 0x2c4, BIT(23) }, BIT 1189 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_DEU1] = { 0x2c4, BIT(24) }, BIT 1190 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_DRC0] = { 0x2c4, BIT(25) }, BIT 1191 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_DRC1] = { 0x2c4, BIT(26) }, BIT 1192 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_AHB1_LVDS] = { 0x2c8, BIT(0) }, BIT 1194 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB1_CODEC] = { 0x2d0, BIT(0) }, BIT 1195 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB1_SPDIF] = { 0x2d0, BIT(1) }, BIT 1196 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) }, BIT 1197 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) }, BIT 1198 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) }, BIT 1200 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB2_I2C0] = { 0x2d8, BIT(0) }, BIT 1201 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB2_I2C1] = { 0x2d8, BIT(1) }, BIT 1202 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB2_I2C2] = { 0x2d8, BIT(2) }, BIT 1203 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB2_I2C3] = { 0x2d8, BIT(3) }, BIT 1204 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB2_UART0] = { 0x2d8, BIT(16) }, BIT 1205 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB2_UART1] = { 0x2d8, BIT(17) }, BIT 1206 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB2_UART2] = { 0x2d8, BIT(18) }, BIT 1207 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB2_UART3] = { 0x2d8, BIT(19) }, BIT 1208 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB2_UART4] = { 0x2d8, BIT(20) }, BIT 1209 drivers/clk/sunxi-ng/ccu-sun6i-a31.c [RST_APB2_UART5] = { 0x2d8, BIT(21) }, BIT 1247 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val &= BIT(16); BIT 28 drivers/clk/sunxi-ng/ccu-sun8i-a23.c .enable = BIT(31), BIT 29 drivers/clk/sunxi-ng/ccu-sun8i-a23.c .lock = BIT(28), BIT 67 drivers/clk/sunxi-ng/ccu-sun8i-a23.c pll_audio_sdm_table, BIT(24), BIT 68 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x284, BIT(31), BIT 69 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 70 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(28), /* lock */ BIT 77 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(24), /* frac enable */ BIT 78 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(25), /* frac select */ BIT 81 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 82 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(28), /* lock */ BIT 89 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(24), /* frac enable */ BIT 90 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(25), /* frac select */ BIT 93 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 94 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(28), /* lock */ BIT 102 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 103 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(28), /* lock */ BIT 110 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 111 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(28), /* lock */ BIT 119 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(24), /* frac enable */ BIT 120 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(25), /* frac select */ BIT 123 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 124 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(28), /* lock */ BIT 140 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31) | BIT(23) | BIT(22), /* gate */ BIT 141 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(28), /* lock */ BIT 148 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(24), /* frac enable */ BIT 149 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(25), /* frac select */ BIT 152 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 153 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(28), /* lock */ BIT 160 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(24), /* frac enable */ BIT 161 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(25), /* frac select */ BIT 164 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 165 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(28), /* lock */ BIT 220 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(1), 0); BIT 222 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(6), 0); BIT 224 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(8), 0); BIT 226 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(9), 0); BIT 228 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(10), 0); BIT 230 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(13), 0); BIT 232 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(14), 0); BIT 234 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(19), 0); BIT 236 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(20), 0); BIT 238 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(21), 0); BIT 240 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(24), 0); BIT 242 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(26), 0); BIT 244 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x060, BIT(29), 0); BIT 247 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x064, BIT(0), 0); BIT 249 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x064, BIT(4), 0); BIT 251 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x064, BIT(8), 0); BIT 253 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x064, BIT(12), 0); BIT 255 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x064, BIT(14), 0); BIT 257 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x064, BIT(20), 0); BIT 259 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x064, BIT(21), 0); BIT 261 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x064, BIT(22), 0); BIT 263 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x064, BIT(25), 0); BIT 266 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x068, BIT(0), 0); BIT 268 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x068, BIT(5), 0); BIT 270 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x068, BIT(12), 0); BIT 272 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x068, BIT(13), 0); BIT 275 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x06c, BIT(0), 0); BIT 277 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x06c, BIT(1), 0); BIT 279 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x06c, BIT(2), 0); BIT 281 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x06c, BIT(16), 0); BIT 283 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x06c, BIT(17), 0); BIT 285 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x06c, BIT(18), 0); BIT 287 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x06c, BIT(19), 0); BIT 289 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x06c, BIT(20), 0); BIT 296 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 303 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 315 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 327 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 339 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 346 drivers/clk/sunxi-ng/ccu-sun8i-a23.c BIT(31), /* gate */ BIT 352 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 355 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 359 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x0cc, BIT(8), 0); BIT 361 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x0cc, BIT(9), 0); BIT 363 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x0cc, BIT(10), 0); BIT 365 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x0cc, BIT(11), 0); BIT 367 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x0cc, BIT(16), 0); BIT 370 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x100, BIT(0), 0); BIT 372 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x100, BIT(1), 0); BIT 374 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x100, BIT(16), 0); BIT 376 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x100, BIT(24), 0); BIT 378 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x100, BIT(26), 0); BIT 385 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x104, 0, 4, 24, 3, BIT(31), 0); BIT 389 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x10c, 0, 4, 24, 3, BIT(31), 0); BIT 396 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x118, 24, 3, BIT(31), BIT 403 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x12c, 0, 4, 24, 2, BIT(31), 0); BIT 410 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x134, 16, 4, 24, 3, BIT(31), 0); BIT 417 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x134, 0, 5, 8, 3, BIT(15), 0); BIT 420 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 423 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x140, BIT(31), CLK_SET_RATE_PARENT); BIT 425 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x144, BIT(31), 0); BIT 430 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); BIT 436 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x168, 16, 4, 24, 2, BIT(31), 0); BIT 442 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x168, 0, 4, 8, 2, BIT(15), 0); BIT 446 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x180, 0, 4, 24, 3, BIT(31), 0); BIT 449 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x1a0, 0, 3, BIT(31), 0); BIT 453 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 0x1b0, 0, 3, 24, 2, BIT(31), 0); BIT 671 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 672 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_USB_PHY1] = { 0x0cc, BIT(1) }, BIT 673 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_USB_HSIC] = { 0x0cc, BIT(2) }, BIT 675 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_MBUS] = { 0x0fc, BIT(31) }, BIT 677 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, BIT 678 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_DMA] = { 0x2c0, BIT(6) }, BIT 679 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, BIT 680 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, BIT 681 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, BIT 682 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_NAND] = { 0x2c0, BIT(13) }, BIT 683 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, BIT 684 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, BIT 685 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, BIT 686 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, BIT 687 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_OTG] = { 0x2c0, BIT(24) }, BIT 688 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_EHCI] = { 0x2c0, BIT(26) }, BIT 689 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_OHCI] = { 0x2c0, BIT(29) }, BIT 691 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_VE] = { 0x2c4, BIT(0) }, BIT 692 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_LCD] = { 0x2c4, BIT(4) }, BIT 693 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_CSI] = { 0x2c4, BIT(8) }, BIT 694 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, BIT 695 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, BIT 696 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_GPU] = { 0x2c4, BIT(20) }, BIT 697 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, BIT 698 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, BIT 699 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_DRC] = { 0x2c4, BIT(25) }, BIT 701 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, BIT 703 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, BIT 704 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, BIT 705 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, BIT 707 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, BIT 708 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, BIT 709 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, BIT 710 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_UART0] = { 0x2d8, BIT(16) }, BIT 711 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_UART1] = { 0x2d8, BIT(17) }, BIT 712 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_UART2] = { 0x2d8, BIT(18) }, BIT 713 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_UART3] = { 0x2d8, BIT(19) }, BIT 714 drivers/clk/sunxi-ng/ccu-sun8i-a23.c [RST_BUS_UART4] = { 0x2d8, BIT(20) }, BIT 745 drivers/clk/sunxi-ng/ccu-sun8i-a23.c val &= ~BIT(16); BIT 26 drivers/clk/sunxi-ng/ccu-sun8i-a33.c .enable = BIT(31), BIT 27 drivers/clk/sunxi-ng/ccu-sun8i-a33.c .lock = BIT(28), BIT 65 drivers/clk/sunxi-ng/ccu-sun8i-a33.c pll_audio_sdm_table, BIT(24), BIT 66 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x284, BIT(31), BIT 67 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 68 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(28), /* lock */ BIT 75 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(24), /* frac enable */ BIT 76 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(25), /* frac select */ BIT 79 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 80 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(28), /* lock */ BIT 87 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(24), /* frac enable */ BIT 88 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(25), /* frac select */ BIT 91 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 92 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(28), /* lock */ BIT 100 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 101 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(28), /* lock */ BIT 108 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 109 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(28), /* lock */ BIT 117 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(24), /* frac enable */ BIT 118 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(25), /* frac select */ BIT 121 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 122 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(28), /* lock */ BIT 138 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31) | BIT(23) | BIT(22), /* gate */ BIT 139 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(28), /* lock */ BIT 146 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(24), /* frac enable */ BIT 147 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(25), /* frac select */ BIT 150 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 151 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(28), /* lock */ BIT 158 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(24), /* frac enable */ BIT 159 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(25), /* frac select */ BIT 162 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 163 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(28), /* lock */ BIT 167 drivers/clk/sunxi-ng/ccu-sun8i-a33.c .enable = BIT(31), BIT 168 drivers/clk/sunxi-ng/ccu-sun8i-a33.c .lock = BIT(28), BIT 230 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(1), 0); BIT 232 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(5), 0); BIT 234 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(6), 0); BIT 236 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(8), 0); BIT 238 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(9), 0); BIT 240 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(10), 0); BIT 242 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(13), 0); BIT 244 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(14), 0); BIT 246 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(19), 0); BIT 248 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(20), 0); BIT 250 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(21), 0); BIT 252 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(24), 0); BIT 254 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(26), 0); BIT 256 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x060, BIT(29), 0); BIT 259 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x064, BIT(0), 0); BIT 261 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x064, BIT(4), 0); BIT 263 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x064, BIT(8), 0); BIT 265 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x064, BIT(12), 0); BIT 267 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x064, BIT(14), 0); BIT 269 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x064, BIT(20), 0); BIT 271 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x064, BIT(21), 0); BIT 273 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x064, BIT(22), 0); BIT 275 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x064, BIT(25), 0); BIT 277 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x064, BIT(26), 0); BIT 280 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x068, BIT(0), 0); BIT 282 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x068, BIT(5), 0); BIT 284 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x068, BIT(12), 0); BIT 286 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x068, BIT(13), 0); BIT 289 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x06c, BIT(0), 0); BIT 291 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x06c, BIT(1), 0); BIT 293 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x06c, BIT(2), 0); BIT 295 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x06c, BIT(16), 0); BIT 297 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x06c, BIT(17), 0); BIT 299 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x06c, BIT(18), 0); BIT 301 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x06c, BIT(19), 0); BIT 303 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x06c, BIT(20), 0); BIT 310 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 317 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 329 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 341 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 353 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 360 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 367 drivers/clk/sunxi-ng/ccu-sun8i-a33.c BIT(31), /* gate */ BIT 373 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 376 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 380 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x0cc, BIT(8), 0); BIT 382 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x0cc, BIT(9), 0); BIT 384 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x0cc, BIT(10), 0); BIT 386 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x0cc, BIT(11), 0); BIT 388 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x0cc, BIT(16), 0); BIT 398 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x100, BIT(0), 0); BIT 400 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x100, BIT(1), 0); BIT 402 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x100, BIT(16), 0); BIT 404 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x100, BIT(24), 0); BIT 406 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x100, BIT(26), 0); BIT 413 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x104, 0, 4, 24, 3, BIT(31), 0); BIT 417 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x10c, 0, 4, 24, 3, BIT(31), 0); BIT 424 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x118, 24, 3, BIT(31), BIT 431 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x12c, 0, 4, 24, 2, BIT(31), 0); BIT 438 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x134, 16, 4, 24, 3, BIT(31), 0); BIT 445 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x134, 0, 5, 8, 3, BIT(15), 0); BIT 448 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 451 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x140, BIT(31), CLK_SET_RATE_PARENT); BIT 453 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x140, BIT(30), CLK_SET_RATE_PARENT); BIT 455 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x144, BIT(31), 0); BIT 460 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); BIT 466 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x168, 16, 4, 24, 2, BIT(31), 0); BIT 472 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x168, 0, 4, 8, 2, BIT(15), 0); BIT 476 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x180, 0, 4, 24, 3, BIT(31), 0); BIT 479 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 483 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 0x1b0, 0, 3, 24, 2, BIT(31), 0); BIT 715 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 716 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_USB_PHY1] = { 0x0cc, BIT(1) }, BIT 717 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_USB_HSIC] = { 0x0cc, BIT(2) }, BIT 719 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_MBUS] = { 0x0fc, BIT(31) }, BIT 721 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, BIT 722 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_SS] = { 0x2c0, BIT(5) }, BIT 723 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_DMA] = { 0x2c0, BIT(6) }, BIT 724 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, BIT 725 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, BIT 726 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, BIT 727 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_NAND] = { 0x2c0, BIT(13) }, BIT 728 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, BIT 729 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, BIT 730 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, BIT 731 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, BIT 732 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_OTG] = { 0x2c0, BIT(24) }, BIT 733 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_EHCI] = { 0x2c0, BIT(26) }, BIT 734 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_OHCI] = { 0x2c0, BIT(29) }, BIT 736 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_VE] = { 0x2c4, BIT(0) }, BIT 737 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_LCD] = { 0x2c4, BIT(4) }, BIT 738 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_CSI] = { 0x2c4, BIT(8) }, BIT 739 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, BIT 740 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, BIT 741 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_GPU] = { 0x2c4, BIT(20) }, BIT 742 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, BIT 743 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, BIT 744 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_DRC] = { 0x2c4, BIT(25) }, BIT 745 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_SAT] = { 0x2c4, BIT(26) }, BIT 747 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, BIT 749 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, BIT 750 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, BIT 751 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, BIT 753 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, BIT 754 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, BIT 755 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, BIT 756 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_UART0] = { 0x2d8, BIT(16) }, BIT 757 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_UART1] = { 0x2d8, BIT(17) }, BIT 758 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_UART2] = { 0x2d8, BIT(18) }, BIT 759 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_UART3] = { 0x2d8, BIT(19) }, BIT 760 drivers/clk/sunxi-ng/ccu-sun8i-a33.c [RST_BUS_UART4] = { 0x2d8, BIT(20) }, BIT 776 drivers/clk/sunxi-ng/ccu-sun8i-a33.c .enable = BIT(31), BIT 777 drivers/clk/sunxi-ng/ccu-sun8i-a33.c .lock = BIT(28), BIT 805 drivers/clk/sunxi-ng/ccu-sun8i-a33.c val &= ~BIT(16); BIT 37 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 38 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(0), BIT 51 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 52 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(1), BIT 79 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 80 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(2), BIT 84 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24), BIT 85 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x284, BIT(31)), BIT 99 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 100 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(3), BIT 116 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 117 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(4), BIT 132 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 133 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(5), BIT 148 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 149 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(6), BIT 164 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 165 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(7), BIT 180 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 181 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(8), BIT 196 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 197 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(9), BIT 212 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(31), BIT 213 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .lock = BIT(10), BIT 296 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(1), 0); BIT 298 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(5), 0); BIT 300 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(6), 0); BIT 302 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(8), 0); BIT 304 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(9), 0); BIT 306 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(10), 0); BIT 308 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(13), 0); BIT 310 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(14), 0); BIT 312 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(17), 0); BIT 314 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(19), 0); BIT 316 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(20), 0); BIT 318 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(21), 0); BIT 320 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(24), 0); BIT 322 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(26), 0); BIT 324 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(27), 0); BIT 326 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x060, BIT(29), 0); BIT 329 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x064, BIT(0), 0); BIT 331 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x064, BIT(4), 0); BIT 333 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x064, BIT(5), 0); BIT 335 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x064, BIT(8), 0); BIT 337 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x064, BIT(11), 0); BIT 339 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x064, BIT(12), 0); BIT 341 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x064, BIT(20), 0); BIT 343 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x064, BIT(21), 0); BIT 345 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x064, BIT(22), 0); BIT 348 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x068, BIT(1), 0); BIT 350 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x068, BIT(5), 0); BIT 352 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x068, BIT(12), 0); BIT 354 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x068, BIT(13), 0); BIT 356 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x068, BIT(14), 0); BIT 358 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x068, BIT(15), 0); BIT 361 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x06c, BIT(0), 0); BIT 363 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x06c, BIT(1), 0); BIT 365 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x06c, BIT(2), 0); BIT 367 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x06c, BIT(16), 0); BIT 369 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x06c, BIT(17), 0); BIT 371 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x06c, BIT(18), 0); BIT 373 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x06c, BIT(19), 0); BIT 375 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x06c, BIT(20), 0); BIT 398 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 406 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 419 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 440 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 448 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 456 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 460 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x0b0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 462 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x0b4, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 464 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x0b8, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 466 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x0bc, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 468 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 471 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x0cc, BIT(8), 0); BIT 473 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x0cc, BIT(9), 0); BIT 475 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x0cc, BIT(10), 0); BIT 477 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .enable = BIT(11), BIT 487 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x0cc, BIT(16), 0); BIT 493 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x100, BIT(0), 0); BIT 495 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x100, BIT(1), 0); BIT 499 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 503 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 505 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0); BIT 507 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0); BIT 517 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(15), /* gate */ BIT 527 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 531 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 16, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 533 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); BIT 540 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 543 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x154, BIT(31), 0); BIT 551 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 561 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 571 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 575 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 583 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c BIT(31), /* gate */ BIT 587 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 0, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 801 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 802 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_USB_PHY1] = { 0x0cc, BIT(1) }, BIT 803 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_USB_HSIC] = { 0x0cc, BIT(2) }, BIT 804 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_DRAM] = { 0x0f4, BIT(31) }, BIT 805 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_MBUS] = { 0x0fc, BIT(31) }, BIT 806 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, BIT 807 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_SS] = { 0x2c0, BIT(5) }, BIT 808 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_DMA] = { 0x2c0, BIT(6) }, BIT 809 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, BIT 810 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, BIT 811 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, BIT 812 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_NAND] = { 0x2c0, BIT(13) }, BIT 813 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, BIT 814 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, BIT 815 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, BIT 816 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, BIT 817 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, BIT 818 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_OTG] = { 0x2c0, BIT(24) }, BIT 819 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, BIT 820 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_EHCI1] = { 0x2c0, BIT(27) }, BIT 821 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, BIT 822 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_VE] = { 0x2c4, BIT(0) }, BIT 823 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, BIT 824 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_TCON1] = { 0x2c4, BIT(5) }, BIT 825 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_CSI] = { 0x2c4, BIT(8) }, BIT 826 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, BIT 827 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, BIT 828 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_DE] = { 0x2c4, BIT(12) }, BIT 829 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_GPU] = { 0x2c4, BIT(20) }, BIT 830 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, BIT 831 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, BIT 832 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, BIT 833 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, BIT 834 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, BIT 835 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, BIT 836 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, BIT 837 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_TDM] = { 0x2d0, BIT(15) }, BIT 838 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, BIT 839 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, BIT 840 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, BIT 841 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_UART0] = { 0x2d8, BIT(16) }, BIT 842 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_UART1] = { 0x2d8, BIT(17) }, BIT 843 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_UART2] = { 0x2d8, BIT(18) }, BIT 844 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_UART3] = { 0x2d8, BIT(19) }, BIT 845 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c [RST_BUS_UART4] = { 0x2d8, BIT(20) }, BIT 867 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c if (!(val & BIT(SUN8I_A83T_PLL_P_SHIFT))) BIT 883 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c val &= ~BIT(SUN8I_A83T_PLL_P_SHIFT); BIT 901 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c val &= ~BIT(16); BIT 902 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c val |= BIT(18); BIT 21 drivers/clk/sunxi-ng/ccu-sun8i-de2.c 0x04, BIT(0), 0); BIT 23 drivers/clk/sunxi-ng/ccu-sun8i-de2.c 0x04, BIT(1), 0); BIT 25 drivers/clk/sunxi-ng/ccu-sun8i-de2.c 0x04, BIT(2), 0); BIT 27 drivers/clk/sunxi-ng/ccu-sun8i-de2.c 0x04, BIT(3), 0); BIT 30 drivers/clk/sunxi-ng/ccu-sun8i-de2.c 0x00, BIT(0), CLK_SET_RATE_PARENT); BIT 32 drivers/clk/sunxi-ng/ccu-sun8i-de2.c 0x00, BIT(1), CLK_SET_RATE_PARENT); BIT 34 drivers/clk/sunxi-ng/ccu-sun8i-de2.c 0x00, BIT(2), CLK_SET_RATE_PARENT); BIT 36 drivers/clk/sunxi-ng/ccu-sun8i-de2.c 0x00, BIT(3), CLK_SET_RATE_PARENT); BIT 180 drivers/clk/sunxi-ng/ccu-sun8i-de2.c [RST_MIXER0] = { 0x08, BIT(0) }, BIT 186 drivers/clk/sunxi-ng/ccu-sun8i-de2.c [RST_WB] = { 0x08, BIT(2) }, BIT 190 drivers/clk/sunxi-ng/ccu-sun8i-de2.c [RST_MIXER0] = { 0x08, BIT(0) }, BIT 191 drivers/clk/sunxi-ng/ccu-sun8i-de2.c [RST_MIXER1] = { 0x08, BIT(1) }, BIT 192 drivers/clk/sunxi-ng/ccu-sun8i-de2.c [RST_WB] = { 0x08, BIT(2) }, BIT 196 drivers/clk/sunxi-ng/ccu-sun8i-de2.c [RST_MIXER0] = { 0x08, BIT(0) }, BIT 197 drivers/clk/sunxi-ng/ccu-sun8i-de2.c [RST_MIXER1] = { 0x08, BIT(1) }, BIT 198 drivers/clk/sunxi-ng/ccu-sun8i-de2.c [RST_WB] = { 0x08, BIT(2) }, BIT 199 drivers/clk/sunxi-ng/ccu-sun8i-de2.c [RST_ROT] = { 0x08, BIT(3) }, BIT 32 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 33 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(28), /* lock */ BIT 59 drivers/clk/sunxi-ng/ccu-sun8i-h3.c pll_audio_sdm_table, BIT(24), BIT 60 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x284, BIT(31), BIT 61 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 62 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(28), /* lock */ BIT 71 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(24), /* frac enable */ BIT 72 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(25), /* frac select */ BIT 75 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 76 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(28), /* lock */ BIT 83 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(24), /* frac enable */ BIT 84 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(25), /* frac select */ BIT 87 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 88 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(28), /* lock */ BIT 96 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 97 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(28), /* lock */ BIT 104 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 105 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(28), /* lock */ BIT 113 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(24), /* frac enable */ BIT 114 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(25), /* frac select */ BIT 117 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 118 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(28), /* lock */ BIT 125 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 126 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(28), /* lock */ BIT 134 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(24), /* frac enable */ BIT 135 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(25), /* frac select */ BIT 138 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 139 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(28), /* lock */ BIT 216 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(5), 0); BIT 218 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(6), 0); BIT 220 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(8), 0); BIT 222 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(9), 0); BIT 224 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(10), 0); BIT 226 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(13), 0); BIT 228 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(14), 0); BIT 230 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(17), 0); BIT 232 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(18), 0); BIT 234 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(19), 0); BIT 236 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(20), 0); BIT 238 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(21), 0); BIT 240 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(23), 0); BIT 242 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(24), 0); BIT 244 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(25), 0); BIT 246 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(26), 0); BIT 248 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(27), 0); BIT 250 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(28), 0); BIT 252 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(29), 0); BIT 254 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(30), 0); BIT 256 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x060, BIT(31), 0); BIT 259 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(0), 0); BIT 261 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(3), 0); BIT 263 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(4), 0); BIT 265 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(5), 0); BIT 267 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(8), 0); BIT 269 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(9), 0); BIT 271 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(11), 0); BIT 273 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(12), 0); BIT 275 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(20), 0); BIT 277 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(21), 0); BIT 279 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x064, BIT(22), 0); BIT 282 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x068, BIT(0), 0); BIT 284 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x068, BIT(1), 0); BIT 286 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x068, BIT(5), 0); BIT 288 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x068, BIT(8), 0); BIT 290 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x068, BIT(12), 0); BIT 292 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x068, BIT(13), 0); BIT 294 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x068, BIT(14), 0); BIT 297 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x06c, BIT(0), 0); BIT 299 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x06c, BIT(1), 0); BIT 301 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x06c, BIT(2), 0); BIT 303 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x06c, BIT(16), 0); BIT 305 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x06c, BIT(17), 0); BIT 307 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x06c, BIT(18), 0); BIT 309 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x06c, BIT(19), 0); BIT 311 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x06c, BIT(20), 0); BIT 313 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x06c, BIT(21), 0); BIT 316 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x070, BIT(0), 0); BIT 318 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x070, BIT(7), 0); BIT 327 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x074, 0, 2, ths_div_table, BIT(31), 0); BIT 335 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 342 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 354 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 366 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 379 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 386 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 393 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 400 drivers/clk/sunxi-ng/ccu-sun8i-h3.c BIT(31), /* gate */ BIT 406 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 409 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 412 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 415 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 418 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0cc, BIT(8), 0); BIT 420 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0cc, BIT(9), 0); BIT 422 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0cc, BIT(10), 0); BIT 424 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0cc, BIT(11), 0); BIT 426 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0cc, BIT(16), 0); BIT 428 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0cc, BIT(17), 0); BIT 430 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0cc, BIT(18), 0); BIT 432 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x0cc, BIT(19), 0); BIT 439 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x100, BIT(0), 0); BIT 441 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x100, BIT(1), 0); BIT 443 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x100, BIT(2), 0); BIT 445 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x100, BIT(3), 0); BIT 449 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x104, 0, 4, 24, 3, BIT(31), BIT 454 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x118, 0, 4, 24, 3, BIT(31), BIT 459 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x120, 0, 4, 24, 3, BIT(31), 0); BIT 463 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x124, 0, 4, 24, 3, BIT(31), 0); BIT 466 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x130, BIT(31), 0); BIT 470 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x134, 16, 4, 24, 3, BIT(31), 0); BIT 474 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x134, 0, 5, 8, 3, BIT(15), 0); BIT 477 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 480 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x140, BIT(31), CLK_SET_RATE_PARENT); BIT 482 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x144, BIT(31), 0); BIT 486 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x150, 0, 4, 24, 2, BIT(31), BIT 490 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x154, BIT(31), 0); BIT 494 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); BIT 497 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 979 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 980 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_USB_PHY1] = { 0x0cc, BIT(1) }, BIT 981 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_USB_PHY2] = { 0x0cc, BIT(2) }, BIT 982 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_USB_PHY3] = { 0x0cc, BIT(3) }, BIT 984 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_MBUS] = { 0x0fc, BIT(31) }, BIT 986 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_CE] = { 0x2c0, BIT(5) }, BIT 987 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_DMA] = { 0x2c0, BIT(6) }, BIT 988 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, BIT 989 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, BIT 990 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, BIT 991 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_NAND] = { 0x2c0, BIT(13) }, BIT 992 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, BIT 993 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, BIT 994 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_TS] = { 0x2c0, BIT(18) }, BIT 995 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, BIT 996 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, BIT 997 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, BIT 998 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_OTG] = { 0x2c0, BIT(23) }, BIT 999 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, BIT 1000 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, BIT 1001 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EHCI2] = { 0x2c0, BIT(26) }, BIT 1002 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EHCI3] = { 0x2c0, BIT(27) }, BIT 1003 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, BIT 1004 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, BIT 1005 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_OHCI2] = { 0x2c0, BIT(30) }, BIT 1006 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_OHCI3] = { 0x2c0, BIT(31) }, BIT 1008 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_VE] = { 0x2c4, BIT(0) }, BIT 1009 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, BIT 1010 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, BIT 1011 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, BIT 1012 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_CSI] = { 0x2c4, BIT(8) }, BIT 1013 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_TVE] = { 0x2c4, BIT(9) }, BIT 1014 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, BIT 1015 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, BIT 1016 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_DE] = { 0x2c4, BIT(12) }, BIT 1017 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_GPU] = { 0x2c4, BIT(20) }, BIT 1018 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, BIT 1019 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, BIT 1020 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_DBG] = { 0x2c4, BIT(31) }, BIT 1022 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, BIT 1024 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, BIT 1025 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, BIT 1026 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_THS] = { 0x2d0, BIT(8) }, BIT 1027 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, BIT 1028 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, BIT 1029 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, BIT 1031 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, BIT 1032 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, BIT 1033 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, BIT 1034 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_UART0] = { 0x2d8, BIT(16) }, BIT 1035 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_UART1] = { 0x2d8, BIT(17) }, BIT 1036 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_UART2] = { 0x2d8, BIT(18) }, BIT 1037 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_UART3] = { 0x2d8, BIT(19) }, BIT 1038 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SCR0] = { 0x2d8, BIT(20) }, BIT 1042 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 1043 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_USB_PHY1] = { 0x0cc, BIT(1) }, BIT 1044 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_USB_PHY2] = { 0x0cc, BIT(2) }, BIT 1045 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_USB_PHY3] = { 0x0cc, BIT(3) }, BIT 1047 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_MBUS] = { 0x0fc, BIT(31) }, BIT 1049 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_CE] = { 0x2c0, BIT(5) }, BIT 1050 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_DMA] = { 0x2c0, BIT(6) }, BIT 1051 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, BIT 1052 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, BIT 1053 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, BIT 1054 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_NAND] = { 0x2c0, BIT(13) }, BIT 1055 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, BIT 1056 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, BIT 1057 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_TS] = { 0x2c0, BIT(18) }, BIT 1058 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, BIT 1059 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, BIT 1060 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, BIT 1061 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_OTG] = { 0x2c0, BIT(23) }, BIT 1062 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, BIT 1063 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, BIT 1064 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EHCI2] = { 0x2c0, BIT(26) }, BIT 1065 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EHCI3] = { 0x2c0, BIT(27) }, BIT 1066 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, BIT 1067 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, BIT 1068 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_OHCI2] = { 0x2c0, BIT(30) }, BIT 1069 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_OHCI3] = { 0x2c0, BIT(31) }, BIT 1071 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_VE] = { 0x2c4, BIT(0) }, BIT 1072 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, BIT 1073 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, BIT 1074 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, BIT 1075 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_CSI] = { 0x2c4, BIT(8) }, BIT 1076 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_TVE] = { 0x2c4, BIT(9) }, BIT 1077 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, BIT 1078 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, BIT 1079 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_DE] = { 0x2c4, BIT(12) }, BIT 1080 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_GPU] = { 0x2c4, BIT(20) }, BIT 1081 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, BIT 1082 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, BIT 1083 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_DBG] = { 0x2c4, BIT(31) }, BIT 1085 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, BIT 1087 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, BIT 1088 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, BIT 1089 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_THS] = { 0x2d0, BIT(8) }, BIT 1090 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, BIT 1091 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, BIT 1092 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, BIT 1094 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, BIT 1095 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, BIT 1096 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, BIT 1097 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_UART0] = { 0x2d8, BIT(16) }, BIT 1098 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_UART1] = { 0x2d8, BIT(17) }, BIT 1099 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_UART2] = { 0x2d8, BIT(18) }, BIT 1100 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_UART3] = { 0x2d8, BIT(19) }, BIT 1101 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SCR0] = { 0x2d8, BIT(20) }, BIT 1102 drivers/clk/sunxi-ng/ccu-sun8i-h3.c [RST_BUS_SCR1] = { 0x2d8, BIT(20) }, BIT 1128 drivers/clk/sunxi-ng/ccu-sun8i-h3.c .enable = BIT(31), BIT 1129 drivers/clk/sunxi-ng/ccu-sun8i-h3.c .lock = BIT(28), BIT 63 drivers/clk/sunxi-ng/ccu-sun8i-r.c apb0_gate_parent, 0x28, BIT(0), 0); BIT 65 drivers/clk/sunxi-ng/ccu-sun8i-r.c apb0_gate_parent, 0x28, BIT(1), 0); BIT 67 drivers/clk/sunxi-ng/ccu-sun8i-r.c apb0_gate_parent, 0x28, BIT(2), 0); BIT 69 drivers/clk/sunxi-ng/ccu-sun8i-r.c apb0_gate_parent, 0x28, BIT(3), 0); BIT 71 drivers/clk/sunxi-ng/ccu-sun8i-r.c apb0_gate_parent, 0x28, BIT(4), 0); BIT 73 drivers/clk/sunxi-ng/ccu-sun8i-r.c apb0_gate_parent, 0x28, BIT(6), 0); BIT 75 drivers/clk/sunxi-ng/ccu-sun8i-r.c apb0_gate_parent, 0x28, BIT(7), 0); BIT 83 drivers/clk/sunxi-ng/ccu-sun8i-r.c BIT(31), /* gate */ BIT 94 drivers/clk/sunxi-ng/ccu-sun8i-r.c .enable = BIT(31), BIT 205 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_IR] = { 0xb0, BIT(1) }, BIT 206 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_TIMER] = { 0xb0, BIT(2) }, BIT 207 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_RSB] = { 0xb0, BIT(3) }, BIT 208 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_UART] = { 0xb0, BIT(4) }, BIT 209 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_I2C] = { 0xb0, BIT(6) }, BIT 213 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_IR] = { 0xb0, BIT(1) }, BIT 214 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_TIMER] = { 0xb0, BIT(2) }, BIT 215 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_UART] = { 0xb0, BIT(4) }, BIT 216 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_I2C] = { 0xb0, BIT(6) }, BIT 220 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_IR] = { 0xb0, BIT(1) }, BIT 221 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_TIMER] = { 0xb0, BIT(2) }, BIT 222 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_RSB] = { 0xb0, BIT(3) }, BIT 223 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_UART] = { 0xb0, BIT(4) }, BIT 224 drivers/clk/sunxi-ng/ccu-sun8i-r.c [RST_APB0_I2C] = { 0xb0, BIT(6) }, BIT 28 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(31), BIT 29 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .lock = BIT(28), BIT 57 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 58 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(28), /* lock */ BIT 67 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(24), /* frac enable */ BIT 68 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(25), /* frac select */ BIT 71 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 72 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(28), /* lock */ BIT 80 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(24), /* frac enable */ BIT 81 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(25), /* frac select */ BIT 84 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 85 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(28), /* lock */ BIT 94 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 95 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(28), /* lock */ BIT 100 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(31), BIT 101 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .lock = BIT(28), BIT 115 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(24), BIT 134 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(31), BIT 135 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .lock = BIT(28), BIT 154 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(24), /* frac enable */ BIT 155 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(25), /* frac select */ BIT 158 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 159 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(28), /* lock */ BIT 163 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(31), BIT 164 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .lock = BIT(28), BIT 183 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(14), /* gate */ BIT 191 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(24), /* frac enable */ BIT 192 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(25), /* frac select */ BIT 195 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 196 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(28), /* lock */ BIT 213 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(31) | BIT(23) | BIT(22), BIT 214 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .lock = BIT(28), BIT 233 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(24), /* frac enable */ BIT 234 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(25), /* frac select */ BIT 237 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 238 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(28), /* lock */ BIT 246 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 247 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(28), /* lock */ BIT 303 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(1), 0); BIT 305 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(5), 0); BIT 307 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(6), 0); BIT 309 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(8), 0); BIT 311 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(9), 0); BIT 313 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(10), 0); BIT 315 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(11), 0); BIT 317 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(13), 0); BIT 319 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(14), 0); BIT 321 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(17), 0); BIT 323 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(18), 0); BIT 325 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(19), 0); BIT 327 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(20), 0); BIT 329 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(21), 0); BIT 331 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(22), 0); BIT 333 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(23), 0); BIT 335 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(24), 0); BIT 337 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(25), 0); BIT 339 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(26), 0); BIT 341 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(27), 0); BIT 343 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(28), 0); BIT 345 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(29), 0); BIT 347 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(30), 0); BIT 349 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x060, BIT(31), 0); BIT 352 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(0), 0); BIT 354 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(2), 0); BIT 356 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(5), 0); BIT 358 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(8), 0); BIT 360 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(9), 0); BIT 362 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(10), 0); BIT 364 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(11), 0); BIT 366 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(12), 0); BIT 368 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(13), 0); BIT 370 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(14), 0); BIT 372 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(15), 0); BIT 374 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(17), 0); BIT 376 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(20), 0); BIT 378 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(21), 0); BIT 380 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(22), 0); BIT 382 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(23), 0); BIT 384 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(24), 0); BIT 386 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(25), 0); BIT 388 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(26), 0); BIT 390 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(27), 0); BIT 392 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(28), 0); BIT 394 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(29), 0); BIT 396 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x064, BIT(30), 0); BIT 399 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(0), 0); BIT 401 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(1), 0); BIT 403 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(2), 0); BIT 405 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(5), 0); BIT 407 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(6), 0); BIT 409 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(7), 0); BIT 411 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(8), 0); BIT 413 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(10), 0); BIT 415 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(12), 0); BIT 417 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(13), 0); BIT 419 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x068, BIT(14), 0); BIT 422 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(0), 0); BIT 424 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(1), 0); BIT 426 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(2), 0); BIT 428 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(3), 0); BIT 434 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(4), 0); BIT 436 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(5), 0); BIT 438 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(6), 0); BIT 440 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(7), 0); BIT 442 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(15), 0); BIT 444 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(16), 0); BIT 446 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(17), 0); BIT 448 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(18), 0); BIT 450 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(19), 0); BIT 452 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(20), 0); BIT 454 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(21), 0); BIT 456 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(22), 0); BIT 458 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x06c, BIT(23), 0); BIT 461 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x070, BIT(7), 0); BIT 465 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(31), BIT 483 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 490 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 497 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 504 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 511 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 519 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 528 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 535 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 542 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 549 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 556 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 562 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 565 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 568 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 571 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 574 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 579 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(31), BIT 594 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT); BIT 603 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0cc, BIT(8), 0); BIT 605 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0cc, BIT(9), 0); BIT 607 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0cc, BIT(10), 0); BIT 609 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0cc, BIT(16), 0); BIT 611 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0cc, BIT(17), 0); BIT 613 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x0cc, BIT(18), 0); BIT 621 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 628 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 636 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x100, BIT(0), 0); BIT 638 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x100, BIT(1), 0); BIT 640 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x100, BIT(2), 0); BIT 642 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x100, BIT(3), 0); BIT 644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x100, BIT(4), 0); BIT 646 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x100, BIT(5), 0); BIT 648 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x100, BIT(6), 0); BIT 652 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x104, 0, 4, 24, 3, BIT(31), BIT 655 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x108, 0, 4, 24, 3, BIT(31), 0); BIT 661 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 663 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 665 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x118, 0, 4, 24, 3, BIT(31), BIT 668 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x11c, 0, 4, 24, 3, BIT(31), BIT 675 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), 0); BIT 680 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x130, 0, 5, 8, 3, BIT(15), 0); BIT 684 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x134, 16, 4, 24, 3, BIT(31), 0); BIT 687 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x134, 0, 5, 8, 3, BIT(15), 0); BIT 690 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 693 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x140, BIT(31), CLK_SET_RATE_PARENT); BIT 695 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x144, BIT(31), 0); BIT 699 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x150, 0, 4, 24, 2, BIT(31), BIT 703 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x154, BIT(31), 0); BIT 718 drivers/clk/sunxi-ng/ccu-sun8i-r40.c BIT(31), /* gate */ BIT 724 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x168, 0, 4, 8, 2, BIT(15), 0); BIT 727 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x180, 0, 4, 24, 3, BIT(31), 0); BIT 729 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x184, 0, 4, 24, 3, BIT(31), 0); BIT 734 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x188, 0, 4, 24, 3, BIT(31), 0); BIT 736 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x18c, 0, 4, 24, 3, BIT(31), 0); BIT 738 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x190, 0, 4, 24, 3, BIT(31), 0); BIT 740 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x194, 0, 4, 24, 3, BIT(31), 0); BIT 743 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 751 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(31), BIT 770 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(31), BIT 1154 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 1155 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_USB_PHY1] = { 0x0cc, BIT(1) }, BIT 1156 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_USB_PHY2] = { 0x0cc, BIT(2) }, BIT 1158 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_DRAM] = { 0x0f4, BIT(31) }, BIT 1159 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_MBUS] = { 0x0fc, BIT(31) }, BIT 1161 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, BIT 1162 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_CE] = { 0x2c0, BIT(5) }, BIT 1163 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_DMA] = { 0x2c0, BIT(6) }, BIT 1164 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, BIT 1165 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, BIT 1166 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, BIT 1167 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_MMC3] = { 0x2c0, BIT(11) }, BIT 1168 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_NAND] = { 0x2c0, BIT(13) }, BIT 1169 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, BIT 1170 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, BIT 1171 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TS] = { 0x2c0, BIT(18) }, BIT 1172 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, BIT 1173 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, BIT 1174 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, BIT 1175 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_SPI2] = { 0x2c0, BIT(22) }, BIT 1176 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_SPI3] = { 0x2c0, BIT(23) }, BIT 1177 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_SATA] = { 0x2c0, BIT(24) }, BIT 1178 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_OTG] = { 0x2c0, BIT(25) }, BIT 1179 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, BIT 1180 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_EHCI1] = { 0x2c0, BIT(27) }, BIT 1181 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_EHCI2] = { 0x2c0, BIT(28) }, BIT 1182 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, BIT 1183 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_OHCI1] = { 0x2c0, BIT(30) }, BIT 1184 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_OHCI2] = { 0x2c0, BIT(31) }, BIT 1186 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_VE] = { 0x2c4, BIT(0) }, BIT 1187 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_MP] = { 0x2c4, BIT(2) }, BIT 1188 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, BIT 1189 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_CSI0] = { 0x2c4, BIT(8) }, BIT 1190 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_CSI1] = { 0x2c4, BIT(9) }, BIT 1191 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, BIT 1192 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, BIT 1193 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_DE] = { 0x2c4, BIT(12) }, BIT 1194 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TVE0] = { 0x2c4, BIT(13) }, BIT 1195 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TVE1] = { 0x2c4, BIT(14) }, BIT 1196 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) }, BIT 1197 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_GMAC] = { 0x2c4, BIT(17) }, BIT 1198 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_GPU] = { 0x2c4, BIT(20) }, BIT 1199 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TVD0] = { 0x2c4, BIT(21) }, BIT 1200 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TVD1] = { 0x2c4, BIT(22) }, BIT 1201 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TVD2] = { 0x2c4, BIT(23) }, BIT 1202 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TVD3] = { 0x2c4, BIT(24) }, BIT 1203 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) }, BIT 1204 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TCON_LCD0] = { 0x2c4, BIT(26) }, BIT 1205 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TCON_LCD1] = { 0x2c4, BIT(27) }, BIT 1206 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TCON_TV0] = { 0x2c4, BIT(28) }, BIT 1207 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TCON_TV1] = { 0x2c4, BIT(29) }, BIT 1208 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) }, BIT 1209 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_DBG] = { 0x2c4, BIT(31) }, BIT 1211 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, BIT 1213 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, BIT 1214 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, BIT 1215 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_AC97] = { 0x2d0, BIT(2) }, BIT 1216 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_IR0] = { 0x2d0, BIT(6) }, BIT 1217 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_IR1] = { 0x2d0, BIT(7) }, BIT 1218 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_THS] = { 0x2d0, BIT(8) }, BIT 1219 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_KEYPAD] = { 0x2d0, BIT(10) }, BIT 1220 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, BIT 1221 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, BIT 1222 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, BIT 1224 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, BIT 1225 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, BIT 1226 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, BIT 1227 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_I2C3] = { 0x2d8, BIT(3) }, BIT 1228 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_CAN] = { 0x2d8, BIT(4) }, BIT 1229 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_SCR] = { 0x2d8, BIT(5) }, BIT 1230 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_PS20] = { 0x2d8, BIT(6) }, BIT 1231 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_PS21] = { 0x2d8, BIT(7) }, BIT 1232 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_I2C4] = { 0x2d8, BIT(15) }, BIT 1233 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_UART0] = { 0x2d8, BIT(16) }, BIT 1234 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_UART1] = { 0x2d8, BIT(17) }, BIT 1235 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_UART2] = { 0x2d8, BIT(18) }, BIT 1236 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_UART3] = { 0x2d8, BIT(19) }, BIT 1237 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_UART4] = { 0x2d8, BIT(20) }, BIT 1238 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_UART5] = { 0x2d8, BIT(21) }, BIT 1239 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_UART6] = { 0x2d8, BIT(22) }, BIT 1240 drivers/clk/sunxi-ng/ccu-sun8i-r40.c [RST_BUS_UART7] = { 0x2d8, BIT(23) }, BIT 1256 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .enable = BIT(31), BIT 1257 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .lock = BIT(28), BIT 1317 drivers/clk/sunxi-ng/ccu-sun8i-r40.c val &= ~BIT(16); BIT 1330 drivers/clk/sunxi-ng/ccu-sun8i-r40.c writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8), BIT 34 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 35 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(28), /* lock */ BIT 52 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 53 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(28), /* lock */ BIT 60 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(24), /* frac enable */ BIT 61 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(25), /* frac select */ BIT 64 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 65 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(28), /* lock */ BIT 72 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(24), /* frac enable */ BIT 73 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(25), /* frac select */ BIT 76 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 77 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(28), /* lock */ BIT 85 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 86 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(28), /* lock */ BIT 93 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 94 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(28), /* lock */ BIT 102 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(24), /* frac enable */ BIT 103 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(25), /* frac select */ BIT 106 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 107 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(28), /* lock */ BIT 114 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 115 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(28), /* lock */ BIT 123 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 124 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(28), /* lock */ BIT 201 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(5), 0); BIT 203 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(6), 0); BIT 205 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(8), 0); BIT 207 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(9), 0); BIT 209 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(10), 0); BIT 211 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(14), 0); BIT 213 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(17), 0); BIT 215 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(19), 0); BIT 217 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(20), 0); BIT 219 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(24), 0); BIT 221 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(26), 0); BIT 223 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x060, BIT(29), 0); BIT 226 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x064, BIT(0), 0); BIT 228 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x064, BIT(4), 0); BIT 230 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x064, BIT(8), 0); BIT 232 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x064, BIT(12), 0); BIT 235 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x068, BIT(0), 0); BIT 237 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x068, BIT(5), 0); BIT 239 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x068, BIT(12), 0); BIT 242 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x06c, BIT(0), 0); BIT 244 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x06c, BIT(1), 0); BIT 246 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x06c, BIT(16), 0); BIT 248 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x06c, BIT(17), 0); BIT 250 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x06c, BIT(18), 0); BIT 253 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x070, BIT(0), 0); BIT 255 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x070, BIT(7), 0); BIT 263 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 275 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 287 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 301 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 308 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c BIT(31), /* gate */ BIT 314 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); BIT 317 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x0cc, BIT(8), 0); BIT 319 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x0cc, BIT(16), 0); BIT 327 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x100, BIT(0), 0); BIT 329 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x100, BIT(1), 0); BIT 331 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x100, BIT(17), 0); BIT 333 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x100, BIT(18), 0); BIT 337 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x104, 0, 4, 24, 2, BIT(31), BIT 342 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x118, 0, 4, 24, 3, BIT(31), 0); BIT 345 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x130, BIT(31), 0); BIT 350 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x130, 0, 5, 8, 3, BIT(15), 0); BIT 354 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x134, 16, 4, 24, 3, BIT(31), 0); BIT 357 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x134, 0, 5, 8, 3, BIT(15), 0); BIT 360 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x13c, 16, 3, BIT(31), 0); BIT 363 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x140, BIT(31), CLK_SET_RATE_PARENT); BIT 365 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x144, BIT(31), 0); BIT 370 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); BIT 375 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 0x16c, 0, 3, 24, 2, BIT(31), 0); BIT 707 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 709 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_MBUS] = { 0x0fc, BIT(31) }, BIT 711 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_CE] = { 0x2c0, BIT(5) }, BIT 712 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_DMA] = { 0x2c0, BIT(6) }, BIT 713 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, BIT 714 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, BIT 715 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, BIT 716 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, BIT 717 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, BIT 718 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, BIT 719 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, BIT 720 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_OTG] = { 0x2c0, BIT(24) }, BIT 721 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, BIT 722 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, BIT 724 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_VE] = { 0x2c4, BIT(0) }, BIT 725 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, BIT 726 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_CSI] = { 0x2c4, BIT(8) }, BIT 727 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_DE] = { 0x2c4, BIT(12) }, BIT 728 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_DBG] = { 0x2c4, BIT(31) }, BIT 730 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, BIT 732 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, BIT 734 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, BIT 735 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, BIT 736 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_UART0] = { 0x2d8, BIT(16) }, BIT 737 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_UART1] = { 0x2d8, BIT(17) }, BIT 738 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_UART2] = { 0x2d8, BIT(18) }, BIT 742 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 744 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_MBUS] = { 0x0fc, BIT(31) }, BIT 746 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_CE] = { 0x2c0, BIT(5) }, BIT 747 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_DMA] = { 0x2c0, BIT(6) }, BIT 748 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, BIT 749 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, BIT 750 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, BIT 751 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, BIT 752 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, BIT 753 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, BIT 754 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, BIT 755 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_OTG] = { 0x2c0, BIT(24) }, BIT 756 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, BIT 757 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, BIT 759 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_VE] = { 0x2c4, BIT(0) }, BIT 760 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, BIT 761 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_CSI] = { 0x2c4, BIT(8) }, BIT 762 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_DE] = { 0x2c4, BIT(12) }, BIT 763 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_DBG] = { 0x2c4, BIT(31) }, BIT 765 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, BIT 767 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, BIT 768 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, BIT 770 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, BIT 771 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, BIT 772 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_UART0] = { 0x2d8, BIT(16) }, BIT 773 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_UART1] = { 0x2d8, BIT(17) }, BIT 774 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c [RST_BUS_UART2] = { 0x2d8, BIT(18) }, BIT 20 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(0), 0); BIT 22 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(1), 0); BIT 24 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(2), 0); BIT 26 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(4), 0); BIT 28 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(5), 0); BIT 30 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(8), 0); BIT 32 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(9), 0); BIT 34 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(10), 0); BIT 36 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(12), 0); BIT 38 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(13), 0); BIT 40 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x00, BIT(20), 0); BIT 43 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x04, BIT(0), 0); BIT 45 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x04, BIT(1), 0); BIT 47 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x04, BIT(2), 0); BIT 49 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x04, BIT(4), 0); BIT 51 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x04, BIT(5), 0); BIT 53 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x04, BIT(8), 0); BIT 55 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x04, BIT(9), 0); BIT 57 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x04, BIT(10), 0); BIT 59 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x04, BIT(12), 0); BIT 61 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x04, BIT(13), 0); BIT 64 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x08, BIT(0), 0); BIT 66 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x08, BIT(1), 0); BIT 68 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x08, BIT(2), 0); BIT 70 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x08, BIT(4), 0); BIT 72 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x08, BIT(5), 0); BIT 74 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x08, BIT(8), 0); BIT 76 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x08, BIT(9), 0); BIT 78 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x08, BIT(10), 0); BIT 80 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x08, BIT(12), 0); BIT 82 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c 0x08, BIT(13), 0); BIT 181 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_FE0] = { 0x0c, BIT(0) }, BIT 182 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_FE1] = { 0x0c, BIT(1) }, BIT 183 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_FE2] = { 0x0c, BIT(2) }, BIT 184 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_DEU0] = { 0x0c, BIT(4) }, BIT 185 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_DEU1] = { 0x0c, BIT(5) }, BIT 186 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_BE0] = { 0x0c, BIT(8) }, BIT 187 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_BE1] = { 0x0c, BIT(9) }, BIT 188 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_BE2] = { 0x0c, BIT(10) }, BIT 189 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_DRC0] = { 0x0c, BIT(12) }, BIT 190 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_DRC1] = { 0x0c, BIT(13) }, BIT 191 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c [RST_MERGE] = { 0x0c, BIT(20) }, BIT 25 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0); BIT 26 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0); BIT 27 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0); BIT 28 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0); BIT 29 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0); BIT 31 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(usb0_phy_clk, "usb0-phy", clk_parent_hosc, 0x4, BIT(1), 0); BIT 32 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(usb1_hsic_clk, "usb1-hsic", clk_parent_hosc, 0x4, BIT(2), 0); BIT 33 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(usb1_phy_clk, "usb1-phy", clk_parent_hosc, 0x4, BIT(3), 0); BIT 34 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(usb2_hsic_clk, "usb2-hsic", clk_parent_hosc, 0x4, BIT(4), 0); BIT 35 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(usb2_phy_clk, "usb2-phy", clk_parent_hosc, 0x4, BIT(5), 0); BIT 36 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c static SUNXI_CCU_GATE_DATA(usb_hsic_clk, "usb-hsic", clk_parent_hosc, 0x4, BIT(10), 0); BIT 72 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c [RST_USB0_HCI] = { 0x0, BIT(17) }, BIT 73 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c [RST_USB1_HCI] = { 0x0, BIT(18) }, BIT 74 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c [RST_USB2_HCI] = { 0x0, BIT(19) }, BIT 76 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c [RST_USB0_PHY] = { 0x4, BIT(17) }, BIT 77 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c [RST_USB1_HSIC] = { 0x4, BIT(18) }, BIT 78 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c [RST_USB1_PHY] = { 0x4, BIT(19) }, BIT 79 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c [RST_USB2_HSIC] = { 0x4, BIT(20) }, BIT 80 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c [RST_USB2_PHY] = { 0x4, BIT(21) }, BIT 36 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 37 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(0), BIT 50 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 51 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(1), BIT 71 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 72 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(2), BIT 86 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 87 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(3), BIT 102 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 103 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(4), BIT 118 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 119 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(5), BIT 134 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 135 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(6), BIT 149 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 150 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(7), BIT 165 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 166 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(8), BIT 181 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 182 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(9), BIT 197 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 198 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(10), BIT 213 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 214 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .lock = BIT(11), BIT 340 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x080, 0, 3, 24, 2, BIT(31), 0); BIT 343 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x084, 0, 3, 24, 2, BIT(31), 0); BIT 351 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 371 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 397 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 405 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 413 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 421 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 429 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 442 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 455 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 468 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 481 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 488 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 506 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 514 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 522 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 530 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 534 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x440, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 536 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x444, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 538 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x44c, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 552 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 554 drivers/clk/sunxi-ng/ccu-sun9i-a80.c static SUNXI_CCU_GATE(edp_clk, "edp", "osc24M", 0x494, BIT(31), 0); BIT 562 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 573 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 582 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 591 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 601 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 609 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 613 drivers/clk/sunxi-ng/ccu-sun9i-a80.c static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0); BIT 616 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0, 4, BIT(31), 0); BIT 619 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 621 drivers/clk/sunxi-ng/ccu-sun9i-a80.c static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0); BIT 628 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 636 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 645 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 648 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 16, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 650 drivers/clk/sunxi-ng/ccu-sun9i-a80.c static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x4d4, BIT(31), 0); BIT 653 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 655 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0, 3, BIT(31), CLK_SET_RATE_PARENT); BIT 664 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 668 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0, 4, BIT(31), 0); BIT 671 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x504, 0, 4, BIT(31), CLK_SET_RATE_PARENT); BIT 677 drivers/clk/sunxi-ng/ccu-sun9i-a80.c BIT(31), /* gate */ BIT 683 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 699 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .enable = BIT(31), BIT 714 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(0), 0); BIT 716 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(1), 0); BIT 718 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(3), 0); BIT 720 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(5), 0); BIT 722 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(8), 0); BIT 724 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(12), 0); BIT 726 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(13), 0); BIT 728 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(14), 0); BIT 730 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(15), 0); BIT 732 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(16), 0); BIT 734 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(18), 0); BIT 736 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(20), 0); BIT 738 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(21), 0); BIT 740 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(22), 0); BIT 742 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x580, BIT(23), 0); BIT 746 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x584, BIT(0), 0); BIT 748 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x584, BIT(1), 0); BIT 750 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x584, BIT(17), 0); BIT 752 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x584, BIT(21), 0); BIT 754 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x584, BIT(22), 0); BIT 756 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x584, BIT(23), 0); BIT 758 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x584, BIT(24), 0); BIT 762 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x588, BIT(0), 0); BIT 764 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x588, BIT(1), 0); BIT 766 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x588, BIT(2), 0); BIT 768 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x588, BIT(4), 0); BIT 770 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x588, BIT(5), 0); BIT 772 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x588, BIT(7), 0); BIT 774 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x588, BIT(8), 0); BIT 776 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x588, BIT(11), 0); BIT 780 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x590, BIT(1), 0); BIT 782 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x590, BIT(5), 0); BIT 784 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x590, BIT(11), 0); BIT 786 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x590, BIT(12), 0); BIT 788 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x590, BIT(13), 0); BIT 790 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x590, BIT(15), 0); BIT 792 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x590, BIT(17), 0); BIT 794 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x590, BIT(18), 0); BIT 796 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x590, BIT(19), 0); BIT 800 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(0), 0); BIT 802 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(1), 0); BIT 804 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(2), 0); BIT 806 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(3), 0); BIT 808 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(4), 0); BIT 810 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(16), 0); BIT 812 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(17), 0); BIT 814 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(18), 0); BIT 816 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(19), 0); BIT 818 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(20), 0); BIT 820 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 0x594, BIT(21), 0); BIT 1113 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_FD] = { 0x5a0, BIT(0) }, BIT 1114 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_VE] = { 0x5a0, BIT(1) }, BIT 1115 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_GPU_CTRL] = { 0x5a0, BIT(3) }, BIT 1116 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_SS] = { 0x5a0, BIT(5) }, BIT 1117 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_MMC] = { 0x5a0, BIT(8) }, BIT 1118 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_NAND0] = { 0x5a0, BIT(12) }, BIT 1119 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_NAND1] = { 0x5a0, BIT(13) }, BIT 1120 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_SDRAM] = { 0x5a0, BIT(14) }, BIT 1121 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_SATA] = { 0x5a0, BIT(16) }, BIT 1122 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_TS] = { 0x5a0, BIT(18) }, BIT 1123 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_SPI0] = { 0x5a0, BIT(20) }, BIT 1124 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_SPI1] = { 0x5a0, BIT(21) }, BIT 1125 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_SPI2] = { 0x5a0, BIT(22) }, BIT 1126 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_SPI3] = { 0x5a0, BIT(23) }, BIT 1129 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_OTG] = { 0x5a4, BIT(0) }, BIT 1130 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_OTG_PHY] = { 0x5a4, BIT(1) }, BIT 1131 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_MIPI_HSI] = { 0x5a4, BIT(9) }, BIT 1132 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_GMAC] = { 0x5a4, BIT(17) }, BIT 1133 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_MSGBOX] = { 0x5a4, BIT(21) }, BIT 1134 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_SPINLOCK] = { 0x5a4, BIT(22) }, BIT 1135 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_HSTIMER] = { 0x5a4, BIT(23) }, BIT 1136 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_DMA] = { 0x5a4, BIT(24) }, BIT 1139 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_LCD0] = { 0x5a8, BIT(0) }, BIT 1140 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_LCD1] = { 0x5a8, BIT(1) }, BIT 1141 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_EDP] = { 0x5a8, BIT(2) }, BIT 1142 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_LVDS] = { 0x5a8, BIT(3) }, BIT 1143 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_CSI] = { 0x5a8, BIT(4) }, BIT 1144 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_HDMI0] = { 0x5a8, BIT(5) }, BIT 1145 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_HDMI1] = { 0x5a8, BIT(6) }, BIT 1146 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_DE] = { 0x5a8, BIT(7) }, BIT 1147 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_MP] = { 0x5a8, BIT(8) }, BIT 1148 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_GPU] = { 0x5a8, BIT(9) }, BIT 1149 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_MIPI_DSI] = { 0x5a8, BIT(11) }, BIT 1152 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_SPDIF] = { 0x5b0, BIT(1) }, BIT 1153 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_AC97] = { 0x5b0, BIT(11) }, BIT 1154 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_I2S0] = { 0x5b0, BIT(12) }, BIT 1155 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_I2S1] = { 0x5b0, BIT(13) }, BIT 1156 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_LRADC] = { 0x5b0, BIT(15) }, BIT 1157 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_GPADC] = { 0x5b0, BIT(17) }, BIT 1158 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_CIR_TX] = { 0x5b0, BIT(19) }, BIT 1161 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_I2C0] = { 0x5b4, BIT(0) }, BIT 1162 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_I2C1] = { 0x5b4, BIT(1) }, BIT 1163 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_I2C2] = { 0x5b4, BIT(2) }, BIT 1164 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_I2C3] = { 0x5b4, BIT(3) }, BIT 1165 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_I2C4] = { 0x5b4, BIT(4) }, BIT 1166 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_UART0] = { 0x5b4, BIT(16) }, BIT 1167 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_UART1] = { 0x5b4, BIT(17) }, BIT 1168 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_UART2] = { 0x5b4, BIT(18) }, BIT 1169 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_UART3] = { 0x5b4, BIT(19) }, BIT 1170 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_UART4] = { 0x5b4, BIT(20) }, BIT 1171 drivers/clk/sunxi-ng/ccu-sun9i-a80.c [RST_BUS_UART5] = { 0x5b4, BIT(21) }, BIT 1193 drivers/clk/sunxi-ng/ccu-sun9i-a80.c if (!(val & BIT(SUN9I_A80_PLL_P_SHIFT))) BIT 1209 drivers/clk/sunxi-ng/ccu-sun9i-a80.c val &= ~BIT(SUN9I_A80_PLL_P_SHIFT); BIT 1227 drivers/clk/sunxi-ng/ccu-sun9i-a80.c val &= ~(BIT(16) | BIT(18)); BIT 27 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .enable = BIT(31), BIT 28 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .lock = BIT(28), BIT 58 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(31), /* gate */ BIT 59 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(28), /* lock */ BIT 66 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(24), /* frac enable */ BIT 67 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(25), /* frac select */ BIT 70 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(31), /* gate */ BIT 71 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(28), /* lock */ BIT 78 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(24), /* frac enable */ BIT 79 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(25), /* frac select */ BIT 82 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(31), /* gate */ BIT 83 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(28), /* lock */ BIT 91 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(31), /* gate */ BIT 92 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(28), /* lock */ BIT 96 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .enable = BIT(31), BIT 97 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .lock = BIT(28), BIT 149 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x060, BIT(6), 0); BIT 151 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x060, BIT(8), 0); BIT 153 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x060, BIT(9), 0); BIT 155 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x060, BIT(14), 0); BIT 157 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x060, BIT(20), 0); BIT 159 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x060, BIT(21), 0); BIT 161 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x060, BIT(24), 0); BIT 164 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x064, BIT(0), 0); BIT 166 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x064, BIT(4), 0); BIT 168 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x064, BIT(5), 0); BIT 170 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x064, BIT(8), 0); BIT 172 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x064, BIT(9), 0); BIT 174 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x064, BIT(10), 0); BIT 176 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x064, BIT(12), 0); BIT 178 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x064, BIT(14), 0); BIT 181 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(0), 0); BIT 183 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(1), 0); BIT 185 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(2), 0); BIT 187 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(3), 0); BIT 189 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(12), 0); BIT 191 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(16), 0); BIT 193 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(17), 0); BIT 195 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(18), 0); BIT 197 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(19), 0); BIT 199 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(20), 0); BIT 201 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(21), 0); BIT 203 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x068, BIT(22), 0); BIT 210 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(31), /* gate */ BIT 222 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c BIT(31), /* gate */ BIT 236 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x0b0, 16, 2, BIT(31), 0); BIT 239 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x0b4, 16, 2, BIT(31), 0); BIT 244 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x0cc, BIT(1), 0); BIT 247 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x100, BIT(0), 0); BIT 249 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x100, BIT(1), 0); BIT 251 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c "pll-ddr", 0x100, BIT(2), 0); BIT 253 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x100, BIT(3), 0); BIT 255 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x100, BIT(24), 0); BIT 257 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x100, BIT(26), 0); BIT 263 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x104, 0, 4, 24, 3, BIT(31), 0); BIT 267 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x10c, 0, 4, 24, 3, BIT(31), 0); BIT 273 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x118, 24, 3, BIT(31), BIT 281 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x11c, 0, 4, 24, 3, BIT(31), 0); BIT 288 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x120, 0, 4, 24, 3, BIT(31), 0); BIT 290 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x120, 8, 1, BIT(15), 0); BIT 295 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x124, 0, 4, 24, 3, BIT(31), 0); BIT 300 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 0x120, 0, 4, 8, 3, BIT(15), 0); BIT 306 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0); BIT 308 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0); BIT 310 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); BIT 471 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_USB_PHY0] = { 0x0cc, BIT(0) }, BIT 473 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_DMA] = { 0x2c0, BIT(6) }, BIT 474 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, BIT 475 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, BIT 476 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, BIT 477 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, BIT 478 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, BIT 479 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_OTG] = { 0x2c0, BIT(24) }, BIT 480 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_VE] = { 0x2c4, BIT(0) }, BIT 481 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_LCD] = { 0x2c4, BIT(4) }, BIT 482 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, BIT 483 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_CSI] = { 0x2c4, BIT(8) }, BIT 484 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_TVD] = { 0x2c4, BIT(9) }, BIT 485 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_TVE] = { 0x2c4, BIT(10) }, BIT 486 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, BIT 487 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, BIT 488 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, BIT 489 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, BIT 490 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_IR] = { 0x2d0, BIT(2) }, BIT 491 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_RSB] = { 0x2d0, BIT(3) }, BIT 492 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, BIT 493 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_I2C0] = { 0x2d0, BIT(16) }, BIT 494 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_I2C1] = { 0x2d0, BIT(17) }, BIT 495 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_I2C2] = { 0x2d0, BIT(18) }, BIT 496 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_UART0] = { 0x2d0, BIT(20) }, BIT 497 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_UART1] = { 0x2d0, BIT(21) }, BIT 498 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c [RST_BUS_UART2] = { 0x2d0, BIT(22) }, BIT 514 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .enable = BIT(31), BIT 515 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .lock = BIT(28), BIT 12 drivers/clk/sunxi-ng/ccu_common.h #define CCU_FEATURE_FRACTIONAL BIT(0) BIT 13 drivers/clk/sunxi-ng/ccu_common.h #define CCU_FEATURE_VARIABLE_PREDIV BIT(1) BIT 14 drivers/clk/sunxi-ng/ccu_common.h #define CCU_FEATURE_FIXED_PREDIV BIT(2) BIT 15 drivers/clk/sunxi-ng/ccu_common.h #define CCU_FEATURE_FIXED_POSTDIV BIT(3) BIT 16 drivers/clk/sunxi-ng/ccu_common.h #define CCU_FEATURE_ALL_PREDIV BIT(4) BIT 17 drivers/clk/sunxi-ng/ccu_common.h #define CCU_FEATURE_LOCK_REG BIT(5) BIT 18 drivers/clk/sunxi-ng/ccu_common.h #define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6) BIT 19 drivers/clk/sunxi-ng/ccu_common.h #define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7) BIT 22 drivers/clk/sunxi-ng/ccu_common.h #define CCU_MMC_NEW_TIMING_MODE BIT(30) BIT 106 drivers/clk/sunxi-ng/ccu_mp.h .enable = BIT(31), \ BIT 51 drivers/clk/sunxi/clk-a10-mod1.c mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1; BIT 45 drivers/clk/sunxi/clk-a10-ve.c writel(reg & ~BIT(SUN4I_VE_RESET), data->reg); BIT 64 drivers/clk/sunxi/clk-a10-ve.c writel(reg | BIT(SUN4I_VE_RESET), data->reg); BIT 61 drivers/clk/sunxi/clk-mod0.c .muxmask = BIT(1) | BIT(0), BIT 124 drivers/clk/sunxi/clk-mod0.c .muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT 56 drivers/clk/sunxi/clk-sun4i-display.c writel(reg & ~BIT(data->offset + id), data->reg); BIT 73 drivers/clk/sunxi/clk-sun4i-display.c writel(reg | BIT(data->offset + id), data->reg); BIT 85 drivers/clk/sunxi/clk-sun4i-display.c return !(readl(data->reg) & BIT(data->offset + id)); BIT 17 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c #define TCON_CH1_SCLK2_GATE_BIT BIT(31) BIT 23 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c #define TCON_CH1_SCLK1_GATE_BIT BIT(15) BIT 24 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c #define TCON_CH1_SCLK1_HALF_BIT BIT(11) BIT 123 drivers/clk/sunxi/clk-sun9i-core.c .muxmask = BIT(1) | BIT(0), BIT 178 drivers/clk/sunxi/clk-sun9i-core.c .muxmask = BIT(1) | BIT(0), BIT 204 drivers/clk/sunxi/clk-sun9i-core.c .muxmask = BIT(0), BIT 261 drivers/clk/sunxi/clk-sun9i-core.c .muxmask = BIT(0), BIT 49 drivers/clk/sunxi/clk-sun9i-mmc.c writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg); BIT 71 drivers/clk/sunxi/clk-sun9i-mmc.c writel(val | BIT(SUN9I_MMC_RESET_BIT), reg); BIT 528 drivers/clk/sunxi/clk-sunxi.c .muxmask = BIT(1) | BIT(0), BIT 535 drivers/clk/sunxi/clk-sunxi.c .muxmask = BIT(1) | BIT(0), BIT 543 drivers/clk/sunxi/clk-sunxi.c .muxmask = BIT(1) | BIT(0), BIT 551 drivers/clk/sunxi/clk-sunxi.c .muxmask = BIT(1) | BIT(0), BIT 1157 drivers/clk/sunxi/clk-sunxi.c .muxmask = BIT(2) | BIT(1) | BIT(0), BIT 42 drivers/clk/sunxi/clk-usb.c writel(reg & ~BIT(id), data->reg); BIT 63 drivers/clk/sunxi/clk-usb.c writel(reg | BIT(id), data->reg); BIT 166 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(8) | BIT(7) | BIT(6), BIT 167 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(2) | BIT(1) | BIT(0), BIT 179 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(8) | BIT(6), BIT 180 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(1) | BIT(0), BIT 190 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8), BIT 191 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(2) | BIT(1) | BIT(0), BIT 201 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(16) | BIT(11) | BIT(10) | BIT(9) | BIT(8), BIT 202 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(2) | BIT(1) | BIT(0), BIT 212 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT 213 drivers/clk/sunxi/clk-usb.c BIT(11) | BIT(10) | BIT(9) | BIT(8), BIT 214 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT 224 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1), BIT 225 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(19) | BIT(18) | BIT(17), BIT 238 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(10) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1), BIT 239 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17), BIT 16 drivers/clk/tegra/clk-bpmp.c #define TEGRA_BPMP_CLK_HAS_MUX BIT(0) BIT 17 drivers/clk/tegra/clk-bpmp.c #define TEGRA_BPMP_CLK_HAS_SET_RATE BIT(1) BIT 18 drivers/clk/tegra/clk-bpmp.c #define TEGRA_BPMP_CLK_IS_ROOT BIT(2) BIT 14 drivers/clk/tegra/clk-divider.c #define pll_out_override(p) (BIT((p->shift - 6))) BIT 19 drivers/clk/tegra/clk-divider.c #define PERIPH_CLK_UART_DIV_ENB BIT(24) BIT 77 drivers/clk/tegra/clk-periph-gate.c writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); BIT 15 drivers/clk/tegra/clk-pll-out.c #define pll_out_enb(p) (BIT(p->enb_bit_idx)) BIT 16 drivers/clk/tegra/clk-pll-out.c #define pll_out_rst(p) (BIT(p->rst_bit_idx)) BIT 15 drivers/clk/tegra/clk-pll.c #define PLL_BASE_BYPASS BIT(31) BIT 16 drivers/clk/tegra/clk-pll.c #define PLL_BASE_ENABLE BIT(30) BIT 17 drivers/clk/tegra/clk-pll.c #define PLL_BASE_REF_ENABLE BIT(29) BIT 18 drivers/clk/tegra/clk-pll.c #define PLL_BASE_OVERRIDE BIT(28) BIT 42 drivers/clk/tegra/clk-pll.c #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) BIT 43 drivers/clk/tegra/clk-pll.c #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) BIT 57 drivers/clk/tegra/clk-pll.c #define PLLE_BASE_ENABLE BIT(31) BIT 61 drivers/clk/tegra/clk-pll.c #define PLLE_MISC_LOCK_ENABLE BIT(9) BIT 62 drivers/clk/tegra/clk-pll.c #define PLLE_MISC_READY BIT(15) BIT 70 drivers/clk/tegra/clk-pll.c #define PLLE_SS_CNTL_BYPASS_SS BIT(10) BIT 71 drivers/clk/tegra/clk-pll.c #define PLLE_SS_CNTL_INTERP_RESET BIT(11) BIT 72 drivers/clk/tegra/clk-pll.c #define PLLE_SS_CNTL_SSC_BYP BIT(12) BIT 73 drivers/clk/tegra/clk-pll.c #define PLLE_SS_CNTL_CENTER BIT(14) BIT 74 drivers/clk/tegra/clk-pll.c #define PLLE_SS_CNTL_INVERT BIT(15) BIT 94 drivers/clk/tegra/clk-pll.c #define PLLE_AUX_PLLP_SEL BIT(2) BIT 95 drivers/clk/tegra/clk-pll.c #define PLLE_AUX_USE_LOCKDET BIT(3) BIT 96 drivers/clk/tegra/clk-pll.c #define PLLE_AUX_ENABLE_SWCTL BIT(4) BIT 97 drivers/clk/tegra/clk-pll.c #define PLLE_AUX_SS_SWCTL BIT(6) BIT 98 drivers/clk/tegra/clk-pll.c #define PLLE_AUX_SEQ_ENABLE BIT(24) BIT 99 drivers/clk/tegra/clk-pll.c #define PLLE_AUX_SEQ_START_STATE BIT(25) BIT 100 drivers/clk/tegra/clk-pll.c #define PLLE_AUX_PLLRE_SEL BIT(28) BIT 101 drivers/clk/tegra/clk-pll.c #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31) BIT 104 drivers/clk/tegra/clk-pll.c #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) BIT 105 drivers/clk/tegra/clk-pll.c #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) BIT 106 drivers/clk/tegra/clk-pll.c #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) BIT 107 drivers/clk/tegra/clk-pll.c #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) BIT 108 drivers/clk/tegra/clk-pll.c #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) BIT 111 drivers/clk/tegra/clk-pll.c #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) BIT 112 drivers/clk/tegra/clk-pll.c #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) BIT 113 drivers/clk/tegra/clk-pll.c #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) BIT 114 drivers/clk/tegra/clk-pll.c #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25) BIT 116 drivers/clk/tegra/clk-pll.c #define PLLE_MISC_PLLE_PTS BIT(8) BIT 117 drivers/clk/tegra/clk-pll.c #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) BIT 118 drivers/clk/tegra/clk-pll.c #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) BIT 124 drivers/clk/tegra/clk-pll.c #define PLLCX_MISC_STROBE BIT(31) BIT 125 drivers/clk/tegra/clk-pll.c #define PLLCX_MISC_RESET BIT(30) BIT 150 drivers/clk/tegra/clk-pll.c #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) BIT 151 drivers/clk/tegra/clk-pll.c #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) BIT 179 drivers/clk/tegra/clk-pll.c #define PLLSS_LOCK_OVERRIDE BIT(24) BIT 186 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) BIT 187 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) BIT 188 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) BIT 189 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) BIT 190 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) BIT 195 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) BIT 196 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1) BIT 197 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) BIT 198 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3) BIT 199 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) BIT 200 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5) BIT 201 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24) BIT 202 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25) BIT 203 drivers/clk/tegra/clk-pll.c #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30) BIT 206 drivers/clk/tegra/clk-pll.c #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) BIT 207 drivers/clk/tegra/clk-pll.c #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) BIT 208 drivers/clk/tegra/clk-pll.c #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) BIT 209 drivers/clk/tegra/clk-pll.c #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) BIT 210 drivers/clk/tegra/clk-pll.c #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) BIT 211 drivers/clk/tegra/clk-pll.c #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) BIT 212 drivers/clk/tegra/clk-pll.c #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) BIT 213 drivers/clk/tegra/clk-pll.c #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) BIT 216 drivers/clk/tegra/clk-pll.c #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0) BIT 217 drivers/clk/tegra/clk-pll.c #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) BIT 218 drivers/clk/tegra/clk-pll.c #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) BIT 219 drivers/clk/tegra/clk-pll.c #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7) BIT 220 drivers/clk/tegra/clk-pll.c #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) BIT 221 drivers/clk/tegra/clk-pll.c #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28) BIT 227 drivers/clk/tegra/clk-pll.c #define PLLU_BASE_CLKENABLE_USB BIT(21) BIT 228 drivers/clk/tegra/clk-pll.c #define PLLU_BASE_OVERRIDE BIT(24) BIT 287 drivers/clk/tegra/clk-pll.c val |= BIT(pll->params->lock_enable_bit_idx); BIT 353 drivers/clk/tegra/clk-pll.c val &= ~BIT(pll->params->iddq_bit_idx); BIT 360 drivers/clk/tegra/clk-pll.c val &= ~BIT(pll->params->reset_bit_idx); BIT 398 drivers/clk/tegra/clk-pll.c val |= BIT(pll->params->reset_bit_idx); BIT 404 drivers/clk/tegra/clk-pll.c val |= BIT(pll->params->iddq_bit_idx); BIT 1584 drivers/clk/tegra/clk-pll.c val &= ~BIT(29); /* Disable lock override */ BIT 2024 drivers/clk/tegra/clk-pll.c WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); BIT 2026 drivers/clk/tegra/clk-pll.c val_iddq |= BIT(pll_params->iddq_bit_idx); BIT 2069 drivers/clk/tegra/clk-pll.c BIT(pll_params->iddq_bit_idx)); BIT 2082 drivers/clk/tegra/clk-pll.c val &= ~BIT(29); BIT 2339 drivers/clk/tegra/clk-pll.c if (val_iddq & BIT(pll_params->iddq_bit_idx)) { BIT 2345 drivers/clk/tegra/clk-pll.c val_iddq |= BIT(pll_params->iddq_bit_idx); BIT 2425 drivers/clk/tegra/clk-pll.c val &= ~BIT(30); /* Disable lock override */ BIT 21 drivers/clk/tegra/clk-super.c #define SUPER_STATE_MASK ((BIT(SUPER_STATE_IDLE) | BIT(SUPER_STATE_RUN) | \ BIT 22 drivers/clk/tegra/clk-super.c BIT(SUPER_STATE_IRQ) | BIT(SUPER_STATE_FIQ)) \ BIT 27 drivers/clk/tegra/clk-super.c #define super_state(s) (BIT(s) << SUPER_STATE_SHIFT) BIT 130 drivers/clk/tegra/clk-tegra-periph.c #define MASK(x) (BIT(x) - 1) BIT 259 drivers/clk/tegra/clk-tegra-periph.c #define PLL_BASE_LOCK BIT(27) BIT 27 drivers/clk/tegra/clk-tegra114.c #define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */ BIT 28 drivers/clk/tegra/clk-tegra114.c #define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */ BIT 29 drivers/clk/tegra/clk-tegra114.c #define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */ BIT 30 drivers/clk/tegra/clk-tegra114.c #define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */ BIT 31 drivers/clk/tegra/clk-tegra114.c #define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */ BIT 32 drivers/clk/tegra/clk-tegra114.c #define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */ BIT 88 drivers/clk/tegra/clk-tegra114.c #define PLL_BASE_LOCK BIT(27) BIT 89 drivers/clk/tegra/clk-tegra114.c #define PLLE_MISC_LOCK BIT(11) BIT 90 drivers/clk/tegra/clk-tegra114.c #define PLLRE_MISC_LOCK BIT(24) BIT 91 drivers/clk/tegra/clk-tegra114.c #define PLLCX_BASE_LOCK (BIT(26)|BIT(27)) BIT 613 drivers/clk/tegra/clk-tegra114.c #define MASK(x) (BIT(x) - 1) BIT 73 drivers/clk/tegra/clk-tegra124.c #define PLL_BASE_LOCK BIT(27) BIT 74 drivers/clk/tegra/clk-tegra124.c #define PLLE_MISC_LOCK BIT(11) BIT 75 drivers/clk/tegra/clk-tegra124.c #define PLLRE_MISC_LOCK BIT(24) BIT 1458 drivers/clk/tegra/clk-tegra124.c plld_base &= ~BIT(25); BIT 61 drivers/clk/tegra/clk-tegra20.c #define PLL_BASE_LOCK BIT(27) BIT 62 drivers/clk/tegra/clk-tegra20.c #define PLLE_MISC_LOCK BIT(11) BIT 792 drivers/clk/tegra/clk-tegra20.c const u32 use_pllm_ud = BIT(29); BIT 120 drivers/clk/tegra/clk-tegra210.c #define PLL_BASE_LOCK BIT(27) BIT 121 drivers/clk/tegra/clk-tegra210.c #define PLLCX_BASE_LOCK BIT(26) BIT 122 drivers/clk/tegra/clk-tegra210.c #define PLLE_MISC_LOCK BIT(11) BIT 123 drivers/clk/tegra/clk-tegra210.c #define PLLRE_MISC_LOCK BIT(27) BIT 140 drivers/clk/tegra/clk-tegra210.c #define PLLA_SDM_EN_MASK BIT(26) BIT 142 drivers/clk/tegra/clk-tegra210.c #define PLLD_SDM_EN_MASK BIT(16) BIT 144 drivers/clk/tegra/clk-tegra210.c #define PLLD2_SDM_EN_MASK BIT(31) BIT 148 drivers/clk/tegra/clk-tegra210.c #define PLLDP_SDM_EN_MASK BIT(31) BIT 149 drivers/clk/tegra/clk-tegra210.c #define PLLDP_SSC_EN_MASK BIT(30) BIT 159 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) BIT 160 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1) BIT 161 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) BIT 162 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3) BIT 163 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) BIT 164 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5) BIT 165 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24) BIT 166 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25) BIT 171 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) BIT 172 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) BIT 173 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) BIT 174 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) BIT 175 drivers/clk/tegra/clk-tegra210.c #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) BIT 178 drivers/clk/tegra/clk-tegra210.c #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) BIT 179 drivers/clk/tegra/clk-tegra210.c #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) BIT 180 drivers/clk/tegra/clk-tegra210.c #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4) BIT 181 drivers/clk/tegra/clk-tegra210.c #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5) BIT 182 drivers/clk/tegra/clk-tegra210.c #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6) BIT 183 drivers/clk/tegra/clk-tegra210.c #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7) BIT 185 drivers/clk/tegra/clk-tegra210.c #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) BIT 186 drivers/clk/tegra/clk-tegra210.c #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) BIT 189 drivers/clk/tegra/clk-tegra210.c #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) BIT 190 drivers/clk/tegra/clk-tegra210.c #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) BIT 191 drivers/clk/tegra/clk-tegra210.c #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) BIT 192 drivers/clk/tegra/clk-tegra210.c #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) BIT 193 drivers/clk/tegra/clk-tegra210.c #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) BIT 196 drivers/clk/tegra/clk-tegra210.c #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31) BIT 197 drivers/clk/tegra/clk-tegra210.c #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) BIT 198 drivers/clk/tegra/clk-tegra210.c #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) BIT 199 drivers/clk/tegra/clk-tegra210.c #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7) BIT 200 drivers/clk/tegra/clk-tegra210.c #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) BIT 201 drivers/clk/tegra/clk-tegra210.c #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) BIT 202 drivers/clk/tegra/clk-tegra210.c #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) BIT 203 drivers/clk/tegra/clk-tegra210.c #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) BIT 204 drivers/clk/tegra/clk-tegra210.c #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) BIT 205 drivers/clk/tegra/clk-tegra210.c #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) BIT 208 drivers/clk/tegra/clk-tegra210.c #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28) BIT 209 drivers/clk/tegra/clk-tegra210.c #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) BIT 210 drivers/clk/tegra/clk-tegra210.c #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7) BIT 211 drivers/clk/tegra/clk-tegra210.c #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) BIT 212 drivers/clk/tegra/clk-tegra210.c #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) BIT 213 drivers/clk/tegra/clk-tegra210.c #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0) BIT 261 drivers/clk/tegra/clk-tegra210.c #define PLL_SDM_COEFF BIT(13) BIT 575 drivers/clk/tegra/clk-tegra210.c writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA); BIT 577 drivers/clk/tegra/clk-tegra210.c writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE); BIT 593 drivers/clk/tegra/clk-tegra210.c writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA); BIT 597 drivers/clk/tegra/clk-tegra210.c writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL); BIT 611 drivers/clk/tegra/clk-tegra210.c writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE); BIT 615 drivers/clk/tegra/clk-tegra210.c writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24), BIT 634 drivers/clk/tegra/clk-tegra210.c writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC); BIT 635 drivers/clk/tegra/clk-tegra210.c writel_relaxed(ovre | BIT(10) | BIT(11), BIT 645 drivers/clk/tegra/clk-tegra210.c writel_relaxed(i2s_ctrl | BIT(10), BIT 2596 drivers/clk/tegra/clk-tegra210.c .lvl2_mask = BIT(0) | BIT(17) | BIT(19), BIT 2601 drivers/clk/tegra/clk-tegra210.c .lvl2_mask = BIT(29), BIT 2608 drivers/clk/tegra/clk-tegra210.c .lvl2_mask = BIT(1) | BIT(2), BIT 2620 drivers/clk/tegra/clk-tegra210.c .lvl2_mask = BIT(2), BIT 2627 drivers/clk/tegra/clk-tegra210.c .lvl2_mask = BIT(30) | BIT(31), BIT 2634 drivers/clk/tegra/clk-tegra210.c .lvl2_mask = BIT(30) | BIT(31), BIT 2641 drivers/clk/tegra/clk-tegra210.c .lvl2_mask = BIT(30) | BIT(31), BIT 2653 drivers/clk/tegra/clk-tegra210.c .lvl2_mask = BIT(9) | BIT(31), BIT 2660 drivers/clk/tegra/clk-tegra210.c .lvl2_mask = BIT(9) | BIT(31), BIT 2670 drivers/clk/tegra/clk-tegra210.c .lvl2_mask = BIT(22), BIT 2842 drivers/clk/tegra/clk-tegra210.c reg &= ~BIT(pllu.params->iddq_bit_idx); BIT 3439 drivers/clk/tegra/clk-tegra210.c writel(GENMASK(26, 21) | BIT(7), BIT 3452 drivers/clk/tegra/clk-tegra210.c writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); BIT 3459 drivers/clk/tegra/clk-tegra210.c writel(GENMASK(26, 22) | BIT(7), BIT 3573 drivers/clk/tegra/clk-tegra210.c value &= ~BIT(25); BIT 38 drivers/clk/tegra/clk-tegra30.c #define OSC_FREQ_DET_TRIG BIT(31) BIT 41 drivers/clk/tegra/clk-tegra30.c #define OSC_FREQ_DET_BUSY BIT(31) BIT 78 drivers/clk/tegra/clk-tegra30.c #define PLL_BASE_LOCK BIT(27) BIT 79 drivers/clk/tegra/clk-tegra30.c #define PLLE_MISC_LOCK BIT(11) BIT 152 drivers/clk/tegra/clk.c writel_relaxed(BIT(id % 32), BIT 166 drivers/clk/tegra/clk.c writel_relaxed(BIT(id % 32), BIT 69 drivers/clk/tegra/clk.h #define TEGRA_DIVIDER_ROUND_UP BIT(0) BIT 70 drivers/clk/tegra/clk.h #define TEGRA_DIVIDER_FIXED BIT(1) BIT 71 drivers/clk/tegra/clk.h #define TEGRA_DIVIDER_INT BIT(2) BIT 72 drivers/clk/tegra/clk.h #define TEGRA_DIVIDER_UART BIT(3) BIT 288 drivers/clk/tegra/clk.h #define TEGRA_PLL_USE_LOCK BIT(0) BIT 289 drivers/clk/tegra/clk.h #define TEGRA_PLL_HAS_CPCON BIT(1) BIT 290 drivers/clk/tegra/clk.h #define TEGRA_PLL_SET_LFCON BIT(2) BIT 291 drivers/clk/tegra/clk.h #define TEGRA_PLL_SET_DCCON BIT(3) BIT 292 drivers/clk/tegra/clk.h #define TEGRA_PLLU BIT(4) BIT 293 drivers/clk/tegra/clk.h #define TEGRA_PLLM BIT(5) BIT 294 drivers/clk/tegra/clk.h #define TEGRA_PLL_FIXED BIT(6) BIT 295 drivers/clk/tegra/clk.h #define TEGRA_PLLE_CONFIGURE BIT(7) BIT 296 drivers/clk/tegra/clk.h #define TEGRA_PLL_LOCK_MISC BIT(8) BIT 297 drivers/clk/tegra/clk.h #define TEGRA_PLL_BYPASS BIT(9) BIT 298 drivers/clk/tegra/clk.h #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) BIT 299 drivers/clk/tegra/clk.h #define TEGRA_MDIV_NEW BIT(11) BIT 300 drivers/clk/tegra/clk.h #define TEGRA_PLLMB BIT(12) BIT 301 drivers/clk/tegra/clk.h #define TEGRA_PLL_VCO_OUT BIT(13) BIT 514 drivers/clk/tegra/clk.h #define TEGRA_PERIPH_NO_RESET BIT(0) BIT 515 drivers/clk/tegra/clk.h #define TEGRA_PERIPH_MANUAL_RESET BIT(1) BIT 516 drivers/clk/tegra/clk.h #define TEGRA_PERIPH_ON_APB BIT(2) BIT 517 drivers/clk/tegra/clk.h #define TEGRA_PERIPH_WAR_1005168 BIT(3) BIT 518 drivers/clk/tegra/clk.h #define TEGRA_PERIPH_NO_DIV BIT(4) BIT 519 drivers/clk/tegra/clk.h #define TEGRA_PERIPH_NO_GATE BIT(5) BIT 650 drivers/clk/tegra/clk.h _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ BIT 687 drivers/clk/tegra/clk.h #define TEGRA_DIVIDER_2 BIT(0) BIT 88 drivers/clk/ti/adpll.c #define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \ BIT 89 drivers/clk/ti/adpll.c BIT(ADPLL_STATUS_FREQLOCK)) BIT 368 drivers/clk/ti/adpll.c v |= BIT(ADPLL_CLKCTRL_IDLE); BIT 380 drivers/clk/ti/adpll.c v &= ~BIT(ADPLL_CLKCTRL_IDLE); BIT 391 drivers/clk/ti/adpll.c return v & BIT(ADPLL_STATUS_BYPASS); BIT 476 drivers/clk/ti/adpll.c if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S)) BIT 41 drivers/clk/ti/clk-dra7-atl.c #define DRA7_ATL_SWEN BIT(0) BIT 43 drivers/clk/ti/clk-dra7-atl.c #define DRA7_ATL_PCLKMUX BIT(0) BIT 287 drivers/clk/ti/clkt_dflt.c v ^= BIT(clk->enable_bit); BIT 289 drivers/clk/ti/clkt_dflt.c v &= BIT(clk->enable_bit); BIT 82 drivers/clk/ti/clock.h #define CLKF_SW_SUP BIT(5) BIT 83 drivers/clk/ti/clock.h #define CLKF_HW_SUP BIT(6) BIT 84 drivers/clk/ti/clock.h #define CLKF_NO_IDLEST BIT(7) BIT 88 drivers/clk/ti/clock.h #define CLKF_SOC_NONSEC BIT(8) BIT 89 drivers/clk/ti/clock.h #define CLKF_SOC_DRA72 BIT(9) BIT 90 drivers/clk/ti/clock.h #define CLKF_SOC_DRA74 BIT(10) BIT 91 drivers/clk/ti/clock.h #define CLKF_SOC_DRA76 BIT(11) BIT 508 drivers/clk/ti/dpll.c .dcc_mask = BIT(22), BIT 30 drivers/clk/ti/dpll44xx.c #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BIT(8) BIT 31 drivers/clk/ti/dpll44xx.c #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BIT(10) BIT 32 drivers/clk/ti/dpll44xx.c #define OMAP4430_DPLL_REGM4XEN_MASK BIT(11) BIT 25 drivers/clk/ti/fapll.c #define FAPLL_MAIN_LOCK BIT(7) BIT 26 drivers/clk/ti/fapll.c #define FAPLL_MAIN_PLLEN BIT(3) BIT 27 drivers/clk/ti/fapll.c #define FAPLL_MAIN_BP BIT(2) BIT 28 drivers/clk/ti/fapll.c #define FAPLL_MAIN_LOC_CTL BIT(0) BIT 57 drivers/clk/ti/fapll.c #define SYNTH_LDMDIV1 BIT(8) BIT 60 drivers/clk/ti/fapll.c #define SYNTH_LDFREQ BIT(31) BIT 16 drivers/clk/uniphier/clk-uniphier-cpugear.c #define UNIPHIER_CLK_CPUGEAR_UPD_BIT BIT(0) BIT 27 drivers/clk/uniphier/clk-uniphier-gate.c return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit), BIT 28 drivers/clk/uniphier/clk-uniphier-gate.c enable ? BIT(gate->bit) : 0); BIT 50 drivers/clk/uniphier/clk-uniphier-gate.c return !!(val & BIT(gate->bit)); BIT 254 drivers/clk/ux500/u8500_of_clk.c BIT(0), 0); BIT 258 drivers/clk/ux500/u8500_of_clk.c BIT(1), 0); BIT 262 drivers/clk/ux500/u8500_of_clk.c BIT(2), 0); BIT 266 drivers/clk/ux500/u8500_of_clk.c BIT(3), 0); BIT 270 drivers/clk/ux500/u8500_of_clk.c BIT(4), 0); BIT 274 drivers/clk/ux500/u8500_of_clk.c BIT(5), 0); BIT 278 drivers/clk/ux500/u8500_of_clk.c BIT(6), 0); BIT 282 drivers/clk/ux500/u8500_of_clk.c BIT(7), 0); BIT 286 drivers/clk/ux500/u8500_of_clk.c BIT(8), 0); BIT 290 drivers/clk/ux500/u8500_of_clk.c BIT(9), 0); BIT 294 drivers/clk/ux500/u8500_of_clk.c BIT(10), 0); BIT 298 drivers/clk/ux500/u8500_of_clk.c BIT(11), 0); BIT 302 drivers/clk/ux500/u8500_of_clk.c BIT(0), 0); BIT 306 drivers/clk/ux500/u8500_of_clk.c BIT(1), 0); BIT 310 drivers/clk/ux500/u8500_of_clk.c BIT(2), 0); BIT 314 drivers/clk/ux500/u8500_of_clk.c BIT(3), 0); BIT 318 drivers/clk/ux500/u8500_of_clk.c BIT(4), 0); BIT 322 drivers/clk/ux500/u8500_of_clk.c BIT(5), 0); BIT 326 drivers/clk/ux500/u8500_of_clk.c BIT(6), 0); BIT 330 drivers/clk/ux500/u8500_of_clk.c BIT(7), 0); BIT 334 drivers/clk/ux500/u8500_of_clk.c BIT(8), 0); BIT 338 drivers/clk/ux500/u8500_of_clk.c BIT(9), 0); BIT 342 drivers/clk/ux500/u8500_of_clk.c BIT(10), 0); BIT 346 drivers/clk/ux500/u8500_of_clk.c BIT(11), 0); BIT 350 drivers/clk/ux500/u8500_of_clk.c BIT(12), 0); BIT 354 drivers/clk/ux500/u8500_of_clk.c BIT(0), 0); BIT 358 drivers/clk/ux500/u8500_of_clk.c BIT(1), 0); BIT 362 drivers/clk/ux500/u8500_of_clk.c BIT(2), 0); BIT 366 drivers/clk/ux500/u8500_of_clk.c BIT(3), 0); BIT 370 drivers/clk/ux500/u8500_of_clk.c BIT(4), 0); BIT 374 drivers/clk/ux500/u8500_of_clk.c BIT(5), 0); BIT 378 drivers/clk/ux500/u8500_of_clk.c BIT(6), 0); BIT 382 drivers/clk/ux500/u8500_of_clk.c BIT(7), 0); BIT 386 drivers/clk/ux500/u8500_of_clk.c BIT(8), 0); BIT 390 drivers/clk/ux500/u8500_of_clk.c BIT(0), 0); BIT 394 drivers/clk/ux500/u8500_of_clk.c BIT(1), 0); BIT 398 drivers/clk/ux500/u8500_of_clk.c BIT(0), 0); BIT 402 drivers/clk/ux500/u8500_of_clk.c BIT(1), 0); BIT 406 drivers/clk/ux500/u8500_of_clk.c BIT(2), 0); BIT 410 drivers/clk/ux500/u8500_of_clk.c BIT(3), 0); BIT 414 drivers/clk/ux500/u8500_of_clk.c BIT(4), 0); BIT 418 drivers/clk/ux500/u8500_of_clk.c BIT(5), 0); BIT 422 drivers/clk/ux500/u8500_of_clk.c BIT(6), 0); BIT 426 drivers/clk/ux500/u8500_of_clk.c BIT(7), 0); BIT 439 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE); BIT 443 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE); BIT 447 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE); BIT 451 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE); BIT 455 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE); BIT 459 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE); BIT 463 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE); BIT 467 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE); BIT 471 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE); BIT 475 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE); BIT 480 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE); BIT 484 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE); BIT 488 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE); BIT 492 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE); BIT 496 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE); BIT 501 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(6), BIT 506 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST2_INDEX], BIT(7), BIT 512 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE); BIT 516 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE); BIT 520 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE); BIT 524 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE); BIT 528 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE); BIT 532 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE); BIT 536 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE); BIT 541 drivers/clk/ux500/u8500_of_clk.c bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE); BIT 34 drivers/clk/versatile/clk-icst.c #define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8) BIT 27 drivers/clk/x86/clk-pmc-atom.c #define PMC_MASK_CLK_FREQ BIT(2) BIT 51 drivers/clk/zte/clk.c hw_cfg0 &= ~BIT(zx_pll->lock_bit); BIT 55 drivers/clk/zte/clk.c hw_cfg0 |= BIT(zx_pll->pd_bit); BIT 116 drivers/clk/zte/clk.c writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); BIT 119 drivers/clk/zte/clk.c reg & BIT(zx_pll->lock_bit), 0, 100); BIT 131 drivers/clk/zte/clk.c writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); BIT 141 drivers/clk/zte/clk.c return !(reg & BIT(zx_pll->pd_bit)); BIT 208 drivers/clk/zte/clk.c tmp |= BIT(28); BIT 218 drivers/clk/zte/clk.c sel = (tmp >> 24) & BIT(0); BIT 265 drivers/clk/zte/clk.c #define ZX_AUDIO_EN BIT(25) BIT 322 drivers/clk/zte/clk.c #define CLK_AUDIO_DIV_FRAC BIT(0) BIT 323 drivers/clk/zte/clk.c #define CLK_AUDIO_DIV_INT BIT(1) BIT 324 drivers/clk/zte/clk.c #define CLK_AUDIO_DIV_UNCOMMON BIT(1) BIT 327 drivers/clk/zte/clk.c #define CLK_AUDIO_DIV_INT_FRAC_RE BIT(16) BIT 102 drivers/clk/zte/clk.h .mask = BIT(_width) - 1, \ BIT 46 drivers/clk/zynq/clkc.c #define DBG_CLK_CTRL_CLKACT_TRC BIT(0) BIT 47 drivers/clk/zynq/clkc.c #define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1) BIT 354 drivers/clk/zynq/clkc.c int enable = !!(fclk_enable & BIT(i - fclk0)); BIT 101 drivers/clk/zynqmp/clkc.c #define CLK_ATTR_VALID BIT(0) BIT 102 drivers/clk/zynqmp/clkc.c #define CLK_ATTR_TYPE BIT(2) BIT 28 drivers/clk/zynqmp/divider.c #define CLK_FRAC BIT(13) /* has a fractional parent */ BIT 37 drivers/clk/zynqmp/pll.c #define PLLFCFG_FRAC_EN BIT(31) BIT 38 drivers/clk/zynqmp/pll.c #define FRAC_DIV BIT(16) /* 2^16 */ BIT 143 drivers/clocksource/arc_timer.c } while (!(status & BIT(31))); BIT 34 drivers/clocksource/arm_arch_timer.c #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) BIT 37 drivers/clocksource/arm_arch_timer.c #define CNTACR_RPCT BIT(0) BIT 38 drivers/clocksource/arm_arch_timer.c #define CNTACR_RVCT BIT(1) BIT 39 drivers/clocksource/arm_arch_timer.c #define CNTACR_RFRQ BIT(2) BIT 40 drivers/clocksource/arm_arch_timer.c #define CNTACR_RVOFF BIT(3) BIT 41 drivers/clocksource/arm_arch_timer.c #define CNTACR_RWVT BIT(4) BIT 42 drivers/clocksource/arm_arch_timer.c #define CNTACR_RWPT BIT(5) BIT 30 drivers/clocksource/arm_global_timer.c #define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */ BIT 31 drivers/clocksource/arm_global_timer.c #define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */ BIT 32 drivers/clocksource/arm_global_timer.c #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ BIT 33 drivers/clocksource/arm_global_timer.c #define GT_CONTROL_AUTO_INC BIT(3) /* banked */ BIT 36 drivers/clocksource/arm_global_timer.c #define GT_INT_STATUS_EVENT_FLAG BIT(0) BIT 21 drivers/clocksource/armv7m_systick.c #define SYST_CSR_ENABLE BIT(0) BIT 32 drivers/clocksource/asm9260_timer.c #define BM_IR_CR0 BIT(4) BIT 33 drivers/clocksource/asm9260_timer.c #define BM_IR_MR3 BIT(3) BIT 34 drivers/clocksource/asm9260_timer.c #define BM_IR_MR2 BIT(2) BIT 35 drivers/clocksource/asm9260_timer.c #define BM_IR_MR1 BIT(1) BIT 36 drivers/clocksource/asm9260_timer.c #define BM_IR_MR0 BIT(0) BIT 43 drivers/clocksource/asm9260_timer.c #define BM_C3_RST BIT(7) BIT 44 drivers/clocksource/asm9260_timer.c #define BM_C2_RST BIT(6) BIT 45 drivers/clocksource/asm9260_timer.c #define BM_C1_RST BIT(5) BIT 46 drivers/clocksource/asm9260_timer.c #define BM_C0_RST BIT(4) BIT 50 drivers/clocksource/asm9260_timer.c #define BM_C3_EN BIT(3) BIT 51 drivers/clocksource/asm9260_timer.c #define BM_C2_EN BIT(2) BIT 52 drivers/clocksource/asm9260_timer.c #define BM_C1_EN BIT(1) BIT 53 drivers/clocksource/asm9260_timer.c #define BM_C0_EN BIT(0) BIT 110 drivers/clocksource/bcm2835_timer.c timer->match_mask = BIT(DEFAULT_TIMER); BIT 64 drivers/clocksource/ingenic-timer.c regmap_write(tcu->map, TCU_REG_TECR, BIT(tcu->timer_channel)); BIT 79 drivers/clocksource/ingenic-timer.c regmap_write(tcu->map, TCU_REG_TESR, BIT(tcu->timer_channel)); BIT 89 drivers/clocksource/ingenic-timer.c regmap_write(tcu->map, TCU_REG_TECR, BIT(tcu->timer_channel)); BIT 200 drivers/clocksource/ingenic-timer.c regmap_write(tcu->map, TCU_REG_TESR, BIT(channel)); BIT 24 drivers/clocksource/mps2-timer.c #define TIMER_CTRL_ENABLE BIT(0) BIT 25 drivers/clocksource/mps2-timer.c #define TIMER_CTRL_IE BIT(3) BIT 54 drivers/clocksource/timer-armada-370-xp.c #define TIMER0_EN BIT(0) BIT 55 drivers/clocksource/timer-armada-370-xp.c #define TIMER0_RELOAD_EN BIT(1) BIT 56 drivers/clocksource/timer-armada-370-xp.c #define TIMER0_25MHZ BIT(11) BIT 58 drivers/clocksource/timer-armada-370-xp.c #define TIMER1_EN BIT(2) BIT 59 drivers/clocksource/timer-armada-370-xp.c #define TIMER1_RELOAD_EN BIT(3) BIT 60 drivers/clocksource/timer-armada-370-xp.c #define TIMER1_25MHZ BIT(12) BIT 54 drivers/clocksource/timer-atcpit100.c #define APB_CLK BIT(3) BIT 76 drivers/clocksource/timer-atlas7.c writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); BIT 92 drivers/clocksource/timer-atlas7.c BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); BIT 147 drivers/clocksource/timer-atlas7.c BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); BIT 251 drivers/clocksource/timer-atlas7.c BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); BIT 23 drivers/clocksource/timer-atmel-pit.c #define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */ BIT 24 drivers/clocksource/timer-atmel-pit.c #define AT91_PIT_PITEN BIT(24) /* Timer Enabled */ BIT 28 drivers/clocksource/timer-atmel-pit.c #define AT91_PIT_PITS BIT(0) /* Timer Status */ BIT 32 drivers/clocksource/timer-davinci.c #define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED BIT(2) BIT 37 drivers/clocksource/timer-davinci.c #define DAVINCI_TIMER_ENAMODE_ONESHOT BIT(0) BIT 38 drivers/clocksource/timer-davinci.c #define DAVINCI_TIMER_ENAMODE_PERIODIC BIT(1) BIT 55 drivers/clocksource/timer-digicolor.c #define CONTROL_ENABLE BIT(0) BIT 43 drivers/clocksource/timer-fttmr010.c #define TIMER_1_CR_ENABLE BIT(0) BIT 44 drivers/clocksource/timer-fttmr010.c #define TIMER_1_CR_CLOCK BIT(1) BIT 45 drivers/clocksource/timer-fttmr010.c #define TIMER_1_CR_INT BIT(2) BIT 46 drivers/clocksource/timer-fttmr010.c #define TIMER_2_CR_ENABLE BIT(3) BIT 47 drivers/clocksource/timer-fttmr010.c #define TIMER_2_CR_CLOCK BIT(4) BIT 48 drivers/clocksource/timer-fttmr010.c #define TIMER_2_CR_INT BIT(5) BIT 49 drivers/clocksource/timer-fttmr010.c #define TIMER_3_CR_ENABLE BIT(6) BIT 50 drivers/clocksource/timer-fttmr010.c #define TIMER_3_CR_CLOCK BIT(7) BIT 51 drivers/clocksource/timer-fttmr010.c #define TIMER_3_CR_INT BIT(8) BIT 52 drivers/clocksource/timer-fttmr010.c #define TIMER_1_CR_UPDOWN BIT(9) BIT 53 drivers/clocksource/timer-fttmr010.c #define TIMER_2_CR_UPDOWN BIT(10) BIT 54 drivers/clocksource/timer-fttmr010.c #define TIMER_3_CR_UPDOWN BIT(11) BIT 61 drivers/clocksource/timer-fttmr010.c #define TIMER_1_CR_ASPEED_ENABLE BIT(0) BIT 62 drivers/clocksource/timer-fttmr010.c #define TIMER_1_CR_ASPEED_CLOCK BIT(1) BIT 63 drivers/clocksource/timer-fttmr010.c #define TIMER_1_CR_ASPEED_INT BIT(2) BIT 64 drivers/clocksource/timer-fttmr010.c #define TIMER_2_CR_ASPEED_ENABLE BIT(4) BIT 65 drivers/clocksource/timer-fttmr010.c #define TIMER_2_CR_ASPEED_CLOCK BIT(5) BIT 66 drivers/clocksource/timer-fttmr010.c #define TIMER_2_CR_ASPEED_INT BIT(6) BIT 67 drivers/clocksource/timer-fttmr010.c #define TIMER_3_CR_ASPEED_ENABLE BIT(8) BIT 68 drivers/clocksource/timer-fttmr010.c #define TIMER_3_CR_ASPEED_CLOCK BIT(9) BIT 69 drivers/clocksource/timer-fttmr010.c #define TIMER_3_CR_ASPEED_INT BIT(10) BIT 83 drivers/clocksource/timer-fttmr010.c #define TIMER_1_INT_MATCH1 BIT(0) BIT 84 drivers/clocksource/timer-fttmr010.c #define TIMER_1_INT_MATCH2 BIT(1) BIT 85 drivers/clocksource/timer-fttmr010.c #define TIMER_1_INT_OVERFLOW BIT(2) BIT 86 drivers/clocksource/timer-fttmr010.c #define TIMER_2_INT_MATCH1 BIT(3) BIT 87 drivers/clocksource/timer-fttmr010.c #define TIMER_2_INT_MATCH2 BIT(4) BIT 88 drivers/clocksource/timer-fttmr010.c #define TIMER_2_INT_OVERFLOW BIT(5) BIT 89 drivers/clocksource/timer-fttmr010.c #define TIMER_3_INT_MATCH1 BIT(6) BIT 90 drivers/clocksource/timer-fttmr010.c #define TIMER_3_INT_MATCH2 BIT(7) BIT 91 drivers/clocksource/timer-fttmr010.c #define TIMER_3_INT_OVERFLOW BIT(8) BIT 19 drivers/clocksource/timer-gx6605s.c #define GX6605S_STATUS_CLR BIT(0) BIT 20 drivers/clocksource/timer-gx6605s.c #define GX6605S_CONTRL_RST BIT(0) BIT 21 drivers/clocksource/timer-gx6605s.c #define GX6605S_CONTRL_START BIT(1) BIT 22 drivers/clocksource/timer-gx6605s.c #define GX6605S_CONFIG_EN BIT(0) BIT 23 drivers/clocksource/timer-gx6605s.c #define GX6605S_CONFIG_IRQ_EN BIT(1) BIT 28 drivers/clocksource/timer-imx-tpm.c #define TPM_STATUS_CH0F BIT(0) BIT 30 drivers/clocksource/timer-imx-tpm.c #define TPM_C0SC_CHIE BIT(6) BIT 31 drivers/clocksource/timer-lpc32xx.c #define LPC32XX_TIMER_IR_MR0INT BIT(0) BIT 33 drivers/clocksource/timer-lpc32xx.c #define LPC32XX_TIMER_TCR_CEN BIT(0) BIT 34 drivers/clocksource/timer-lpc32xx.c #define LPC32XX_TIMER_TCR_CRST BIT(1) BIT 38 drivers/clocksource/timer-lpc32xx.c #define LPC32XX_TIMER_MCR_MR0I BIT(0) BIT 39 drivers/clocksource/timer-lpc32xx.c #define LPC32XX_TIMER_MCR_MR0R BIT(1) BIT 40 drivers/clocksource/timer-lpc32xx.c #define LPC32XX_TIMER_MCR_MR0S BIT(2) BIT 27 drivers/clocksource/timer-mediatek.c #define GPT_IRQ_ENABLE(val) BIT((val) - 1) BIT 29 drivers/clocksource/timer-mediatek.c #define GPT_IRQ_ACK(val) BIT((val) - 1) BIT 69 drivers/clocksource/timer-mediatek.c #define SYST_CON_EN BIT(0) BIT 70 drivers/clocksource/timer-mediatek.c #define SYST_CON_IRQ_EN BIT(1) BIT 71 drivers/clocksource/timer-mediatek.c #define SYST_CON_IRQ_CLR BIT(4) BIT 27 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19) BIT 28 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18) BIT 29 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERB_EN BIT(17) BIT 30 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERA_EN BIT(16) BIT 31 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERD_MODE BIT(15) BIT 32 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERC_MODE BIT(14) BIT 33 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERB_MODE BIT(13) BIT 34 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERA_MODE BIT(12) BIT 19 drivers/clocksource/timer-milbeaut.c #define MLB_TMR_TMCSR_OUTL BIT(5) BIT 20 drivers/clocksource/timer-milbeaut.c #define MLB_TMR_TMCSR_RELD BIT(4) BIT 21 drivers/clocksource/timer-milbeaut.c #define MLB_TMR_TMCSR_INTE BIT(3) BIT 22 drivers/clocksource/timer-milbeaut.c #define MLB_TMR_TMCSR_UF BIT(2) BIT 23 drivers/clocksource/timer-milbeaut.c #define MLB_TMR_TMCSR_CNTE BIT(1) BIT 24 drivers/clocksource/timer-milbeaut.c #define MLB_TMR_TMCSR_TRG BIT(0) BIT 31 drivers/clocksource/timer-npcm7xx.c #define NPCM7XX_Tx_PERIOD BIT(27) BIT 32 drivers/clocksource/timer-npcm7xx.c #define NPCM7XX_Tx_INTEN BIT(29) BIT 33 drivers/clocksource/timer-npcm7xx.c #define NPCM7XX_Tx_COUNTEN BIT(30) BIT 131 drivers/clocksource/timer-nps.c #define TIMER0_CTRL_IE BIT(0) BIT 132 drivers/clocksource/timer-nps.c #define TIMER0_CTRL_NH BIT(1) BIT 26 drivers/clocksource/timer-orion.c #define TIMER0_EN BIT(0) BIT 27 drivers/clocksource/timer-orion.c #define TIMER0_RELOAD_EN BIT(1) BIT 28 drivers/clocksource/timer-orion.c #define TIMER1_EN BIT(2) BIT 29 drivers/clocksource/timer-orion.c #define TIMER1_RELOAD_EN BIT(3) BIT 26 drivers/clocksource/timer-owl.c #define OWL_Tx_CTL_PD BIT(0) BIT 27 drivers/clocksource/timer-owl.c #define OWL_Tx_CTL_INTEN BIT(1) BIT 28 drivers/clocksource/timer-owl.c #define OWL_Tx_CTL_EN BIT(2) BIT 36 drivers/clocksource/timer-oxnas-rps.c #define TIMER_MAX_VAL (BIT(TIMER_BITS) - 1) BIT 38 drivers/clocksource/timer-oxnas-rps.c #define TIMER_PERIODIC BIT(6) BIT 39 drivers/clocksource/timer-oxnas-rps.c #define TIMER_ENABLE BIT(7) BIT 30 drivers/clocksource/timer-pistachio.c #define TIMER_ME_GLOBAL BIT(0) BIT 35 drivers/clocksource/timer-pistachio.c #define TIMER_ME_LOCAL BIT(0) BIT 42 drivers/clocksource/timer-prima2.c #define SIRFSOC_TIMER_LATCH_BIT BIT(0) BIT 63 drivers/clocksource/timer-prima2.c BIT(0))); BIT 66 drivers/clocksource/timer-prima2.c writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); BIT 109 drivers/clocksource/timer-prima2.c writel_relaxed(val & ~BIT(0), BIT 118 drivers/clocksource/timer-prima2.c writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); BIT 227 drivers/clocksource/timer-prima2.c writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); BIT 25 drivers/clocksource/timer-qcom.c #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) BIT 26 drivers/clocksource/timer-qcom.c #define TIMER_ENABLE_EN BIT(0) BIT 30 drivers/clocksource/timer-qcom.c #define TIMER_STS_GPT0_CLR_PEND BIT(10) BIT 27 drivers/clocksource/timer-rda.c #define RDA_OSTIMER_CTRL_ENABLE BIT(24) BIT 28 drivers/clocksource/timer-rda.c #define RDA_OSTIMER_CTRL_REPEAT BIT(28) BIT 29 drivers/clocksource/timer-rda.c #define RDA_OSTIMER_CTRL_LOAD BIT(30) BIT 31 drivers/clocksource/timer-rda.c #define RDA_TIMER_IRQ_MASK_OSTIMER BIT(0) BIT 33 drivers/clocksource/timer-rda.c #define RDA_TIMER_IRQ_CLR_OSTIMER BIT(0) BIT 19 drivers/clocksource/timer-sprd.c #define TIMER_CTL_PERIOD_MODE BIT(0) BIT 20 drivers/clocksource/timer-sprd.c #define TIMER_CTL_ENABLE BIT(1) BIT 21 drivers/clocksource/timer-sprd.c #define TIMER_CTL_64BIT_WIDTH BIT(16) BIT 24 drivers/clocksource/timer-sprd.c #define TIMER_INT_EN BIT(0) BIT 25 drivers/clocksource/timer-sprd.c #define TIMER_INT_RAW_STS BIT(1) BIT 26 drivers/clocksource/timer-sprd.c #define TIMER_INT_MASK_STS BIT(2) BIT 27 drivers/clocksource/timer-sprd.c #define TIMER_INT_CLR BIT(3) BIT 34 drivers/clocksource/timer-stm32.c #define TIM_CR1_CEN BIT(0) BIT 35 drivers/clocksource/timer-stm32.c #define TIM_CR1_UDIS BIT(1) BIT 36 drivers/clocksource/timer-stm32.c #define TIM_CR1_OPM BIT(3) BIT 37 drivers/clocksource/timer-stm32.c #define TIM_CR1_ARPE BIT(7) BIT 39 drivers/clocksource/timer-stm32.c #define TIM_DIER_UIE BIT(0) BIT 40 drivers/clocksource/timer-stm32.c #define TIM_DIER_CC1IE BIT(1) BIT 42 drivers/clocksource/timer-stm32.c #define TIM_SR_UIF BIT(0) BIT 44 drivers/clocksource/timer-stm32.c #define TIM_EGR_UG BIT(0) BIT 30 drivers/clocksource/timer-sun4i.c #define TIMER_IRQ_EN(val) BIT(val) BIT 33 drivers/clocksource/timer-sun4i.c #define TIMER_CTL_ENABLE BIT(0) BIT 34 drivers/clocksource/timer-sun4i.c #define TIMER_CTL_RELOAD BIT(1) BIT 38 drivers/clocksource/timer-sun4i.c #define TIMER_CTL_ONESHOT BIT(7) BIT 27 drivers/clocksource/timer-sun5i.c #define TIMER_IRQ_EN(val) BIT(val) BIT 30 drivers/clocksource/timer-sun5i.c #define TIMER_CTL_ENABLE BIT(0) BIT 31 drivers/clocksource/timer-sun5i.c #define TIMER_CTL_RELOAD BIT(1) BIT 33 drivers/clocksource/timer-sun5i.c #define TIMER_CTL_ONESHOT BIT(7) BIT 35 drivers/clocksource/timer-tegra.c #define TIMER_PTV_EN BIT(31) BIT 36 drivers/clocksource/timer-tegra.c #define TIMER_PTV_PER BIT(30) BIT 38 drivers/clocksource/timer-tegra.c #define TIMER_PCR_INTR_CLR BIT(30) BIT 61 drivers/counter/104-quad-8.c #define QUAD8_FLAG_BT BIT(0) BIT 63 drivers/counter/104-quad-8.c #define QUAD8_FLAG_CT BIT(1) BIT 65 drivers/counter/104-quad-8.c #define QUAD8_FLAG_E BIT(4) BIT 67 drivers/counter/104-quad-8.c #define QUAD8_FLAG_UD BIT(5) BIT 109 drivers/counter/104-quad-8.c & BIT(chan->channel)); BIT 591 drivers/counter/104-quad-8.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 592 drivers/counter/104-quad-8.c BIT(IIO_CHAN_INFO_ENABLE) | BIT(IIO_CHAN_INFO_SCALE), \ BIT 600 drivers/counter/104-quad-8.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 628 drivers/counter/104-quad-8.c & BIT(signal->id - 16); BIT 319 drivers/counter/stm32-lptimer-cnt.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 320 drivers/counter/stm32-lptimer-cnt.c BIT(IIO_CHAN_INFO_ENABLE) | BIT 321 drivers/counter/stm32-lptimer-cnt.c BIT(IIO_CHAN_INFO_SCALE), BIT 342 drivers/counter/stm32-lptimer-cnt.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 343 drivers/counter/stm32-lptimer-cnt.c BIT(IIO_CHAN_INFO_ENABLE) | BIT 344 drivers/counter/stm32-lptimer-cnt.c BIT(IIO_CHAN_INFO_SCALE), BIT 17 drivers/counter/stm32-timer-cnt.c #define TIM_CCMR_CCXS (BIT(8) | BIT(0)) BIT 42 drivers/cpufreq/armada-37xx-cpufreq.c #define ARMADA_37XX_NB_CLK_SEL_EN BIT(26) BIT 43 drivers/cpufreq/armada-37xx-cpufreq.c #define ARMADA_37XX_NB_TBG_EN BIT(28) BIT 44 drivers/cpufreq/armada-37xx-cpufreq.c #define ARMADA_37XX_NB_DIV_EN BIT(29) BIT 45 drivers/cpufreq/armada-37xx-cpufreq.c #define ARMADA_37XX_NB_VDD_EN BIT(30) BIT 46 drivers/cpufreq/armada-37xx-cpufreq.c #define ARMADA_37XX_NB_DFS_EN BIT(31) BIT 56 drivers/cpufreq/armada-37xx-cpufreq.c #define ARMADA_37XX_AVS_ENABLE BIT(30) BIT 61 drivers/cpufreq/armada-37xx-cpufreq.c #define ARMADA_37XX_AVS_LOW_VDD_EN BIT(6) BIT 137 drivers/cpufreq/brcmstb-avs-cpufreq.c #define AVS_CPU_L2_INT_MASK BIT(31) BIT 61 drivers/cpufreq/imx-cpufreq-dt.c supported_hw[0] = BIT(speed_grade); BIT 62 drivers/cpufreq/imx-cpufreq-dt.c supported_hw[1] = BIT(mkt_segment); BIT 1302 drivers/cpufreq/intel_pstate.c if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { BIT 1304 drivers/cpufreq/intel_pstate.c power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); BIT 17 drivers/cpufreq/kirkwood-cpufreq.c #define CPU_SW_INT_BLK BIT(28) BIT 218 drivers/cpufreq/sti-cpufreq.c version[0] = BIT(major); BIT 219 drivers/cpufreq/sti-cpufreq.c version[1] = BIT(minor); BIT 220 drivers/cpufreq/sti-cpufreq.c version[2] = BIT(substrate); BIT 30 drivers/cpufreq/ti-cpufreq.c #define DRA7_EFUSE_NOM_MPU_OPP BIT(0) BIT 31 drivers/cpufreq/ti-cpufreq.c #define DRA7_EFUSE_OD_MPU_OPP BIT(1) BIT 32 drivers/cpufreq/ti-cpufreq.c #define DRA7_EFUSE_HIGH_MPU_OPP BIT(2) BIT 169 drivers/cpufreq/ti-cpufreq.c *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK); BIT 41 drivers/crypto/amcc/crypto4xx_core.h #define PD_ENTRY_BUSY BIT(1) BIT 42 drivers/crypto/amcc/crypto4xx_core.h #define PD_ENTRY_INUSE BIT(0) BIT 258 drivers/crypto/amcc/crypto4xx_reg_def.h #define PD_CTL_HASH_FINAL BIT(4) BIT 259 drivers/crypto/amcc/crypto4xx_reg_def.h #define PD_CTL_PE_DONE BIT(1) BIT 260 drivers/crypto/amcc/crypto4xx_reg_def.h #define PD_CTL_HOST_READY BIT(0) BIT 73 drivers/crypto/atmel-aes-regs.h #define AES_EMR_APEN BIT(0) /* Auto Padding Enable */ BIT 74 drivers/crypto/atmel-aes-regs.h #define AES_EMR_APM BIT(1) /* Auto Padding Mode */ BIT 76 drivers/crypto/atmel-aes-regs.h #define AES_EMR_APM_SSL BIT(1) BIT 77 drivers/crypto/atmel-aes-regs.h #define AES_EMR_PLIPEN BIT(4) /* PLIP Enable */ BIT 78 drivers/crypto/atmel-aes-regs.h #define AES_EMR_PLIPD BIT(5) /* PLIP Decipher */ BIT 77 drivers/crypto/atmel-aes.c #define AES_FLAGS_BUSY BIT(3) BIT 78 drivers/crypto/atmel-aes.c #define AES_FLAGS_DUMP_REG BIT(4) BIT 79 drivers/crypto/atmel-aes.c #define AES_FLAGS_OWN_SHA BIT(5) BIT 44 drivers/crypto/atmel-sha.c #define SHA_FLAGS_BUSY BIT(0) BIT 45 drivers/crypto/atmel-sha.c #define SHA_FLAGS_FINAL BIT(1) BIT 46 drivers/crypto/atmel-sha.c #define SHA_FLAGS_DMA_ACTIVE BIT(2) BIT 47 drivers/crypto/atmel-sha.c #define SHA_FLAGS_OUTPUT_READY BIT(3) BIT 48 drivers/crypto/atmel-sha.c #define SHA_FLAGS_INIT BIT(4) BIT 49 drivers/crypto/atmel-sha.c #define SHA_FLAGS_CPU BIT(5) BIT 50 drivers/crypto/atmel-sha.c #define SHA_FLAGS_DMA_READY BIT(6) BIT 51 drivers/crypto/atmel-sha.c #define SHA_FLAGS_DUMP_REG BIT(7) BIT 55 drivers/crypto/atmel-sha.c #define SHA_FLAGS_FINUP BIT(16) BIT 56 drivers/crypto/atmel-sha.c #define SHA_FLAGS_SG BIT(17) BIT 57 drivers/crypto/atmel-sha.c #define SHA_FLAGS_ERROR BIT(23) BIT 58 drivers/crypto/atmel-sha.c #define SHA_FLAGS_PAD BIT(24) BIT 59 drivers/crypto/atmel-sha.c #define SHA_FLAGS_RESTORE BIT(25) BIT 60 drivers/crypto/atmel-sha.c #define SHA_FLAGS_IDATAR0 BIT(26) BIT 61 drivers/crypto/atmel-sha.c #define SHA_FLAGS_WAIT_DATARDY BIT(27) BIT 44 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_ENCRYPT BIT(0) BIT 45 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_CBC BIT(1) BIT 46 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_CFB BIT(2) BIT 47 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_CFB8 BIT(3) BIT 48 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_CFB16 BIT(4) BIT 49 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_CFB32 BIT(5) BIT 50 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_CFB64 BIT(6) BIT 51 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_OFB BIT(7) BIT 53 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_INIT BIT(16) BIT 54 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_FAST BIT(17) BIT 55 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_BUSY BIT(18) BIT 56 drivers/crypto/atmel-tdes.c #define TDES_FLAGS_DMA BIT(19) BIT 63 drivers/crypto/axis/artpec6_crypto.c #define PDMA_OUT_CFG_EN BIT(0) BIT 68 drivers/crypto/axis/artpec6_crypto.c #define PDMA_OUT_CMD_START BIT(0) BIT 69 drivers/crypto/axis/artpec6_crypto.c #define A6_PDMA_OUT_CMD_STOP BIT(3) BIT 70 drivers/crypto/axis/artpec6_crypto.c #define A7_PDMA_OUT_CMD_STOP BIT(2) BIT 78 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_CFG_EN BIT(0) BIT 84 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_CMD_START BIT(0) BIT 85 drivers/crypto/axis/artpec6_crypto.c #define A6_PDMA_IN_CMD_FLUSH_STAT BIT(2) BIT 86 drivers/crypto/axis/artpec6_crypto.c #define A6_PDMA_IN_CMD_STOP BIT(3) BIT 87 drivers/crypto/axis/artpec6_crypto.c #define A7_PDMA_IN_CMD_FLUSH_STAT BIT(1) BIT 88 drivers/crypto/axis/artpec6_crypto.c #define A7_PDMA_IN_CMD_STOP BIT(2) BIT 99 drivers/crypto/axis/artpec6_crypto.c #define A6_PDMA_INTR_MASK_IN_DATA BIT(2) BIT 100 drivers/crypto/axis/artpec6_crypto.c #define A6_PDMA_INTR_MASK_IN_EOP BIT(3) BIT 101 drivers/crypto/axis/artpec6_crypto.c #define A6_PDMA_INTR_MASK_IN_EOP_FLUSH BIT(4) BIT 103 drivers/crypto/axis/artpec6_crypto.c #define A7_PDMA_INTR_MASK_IN_DATA BIT(3) BIT 104 drivers/crypto/axis/artpec6_crypto.c #define A7_PDMA_INTR_MASK_IN_EOP BIT(4) BIT 105 drivers/crypto/axis/artpec6_crypto.c #define A7_PDMA_INTR_MASK_IN_EOP_FLUSH BIT(5) BIT 110 drivers/crypto/axis/artpec6_crypto.c #define A6_CRY_MD_HASH_HMAC_FIN BIT(23) BIT 113 drivers/crypto/axis/artpec6_crypto.c #define A6_CRY_MD_CIPHER_DECR BIT(22) BIT 114 drivers/crypto/axis/artpec6_crypto.c #define A6_CRY_MD_CIPHER_TWEAK BIT(23) BIT 115 drivers/crypto/axis/artpec6_crypto.c #define A6_CRY_MD_CIPHER_DSEQ BIT(24) BIT 120 drivers/crypto/axis/artpec6_crypto.c #define A7_CRY_MD_HASH_HMAC_FIN BIT(15) BIT 123 drivers/crypto/axis/artpec6_crypto.c #define A7_CRY_MD_CIPHER_DECR BIT(14) BIT 124 drivers/crypto/axis/artpec6_crypto.c #define A7_CRY_MD_CIPHER_TWEAK BIT(15) BIT 125 drivers/crypto/axis/artpec6_crypto.c #define A7_CRY_MD_CIPHER_DSEQ BIT(16) BIT 60 drivers/crypto/bcm/spum.h #define SPUM_NS2_MAX_PAYLOAD (BIT(16) - 1) BIT 94 drivers/crypto/bcm/spum.h #define MH_SUPDT_PRES BIT(0) BIT 95 drivers/crypto/bcm/spum.h #define MH_HASH_PRES BIT(2) BIT 96 drivers/crypto/bcm/spum.h #define MH_BD_PRES BIT(3) BIT 97 drivers/crypto/bcm/spum.h #define MH_MFM_PRES BIT(4) BIT 98 drivers/crypto/bcm/spum.h #define MH_BDESC_PRES BIT(5) BIT 99 drivers/crypto/bcm/spum.h #define MH_SCTX_PRES BIT(7) BIT 118 drivers/crypto/bcm/spum.h #define ICV_IS_512 BIT(27) BIT 120 drivers/crypto/bcm/spum.h #define CIPHER_ORDER BIT(30) BIT 122 drivers/crypto/bcm/spum.h #define CIPHER_INBOUND BIT(31) BIT 127 drivers/crypto/bcm/spum.h #define IV_OFFSET BIT(3) BIT 129 drivers/crypto/bcm/spum.h #define GEN_IV BIT(5) BIT 131 drivers/crypto/bcm/spum.h #define EXPLICIT_IV BIT(6) BIT 133 drivers/crypto/bcm/spum.h #define SCTX_IV BIT(7) BIT 137 drivers/crypto/bcm/spum.h #define CHECK_ICV BIT(12) BIT 139 drivers/crypto/bcm/spum.h #define INSERT_ICV BIT(13) BIT 141 drivers/crypto/bcm/spum.h #define BD_SUPPRESS BIT(19) BIT 1533 drivers/crypto/caam/caamalg_desc.c __be64 sector_size = cpu_to_be64(BIT(15)); BIT 1592 drivers/crypto/caam/caamalg_desc.c __be64 sector_size = cpu_to_be64(BIT(15)); BIT 21 drivers/crypto/caam/qi.c #define PREHDR_ABS BIT(25) BIT 318 drivers/crypto/caam/regs.h #define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT) BIT 402 drivers/crypto/caam/regs.h #define CTPR_MS_PS BIT(17) BIT 403 drivers/crypto/caam/regs.h #define CTPR_MS_DPAA2 BIT(13) BIT 417 drivers/crypto/caam/regs.h #define CSTA_PLEND BIT(10) BIT 418 drivers/crypto/caam/regs.h #define CSTA_ALT_PLEND BIT(18) BIT 20 drivers/crypto/cavium/cpt/cpt_common.h #define CPT_FLAG_SRIOV_ENABLED BIT(1) BIT 21 drivers/crypto/cavium/cpt/cpt_common.h #define CPT_FLAG_VF_DRIVER BIT(2) BIT 22 drivers/crypto/cavium/cpt/cpt_common.h #define CPT_FLAG_DEVICE_READY BIT(3) BIT 24 drivers/crypto/cavium/cpt/cptvf.h #define CPT_VF_INTR_MBOX_MASK BIT(0) BIT 25 drivers/crypto/cavium/cpt/cptvf.h #define CPT_VF_INTR_DOVF_MASK BIT(1) BIT 26 drivers/crypto/cavium/cpt/cptvf.h #define CPT_VF_INTR_IRDE_MASK BIT(2) BIT 27 drivers/crypto/cavium/cpt/cptvf.h #define CPT_VF_INTR_NWRP_MASK BIT(3) BIT 28 drivers/crypto/cavium/cpt/cptvf.h #define CPT_VF_INTR_SERR_MASK BIT(4) BIT 186 drivers/crypto/ccp/ccp-dev.h #define CCP_DMAPOOL_ALIGN BIT(5) BIT 29 drivers/crypto/ccp/psp-dev.h #define PSP_CMD_COMPLETE BIT(1) BIT 32 drivers/crypto/ccp/psp-dev.h #define PSP_CMDRESP_IOC BIT(0) BIT 33 drivers/crypto/ccp/psp-dev.h #define PSP_CMDRESP_RESP BIT(31) BIT 67 drivers/crypto/ccree/cc_driver.h #define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT) BIT 69 drivers/crypto/ccree/cc_driver.h #define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT) BIT 71 drivers/crypto/ccree/cc_driver.h #define CC_SECURITY_DISABLED_MASK BIT(CC_SECURITY_DISABLED_VALUE_BIT_SHIFT) BIT 73 drivers/crypto/ccree/cc_driver.h #define CC_NVM_IS_IDLE_MASK BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT) BIT 80 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT) | \ BIT 81 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT) | \ BIT 82 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT) | \ BIT 83 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT) | \ BIT 84 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT) | \ BIT 85 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT) | \ BIT 86 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT) | \ BIT 87 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT)) BIT 90 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT) | \ BIT 91 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT) | \ BIT 92 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT) | \ BIT 93 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT) | \ BIT 94 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT) | \ BIT 95 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT) | \ BIT 96 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT) | \ BIT 97 drivers/crypto/ccree/cc_driver.h BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT)) BIT 103 drivers/crypto/ccree/cc_driver.h #define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT) BIT 55 drivers/crypto/ccree/cc_request_mgr.c { BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SHIFT), BIT 56 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT), BIT 57 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SHIFT), BIT 58 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SHIFT), BIT 59 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SHIFT), BIT 60 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SHIFT), BIT 61 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SHIFT), BIT 62 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT) }, BIT 63 drivers/crypto/ccree/cc_request_mgr.c { BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SHIFT), BIT 64 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT), BIT 65 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SHIFT), BIT 66 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SHIFT), BIT 67 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SHIFT), BIT 68 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT), BIT 69 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SHIFT), BIT 70 drivers/crypto/ccree/cc_request_mgr.c BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT) } BIT 27 drivers/crypto/exynos-rng.c #define EXYNOS_RNG_GEN_PRNG BIT(1) BIT 37 drivers/crypto/exynos-rng.c #define EXYNOS_RNG_STATUS_SEED_SETTING_DONE BIT(1) BIT 38 drivers/crypto/exynos-rng.c #define EXYNOS_RNG_STATUS_RNG_DONE BIT(5) BIT 294 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(0), .msg = "qm_axi_rresp" }, BIT 295 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(1), .msg = "qm_axi_bresp" }, BIT 296 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(2), .msg = "qm_ecc_mbit" }, BIT 297 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(3), .msg = "qm_ecc_1bit" }, BIT 298 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(4), .msg = "qm_acc_get_task_timeout" }, BIT 299 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(5), .msg = "qm_acc_do_task_timeout" }, BIT 300 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(6), .msg = "qm_acc_wb_not_ready_timeout" }, BIT 301 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(7), .msg = "qm_sq_cq_vf_invalid" }, BIT 302 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(8), .msg = "qm_cq_vf_invalid" }, BIT 303 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(9), .msg = "qm_sq_vf_invalid" }, BIT 304 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(10), .msg = "qm_db_timeout" }, BIT 305 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(11), .msg = "qm_of_fifo_of" }, BIT 306 drivers/crypto/hisilicon/qm.c { .int_msk = BIT(12), .msg = "qm_db_random_invalid" }, BIT 427 drivers/crypto/hisilicon/qm.c val & BIT(0), 10, 1000); BIT 707 drivers/crypto/hisilicon/qm.c val & BIT(0), 10, 1000); BIT 721 drivers/crypto/hisilicon/qm.c val & BIT(0), 10, 1000); BIT 1389 drivers/crypto/hisilicon/qm.c val, val & BIT(0), 10, 1000)) BIT 13 drivers/crypto/hisilicon/qm.h #define AXUSER_SNOOP_ENABLE BIT(30) BIT 16 drivers/crypto/hisilicon/qm.h #define AXUSER_NS BIT(6) BIT 17 drivers/crypto/hisilicon/qm.h #define AXUSER_NO BIT(5) BIT 18 drivers/crypto/hisilicon/qm.h #define AXUSER_FP BIT(4) BIT 19 drivers/crypto/hisilicon/qm.h #define AXUSER_SSV BIT(0) BIT 34 drivers/crypto/hisilicon/qm.h #define SQC_CACHE_ENABLE BIT(0) BIT 35 drivers/crypto/hisilicon/qm.h #define CQC_CACHE_ENABLE BIT(1) BIT 36 drivers/crypto/hisilicon/qm.h #define SQC_CACHE_WB_ENABLE BIT(4) BIT 38 drivers/crypto/hisilicon/qm.h #define CQC_CACHE_WB_ENABLE BIT(11) BIT 57 drivers/crypto/hisilicon/qm.h #define QM_AXI_RRESP BIT(0) BIT 58 drivers/crypto/hisilicon/qm.h #define QM_AXI_BRESP BIT(1) BIT 59 drivers/crypto/hisilicon/qm.h #define QM_ECC_MBIT BIT(2) BIT 60 drivers/crypto/hisilicon/qm.h #define QM_ECC_1BIT BIT(3) BIT 61 drivers/crypto/hisilicon/qm.h #define QM_ACC_GET_TASK_TIMEOUT BIT(4) BIT 62 drivers/crypto/hisilicon/qm.h #define QM_ACC_DO_TASK_TIMEOUT BIT(5) BIT 63 drivers/crypto/hisilicon/qm.h #define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6) BIT 64 drivers/crypto/hisilicon/qm.h #define QM_SQ_CQ_VF_INVALID BIT(7) BIT 65 drivers/crypto/hisilicon/qm.h #define QM_CQ_VF_INVALID BIT(8) BIT 66 drivers/crypto/hisilicon/qm.h #define QM_SQ_VF_INVALID BIT(9) BIT 67 drivers/crypto/hisilicon/qm.h #define QM_DB_TIMEOUT BIT(10) BIT 68 drivers/crypto/hisilicon/qm.h #define QM_OF_FIFO_OF BIT(11) BIT 69 drivers/crypto/hisilicon/qm.h #define QM_DB_RANDOM_INVALID BIT(12) BIT 41 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_ALGSUB_RST_ST_IS_RST BIT(0) BIT 46 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_ALGSUB_BUILD_RST_ST_IS_RST BIT(0) BIT 52 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_SAA_CTRL_GET_QM_EN BIT(0) BIT 79 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_COMMON_CNT_CLR_CE_CLEAR BIT(0) BIT 80 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_COMMON_CNT_CLR_CE_SNAP_EN BIT(1) BIT 94 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_CTRL2_CLK_GATE_EN BIT(7) BIT 95 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_CTRL2_ENDIAN_BD BIT(8) BIT 96 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_CTRL2_ENDIAN_BD_TYPE BIT(9) BIT 100 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_DEBUG_BD_CFG_WB_NORMAL BIT(0) BIT 101 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_DEBUG_BD_CFG_WB_EN BIT(1) BIT 130 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_Q_CFG_REORDER BIT(0) BIT 148 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_Q_ARUSER_CFG_FA BIT(0) BIT 149 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_Q_ARUSER_CFG_FNA BIT(1) BIT 150 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_Q_ARUSER_CFG_RINVLD BIT(2) BIT 151 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_Q_ARUSER_CFG_PKG BIT(3) BIT 154 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_Q_AWUSER_CFG_FA BIT(0) BIT 155 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_Q_AWUSER_CFG_FNA BIT(1) BIT 156 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_Q_AWUSER_CFG_PKG BIT(2) BIT 219 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_OUT_BD_INFO_ECC_2BIT_ERR BIT(14) BIT 44 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_SEQ BIT(10) BIT 45 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_DE BIT(11) BIT 63 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_AI_GEN BIT(22) BIT 64 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_CI_GEN BIT(23) BIT 65 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_NO_HPAD BIT(24) BIT 77 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_DONE BIT(31) BIT 82 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W1_M_KEY_EN BIT(22) BIT 83 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W1_BD_INVALID BIT(23) BIT 84 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W1_ADDR_TYPE BIT(24) BIT 12 drivers/crypto/hisilicon/zip/zip_crypto.c #define GZIP_HEAD_FHCRC_BIT BIT(1) BIT 13 drivers/crypto/hisilicon/zip/zip_crypto.c #define GZIP_HEAD_FEXTRA_BIT BIT(2) BIT 14 drivers/crypto/hisilicon/zip/zip_crypto.c #define GZIP_HEAD_FNAME_BIT BIT(3) BIT 15 drivers/crypto/hisilicon/zip/zip_crypto.c #define GZIP_HEAD_FCOMMENT_BIT BIT(4) BIT 24 drivers/crypto/hisilicon/zip/zip_main.c #define COMP0_ENABLE BIT(0) BIT 25 drivers/crypto/hisilicon/zip/zip_main.c #define COMP1_ENABLE BIT(1) BIT 26 drivers/crypto/hisilicon/zip/zip_main.c #define DECOMP0_ENABLE BIT(2) BIT 27 drivers/crypto/hisilicon/zip/zip_main.c #define DECOMP1_ENABLE BIT(3) BIT 28 drivers/crypto/hisilicon/zip/zip_main.c #define DECOMP2_ENABLE BIT(4) BIT 29 drivers/crypto/hisilicon/zip/zip_main.c #define DECOMP3_ENABLE BIT(5) BIT 30 drivers/crypto/hisilicon/zip/zip_main.c #define DECOMP4_ENABLE BIT(6) BIT 31 drivers/crypto/hisilicon/zip/zip_main.c #define DECOMP5_ENABLE BIT(7) BIT 36 drivers/crypto/hisilicon/zip/zip_main.c #define DECOMP_CHECK_ENABLE BIT(16) BIT 65 drivers/crypto/hisilicon/zip/zip_main.c #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) BIT 80 drivers/crypto/hisilicon/zip/zip_main.c #define SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) BIT 131 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, BIT 132 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, BIT 133 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, BIT 134 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, BIT 135 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, BIT 136 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, BIT 137 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, BIT 138 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, BIT 139 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, BIT 140 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, BIT 141 drivers/crypto/hisilicon/zip/zip_main.c { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, BIT 44 drivers/crypto/img-hash.c #define CR_INT_RESULTS_AVAILABLE BIT(0) BIT 45 drivers/crypto/img-hash.c #define CR_INT_NEW_RESULTS_SET BIT(1) BIT 46 drivers/crypto/img-hash.c #define CR_INT_RESULT_READ_ERR BIT(2) BIT 47 drivers/crypto/img-hash.c #define CR_INT_MESSAGE_WRITE_ERROR BIT(3) BIT 48 drivers/crypto/img-hash.c #define CR_INT_STATUS BIT(8) BIT 56 drivers/crypto/img-hash.c #define DRIVER_FLAGS_BUSY BIT(0) BIT 57 drivers/crypto/img-hash.c #define DRIVER_FLAGS_FINAL BIT(1) BIT 58 drivers/crypto/img-hash.c #define DRIVER_FLAGS_DMA_ACTIVE BIT(2) BIT 59 drivers/crypto/img-hash.c #define DRIVER_FLAGS_OUTPUT_READY BIT(3) BIT 60 drivers/crypto/img-hash.c #define DRIVER_FLAGS_INIT BIT(4) BIT 61 drivers/crypto/img-hash.c #define DRIVER_FLAGS_CPU BIT(5) BIT 62 drivers/crypto/img-hash.c #define DRIVER_FLAGS_DMA_READY BIT(6) BIT 63 drivers/crypto/img-hash.c #define DRIVER_FLAGS_ERROR BIT(7) BIT 64 drivers/crypto/img-hash.c #define DRIVER_FLAGS_SG BIT(8) BIT 65 drivers/crypto/img-hash.c #define DRIVER_FLAGS_SHA1 BIT(18) BIT 66 drivers/crypto/img-hash.c #define DRIVER_FLAGS_SHA224 BIT(19) BIT 67 drivers/crypto/img-hash.c #define DRIVER_FLAGS_SHA256 BIT(20) BIT 68 drivers/crypto/img-hash.c #define DRIVER_FLAGS_MD5 BIT(21) BIT 461 drivers/crypto/inside-secure/safexcel.c (BIT(priv->hwconfig.hwdataw) - 1)) >> BIT 510 drivers/crypto/inside-secure/safexcel.c (BIT(priv->hwconfig.hwdataw) - 1)) >> BIT 868 drivers/crypto/inside-secure/safexcel.c (BIT(7) | BIT(4) | BIT(3) | BIT(0))) { BIT 875 drivers/crypto/inside-secure/safexcel.c } else if (rdesc->result_data.error_code & BIT(9)) { BIT 1260 drivers/crypto/inside-secure/safexcel.c mask = BIT(val) - 1; BIT 190 drivers/crypto/inside-secure/safexcel.h #define EIP197_xDR_DESC_MODE_64BIT BIT(31) BIT 193 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_xDR_WR_RES_BUF BIT(22) BIT 194 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23) BIT 195 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_xDR_WR_OWN_BUF BIT(24) BIT 201 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22) BIT 202 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23) BIT 207 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23) BIT 211 drivers/crypto/inside-secure/safexcel.h #define EIP197_xDR_PREP_CLR_COUNT BIT(31) BIT 218 drivers/crypto/inside-secure/safexcel.h #define EIP197_xDR_PROC_CLR_COUNT BIT(31) BIT 221 drivers/crypto/inside-secure/safexcel.h #define EIP197_xDR_DMA_ERR BIT(0) BIT 222 drivers/crypto/inside-secure/safexcel.h #define EIP197_xDR_PREP_CMD_THRES BIT(1) BIT 223 drivers/crypto/inside-secure/safexcel.h #define EIP197_xDR_ERR BIT(2) BIT 224 drivers/crypto/inside-secure/safexcel.h #define EIP197_xDR_THRESH BIT(4) BIT 225 drivers/crypto/inside-secure/safexcel.h #define EIP197_xDR_TIMEOUT BIT(5) BIT 227 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_RA_PE_CTRL_RESET BIT(31) BIT 228 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_RA_PE_CTRL_EN BIT(30) BIT 249 drivers/crypto/inside-secure/safexcel.h #define EIP197_CDR_IRQ(n) BIT((n) * 2) BIT 250 drivers/crypto/inside-secure/safexcel.h #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1) BIT 260 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_DFE_CFG_DIS_DEBUG (BIT(31) | BIT(29)) BIT 261 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29) BIT 262 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_DSE_CFG_DIS_DEBUG BIT(31) BIT 265 drivers/crypto/inside-secure/safexcel.h #define EIP197_DxE_THR_CTRL_EN BIT(30) BIT 266 drivers/crypto/inside-secure/safexcel.h #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31) BIT 271 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3) BIT 274 drivers/crypto/inside-secure/safexcel.h #define EIP197_G_IRQ_DFE(n) BIT((n) << 1) BIT 275 drivers/crypto/inside-secure/safexcel.h #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1) BIT 276 drivers/crypto/inside-secure/safexcel.h #define EIP197_G_IRQ_RING BIT(16) BIT 277 drivers/crypto/inside-secure/safexcel.h #define EIP197_G_IRQ_PE(n) BIT((n) + 20) BIT 282 drivers/crypto/inside-secure/safexcel.h #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0)) BIT 283 drivers/crypto/inside-secure/safexcel.h #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0)) BIT 287 drivers/crypto/inside-secure/safexcel.h #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) BIT 288 drivers/crypto/inside-secure/safexcel.h #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) BIT 300 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2) BIT 301 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3) BIT 302 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24) BIT 303 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25) BIT 309 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0) BIT 310 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14) BIT 311 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15) BIT 314 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0) BIT 315 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1) BIT 318 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES BIT(16) BIT 319 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_EIP96_TOKEN_CTRL_NO_TOKEN_WAIT BIT(17) BIT 320 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE_EIP96_TOKEN_CTRL_ENABLE_TIMEOUT BIT(22) BIT 327 drivers/crypto/inside-secure/safexcel.h #define EIP197_ADDRESS_MODE BIT(8) BIT 328 drivers/crypto/inside-secure/safexcel.h #define EIP197_CONTROL_MODE BIT(9) BIT 352 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_RESTART_HASH BIT(4) BIT 353 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5) BIT 355 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_KEY_EN BIT(16) BIT 384 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_CRYPTO_MODE_XCM ((6 << 0) | BIT(17)) BIT 385 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_IV0 BIT(5) BIT 386 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_IV1 BIT(6) BIT 387 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_IV2 BIT(7) BIT 388 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_IV3 BIT(8) BIT 389 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_DIGEST_CNT BIT(9) BIT 390 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_COUNTER_MODE BIT(10) BIT 391 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_CRYPTO_STORE BIT(12) BIT 392 drivers/crypto/inside-secure/safexcel.h #define CONTEXT_CONTROL_HASH_STORE BIT(19) BIT 403 drivers/crypto/inside-secure/safexcel.h #define EIP197_TRC_ENABLE_0 BIT(4) BIT 404 drivers/crypto/inside-secure/safexcel.h #define EIP197_TRC_ENABLE_1 BIT(5) BIT 405 drivers/crypto/inside-secure/safexcel.h #define EIP197_TRC_ENABLE_2 BIT(6) BIT 411 drivers/crypto/inside-secure/safexcel.h #define EIP197_TRC_PARAMS_SW_RESET BIT(0) BIT 412 drivers/crypto/inside-secure/safexcel.h #define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2) BIT 487 drivers/crypto/inside-secure/safexcel.h #define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16) BIT 490 drivers/crypto/inside-secure/safexcel.h #define EIP197_TOKEN_DIRECTION_EXTERNAL BIT(11) BIT 493 drivers/crypto/inside-secure/safexcel.h #define EIP197_TOKEN_STAT_LAST_HASH BIT(0) BIT 494 drivers/crypto/inside-secure/safexcel.h #define EIP197_TOKEN_STAT_LAST_PACKET BIT(1) BIT 507 drivers/crypto/inside-secure/safexcel.h token->packet_length = BIT(2); BIT 515 drivers/crypto/inside-secure/safexcel.h #define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5) BIT 516 drivers/crypto/inside-secure/safexcel.h #define EIP197_TOKEN_INS_TYPE_HASH BIT(6) BIT 517 drivers/crypto/inside-secure/safexcel.h #define EIP197_TOKEN_INS_TYPE_CRYPTO BIT(7) BIT 518 drivers/crypto/inside-secure/safexcel.h #define EIP197_TOKEN_INS_LAST BIT(8) BIT 539 drivers/crypto/inside-secure/safexcel.h #define EIP197_OPTION_MAGIC_VALUE BIT(0) BIT 540 drivers/crypto/inside-secure/safexcel.h #define EIP197_OPTION_64BIT_CTX BIT(1) BIT 542 drivers/crypto/inside-secure/safexcel.h #define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8) BIT 659 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_BC0 = BIT(5), BIT 660 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_SM4 = BIT(6), BIT 661 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_SM3 = BIT(7), BIT 662 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_CHACHA20 = BIT(8), BIT 663 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_POLY1305 = BIT(9), BIT 664 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_SEQMASK_256 = BIT(10), BIT 665 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_SEQMASK_384 = BIT(11), BIT 666 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_AES = BIT(12), BIT 667 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_AES_XFB = BIT(13), BIT 668 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_DES = BIT(15), BIT 669 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_DES_XFB = BIT(16), BIT 670 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_ARC4 = BIT(18), BIT 671 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_AES_XTS = BIT(20), BIT 672 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_WIRELESS = BIT(21), BIT 673 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_MD5 = BIT(22), BIT 674 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_SHA1 = BIT(23), BIT 675 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_SHA2_256 = BIT(25), BIT 676 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_SHA2_512 = BIT(26), BIT 677 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_XCBC_MAC = BIT(27), BIT 678 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_CBC_MAC_ALL = BIT(29), BIT 679 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_GHASH = BIT(30), BIT 680 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_ALG_SHA3 = BIT(31), BIT 698 drivers/crypto/inside-secure/safexcel.h EIP197_TRC_CACHE = BIT(0), BIT 699 drivers/crypto/inside-secure/safexcel.h SAFEXCEL_HW_EIP197 = BIT(1), BIT 24 drivers/crypto/marvell/cesa.h #define CESA_TDMA_OUT_RD_EN BIT(4) BIT 28 drivers/crypto/marvell/cesa.h #define CESA_TDMA_CHAIN BIT(9) BIT 29 drivers/crypto/marvell/cesa.h #define CESA_TDMA_BYTE_SWAP BIT(11) BIT 30 drivers/crypto/marvell/cesa.h #define CESA_TDMA_NO_BYTE_SWAP BIT(11) BIT 31 drivers/crypto/marvell/cesa.h #define CESA_TDMA_EN BIT(12) BIT 32 drivers/crypto/marvell/cesa.h #define CESA_TDMA_FETCH_ND BIT(13) BIT 33 drivers/crypto/marvell/cesa.h #define CESA_TDMA_ACT BIT(14) BIT 46 drivers/crypto/marvell/cesa.h #define CESA_SA_CMD_EN_CESA_SA_ACCL0 BIT(0) BIT 47 drivers/crypto/marvell/cesa.h #define CESA_SA_CMD_EN_CESA_SA_ACCL1 BIT(1) BIT 48 drivers/crypto/marvell/cesa.h #define CESA_SA_CMD_DISABLE_SEC BIT(2) BIT 59 drivers/crypto/marvell/cesa.h #define CESA_SA_CFG_CH0_W_IDMA BIT(7) BIT 60 drivers/crypto/marvell/cesa.h #define CESA_SA_CFG_CH1_W_IDMA BIT(8) BIT 61 drivers/crypto/marvell/cesa.h #define CESA_SA_CFG_ACT_CH0_IDMA BIT(9) BIT 62 drivers/crypto/marvell/cesa.h #define CESA_SA_CFG_ACT_CH1_IDMA BIT(10) BIT 63 drivers/crypto/marvell/cesa.h #define CESA_SA_CFG_MULTI_PKT BIT(11) BIT 64 drivers/crypto/marvell/cesa.h #define CESA_SA_CFG_PARA_DIS BIT(13) BIT 67 drivers/crypto/marvell/cesa.h #define CESA_SA_ST_ACT_0 BIT(0) BIT 68 drivers/crypto/marvell/cesa.h #define CESA_SA_ST_ACT_1 BIT(1) BIT 78 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_AUTH_DONE BIT(0) BIT 79 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_DES_E_DONE BIT(1) BIT 80 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_AES_E_DONE BIT(2) BIT 81 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_AES_D_DONE BIT(3) BIT 82 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_ENC_DONE BIT(4) BIT 83 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_ACCEL0_DONE BIT(5) BIT 84 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_ACCEL1_DONE BIT(6) BIT 85 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_ACC0_IDMA_DONE BIT(7) BIT 86 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_ACC1_IDMA_DONE BIT(8) BIT 87 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_IDMA_DONE BIT(9) BIT 88 drivers/crypto/marvell/cesa.h #define CESA_SA_INT_IDMA_OWN_ERR BIT(10) BIT 112 drivers/crypto/marvell/cesa.h #define CESA_SA_DESC_CFG_CRYPTCM_MSK BIT(16) BIT 274 drivers/crypto/marvell/cesa.h #define CESA_TDMA_DST_IN_SRAM BIT(31) BIT 275 drivers/crypto/marvell/cesa.h #define CESA_TDMA_SRC_IN_SRAM BIT(30) BIT 276 drivers/crypto/marvell/cesa.h #define CESA_TDMA_END_OF_REQ BIT(29) BIT 277 drivers/crypto/marvell/cesa.h #define CESA_TDMA_BREAK_CHAIN BIT(28) BIT 278 drivers/crypto/marvell/cesa.h #define CESA_TDMA_SET_STATE BIT(27) BIT 237 drivers/crypto/marvell/tdma.c tdma->byte_cnt = cpu_to_le32(size | BIT(31)); BIT 271 drivers/crypto/marvell/tdma.c tdma->byte_cnt = cpu_to_le32(size | BIT(31)); BIT 289 drivers/crypto/marvell/tdma.c tdma->byte_cnt = cpu_to_le32(size | BIT(31)); BIT 315 drivers/crypto/marvell/tdma.c tdma->byte_cnt = cpu_to_le32(BIT(31)); BIT 64 drivers/crypto/mediatek/mtk-aes.c #define AES_FLAGS_ECB BIT(0) BIT 65 drivers/crypto/mediatek/mtk-aes.c #define AES_FLAGS_CBC BIT(1) BIT 66 drivers/crypto/mediatek/mtk-aes.c #define AES_FLAGS_CTR BIT(2) BIT 67 drivers/crypto/mediatek/mtk-aes.c #define AES_FLAGS_OFB BIT(3) BIT 68 drivers/crypto/mediatek/mtk-aes.c #define AES_FLAGS_CFB128 BIT(4) BIT 69 drivers/crypto/mediatek/mtk-aes.c #define AES_FLAGS_GCM BIT(5) BIT 70 drivers/crypto/mediatek/mtk-aes.c #define AES_FLAGS_ENCRYPT BIT(6) BIT 71 drivers/crypto/mediatek/mtk-aes.c #define AES_FLAGS_BUSY BIT(7) BIT 73 drivers/crypto/mediatek/mtk-aes.c #define AES_AUTH_TAG_ERR cpu_to_le32(BIT(26)) BIT 23 drivers/crypto/mediatek/mtk-platform.c #define MTK_DESC_OVL_IRQ_EN BIT(25) BIT 24 drivers/crypto/mediatek/mtk-platform.c #define MTK_DESC_ATP_PRESENT BIT(30) BIT 27 drivers/crypto/mediatek/mtk-platform.c #define MTK_DFSE_THR_CTRL_EN BIT(30) BIT 28 drivers/crypto/mediatek/mtk-platform.c #define MTK_DFSE_THR_CTRL_RESET BIT(31) BIT 45 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_TK_LOC_AVL BIT(2) BIT 46 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_PROC_HELD BIT(14) BIT 47 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_TK_TIMEOUT_EN BIT(22) BIT 48 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_INPUT_DMA_ERR BIT(0) BIT 49 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_OUTPUT_DMA_ERR BIT(1) BIT 50 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_PKT_PORC_ERR BIT(2) BIT 51 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_PKT_TIMEOUT BIT(3) BIT 52 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_FATAL_ERR BIT(14) BIT 53 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_INPUT_DMA_ERR_EN BIT(16) BIT 54 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_OUTPUT_DMA_ERR_EN BIT(17) BIT 55 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_PKT_PORC_ERR_EN BIT(18) BIT 56 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_PKT_TIMEOUT_EN BIT(19) BIT 57 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_FATAL_ERR_EN BIT(30) BIT 58 drivers/crypto/mediatek/mtk-platform.c #define MTK_PE_INT_OUT_EN BIT(31) BIT 22 drivers/crypto/mediatek/mtk-platform.h #define MTK_RDR_PROC_THRESH BIT(0) BIT 23 drivers/crypto/mediatek/mtk-platform.h #define MTK_RDR_PROC_MODE BIT(23) BIT 24 drivers/crypto/mediatek/mtk-platform.h #define MTK_CNT_RST BIT(31) BIT 25 drivers/crypto/mediatek/mtk-platform.h #define MTK_IRQ_RDR0 BIT(1) BIT 26 drivers/crypto/mediatek/mtk-platform.h #define MTK_IRQ_RDR1 BIT(3) BIT 27 drivers/crypto/mediatek/mtk-platform.h #define MTK_IRQ_RDR2 BIT(5) BIT 28 drivers/crypto/mediatek/mtk-platform.h #define MTK_IRQ_RDR3 BIT(7) BIT 75 drivers/crypto/mediatek/mtk-platform.h #define MTK_DESC_LAST cpu_to_le32(BIT(22)) BIT 76 drivers/crypto/mediatek/mtk-platform.h #define MTK_DESC_FIRST cpu_to_le32(BIT(23)) BIT 47 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_BUSY BIT(0) BIT 48 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_FINAL BIT(1) BIT 49 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_FINUP BIT(2) BIT 50 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_SG BIT(3) BIT 52 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_SHA1 BIT(4) BIT 53 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_SHA224 BIT(5) BIT 54 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_SHA256 BIT(6) BIT 55 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_SHA384 BIT(7) BIT 56 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_SHA512 BIT(8) BIT 57 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_HMAC BIT(9) BIT 58 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_PAD BIT(10) BIT 821 drivers/crypto/omap-aes.c .dma_enable_in = BIT(2), BIT 822 drivers/crypto/omap-aes.c .dma_enable_out = BIT(3), BIT 823 drivers/crypto/omap-aes.c .dma_start = BIT(5), BIT 852 drivers/crypto/omap-aes.c .dma_enable_in = BIT(2), BIT 853 drivers/crypto/omap-aes.c .dma_enable_out = BIT(3), BIT 854 drivers/crypto/omap-aes.c .dma_start = BIT(5), BIT 874 drivers/crypto/omap-aes.c .dma_enable_in = BIT(5), BIT 875 drivers/crypto/omap-aes.c .dma_enable_out = BIT(6), BIT 31 drivers/crypto/omap-aes.h #define AES_REG_CTRL_CONTEXT_READY BIT(31) BIT 34 drivers/crypto/omap-aes.h #define AES_REG_CTRL_CTR_WIDTH_64 BIT(7) BIT 35 drivers/crypto/omap-aes.h #define AES_REG_CTRL_CTR_WIDTH_96 BIT(8) BIT 38 drivers/crypto/omap-aes.h #define AES_REG_CTRL_CTR BIT(6) BIT 39 drivers/crypto/omap-aes.h #define AES_REG_CTRL_CBC BIT(5) BIT 41 drivers/crypto/omap-aes.h #define AES_REG_CTRL_DIRECTION BIT(2) BIT 42 drivers/crypto/omap-aes.h #define AES_REG_CTRL_INPUT_READY BIT(1) BIT 43 drivers/crypto/omap-aes.h #define AES_REG_CTRL_OUTPUT_READY BIT(0) BIT 56 drivers/crypto/omap-aes.h #define AES_REG_MASK_SIDLE BIT(6) BIT 57 drivers/crypto/omap-aes.h #define AES_REG_MASK_START BIT(5) BIT 58 drivers/crypto/omap-aes.h #define AES_REG_MASK_DMA_OUT_EN BIT(3) BIT 59 drivers/crypto/omap-aes.h #define AES_REG_MASK_DMA_IN_EN BIT(2) BIT 60 drivers/crypto/omap-aes.h #define AES_REG_MASK_SOFTRESET BIT(1) BIT 61 drivers/crypto/omap-aes.h #define AES_REG_AUTOIDLE BIT(0) BIT 67 drivers/crypto/omap-aes.h #define AES_REG_IRQ_DATA_IN BIT(1) BIT 68 drivers/crypto/omap-aes.h #define AES_REG_IRQ_DATA_OUT BIT(2) BIT 74 drivers/crypto/omap-aes.h #define FLAGS_ENCRYPT BIT(0) BIT 75 drivers/crypto/omap-aes.h #define FLAGS_CBC BIT(1) BIT 76 drivers/crypto/omap-aes.h #define FLAGS_CTR BIT(2) BIT 77 drivers/crypto/omap-aes.h #define FLAGS_GCM BIT(3) BIT 78 drivers/crypto/omap-aes.h #define FLAGS_RFC4106_GCM BIT(4) BIT 80 drivers/crypto/omap-aes.h #define FLAGS_INIT BIT(5) BIT 81 drivers/crypto/omap-aes.h #define FLAGS_FAST BIT(6) BIT 82 drivers/crypto/omap-aes.h #define FLAGS_BUSY BIT(7) BIT 17 drivers/crypto/omap-crypto.h #define OMAP_CRYPTO_DATA_COPIED BIT(0) BIT 18 drivers/crypto/omap-crypto.h #define OMAP_CRYPTO_SG_COPIED BIT(1) BIT 22 drivers/crypto/omap-crypto.h #define OMAP_CRYPTO_COPY_DATA BIT(0) BIT 23 drivers/crypto/omap-crypto.h #define OMAP_CRYPTO_FORCE_COPY BIT(1) BIT 24 drivers/crypto/omap-crypto.h #define OMAP_CRYPTO_ZERO_BUF BIT(2) BIT 25 drivers/crypto/omap-crypto.h #define OMAP_CRYPTO_FORCE_SINGLE_ENTRY BIT(3) BIT 54 drivers/crypto/omap-des.c #define DES_REG_CTRL_CBC BIT(4) BIT 55 drivers/crypto/omap-des.c #define DES_REG_CTRL_TDES BIT(3) BIT 56 drivers/crypto/omap-des.c #define DES_REG_CTRL_DIRECTION BIT(2) BIT 57 drivers/crypto/omap-des.c #define DES_REG_CTRL_INPUT_READY BIT(1) BIT 58 drivers/crypto/omap-des.c #define DES_REG_CTRL_OUTPUT_READY BIT(0) BIT 70 drivers/crypto/omap-des.c #define DES_REG_IRQ_DATA_IN BIT(1) BIT 71 drivers/crypto/omap-des.c #define DES_REG_IRQ_DATA_OUT BIT(2) BIT 74 drivers/crypto/omap-des.c #define FLAGS_ENCRYPT BIT(0) BIT 75 drivers/crypto/omap-des.c #define FLAGS_CBC BIT(1) BIT 76 drivers/crypto/omap-des.c #define FLAGS_INIT BIT(4) BIT 77 drivers/crypto/omap-des.c #define FLAGS_BUSY BIT(6) BIT 845 drivers/crypto/omap-des.c .dma_enable_in = BIT(5), BIT 846 drivers/crypto/omap-des.c .dma_enable_out = BIT(6), BIT 302 drivers/crypto/omap-sham.c if (ctx->flags & BIT(FLAGS_HMAC)) { BIT 472 drivers/crypto/omap-sham.c if (ctx->flags & BIT(FLAGS_HMAC)) { BIT 487 drivers/crypto/omap-sham.c if (ctx->flags & BIT(FLAGS_HMAC)) BIT 814 drivers/crypto/omap-sham.c bool final = rctx->flags & BIT(FLAGS_FINUP); BIT 981 drivers/crypto/omap-sham.c if (tctx->flags & BIT(FLAGS_HMAC)) { BIT 989 drivers/crypto/omap-sham.c ctx->flags |= BIT(FLAGS_HMAC); BIT 1001 drivers/crypto/omap-sham.c bool final = ctx->flags & BIT(FLAGS_FINUP); BIT 1004 drivers/crypto/omap-sham.c ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0); BIT 1008 drivers/crypto/omap-sham.c ctx->flags |= BIT(FLAGS_CPU); BIT 1010 drivers/crypto/omap-sham.c if (ctx->flags & BIT(FLAGS_CPU)) BIT 1069 drivers/crypto/omap-sham.c if ((ctx->flags & BIT(FLAGS_HMAC)) && BIT 1093 drivers/crypto/omap-sham.c dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED)); BIT 1100 drivers/crypto/omap-sham.c ctx->flags |= BIT(FLAGS_ERROR); BIT 1104 drivers/crypto/omap-sham.c dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | BIT 1105 drivers/crypto/omap-sham.c BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); BIT 1163 drivers/crypto/omap-sham.c if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) BIT 1214 drivers/crypto/omap-sham.c ctx->flags |= BIT(FLAGS_CPU); BIT 1253 drivers/crypto/omap-sham.c ctx->flags |= BIT(FLAGS_FINUP); BIT 1255 drivers/crypto/omap-sham.c if (ctx->flags & BIT(FLAGS_ERROR)) BIT 1279 drivers/crypto/omap-sham.c ctx->flags |= BIT(FLAGS_FINUP); BIT 1368 drivers/crypto/omap-sham.c tctx->flags |= BIT(FLAGS_HMAC); BIT 1425 drivers/crypto/omap-sham.c if (tctx->flags & BIT(FLAGS_HMAC)) { BIT 1814 drivers/crypto/omap-sham.c .flags = BIT(FLAGS_BE32_SHA1), BIT 1848 drivers/crypto/omap-sham.c .flags = BIT(FLAGS_AUTO_XOR), BIT 1888 drivers/crypto/omap-sham.c .flags = BIT(FLAGS_AUTO_XOR), BIT 68 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h #define ADF_C3XXX_ENABLE_AE_ECC_ERR BIT(28) BIT 69 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h #define ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) BIT 72 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h #define ADF_C3XXX_ERRSSMSH_EN BIT(3) BIT 69 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h #define ADF_C62X_ENABLE_AE_ECC_ERR BIT(28) BIT 70 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h #define ADF_C62X_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) BIT 73 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h #define ADF_C62X_ERRSSMSH_EN BIT(3) BIT 102 drivers/crypto/qat/qat_common/adf_pf2vf_msg.h #define ADF_PF2VF_INT BIT(0) BIT 103 drivers/crypto/qat/qat_common/adf_pf2vf_msg.h #define ADF_PF2VF_MSGORIGIN_SYSTEM BIT(1) BIT 125 drivers/crypto/qat/qat_common/adf_pf2vf_msg.h #define ADF_VF2PF_INT BIT(16) BIT 126 drivers/crypto/qat/qat_common/adf_pf2vf_msg.h #define ADF_VF2PF_MSGORIGIN_SYSTEM BIT(17) BIT 64 drivers/crypto/qat/qat_common/adf_sriov.c #define ME2FUNCTION_MAP_VALID BIT(7) BIT 65 drivers/crypto/qat/qat_common/adf_vf_isr.c #define ADF_VINTSOU_BUN BIT(0) BIT 66 drivers/crypto/qat/qat_common/adf_vf_isr.c #define ADF_VINTSOU_PF2VF BIT(1) BIT 447 drivers/crypto/qat/qat_common/qat_hal.c #define ESRAM_AUTO_TINIT BIT(2) BIT 448 drivers/crypto/qat/qat_common/qat_hal.c #define ESRAM_AUTO_TINIT_DONE BIT(3) BIT 75 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h #define ADF_DH895XCC_ENABLE_AE_ECC_ERR BIT(28) BIT 76 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h #define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) BIT 79 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h #define ADF_DH895XCC_ERRSSMSH_EN BIT(3) BIT 135 drivers/crypto/qce/common.c cfg |= BIT(AUTH_LAST_SHIFT) | BIT(AUTH_FIRST_SHIFT); BIT 147 drivers/crypto/qce/common.c config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) | BIT 148 drivers/crypto/qce/common.c BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT); BIT 153 drivers/crypto/qce/common.c config |= BIT(LITTLE_ENDIAN_MODE_SHIFT); BIT 219 drivers/crypto/qce/common.c qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); BIT 282 drivers/crypto/qce/common.c auth_cfg |= BIT(AUTH_LAST_SHIFT); BIT 284 drivers/crypto/qce/common.c auth_cfg &= ~BIT(AUTH_LAST_SHIFT); BIT 287 drivers/crypto/qce/common.c auth_cfg |= BIT(AUTH_FIRST_SHIFT); BIT 289 drivers/crypto/qce/common.c auth_cfg &= ~BIT(AUTH_FIRST_SHIFT); BIT 364 drivers/crypto/qce/common.c encr_cfg |= BIT(ENCODE_SHIFT); BIT 402 drivers/crypto/qce/common.c (BIT(SW_ERR_SHIFT) | BIT(AXI_ERR_SHIFT) | BIT(HSD_ERR_SHIFT)) BIT 416 drivers/crypto/qce/common.c if (*status & STATUS_ERRORS || !(*status & BIT(OPERATION_DONE_SHIFT))) BIT 31 drivers/crypto/qce/common.h #define QCE_ALG_DES BIT(0) BIT 32 drivers/crypto/qce/common.h #define QCE_ALG_3DES BIT(1) BIT 33 drivers/crypto/qce/common.h #define QCE_ALG_AES BIT(2) BIT 36 drivers/crypto/qce/common.h #define QCE_HASH_SHA1 BIT(3) BIT 37 drivers/crypto/qce/common.h #define QCE_HASH_SHA256 BIT(4) BIT 38 drivers/crypto/qce/common.h #define QCE_HASH_SHA1_HMAC BIT(5) BIT 39 drivers/crypto/qce/common.h #define QCE_HASH_SHA256_HMAC BIT(6) BIT 40 drivers/crypto/qce/common.h #define QCE_HASH_AES_CMAC BIT(7) BIT 43 drivers/crypto/qce/common.h #define QCE_MODE_CBC BIT(8) BIT 44 drivers/crypto/qce/common.h #define QCE_MODE_ECB BIT(9) BIT 45 drivers/crypto/qce/common.h #define QCE_MODE_CTR BIT(10) BIT 46 drivers/crypto/qce/common.h #define QCE_MODE_XTS BIT(11) BIT 47 drivers/crypto/qce/common.h #define QCE_MODE_CCM BIT(12) BIT 51 drivers/crypto/qce/common.h #define QCE_ENCRYPT BIT(13) BIT 52 drivers/crypto/qce/common.h #define QCE_DECRYPT BIT(14) BIT 23 drivers/crypto/qcom-rng.c #define PRNG_CONFIG_HW_ENABLE BIT(1) BIT 24 drivers/crypto/qcom-rng.c #define PRNG_STATUS_DATA_AVAIL BIT(0) BIT 19 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_PKA_DONE_INT BIT(5) BIT 20 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HASH_DONE_INT BIT(4) BIT 21 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HRDMA_ERR_INT BIT(3) BIT 22 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HRDMA_DONE_INT BIT(2) BIT 23 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BCDMA_ERR_INT BIT(1) BIT 24 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BCDMA_DONE_INT BIT(0) BIT 27 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_PKA_DONE_ENA BIT(5) BIT 28 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HASH_DONE_ENA BIT(4) BIT 29 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HRDMA_ERR_ENA BIT(3) BIT 30 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HRDMA_DONE_ENA BIT(2) BIT 31 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BCDMA_ERR_ENA BIT(1) BIT 32 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BCDMA_DONE_ENA BIT(0) BIT 36 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TRNG_FLUSH BIT(9) BIT 37 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TRNG_START BIT(8) BIT 38 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_PKA_FLUSH BIT(7) BIT 39 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HASH_FLUSH BIT(6) BIT 40 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BLOCK_FLUSH BIT(5) BIT 41 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_PKA_START BIT(4) BIT 42 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HASH_START BIT(3) BIT 43 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BLOCK_START BIT(2) BIT 44 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_START BIT(1) BIT 45 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_AES_START BIT(0) BIT 49 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HR_ADDR_MODE BIT(8) BIT 51 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BT_ADDR_MODE BIT(7) BIT 53 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BR_ADDR_MODE BIT(6) BIT 54 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BYTESWAP_HRFIFO BIT(5) BIT 55 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BYTESWAP_BTFIFO BIT(4) BIT 56 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_BYTESWAP_BRFIFO BIT(3) BIT 58 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_DESSEL BIT(2) BIT 76 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_AES_BYTESWAP_CNT BIT(11) BIT 77 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_AES_BYTESWAP_KEY BIT(10) BIT 78 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_AES_BYTESWAP_IV BIT(9) BIT 79 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_AES_BYTESWAP_DO BIT(8) BIT 80 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_AES_BYTESWAP_DI BIT(7) BIT 81 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_AES_KEY_CHANGE BIT(6) BIT 89 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_AES_FIFO_MODE BIT(1) BIT 91 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_AES_DEC BIT(0) BIT 94 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_AES_DONE BIT(0) BIT 126 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_BYTESWAP_KEY BIT(8) BIT 127 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_BYTESWAP_IV BIT(7) BIT 128 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_BYTESWAP_DO BIT(6) BIT 129 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_BYTESWAP_DI BIT(5) BIT 131 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_CHAINMODE_CBC BIT(4) BIT 133 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_EEE BIT(3) BIT 135 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_SELECT BIT(2) BIT 137 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_FIFO_MODE BIT(1) BIT 139 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_DEC BIT(0) BIT 142 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_TDES_DONE BIT(0) BIT 159 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HASH_SWAP_DO BIT(3) BIT 160 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HASH_SWAP_DI BIT(2) BIT 167 drivers/crypto/rockchip/rk3288_crypto.h #define RK_CRYPTO_HASH_DONE BIT(0) BIT 13 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c #define RK_CRYPTO_DEC BIT(0) BIT 40 drivers/crypto/s5p-sss.c #define SSS_FCINTSTAT_HPARTINT BIT(7) BIT 41 drivers/crypto/s5p-sss.c #define SSS_FCINTSTAT_HDONEINT BIT(5) BIT 42 drivers/crypto/s5p-sss.c #define SSS_FCINTSTAT_BRDMAINT BIT(3) BIT 43 drivers/crypto/s5p-sss.c #define SSS_FCINTSTAT_BTDMAINT BIT(2) BIT 44 drivers/crypto/s5p-sss.c #define SSS_FCINTSTAT_HRDMAINT BIT(1) BIT 45 drivers/crypto/s5p-sss.c #define SSS_FCINTSTAT_PKDMAINT BIT(0) BIT 48 drivers/crypto/s5p-sss.c #define SSS_FCINTENSET_HPARTINTENSET BIT(7) BIT 49 drivers/crypto/s5p-sss.c #define SSS_FCINTENSET_HDONEINTENSET BIT(5) BIT 50 drivers/crypto/s5p-sss.c #define SSS_FCINTENSET_BRDMAINTENSET BIT(3) BIT 51 drivers/crypto/s5p-sss.c #define SSS_FCINTENSET_BTDMAINTENSET BIT(2) BIT 52 drivers/crypto/s5p-sss.c #define SSS_FCINTENSET_HRDMAINTENSET BIT(1) BIT 53 drivers/crypto/s5p-sss.c #define SSS_FCINTENSET_PKDMAINTENSET BIT(0) BIT 56 drivers/crypto/s5p-sss.c #define SSS_FCINTENCLR_HPARTINTENCLR BIT(7) BIT 57 drivers/crypto/s5p-sss.c #define SSS_FCINTENCLR_HDONEINTENCLR BIT(5) BIT 58 drivers/crypto/s5p-sss.c #define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3) BIT 59 drivers/crypto/s5p-sss.c #define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2) BIT 60 drivers/crypto/s5p-sss.c #define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1) BIT 61 drivers/crypto/s5p-sss.c #define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0) BIT 64 drivers/crypto/s5p-sss.c #define SSS_FCINTPEND_HPARTINTP BIT(7) BIT 65 drivers/crypto/s5p-sss.c #define SSS_FCINTPEND_HDONEINTP BIT(5) BIT 66 drivers/crypto/s5p-sss.c #define SSS_FCINTPEND_BRDMAINTP BIT(3) BIT 67 drivers/crypto/s5p-sss.c #define SSS_FCINTPEND_BTDMAINTP BIT(2) BIT 68 drivers/crypto/s5p-sss.c #define SSS_FCINTPEND_HRDMAINTP BIT(1) BIT 69 drivers/crypto/s5p-sss.c #define SSS_FCINTPEND_PKDMAINTP BIT(0) BIT 72 drivers/crypto/s5p-sss.c #define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7) BIT 73 drivers/crypto/s5p-sss.c #define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6) BIT 74 drivers/crypto/s5p-sss.c #define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5) BIT 75 drivers/crypto/s5p-sss.c #define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4) BIT 76 drivers/crypto/s5p-sss.c #define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3) BIT 77 drivers/crypto/s5p-sss.c #define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2) BIT 78 drivers/crypto/s5p-sss.c #define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1) BIT 79 drivers/crypto/s5p-sss.c #define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0) BIT 82 drivers/crypto/s5p-sss.c #define SSS_FCFIFOCTRL_DESSEL BIT(2) BIT 91 drivers/crypto/s5p-sss.c #define SSS_FCBRDMAC_BYTESWAP BIT(1) BIT 92 drivers/crypto/s5p-sss.c #define SSS_FCBRDMAC_FLUSH BIT(0) BIT 97 drivers/crypto/s5p-sss.c #define SSS_FCBTDMAC_BYTESWAP BIT(1) BIT 98 drivers/crypto/s5p-sss.c #define SSS_FCBTDMAC_FLUSH BIT(0) BIT 103 drivers/crypto/s5p-sss.c #define SSS_FCHRDMAC_BYTESWAP BIT(1) BIT 104 drivers/crypto/s5p-sss.c #define SSS_FCHRDMAC_FLUSH BIT(0) BIT 109 drivers/crypto/s5p-sss.c #define SSS_FCPKDMAC_BYTESWAP BIT(3) BIT 110 drivers/crypto/s5p-sss.c #define SSS_FCPKDMAC_DESCEND BIT(2) BIT 111 drivers/crypto/s5p-sss.c #define SSS_FCPKDMAC_TRANSMIT BIT(1) BIT 112 drivers/crypto/s5p-sss.c #define SSS_FCPKDMAC_FLUSH BIT(0) BIT 118 drivers/crypto/s5p-sss.c #define SSS_AES_BYTESWAP_DI BIT(11) BIT 119 drivers/crypto/s5p-sss.c #define SSS_AES_BYTESWAP_DO BIT(10) BIT 120 drivers/crypto/s5p-sss.c #define SSS_AES_BYTESWAP_IV BIT(9) BIT 121 drivers/crypto/s5p-sss.c #define SSS_AES_BYTESWAP_CNT BIT(8) BIT 122 drivers/crypto/s5p-sss.c #define SSS_AES_BYTESWAP_KEY BIT(7) BIT 123 drivers/crypto/s5p-sss.c #define SSS_AES_KEY_CHANGE_MODE BIT(6) BIT 127 drivers/crypto/s5p-sss.c #define SSS_AES_FIFO_MODE BIT(3) BIT 131 drivers/crypto/s5p-sss.c #define SSS_AES_MODE_DECRYPT BIT(0) BIT 134 drivers/crypto/s5p-sss.c #define SSS_AES_BUSY BIT(2) BIT 135 drivers/crypto/s5p-sss.c #define SSS_AES_INPUT_READY BIT(1) BIT 136 drivers/crypto/s5p-sss.c #define SSS_AES_OUTPUT_READY BIT(0) BIT 153 drivers/crypto/s5p-sss.c #define FLAGS_AES_DECRYPT BIT(0) BIT 164 drivers/crypto/s5p-sss.c #define SSS_HASH_USER_IV_EN BIT(5) BIT 165 drivers/crypto/s5p-sss.c #define SSS_HASH_INIT_BIT BIT(4) BIT 174 drivers/crypto/s5p-sss.c #define SSS_HASH_PAUSE BIT(0) BIT 178 drivers/crypto/s5p-sss.c #define SSS_HASH_FIFO_MODE_DMA BIT(0) BIT 183 drivers/crypto/s5p-sss.c #define SSS_HASH_BYTESWAP_DI BIT(3) BIT 184 drivers/crypto/s5p-sss.c #define SSS_HASH_BYTESWAP_DO BIT(2) BIT 185 drivers/crypto/s5p-sss.c #define SSS_HASH_BYTESWAP_IV BIT(1) BIT 186 drivers/crypto/s5p-sss.c #define SSS_HASH_BYTESWAP_KEY BIT(0) BIT 190 drivers/crypto/s5p-sss.c #define SSS_HASH_STATUS_MSG_DONE BIT(6) BIT 191 drivers/crypto/s5p-sss.c #define SSS_HASH_STATUS_PARTIAL_DONE BIT(4) BIT 192 drivers/crypto/s5p-sss.c #define SSS_HASH_STATUS_BUFFER_READY BIT(0) BIT 960 drivers/crypto/s5p-sss.c high = BIT(31); BIT 1341 drivers/crypto/s5p-sss.c dd->hash_flags &= ~(BIT(HASH_FLAGS_SGS_ALLOCED) | BIT 1342 drivers/crypto/s5p-sss.c BIT(HASH_FLAGS_SGS_COPIED)); BIT 1353 drivers/crypto/s5p-sss.c dd->hash_flags &= ~(BIT(HASH_FLAGS_BUSY) | BIT(HASH_FLAGS_FINAL) | BIT 1354 drivers/crypto/s5p-sss.c BIT(HASH_FLAGS_DMA_READY) | BIT 1355 drivers/crypto/s5p-sss.c BIT(HASH_FLAGS_OUTPUT_READY)); BIT 44 drivers/crypto/sahara.c #define FLAGS_ENCRYPT BIT(0) BIT 45 drivers/crypto/sahara.c #define FLAGS_CBC BIT(1) BIT 46 drivers/crypto/sahara.c #define FLAGS_NEW_KEY BIT(3) BIT 30 drivers/crypto/stm32/stm32-crc32.c #define CRC_CR_RESET BIT(0) BIT 31 drivers/crypto/stm32/stm32-crc32.c #define CRC_CR_REVERSE (BIT(7) | BIT(6) | BIT(5)) BIT 26 drivers/crypto/stm32/stm32-cryp.c #define FLG_ENCRYPT BIT(0) BIT 28 drivers/crypto/stm32/stm32-cryp.c #define FLG_AES BIT(1) BIT 29 drivers/crypto/stm32/stm32-cryp.c #define FLG_DES BIT(2) BIT 30 drivers/crypto/stm32/stm32-cryp.c #define FLG_TDES BIT(3) BIT 31 drivers/crypto/stm32/stm32-cryp.c #define FLG_ECB BIT(4) BIT 32 drivers/crypto/stm32/stm32-cryp.c #define FLG_CBC BIT(5) BIT 33 drivers/crypto/stm32/stm32-cryp.c #define FLG_CTR BIT(6) BIT 34 drivers/crypto/stm32/stm32-cryp.c #define FLG_GCM BIT(7) BIT 35 drivers/crypto/stm32/stm32-cryp.c #define FLG_CCM BIT(8) BIT 39 drivers/crypto/stm32/stm32-cryp.c #define FLG_CCM_PADDED_WA BIT(16) BIT 98 drivers/crypto/stm32/stm32-cryp.c #define IMSCR_IN BIT(0) BIT 99 drivers/crypto/stm32/stm32-cryp.c #define IMSCR_OUT BIT(1) BIT 101 drivers/crypto/stm32/stm32-cryp.c #define MISR_IN BIT(0) BIT 102 drivers/crypto/stm32/stm32-cryp.c #define MISR_OUT BIT(1) BIT 42 drivers/crypto/stm32/stm32-hash.c #define HASH_CR_INIT BIT(2) BIT 43 drivers/crypto/stm32/stm32-hash.c #define HASH_CR_DMAE BIT(3) BIT 45 drivers/crypto/stm32/stm32-hash.c #define HASH_CR_MODE BIT(6) BIT 46 drivers/crypto/stm32/stm32-hash.c #define HASH_CR_MDMAT BIT(13) BIT 47 drivers/crypto/stm32/stm32-hash.c #define HASH_CR_DMAA BIT(14) BIT 48 drivers/crypto/stm32/stm32-hash.c #define HASH_CR_LKEY BIT(16) BIT 56 drivers/crypto/stm32/stm32-hash.c #define HASH_DINIE BIT(0) BIT 57 drivers/crypto/stm32/stm32-hash.c #define HASH_DCIE BIT(1) BIT 60 drivers/crypto/stm32/stm32-hash.c #define HASH_MASK_CALC_COMPLETION BIT(0) BIT 61 drivers/crypto/stm32/stm32-hash.c #define HASH_MASK_DATA_INPUT BIT(1) BIT 67 drivers/crypto/stm32/stm32-hash.c #define HASH_SR_DATA_INPUT_READY BIT(0) BIT 68 drivers/crypto/stm32/stm32-hash.c #define HASH_SR_OUTPUT_READY BIT(1) BIT 69 drivers/crypto/stm32/stm32-hash.c #define HASH_SR_DMA_ACTIVE BIT(2) BIT 70 drivers/crypto/stm32/stm32-hash.c #define HASH_SR_BUSY BIT(3) BIT 74 drivers/crypto/stm32/stm32-hash.c #define HASH_STR_DCAL BIT(8) BIT 76 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_INIT BIT(0) BIT 77 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_OUTPUT_READY BIT(1) BIT 78 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_CPU BIT(2) BIT 79 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_DMA_READY BIT(3) BIT 80 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_DMA_ACTIVE BIT(4) BIT 81 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_HMAC_INIT BIT(5) BIT 82 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_HMAC_FINAL BIT(6) BIT 83 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_HMAC_KEY BIT(7) BIT 85 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_FINAL BIT(15) BIT 86 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_FINUP BIT(16) BIT 88 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_MD5 BIT(18) BIT 89 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_SHA1 BIT(19) BIT 90 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_SHA224 BIT(20) BIT 91 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_SHA256 BIT(21) BIT 92 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_ERRORS BIT(22) BIT 93 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_HMAC BIT(23) BIT 68 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_SECURE_MASK BIT(0) BIT 69 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_PRLG_MASK BIT(1) BIT 70 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_ALGODIR_MASK BIT(2) BIT 71 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_ALGOMODE_MASK (BIT(5) | BIT(4) | BIT(3)) BIT 72 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_DATATYPE_MASK (BIT(7) | BIT(6)) BIT 73 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_KEYSIZE_MASK (BIT(9) | BIT(8)) BIT 74 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_KEYRDEN_MASK BIT(10) BIT 75 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_KSE_MASK BIT(11) BIT 76 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_START_MASK BIT(12) BIT 77 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_INIT_MASK BIT(13) BIT 78 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_FFLUSH_MASK BIT(14) BIT 79 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_CR_CRYPEN_MASK BIT(15) BIT 90 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_SR_INFIFO_READY_MASK (BIT(0) | BIT(1)) BIT 91 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_SR_IFEM_MASK BIT(0) BIT 92 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_SR_BUSY_MASK BIT(4) BIT 114 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_DMA_REQ_MASK (BIT(1) | BIT(0)) BIT 43 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_SWITCHON_MASK BIT(31) BIT 46 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_EMPTYMSG_MASK BIT(20) BIT 49 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_DINF_MASK BIT(12) BIT 55 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_LKEY_MASK BIT(16) BIT 58 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_ALGO_MASK BIT(7) BIT 61 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_MODE_MASK BIT(6) BIT 64 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_DATAFORM_MASK (BIT(4) | BIT(5)) BIT 67 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_DMAE_MASK BIT(3) BIT 70 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_INIT_MASK BIT(2) BIT 73 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_PRIVN_MASK BIT(1) BIT 76 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CR_SECN_MASK BIT(0) BIT 80 drivers/crypto/ux500/hash/hash_alg.h #define HASH_STR_DCAL_MASK BIT(8) BIT 42 drivers/devfreq/event/exynos-nocp.h #define NOCP_MAIN_CTL_ERREN_MASK BIT(0) BIT 43 drivers/devfreq/event/exynos-nocp.h #define NOCP_MAIN_CTL_TRACEEN_MASK BIT(1) BIT 44 drivers/devfreq/event/exynos-nocp.h #define NOCP_MAIN_CTL_PAYLOADEN_MASK BIT(2) BIT 45 drivers/devfreq/event/exynos-nocp.h #define NOCP_MAIN_CTL_STATEN_MASK BIT(3) BIT 46 drivers/devfreq/event/exynos-nocp.h #define NOCP_MAIN_CTL_ALARMEN_MASK BIT(4) BIT 47 drivers/devfreq/event/exynos-nocp.h #define NOCP_MAIN_CTL_STATCONDDUMP_MASK BIT(5) BIT 48 drivers/devfreq/event/exynos-nocp.h #define NOCP_MAIN_CTL_INTRUSIVEMODE_MASK BIT(6) BIT 51 drivers/devfreq/event/exynos-nocp.h #define NOCP_CFG_CTL_GLOBALEN_MASK BIT(0) BIT 52 drivers/devfreq/event/exynos-nocp.h #define NOCP_CFG_CTL_ACTIVE_MASK BIT(1) BIT 76 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMNC_START_MODE_MASK BIT(16) BIT 77 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMNC_CC_DIVIDER_MASK BIT(3) BIT 78 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMNC_CC_RESET_MASK BIT(2) BIT 79 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMNC_COUNTER_RESET_MASK BIT(1) BIT 80 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMNC_ENABLE_MASK BIT(0) BIT 83 drivers/devfreq/event/exynos-ppmu.h #define PPMU_CCNT_MASK BIT(31) BIT 84 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMCNT3_MASK BIT(3) BIT 85 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMCNT2_MASK BIT(2) BIT 86 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMCNT1_MASK BIT(1) BIT 87 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMCNT0_MASK BIT(0) BIT 151 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMNC_START_MODE_MASK BIT(16) BIT 152 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMNC_CC_DIVIDER_MASK BIT(3) BIT 153 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMNC_CC_RESET_MASK BIT(2) BIT 154 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMNC_COUNTER_RESET_MASK BIT(1) BIT 155 drivers/devfreq/event/exynos-ppmu.h #define PPMU_PMNC_ENABLE_MASK BIT(0) BIT 27 drivers/devfreq/tegra30-devfreq.c #define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18) BIT 28 drivers/devfreq/tegra30-devfreq.c #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN BIT(20) BIT 29 drivers/devfreq/tegra30-devfreq.c #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN BIT(21) BIT 32 drivers/devfreq/tegra30-devfreq.c #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN BIT(29) BIT 33 drivers/devfreq/tegra30-devfreq.c #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN BIT(30) BIT 34 drivers/devfreq/tegra30-devfreq.c #define ACTMON_DEV_CTRL_ENB BIT(31) BIT 47 drivers/devfreq/tegra30-devfreq.c #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER BIT(31) BIT 48 drivers/devfreq/tegra30-devfreq.c #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER BIT(30) BIT 55 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_GEN_SOP BIT(8) BIT 56 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_GEN_EOP BIT(9) BIT 57 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_PARK_READS BIT(10) BIT 58 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_PARK_WRITES BIT(11) BIT 59 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_END_ON_EOP BIT(12) BIT 60 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_END_ON_LEN BIT(13) BIT 61 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14) BIT 62 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15) BIT 64 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_EARLY_DONE BIT(24) BIT 70 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_GO BIT(31) BIT 113 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_BUSY BIT(0) BIT 114 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY BIT(1) BIT 115 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_DESC_BUF_FULL BIT(2) BIT 116 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY BIT(3) BIT 117 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_RESP_BUF_FULL BIT(4) BIT 118 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_STOPPED BIT(5) BIT 119 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_RESETTING BIT(6) BIT 120 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_STOPPED_ON_ERR BIT(7) BIT 121 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY BIT(8) BIT 122 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_IRQ BIT(9) BIT 130 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_CTL_STOP BIT(0) BIT 131 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_CTL_RESET BIT(1) BIT 132 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_CTL_STOP_ON_ERR BIT(2) BIT 133 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_CTL_STOP_ON_EARLY BIT(3) BIT 134 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_CTL_GLOBAL_INTR BIT(4) BIT 135 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_CTL_STOP_DESCS BIT(5) BIT 149 drivers/dma/altera-msgdma.c #define MSGDMA_RESP_EARLY_TERM BIT(8) BIT 849 drivers/dma/altera-msgdma.c dma_dev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 850 drivers/dma/altera-msgdma.c dma_dev->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 851 drivers/dma/altera-msgdma.c dma_dev->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM) | BIT 852 drivers/dma/altera-msgdma.c BIT(DMA_MEM_TO_MEM); BIT 88 drivers/dma/amba-pl08x.c BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ BIT 89 drivers/dma/amba-pl08x.c BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 90 drivers/dma/amba-pl08x.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 91 drivers/dma/amba-pl08x.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) BIT 376 drivers/dma/amba-pl08x.c return !!(val & BIT(ch->id)); BIT 547 drivers/dma/amba-pl08x.c while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id)) BIT 655 drivers/dma/amba-pl08x.c writel(BIT(ch->id) | BIT(ch->id + 16), BIT 657 drivers/dma/amba-pl08x.c writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR); BIT 667 drivers/dma/amba-pl08x.c writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR); BIT 668 drivers/dma/amba-pl08x.c writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR); BIT 2312 drivers/dma/amba-pl08x.c if ((BIT(i) & err) || (BIT(i) & tc)) { BIT 2350 drivers/dma/amba-pl08x.c mask |= BIT(i); BIT 2746 drivers/dma/amba-pl08x.c (val & BIT(10)) ? "no" : "has", BIT 2747 drivers/dma/amba-pl08x.c (val & BIT(9)) ? "AHB0 and AHB1" : "AHB0", BIT 2748 drivers/dma/amba-pl08x.c (val & BIT(8)) ? "supports" : "does not support"); BIT 2751 drivers/dma/amba-pl08x.c if (!(val & BIT(8))) BIT 2755 drivers/dma/amba-pl08x.c vd->dualmaster = !!(val & BIT(9)); BIT 2773 drivers/dma/amba-pl08x.c pl08x->memcpy.directions = BIT(DMA_MEM_TO_MEM); BIT 2804 drivers/dma/amba-pl08x.c BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 41 drivers/dma/at_hdmac.c (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ BIT 42 drivers/dma/at_hdmac.c BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ BIT 43 drivers/dma/at_hdmac.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ BIT 44 drivers/dma/at_hdmac.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) BIT 1941 drivers/dma/at_hdmac.c atdma->dma_common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 52 drivers/dma/at_xdmac.c #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */ BIT 53 drivers/dma/at_xdmac.c #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */ BIT 54 drivers/dma/at_xdmac.c #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */ BIT 55 drivers/dma/at_xdmac.c #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */ BIT 56 drivers/dma/at_xdmac.c #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */ BIT 57 drivers/dma/at_xdmac.c #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */ BIT 58 drivers/dma/at_xdmac.c #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */ BIT 60 drivers/dma/at_xdmac.c #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */ BIT 61 drivers/dma/at_xdmac.c #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */ BIT 62 drivers/dma/at_xdmac.c #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */ BIT 63 drivers/dma/at_xdmac.c #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */ BIT 64 drivers/dma/at_xdmac.c #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */ BIT 65 drivers/dma/at_xdmac.c #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */ BIT 66 drivers/dma/at_xdmac.c #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */ BIT 68 drivers/dma/at_xdmac.c #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */ BIT 69 drivers/dma/at_xdmac.c #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */ BIT 70 drivers/dma/at_xdmac.c #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */ BIT 71 drivers/dma/at_xdmac.c #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */ BIT 72 drivers/dma/at_xdmac.c #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */ BIT 73 drivers/dma/at_xdmac.c #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */ BIT 74 drivers/dma/at_xdmac.c #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */ BIT 76 drivers/dma/at_xdmac.c #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */ BIT 77 drivers/dma/at_xdmac.c #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */ BIT 78 drivers/dma/at_xdmac.c #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */ BIT 79 drivers/dma/at_xdmac.c #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */ BIT 80 drivers/dma/at_xdmac.c #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */ BIT 81 drivers/dma/at_xdmac.c #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */ BIT 82 drivers/dma/at_xdmac.c #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */ BIT 171 drivers/dma/at_xdmac.c (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ BIT 172 drivers/dma/at_xdmac.c BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ BIT 173 drivers/dma/at_xdmac.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ BIT 174 drivers/dma/at_xdmac.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\ BIT 175 drivers/dma/at_xdmac.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) BIT 2058 drivers/dma/at_xdmac.c atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 68 drivers/dma/bcm-sba-raid.c #define SBA_INT_MASK BIT(0) BIT 70 drivers/dma/bcm-sba-raid.c #define SBA_RESP_MASK BIT(0) BIT 111 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_ACTIVE BIT(0) /* activate the DMA */ BIT 112 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_END BIT(1) /* current CB has ended */ BIT 113 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_INT BIT(2) /* interrupt status */ BIT 114 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_DREQ BIT(3) /* DREQ state */ BIT 115 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ BIT 116 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ BIT 117 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last BIT 120 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_ERR BIT(8) BIT 124 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_WAIT_FOR_WRITES BIT(28) BIT 125 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_DIS_DEBUG BIT(29) /* disable debug pause signal */ BIT 126 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */ BIT 127 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */ BIT 130 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_INT_EN BIT(0) BIT 131 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_TDMODE BIT(1) /* 2D-Mode */ BIT 132 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_WAIT_RESP BIT(3) /* wait for AXI-write to be acked */ BIT 133 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_D_INC BIT(4) BIT 134 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_D_WIDTH BIT(5) /* 128bit writes if set */ BIT 135 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_D_DREQ BIT(6) /* enable DREQ for destination */ BIT 136 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_D_IGNORE BIT(7) /* ignore destination writes */ BIT 137 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_S_INC BIT(8) BIT 138 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */ BIT 139 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */ BIT 140 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */ BIT 144 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */ BIT 147 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0) BIT 148 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1) BIT 149 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_DEBUG_READ_ERR BIT(2) BIT 158 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_DEBUG_LITE BIT(28) BIT 932 drivers/dma/bcm2835-dma.c od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 933 drivers/dma/bcm2835-dma.c od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 934 drivers/dma/bcm2835-dma.c od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | BIT 935 drivers/dma/bcm2835-dma.c BIT(DMA_MEM_TO_MEM); BIT 70 drivers/dma/dma-axi-dmac.c #define AXI_DMAC_CTRL_ENABLE BIT(0) BIT 71 drivers/dma/dma-axi-dmac.c #define AXI_DMAC_CTRL_PAUSE BIT(1) BIT 73 drivers/dma/dma-axi-dmac.c #define AXI_DMAC_IRQ_SOT BIT(0) BIT 74 drivers/dma/dma-axi-dmac.c #define AXI_DMAC_IRQ_EOT BIT(1) BIT 76 drivers/dma/dma-axi-dmac.c #define AXI_DMAC_FLAG_CYCLIC BIT(0) BIT 77 drivers/dma/dma-axi-dmac.c #define AXI_DMAC_FLAG_LAST BIT(1) BIT 78 drivers/dma/dma-axi-dmac.c #define AXI_DMAC_FLAG_PARTIAL_REPORT BIT(2) BIT 80 drivers/dma/dma-axi-dmac.c #define AXI_DMAC_FLAG_PARTIAL_XFER_DONE BIT(31) BIT 368 drivers/dma/dma-axi-dmac.c if (!(BIT(sg->id) & completed_transfers)) BIT 888 drivers/dma/dma-axi-dmac.c dma_dev->src_addr_widths = BIT(dmac->chan.src_width); BIT 889 drivers/dma/dma-axi-dmac.c dma_dev->dst_addr_widths = BIT(dmac->chan.dest_width); BIT 890 drivers/dma/dma-axi-dmac.c dma_dev->directions = BIT(dmac->chan.direction); BIT 48 drivers/dma/dma-jz4780.c #define JZ_DMA_DMAC_DMAE BIT(0) BIT 49 drivers/dma/dma-jz4780.c #define JZ_DMA_DMAC_AR BIT(2) BIT 50 drivers/dma/dma-jz4780.c #define JZ_DMA_DMAC_HLT BIT(3) BIT 51 drivers/dma/dma-jz4780.c #define JZ_DMA_DMAC_FAIC BIT(27) BIT 52 drivers/dma/dma-jz4780.c #define JZ_DMA_DMAC_FMSC BIT(31) BIT 56 drivers/dma/dma-jz4780.c #define JZ_DMA_DCS_CTE BIT(0) BIT 57 drivers/dma/dma-jz4780.c #define JZ_DMA_DCS_HLT BIT(2) BIT 58 drivers/dma/dma-jz4780.c #define JZ_DMA_DCS_TT BIT(3) BIT 59 drivers/dma/dma-jz4780.c #define JZ_DMA_DCS_AR BIT(4) BIT 60 drivers/dma/dma-jz4780.c #define JZ_DMA_DCS_DES8 BIT(30) BIT 62 drivers/dma/dma-jz4780.c #define JZ_DMA_DCM_LINK BIT(0) BIT 63 drivers/dma/dma-jz4780.c #define JZ_DMA_DCM_TIE BIT(1) BIT 64 drivers/dma/dma-jz4780.c #define JZ_DMA_DCM_STDE BIT(2) BIT 69 drivers/dma/dma-jz4780.c #define JZ_DMA_DCM_DAI BIT(22) BIT 70 drivers/dma/dma-jz4780.c #define JZ_DMA_DCM_SAI BIT(23) BIT 84 drivers/dma/dma-jz4780.c #define JZ_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 85 drivers/dma/dma-jz4780.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 86 drivers/dma/dma-jz4780.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) BIT 91 drivers/dma/dma-jz4780.c #define JZ_SOC_DATA_ALLOW_LEGACY_DT BIT(0) BIT 92 drivers/dma/dma-jz4780.c #define JZ_SOC_DATA_PROGRAMMABLE_DMA BIT(1) BIT 93 drivers/dma/dma-jz4780.c #define JZ_SOC_DATA_PER_CHAN_PM BIT(2) BIT 94 drivers/dma/dma-jz4780.c #define JZ_SOC_DATA_NO_DCKES_DCKEC BIT(3) BIT 95 drivers/dma/dma-jz4780.c #define JZ_SOC_DATA_BREAK_LINKS BIT(4) BIT 217 drivers/dma/dma-jz4780.c jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn)); BIT 226 drivers/dma/dma-jz4780.c jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn)); BIT 546 drivers/dma/dma-jz4780.c jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id)); BIT 736 drivers/dma/dma-jz4780.c pending &= ~BIT(i); BIT 786 drivers/dma/dma-jz4780.c } else if (jzdma->chan_reserved & BIT(jzchan->id)) { BIT 817 drivers/dma/dma-jz4780.c if (!(jzdma->chan_reserved & BIT(data.channel))) { BIT 934 drivers/dma/dma-jz4780.c dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 151 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT); BIT 152 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; BIT 161 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT | BIT 162 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; BIT 172 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT)); BIT 190 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c return __ffs(src | dst | len | BIT(max_width)); BIT 662 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT | BIT 663 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; BIT 688 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); BIT 689 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); BIT 905 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c dw->dma.directions = BIT(DMA_MEM_TO_MEM); BIT 163 drivers/dma/dw-axi-dmac/dw-axi-dmac.h #define DMAC_EN_MASK BIT(DMAC_EN_POS) BIT 166 drivers/dma/dw-axi-dmac/dw-axi-dmac.h #define INT_EN_MASK BIT(INT_EN_POS) BIT 175 drivers/dma/dw-axi-dmac/dw-axi-dmac.h #define CH_CTL_H_ARLEN_EN BIT(6) BIT 177 drivers/dma/dw-axi-dmac/dw-axi-dmac.h #define CH_CTL_H_AWLEN_EN BIT(15) BIT 194 drivers/dma/dw-axi-dmac/dw-axi-dmac.h #define CH_CTL_H_LLI_LAST BIT(30) BIT 195 drivers/dma/dw-axi-dmac/dw-axi-dmac.h #define CH_CTL_H_LLI_VALID BIT(31) BIT 198 drivers/dma/dw-axi-dmac/dw-axi-dmac.h #define CH_CTL_L_LAST_WRITE_EN BIT(30) BIT 226 drivers/dma/dw-axi-dmac/dw-axi-dmac.h #define CH_CTL_L_DST_MAST BIT(2) BIT 227 drivers/dma/dw-axi-dmac/dw-axi-dmac.h #define CH_CTL_L_SRC_MAST BIT(0) BIT 294 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_BLOCK_TRF = BIT(0), BIT 295 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_DMA_TRF = BIT(1), BIT 296 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_SRC_TRAN = BIT(3), BIT 297 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_DST_TRAN = BIT(4), BIT 298 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_SRC_DEC_ERR = BIT(5), BIT 299 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_DST_DEC_ERR = BIT(6), BIT 300 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_SRC_SLV_ERR = BIT(7), BIT 301 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_DST_SLV_ERR = BIT(8), BIT 302 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_LLI_RD_DEC_ERR = BIT(9), BIT 303 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_LLI_WR_DEC_ERR = BIT(10), BIT 304 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_LLI_RD_SLV_ERR = BIT(11), BIT 305 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_LLI_WR_SLV_ERR = BIT(12), BIT 306 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_INVALID_ERR = BIT(13), BIT 307 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR = BIT(14), BIT 308 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_DEC_ERR = BIT(16), BIT 309 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_WR2RO_ERR = BIT(17), BIT 310 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_RD2RWO_ERR = BIT(18), BIT 311 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_WRONCHEN_ERR = BIT(19), BIT 312 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_SHADOWREG_ERR = BIT(20), BIT 313 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_WRONHOLD_ERR = BIT(21), BIT 314 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_LOCK_CLEARED = BIT(27), BIT 315 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_SRC_SUSPENDED = BIT(28), BIT 316 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_SUSPENDED = BIT(29), BIT 317 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_DISABLED = BIT(30), BIT 318 drivers/dma/dw-axi-dmac/dw-axi-dmac.h DWAXIDMAC_IRQ_ABORTED = BIT(31), BIT 696 drivers/dma/dw-edma/dw-edma-core.c irq->wr_mask |= BIT(j); BIT 698 drivers/dma/dw-edma/dw-edma-core.c irq->rd_mask |= BIT(j); BIT 726 drivers/dma/dw-edma/dw-edma-core.c dma->directions = BIT(write ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV); BIT 727 drivers/dma/dw-edma/dw-edma-core.c dma->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 728 drivers/dma/dw-edma/dw-edma-core.c dma->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 74 drivers/dma/dw-edma/dw-edma-pcie.c err = pcim_iomap_regions(pdev, BIT(pdata->rg_bar) | BIT 75 drivers/dma/dw-edma/dw-edma-pcie.c BIT(pdata->ll_bar) | BIT 76 drivers/dma/dw-edma/dw-edma-pcie.c BIT(pdata->dt_bar), BIT 17 drivers/dma/dw-edma/dw-edma-v0-core.c DW_EDMA_V0_CB = BIT(0), BIT 18 drivers/dma/dw-edma/dw-edma-v0-core.c DW_EDMA_V0_TCB = BIT(1), BIT 19 drivers/dma/dw-edma/dw-edma-v0-core.c DW_EDMA_V0_LLP = BIT(2), BIT 20 drivers/dma/dw-edma/dw-edma-v0-core.c DW_EDMA_V0_LIE = BIT(3), BIT 21 drivers/dma/dw-edma/dw-edma-v0-core.c DW_EDMA_V0_RIE = BIT(4), BIT 22 drivers/dma/dw-edma/dw-edma-v0-core.c DW_EDMA_V0_CCS = BIT(8), BIT 23 drivers/dma/dw-edma/dw-edma-v0-core.c DW_EDMA_V0_LLE = BIT(9), BIT 79 drivers/dma/dw-edma/dw-edma-v0-core.c viewport_sel |= BIT(31); BIT 104 drivers/dma/dw-edma/dw-edma-v0-core.c viewport_sel |= BIT(31); BIT 171 drivers/dma/dw-edma/dw-edma-v0-core.c FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id))); BIT 179 drivers/dma/dw-edma/dw-edma-v0-core.c FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id))); BIT 246 drivers/dma/dw-edma/dw-edma-v0-core.c SET_RW(dw, chan->dir, engine_en, BIT(0)); BIT 249 drivers/dma/dw-edma/dw-edma-v0-core.c tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); BIT 250 drivers/dma/dw-edma/dw-edma-v0-core.c tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); BIT 254 drivers/dma/dw-edma/dw-edma-v0-core.c tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id)); BIT 304 drivers/dma/dw-edma/dw-edma-v0-core.c if (chan->id & BIT(0)) { BIT 79 drivers/dma/dw-edma/dw-edma-v0-debugfs.c viewport_sel = BIT(31); BIT 39 drivers/dma/dw/core.c BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ BIT 40 drivers/dma/dw/core.c BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 41 drivers/dma/dw/core.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 42 drivers/dma/dw/core.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) BIT 1219 drivers/dma/dw/core.c dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | BIT 1220 drivers/dma/dw/core.c BIT(DMA_MEM_TO_MEM); BIT 90 drivers/dma/dw/of.c pdata->data_width[tmp] = BIT(arr[tmp] & 0x07); BIT 32 drivers/dma/ep93xx_dma.c #define M2P_CONTROL_STALLINT BIT(0) BIT 33 drivers/dma/ep93xx_dma.c #define M2P_CONTROL_NFBINT BIT(1) BIT 34 drivers/dma/ep93xx_dma.c #define M2P_CONTROL_CH_ERROR_INT BIT(3) BIT 35 drivers/dma/ep93xx_dma.c #define M2P_CONTROL_ENABLE BIT(4) BIT 36 drivers/dma/ep93xx_dma.c #define M2P_CONTROL_ICE BIT(6) BIT 39 drivers/dma/ep93xx_dma.c #define M2P_INTERRUPT_STALL BIT(0) BIT 40 drivers/dma/ep93xx_dma.c #define M2P_INTERRUPT_NFB BIT(1) BIT 41 drivers/dma/ep93xx_dma.c #define M2P_INTERRUPT_ERROR BIT(3) BIT 58 drivers/dma/ep93xx_dma.c #define M2M_CONTROL_DONEINT BIT(2) BIT 59 drivers/dma/ep93xx_dma.c #define M2M_CONTROL_ENABLE BIT(3) BIT 60 drivers/dma/ep93xx_dma.c #define M2M_CONTROL_START BIT(4) BIT 61 drivers/dma/ep93xx_dma.c #define M2M_CONTROL_DAH BIT(11) BIT 62 drivers/dma/ep93xx_dma.c #define M2M_CONTROL_SAH BIT(12) BIT 71 drivers/dma/ep93xx_dma.c #define M2M_CONTROL_NFBINT BIT(21) BIT 76 drivers/dma/ep93xx_dma.c #define M2M_CONTROL_NO_HDSK BIT(24) BIT 95 drivers/dma/ep93xx_dma.c #define M2M_STATUS_DONE BIT(6) BIT 13 drivers/dma/fsl-edma-common.h #define EDMA_CR_EDBG BIT(1) BIT 14 drivers/dma/fsl-edma-common.h #define EDMA_CR_ERCA BIT(2) BIT 15 drivers/dma/fsl-edma-common.h #define EDMA_CR_ERGA BIT(3) BIT 16 drivers/dma/fsl-edma-common.h #define EDMA_CR_HOE BIT(4) BIT 17 drivers/dma/fsl-edma-common.h #define EDMA_CR_HALT BIT(5) BIT 18 drivers/dma/fsl-edma-common.h #define EDMA_CR_CLM BIT(6) BIT 19 drivers/dma/fsl-edma-common.h #define EDMA_CR_EMLM BIT(7) BIT 20 drivers/dma/fsl-edma-common.h #define EDMA_CR_ECX BIT(16) BIT 21 drivers/dma/fsl-edma-common.h #define EDMA_CR_CX BIT(17) BIT 33 drivers/dma/fsl-edma-common.h #define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0) BIT 34 drivers/dma/fsl-edma-common.h #define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1) BIT 35 drivers/dma/fsl-edma-common.h #define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1)) BIT 36 drivers/dma/fsl-edma-common.h #define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(3) | BIT(0)) BIT 46 drivers/dma/fsl-edma-common.h #define EDMA_TCD_CSR_START BIT(0) BIT 47 drivers/dma/fsl-edma-common.h #define EDMA_TCD_CSR_INT_MAJOR BIT(1) BIT 48 drivers/dma/fsl-edma-common.h #define EDMA_TCD_CSR_INT_HALF BIT(2) BIT 49 drivers/dma/fsl-edma-common.h #define EDMA_TCD_CSR_D_REQ BIT(3) BIT 50 drivers/dma/fsl-edma-common.h #define EDMA_TCD_CSR_E_SG BIT(4) BIT 51 drivers/dma/fsl-edma-common.h #define EDMA_TCD_CSR_E_LINK BIT(5) BIT 52 drivers/dma/fsl-edma-common.h #define EDMA_TCD_CSR_ACTIVE BIT(6) BIT 53 drivers/dma/fsl-edma-common.h #define EDMA_TCD_CSR_DONE BIT(7) BIT 61 drivers/dma/fsl-edma-common.h #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 62 drivers/dma/fsl-edma-common.h BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 63 drivers/dma/fsl-edma-common.h BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ BIT 64 drivers/dma/fsl-edma-common.h BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) BIT 378 drivers/dma/fsl-edma.c fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 58 drivers/dma/fsl-qdma.c #define FSL_QDMA_CQIDR_SQT BIT(15) BIT 59 drivers/dma/fsl-qdma.c #define QDMA_CCDF_FOTMAT BIT(29) BIT 60 drivers/dma/fsl-qdma.c #define QDMA_CCDF_SER BIT(30) BIT 61 drivers/dma/fsl-qdma.c #define QDMA_SG_FIN BIT(30) BIT 69 drivers/dma/fsl-qdma.c #define FSL_QDMA_BCQIER_CQTIE BIT(15) BIT 70 drivers/dma/fsl-qdma.c #define FSL_QDMA_BCQIER_CQPEIE BIT(23) BIT 71 drivers/dma/fsl-qdma.c #define FSL_QDMA_BSQICR_ICEN BIT(31) BIT 74 drivers/dma/fsl-qdma.c #define FSL_QDMA_CQIER_MEIE BIT(31) BIT 75 drivers/dma/fsl-qdma.c #define FSL_QDMA_CQIER_TEIE BIT(0) BIT 76 drivers/dma/fsl-qdma.c #define FSL_QDMA_SQCCMR_ENTER_WM BIT(21) BIT 78 drivers/dma/fsl-qdma.c #define FSL_QDMA_BCQMR_EN BIT(31) BIT 79 drivers/dma/fsl-qdma.c #define FSL_QDMA_BCQMR_EI BIT(30) BIT 83 drivers/dma/fsl-qdma.c #define FSL_QDMA_BCQSR_QF BIT(16) BIT 84 drivers/dma/fsl-qdma.c #define FSL_QDMA_BCQSR_XOFF BIT(0) BIT 86 drivers/dma/fsl-qdma.c #define FSL_QDMA_BSQMR_EN BIT(31) BIT 87 drivers/dma/fsl-qdma.c #define FSL_QDMA_BSQMR_DI BIT(30) BIT 90 drivers/dma/fsl-qdma.c #define FSL_QDMA_BSQSR_QE BIT(17) BIT 92 drivers/dma/fsl-qdma.c #define FSL_QDMA_DMR_DQD BIT(30) BIT 93 drivers/dma/fsl-qdma.c #define FSL_QDMA_DSR_DB BIT(31) BIT 45 drivers/dma/fsl_raid.h #define FSL_RE_DPAA_MODE BIT(30) BIT 46 drivers/dma/fsl_raid.h #define FSL_RE_NON_DPAA_MODE BIT(31) BIT 70 drivers/dma/fsl_raid.h #define FSL_RE_ADDR_BIT_MASK (BIT(FSL_RE_ADDR_BIT_SHIFT) - 1) BIT 1252 drivers/dma/fsldma.c fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 85 drivers/dma/fsldma.h #define FSL_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 86 drivers/dma/fsldma.h BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 87 drivers/dma/fsldma.h BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ BIT 88 drivers/dma/fsldma.h BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) BIT 29 drivers/dma/hsu/hsu.c BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ BIT 30 drivers/dma/hsu/hsu.c BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 31 drivers/dma/hsu/hsu.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 32 drivers/dma/hsu/hsu.c BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT 33 drivers/dma/hsu/hsu.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ BIT 34 drivers/dma/hsu/hsu.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \ BIT 35 drivers/dma/hsu/hsu.c BIT(DMA_SLAVE_BUSWIDTH_16_BYTES) BIT 466 drivers/dma/hsu/hsu.c hsu->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 38 drivers/dma/hsu/hsu.h #define HSU_CH_SR_DESCTO(x) BIT(8 + (x)) BIT 39 drivers/dma/hsu/hsu.h #define HSU_CH_SR_DESCTO_ANY (BIT(11) | BIT(10) | BIT(9) | BIT(8)) BIT 40 drivers/dma/hsu/hsu.h #define HSU_CH_SR_CHE BIT(15) BIT 41 drivers/dma/hsu/hsu.h #define HSU_CH_SR_DESCE(x) BIT(16 + (x)) BIT 42 drivers/dma/hsu/hsu.h #define HSU_CH_SR_DESCE_ANY (BIT(19) | BIT(18) | BIT(17) | BIT(16)) BIT 43 drivers/dma/hsu/hsu.h #define HSU_CH_SR_CDESC_ANY (BIT(31) | BIT(30)) BIT 46 drivers/dma/hsu/hsu.h #define HSU_CH_CR_CHA BIT(0) BIT 47 drivers/dma/hsu/hsu.h #define HSU_CH_CR_CHD BIT(1) BIT 50 drivers/dma/hsu/hsu.h #define HSU_CH_DCR_DESCA(x) BIT(0 + (x)) BIT 51 drivers/dma/hsu/hsu.h #define HSU_CH_DCR_CHSOD(x) BIT(8 + (x)) BIT 52 drivers/dma/hsu/hsu.h #define HSU_CH_DCR_CHSOTO BIT(14) BIT 53 drivers/dma/hsu/hsu.h #define HSU_CH_DCR_CHSOE BIT(15) BIT 54 drivers/dma/hsu/hsu.h #define HSU_CH_DCR_CHDI(x) BIT(16 + (x)) BIT 55 drivers/dma/hsu/hsu.h #define HSU_CH_DCR_CHEI BIT(23) BIT 56 drivers/dma/hsu/hsu.h #define HSU_CH_DCR_CHTOI(x) BIT(24 + (x)) BIT 69 drivers/dma/hsu/pci.c ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); BIT 525 drivers/dma/idma64.c BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 526 drivers/dma/idma64.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 527 drivers/dma/idma64.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) BIT 566 drivers/dma/idma64.c idma64c->mask = BIT(i); BIT 588 drivers/dma/idma64.c idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 34 drivers/dma/img-mdc-dma.c #define MDC_GENERAL_CONFIG_LIST_IEN BIT(31) BIT 35 drivers/dma/img-mdc-dma.c #define MDC_GENERAL_CONFIG_IEN BIT(29) BIT 36 drivers/dma/img-mdc-dma.c #define MDC_GENERAL_CONFIG_LEVEL_INT BIT(28) BIT 37 drivers/dma/img-mdc-dma.c #define MDC_GENERAL_CONFIG_INC_W BIT(12) BIT 38 drivers/dma/img-mdc-dma.c #define MDC_GENERAL_CONFIG_INC_R BIT(8) BIT 39 drivers/dma/img-mdc-dma.c #define MDC_GENERAL_CONFIG_PHYSICAL_W BIT(7) BIT 42 drivers/dma/img-mdc-dma.c #define MDC_GENERAL_CONFIG_PHYSICAL_R BIT(3) BIT 55 drivers/dma/img-mdc-dma.c #define MDC_READ_PORT_CONFIG_DREQ_ENABLE BIT(1) BIT 69 drivers/dma/img-mdc-dma.c #define MDC_CMDS_PROCESSED_INT_ACTIVE BIT(8) BIT 74 drivers/dma/img-mdc-dma.c #define MDC_CONTROL_AND_STATUS_CANCEL BIT(20) BIT 75 drivers/dma/img-mdc-dma.c #define MDC_CONTROL_AND_STATUS_LIST_EN BIT(4) BIT 76 drivers/dma/img-mdc-dma.c #define MDC_CONTROL_AND_STATUS_EN BIT(0) BIT 820 drivers/dma/img-mdc-dma.c if (!(dma_spec->args[1] & BIT(mchan->chan_nr))) BIT 961 drivers/dma/img-mdc-dma.c mdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 964 drivers/dma/img-mdc-dma.c mdma->dma_dev.src_addr_widths |= BIT(i); BIT 965 drivers/dma/img-mdc-dma.c mdma->dma_dev.dst_addr_widths |= BIT(i); BIT 166 drivers/dma/imx-sdma.c #define SDMA_WATERMARK_LEVEL_PS BIT(8) BIT 167 drivers/dma/imx-sdma.c #define SDMA_WATERMARK_LEVEL_PA BIT(9) BIT 168 drivers/dma/imx-sdma.c #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) BIT 169 drivers/dma/imx-sdma.c #define SDMA_WATERMARK_LEVEL_SP BIT(11) BIT 170 drivers/dma/imx-sdma.c #define SDMA_WATERMARK_LEVEL_DP BIT(12) BIT 172 drivers/dma/imx-sdma.c #define SDMA_WATERMARK_LEVEL_LWE BIT(28) BIT 173 drivers/dma/imx-sdma.c #define SDMA_WATERMARK_LEVEL_HWE BIT(29) BIT 174 drivers/dma/imx-sdma.c #define SDMA_WATERMARK_LEVEL_CONT BIT(31) BIT 176 drivers/dma/imx-sdma.c #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 177 drivers/dma/imx-sdma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 178 drivers/dma/imx-sdma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) BIT 180 drivers/dma/imx-sdma.c #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \ BIT 181 drivers/dma/imx-sdma.c BIT(DMA_MEM_TO_DEV) | \ BIT 182 drivers/dma/imx-sdma.c BIT(DMA_DEV_TO_DEV)) BIT 385 drivers/dma/imx-sdma.c #define IMX_DMA_SG_LOOP BIT(0) BIT 612 drivers/dma/imx-sdma.c #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ BIT 613 drivers/dma/imx-sdma.c #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ BIT 614 drivers/dma/imx-sdma.c #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ BIT 661 drivers/dma/imx-sdma.c writel(BIT(channel), sdma->regs + SDMA_H_START); BIT 1052 drivers/dma/imx-sdma.c writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); BIT 1842 drivers/dma/imx-sdma.c regmap_update_bits(gpr, reg, BIT(shift), val << shift); BIT 55 drivers/dma/k3dma.c #define CX_CFG_NODEIRQ BIT(1) BIT 116 drivers/dma/k3dma.c #define K3_FLAG_NOCLK BIT(1) BIT 224 drivers/dma/k3dma.c stat &= ~BIT(i); BIT 225 drivers/dma/k3dma.c if (likely(tc1 & BIT(i)) || (tc2 & BIT(i))) { BIT 230 drivers/dma/k3dma.c if (c && (tc1 & BIT(i))) { BIT 239 drivers/dma/k3dma.c if (c && (tc2 & BIT(i))) { BIT 245 drivers/dma/k3dma.c irq_chan |= BIT(i); BIT 247 drivers/dma/k3dma.c if (unlikely((err1 & BIT(i)) || (err2 & BIT(i)))) BIT 273 drivers/dma/k3dma.c if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d)) BIT 909 drivers/dma/k3dma.c if (!(d->dma_channel_mask & BIT(i))) BIT 32 drivers/dma/mcf-edma.c if (intmap & BIT(ch)) { BIT 69 drivers/dma/mcf-edma.c if (err & BIT(ch)) { BIT 82 drivers/dma/mcf-edma.c if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) { BIT 257 drivers/dma/mcf-edma.c BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 32 drivers/dma/mediatek/mtk-cqdma.c #define MTK_CQDMA_DMA_BUSWIDTHS BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) BIT 55 drivers/dma/mediatek/mtk-cqdma.c #define MTK_CQDMA_EN_BIT BIT(0) BIT 56 drivers/dma/mediatek/mtk-cqdma.c #define MTK_CQDMA_INT_FLAG_BIT BIT(0) BIT 57 drivers/dma/mediatek/mtk-cqdma.c #define MTK_CQDMA_INT_EN_BIT BIT(0) BIT 58 drivers/dma/mediatek/mtk-cqdma.c #define MTK_CQDMA_FLUSH_BIT BIT(0) BIT 60 drivers/dma/mediatek/mtk-cqdma.c #define MTK_CQDMA_WARM_RST_BIT BIT(0) BIT 61 drivers/dma/mediatek/mtk-cqdma.c #define MTK_CQDMA_HARD_RST_BIT BIT(1) BIT 782 drivers/dma/mediatek/mtk-cqdma.c dd->directions = BIT(DMA_MEM_TO_MEM); BIT 31 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_DMA_BUSWIDTHS BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) BIT 62 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_GLO_MULTI_DMA BIT(10) BIT 63 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_TX_WB_DDONE BIT(6) BIT 65 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_GLO_RX_BUSY BIT(3) BIT 66 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_GLO_RX_DMA BIT(2) BIT 67 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_GLO_TX_BUSY BIT(1) BIT 68 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_GLO_TX_DMA BIT(0) BIT 81 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_RST_TX BIT(0) BIT 82 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_RST_RX BIT(16) BIT 86 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_RXDLY_INT_EN BIT(15) BIT 98 drivers/dma/mediatek/mtk-hsdma.c #define MTK_HSDMA_INT_RXDONE BIT(16) BIT 878 drivers/dma/mediatek/mtk-hsdma.c .ddone = BIT(31), BIT 879 drivers/dma/mediatek/mtk-hsdma.c .ls0 = BIT(30), BIT 883 drivers/dma/mediatek/mtk-hsdma.c .ddone = BIT(15), BIT 884 drivers/dma/mediatek/mtk-hsdma.c .ls0 = BIT(14), BIT 948 drivers/dma/mediatek/mtk-hsdma.c dd->directions = BIT(DMA_MEM_TO_MEM); BIT 31 drivers/dma/mediatek/mtk-uart-apdma.c #define VFF_EN_B BIT(0) BIT 32 drivers/dma/mediatek/mtk-uart-apdma.c #define VFF_STOP_B BIT(0) BIT 33 drivers/dma/mediatek/mtk-uart-apdma.c #define VFF_FLUSH_B BIT(0) BIT 34 drivers/dma/mediatek/mtk-uart-apdma.c #define VFF_4G_EN_B BIT(0) BIT 36 drivers/dma/mediatek/mtk-uart-apdma.c #define VFF_RX_INT_EN_B (BIT(0) | BIT(1)) BIT 38 drivers/dma/mediatek/mtk-uart-apdma.c #define VFF_TX_INT_EN_B BIT(0) BIT 39 drivers/dma/mediatek/mtk-uart-apdma.c #define VFF_WARM_RST_B BIT(0) BIT 40 drivers/dma/mediatek/mtk-uart-apdma.c #define VFF_RX_INT_CLR_B (BIT(0) | BIT(1)) BIT 514 drivers/dma/mediatek/mtk-uart-apdma.c mtkd->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE); BIT 515 drivers/dma/mediatek/mtk-uart-apdma.c mtkd->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE); BIT 516 drivers/dma/mediatek/mtk-uart-apdma.c mtkd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 33 drivers/dma/mmp_pdma.c #define DCSR_RUN BIT(31) /* Run Bit (read / write) */ BIT 34 drivers/dma/mmp_pdma.c #define DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */ BIT 35 drivers/dma/mmp_pdma.c #define DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (read / write) */ BIT 36 drivers/dma/mmp_pdma.c #define DCSR_REQPEND BIT(8) /* Request Pending (read-only) */ BIT 37 drivers/dma/mmp_pdma.c #define DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */ BIT 38 drivers/dma/mmp_pdma.c #define DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */ BIT 39 drivers/dma/mmp_pdma.c #define DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */ BIT 40 drivers/dma/mmp_pdma.c #define DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */ BIT 42 drivers/dma/mmp_pdma.c #define DCSR_EORIRQEN BIT(28) /* End of Receive Interrupt Enable (R/W) */ BIT 43 drivers/dma/mmp_pdma.c #define DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */ BIT 44 drivers/dma/mmp_pdma.c #define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */ BIT 45 drivers/dma/mmp_pdma.c #define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */ BIT 46 drivers/dma/mmp_pdma.c #define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */ BIT 47 drivers/dma/mmp_pdma.c #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ BIT 48 drivers/dma/mmp_pdma.c #define DCSR_EORINTR BIT(9) /* The end of Receive */ BIT 51 drivers/dma/mmp_pdma.c #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ BIT 55 drivers/dma/mmp_pdma.c #define DDADR_STOP BIT(0) /* Stop (read / write) */ BIT 57 drivers/dma/mmp_pdma.c #define DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */ BIT 58 drivers/dma/mmp_pdma.c #define DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */ BIT 59 drivers/dma/mmp_pdma.c #define DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */ BIT 60 drivers/dma/mmp_pdma.c #define DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */ BIT 61 drivers/dma/mmp_pdma.c #define DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */ BIT 62 drivers/dma/mmp_pdma.c #define DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */ BIT 63 drivers/dma/mmp_pdma.c #define DCMD_ENDIAN BIT(18) /* Device Endian-ness. */ BIT 190 drivers/dma/mmp_pdma.c if (!(dint & BIT(phy->idx))) BIT 1105 drivers/dma/mmp_pdma.c pdev->device.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); BIT 41 drivers/dma/moxart-dma.c #define APB_DMA_ENABLE BIT(0) BIT 42 drivers/dma/moxart-dma.c #define APB_DMA_FIN_INT_STS BIT(1) BIT 43 drivers/dma/moxart-dma.c #define APB_DMA_FIN_INT_EN BIT(2) BIT 44 drivers/dma/moxart-dma.c #define APB_DMA_BURST_MODE BIT(3) BIT 45 drivers/dma/moxart-dma.c #define APB_DMA_ERR_INT_STS BIT(4) BIT 46 drivers/dma/moxart-dma.c #define APB_DMA_ERR_INT_EN BIT(5) BIT 161 drivers/dma/mv_xor.c writel(BIT(0), XOR_ACTIVATION(chan)); BIT 26 drivers/dma/mv_xor.h #define XOR_DESCRIPTOR_SWAP BIT(14) BIT 33 drivers/dma/mv_xor.h #define XOR_DESC_DMA_OWNED BIT(31) BIT 34 drivers/dma/mv_xor.h #define XOR_DESC_EOD_INT_EN BIT(31) BIT 51 drivers/dma/mv_xor.h #define XOR_INT_END_OF_DESC BIT(0) BIT 52 drivers/dma/mv_xor.h #define XOR_INT_END_OF_CHAIN BIT(1) BIT 53 drivers/dma/mv_xor.h #define XOR_INT_STOPPED BIT(2) BIT 54 drivers/dma/mv_xor.h #define XOR_INT_PAUSED BIT(3) BIT 55 drivers/dma/mv_xor.h #define XOR_INT_ERR_DECODE BIT(4) BIT 56 drivers/dma/mv_xor.h #define XOR_INT_ERR_RDPROT BIT(5) BIT 57 drivers/dma/mv_xor.h #define XOR_INT_ERR_WRPROT BIT(6) BIT 58 drivers/dma/mv_xor.h #define XOR_INT_ERR_OWN BIT(7) BIT 59 drivers/dma/mv_xor.h #define XOR_INT_ERR_PAR BIT(8) BIT 60 drivers/dma/mv_xor.h #define XOR_INT_ERR_MBUS BIT(9) BIT 36 drivers/dma/mv_xor_v2.c #define MV_XOR_V2_DMA_IMSG_TIMER_EN BIT(18) BIT 125 drivers/dma/mv_xor_v2.c #define DESC_Q_BUFFER_ENABLE BIT(16) BIT 126 drivers/dma/mv_xor_v2.c #define DESC_P_BUFFER_ENABLE BIT(17) BIT 127 drivers/dma/mv_xor_v2.c #define DESC_IOD BIT(27) BIT 843 drivers/dma/mxs-dma.c mxs_dma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 844 drivers/dma/mxs-dma.c mxs_dma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 845 drivers/dma/mxs-dma.c mxs_dma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 92 drivers/dma/nbpfaxi.c (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ BIT 93 drivers/dma/nbpfaxi.c BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 94 drivers/dma/nbpfaxi.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 95 drivers/dma/nbpfaxi.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ BIT 96 drivers/dma/nbpfaxi.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) BIT 341 drivers/dma/nbpfaxi.c return status & BIT(chan - chan->nbpf->chan); BIT 1427 drivers/dma/nbpfaxi.c dma_dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 86 drivers/dma/owl-dma.c #define OWL_DMA_MODE_CB BIT(23) BIT 90 drivers/dma/owl-dma.c #define OWL_DMA_MODE_CFE BIT(29) BIT 91 drivers/dma/owl-dma.c #define OWL_DMA_MODE_LME BIT(30) BIT 92 drivers/dma/owl-dma.c #define OWL_DMA_MODE_CME BIT(31) BIT 103 drivers/dma/owl-dma.c #define OWL_DMA_LLC_SUSPEND BIT(16) BIT 106 drivers/dma/owl-dma.c #define OWL_DMA_INTCTL_BLOCK BIT(0) BIT 107 drivers/dma/owl-dma.c #define OWL_DMA_INTCTL_SUPER_BLOCK BIT(1) BIT 108 drivers/dma/owl-dma.c #define OWL_DMA_INTCTL_FRAME BIT(2) BIT 109 drivers/dma/owl-dma.c #define OWL_DMA_INTCTL_HALF_FRAME BIT(3) BIT 110 drivers/dma/owl-dma.c #define OWL_DMA_INTCTL_LAST_FRAME BIT(4) BIT 113 drivers/dma/owl-dma.c #define OWL_DMA_INTSTAT_BLOCK BIT(0) BIT 114 drivers/dma/owl-dma.c #define OWL_DMA_INTSTAT_SUPER_BLOCK BIT(1) BIT 115 drivers/dma/owl-dma.c #define OWL_DMA_INTSTAT_FRAME BIT(2) BIT 116 drivers/dma/owl-dma.c #define OWL_DMA_INTSTAT_HALF_FRAME BIT(3) BIT 117 drivers/dma/owl-dma.c #define OWL_DMA_INTSTAT_LAST_FRAME BIT(4) BIT 121 drivers/dma/owl-dma.c ((((val) >> (shift)) & ((BIT(width)) - 1)) << (newshift)) BIT 585 drivers/dma/owl-dma.c if (chan_irq_pending && !(global_irq_pending & BIT(i))) { BIT 594 drivers/dma/owl-dma.c pending |= BIT(i); BIT 1099 drivers/dma/owl-dma.c od->dma.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 1100 drivers/dma/owl-dma.c od->dma.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 1101 drivers/dma/owl-dma.c od->dma.directions = BIT(DMA_MEM_TO_MEM); BIT 36 drivers/dma/pl330.c #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0) BIT 2899 drivers/dma/pl330.c BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ BIT 2900 drivers/dma/pl330.c BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 2901 drivers/dma/pl330.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 2902 drivers/dma/pl330.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ BIT 2903 drivers/dma/pl330.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) BIT 3135 drivers/dma/pl330.c pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 35 drivers/dma/pxa_dma.c #define PXA_DCSR_RUN BIT(31) /* Run Bit (read / write) */ BIT 36 drivers/dma/pxa_dma.c #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */ BIT 37 drivers/dma/pxa_dma.c #define PXA_DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (R/W) */ BIT 38 drivers/dma/pxa_dma.c #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */ BIT 39 drivers/dma/pxa_dma.c #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */ BIT 40 drivers/dma/pxa_dma.c #define PXA_DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */ BIT 41 drivers/dma/pxa_dma.c #define PXA_DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */ BIT 42 drivers/dma/pxa_dma.c #define PXA_DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */ BIT 44 drivers/dma/pxa_dma.c #define PXA_DCSR_EORIRQEN BIT(28) /* End of Receive IRQ Enable (R/W) */ BIT 45 drivers/dma/pxa_dma.c #define PXA_DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */ BIT 46 drivers/dma/pxa_dma.c #define PXA_DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */ BIT 47 drivers/dma/pxa_dma.c #define PXA_DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */ BIT 48 drivers/dma/pxa_dma.c #define PXA_DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */ BIT 49 drivers/dma/pxa_dma.c #define PXA_DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ BIT 50 drivers/dma/pxa_dma.c #define PXA_DCSR_EORINTR BIT(9) /* The end of Receive */ BIT 52 drivers/dma/pxa_dma.c #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ BIT 56 drivers/dma/pxa_dma.c #define DDADR_STOP BIT(0) /* Stop (read / write) */ BIT 58 drivers/dma/pxa_dma.c #define PXA_DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */ BIT 59 drivers/dma/pxa_dma.c #define PXA_DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */ BIT 60 drivers/dma/pxa_dma.c #define PXA_DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */ BIT 61 drivers/dma/pxa_dma.c #define PXA_DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */ BIT 62 drivers/dma/pxa_dma.c #define PXA_DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */ BIT 63 drivers/dma/pxa_dma.c #define PXA_DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */ BIT 64 drivers/dma/pxa_dma.c #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */ BIT 280 drivers/dma/pxa_dma.c _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ? BIT 447 drivers/dma/pxa_dma.c return dalgn & (BIT(chan->phy->idx)); BIT 470 drivers/dma/pxa_dma.c dalgn |= BIT(phy->idx); BIT 472 drivers/dma/pxa_dma.c dalgn &= ~BIT(phy->idx); BIT 589 drivers/dma/pxa_dma.c if (!(dint & BIT(phy->idx))) BIT 1410 drivers/dma/pxa_dma.c pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); BIT 56 drivers/dma/qcom/bam_dma.c #define DESC_FLAG_INT BIT(15) BIT 57 drivers/dma/qcom/bam_dma.c #define DESC_FLAG_EOT BIT(14) BIT 58 drivers/dma/qcom/bam_dma.c #define DESC_FLAG_EOB BIT(13) BIT 59 drivers/dma/qcom/bam_dma.c #define DESC_FLAG_NWD BIT(12) BIT 60 drivers/dma/qcom/bam_dma.c #define DESC_FLAG_CMD BIT(11) BIT 202 drivers/dma/qcom/bam_dma.c #define BAM_SW_RST BIT(0) BIT 203 drivers/dma/qcom/bam_dma.c #define BAM_EN BIT(1) BIT 204 drivers/dma/qcom/bam_dma.c #define BAM_EN_ACCUM BIT(4) BIT 209 drivers/dma/qcom/bam_dma.c #define BAM_CACHED_DESC_STORE BIT(15) BIT 210 drivers/dma/qcom/bam_dma.c #define IBC_DISABLE BIT(16) BIT 217 drivers/dma/qcom/bam_dma.c #define CE_BUFFER_SIZE BIT(13) BIT 218 drivers/dma/qcom/bam_dma.c #define AXI_ACTIVE BIT(14) BIT 219 drivers/dma/qcom/bam_dma.c #define USE_VMIDMT BIT(15) BIT 220 drivers/dma/qcom/bam_dma.c #define SECURED BIT(16) BIT 221 drivers/dma/qcom/bam_dma.c #define BAM_HAS_NO_BYPASS BIT(17) BIT 222 drivers/dma/qcom/bam_dma.c #define HIGH_FREQUENCY_BAM BIT(18) BIT 223 drivers/dma/qcom/bam_dma.c #define INACTIV_TMRS_EXST BIT(19) BIT 224 drivers/dma/qcom/bam_dma.c #define NUM_INACTIV_TMRS BIT(20) BIT 230 drivers/dma/qcom/bam_dma.c #define CMD_DESC_EN BIT(23) BIT 243 drivers/dma/qcom/bam_dma.c #define BAM_PIPE_CNFG BIT(2) BIT 244 drivers/dma/qcom/bam_dma.c #define BAM_FULL_PIPE BIT(11) BIT 245 drivers/dma/qcom/bam_dma.c #define BAM_NO_EXT_P_RST BIT(12) BIT 246 drivers/dma/qcom/bam_dma.c #define BAM_IBC_DISABLE BIT(13) BIT 247 drivers/dma/qcom/bam_dma.c #define BAM_SB_CLK_REQ BIT(14) BIT 248 drivers/dma/qcom/bam_dma.c #define BAM_PSM_CSW_REQ BIT(15) BIT 249 drivers/dma/qcom/bam_dma.c #define BAM_PSM_P_RES BIT(16) BIT 250 drivers/dma/qcom/bam_dma.c #define BAM_AU_P_RES BIT(17) BIT 251 drivers/dma/qcom/bam_dma.c #define BAM_SI_P_RES BIT(18) BIT 252 drivers/dma/qcom/bam_dma.c #define BAM_WB_P_RES BIT(19) BIT 253 drivers/dma/qcom/bam_dma.c #define BAM_WB_BLK_CSW BIT(20) BIT 254 drivers/dma/qcom/bam_dma.c #define BAM_WB_CSW_ACK_IDL BIT(21) BIT 255 drivers/dma/qcom/bam_dma.c #define BAM_WB_RETR_SVPNT BIT(22) BIT 256 drivers/dma/qcom/bam_dma.c #define BAM_WB_DSC_AVL_P_RST BIT(23) BIT 257 drivers/dma/qcom/bam_dma.c #define BAM_REG_P_EN BIT(24) BIT 258 drivers/dma/qcom/bam_dma.c #define BAM_PSM_P_HD_DATA BIT(25) BIT 259 drivers/dma/qcom/bam_dma.c #define BAM_AU_ACCUMED BIT(26) BIT 260 drivers/dma/qcom/bam_dma.c #define BAM_CMD_ENABLE BIT(27) BIT 281 drivers/dma/qcom/bam_dma.c #define P_EN BIT(1) BIT 282 drivers/dma/qcom/bam_dma.c #define P_DIRECTION BIT(3) BIT 283 drivers/dma/qcom/bam_dma.c #define P_SYS_STRM BIT(4) BIT 284 drivers/dma/qcom/bam_dma.c #define P_SYS_MODE BIT(5) BIT 285 drivers/dma/qcom/bam_dma.c #define P_AUTO_EOB BIT(6) BIT 295 drivers/dma/qcom/bam_dma.c #define P_WRITE_NWD BIT(11) BIT 304 drivers/dma/qcom/bam_dma.c #define BAM_IRQ BIT(31) BIT 312 drivers/dma/qcom/bam_dma.c #define BAM_TIMER_IRQ BIT(4) BIT 313 drivers/dma/qcom/bam_dma.c #define BAM_EMPTY_IRQ BIT(3) BIT 314 drivers/dma/qcom/bam_dma.c #define BAM_ERROR_IRQ BIT(2) BIT 315 drivers/dma/qcom/bam_dma.c #define BAM_HRESP_ERR_IRQ BIT(1) BIT 318 drivers/dma/qcom/bam_dma.c #define BAM_TIMER_CLR BIT(4) BIT 319 drivers/dma/qcom/bam_dma.c #define BAM_EMPTY_CLR BIT(3) BIT 320 drivers/dma/qcom/bam_dma.c #define BAM_ERROR_CLR BIT(2) BIT 321 drivers/dma/qcom/bam_dma.c #define BAM_HRESP_ERR_CLR BIT(1) BIT 324 drivers/dma/qcom/bam_dma.c #define BAM_TIMER_EN BIT(4) BIT 325 drivers/dma/qcom/bam_dma.c #define BAM_EMPTY_EN BIT(3) BIT 326 drivers/dma/qcom/bam_dma.c #define BAM_ERROR_EN BIT(2) BIT 327 drivers/dma/qcom/bam_dma.c #define BAM_HRESP_ERR_EN BIT(1) BIT 330 drivers/dma/qcom/bam_dma.c #define P_PRCSD_DESC_EN BIT(0) BIT 331 drivers/dma/qcom/bam_dma.c #define P_TIMER_EN BIT(1) BIT 332 drivers/dma/qcom/bam_dma.c #define P_WAKE_EN BIT(2) BIT 333 drivers/dma/qcom/bam_dma.c #define P_OUT_OF_DESC_EN BIT(3) BIT 334 drivers/dma/qcom/bam_dma.c #define P_ERR_EN BIT(4) BIT 335 drivers/dma/qcom/bam_dma.c #define P_TRNSFR_END_EN BIT(5) BIT 473 drivers/dma/qcom/bam_dma.c val |= BIT(bchan->id); BIT 563 drivers/dma/qcom/bam_dma.c val &= ~BIT(bchan->id); BIT 804 drivers/dma/qcom/bam_dma.c if (!(srcs & BIT(i))) BIT 1333 drivers/dma/qcom/bam_dma.c bdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 61 drivers/dma/qcom/hidma_ll.c #define ENABLE_IRQS (BIT(HIDMA_IRQ_EV_CH_EOB_IRQ_BIT_POS) | \ BIT 62 drivers/dma/qcom/hidma_ll.c BIT(HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS) | \ BIT 63 drivers/dma/qcom/hidma_ll.c BIT(HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS) | \ BIT 64 drivers/dma/qcom/hidma_ll.c BIT(HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS) | \ BIT 65 drivers/dma/qcom/hidma_ll.c BIT(HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS) | \ BIT 66 drivers/dma/qcom/hidma_ll.c BIT(HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS)) BIT 79 drivers/dma/qcom/hidma_ll.c (BIT(HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS) | \ BIT 80 drivers/dma/qcom/hidma_ll.c BIT(HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS) | \ BIT 81 drivers/dma/qcom/hidma_ll.c BIT(HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS) | \ BIT 82 drivers/dma/qcom/hidma_ll.c BIT(HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS) | \ BIT 83 drivers/dma/qcom/hidma_ll.c BIT(HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS)) BIT 166 drivers/dma/qcom/hidma_ll.c tre_local[HIDMA_TRE_CFG_IDX] |= BIT(16); /* set IEOB */ BIT 46 drivers/dma/s3c24xx-dma.c #define S3C24XX_DISRCC_INC_FIXED BIT(0) BIT 48 drivers/dma/s3c24xx-dma.c #define S3C24XX_DISRCC_LOC_APB BIT(1) BIT 53 drivers/dma/s3c24xx-dma.c #define S3C24XX_DIDSTC_INC_FIXED BIT(0) BIT 55 drivers/dma/s3c24xx-dma.c #define S3C24XX_DIDSTC_LOC_APB BIT(1) BIT 57 drivers/dma/s3c24xx-dma.c #define S3C24XX_DIDSTC_INT_RELOAD BIT(2) BIT 68 drivers/dma/s3c24xx-dma.c #define S3C24XX_DCON_NORELOAD BIT(22) BIT 69 drivers/dma/s3c24xx-dma.c #define S3C24XX_DCON_HWTRIG BIT(23) BIT 72 drivers/dma/s3c24xx-dma.c #define S3C24XX_DCON_SERV_WHOLE BIT(27) BIT 74 drivers/dma/s3c24xx-dma.c #define S3C24XX_DCON_TSZ_BURST4 BIT(28) BIT 75 drivers/dma/s3c24xx-dma.c #define S3C24XX_DCON_INT BIT(29) BIT 77 drivers/dma/s3c24xx-dma.c #define S3C24XX_DCON_SYNC_HCLK BIT(30) BIT 79 drivers/dma/s3c24xx-dma.c #define S3C24XX_DCON_HANDSHAKE BIT(31) BIT 82 drivers/dma/s3c24xx-dma.c #define S3C24XX_DSTAT_STAT_BUSY BIT(20) BIT 86 drivers/dma/s3c24xx-dma.c #define S3C24XX_DMASKTRIG_SWTRIG BIT(0) BIT 87 drivers/dma/s3c24xx-dma.c #define S3C24XX_DMASKTRIG_ON BIT(1) BIT 88 drivers/dma/s3c24xx-dma.c #define S3C24XX_DMASKTRIG_STOP BIT(2) BIT 91 drivers/dma/s3c24xx-dma.c #define S3C24XX_DMAREQSEL_HW BIT(0) BIT 112 drivers/dma/s3c24xx-dma.c #define S3C24XX_CHANSEL_VALID BIT(3) BIT 958 drivers/dma/sa11x0-dma.c d->slave.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 960 drivers/dma/sa11x0-dma.c d->slave.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 961 drivers/dma/sa11x0-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES); BIT 962 drivers/dma/sa11x0-dma.c d->slave.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 963 drivers/dma/sa11x0-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES); BIT 819 drivers/dma/sh/rcar-dmac.c if (!(dmac->channels_mask & BIT(i))) BIT 1843 drivers/dma/sh/rcar-dmac.c dmac->channels_mask &= ~BIT(0); BIT 1883 drivers/dma/sh/rcar-dmac.c engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); BIT 1901 drivers/dma/sh/rcar-dmac.c if (!(dmac->channels_mask & BIT(i))) BIT 733 drivers/dma/sh/shdmac.c dma_dev->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); BIT 837 drivers/dma/sh/usb-dmac.c engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); BIT 68 drivers/dma/sirf-dma.c #define SIRFSOC_DMA_INT_FINI_INT_ATLAS7 BIT(0) BIT 69 drivers/dma/sirf-dma.c #define SIRFSOC_DMA_INT_CNT_INT_ATLAS7 BIT(1) BIT 70 drivers/dma/sirf-dma.c #define SIRFSOC_DMA_INT_PAU_INT_ATLAS7 BIT(2) BIT 71 drivers/dma/sirf-dma.c #define SIRFSOC_DMA_INT_LOOP_INT_ATLAS7 BIT(3) BIT 72 drivers/dma/sirf-dma.c #define SIRFSOC_DMA_INT_INV_INT_ATLAS7 BIT(4) BIT 73 drivers/dma/sirf-dma.c #define SIRFSOC_DMA_INT_END_INT_ATLAS7 BIT(5) BIT 821 drivers/dma/sirf-dma.c (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ BIT 822 drivers/dma/sirf-dma.c BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 823 drivers/dma/sirf-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 824 drivers/dma/sirf-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ BIT 825 drivers/dma/sirf-dma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) BIT 917 drivers/dma/sirf-dma.c dma->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 63 drivers/dma/sprd-dma.c #define SPRD_DMA_GLB_2STAGE_EN BIT(24) BIT 65 drivers/dma/sprd-dma.c #define SPRD_DMA_GLB_DEST_INT BIT(22) BIT 66 drivers/dma/sprd-dma.c #define SPRD_DMA_GLB_SRC_INT BIT(20) BIT 67 drivers/dma/sprd-dma.c #define SPRD_DMA_GLB_LIST_DONE_TRG BIT(19) BIT 68 drivers/dma/sprd-dma.c #define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18) BIT 69 drivers/dma/sprd-dma.c #define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17) BIT 70 drivers/dma/sprd-dma.c #define SPRD_DMA_GLB_FRAG_DONE_TRG BIT(16) BIT 79 drivers/dma/sprd-dma.c #define SPRD_DMA_FRAG_INT_EN BIT(0) BIT 80 drivers/dma/sprd-dma.c #define SPRD_DMA_BLK_INT_EN BIT(1) BIT 81 drivers/dma/sprd-dma.c #define SPRD_DMA_TRANS_INT_EN BIT(2) BIT 82 drivers/dma/sprd-dma.c #define SPRD_DMA_LIST_INT_EN BIT(3) BIT 83 drivers/dma/sprd-dma.c #define SPRD_DMA_CFG_ERR_INT_EN BIT(4) BIT 86 drivers/dma/sprd-dma.c #define SPRD_DMA_CHN_EN BIT(0) BIT 87 drivers/dma/sprd-dma.c #define SPRD_DMA_LINKLIST_EN BIT(4) BIT 92 drivers/dma/sprd-dma.c #define SPRD_DMA_REQ_EN BIT(0) BIT 95 drivers/dma/sprd-dma.c #define SPRD_DMA_PAUSE_EN BIT(0) BIT 96 drivers/dma/sprd-dma.c #define SPRD_DMA_PAUSE_STS BIT(2) BIT 105 drivers/dma/sprd-dma.c #define SPRD_DMA_FRAG_INT_STS BIT(16) BIT 106 drivers/dma/sprd-dma.c #define SPRD_DMA_BLK_INT_STS BIT(17) BIT 107 drivers/dma/sprd-dma.c #define SPRD_DMA_TRSC_INT_STS BIT(18) BIT 108 drivers/dma/sprd-dma.c #define SPRD_DMA_LIST_INT_STS BIT(19) BIT 109 drivers/dma/sprd-dma.c #define SPRD_DMA_CFGERR_INT_STS BIT(20) BIT 123 drivers/dma/sprd-dma.c #define SPRD_DMA_LLIST_END BIT(19) BIT 439 drivers/dma/sprd-dma.c val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; BIT 449 drivers/dma/sprd-dma.c val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; BIT 721 drivers/dma/st_fdma.c #define FDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 722 drivers/dma/st_fdma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 723 drivers/dma/st_fdma.c BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT 724 drivers/dma/st_fdma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) BIT 802 drivers/dma/st_fdma.c fdev->dreq_mask = BIT(0) | BIT(31); BIT 823 drivers/dma/st_fdma.c fdev->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 68 drivers/dma/st_fdma.h #define FDMA_NODE_CTRL_SRC_STATIC BIT(5) BIT 69 drivers/dma/st_fdma.h #define FDMA_NODE_CTRL_SRC_INCR BIT(6) BIT 71 drivers/dma/st_fdma.h #define FDMA_NODE_CTRL_DST_STATIC BIT(7) BIT 72 drivers/dma/st_fdma.h #define FDMA_NODE_CTRL_DST_INCR BIT(8) BIT 73 drivers/dma/st_fdma.h #define FDMA_NODE_CTRL_SECURE BIT(15) BIT 74 drivers/dma/st_fdma.h #define FDMA_NODE_CTRL_PAUSE_EON BIT(30) BIT 75 drivers/dma/st_fdma.h #define FDMA_NODE_CTRL_INT_EON BIT(31) BIT 222 drivers/dma/st_fdma.h #define FDMA_REQ_CTRL_INITIATOR_MASK BIT(22) BIT 225 drivers/dma/st_fdma.h #define FDMA_REQ_CTRL_INC_ADDR_ON BIT(21) BIT 226 drivers/dma/st_fdma.h #define FDMA_REQ_CTRL_DATA_SWAP_ON BIT(17) BIT 227 drivers/dma/st_fdma.h #define FDMA_REQ_CTRL_WNR BIT(14) BIT 58 drivers/dma/ste_dma40.c #define D40_ALLOC_FREE BIT(31) BIT 59 drivers/dma/ste_dma40.c #define D40_ALLOC_PHY BIT(30) BIT 1684 drivers/dma/ste_dma40.c writel(BIT(idx), base->virtbase + il[row].clr); BIT 1774 drivers/dma/ste_dma40.c if (!(phy->allocated_src & BIT(log_event_line))) { BIT 1775 drivers/dma/ste_dma40.c phy->allocated_src |= BIT(log_event_line); BIT 1786 drivers/dma/ste_dma40.c if (!(phy->allocated_dst & BIT(log_event_line))) { BIT 1787 drivers/dma/ste_dma40.c phy->allocated_dst |= BIT(log_event_line); BIT 1815 drivers/dma/ste_dma40.c phy->allocated_src &= ~BIT(log_event_line); BIT 1819 drivers/dma/ste_dma40.c phy->allocated_dst &= ~BIT(log_event_line); BIT 1975 drivers/dma/ste_dma40.c d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS); BIT 1978 drivers/dma/ste_dma40.c d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS); BIT 1979 drivers/dma/ste_dma40.c d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS); BIT 2300 drivers/dma/ste_dma40.c u32 bit = BIT(event); BIT 2430 drivers/dma/ste_dma40.c d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS); BIT 2431 drivers/dma/ste_dma40.c d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS); BIT 2819 drivers/dma/ste_dma40.c dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 2824 drivers/dma/ste_dma40.c dev->directions = BIT(DMA_MEM_TO_MEM); BIT 35 drivers/dma/ste_dma40_ll.c l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS); BIT 40 drivers/dma/ste_dma40_ll.c l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS); BIT 45 drivers/dma/ste_dma40_ll.c l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS); BIT 50 drivers/dma/ste_dma40_ll.c l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS); BIT 52 drivers/dma/ste_dma40_ll.c l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS); BIT 57 drivers/dma/ste_dma40_ll.c l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS); BIT 75 drivers/dma/ste_dma40_ll.c src |= BIT(D40_SREG_CFG_MST_POS); BIT 79 drivers/dma/ste_dma40_ll.c src |= BIT(D40_SREG_CFG_PHY_TM_POS); BIT 86 drivers/dma/ste_dma40_ll.c dst |= BIT(D40_SREG_CFG_MST_POS); BIT 90 drivers/dma/ste_dma40_ll.c dst |= BIT(D40_SREG_CFG_PHY_TM_POS); BIT 95 drivers/dma/ste_dma40_ll.c dst |= BIT(D40_SREG_CFG_TIM_POS); BIT 98 drivers/dma/ste_dma40_ll.c src |= BIT(D40_SREG_CFG_EIM_POS); BIT 99 drivers/dma/ste_dma40_ll.c dst |= BIT(D40_SREG_CFG_EIM_POS); BIT 103 drivers/dma/ste_dma40_ll.c src |= BIT(D40_SREG_CFG_PHY_PEN_POS); BIT 107 drivers/dma/ste_dma40_ll.c dst |= BIT(D40_SREG_CFG_PHY_PEN_POS); BIT 119 drivers/dma/ste_dma40_ll.c src |= BIT(D40_SREG_CFG_PRI_POS); BIT 120 drivers/dma/ste_dma40_ll.c dst |= BIT(D40_SREG_CFG_PRI_POS); BIT 124 drivers/dma/ste_dma40_ll.c src |= BIT(D40_SREG_CFG_LBE_POS); BIT 126 drivers/dma/ste_dma40_ll.c dst |= BIT(D40_SREG_CFG_LBE_POS); BIT 175 drivers/dma/ste_dma40_ll.c lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS); BIT 181 drivers/dma/ste_dma40_ll.c lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS); BIT 183 drivers/dma/ste_dma40_ll.c lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS); BIT 36 drivers/dma/stm32-dma.c #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */ BIT 37 drivers/dma/stm32-dma.c #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */ BIT 38 drivers/dma/stm32-dma.c #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ BIT 39 drivers/dma/stm32-dma.c #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ BIT 40 drivers/dma/stm32-dma.c #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ BIT 62 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */ BIT 63 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */ BIT 64 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */ BIT 65 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */ BIT 66 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */ BIT 67 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */ BIT 68 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */ BIT 69 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable BIT 71 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */ BIT 72 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */ BIT 73 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */ BIT 98 drivers/dma/stm32-dma.c #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */ BIT 99 drivers/dma/stm32-dma.c #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */ BIT 1331 drivers/dma/stm32-dma.c dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1332 drivers/dma/stm32-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1333 drivers/dma/stm32-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 1334 drivers/dma/stm32-dma.c dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1335 drivers/dma/stm32-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1336 drivers/dma/stm32-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 1337 drivers/dma/stm32-dma.c dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 1346 drivers/dma/stm32-dma.c dd->directions |= BIT(DMA_MEM_TO_MEM); BIT 47 drivers/dma/stm32-mdma.c #define STM32_MDMA_CISR_CRQA BIT(16) BIT 48 drivers/dma/stm32-mdma.c #define STM32_MDMA_CISR_TCIF BIT(4) BIT 49 drivers/dma/stm32-mdma.c #define STM32_MDMA_CISR_BTIF BIT(3) BIT 50 drivers/dma/stm32-mdma.c #define STM32_MDMA_CISR_BRTIF BIT(2) BIT 51 drivers/dma/stm32-mdma.c #define STM32_MDMA_CISR_CTCIF BIT(1) BIT 52 drivers/dma/stm32-mdma.c #define STM32_MDMA_CISR_TEIF BIT(0) BIT 56 drivers/dma/stm32-mdma.c #define STM32_MDMA_CIFCR_CLTCIF BIT(4) BIT 57 drivers/dma/stm32-mdma.c #define STM32_MDMA_CIFCR_CBTIF BIT(3) BIT 58 drivers/dma/stm32-mdma.c #define STM32_MDMA_CIFCR_CBRTIF BIT(2) BIT 59 drivers/dma/stm32-mdma.c #define STM32_MDMA_CIFCR_CCTCIF BIT(1) BIT 60 drivers/dma/stm32-mdma.c #define STM32_MDMA_CIFCR_CTEIF BIT(0) BIT 69 drivers/dma/stm32-mdma.c #define STM32_MDMA_CESR_BSE BIT(11) BIT 70 drivers/dma/stm32-mdma.c #define STM32_MDMA_CESR_ASR BIT(10) BIT 71 drivers/dma/stm32-mdma.c #define STM32_MDMA_CESR_TEMD BIT(9) BIT 72 drivers/dma/stm32-mdma.c #define STM32_MDMA_CESR_TELD BIT(8) BIT 73 drivers/dma/stm32-mdma.c #define STM32_MDMA_CESR_TED BIT(7) BIT 78 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_SWRQ BIT(16) BIT 79 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_WEX BIT(14) BIT 80 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_HEX BIT(13) BIT 81 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_BEX BIT(12) BIT 85 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_TCIE BIT(5) BIT 86 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_BTIE BIT(4) BIT 87 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_BRTIE BIT(3) BIT 88 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_CTCIE BIT(2) BIT 89 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_TEIE BIT(1) BIT 90 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_EN BIT(0) BIT 99 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_BWM BIT(31) BIT 100 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_SWRM BIT(30) BIT 109 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_PKE BIT(25) BIT 159 drivers/dma/stm32-mdma.c #define STM32_MDMA_CBNDTR_BRDUM BIT(19) BIT 160 drivers/dma/stm32-mdma.c #define STM32_MDMA_CBNDTR_BRSUM BIT(18) BIT 185 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTBR_DBUS BIT(17) BIT 186 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTBR_SBUS BIT(16) BIT 1617 drivers/dma/stm32-mdma.c dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1618 drivers/dma/stm32-mdma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1619 drivers/dma/stm32-mdma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT 1620 drivers/dma/stm32-mdma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); BIT 1621 drivers/dma/stm32-mdma.c dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1622 drivers/dma/stm32-mdma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1623 drivers/dma/stm32-mdma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT 1624 drivers/dma/stm32-mdma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); BIT 1625 drivers/dma/stm32-mdma.c dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | BIT 1626 drivers/dma/stm32-mdma.c BIT(DMA_MEM_TO_MEM); BIT 23 drivers/dma/sun4i-dma.c #define SUN4I_DMA_CFG_LOADING BIT(31) BIT 46 drivers/dma/sun4i-dma.c #define SUN4I_NDMA_CFG_CONT_MODE BIT(30) BIT 48 drivers/dma/sun4i-dma.c #define SUN4I_NDMA_CFG_DST_NON_SECURE BIT(22) BIT 49 drivers/dma/sun4i-dma.c #define SUN4I_NDMA_CFG_BYTE_COUNT_MODE_REMAIN BIT(15) BIT 50 drivers/dma/sun4i-dma.c #define SUN4I_NDMA_CFG_SRC_NON_SECURE BIT(6) BIT 67 drivers/dma/sun4i-dma.c #define SUN4I_DDMA_CFG_BUSY BIT(30) BIT 68 drivers/dma/sun4i-dma.c #define SUN4I_DDMA_CFG_CONT_MODE BIT(29) BIT 69 drivers/dma/sun4i-dma.c #define SUN4I_DDMA_CFG_DST_NON_SECURE BIT(28) BIT 70 drivers/dma/sun4i-dma.c #define SUN4I_DDMA_CFG_BYTE_COUNT_MODE_REMAIN BIT(15) BIT 71 drivers/dma/sun4i-dma.c #define SUN4I_DDMA_CFG_SRC_NON_SECURE BIT(12) BIT 296 drivers/dma/sun4i-dma.c reg |= BIT(pchan_number * 2); BIT 298 drivers/dma/sun4i-dma.c reg &= ~BIT(pchan_number * 2); BIT 301 drivers/dma/sun4i-dma.c reg |= BIT(pchan_number * 2 + 1); BIT 303 drivers/dma/sun4i-dma.c reg &= ~BIT(pchan_number * 2 + 1); BIT 1066 drivers/dma/sun4i-dma.c disableirqs |= BIT(bit); BIT 1076 drivers/dma/sun4i-dma.c disableirqs |= BIT(bit); BIT 1163 drivers/dma/sun4i-dma.c priv->slave.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1164 drivers/dma/sun4i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1165 drivers/dma/sun4i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 1166 drivers/dma/sun4i-dma.c priv->slave.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1167 drivers/dma/sun4i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1168 drivers/dma/sun4i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 1169 drivers/dma/sun4i-dma.c priv->slave.directions = BIT(DMA_DEV_TO_MEM) | BIT 1170 drivers/dma/sun4i-dma.c BIT(DMA_MEM_TO_DEV); BIT 29 drivers/dma/sun6i-dma.c #define DMA_IRQ_HALF BIT(0) BIT 30 drivers/dma/sun6i-dma.c #define DMA_IRQ_PKG BIT(1) BIT 31 drivers/dma/sun6i-dma.c #define DMA_IRQ_QUEUE BIT(2) BIT 57 drivers/dma/sun6i-dma.c #define DMA_CHAN_ENABLE_START BIT(0) BIT 61 drivers/dma/sun6i-dma.c #define DMA_CHAN_PAUSE_PAUSE BIT(1) BIT 511 drivers/dma/sun6i-dma.c pchan_alloc |= BIT(pchan_idx); BIT 522 drivers/dma/sun6i-dma.c if (!(pchan_alloc & BIT(pchan_idx))) BIT 607 drivers/dma/sun6i-dma.c if (!(BIT(src_addr_width) & sdev->slave.src_addr_widths)) BIT 609 drivers/dma/sun6i-dma.c if (!(BIT(dst_addr_width) & sdev->slave.dst_addr_widths)) BIT 611 drivers/dma/sun6i-dma.c if (!(BIT(src_maxburst) & sdev->cfg->src_burst_lengths)) BIT 613 drivers/dma/sun6i-dma.c if (!(BIT(dst_maxburst) & sdev->cfg->dst_burst_lengths)) BIT 1077 drivers/dma/sun6i-dma.c .src_burst_lengths = BIT(1) | BIT(8), BIT 1078 drivers/dma/sun6i-dma.c .dst_burst_lengths = BIT(1) | BIT(8), BIT 1079 drivers/dma/sun6i-dma.c .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1080 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1081 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), BIT 1082 drivers/dma/sun6i-dma.c .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1083 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1084 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), BIT 1100 drivers/dma/sun6i-dma.c .src_burst_lengths = BIT(1) | BIT(8), BIT 1101 drivers/dma/sun6i-dma.c .dst_burst_lengths = BIT(1) | BIT(8), BIT 1102 drivers/dma/sun6i-dma.c .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1103 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1104 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), BIT 1105 drivers/dma/sun6i-dma.c .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1106 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1107 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), BIT 1118 drivers/dma/sun6i-dma.c .src_burst_lengths = BIT(1) | BIT(8), BIT 1119 drivers/dma/sun6i-dma.c .dst_burst_lengths = BIT(1) | BIT(8), BIT 1120 drivers/dma/sun6i-dma.c .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1121 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1122 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), BIT 1123 drivers/dma/sun6i-dma.c .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1124 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1125 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), BIT 1143 drivers/dma/sun6i-dma.c .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), BIT 1144 drivers/dma/sun6i-dma.c .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), BIT 1145 drivers/dma/sun6i-dma.c .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1146 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1147 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT 1148 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), BIT 1149 drivers/dma/sun6i-dma.c .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1150 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1151 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT 1152 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), BIT 1164 drivers/dma/sun6i-dma.c .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), BIT 1165 drivers/dma/sun6i-dma.c .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), BIT 1166 drivers/dma/sun6i-dma.c .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1167 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1168 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT 1169 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), BIT 1170 drivers/dma/sun6i-dma.c .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1171 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1172 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT 1173 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), BIT 1185 drivers/dma/sun6i-dma.c .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), BIT 1186 drivers/dma/sun6i-dma.c .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), BIT 1187 drivers/dma/sun6i-dma.c .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1188 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1189 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT 1190 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), BIT 1191 drivers/dma/sun6i-dma.c .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1192 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1193 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT 1194 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), BIT 1211 drivers/dma/sun6i-dma.c .src_burst_lengths = BIT(1) | BIT(8), BIT 1212 drivers/dma/sun6i-dma.c .dst_burst_lengths = BIT(1) | BIT(8), BIT 1213 drivers/dma/sun6i-dma.c .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1214 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1215 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), BIT 1216 drivers/dma/sun6i-dma.c .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1217 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1218 drivers/dma/sun6i-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), BIT 1307 drivers/dma/sun6i-dma.c sdc->slave.directions = BIT(DMA_DEV_TO_MEM) | BIT 1308 drivers/dma/sun6i-dma.c BIT(DMA_MEM_TO_DEV); BIT 34 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_GENERAL_ENABLE BIT(31) BIT 42 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_CSR_ENB BIT(31) BIT 43 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_CSR_IE_EOC BIT(30) BIT 44 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_CSR_HOLD BIT(29) BIT 45 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_CSR_DIR BIT(28) BIT 46 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_CSR_ONCE BIT(27) BIT 47 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_CSR_FLOW BIT(21) BIT 54 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_STATUS_BUSY BIT(31) BIT 55 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30) BIT 56 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_STATUS_HALT BIT(29) BIT 57 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_STATUS_PING_PONG BIT(28) BIT 69 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31) BIT 75 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27) BIT 79 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19) BIT 93 drivers/dma/tegra20-apb-dma.c #define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27) BIT 1497 drivers/dma/tegra20-apb-dma.c tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1498 drivers/dma/tegra20-apb-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1499 drivers/dma/tegra20-apb-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT 1500 drivers/dma/tegra20-apb-dma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); BIT 1501 drivers/dma/tegra20-apb-dma.c tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 1502 drivers/dma/tegra20-apb-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 1503 drivers/dma/tegra20-apb-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT 1504 drivers/dma/tegra20-apb-dma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); BIT 1505 drivers/dma/tegra20-apb-dma.c tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 21 drivers/dma/tegra210-adma.c #define ADMA_CH_STATUS_XFER_EN BIT(0) BIT 22 drivers/dma/tegra210-adma.c #define ADMA_CH_STATUS_XFER_PAUSED BIT(1) BIT 25 drivers/dma/tegra210-adma.c #define ADMA_CH_INT_STATUS_XFER_DONE BIT(0) BIT 33 drivers/dma/tegra210-adma.c #define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1) BIT 893 drivers/dma/tegra210-adma.c tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 894 drivers/dma/tegra210-adma.c tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 895 drivers/dma/tegra210-adma.c tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 1032 drivers/dma/ti/cppi41.c #define CPPI41_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 1033 drivers/dma/ti/cppi41.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 1034 drivers/dma/ti/cppi41.c BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT 1035 drivers/dma/ti/cppi41.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) BIT 1062 drivers/dma/ti/cppi41.c cdd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 114 drivers/dma/ti/edma.c #define CHMAP_EXIST BIT(24) BIT 117 drivers/dma/ti/edma.c #define EDMA_CCSTAT_ACTV BIT(4) BIT 145 drivers/dma/ti/edma.c #define EDMA_CHANNEL_BIT(channel) (BIT((channel) & 0x1f)) BIT 160 drivers/dma/ti/edma.c #define SAM BIT(0) BIT 161 drivers/dma/ti/edma.c #define DAM BIT(1) BIT 162 drivers/dma/ti/edma.c #define SYNCDIM BIT(2) BIT 163 drivers/dma/ti/edma.c #define STATIC BIT(3) BIT 165 drivers/dma/ti/edma.c #define TCCMODE BIT(11) BIT 167 drivers/dma/ti/edma.c #define TCINTEN BIT(20) BIT 168 drivers/dma/ti/edma.c #define ITCINTEN BIT(21) BIT 169 drivers/dma/ti/edma.c #define TCCHEN BIT(22) BIT 170 drivers/dma/ti/edma.c #define ITCCHEN BIT(23) BIT 691 drivers/dma/ti/edma.c edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); BIT 1491 drivers/dma/ti/edma.c sh_ipr &= ~(BIT(slot)); BIT 1493 drivers/dma/ti/edma.c if (sh_ier & BIT(slot)) { BIT 1496 drivers/dma/ti/edma.c edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); BIT 1601 drivers/dma/ti/edma.c edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); BIT 1604 drivers/dma/ti/edma.c BIT(i)); BIT 1887 drivers/dma/ti/edma.c #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 1888 drivers/dma/ti/edma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 1889 drivers/dma/ti/edma.c BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT 1890 drivers/dma/ti/edma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) BIT 1908 drivers/dma/ti/edma.c s_ddev->directions = BIT(DMA_MEM_TO_MEM); BIT 1925 drivers/dma/ti/edma.c s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV)); BIT 1957 drivers/dma/ti/edma.c m_ddev->directions = BIT(DMA_MEM_TO_MEM); BIT 1995 drivers/dma/ti/edma.c ecc->num_region = BIT(value); BIT 1998 drivers/dma/ti/edma.c ecc->num_channels = BIT(value + 1); BIT 2004 drivers/dma/ti/edma.c ecc->num_slots = BIT(value + 4); BIT 109 drivers/dma/ti/omap-dma.c CAPS_0_SUPPORT_LL123 = BIT(20), /* Linked List type1/2/3 */ BIT 110 drivers/dma/ti/omap-dma.c CAPS_0_SUPPORT_LL4 = BIT(21), /* Linked List type4 */ BIT 112 drivers/dma/ti/omap-dma.c CCR_FS = BIT(5), BIT 113 drivers/dma/ti/omap-dma.c CCR_READ_PRIORITY = BIT(6), BIT 114 drivers/dma/ti/omap-dma.c CCR_ENABLE = BIT(7), BIT 115 drivers/dma/ti/omap-dma.c CCR_AUTO_INIT = BIT(8), /* OMAP1 only */ BIT 116 drivers/dma/ti/omap-dma.c CCR_REPEAT = BIT(9), /* OMAP1 only */ BIT 117 drivers/dma/ti/omap-dma.c CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */ BIT 118 drivers/dma/ti/omap-dma.c CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */ BIT 119 drivers/dma/ti/omap-dma.c CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */ BIT 120 drivers/dma/ti/omap-dma.c CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */ BIT 129 drivers/dma/ti/omap-dma.c CCR_CONSTANT_FILL = BIT(16), BIT 130 drivers/dma/ti/omap-dma.c CCR_TRANSPARENT_COPY = BIT(17), BIT 131 drivers/dma/ti/omap-dma.c CCR_BS = BIT(18), BIT 132 drivers/dma/ti/omap-dma.c CCR_SUPERVISOR = BIT(22), BIT 133 drivers/dma/ti/omap-dma.c CCR_PREFETCH = BIT(23), BIT 134 drivers/dma/ti/omap-dma.c CCR_TRIGGER_SRC = BIT(24), BIT 135 drivers/dma/ti/omap-dma.c CCR_BUFFERING_DISABLE = BIT(25), BIT 136 drivers/dma/ti/omap-dma.c CCR_WRITE_PRIORITY = BIT(26), BIT 151 drivers/dma/ti/omap-dma.c CSDP_SRC_PACKED = BIT(6), BIT 162 drivers/dma/ti/omap-dma.c CSDP_DST_PACKED = BIT(13), BIT 171 drivers/dma/ti/omap-dma.c CICR_TOUT_IE = BIT(0), /* OMAP1 only */ BIT 172 drivers/dma/ti/omap-dma.c CICR_DROP_IE = BIT(1), BIT 173 drivers/dma/ti/omap-dma.c CICR_HALF_IE = BIT(2), BIT 174 drivers/dma/ti/omap-dma.c CICR_FRAME_IE = BIT(3), BIT 175 drivers/dma/ti/omap-dma.c CICR_LAST_IE = BIT(4), BIT 176 drivers/dma/ti/omap-dma.c CICR_BLOCK_IE = BIT(5), BIT 177 drivers/dma/ti/omap-dma.c CICR_PKT_IE = BIT(7), /* OMAP2+ only */ BIT 178 drivers/dma/ti/omap-dma.c CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */ BIT 179 drivers/dma/ti/omap-dma.c CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */ BIT 180 drivers/dma/ti/omap-dma.c CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */ BIT 181 drivers/dma/ti/omap-dma.c CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */ BIT 182 drivers/dma/ti/omap-dma.c CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */ BIT 184 drivers/dma/ti/omap-dma.c CLNK_CTRL_ENABLE_LNK = BIT(15), BIT 197 drivers/dma/ti/omap-dma.c CDP_FAST = BIT(10), BIT 615 drivers/dma/ti/omap-dma.c mask = BIT(channel); BIT 660 drivers/dma/ti/omap-dma.c val = BIT(c->dma_ch); BIT 666 drivers/dma/ti/omap-dma.c val &= ~BIT(c->dma_ch); BIT 697 drivers/dma/ti/omap-dma.c od->irq_enable_mask &= ~BIT(c->dma_ch); BIT 1188 drivers/dma/ti/omap-dma.c d->sg[0].en = len / BIT(data_type); BIT 1243 drivers/dma/ti/omap-dma.c sg->en = xt->sgl[0].size / BIT(data_type); BIT 1456 drivers/dma/ti/omap-dma.c #define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 1457 drivers/dma/ti/omap-dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 1458 drivers/dma/ti/omap-dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) BIT 1501 drivers/dma/ti/omap-dma.c od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 24 drivers/dma/uniphier-mdmac.c #define UNIPHIER_MDMAC_CMD_ABORT BIT(31) /* 1: abort, 0: start */ BIT 34 drivers/dma/uniphier-mdmac.c #define UNIPHIER_MDMAC_CH_IRQ__ABORT BIT(13) BIT 35 drivers/dma/uniphier-mdmac.c #define UNIPHIER_MDMAC_CH_IRQ__DONE BIT(1) BIT 46 drivers/dma/uniphier-mdmac.c (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 47 drivers/dma/uniphier-mdmac.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 48 drivers/dma/uniphier-mdmac.c BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT 49 drivers/dma/uniphier-mdmac.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) BIT 141 drivers/dma/uniphier-mdmac.c writel(BIT(mc->chan_id), mdev->reg_base + UNIPHIER_MDMAC_CMD); BIT 164 drivers/dma/uniphier-mdmac.c writel(UNIPHIER_MDMAC_CMD_ABORT | BIT(mc->chan_id), BIT 421 drivers/dma/uniphier-mdmac.c ddev->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); BIT 28 drivers/dma/xgene-dma.c #define XGENE_DMA_RING_ENABLE BIT(31) BIT 30 drivers/dma/xgene-dma.c #define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31)) BIT 32 drivers/dma/xgene-dma.c #define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) BIT 43 drivers/dma/xgene-dma.c ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) BIT 45 drivers/dma/xgene-dma.c ((m) &= (~BIT(31 - (v)))) BIT 56 drivers/dma/xgene-dma.c (((u32 *)(m))[2] |= BIT(4)) BIT 62 drivers/dma/xgene-dma.c (((u32 *)(m))[3] |= BIT(19)) BIT 66 drivers/dma/xgene-dma.c (((u32 *)(m))[3] |= BIT(27)) BIT 72 drivers/dma/xgene-dma.c (((u32 *)(m))[4] |= BIT(3)) BIT 84 drivers/dma/xgene-dma.c #define XGENE_DMA_ENABLE(v) ((v) |= BIT(31)) BIT 85 drivers/dma/xgene-dma.c #define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31)) BIT 107 drivers/dma/xgene-dma.c #define XGENE_DMA_PQ_DISABLE_MASK BIT(13) BIT 181 drivers/dma/xgene-dma.c #define XGENE_DMA_FLAG_64B_DESC BIT(0) BIT 60 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_ERR_IRQ BIT(14) BIT 61 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13) BIT 62 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12) BIT 65 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4) BIT 66 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3) BIT 67 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_RESET BIT(2) BIT 68 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_CIRC_EN BIT(1) BIT 69 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_RUNSTOP BIT(0) BIT 76 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15) BIT 77 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_ERR_IRQ BIT(14) BIT 78 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13) BIT 79 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12) BIT 80 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11) BIT 81 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10) BIT 82 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9) BIT 83 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8) BIT 84 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7) BIT 85 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) BIT 86 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) BIT 87 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) BIT 88 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_SG_MASK BIT(3) BIT 89 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_IDLE BIT(1) BIT 90 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_HALTED BIT(0) BIT 119 drivers/dma/xilinx/xilinx_dma.c #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0) BIT 168 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) BIT 170 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_BD_SOP BIT(27) BIT 171 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_BD_EOP BIT(26) BIT 193 drivers/dma/xilinx/xilinx_dma.c #define XILINX_CDMA_CR_SGMODE BIT(3) BIT 54 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_DONE BIT(10) BIT 55 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AXI_WR_DATA BIT(9) BIT 56 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AXI_RD_DATA BIT(8) BIT 57 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AXI_RD_DST_DSCR BIT(7) BIT 58 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AXI_RD_SRC_DSCR BIT(6) BIT 59 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_IRQ_DST_ACCT_ERR BIT(5) BIT 60 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_IRQ_SRC_ACCT_ERR BIT(4) BIT 61 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_BYTE_CNT_OVRFL BIT(3) BIT 62 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_DST_DSCR_DONE BIT(2) BIT 63 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_INV_APB BIT(0) BIT 66 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_OVR_FETCH BIT(7) BIT 67 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_POINT_TYPE_SG BIT(6) BIT 68 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_RATE_CTRL_EN BIT(3) BIT 90 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AXCOHRNT BIT(8) BIT 97 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_ENABLE BIT(0) BIT 1088 drivers/dma/xilinx/zynqmp_dma.c p->dst_addr_widths = BIT(zdev->chan->bus_width / 8); BIT 1089 drivers/dma/xilinx/zynqmp_dma.c p->src_addr_widths = BIT(zdev->chan->bus_width / 8); BIT 49 drivers/dma/zx_dma.c #define ZX_FORCE_CLOSE BIT(31) BIT 55 drivers/dma/zx_dma.c #define ZX_DST_FIFO_MODE BIT(3) BIT 56 drivers/dma/zx_dma.c #define ZX_SRC_FIFO_MODE BIT(2) BIT 57 drivers/dma/zx_dma.c #define ZX_SOFT_REQ BIT(1) BIT 58 drivers/dma/zx_dma.c #define ZX_CH_ENABLE BIT(0) BIT 61 drivers/dma/zx_dma.c (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ BIT 62 drivers/dma/zx_dma.c BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT 63 drivers/dma/zx_dma.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT 64 drivers/dma/zx_dma.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ BIT 65 drivers/dma/zx_dma.c BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) BIT 195 drivers/dma/zx_dma.c if (BIT(c->phy->idx) & zx_dma_get_chan_stat(d)) BIT 284 drivers/dma/zx_dma.c tc &= ~BIT(i); BIT 299 drivers/dma/zx_dma.c irq_chan |= BIT(i); BIT 829 drivers/dma/zx_dma.c d->slave.directions = BIT(DMA_MEM_TO_MEM) | BIT(DMA_MEM_TO_DEV) BIT 830 drivers/dma/zx_dma.c | BIT(DMA_DEV_TO_MEM); BIT 1165 drivers/edac/altera_edac.c altr_init_a10_ecc_block(child, BIT(irq), BIT 2088 drivers/edac/altera_edac.c BIT(d->hwirq)); BIT 2096 drivers/edac/altera_edac.c BIT(d->hwirq)); BIT 2145 drivers/edac/altera_edac.c if (!(BIT(ed->db_irq) & dberror)) BIT 157 drivers/edac/altera_edac.h #define A10_DDR0_IRQ_MASK BIT(17) BIT 201 drivers/edac/altera_edac.h #define ALTR_OCR_ECC_EN BIT(0) BIT 202 drivers/edac/altera_edac.h #define ALTR_OCR_ECC_INJS BIT(1) BIT 203 drivers/edac/altera_edac.h #define ALTR_OCR_ECC_INJD BIT(2) BIT 204 drivers/edac/altera_edac.h #define ALTR_OCR_ECC_SERR BIT(3) BIT 205 drivers/edac/altera_edac.h #define ALTR_OCR_ECC_DERR BIT(4) BIT 210 drivers/edac/altera_edac.h #define ALTR_L2_ECC_EN BIT(0) BIT 211 drivers/edac/altera_edac.h #define ALTR_L2_ECC_INJS BIT(1) BIT 212 drivers/edac/altera_edac.h #define ALTR_L2_ECC_INJD BIT(2) BIT 216 drivers/edac/altera_edac.h #define ALTR_A10_ECC_EN BIT(0) BIT 217 drivers/edac/altera_edac.h #define ALTR_A10_ECC_INITA BIT(16) BIT 218 drivers/edac/altera_edac.h #define ALTR_A10_ECC_INITB BIT(24) BIT 221 drivers/edac/altera_edac.h #define ALTR_A10_ECC_INITCOMPLETEA BIT(0) BIT 222 drivers/edac/altera_edac.h #define ALTR_A10_ECC_INITCOMPLETEB BIT(8) BIT 227 drivers/edac/altera_edac.h #define ALTR_A10_ECC_SERRINTEN BIT(0) BIT 230 drivers/edac/altera_edac.h #define ALTR_A10_ECC_INTMODE BIT(0) BIT 233 drivers/edac/altera_edac.h #define ALTR_A10_ECC_SERRPENA BIT(0) BIT 234 drivers/edac/altera_edac.h #define ALTR_A10_ECC_DERRPENA BIT(8) BIT 237 drivers/edac/altera_edac.h #define ALTR_A10_ECC_SERRPENB BIT(16) BIT 238 drivers/edac/altera_edac.h #define ALTR_A10_ECC_DERRPENB BIT(24) BIT 243 drivers/edac/altera_edac.h #define ALTR_A10_ECC_TSERRA BIT(0) BIT 244 drivers/edac/altera_edac.h #define ALTR_A10_ECC_TDERRA BIT(8) BIT 245 drivers/edac/altera_edac.h #define ALTR_A10_ECC_TSERRB BIT(16) BIT 246 drivers/edac/altera_edac.h #define ALTR_A10_ECC_TDERRB BIT(24) BIT 251 drivers/edac/altera_edac.h #define A10_SYSMGR_ECC_INTMASK_OCRAM BIT(1) BIT 255 drivers/edac/altera_edac.h #define A10_SYSMGR_ECC_INTSTAT_L2 BIT(0) BIT 256 drivers/edac/altera_edac.h #define A10_SYSMGR_ECC_INTSTAT_OCRAM BIT(1) BIT 259 drivers/edac/altera_edac.h #define A10_SYSGMR_MPU_CLEAR_L2_ECC_SB BIT(15) BIT 260 drivers/edac/altera_edac.h #define A10_SYSGMR_MPU_CLEAR_L2_ECC_MB BIT(31) BIT 264 drivers/edac/altera_edac.h #define ALTR_A10_L2_ECC_EN_CTL BIT(0) BIT 268 drivers/edac/altera_edac.h #define ALTR_A10_L2_ECC_SERR_PEND BIT(0) BIT 269 drivers/edac/altera_edac.h #define ALTR_A10_L2_ECC_MERR_PEND BIT(0) BIT 272 drivers/edac/altera_edac.h #define ALTR_A10_L2_ECC_SERR_CLR BIT(15) BIT 273 drivers/edac/altera_edac.h #define ALTR_A10_L2_ECC_MERR_CLR BIT(31) BIT 280 drivers/edac/altera_edac.h #define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0)) BIT 283 drivers/edac/altera_edac.h #define ALTR_A10_COMMON_ECC_EN_CTL BIT(0) BIT 286 drivers/edac/altera_edac.h #define ALTR_A10_SDMMC_IRQ_MASK (BIT(16) | BIT(15)) BIT 293 drivers/edac/altera_edac.h #define ALTR_S10_ECC_EN BIT(0) BIT 298 drivers/edac/altera_edac.h #define ALTR_S10_ECC_SERRINTEN BIT(0) BIT 301 drivers/edac/altera_edac.h #define ALTR_S10_ECC_INTMODE BIT(0) BIT 304 drivers/edac/altera_edac.h #define ALTR_S10_ECC_SERRPENA BIT(0) BIT 305 drivers/edac/altera_edac.h #define ALTR_S10_ECC_DERRPENA BIT(8) BIT 310 drivers/edac/altera_edac.h #define ALTR_S10_ECC_TSERRA BIT(0) BIT 311 drivers/edac/altera_edac.h #define ALTR_S10_ECC_TDERRA BIT(8) BIT 312 drivers/edac/altera_edac.h #define ALTR_S10_ECC_TSERRB BIT(16) BIT 313 drivers/edac/altera_edac.h #define ALTR_S10_ECC_TDERRB BIT(24) BIT 325 drivers/edac/altera_edac.h #define S10_DDR0_IRQ_MASK BIT(16) BIT 273 drivers/edac/amd64_edac.c if (scrubval & BIT(0)) { BIT 736 drivers/edac/amd64_edac.c umc_en_mask |= BIT(i); BIT 739 drivers/edac/amd64_edac.c if (pvt->umc[i].umc_cfg & BIT(12)) BIT 740 drivers/edac/amd64_edac.c dimm_ecc_en_mask |= BIT(i); BIT 750 drivers/edac/amd64_edac.c if (pvt->dclr0 & BIT(bit)) BIT 774 drivers/edac/amd64_edac.c (dclr & BIT(19)) ? "yes" : "no"); BIT 778 drivers/edac/amd64_edac.c (dclr & BIT(8)) ? "enabled" : "disabled"); BIT 782 drivers/edac/amd64_edac.c (dclr & BIT(11)) ? "128b" : "64b"); BIT 785 drivers/edac/amd64_edac.c (dclr & BIT(12)) ? "yes" : "no", BIT 786 drivers/edac/amd64_edac.c (dclr & BIT(13)) ? "yes" : "no", BIT 787 drivers/edac/amd64_edac.c (dclr & BIT(14)) ? "yes" : "no", BIT 788 drivers/edac/amd64_edac.c (dclr & BIT(15)) ? "yes" : "no"); BIT 791 drivers/edac/amd64_edac.c #define CS_EVEN_PRIMARY BIT(0) BIT 792 drivers/edac/amd64_edac.c #define CS_ODD_PRIMARY BIT(1) BIT 793 drivers/edac/amd64_edac.c #define CS_EVEN_SECONDARY BIT(2) BIT 794 drivers/edac/amd64_edac.c #define CS_ODD_SECONDARY BIT(3) BIT 859 drivers/edac/amd64_edac.c i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no", BIT 860 drivers/edac/amd64_edac.c (umc->umc_cap_hi & BIT(31)) ? "yes" : "no"); BIT 862 drivers/edac/amd64_edac.c i, (umc->umc_cfg & BIT(12)) ? "yes" : "no"); BIT 864 drivers/edac/amd64_edac.c i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no"); BIT 866 drivers/edac/amd64_edac.c i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); BIT 1064 drivers/edac/amd64_edac.c pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; BIT 1071 drivers/edac/amd64_edac.c pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; BIT 1092 drivers/edac/amd64_edac.c else if (pvt->dclr0 & BIT(16)) BIT 1106 drivers/edac/amd64_edac.c if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) BIT 1108 drivers/edac/amd64_edac.c else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) BIT 1121 drivers/edac/amd64_edac.c pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; BIT 1328 drivers/edac/amd64_edac.c err->channel = ((sys_addr & BIT(3)) != 0); BIT 2002 drivers/edac/amd64_edac.c dct_offset_en = (u8) ((dct_cont_base_reg >> 3) & BIT(0)); BIT 2024 drivers/edac/amd64_edac.c if (!(dct_cont_base_reg & BIT(0)) && BIT 2045 drivers/edac/amd64_edac.c leg_mmio_hole = (u8) (dct_cont_base_reg >> 1 & BIT(0)); BIT 2716 drivers/edac/amd64_edac.c if (pvt->umc[i].ecc_ctrl & BIT(9)) { BIT 2719 drivers/edac/amd64_edac.c } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { BIT 2734 drivers/edac/amd64_edac.c if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) BIT 2780 drivers/edac/amd64_edac.c if (msr_val & BIT(21)) { BIT 3214 drivers/edac/amd64_edac.c umc_en_mask |= BIT(i); BIT 3220 drivers/edac/amd64_edac.c ecc_en_mask |= BIT(i); BIT 3262 drivers/edac/amd64_edac.c dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); BIT 3263 drivers/edac/amd64_edac.c dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); BIT 148 drivers/edac/amd64_edac.h #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) BIT 169 drivers/edac/amd64_edac.h #define DCSB_CS_ENABLE BIT(0) BIT 189 drivers/edac/amd64_edac.h #define REVE_WIDTH_128 BIT(16) BIT 190 drivers/edac/amd64_edac.h #define WIDTH_128 BIT(11) BIT 194 drivers/edac/amd64_edac.h #define DDR3_MODE BIT(8) BIT 197 drivers/edac/amd64_edac.h #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) BIT 198 drivers/edac/amd64_edac.h #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) BIT 200 drivers/edac/amd64_edac.h #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) BIT 202 drivers/edac/amd64_edac.h #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) BIT 203 drivers/edac/amd64_edac.h #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) BIT 219 drivers/edac/amd64_edac.h #define NBCFG_CHIPKILL BIT(23) BIT 220 drivers/edac/amd64_edac.h #define NBCFG_ECC_ENABLE BIT(22) BIT 233 drivers/edac/amd64_edac.h #define F10_NB_ARRAY_DRAM BIT(31) BIT 239 drivers/edac/amd64_edac.h #define F10_NB_ARR_ECC_WR_REQ BIT(17) BIT 241 drivers/edac/amd64_edac.h (BIT(((inj.word) & 0xF) + 20) | \ BIT 244 drivers/edac/amd64_edac.h (BIT(((inj.word) & 0xF) + 20) | \ BIT 245 drivers/edac/amd64_edac.h BIT(16) | inj.bit_map) BIT 249 drivers/edac/amd64_edac.h #define NBCAP_CHIPKILL BIT(4) BIT 250 drivers/edac/amd64_edac.h #define NBCAP_SECDED BIT(3) BIT 251 drivers/edac/amd64_edac.h #define NBCAP_DCT_DUAL BIT(0) BIT 256 drivers/edac/amd64_edac.h #define MSR_MCGCTL_NBE BIT(4) BIT 278 drivers/edac/amd64_edac.h #define UMC_ECC_CHIPKILL_CAP BIT(31) BIT 279 drivers/edac/amd64_edac.h #define UMC_ECC_ENABLED BIT(30) BIT 281 drivers/edac/amd64_edac.h #define UMC_SDP_INIT BIT(31) BIT 528 drivers/edac/amd64_edac.h return (tmp >> 1) & BIT(0); BIT 530 drivers/edac/amd64_edac.h return (pvt)->dhar & BIT(0); BIT 111 drivers/edac/amd76x_edac.c if (info->ecc_mode_status & BIT(8)) BIT 113 drivers/edac/amd76x_edac.c (u32) BIT(8), (u32) BIT(8)); BIT 115 drivers/edac/amd76x_edac.c if (info->ecc_mode_status & BIT(9)) BIT 117 drivers/edac/amd76x_edac.c (u32) BIT(9), (u32) BIT(9)); BIT 142 drivers/edac/amd76x_edac.c if (info->ecc_mode_status & BIT(8)) { BIT 157 drivers/edac/amd76x_edac.c if (info->ecc_mode_status & BIT(9)) { BIT 203 drivers/edac/amd76x_edac.c if (!(mba & BIT(0))) BIT 20 drivers/edac/amd8111_edac.h PCI_STSCMD_SSE = BIT(30), BIT 21 drivers/edac/amd8111_edac.h PCI_STSCMD_RMA = BIT(29), BIT 22 drivers/edac/amd8111_edac.h PCI_STSCMD_RTA = BIT(28), BIT 23 drivers/edac/amd8111_edac.h PCI_STSCMD_SERREN = BIT(8), BIT 34 drivers/edac/amd8111_edac.h MEM_LIMIT_DPE = BIT(31), BIT 35 drivers/edac/amd8111_edac.h MEM_LIMIT_RSE = BIT(30), BIT 36 drivers/edac/amd8111_edac.h MEM_LIMIT_RMA = BIT(29), BIT 37 drivers/edac/amd8111_edac.h MEM_LIMIT_RTA = BIT(28), BIT 38 drivers/edac/amd8111_edac.h MEM_LIMIT_STA = BIT(27), BIT 39 drivers/edac/amd8111_edac.h MEM_LIMIT_MDPE = BIT(24), BIT 53 drivers/edac/amd8111_edac.h HT_LINK_LKFAIL = BIT(4), BIT 54 drivers/edac/amd8111_edac.h HT_LINK_CRCFEN = BIT(1), BIT 63 drivers/edac/amd8111_edac.h PCI_INTBRG_CTRL_DTSERREN = BIT(27), BIT 64 drivers/edac/amd8111_edac.h PCI_INTBRG_CTRL_DTSTAT = BIT(26), BIT 65 drivers/edac/amd8111_edac.h PCI_INTBRG_CTRL_MARSP = BIT(21), BIT 66 drivers/edac/amd8111_edac.h PCI_INTBRG_CTRL_SERREN = BIT(17), BIT 67 drivers/edac/amd8111_edac.h PCI_INTBRG_CTRL_PEREN = BIT(16), BIT 79 drivers/edac/amd8111_edac.h IO_CTRL_1_NMIONERR = BIT(7), BIT 80 drivers/edac/amd8111_edac.h IO_CTRL_1_LPC_ERR = BIT(6), BIT 81 drivers/edac/amd8111_edac.h IO_CTRL_1_PW2LPC = BIT(1), BIT 90 drivers/edac/amd8111_edac.h AT_COMPAT_SERR = BIT(7), BIT 91 drivers/edac/amd8111_edac.h AT_COMPAT_IOCHK = BIT(6), BIT 92 drivers/edac/amd8111_edac.h AT_COMPAT_CLRIOCHK = BIT(3), BIT 93 drivers/edac/amd8111_edac.h AT_COMPAT_CLRSERR = BIT(2), BIT 25 drivers/edac/amd8131_edac.h STS_CMD_SSE = BIT(30), BIT 26 drivers/edac/amd8131_edac.h STS_CMD_SERREN = BIT(8) BIT 34 drivers/edac/amd8131_edac.h INT_CTLR_DTSE = BIT(27), BIT 35 drivers/edac/amd8131_edac.h INT_CTLR_DTS = BIT(26), BIT 36 drivers/edac/amd8131_edac.h INT_CTLR_SERR = BIT(17), BIT 37 drivers/edac/amd8131_edac.h INT_CTLR_PERR = BIT(16) BIT 45 drivers/edac/amd8131_edac.h MEM_LIMIT_DPE = BIT(31), BIT 46 drivers/edac/amd8131_edac.h MEM_LIMIT_RSE = BIT(30), BIT 47 drivers/edac/amd8131_edac.h MEM_LIMIT_RMA = BIT(29), BIT 48 drivers/edac/amd8131_edac.h MEM_LIMIT_RTA = BIT(28), BIT 49 drivers/edac/amd8131_edac.h MEM_LIMIT_STA = BIT(27), BIT 50 drivers/edac/amd8131_edac.h MEM_LIMIT_MDPE = BIT(24), BIT 66 drivers/edac/amd8131_edac.h LNK_CTRL_CRCERR_A = BIT(9), BIT 67 drivers/edac/amd8131_edac.h LNK_CTRL_CRCERR_B = BIT(8), BIT 68 drivers/edac/amd8131_edac.h LNK_CTRL_CRCFEN = BIT(1) BIT 22 drivers/edac/armada_xp_edac.c #define SDRAM_CONFIG_ECC_MASK BIT(18) BIT 23 drivers/edac/armada_xp_edac.c #define SDRAM_CONFIG_REGISTERED_MASK BIT(17) BIT 24 drivers/edac/armada_xp_edac.c #define SDRAM_CONFIG_BUS_WIDTH_MASK BIT(15) BIT 29 drivers/edac/armada_xp_edac.c #define SDRAM_ADDR_CTRL_ADDR_SEL_MASK(cs) BIT(16+cs) BIT 53 drivers/edac/armada_xp_edac.c #define SDRAM_ERR_ADDR_TYPE_MASK BIT(0) BIT 58 drivers/edac/armada_xp_edac.c #define SDRAM_ERR_CTRL_PROP_MASK BIT(9) BIT 65 drivers/edac/armada_xp_edac.c #define SDRAM_ERR_CAUSE_DBE_MASK BIT(1) BIT 66 drivers/edac/armada_xp_edac.c #define SDRAM_ERR_CAUSE_SBE_MASK BIT(0) BIT 69 drivers/edac/armada_xp_edac.c #define SDRAM_RANK_CTRL_EXIST_MASK(cs) BIT(cs) BIT 30 drivers/edac/aspeed_edac.c #define ASPEED_MCR_CONF_DRAM_TYPE BIT(4) BIT 31 drivers/edac/aspeed_edac.c #define ASPEED_MCR_CONF_ECC BIT(7) BIT 32 drivers/edac/aspeed_edac.c #define ASPEED_MCR_INTR_CTRL_CLEAR BIT(31) BIT 35 drivers/edac/aspeed_edac.c #define ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1)) BIT 29 drivers/edac/bluefield_edac.c #define MLXBF_ECC_ERR__SECC BIT(0) BIT 30 drivers/edac/bluefield_edac.c #define MLXBF_ECC_ERR__DECC BIT(16) BIT 33 drivers/edac/bluefield_edac.c #define MLXBF_ECC_LATCH_SEL__START BIT(24) BIT 40 drivers/edac/bluefield_edac.c #define MLXBF_SYNDROM__DERR BIT(0) BIT 41 drivers/edac/bluefield_edac.c #define MLXBF_SYNDROM__SERR BIT(1) BIT 68 drivers/edac/bluefield_edac.c #define MLXBF_DIMM_INFO__IS_RDIMM BIT(16) BIT 69 drivers/edac/bluefield_edac.c #define MLXBF_DIMM_INFO__IS_LRDIMM BIT(17) BIT 70 drivers/edac/bluefield_edac.c #define MLXBF_DIMM_INFO__IS_NVDIMM BIT(18) BIT 112 drivers/edac/ghes_edac.c u16 rdr_mask = BIT(7) | BIT(13); BIT 121 drivers/edac/ghes_edac.c if (entry->size & BIT(15)) BIT 129 drivers/edac/ghes_edac.c if (entry->type_detail & BIT(13)) BIT 135 drivers/edac/ghes_edac.c if (entry->type_detail & BIT(13)) BIT 144 drivers/edac/ghes_edac.c if (entry->type_detail & BIT(12)) BIT 146 drivers/edac/ghes_edac.c else if (entry->type_detail & BIT(13)) BIT 152 drivers/edac/ghes_edac.c if (entry->type_detail & BIT(12)) BIT 154 drivers/edac/ghes_edac.c else if (entry->type_detail & BIT(13)) BIT 160 drivers/edac/ghes_edac.c if (entry->type_detail & BIT(6)) BIT 164 drivers/edac/ghes_edac.c else if (entry->type_detail & BIT(7)) BIT 166 drivers/edac/ghes_edac.c else if (entry->type_detail & BIT(9)) BIT 485 drivers/edac/i7300_edac.c channel += !!(value & BIT(17)); BIT 81 drivers/edac/i82443bxgx_edac.c #define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */ BIT 82 drivers/edac/i82443bxgx_edac.c #define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */ BIT 86 drivers/edac/i82443bxgx_edac.c #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */ BIT 87 drivers/edac/i82443bxgx_edac.c #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */ BIT 92 drivers/edac/i82443bxgx_edac.c #define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */ BIT 94 drivers/edac/i82443bxgx_edac.c #define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */ BIT 264 drivers/edac/i82443bxgx_edac.c switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) { BIT 287 drivers/edac/i82443bxgx_edac.c (BIT(0) | BIT(1))); BIT 96 drivers/edac/ie31200_edac.c #define IE31200_MMR_WINDOW_SIZE BIT(15) BIT 118 drivers/edac/ie31200_edac.c #define IE31200_ERRSTS_UE BIT(1) BIT 119 drivers/edac/ie31200_edac.c #define IE31200_ERRSTS_CE BIT(0) BIT 140 drivers/edac/ie31200_edac.c #define IE31200_ECCERRLOG_CE BIT(0) BIT 141 drivers/edac/ie31200_edac.c #define IE31200_ECCERRLOG_UE BIT(1) BIT 152 drivers/edac/ie31200_edac.c #define IE31200_CAPID0_PDCD BIT(4) BIT 153 drivers/edac/ie31200_edac.c #define IE31200_CAPID0_DDPCD BIT(6) BIT 154 drivers/edac/ie31200_edac.c #define IE31200_CAPID0_ECC BIT(1) BIT 159 drivers/edac/ie31200_edac.c #define IE31200_MAD_DIMM_A_RANK BIT(17) BIT 161 drivers/edac/ie31200_edac.c #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10) BIT 163 drivers/edac/ie31200_edac.c #define IE31200_MAD_DIMM_A_WIDTH BIT(19) BIT 1090 drivers/edac/pnd2_edac.c if (chan_mask & BIT(i)) BIT 1231 drivers/edac/pnd2_edac.c if (!(chan_mask & BIT(i))) BIT 51 drivers/edac/qcom_edac.c #define ECC_DB_ERR_WAYS_SHIFT BIT(4) BIT 54 drivers/edac/qcom_edac.c #define ECC_SB_ERR_COUNT_SHIFT BIT(4) BIT 57 drivers/edac/qcom_edac.c #define SB_ECC_ERROR BIT(0) BIT 58 drivers/edac/qcom_edac.c #define DB_ECC_ERROR BIT(1) BIT 76 drivers/edac/qcom_edac.c #define DRP0_INTERRUPT_ENABLE BIT(6) BIT 145 drivers/edac/r82600_edac.c if (info->eapr & BIT(0)) BIT 148 drivers/edac/r82600_edac.c ((u32) BIT(0) & (u32) BIT(1)), BIT 149 drivers/edac/r82600_edac.c ((u32) BIT(0) & (u32) BIT(1))); BIT 151 drivers/edac/r82600_edac.c if (info->eapr & BIT(1)) BIT 154 drivers/edac/r82600_edac.c ((u32) BIT(0) & (u32) BIT(1)), BIT 155 drivers/edac/r82600_edac.c ((u32) BIT(0) & (u32) BIT(1))); BIT 177 drivers/edac/r82600_edac.c if (info->eapr & BIT(0)) { /* CE? */ BIT 188 drivers/edac/r82600_edac.c if (info->eapr & BIT(1)) { /* UE? */ BIT 214 drivers/edac/r82600_edac.c return dramcr & BIT(5); BIT 228 drivers/edac/r82600_edac.c reg_sdram = dramcr & BIT(4); BIT 282 drivers/edac/r82600_edac.c scrub_disabled = eapr & BIT(31); BIT 283 drivers/edac/r82600_edac.c sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); BIT 337 drivers/edac/r82600_edac.c pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31)); BIT 102 drivers/edac/synopsys_edac.c #define DDR_ECC_INTR_SUPPORT BIT(0) BIT 103 drivers/edac/synopsys_edac.c #define DDR_ECC_DATA_POISON_SUPPORT BIT(1) BIT 151 drivers/edac/synopsys_edac.c #define ECC_CTRL_CLR_CE_ERRCNT BIT(2) BIT 152 drivers/edac/synopsys_edac.c #define ECC_CTRL_CLR_UE_ERRCNT BIT(3) BIT 176 drivers/edac/synopsys_edac.c #define ECC_CEADDR0_RNK_MASK BIT(24) BIT 185 drivers/edac/synopsys_edac.c #define ECC_POISON0_RANK_MASK BIT(24) BIT 930 drivers/edac/synopsys_edac.c BIT(0)) << index); BIT 938 drivers/edac/synopsys_edac.c BIT(0)) << index); BIT 946 drivers/edac/synopsys_edac.c BIT(0)) << index); BIT 954 drivers/edac/synopsys_edac.c & BIT(0)) << index); BIT 960 drivers/edac/synopsys_edac.c rank = (hif_addr >> priv->rank_shift[0]) & BIT(0); BIT 75 drivers/edac/thunderx_edac.c #define L2C_CTL_DISIDXALIAS BIT(0) BIT 98 drivers/edac/thunderx_edac.c #define LMC_CONFIG_BG2 BIT(62) BIT 99 drivers/edac/thunderx_edac.c #define LMC_CONFIG_RANK_ENA BIT(42) BIT 104 drivers/edac/thunderx_edac.c #define LMC_CONTROL_XOR_BANK BIT(16) BIT 108 drivers/edac/thunderx_edac.c #define LMC_INT_DDR_ERR BIT(11) BIT 111 drivers/edac/thunderx_edac.c #define LMC_INT_NXM_WR_MASK BIT(0) BIT 114 drivers/edac/thunderx_edac.c #define LMC_DDR_PLL_CTL_DDR4 BIT(29) BIT 147 drivers/edac/thunderx_edac.c #define LMC_INT_EN_DDR_ERROR_ALERT_ENA BIT(5) BIT 148 drivers/edac/thunderx_edac.c #define LMC_INT_EN_DLCRAM_DED_ERR BIT(4) BIT 149 drivers/edac/thunderx_edac.c #define LMC_INT_EN_DLCRAM_SEC_ERR BIT(3) BIT 150 drivers/edac/thunderx_edac.c #define LMC_INT_INTR_DED_ENA BIT(2) BIT 151 drivers/edac/thunderx_edac.c #define LMC_INT_INTR_SEC_ENA BIT(1) BIT 152 drivers/edac/thunderx_edac.c #define LMC_INT_INTR_NXM_WR_ENA BIT(0) BIT 157 drivers/edac/thunderx_edac.c #define LMC_DDR_PLL_CTL_DDR4 BIT(29) BIT 160 drivers/edac/thunderx_edac.c #define LMC_CONTROL_RDIMM BIT(0) BIT 682 drivers/edac/thunderx_edac.c ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_lmc"); BIT 837 drivers/edac/thunderx_edac.c #define OCX_COM_IO_BADID BIT(54) BIT 838 drivers/edac/thunderx_edac.c #define OCX_COM_MEM_BADID BIT(53) BIT 839 drivers/edac/thunderx_edac.c #define OCX_COM_COPR_BADID BIT(52) BIT 840 drivers/edac/thunderx_edac.c #define OCX_COM_WIN_REQ_BADID BIT(51) BIT 841 drivers/edac/thunderx_edac.c #define OCX_COM_WIN_REQ_TOUT BIT(50) BIT 884 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_BAD_WORD BIT(13) BIT 885 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_ALIGN_FAIL BIT(12) BIT 886 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_ALIGN_DONE BIT(11) BIT 887 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_UP BIT(10) BIT 888 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_STOP BIT(9) BIT 889 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_BLK_ERR BIT(8) BIT 890 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_REINIT BIT(7) BIT 891 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_LNK_DATA BIT(6) BIT 892 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_RXFIFO_DBE BIT(5) BIT 893 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_RXFIFO_SBE BIT(4) BIT 894 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_TXFIFO_DBE BIT(3) BIT 895 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_TXFIFO_SBE BIT(2) BIT 896 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_REPLAY_DBE BIT(1) BIT 897 drivers/edac/thunderx_edac.c #define OCX_COM_LINK_REPLAY_SBE BIT(0) BIT 971 drivers/edac/thunderx_edac.c #define OCX_LNE_CFG_RX_BDRY_LOCK_DIS BIT(8) BIT 972 drivers/edac/thunderx_edac.c #define OCX_LNE_CFG_RX_STAT_WRAP_DIS BIT(2) BIT 973 drivers/edac/thunderx_edac.c #define OCX_LNE_CFG_RX_STAT_RDCLR BIT(1) BIT 974 drivers/edac/thunderx_edac.c #define OCX_LNE_CFG_RX_STAT_ENA BIT(0) BIT 977 drivers/edac/thunderx_edac.c #define OCX_LANE_BAD_64B67B BIT(8) BIT 978 drivers/edac/thunderx_edac.c #define OCX_LANE_DSKEW_FIFO_OVFL BIT(5) BIT 979 drivers/edac/thunderx_edac.c #define OCX_LANE_SCRM_SYNC_LOSS BIT(4) BIT 980 drivers/edac/thunderx_edac.c #define OCX_LANE_UKWN_CNTL_WORD BIT(3) BIT 981 drivers/edac/thunderx_edac.c #define OCX_LANE_CRC32_ERR BIT(2) BIT 982 drivers/edac/thunderx_edac.c #define OCX_LANE_BDRY_SYNC_LOSS BIT(1) BIT 983 drivers/edac/thunderx_edac.c #define OCX_LANE_SERDES_LOCK_LOSS BIT(0) BIT 1139 drivers/edac/thunderx_edac.c if (ctx->reg_com_int & BIT(lane)) { BIT 1359 drivers/edac/thunderx_edac.c ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_ocx"); BIT 1514 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_L2DDBE BIT(1) BIT 1515 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_SBFSBE BIT(2) BIT 1516 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_SBFDBE BIT(3) BIT 1517 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_FBFSBE BIT(4) BIT 1518 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_FBFDBE BIT(5) BIT 1519 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_TAGDBE BIT(9) BIT 1520 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_RDDISLMC BIT(15) BIT 1521 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_WRDISLMC BIT(16) BIT 1522 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_LFBTO BIT(17) BIT 1523 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_GSYNCTO BIT(18) BIT 1524 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_RTGSBE BIT(32) BIT 1525 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_RTGDBE BIT(33) BIT 1526 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_RDDISOCI BIT(34) BIT 1527 drivers/edac/thunderx_edac.c #define L2C_TAD_INT_WRDISOCI BIT(35) BIT 1639 drivers/edac/thunderx_edac.c #define L2C_CBC_INT_RSDSBE BIT(0) BIT 1640 drivers/edac/thunderx_edac.c #define L2C_CBC_INT_RSDDBE BIT(1) BIT 1644 drivers/edac/thunderx_edac.c #define L2C_CBC_INT_MIBSBE BIT(4) BIT 1645 drivers/edac/thunderx_edac.c #define L2C_CBC_INT_MIBDBE BIT(5) BIT 1649 drivers/edac/thunderx_edac.c #define L2C_CBC_INT_IORDDISOCI BIT(6) BIT 1650 drivers/edac/thunderx_edac.c #define L2C_CBC_INT_IOWRDISOCI BIT(7) BIT 1709 drivers/edac/thunderx_edac.c #define L2C_MCI_INT_VBFSBE BIT(0) BIT 1710 drivers/edac/thunderx_edac.c #define L2C_MCI_INT_VBFDBE BIT(1) BIT 1965 drivers/edac/thunderx_edac.c ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_l2c"); BIT 55 drivers/edac/ti_edac.c #define SDRAM_K2_EBANK_MASK BIT(SDRAM_K2_EBANK_SHIFT) BIT 64 drivers/edac/ti_edac.c #define EMIF_1B_ECC_ERR BIT(5) BIT 65 drivers/edac/ti_edac.c #define EMIF_2B_ECC_ERR BIT(4) BIT 66 drivers/edac/ti_edac.c #define EMIF_WR_ECC_ERR BIT(3) BIT 67 drivers/edac/ti_edac.c #define EMIF_SYS_ERR BIT(0) BIT 69 drivers/edac/ti_edac.c #define ECC_ENABLED (BIT(31) | BIT(28)) BIT 26 drivers/edac/xgene_edac.c #define MCU_CTL_ERR_MASK BIT(12) BIT 27 drivers/edac/xgene_edac.c #define IOB_PA_ERR_MASK BIT(11) BIT 28 drivers/edac/xgene_edac.c #define IOB_BA_ERR_MASK BIT(10) BIT 29 drivers/edac/xgene_edac.c #define IOB_XGIC_ERR_MASK BIT(9) BIT 30 drivers/edac/xgene_edac.c #define IOB_RB_ERR_MASK BIT(8) BIT 31 drivers/edac/xgene_edac.c #define L3C_UNCORR_ERR_MASK BIT(5) BIT 32 drivers/edac/xgene_edac.c #define MCU_UNCORR_ERR_MASK BIT(4) BIT 33 drivers/edac/xgene_edac.c #define PMD3_MERR_MASK BIT(3) BIT 34 drivers/edac/xgene_edac.c #define PMD2_MERR_MASK BIT(2) BIT 35 drivers/edac/xgene_edac.c #define PMD1_MERR_MASK BIT(1) BIT 36 drivers/edac/xgene_edac.c #define PMD0_MERR_MASK BIT(0) BIT 39 drivers/edac/xgene_edac.c #define CSW_SWITCH_TRACE_ERR_MASK BIT(2) BIT 40 drivers/edac/xgene_edac.c #define L3C_CORR_ERR_MASK BIT(1) BIT 41 drivers/edac/xgene_edac.c #define MCU_CORR_ERR_MASK BIT(0) BIT 100 drivers/edac/xgene_edac.c #define MCU_GECR_DEMANDUCINTREN_MASK BIT(0) BIT 101 drivers/edac/xgene_edac.c #define MCU_GECR_BACKUCINTREN_MASK BIT(1) BIT 102 drivers/edac/xgene_edac.c #define MCU_GECR_CINTREN_MASK BIT(2) BIT 103 drivers/edac/xgene_edac.c #define MUC_GECR_MCUADDRERREN_MASK BIT(9) BIT 105 drivers/edac/xgene_edac.c #define MCU_GESR_ADDRNOMATCH_ERR_MASK BIT(7) BIT 106 drivers/edac/xgene_edac.c #define MCU_GESR_ADDRMULTIMATCH_ERR_MASK BIT(6) BIT 107 drivers/edac/xgene_edac.c #define MCU_GESR_PHYP_ERR_MASK BIT(3) BIT 109 drivers/edac/xgene_edac.c #define MCU_ESRR_MULTUCERR_MASK BIT(3) BIT 110 drivers/edac/xgene_edac.c #define MCU_ESRR_BACKUCERR_MASK BIT(2) BIT 111 drivers/edac/xgene_edac.c #define MCU_ESRR_DEMANDUCERR_MASK BIT(1) BIT 112 drivers/edac/xgene_edac.c #define MCU_ESRR_CERR_MASK BIT(0) BIT 123 drivers/edac/xgene_edac.c #define CSW_CSWCR_DUALMCB_MASK BIT(0) BIT 126 drivers/edac/xgene_edac.c #define MCBADDRMR_MCU_INTLV_MODE_MASK BIT(3) BIT 127 drivers/edac/xgene_edac.c #define MCBADDRMR_DUALMCU_MODE_MASK BIT(2) BIT 128 drivers/edac/xgene_edac.c #define MCBADDRMR_MCB_INTLV_MODE_MASK BIT(1) BIT 129 drivers/edac/xgene_edac.c #define MCBADDRMR_ADDRESS_MODE_MASK BIT(0) BIT 458 drivers/edac/xgene_edac.c #define MEMERR_CPU_ICFESR_MULTCERR_MASK BIT(2) BIT 459 drivers/edac/xgene_edac.c #define MEMERR_CPU_ICFESR_CERR_MASK BIT(0) BIT 465 drivers/edac/xgene_edac.c #define MEMERR_CPU_LSUESR_MULTCERR_MASK BIT(2) BIT 466 drivers/edac/xgene_edac.c #define MEMERR_CPU_LSUESR_CERR_MASK BIT(0) BIT 473 drivers/edac/xgene_edac.c #define MEMERR_CPU_MMUESR_ERRREQSTR_LSU_MASK BIT(7) BIT 475 drivers/edac/xgene_edac.c #define MEMERR_CPU_MMUESR_MULTCERR_MASK BIT(2) BIT 476 drivers/edac/xgene_edac.c #define MEMERR_CPU_MMUESR_CERR_MASK BIT(0) BIT 489 drivers/edac/xgene_edac.c #define MEMERR_L2C_L2ESR_MULTUCERR_MASK BIT(3) BIT 490 drivers/edac/xgene_edac.c #define MEMERR_L2C_L2ESR_MULTICERR_MASK BIT(2) BIT 491 drivers/edac/xgene_edac.c #define MEMERR_L2C_L2ESR_UCERR_MASK BIT(1) BIT 492 drivers/edac/xgene_edac.c #define MEMERR_L2C_L2ESR_ERR_MASK BIT(0) BIT 497 drivers/edac/xgene_edac.c #define MEMERR_L2C_L2RTOSR_MULTERR_MASK BIT(1) BIT 498 drivers/edac/xgene_edac.c #define MEMERR_L2C_L2RTOSR_ERR_MASK BIT(0) BIT 991 drivers/edac/xgene_edac.c #define L3C_ESR_DATATAG_MASK BIT(9) BIT 992 drivers/edac/xgene_edac.c #define L3C_ESR_MULTIHIT_MASK BIT(8) BIT 993 drivers/edac/xgene_edac.c #define L3C_ESR_UCEVICT_MASK BIT(6) BIT 994 drivers/edac/xgene_edac.c #define L3C_ESR_MULTIUCERR_MASK BIT(5) BIT 995 drivers/edac/xgene_edac.c #define L3C_ESR_MULTICERR_MASK BIT(4) BIT 996 drivers/edac/xgene_edac.c #define L3C_ESR_UCERR_MASK BIT(3) BIT 997 drivers/edac/xgene_edac.c #define L3C_ESR_CERR_MASK BIT(2) BIT 998 drivers/edac/xgene_edac.c #define L3C_ESR_UCERRINTR_MASK BIT(1) BIT 999 drivers/edac/xgene_edac.c #define L3C_ESR_CERRINTR_MASK BIT(0) BIT 1001 drivers/edac/xgene_edac.c #define L3C_ECR_UCINTREN BIT(3) BIT 1002 drivers/edac/xgene_edac.c #define L3C_ECR_CINTREN BIT(2) BIT 1003 drivers/edac/xgene_edac.c #define L3C_UCERREN BIT(1) BIT 1004 drivers/edac/xgene_edac.c #define L3C_CERREN BIT(0) BIT 1274 drivers/edac/xgene_edac.c #define IOBAXIS0_M_ILLEGAL_ACCESS_MASK BIT(1) BIT 1275 drivers/edac/xgene_edac.c #define IOBAXIS0_ILLEGAL_ACCESS_MASK BIT(0) BIT 1279 drivers/edac/xgene_edac.c #define REQTYPE_RD(src) (((src) & BIT(0))) BIT 1286 drivers/edac/xgene_edac.c #define IOBPA_M_REQIDRAM_CORRUPT_MASK BIT(7) BIT 1287 drivers/edac/xgene_edac.c #define IOBPA_REQIDRAM_CORRUPT_MASK BIT(6) BIT 1288 drivers/edac/xgene_edac.c #define IOBPA_M_TRANS_CORRUPT_MASK BIT(5) BIT 1289 drivers/edac/xgene_edac.c #define IOBPA_TRANS_CORRUPT_MASK BIT(4) BIT 1290 drivers/edac/xgene_edac.c #define IOBPA_M_WDATA_CORRUPT_MASK BIT(3) BIT 1291 drivers/edac/xgene_edac.c #define IOBPA_WDATA_CORRUPT_MASK BIT(2) BIT 1292 drivers/edac/xgene_edac.c #define IOBPA_M_RDATA_CORRUPT_MASK BIT(1) BIT 1293 drivers/edac/xgene_edac.c #define IOBPA_RDATA_CORRUPT_MASK BIT(0) BIT 1295 drivers/edac/xgene_edac.c #define M_ILLEGAL_ACCESS_MASK BIT(15) BIT 1296 drivers/edac/xgene_edac.c #define ILLEGAL_ACCESS_MASK BIT(14) BIT 1297 drivers/edac/xgene_edac.c #define M_WIDRAM_CORRUPT_MASK BIT(13) BIT 1298 drivers/edac/xgene_edac.c #define WIDRAM_CORRUPT_MASK BIT(12) BIT 1299 drivers/edac/xgene_edac.c #define M_RIDRAM_CORRUPT_MASK BIT(11) BIT 1300 drivers/edac/xgene_edac.c #define RIDRAM_CORRUPT_MASK BIT(10) BIT 1301 drivers/edac/xgene_edac.c #define M_TRANS_CORRUPT_MASK BIT(9) BIT 1302 drivers/edac/xgene_edac.c #define TRANS_CORRUPT_MASK BIT(8) BIT 1303 drivers/edac/xgene_edac.c #define M_WDATA_CORRUPT_MASK BIT(7) BIT 1304 drivers/edac/xgene_edac.c #define WDATA_CORRUPT_MASK BIT(6) BIT 1305 drivers/edac/xgene_edac.c #define M_RBM_POISONED_REQ_MASK BIT(5) BIT 1306 drivers/edac/xgene_edac.c #define RBM_POISONED_REQ_MASK BIT(4) BIT 1307 drivers/edac/xgene_edac.c #define M_XGIC_POISONED_REQ_MASK BIT(3) BIT 1308 drivers/edac/xgene_edac.c #define XGIC_POISONED_REQ_MASK BIT(2) BIT 1309 drivers/edac/xgene_edac.c #define M_WRERR_RESP_MASK BIT(1) BIT 1310 drivers/edac/xgene_edac.c #define WRERR_RESP_MASK BIT(0) BIT 1313 drivers/edac/xgene_edac.c #define REQTYPE_F2_RD(src) ((src) & BIT(0)) BIT 1317 drivers/edac/xgene_edac.c #define M_WR_ACCESS_ERR_MASK BIT(3) BIT 1318 drivers/edac/xgene_edac.c #define WR_ACCESS_ERR_MASK BIT(2) BIT 1319 drivers/edac/xgene_edac.c #define M_RD_ACCESS_ERR_MASK BIT(1) BIT 1320 drivers/edac/xgene_edac.c #define RD_ACCESS_ERR_MASK BIT(0) BIT 1323 drivers/edac/xgene_edac.c #define REQTYPE_MASK BIT(26) BIT 1326 drivers/edac/xgene_edac.c #define MDED_ERR_MASK BIT(3) BIT 1327 drivers/edac/xgene_edac.c #define DED_ERR_MASK BIT(2) BIT 1328 drivers/edac/xgene_edac.c #define MSEC_ERR_MASK BIT(1) BIT 1329 drivers/edac/xgene_edac.c #define SEC_ERR_MASK BIT(0) BIT 1345 drivers/edac/xgene_edac.c #define STICKYERR_MASK BIT(0) BIT 1347 drivers/edac/xgene_edac.c #define AGENT_OFFLINE_ERR_MASK BIT(30) BIT 1348 drivers/edac/xgene_edac.c #define UNIMPL_RBPAGE_ERR_MASK BIT(29) BIT 1349 drivers/edac/xgene_edac.c #define WORD_ALIGNED_ERR_MASK BIT(28) BIT 1350 drivers/edac/xgene_edac.c #define PAGE_ACCESS_ERR_MASK BIT(27) BIT 1351 drivers/edac/xgene_edac.c #define WRITE_ACCESS_MASK BIT(26) BIT 29 drivers/extcon/extcon-axp288.c #define PS_STAT_VBUS_TRIGGER BIT(0) BIT 30 drivers/extcon/extcon-axp288.c #define PS_STAT_BAT_CHRG_DIR BIT(2) BIT 31 drivers/extcon/extcon-axp288.c #define PS_STAT_VBUS_ABOVE_VHOLD BIT(3) BIT 32 drivers/extcon/extcon-axp288.c #define PS_STAT_VBUS_VALID BIT(4) BIT 33 drivers/extcon/extcon-axp288.c #define PS_STAT_VBUS_PRESENT BIT(5) BIT 36 drivers/extcon/extcon-axp288.c #define BC_GLOBAL_RUN BIT(0) BIT 37 drivers/extcon/extcon-axp288.c #define BC_GLOBAL_DET_STAT BIT(2) BIT 38 drivers/extcon/extcon-axp288.c #define BC_GLOBAL_DBP_TOUT BIT(3) BIT 39 drivers/extcon/extcon-axp288.c #define BC_GLOBAL_VLGC_COM_SEL BIT(4) BIT 40 drivers/extcon/extcon-axp288.c #define BC_GLOBAL_DCD_TOUT_MASK (BIT(6)|BIT(5)) BIT 45 drivers/extcon/extcon-axp288.c #define BC_GLOBAL_DCD_DET_SEL BIT(7) BIT 48 drivers/extcon/extcon-axp288.c #define VBUS_CNTL_DPDM_PD_EN BIT(4) BIT 49 drivers/extcon/extcon-axp288.c #define VBUS_CNTL_DPDM_FD_EN BIT(5) BIT 50 drivers/extcon/extcon-axp288.c #define VBUS_CNTL_FIRST_PO_STAT BIT(6) BIT 53 drivers/extcon/extcon-axp288.c #define USB_STAT_BUS_STAT_MASK (BIT(3)|BIT(2)|BIT(1)|BIT(0)) BIT 59 drivers/extcon/extcon-axp288.c #define USB_STAT_USB_SS_MODE BIT(4) BIT 60 drivers/extcon/extcon-axp288.c #define USB_STAT_DEAD_BAT_DET BIT(6) BIT 61 drivers/extcon/extcon-axp288.c #define USB_STAT_DBP_UNCFG BIT(7) BIT 64 drivers/extcon/extcon-axp288.c #define DET_STAT_MASK (BIT(7)|BIT(6)|BIT(5)) BIT 25 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0) BIT 26 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1) BIT 27 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2) BIT 28 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3) BIT 29 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL0_TTLCK BIT(4) BIT 30 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL0_CCSM_OFF BIT(5) BIT 31 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL0_DBPOFF BIT(6) BIT 32 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL0_CHR_WDT_NOKICK BIT(7) BIT 35 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL1_FUSB_INLMT_100 BIT(0) BIT 36 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL1_FUSB_INLMT_150 BIT(1) BIT 37 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL1_FUSB_INLMT_500 BIT(2) BIT 38 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL1_FUSB_INLMT_900 BIT(3) BIT 39 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL1_FUSB_INLMT_1500 BIT(4) BIT 40 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL1_FTEMP_EVENT BIT(5) BIT 41 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL1_OTGMODE BIT(6) BIT 42 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGRCTRL1_DBPEN BIT(7) BIT 62 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGDISCTRL_OUT BIT(0) BIT 64 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGDISCTRL_DRV BIT(4) BIT 66 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_CHGDISCTRL_FN BIT(6) BIT 71 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_PWRSRC_VBUS BIT(0) BIT 72 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_PWRSRC_DC BIT(1) BIT 73 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_PWRSRC_BATT BIT(2) BIT 81 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_VBUS_GPIO_CTLO_OUTPUT BIT(0) BIT 82 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_VBUS_GPIO_CTLO_DRV_OD BIT(4) BIT 83 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_VBUS_GPIO_CTLO_DIR_OUT BIT(5) BIT 21 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_USBIDCTRL_ID BIT(0) BIT 22 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_USBIDCTRL_ACA BIT(1) BIT 26 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_USBIDSTS_GND BIT(0) BIT 33 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_USBIDSTS_FLOAT BIT(3) BIT 34 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_USBIDSTS_SHORT BIT(4) BIT 40 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_CHGRCTRL0_CHGRRESET BIT(0) BIT 41 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_CHGRCTRL0_EMRGCHREN BIT(1) BIT 42 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_CHGRCTRL0_EXTCHRDIS BIT(2) BIT 43 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_CHGRCTRL0_SWCONTROL BIT(3) BIT 44 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_CHGRCTRL0_TTLCK BIT(4) BIT 45 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_CHGRCTRL0_BIT_5 BIT(5) BIT 46 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_CHGRCTRL0_BIT_6 BIT(6) BIT 47 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_CHGRCTRL0_CHR_WDT_NOKICK BIT(7) BIT 183 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT1_ATTACH_MASK BIT(0) BIT 184 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT1_DETACH_MASK BIT(1) BIT 185 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT1_CHGDET_MASK BIT(2) BIT 186 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT1_DCD_T_MASK BIT(3) BIT 187 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT1_OVP_MASK BIT(4) BIT 188 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT1_CONNECT_MASK BIT(5) BIT 189 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT1_ADC_CHG_MASK BIT(6) BIT 190 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT1_OTP_MASK BIT(7) BIT 191 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT2_UVLOT_MASK BIT(0) BIT 192 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT2_POR_MASK BIT(1) BIT 193 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT2_OTP_FET_MASK BIT(2) BIT 194 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT2_OVP_FET_MASK BIT(3) BIT 195 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT2_OCP_LATCH_MASK BIT(4) BIT 196 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT2_OCP_MASK BIT(5) BIT 197 drivers/extcon/extcon-rt8973a.h #define RT8973A_INT2_OVP_OCP_MASK BIT(6) BIT 265 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT1_ATTACH_MASK BIT(0) BIT 266 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT1_DETACH_MASK BIT(1) BIT 267 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT1_KP_MASK BIT(2) BIT 268 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT1_LKP_MASK BIT(3) BIT 269 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT1_LKR_MASK BIT(4) BIT 270 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT1_OVP_EVENT_MASK BIT(5) BIT 271 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT1_OCP_EVENT_MASK BIT(6) BIT 272 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT1_OVP_OCP_DIS_MASK BIT(7) BIT 273 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT2_VBUS_DET_MASK BIT(0) BIT 274 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT2_REV_ACCE_MASK BIT(1) BIT 275 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT2_ADC_CHG_MASK BIT(2) BIT 276 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT2_STUCK_KEY_MASK BIT(3) BIT 277 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK BIT(4) BIT 278 drivers/extcon/extcon-sm5502.h #define SM5502_IRQ_INT2_MHL_MASK BIT(5) BIT 277 drivers/extcon/extcon.c return !!(edev->state & BIT(index)); BIT 283 drivers/extcon/extcon.c int state = !!(edev->state & BIT(index)); BIT 360 drivers/extcon/extcon.c !!(edev->state & BIT(i))); BIT 428 drivers/extcon/extcon.c state = !!(edev->state & BIT(index)); BIT 541 drivers/extcon/extcon.c (edev->state & ~BIT(index)) | (state & BIT(index)))) { BIT 555 drivers/extcon/extcon.c edev->state |= BIT(index); BIT 557 drivers/extcon/extcon.c edev->state &= ~(BIT(index)); BIT 26 drivers/firmware/arm_scmi/clock.c #define CLOCK_ENABLE BIT(0) BIT 43 drivers/firmware/arm_scmi/clock.c #define RATE_DISCRETE(x) !((x) & BIT(12)) BIT 58 drivers/firmware/arm_scmi/clock.c #define CLOCK_SET_ASYNC BIT(0) BIT 59 drivers/firmware/arm_scmi/clock.c #define CLOCK_SET_IGNORE_RESP BIT(1) BIT 60 drivers/firmware/arm_scmi/clock.c #define CLOCK_SET_ROUND_UP BIT(2) BIT 61 drivers/firmware/arm_scmi/clock.c #define CLOCK_SET_ROUND_AUTO BIT(3) BIT 152 drivers/firmware/arm_scmi/driver.c #define SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR BIT(1) BIT 153 drivers/firmware/arm_scmi/driver.c #define SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE BIT(0) BIT 156 drivers/firmware/arm_scmi/driver.c #define SCMI_SHMEM_FLAG_INTR_ENABLED BIT(0) BIT 39 drivers/firmware/arm_scmi/perf.c #define POWER_SCALE_IN_MILLIWATT(x) ((x) & BIT(0)) BIT 47 drivers/firmware/arm_scmi/perf.c #define SUPPORTS_SET_LIMITS(x) ((x) & BIT(31)) BIT 48 drivers/firmware/arm_scmi/perf.c #define SUPPORTS_SET_PERF_LVL(x) ((x) & BIT(30)) BIT 49 drivers/firmware/arm_scmi/perf.c #define SUPPORTS_PERF_LIMIT_NOTIFY(x) ((x) & BIT(29)) BIT 50 drivers/firmware/arm_scmi/perf.c #define SUPPORTS_PERF_LEVEL_NOTIFY(x) ((x) & BIT(28)) BIT 51 drivers/firmware/arm_scmi/perf.c #define SUPPORTS_PERF_FASTCHANNELS(x) ((x) & BIT(27)) BIT 102 drivers/firmware/arm_scmi/perf.c #define SUPPORTS_DOORBELL(x) ((x) & BIT(0)) BIT 27 drivers/firmware/arm_scmi/power.c #define SUPPORTS_STATE_SET_NOTIFY(x) ((x) & BIT(31)) BIT 28 drivers/firmware/arm_scmi/power.c #define SUPPORTS_STATE_SET_ASYNC(x) ((x) & BIT(30)) BIT 29 drivers/firmware/arm_scmi/power.c #define SUPPORTS_STATE_SET_SYNC(x) ((x) & BIT(29)) BIT 35 drivers/firmware/arm_scmi/power.c #define STATE_SET_ASYNC BIT(0) BIT 21 drivers/firmware/arm_scmi/reset.c #define RESET_NOTIFY_ENABLE BIT(0) BIT 25 drivers/firmware/arm_scmi/reset.c #define SUPPORTS_ASYNC_RESET(x) ((x) & BIT(31)) BIT 26 drivers/firmware/arm_scmi/reset.c #define SUPPORTS_NOTIFY_RESET(x) ((x) & BIT(30)) BIT 34 drivers/firmware/arm_scmi/reset.c #define AUTONOMOUS_RESET BIT(0) BIT 35 drivers/firmware/arm_scmi/reset.c #define EXPLICIT_RESET_ASSERT BIT(1) BIT 36 drivers/firmware/arm_scmi/reset.c #define ASYNCHRONOUS_RESET BIT(2) BIT 38 drivers/firmware/arm_scmi/reset.c #define ARCH_RESET_TYPE BIT(31) BIT 39 drivers/firmware/arm_scmi/reset.c #define COLD_RESET_STATE BIT(0) BIT 32 drivers/firmware/arm_scmi/sensors.c #define SUPPORTS_ASYNC_READ(x) ((x) & BIT(31)) BIT 37 drivers/firmware/arm_scmi/sensors.c #define SENSOR_SCALE_SIGN BIT(4) BIT 48 drivers/firmware/arm_scmi/sensors.c #define SENSOR_TP_NOTIFY_ALL BIT(0) BIT 67 drivers/firmware/arm_scmi/sensors.c #define SENSOR_READ_ASYNC BIT(0) BIT 499 drivers/firmware/arm_scpi.c msg->slot = BIT(SCPI_SLOT); BIT 175 drivers/firmware/broadcom/bcm47xx_sprom.c if (_revmask & BIT(sprom->revision)) \ BIT 219 drivers/firmware/qcom_scm-32.c #define SCM_MASK_IRQS BIT(5) BIT 254 drivers/firmware/qcom_scm-64.c arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)), BIT 28 drivers/firmware/qcom_scm.c #define SCM_HAS_CORE_CLK BIT(0) BIT 29 drivers/firmware/qcom_scm.c #define SCM_HAS_IFACE_CLK BIT(1) BIT 30 drivers/firmware/qcom_scm.c #define SCM_HAS_BUS_CLK BIT(2) BIT 488 drivers/firmware/qcom_scm.c next_vm |= BIT(newvm->vmid); BIT 76 drivers/firmware/stratix10-rsu.c if (data->status == BIT(SVC_STATUS_RSU_OK)) { BIT 112 drivers/firmware/stratix10-rsu.c if (data->status != BIT(SVC_STATUS_RSU_OK)) BIT 134 drivers/firmware/stratix10-rsu.c if (data->status == BIT(SVC_STATUS_RSU_OK)) BIT 217 drivers/firmware/stratix10-svc.c cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_DONE); BIT 253 drivers/firmware/stratix10-svc.c cb_data->status = BIT(SVC_STATUS_RECONFIG_ERROR); BIT 274 drivers/firmware/stratix10-svc.c cb_data->status = BIT(SVC_STATUS_RECONFIG_COMPLETED); BIT 297 drivers/firmware/stratix10-svc.c cb_data->status = BIT(SVC_STATUS_RECONFIG_REQUEST_OK); BIT 300 drivers/firmware/stratix10-svc.c cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED); BIT 303 drivers/firmware/stratix10-svc.c cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED); BIT 307 drivers/firmware/stratix10-svc.c cb_data->status = BIT(SVC_STATUS_RECONFIG_COMPLETED); BIT 311 drivers/firmware/stratix10-svc.c cb_data->status = BIT(SVC_STATUS_RSU_OK); BIT 314 drivers/firmware/stratix10-svc.c cb_data->status = BIT(SVC_STATUS_RSU_OK); BIT 433 drivers/firmware/stratix10-svc.c cbdata->status = BIT(SVC_STATUS_RSU_ERROR); BIT 435 drivers/firmware/stratix10-svc.c cbdata->status = BIT(SVC_STATUS_RSU_OK); BIT 476 drivers/firmware/stratix10-svc.c BIT(SVC_STATUS_RECONFIG_ERROR); BIT 485 drivers/firmware/stratix10-svc.c BIT(SVC_STATUS_RSU_ERROR); BIT 489 drivers/firmware/stratix10-svc.c cbdata->status = BIT(SVC_STATUS_RECONFIG_ERROR); BIT 23 drivers/firmware/tegra/bpmp.c #define MSG_ACK BIT(0) BIT 24 drivers/firmware/tegra/bpmp.c #define MSG_RING BIT(1) BIT 29 drivers/fpga/altera-cvp.c #define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */ BIT 30 drivers/fpga/altera-cvp.c #define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */ BIT 31 drivers/fpga/altera-cvp.c #define VSE_CVP_STATUS_CVP_EN BIT(20) /* ctrl block is enabling CVP */ BIT 32 drivers/fpga/altera-cvp.c #define VSE_CVP_STATUS_USERMODE BIT(21) /* USERMODE */ BIT 33 drivers/fpga/altera-cvp.c #define VSE_CVP_STATUS_CFG_DONE BIT(23) /* CVP_CONFIG_DONE */ BIT 34 drivers/fpga/altera-cvp.c #define VSE_CVP_STATUS_PLD_CLK_IN_USE BIT(24) /* PLD_CLK_IN_USE */ BIT 37 drivers/fpga/altera-cvp.c #define VSE_CVP_MODE_CTRL_CVP_MODE BIT(0) /* CVP (1) or normal mode (0) */ BIT 38 drivers/fpga/altera-cvp.c #define VSE_CVP_MODE_CTRL_HIP_CLK_SEL BIT(1) /* PMA (1) or fabric clock (0) */ BIT 44 drivers/fpga/altera-cvp.c #define VSE_CVP_PROG_CTRL_CONFIG BIT(0) BIT 45 drivers/fpga/altera-cvp.c #define VSE_CVP_PROG_CTRL_START_XFER BIT(1) BIT 49 drivers/fpga/altera-cvp.c #define VSE_UNCOR_ERR_CVP_CFG_ERR BIT(5) /* CVP_CONFIG_ERROR_LATCHED */ BIT 277 drivers/fpga/altera-cvp.c mask = BIT(remainder * 8) - 1; BIT 22 drivers/fpga/altera-freeze-bridge.c #define FREEZE_CSR_STATUS_FREEZE_REQ_DONE BIT(0) BIT 23 drivers/fpga/altera-freeze-bridge.c #define FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE BIT(1) BIT 25 drivers/fpga/altera-freeze-bridge.c #define FREEZE_CSR_CTRL_FREEZE_REQ BIT(0) BIT 26 drivers/fpga/altera-freeze-bridge.c #define FREEZE_CSR_CTRL_RESET_REQ BIT(1) BIT 27 drivers/fpga/altera-freeze-bridge.c #define FREEZE_CSR_CTRL_UNFREEZE_REQ BIT(2) BIT 18 drivers/fpga/altera-pr-ip-core.c #define ALT_PR_CSR_PR_START BIT(0) BIT 36 drivers/fpga/dfl-pci.c if (pcim_iomap_regions(pcidev, BIT(bar), DRV_NAME)) BIT 23 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_DCLKSTAT_DCLKDONE BIT(0) BIT 25 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG BIT(0) BIT 26 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS BIT(1) BIT 27 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE BIT(2) BIT 28 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG BIT(8) BIT 29 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE BIT(16) BIT 30 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE BIT(24) BIT 32 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG BIT(0) BIT 33 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST BIT(16) BIT 34 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE BIT(24) BIT 36 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL BIT(0) BIT 37 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK (BIT(16) | BIT(17)) BIT 39 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH BIT(24) BIT 42 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR BIT(0) BIT 43 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE BIT(1) BIT 44 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE BIT(2) BIT 45 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN BIT(4) BIT 46 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN BIT(6) BIT 47 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY BIT(9) BIT 48 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE BIT(10) BIT 49 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR BIT(11) BIT 50 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN BIT(12) BIT 51 drivers/fpga/socfpga-a10.c #define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK (BIT(16) | BIT(17) | BIT(18)) BIT 161 drivers/fpga/stratix10-soc.c if (status & BIT(SVC_STATUS_RECONFIG_BUFFER_DONE)) { BIT 188 drivers/fpga/stratix10-soc.c ctype.flags |= BIT(COMMAND_RECONFIG_FLAG_PARTIAL); BIT 17 drivers/fpga/xilinx-pr-decoupler.c #define CTRL_CMD_DECOUPLE BIT(0) BIT 62 drivers/fpga/zynq-fpga.c #define CTRL_PCFG_PROG_B_MASK BIT(30) BIT 64 drivers/fpga/zynq-fpga.c #define CTRL_PCAP_PR_MASK BIT(27) BIT 66 drivers/fpga/zynq-fpga.c #define CTRL_PCAP_MODE_MASK BIT(26) BIT 68 drivers/fpga/zynq-fpga.c #define CTRL_PCAP_RATE_EN_MASK BIT(25) BIT 70 drivers/fpga/zynq-fpga.c #define CTRL_SEC_EN_MASK BIT(7) BIT 74 drivers/fpga/zynq-fpga.c #define MCTRL_PCAP_LPBK_MASK BIT(4) BIT 79 drivers/fpga/zynq-fpga.c #define STATUS_DMA_Q_F BIT(31) BIT 80 drivers/fpga/zynq-fpga.c #define STATUS_DMA_Q_E BIT(30) BIT 81 drivers/fpga/zynq-fpga.c #define STATUS_PCFG_INIT_MASK BIT(4) BIT 85 drivers/fpga/zynq-fpga.c #define IXR_DMA_DONE_MASK BIT(13) BIT 87 drivers/fpga/zynq-fpga.c #define IXR_D_P_DONE_MASK BIT(12) BIT 89 drivers/fpga/zynq-fpga.c #define IXR_PCFG_DONE_MASK BIT(2) BIT 16 drivers/fpga/zynqmp-fpga.c #define IXR_FPGA_DONE_MASK BIT(3) BIT 563 drivers/fsi/fsi-core.c offset_unit = BIT(__builtin_ctzl(offset | 4)); BIT 566 drivers/fsi/fsi-core.c count_unit = BIT(8 * sizeof(unsigned long) - 1 - __builtin_clzl(count)); BIT 569 drivers/fsi/fsi-core.c return BIT(__builtin_ctzl(offset_unit | count_unit)); BIT 23 drivers/gnss/core.c #define GNSS_FLAG_HAS_WRITE_RAW BIT(0) BIT 60 drivers/gpio/gpio-104-dio-48e.c const unsigned mask = BIT(offset % 8); BIT 81 drivers/gpio/gpio-104-dio-48e.c dio48egpio->control[control_port] |= BIT(3); BIT 84 drivers/gpio/gpio-104-dio-48e.c dio48egpio->control[control_port] |= BIT(0); BIT 89 drivers/gpio/gpio-104-dio-48e.c dio48egpio->control[control_port] |= BIT(4); BIT 91 drivers/gpio/gpio-104-dio-48e.c dio48egpio->control[control_port] |= BIT(1); BIT 94 drivers/gpio/gpio-104-dio-48e.c control = BIT(7) | dio48egpio->control[control_port]; BIT 96 drivers/gpio/gpio-104-dio-48e.c control &= ~BIT(7); BIT 110 drivers/gpio/gpio-104-dio-48e.c const unsigned mask = BIT(offset % 8); BIT 123 drivers/gpio/gpio-104-dio-48e.c dio48egpio->control[control_port] &= ~BIT(3); BIT 126 drivers/gpio/gpio-104-dio-48e.c dio48egpio->control[control_port] &= ~BIT(0); BIT 131 drivers/gpio/gpio-104-dio-48e.c dio48egpio->control[control_port] &= ~BIT(4); BIT 133 drivers/gpio/gpio-104-dio-48e.c dio48egpio->control[control_port] &= ~BIT(1); BIT 141 drivers/gpio/gpio-104-dio-48e.c control = BIT(7) | dio48egpio->control[control_port]; BIT 146 drivers/gpio/gpio-104-dio-48e.c control &= ~BIT(7); BIT 158 drivers/gpio/gpio-104-dio-48e.c const unsigned mask = BIT(offset % 8); BIT 227 drivers/gpio/gpio-104-dio-48e.c const unsigned mask = BIT(offset % 8); BIT 299 drivers/gpio/gpio-104-dio-48e.c dio48egpio->irq_mask &= ~BIT(0); BIT 301 drivers/gpio/gpio-104-dio-48e.c dio48egpio->irq_mask &= ~BIT(1); BIT 330 drivers/gpio/gpio-104-dio-48e.c dio48egpio->irq_mask |= BIT(0); BIT 332 drivers/gpio/gpio-104-dio-48e.c dio48egpio->irq_mask |= BIT(1); BIT 75 drivers/gpio/gpio-104-idi-48.c mask = BIT(offset - i); BIT 145 drivers/gpio/gpio-104-idi-48.c mask = BIT(offset - i); BIT 151 drivers/gpio/gpio-104-idi-48.c idi48gpio->cos_enb &= ~BIT(boundary); BIT 178 drivers/gpio/gpio-104-idi-48.c mask = BIT(offset - i); BIT 185 drivers/gpio/gpio-104-idi-48.c idi48gpio->cos_enb |= BIT(boundary); BIT 236 drivers/gpio/gpio-104-idi-48.c if (cos_status & BIT(6)) { BIT 74 drivers/gpio/gpio-104-idio-16.c const unsigned mask = BIT(offset-16); BIT 102 drivers/gpio/gpio-104-idio-16.c const unsigned mask = BIT(offset); BIT 150 drivers/gpio/gpio-104-idio-16.c const unsigned long mask = BIT(irqd_to_hwirq(data)); BIT 168 drivers/gpio/gpio-104-idio-16.c const unsigned long mask = BIT(irqd_to_hwirq(data)); BIT 77 drivers/gpio/gpio-adnp.c return (value & BIT(pos)) ? 1 : 0; BIT 92 drivers/gpio/gpio-adnp.c val |= BIT(pos); BIT 94 drivers/gpio/gpio-adnp.c val &= ~BIT(pos); BIT 122 drivers/gpio/gpio-adnp.c value &= ~BIT(pos); BIT 132 drivers/gpio/gpio-adnp.c if (value & BIT(pos)) { BIT 159 drivers/gpio/gpio-adnp.c val |= BIT(pos); BIT 169 drivers/gpio/gpio-adnp.c if (!(val & BIT(pos))) { BIT 218 drivers/gpio/gpio-adnp.c if (ddr & BIT(j)) BIT 221 drivers/gpio/gpio-adnp.c if (plr & BIT(j)) BIT 224 drivers/gpio/gpio-adnp.c if (ier & BIT(j)) BIT 227 drivers/gpio/gpio-adnp.c if (isr & BIT(j)) BIT 338 drivers/gpio/gpio-adnp.c adnp->irq_enable[reg] &= ~BIT(pos); BIT 348 drivers/gpio/gpio-adnp.c adnp->irq_enable[reg] |= BIT(pos); BIT 359 drivers/gpio/gpio-adnp.c adnp->irq_rise[reg] |= BIT(pos); BIT 361 drivers/gpio/gpio-adnp.c adnp->irq_rise[reg] &= ~BIT(pos); BIT 364 drivers/gpio/gpio-adnp.c adnp->irq_fall[reg] |= BIT(pos); BIT 366 drivers/gpio/gpio-adnp.c adnp->irq_fall[reg] &= ~BIT(pos); BIT 369 drivers/gpio/gpio-adnp.c adnp->irq_high[reg] |= BIT(pos); BIT 371 drivers/gpio/gpio-adnp.c adnp->irq_high[reg] &= ~BIT(pos); BIT 374 drivers/gpio/gpio-adnp.c adnp->irq_low[reg] |= BIT(pos); BIT 376 drivers/gpio/gpio-adnp.c adnp->irq_low[reg] &= ~BIT(pos); BIT 33 drivers/gpio/gpio-altera-a10sr.c return !!(val & BIT(offset - ALTR_A10SR_LED_VALID_SHIFT)); BIT 42 drivers/gpio/gpio-altera-a10sr.c BIT(ALTR_A10SR_LED_VALID_SHIFT + offset), BIT 43 drivers/gpio/gpio-altera-a10sr.c value ? BIT(ALTR_A10SR_LED_VALID_SHIFT + offset) BIT 49 drivers/gpio/gpio-altera.c intmask |= BIT(irqd_to_hwirq(d)); BIT 67 drivers/gpio/gpio-altera.c intmask &= ~BIT(irqd_to_hwirq(d)); BIT 111 drivers/gpio/gpio-altera.c return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset)); BIT 127 drivers/gpio/gpio-altera.c data_reg |= BIT(offset); BIT 129 drivers/gpio/gpio-altera.c data_reg &= ~BIT(offset); BIT 147 drivers/gpio/gpio-altera.c gpio_ddr &= ~BIT(offset); BIT 169 drivers/gpio/gpio-altera.c data_reg |= BIT(offset); BIT 171 drivers/gpio/gpio-altera.c data_reg &= ~BIT(offset); BIT 176 drivers/gpio/gpio-altera.c gpio_ddr |= BIT(offset); BIT 24 drivers/gpio/gpio-amd-fch.c #define AMD_FCH_GPIO_FLAG_DIRECTION BIT(23) BIT 25 drivers/gpio/gpio-amd-fch.c #define AMD_FCH_GPIO_FLAG_WRITE BIT(22) BIT 26 drivers/gpio/gpio-amd-fch.c #define AMD_FCH_GPIO_FLAG_READ BIT(16) BIT 41 drivers/gpio/gpio-amdpt.c if (using_pins & BIT(offset)) { BIT 48 drivers/gpio/gpio-amdpt.c writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); BIT 64 drivers/gpio/gpio-amdpt.c using_pins &= ~BIT(offset); BIT 245 drivers/gpio/gpio-aspeed.c #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) BIT 247 drivers/gpio/gpio-aspeed.c #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o)) BIT 318 drivers/gpio/gpio-aspeed.c bit = BIT((bindex & 3) << 3); BIT 71 drivers/gpio/gpio-ath79.c u32 mask = BIT(irqd_to_hwirq(data)); BIT 82 drivers/gpio/gpio-ath79.c u32 mask = BIT(irqd_to_hwirq(data)); BIT 93 drivers/gpio/gpio-ath79.c u32 mask = BIT(irqd_to_hwirq(data)); BIT 105 drivers/gpio/gpio-ath79.c u32 mask = BIT(irqd_to_hwirq(data)); BIT 118 drivers/gpio/gpio-ath79.c u32 mask = BIT(irqd_to_hwirq(data)); BIT 101 drivers/gpio/gpio-bcm-kona.c val |= BIT(gpio); BIT 117 drivers/gpio/gpio-bcm-kona.c val &= ~BIT(gpio); BIT 153 drivers/gpio/gpio-bcm-kona.c val |= BIT(bit); BIT 184 drivers/gpio/gpio-bcm-kona.c return !!(val & BIT(bit)); BIT 244 drivers/gpio/gpio-bcm-kona.c val |= BIT(bit); BIT 286 drivers/gpio/gpio-bcm-kona.c if (res > 0 && (debounce & BIT(res - 1))) BIT 353 drivers/gpio/gpio-bcm-kona.c val |= BIT(bit); BIT 374 drivers/gpio/gpio-bcm-kona.c val |= BIT(bit); BIT 396 drivers/gpio/gpio-bcm-kona.c val |= BIT(bit); BIT 478 drivers/gpio/gpio-bcm-kona.c BIT(bit), reg_base + GPIO_INT_STATUS(bank_id)); BIT 41 drivers/gpio/gpio-bd9571mwv.c return val & BIT(offset); BIT 50 drivers/gpio/gpio-bd9571mwv.c BIT(offset), 0); BIT 62 drivers/gpio/gpio-bd9571mwv.c BIT(offset), value ? BIT(offset) : 0); BIT 64 drivers/gpio/gpio-bd9571mwv.c BIT(offset), BIT(offset)); BIT 78 drivers/gpio/gpio-bd9571mwv.c return val & BIT(offset); BIT 87 drivers/gpio/gpio-bd9571mwv.c BIT(offset), value ? BIT(offset) : 0); BIT 113 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); BIT 161 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); BIT 171 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); BIT 247 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); BIT 46 drivers/gpio/gpio-cadence.c iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset), BIT 61 drivers/gpio/gpio-cadence.c (BIT(offset) & cgpio->bypass_orig), BIT 72 drivers/gpio/gpio-cadence.c iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_DIS); BIT 80 drivers/gpio/gpio-cadence.c iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_EN); BIT 90 drivers/gpio/gpio-cadence.c u32 mask = BIT(d->hwirq); BIT 22 drivers/gpio/gpio-crystalcove.c #define UPDATE_IRQ_TYPE BIT(0) BIT 23 drivers/gpio/gpio-crystalcove.c #define UPDATE_IRQ_MASK BIT(1) BIT 117 drivers/gpio/gpio-crystalcove.c int mask = BIT(gpio % 8); BIT 320 drivers/gpio/gpio-crystalcove.c mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask", BIT 321 drivers/gpio/gpio-crystalcove.c mirqsx & BIT(offset) ? "sx mask " : "sx unmask", BIT 322 drivers/gpio/gpio-crystalcove.c irq & BIT(offset) ? "pending" : " "); BIT 373 drivers/gpio/gpio-davinci.c status &= ~BIT(bit); BIT 621 drivers/gpio/gpio-davinci.c binten |= BIT(bank); BIT 183 drivers/gpio/gpio-dwapb.c pol &= ~BIT(offs); BIT 185 drivers/gpio/gpio-dwapb.c pol |= BIT(offs); BIT 200 drivers/gpio/gpio-dwapb.c irq_status &= ~BIT(hwirq); BIT 231 drivers/gpio/gpio-dwapb.c val |= BIT(d->hwirq); BIT 246 drivers/gpio/gpio-dwapb.c val &= ~BIT(d->hwirq); BIT 294 drivers/gpio/gpio-dwapb.c level |= BIT(bit); BIT 298 drivers/gpio/gpio-dwapb.c level |= BIT(bit); BIT 299 drivers/gpio/gpio-dwapb.c polarity |= BIT(bit); BIT 302 drivers/gpio/gpio-dwapb.c level |= BIT(bit); BIT 303 drivers/gpio/gpio-dwapb.c polarity &= ~BIT(bit); BIT 306 drivers/gpio/gpio-dwapb.c level &= ~BIT(bit); BIT 307 drivers/gpio/gpio-dwapb.c polarity |= BIT(bit); BIT 310 drivers/gpio/gpio-dwapb.c level &= ~BIT(bit); BIT 311 drivers/gpio/gpio-dwapb.c polarity &= ~BIT(bit); BIT 333 drivers/gpio/gpio-dwapb.c ctx->wake_en |= BIT(d->hwirq); BIT 335 drivers/gpio/gpio-dwapb.c ctx->wake_en &= ~BIT(d->hwirq); BIT 347 drivers/gpio/gpio-dwapb.c unsigned long mask = BIT(offset); BIT 153 drivers/gpio/gpio-eic-sprd.c tmp |= BIT(SPRD_EIC_BIT(offset)); BIT 155 drivers/gpio/gpio-eic-sprd.c tmp &= ~BIT(SPRD_EIC_BIT(offset)); BIT 167 drivers/gpio/gpio-eic-sprd.c return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); BIT 79 drivers/gpio/gpio-em.c em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d))); BIT 86 drivers/gpio/gpio-em.c em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d))); BIT 145 drivers/gpio/gpio-em.c tmp &= ~BIT(offset); BIT 155 drivers/gpio/gpio-em.c em_gio_write(p, GIO_IIR, BIT(offset)); BIT 159 drivers/gpio/gpio-em.c tmp |= BIT(offset); BIT 175 drivers/gpio/gpio-em.c em_gio_write(p, GIO_IIR, BIT(offset)); BIT 190 drivers/gpio/gpio-em.c em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset)); BIT 196 drivers/gpio/gpio-em.c return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset)); BIT 204 drivers/gpio/gpio-em.c (BIT(shift + 16)) | (value << shift)); BIT 221 drivers/gpio/gpio-em.c em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset)); BIT 96 drivers/gpio/gpio-ep93xx.c int port_mask = BIT(offset); BIT 158 drivers/gpio/gpio-ep93xx.c int port_mask = BIT(d->irq & 7); BIT 173 drivers/gpio/gpio-ep93xx.c int port_mask = BIT(d->irq & 7); BIT 190 drivers/gpio/gpio-ep93xx.c gpio_int_unmasked[port] &= ~BIT(d->irq & 7); BIT 200 drivers/gpio/gpio-ep93xx.c gpio_int_unmasked[port] |= BIT(d->irq & 7); BIT 215 drivers/gpio/gpio-ep93xx.c int port_mask = BIT(offset); BIT 42 drivers/gpio/gpio-exar.c temp &= ~BIT(offset); BIT 44 drivers/gpio/gpio-exar.c temp |= BIT(offset); BIT 80 drivers/gpio/gpio-exar.c return !!(exar_get(chip, addr) & BIT(bit)); BIT 90 drivers/gpio/gpio-exar.c return !!(exar_get(chip, addr) & BIT(bit)); BIT 269 drivers/gpio/gpio-f7188x.c dir &= ~BIT(offset); BIT 290 drivers/gpio/gpio-f7188x.c dir = !!(dir & BIT(offset)); BIT 298 drivers/gpio/gpio-f7188x.c return !!(data & BIT(offset)); BIT 316 drivers/gpio/gpio-f7188x.c data_out |= BIT(offset); BIT 318 drivers/gpio/gpio-f7188x.c data_out &= ~BIT(offset); BIT 322 drivers/gpio/gpio-f7188x.c dir |= BIT(offset); BIT 344 drivers/gpio/gpio-f7188x.c data_out |= BIT(offset); BIT 346 drivers/gpio/gpio-f7188x.c data_out &= ~BIT(offset); BIT 372 drivers/gpio/gpio-f7188x.c data &= ~BIT(offset); BIT 374 drivers/gpio/gpio-f7188x.c data |= BIT(offset); BIT 61 drivers/gpio/gpio-ftgpio010.c writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR); BIT 71 drivers/gpio/gpio-ftgpio010.c val &= ~BIT(irqd_to_hwirq(d)); BIT 82 drivers/gpio/gpio-ftgpio010.c val |= BIT(irqd_to_hwirq(d)); BIT 90 drivers/gpio/gpio-ftgpio010.c u32 mask = BIT(irqd_to_hwirq(d)); BIT 202 drivers/gpio/gpio-ftgpio010.c val |= BIT(offset); BIT 219 drivers/gpio/gpio-ftgpio010.c val |= BIT(offset); BIT 53 drivers/gpio/gpio-gpio-mm.c const unsigned int mask = BIT(offset % 8); BIT 75 drivers/gpio/gpio-gpio-mm.c gpiommgpio->control[control_port] |= BIT(3); BIT 78 drivers/gpio/gpio-gpio-mm.c gpiommgpio->control[control_port] |= BIT(0); BIT 83 drivers/gpio/gpio-gpio-mm.c gpiommgpio->control[control_port] |= BIT(4); BIT 85 drivers/gpio/gpio-gpio-mm.c gpiommgpio->control[control_port] |= BIT(1); BIT 88 drivers/gpio/gpio-gpio-mm.c control = BIT(7) | gpiommgpio->control[control_port]; BIT 102 drivers/gpio/gpio-gpio-mm.c const unsigned int mask = BIT(offset % 8); BIT 115 drivers/gpio/gpio-gpio-mm.c gpiommgpio->control[control_port] &= ~BIT(3); BIT 118 drivers/gpio/gpio-gpio-mm.c gpiommgpio->control[control_port] &= ~BIT(0); BIT 123 drivers/gpio/gpio-gpio-mm.c gpiommgpio->control[control_port] &= ~BIT(4); BIT 125 drivers/gpio/gpio-gpio-mm.c gpiommgpio->control[control_port] &= ~BIT(1); BIT 133 drivers/gpio/gpio-gpio-mm.c control = BIT(7) | gpiommgpio->control[control_port]; BIT 147 drivers/gpio/gpio-gpio-mm.c const unsigned int mask = BIT(offset % 8); BIT 217 drivers/gpio/gpio-gpio-mm.c const unsigned int mask = BIT(offset % 8); BIT 96 drivers/gpio/gpio-grgpio.c priv->imask |= BIT(offset); BIT 98 drivers/gpio/gpio-grgpio.c priv->imask &= ~BIT(offset); BIT 121 drivers/gpio/gpio-grgpio.c u32 mask = BIT(d->hwirq); BIT 211 drivers/gpio/gpio-grgpio.c if (priv->imask & BIT(i) && lirq->index >= 0 && BIT 39 drivers/gpio/gpio-gw-pld.c gw->out |= BIT(offset); BIT 50 drivers/gpio/gpio-gw-pld.c return (val < 0) ? 0 : !!(val & BIT(offset)); BIT 58 drivers/gpio/gpio-gw-pld.c gw->out |= BIT(offset); BIT 60 drivers/gpio/gpio-gw-pld.c gw->out &= ~BIT(offset); BIT 114 drivers/gpio/gpio-hlwd.c iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG); BIT 126 drivers/gpio/gpio-hlwd.c mask &= ~BIT(data->hwirq); BIT 140 drivers/gpio/gpio-hlwd.c mask |= BIT(data->hwirq); BIT 158 drivers/gpio/gpio-hlwd.c state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq); BIT 159 drivers/gpio/gpio-hlwd.c level &= ~BIT(hwirq); BIT 160 drivers/gpio/gpio-hlwd.c level |= state ^ BIT(hwirq); BIT 163 drivers/gpio/gpio-hlwd.c hlwd->edge_emulation |= BIT(hwirq); BIT 164 drivers/gpio/gpio-hlwd.c hlwd->rising_edge &= ~BIT(hwirq); BIT 165 drivers/gpio/gpio-hlwd.c hlwd->falling_edge &= ~BIT(hwirq); BIT 167 drivers/gpio/gpio-hlwd.c hlwd->rising_edge |= BIT(hwirq); BIT 169 drivers/gpio/gpio-hlwd.c hlwd->falling_edge |= BIT(hwirq); BIT 181 drivers/gpio/gpio-hlwd.c hlwd->edge_emulation &= ~BIT(data->hwirq); BIT 186 drivers/gpio/gpio-hlwd.c level |= BIT(data->hwirq); BIT 191 drivers/gpio/gpio-hlwd.c level &= ~BIT(data->hwirq); BIT 119 drivers/gpio/gpio-ich.c data |= BIT(bit); BIT 121 drivers/gpio/gpio-ich.c data &= ~BIT(bit); BIT 152 drivers/gpio/gpio-ich.c return !!(data & BIT(bit)); BIT 157 drivers/gpio/gpio-ich.c return !!(ichx_priv.use_gpio & BIT(nr / 32)); BIT 212 drivers/gpio/gpio-ich.c ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base); BIT 217 drivers/gpio/gpio-ich.c return !!((data >> 16) & BIT(nr)); BIT 234 drivers/gpio/gpio-ich.c if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f)) BIT 374 drivers/gpio/gpio-ich.c if (!(use_gpio & BIT(i))) BIT 104 drivers/gpio/gpio-intel-mid.c return !!(readl(gplr) & BIT(offset % 32)); BIT 113 drivers/gpio/gpio-intel-mid.c writel(BIT(offset % 32), gpsr); BIT 116 drivers/gpio/gpio-intel-mid.c writel(BIT(offset % 32), gpcr); BIT 132 drivers/gpio/gpio-intel-mid.c value &= ~BIT(offset % 32); BIT 156 drivers/gpio/gpio-intel-mid.c value |= BIT(offset % 32); BIT 184 drivers/gpio/gpio-intel-mid.c value = readl(grer) | BIT(gpio % 32); BIT 186 drivers/gpio/gpio-intel-mid.c value = readl(grer) & (~BIT(gpio % 32)); BIT 190 drivers/gpio/gpio-intel-mid.c value = readl(gfer) | BIT(gpio % 32); BIT 192 drivers/gpio/gpio-intel-mid.c value = readl(gfer) & (~BIT(gpio % 32)); BIT 285 drivers/gpio/gpio-intel-mid.c mask = BIT(gpio); BIT 67 drivers/gpio/gpio-ixp4xx.c __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); BIT 76 drivers/gpio/gpio-ixp4xx.c if (!(g->irq_edge & BIT(d->hwirq))) BIT 96 drivers/gpio/gpio-ixp4xx.c g->irq_edge |= BIT(d->hwirq); BIT 101 drivers/gpio/gpio-ixp4xx.c g->irq_edge |= BIT(d->hwirq); BIT 106 drivers/gpio/gpio-ixp4xx.c g->irq_edge |= BIT(d->hwirq); BIT 111 drivers/gpio/gpio-ixp4xx.c g->irq_edge &= ~BIT(d->hwirq); BIT 116 drivers/gpio/gpio-ixp4xx.c g->irq_edge &= ~BIT(d->hwirq); BIT 138 drivers/gpio/gpio-ixp4xx.c __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); BIT 147 drivers/gpio/gpio-ixp4xx.c val |= BIT(d->hwirq); BIT 33 drivers/gpio/gpio-janz-ttl.c #define CONF_PAE BIT(2) BIT 34 drivers/gpio/gpio-janz-ttl.c #define CONF_PBE BIT(7) BIT 35 drivers/gpio/gpio-janz-ttl.c #define CONF_PCE BIT(4) BIT 74 drivers/gpio/gpio-janz-ttl.c ret = *shadow & BIT(offset); BIT 100 drivers/gpio/gpio-janz-ttl.c *shadow |= BIT(offset); BIT 102 drivers/gpio/gpio-janz-ttl.c *shadow &= ~BIT(offset); BIT 19 drivers/gpio/gpio-kempld.c #define KEMPLD_GPIO_MASK(x) (BIT((x) % 8)) BIT 48 drivers/gpio/gpio-loongson.c return !!(val & BIT(gpio + LOONGSON_GPIO_IN_OFFSET)); BIT 59 drivers/gpio/gpio-loongson.c val |= BIT(gpio); BIT 61 drivers/gpio/gpio-loongson.c val &= ~BIT(gpio); BIT 72 drivers/gpio/gpio-loongson.c temp |= BIT(gpio); BIT 87 drivers/gpio/gpio-loongson.c temp &= ~BIT(gpio); BIT 29 drivers/gpio/gpio-loongson1.c __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) | BIT(offset), BIT 41 drivers/gpio/gpio-loongson1.c __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) & ~BIT(offset), BIT 79 drivers/gpio/gpio-lp3943.c lp3943_gpio->input_mask |= BIT(offset); BIT 106 drivers/gpio/gpio-lp3943.c return !!(read & BIT(offset)); BIT 144 drivers/gpio/gpio-lp3943.c if (lp3943_gpio->input_mask & BIT(offset)) BIT 169 drivers/gpio/gpio-lp3943.c lp3943_gpio->input_mask &= ~BIT(offset); BIT 53 drivers/gpio/gpio-lp873x.c BIT(offset * BITS_PER_GPO), BIT 54 drivers/gpio/gpio-lp873x.c value ? BIT(offset * BITS_PER_GPO) : 0); BIT 66 drivers/gpio/gpio-lp873x.c return val & BIT(offset * BITS_PER_GPO); BIT 75 drivers/gpio/gpio-lp873x.c BIT(offset * BITS_PER_GPO), BIT 76 drivers/gpio/gpio-lp873x.c value ? BIT(offset * BITS_PER_GPO) : 0); BIT 112 drivers/gpio/gpio-lp873x.c BIT(offset * BITS_PER_GPO + BIT 114 drivers/gpio/gpio-lp873x.c BIT(offset * BITS_PER_GPO + BIT 120 drivers/gpio/gpio-lp873x.c BIT(offset * BITS_PER_GPO + BIT 38 drivers/gpio/gpio-lp87565.c return !!(val & BIT(offset)); BIT 47 drivers/gpio/gpio-lp87565.c BIT(offset), value ? BIT(offset) : 0); BIT 60 drivers/gpio/gpio-lp87565.c return !(val & BIT(offset)); BIT 70 drivers/gpio/gpio-lp87565.c BIT(offset), 0); BIT 82 drivers/gpio/gpio-lp87565.c BIT(offset), BIT(offset)); BIT 101 drivers/gpio/gpio-lp87565.c BIT(offset), BIT(offset)); BIT 122 drivers/gpio/gpio-lp87565.c BIT(offset + BIT 124 drivers/gpio/gpio-lp87565.c BIT(offset + BIT 129 drivers/gpio/gpio-lp87565.c BIT(offset + BIT 62 drivers/gpio/gpio-lpc18xx.c val &= ~BIT(pin); BIT 64 drivers/gpio/gpio-lpc18xx.c val |= BIT(pin); BIT 72 drivers/gpio/gpio-lpc18xx.c writel_relaxed(BIT(pin), ic->base + reg); BIT 293 drivers/gpio/gpio-lpc18xx.c dir |= BIT(pin); BIT 295 drivers/gpio/gpio-lpc18xx.c dir &= ~BIT(pin); BIT 36 drivers/gpio/gpio-lynxpoint.c #define OUT_LVL_BIT BIT(31) BIT 37 drivers/gpio/gpio-lynxpoint.c #define IN_LVL_BIT BIT(30) BIT 38 drivers/gpio/gpio-lynxpoint.c #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ BIT 39 drivers/gpio/gpio-lynxpoint.c #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ BIT 40 drivers/gpio/gpio-lynxpoint.c #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ BIT 41 drivers/gpio/gpio-lynxpoint.c #define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */ BIT 44 drivers/gpio/gpio-lynxpoint.c #define GPINDIS_BIT BIT(2) /* disable input sensing */ BIT 45 drivers/gpio/gpio-lynxpoint.c #define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */ BIT 109 drivers/gpio/gpio-lynxpoint.c if (!(inl(acpi_use) & BIT(offset % 32))) { BIT 250 drivers/gpio/gpio-lynxpoint.c outl(BIT(pin), reg); BIT 276 drivers/gpio/gpio-lynxpoint.c outl(inl(reg) | BIT(hwirq % 32), reg); BIT 289 drivers/gpio/gpio-lynxpoint.c outl(inl(reg) & ~BIT(hwirq % 32), reg); BIT 61 drivers/gpio/gpio-max730x.c if (ts->input_pullup_active & BIT(offset)) BIT 15 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_DIR_MASK BIT(0) BIT 16 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_INVAL_MASK BIT(1) BIT 17 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_DRV_MASK BIT(2) BIT 18 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_OUTVAL_MASK BIT(3) BIT 19 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_DEBOUNCE_MASK BIT(4) BIT 22 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_DIR_IN BIT(0) BIT 24 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_OUT_HIGH BIT(3) BIT 26 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_DRV_PUSH_PULL BIT(2) BIT 27 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_DEBOUNCE BIT(4) BIT 34 drivers/gpio/gpio-mb86s7x.c #define OFFSET(x) BIT((x) % 8) BIT 55 drivers/gpio/gpio-menz127.c if (rnd && (debounce & BIT(rnd - 1))) BIT 72 drivers/gpio/gpio-menz127.c db_en &= ~BIT(gpio); BIT 75 drivers/gpio/gpio-menz127.c db_en |= BIT(gpio); BIT 98 drivers/gpio/gpio-menz127.c od_en |= BIT(offset); BIT 101 drivers/gpio/gpio-menz127.c od_en &= ~BIT(offset); BIT 99 drivers/gpio/gpio-merrifield.c return !!(readl(gplr) & BIT(offset % 32)); BIT 113 drivers/gpio/gpio-merrifield.c writel(BIT(offset % 32), gpsr); BIT 116 drivers/gpio/gpio-merrifield.c writel(BIT(offset % 32), gpcr); BIT 133 drivers/gpio/gpio-merrifield.c value &= ~BIT(offset % 32); BIT 153 drivers/gpio/gpio-merrifield.c value |= BIT(offset % 32); BIT 165 drivers/gpio/gpio-merrifield.c return !(readl(gpdr) & BIT(offset % 32)); BIT 179 drivers/gpio/gpio-merrifield.c value = readl(gfbr) & ~BIT(offset % 32); BIT 181 drivers/gpio/gpio-merrifield.c value = readl(gfbr) | BIT(offset % 32); BIT 210 drivers/gpio/gpio-merrifield.c writel(BIT(gpio % 32), gisr); BIT 226 drivers/gpio/gpio-merrifield.c value = readl(gimr) | BIT(gpio % 32); BIT 228 drivers/gpio/gpio-merrifield.c value = readl(gimr) & ~BIT(gpio % 32); BIT 259 drivers/gpio/gpio-merrifield.c value = readl(grer) | BIT(gpio % 32); BIT 261 drivers/gpio/gpio-merrifield.c value = readl(grer) & ~BIT(gpio % 32); BIT 265 drivers/gpio/gpio-merrifield.c value = readl(gfer) | BIT(gpio % 32); BIT 267 drivers/gpio/gpio-merrifield.c value = readl(gfer) & ~BIT(gpio % 32); BIT 275 drivers/gpio/gpio-merrifield.c value = readl(glpr) | BIT(gpio % 32); BIT 277 drivers/gpio/gpio-merrifield.c value = readl(glpr) & ~BIT(gpio % 32); BIT 281 drivers/gpio/gpio-merrifield.c value = readl(gitr) | BIT(gpio % 32); BIT 286 drivers/gpio/gpio-merrifield.c value = readl(gitr) & ~BIT(gpio % 32); BIT 310 drivers/gpio/gpio-merrifield.c writel(BIT(gpio % 32), gwsr); BIT 313 drivers/gpio/gpio-merrifield.c value = readl(gwmr) | BIT(gpio % 32); BIT 315 drivers/gpio/gpio-merrifield.c value = readl(gwmr) & ~BIT(gpio % 32); BIT 410 drivers/gpio/gpio-merrifield.c retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev)); BIT 422 drivers/gpio/gpio-merrifield.c pcim_iounmap_regions(pdev, BIT(1)); BIT 14 drivers/gpio/gpio-ml-ioh.c #define IOH_EDGE_RISING BIT(0) BIT 15 drivers/gpio/gpio-ml-ioh.c #define IOH_LEVEL_L BIT(1) BIT 16 drivers/gpio/gpio-ml-ioh.c #define IOH_LEVEL_H (BIT(0) | BIT(1)) BIT 17 drivers/gpio/gpio-ml-ioh.c #define IOH_EDGE_BOTH BIT(2) BIT 18 drivers/gpio/gpio-ml-ioh.c #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2)) BIT 290 drivers/gpio/gpio-ml-ioh.c iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr); BIT 293 drivers/gpio/gpio-ml-ioh.c iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr); BIT 297 drivers/gpio/gpio-ml-ioh.c iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien); BIT 360 drivers/gpio/gpio-ml-ioh.c if (reg_val & BIT(j)) { BIT 364 drivers/gpio/gpio-ml-ioh.c iowrite32(BIT(j), BIT 128 drivers/gpio/gpio-mmio.c return BIT(gc->bgpio_bits - 1 - line); BIT 129 drivers/gpio/gpio-mmio.c return BIT(line); BIT 39 drivers/gpio/gpio-moxtet.c if (chip->desc->in_mask & BIT(offset)) { BIT 41 drivers/gpio/gpio-moxtet.c } else if (chip->desc->out_mask & BIT(offset)) { BIT 52 drivers/gpio/gpio-moxtet.c return !!(ret & BIT(offset)); BIT 68 drivers/gpio/gpio-moxtet.c state |= BIT(offset); BIT 70 drivers/gpio/gpio-moxtet.c state &= ~BIT(offset); BIT 80 drivers/gpio/gpio-moxtet.c if (chip->desc->in_mask & BIT(offset)) BIT 82 drivers/gpio/gpio-moxtet.c else if (chip->desc->out_mask & BIT(offset)) BIT 93 drivers/gpio/gpio-moxtet.c if (chip->desc->in_mask & BIT(offset)) BIT 95 drivers/gpio/gpio-moxtet.c else if (chip->desc->out_mask & BIT(offset)) BIT 106 drivers/gpio/gpio-moxtet.c if (chip->desc->out_mask & BIT(offset)) BIT 108 drivers/gpio/gpio-moxtet.c else if (chip->desc->in_mask & BIT(offset)) BIT 77 drivers/gpio/gpio-mpc8xxx.c return BIT(31 - offset); BIT 22 drivers/gpio/gpio-msic.c #define MSIC_GPIO_DIR_OUT BIT(5) BIT 23 drivers/gpio/gpio-msic.c #define MSIC_GPIO_TRIG_FALL BIT(1) BIT 24 drivers/gpio/gpio-msic.c #define MSIC_GPIO_TRIG_RISE BIT(2) BIT 27 drivers/gpio/gpio-msic.c #define MSIC_GPIO_DIR_MASK BIT(5) BIT 28 drivers/gpio/gpio-msic.c #define MSIC_GPIO_DRV_MASK BIT(4) BIT 29 drivers/gpio/gpio-msic.c #define MSIC_GPIO_REN_MASK BIT(3) BIT 30 drivers/gpio/gpio-msic.c #define MSIC_GPIO_RVAL_MASK (BIT(2) | BIT(1)) BIT 31 drivers/gpio/gpio-msic.c #define MSIC_GPIO_DOUT_MASK BIT(0) BIT 34 drivers/gpio/gpio-msic.c #define MSIC_GPIO_GLBYP_MASK BIT(5) BIT 35 drivers/gpio/gpio-msic.c #define MSIC_GPIO_DBNC_MASK (BIT(4) | BIT(3)) BIT 36 drivers/gpio/gpio-msic.c #define MSIC_GPIO_INTCNT_MASK (BIT(2) | BIT(1)) BIT 37 drivers/gpio/gpio-msic.c #define MSIC_GPIO_DIN_MASK BIT(0) BIT 101 drivers/gpio/gpio-mt7621.c mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); BIT 122 drivers/gpio/gpio-mt7621.c mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising)); BIT 123 drivers/gpio/gpio-mt7621.c mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling)); BIT 124 drivers/gpio/gpio-mt7621.c mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel)); BIT 125 drivers/gpio/gpio-mt7621.c mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel)); BIT 143 drivers/gpio/gpio-mt7621.c mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin)); BIT 144 drivers/gpio/gpio-mt7621.c mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin)); BIT 145 drivers/gpio/gpio-mt7621.c mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin)); BIT 146 drivers/gpio/gpio-mt7621.c mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin)); BIT 156 drivers/gpio/gpio-mt7621.c u32 mask = BIT(pin); BIT 304 drivers/gpio/gpio-mvebu.c BIT(pin), value ? BIT(pin) : 0); BIT 314 drivers/gpio/gpio-mvebu.c if (u & BIT(pin)) { BIT 335 drivers/gpio/gpio-mvebu.c BIT(pin), value ? BIT(pin) : 0); BIT 352 drivers/gpio/gpio-mvebu.c BIT(pin), BIT(pin)); BIT 375 drivers/gpio/gpio-mvebu.c BIT(pin), 0); BIT 387 drivers/gpio/gpio-mvebu.c return !!(u & BIT(pin)); BIT 500 drivers/gpio/gpio-mvebu.c if ((u & BIT(pin)) == 0) BIT 520 drivers/gpio/gpio-mvebu.c BIT(pin), 0); BIT 526 drivers/gpio/gpio-mvebu.c BIT(pin), BIT(pin)); BIT 539 drivers/gpio/gpio-mvebu.c if ((data_in ^ in_pol) & BIT(pin)) BIT 540 drivers/gpio/gpio-mvebu.c val = BIT(pin); /* falling */ BIT 546 drivers/gpio/gpio-mvebu.c BIT(pin), val); BIT 577 drivers/gpio/gpio-mvebu.c if (!(cause & BIT(i))) BIT 588 drivers/gpio/gpio-mvebu.c polarity ^= BIT(i); BIT 868 drivers/gpio/gpio-mvebu.c msk = BIT(i); BIT 79 drivers/gpio/gpio-omap.c #define GPIO_MOD_CTRL_BIT BIT(0) BIT 82 drivers/gpio/gpio-omap.c #define LINE_USED(line, offset) (line & (BIT(offset))) BIT 110 drivers/gpio/gpio-omap.c BIT(gpio), is_input); BIT 119 drivers/gpio/gpio-omap.c u32 l = BIT(offset); BIT 137 drivers/gpio/gpio-omap.c BIT(offset), enable); BIT 194 drivers/gpio/gpio-omap.c l = BIT(offset); BIT 232 drivers/gpio/gpio-omap.c u32 gpio_bit = BIT(offset); BIT 274 drivers/gpio/gpio-omap.c u32 gpio_bit = BIT(gpio); BIT 327 drivers/gpio/gpio-omap.c writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg); BIT 344 drivers/gpio/gpio-omap.c bank->toggle_mask |= BIT(gpio); BIT 346 drivers/gpio/gpio-omap.c l |= BIT(gpio); BIT 348 drivers/gpio/gpio-omap.c l &= ~(BIT(gpio)); BIT 365 drivers/gpio/gpio-omap.c l |= BIT(gpio << 1); BIT 377 drivers/gpio/gpio-omap.c writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); BIT 410 drivers/gpio/gpio-omap.c return readl_relaxed(reg) & BIT(offset); BIT 419 drivers/gpio/gpio-omap.c bank->irq_usage |= BIT(offset); BIT 487 drivers/gpio/gpio-omap.c omap_clear_gpio_irqbank(bank, BIT(offset)); BIT 494 drivers/gpio/gpio-omap.c u32 mask = (BIT(bank->width)) - 1; BIT 508 drivers/gpio/gpio-omap.c u32 gpio_mask = BIT(offset); BIT 595 drivers/gpio/gpio-omap.c isr &= ~(BIT(bit)); BIT 605 drivers/gpio/gpio-omap.c if (bank->toggle_mask & (BIT(bit))) BIT 634 drivers/gpio/gpio-omap.c bank->irq_usage |= BIT(offset); BIT 649 drivers/gpio/gpio-omap.c bank->irq_usage &= ~(BIT(offset)); BIT 781 drivers/gpio/gpio-omap.c bank->mod_usage |= BIT(offset); BIT 793 drivers/gpio/gpio-omap.c bank->mod_usage &= ~(BIT(offset)); BIT 809 drivers/gpio/gpio-omap.c BIT(offset)); BIT 834 drivers/gpio/gpio-omap.c return (readl_relaxed(reg) & BIT(offset)) != 0; BIT 45 drivers/gpio/gpio-palmas.c if (val & BIT(offset)) BIT 55 drivers/gpio/gpio-palmas.c return !!(val & BIT(offset)); BIT 75 drivers/gpio/gpio-palmas.c ret = palmas_write(palmas, PALMAS_GPIO_BASE, reg, BIT(offset)); BIT 96 drivers/gpio/gpio-palmas.c BIT(offset), BIT(offset)); BIT 114 drivers/gpio/gpio-palmas.c ret = palmas_update_bits(palmas, PALMAS_GPIO_BASE, reg, BIT(offset), 0); BIT 33 drivers/gpio/gpio-pca953x.c #define REG_ADDR_EXT BIT(6) BIT 34 drivers/gpio/gpio-pca953x.c #define REG_ADDR_AI BIT(7) BIT 64 drivers/gpio/gpio-pca953x.c #define PCA_INT BIT(8) BIT 65 drivers/gpio/gpio-pca953x.c #define PCA_PCAL BIT(9) BIT 67 drivers/gpio/gpio-pca953x.c #define PCA953X_TYPE BIT(12) BIT 68 drivers/gpio/gpio-pca953x.c #define PCA957X_TYPE BIT(13) BIT 171 drivers/gpio/gpio-pca953x.c #define PCA953x_BANK_INPUT BIT(0) BIT 172 drivers/gpio/gpio-pca953x.c #define PCA953x_BANK_OUTPUT BIT(1) BIT 173 drivers/gpio/gpio-pca953x.c #define PCA953x_BANK_POLARITY BIT(2) BIT 174 drivers/gpio/gpio-pca953x.c #define PCA953x_BANK_CONFIG BIT(3) BIT 176 drivers/gpio/gpio-pca953x.c #define PCA957x_BANK_INPUT BIT(0) BIT 177 drivers/gpio/gpio-pca953x.c #define PCA957x_BANK_POLARITY BIT(1) BIT 178 drivers/gpio/gpio-pca953x.c #define PCA957x_BANK_BUSHOLD BIT(2) BIT 179 drivers/gpio/gpio-pca953x.c #define PCA957x_BANK_CONFIG BIT(4) BIT 180 drivers/gpio/gpio-pca953x.c #define PCA957x_BANK_OUTPUT BIT(5) BIT 182 drivers/gpio/gpio-pca953x.c #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) BIT 183 drivers/gpio/gpio-pca953x.c #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) BIT 184 drivers/gpio/gpio-pca953x.c #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) BIT 185 drivers/gpio/gpio-pca953x.c #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) BIT 186 drivers/gpio/gpio-pca953x.c #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) BIT 221 drivers/gpio/gpio-pca953x.c int offset = reg & (BIT(bank_shift) - 1); BIT 231 drivers/gpio/gpio-pca953x.c if (!(BIT(bank) & checkbank)) BIT 369 drivers/gpio/gpio-pca953x.c u8 bit = BIT(off % BANK_SZ); BIT 386 drivers/gpio/gpio-pca953x.c u8 bit = BIT(off % BANK_SZ); BIT 407 drivers/gpio/gpio-pca953x.c u8 bit = BIT(off % BANK_SZ); BIT 430 drivers/gpio/gpio-pca953x.c u8 bit = BIT(off % BANK_SZ); BIT 442 drivers/gpio/gpio-pca953x.c u8 bit = BIT(off % BANK_SZ); BIT 493 drivers/gpio/gpio-pca953x.c u8 bit = BIT(offset % BANK_SZ); BIT 569 drivers/gpio/gpio-pca953x.c chip->irq_mask[d->hwirq / BANK_SZ] &= ~BIT(d->hwirq % BANK_SZ); BIT 577 drivers/gpio/gpio-pca953x.c chip->irq_mask[d->hwirq / BANK_SZ] |= BIT(d->hwirq % BANK_SZ); BIT 644 drivers/gpio/gpio-pca953x.c u8 mask = BIT(d->hwirq % BANK_SZ); BIT 669 drivers/gpio/gpio-pca953x.c u8 mask = BIT(d->hwirq % BANK_SZ); BIT 419 drivers/gpio/gpio-pcf857x.c gpio->write(gpio->client, BIT(gpio->chip.ngpio) - 1); BIT 14 drivers/gpio/gpio-pch.c #define PCH_EDGE_RISING BIT(0) BIT 15 drivers/gpio/gpio-pch.c #define PCH_LEVEL_L BIT(1) BIT 16 drivers/gpio/gpio-pch.c #define PCH_LEVEL_H (BIT(0) | BIT(1)) BIT 17 drivers/gpio/gpio-pch.c #define PCH_EDGE_BOTH BIT(2) BIT 18 drivers/gpio/gpio-pch.c #define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2)) BIT 85 drivers/gpio/gpio-pci-idio-16.c unsigned long mask = BIT(offset); BIT 151 drivers/gpio/gpio-pci-idio-16.c unsigned int mask = BIT(offset); BIT 215 drivers/gpio/gpio-pci-idio-16.c const unsigned long mask = BIT(irqd_to_hwirq(data)); BIT 233 drivers/gpio/gpio-pci-idio-16.c const unsigned long mask = BIT(irqd_to_hwirq(data)); BIT 322 drivers/gpio/gpio-pci-idio-16.c err = pcim_iomap_regions(pdev, BIT(pci_bar_index), name); BIT 103 drivers/gpio/gpio-pcie-idio-24.c const unsigned long out_mode_mask = BIT(1); BIT 124 drivers/gpio/gpio-pcie-idio-24.c const unsigned long out_mode_mask = BIT(1); BIT 146 drivers/gpio/gpio-pcie-idio-24.c const unsigned long out_mode_mask = BIT(1); BIT 166 drivers/gpio/gpio-pcie-idio-24.c const unsigned long offset_mask = BIT(offset % 8); BIT 167 drivers/gpio/gpio-pcie-idio-24.c const unsigned long out_mode_mask = BIT(1); BIT 214 drivers/gpio/gpio-pcie-idio-24.c const unsigned long out_mode_mask = BIT(1); BIT 256 drivers/gpio/gpio-pcie-idio-24.c const unsigned long out_mode_mask = BIT(1); BIT 258 drivers/gpio/gpio-pcie-idio-24.c const unsigned int mask = BIT(offset % 8); BIT 308 drivers/gpio/gpio-pcie-idio-24.c const unsigned long out_mode_mask = BIT(1); BIT 368 drivers/gpio/gpio-pcie-idio-24.c idio24gpio->irq_mask &= BIT(bit_offset); BIT 375 drivers/gpio/gpio-pcie-idio-24.c cos_enable_state &= ~BIT(bank_offset); BIT 377 drivers/gpio/gpio-pcie-idio-24.c cos_enable_state &= ~BIT(bank_offset + 4); BIT 398 drivers/gpio/gpio-pcie-idio-24.c idio24gpio->irq_mask |= BIT(bit_offset); BIT 404 drivers/gpio/gpio-pcie-idio-24.c cos_enable_state |= BIT(bank_offset); BIT 406 drivers/gpio/gpio-pcie-idio-24.c cos_enable_state |= BIT(bank_offset + 4); BIT 497 drivers/gpio/gpio-pcie-idio-24.c err = pcim_iomap_regions(pdev, BIT(pci_bar_index), name); BIT 66 drivers/gpio/gpio-pl061.c return !(readb(pl061->base + GPIODIR) & BIT(offset)); BIT 77 drivers/gpio/gpio-pl061.c gpiodir &= ~(BIT(offset)); BIT 92 drivers/gpio/gpio-pl061.c writeb(!!value << offset, pl061->base + (BIT(offset + 2))); BIT 94 drivers/gpio/gpio-pl061.c gpiodir |= BIT(offset); BIT 101 drivers/gpio/gpio-pl061.c writeb(!!value << offset, pl061->base + (BIT(offset + 2))); BIT 111 drivers/gpio/gpio-pl061.c return !!readb(pl061->base + (BIT(offset + 2))); BIT 118 drivers/gpio/gpio-pl061.c writeb(!!value << offset, pl061->base + (BIT(offset + 2))); BIT 128 drivers/gpio/gpio-pl061.c u8 bit = BIT(offset); BIT 233 drivers/gpio/gpio-pl061.c u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); BIT 246 drivers/gpio/gpio-pl061.c u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); BIT 267 drivers/gpio/gpio-pl061.c u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); BIT 368 drivers/gpio/gpio-pl061.c if (pl061->csave_regs.gpio_dir & (BIT(offset))) BIT 382 drivers/gpio/gpio-pl061.c if (pl061->csave_regs.gpio_dir & (BIT(offset))) BIT 385 drivers/gpio/gpio-pl061.c (BIT(offset))); BIT 74 drivers/gpio/gpio-pmic-eic-sprd.c BIT(shift), val << shift); BIT 88 drivers/gpio/gpio-pmic-eic-sprd.c return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset))); BIT 35 drivers/gpio/gpio-rc5t583.c return !!(val & BIT(offset)); BIT 43 drivers/gpio/gpio-rc5t583.c rc5t583_set_bits(parent, RC5T583_GPIO_IOOUT, BIT(offset)); BIT 45 drivers/gpio/gpio-rc5t583.c rc5t583_clear_bits(parent, RC5T583_GPIO_IOOUT, BIT(offset)); BIT 54 drivers/gpio/gpio-rc5t583.c ret = rc5t583_clear_bits(parent, RC5T583_GPIO_IOSEL, BIT(offset)); BIT 59 drivers/gpio/gpio-rc5t583.c return rc5t583_clear_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset)); BIT 70 drivers/gpio/gpio-rc5t583.c ret = rc5t583_set_bits(parent, RC5T583_GPIO_IOSEL, BIT(offset)); BIT 75 drivers/gpio/gpio-rc5t583.c return rc5t583_clear_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset)); BIT 93 drivers/gpio/gpio-rc5t583.c rc5t583_set_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset)); BIT 81 drivers/gpio/gpio-rcar.c tmp |= BIT(bit); BIT 83 drivers/gpio/gpio-rcar.c tmp &= ~BIT(bit); BIT 93 drivers/gpio/gpio-rcar.c gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); BIT 101 drivers/gpio/gpio-rcar.c gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); BIT 134 drivers/gpio/gpio-rcar.c gpio_rcar_write(p, INTCLR, BIT(hwirq)); BIT 208 drivers/gpio/gpio-rcar.c gpio_rcar_write(p, INTCLR, BIT(offset)); BIT 282 drivers/gpio/gpio-rcar.c return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset)); BIT 293 drivers/gpio/gpio-rcar.c u32 bit = BIT(offset); BIT 566 drivers/gpio/gpio-rcar.c mask = BIT(offset); BIT 29 drivers/gpio/gpio-reg.c return r->direction & BIT(offset) ? 1 : 0; BIT 37 drivers/gpio/gpio-reg.c if (r->direction & BIT(offset)) BIT 48 drivers/gpio/gpio-reg.c return r->direction & BIT(offset) ? 0 : -ENOTSUPP; BIT 55 drivers/gpio/gpio-reg.c u32 val, mask = BIT(offset); BIT 71 drivers/gpio/gpio-reg.c u32 val, mask = BIT(offset); BIT 42 drivers/gpio/gpio-sa1100.c BIT(offset); BIT 49 drivers/gpio/gpio-sa1100.c writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); BIT 56 drivers/gpio/gpio-sa1100.c return !(readl_relaxed(gpdr) & BIT(offset)); BIT 65 drivers/gpio/gpio-sa1100.c writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr); BIT 78 drivers/gpio/gpio-sa1100.c writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr); BIT 125 drivers/gpio/gpio-sa1100.c unsigned int mask = BIT(d->hwirq); BIT 154 drivers/gpio/gpio-sa1100.c writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); BIT 160 drivers/gpio/gpio-sa1100.c unsigned int mask = BIT(d->hwirq); BIT 170 drivers/gpio/gpio-sa1100.c unsigned int mask = BIT(d->hwirq); BIT 183 drivers/gpio/gpio-sa1100.c sgc->irqwake |= BIT(d->hwirq); BIT 185 drivers/gpio/gpio-sa1100.c sgc->irqwake &= ~BIT(d->hwirq); BIT 37 drivers/gpio/gpio-sama5d2-piobu.c #define PIOBU_DIRECTION BIT(8) BIT 38 drivers/gpio/gpio-sama5d2-piobu.c #define PIOBU_OUT BIT(8) BIT 41 drivers/gpio/gpio-sama5d2-piobu.c #define PIOBU_SOD BIT(9) BIT 42 drivers/gpio/gpio-sama5d2-piobu.c #define PIOBU_PDS BIT(10) BIT 44 drivers/gpio/gpio-sama5d2-piobu.c #define PIOBU_HIGH BIT(9) BIT 63 drivers/gpio/gpio-sama5d2-piobu.c unsigned int mask = BIT(PIOBU_DET_OFFSET + pin); BIT 57 drivers/gpio/gpio-sch.c reg_val = !!(inb(sch->iobase + offset) & BIT(bit)); BIT 74 drivers/gpio/gpio-sch.c outb(reg_val | BIT(bit), sch->iobase + offset); BIT 76 drivers/gpio/gpio-sch.c outb((reg_val & ~BIT(bit)), sch->iobase + offset); BIT 22 drivers/gpio/gpio-sch311x.c #define SCH311X_GPIO_CONF_DIR BIT(0) BIT 23 drivers/gpio/gpio-sch311x.c #define SCH311X_GPIO_CONF_INVERT BIT(1) BIT 24 drivers/gpio/gpio-sch311x.c #define SCH311X_GPIO_CONF_OPEN_DRAIN BIT(7) BIT 167 drivers/gpio/gpio-sch311x.c return !!(data & BIT(offset)); BIT 175 drivers/gpio/gpio-sch311x.c data |= BIT(offset); BIT 177 drivers/gpio/gpio-sch311x.c data &= ~BIT(offset); BIT 61 drivers/gpio/gpio-sodaville.c reg &= ~BIT(4 * (d->hwirq % 8)); BIT 65 drivers/gpio/gpio-sodaville.c reg |= BIT(4 * (d->hwirq % 8)); BIT 61 drivers/gpio/gpio-sprd.c tmp |= BIT(SPRD_GPIO_BIT(offset)); BIT 63 drivers/gpio/gpio-sprd.c tmp &= ~BIT(SPRD_GPIO_BIT(offset)); BIT 75 drivers/gpio/gpio-sprd.c return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset))); BIT 57 drivers/gpio/gpio-sta2x11.c u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); BIT 69 drivers/gpio/gpio-sta2x11.c u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); BIT 79 drivers/gpio/gpio-sta2x11.c u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); BIT 94 drivers/gpio/gpio-sta2x11.c u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); BIT 148 drivers/gpio/gpio-sta2x11.c u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); BIT 216 drivers/gpio/gpio-sta2x11.c u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); BIT 239 drivers/gpio/gpio-sta2x11.c u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); BIT 46 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); BIT 62 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); BIT 80 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); BIT 96 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); BIT 109 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); BIT 119 drivers/gpio/gpio-stmpe.c if (stmpe_gpio->norequest_mask & BIT(offset)) BIT 122 drivers/gpio/gpio-stmpe.c return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO); BIT 143 drivers/gpio/gpio-stmpe.c int mask = BIT(offset % 8); BIT 231 drivers/gpio/gpio-stmpe.c int mask = BIT(offset % 8); BIT 242 drivers/gpio/gpio-stmpe.c int mask = BIT(offset % 8); BIT 257 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); BIT 412 drivers/gpio/gpio-stmpe.c stat &= ~BIT(bit); BIT 444 drivers/gpio/gpio-stmpe.c if (stmpe_gpio->norequest_mask & BIT(i)) BIT 37 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_CON_SWU BIT(31) BIT 41 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_4HZ BIT(23) BIT 42 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_8HZ BIT(24) BIT 43 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_10HZ (BIT(24) | BIT(23)) BIT 47 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_UPD_FPI BIT(31) BIT 48 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_UPD_MASK (BIT(31) | BIT(30)) BIT 60 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_GROUP0 BIT(0) BIT 61 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_GROUP1 BIT(1) BIT 62 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_GROUP2 BIT(2) BIT 66 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_FALLING BIT(26) BIT 67 drivers/gpio/gpio-stp-xway.c #define XWAY_STP_EDGE_MASK BIT(26) BIT 97 drivers/gpio/gpio-stp-xway.c return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio)); BIT 113 drivers/gpio/gpio-stp-xway.c chip->shadow |= BIT(gpio); BIT 115 drivers/gpio/gpio-stp-xway.c chip->shadow &= ~BIT(gpio); BIT 146 drivers/gpio/gpio-stp-xway.c if ((gpio < 8) && (chip->reserved & BIT(gpio))) { BIT 17 drivers/gpio/gpio-syscon.c #define GPIO_SYSCON_FEAT_IN BIT(0) BIT 18 drivers/gpio/gpio-syscon.c #define GPIO_SYSCON_FEAT_OUT BIT(1) BIT 19 drivers/gpio/gpio-syscon.c #define GPIO_SYSCON_FEAT_DIR BIT(2) BIT 71 drivers/gpio/gpio-syscon.c return !!(val & BIT(offs % SYSCON_REG_BITS)); BIT 83 drivers/gpio/gpio-syscon.c BIT(offs % SYSCON_REG_BITS), BIT 84 drivers/gpio/gpio-syscon.c val ? BIT(offs % SYSCON_REG_BITS) : 0); BIT 99 drivers/gpio/gpio-syscon.c BIT(offs % SYSCON_REG_BITS), 0); BIT 117 drivers/gpio/gpio-syscon.c BIT(offs % SYSCON_REG_BITS), BIT 118 drivers/gpio/gpio-syscon.c BIT(offs % SYSCON_REG_BITS)); BIT 145 drivers/gpio/gpio-syscon.c data = (val ? BIT(bit) : 0) | BIT(bit + 16); BIT 161 drivers/gpio/gpio-syscon.c #define KEYSTONE_LOCK_BIT BIT(0) BIT 177 drivers/gpio/gpio-syscon.c BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT, BIT 178 drivers/gpio/gpio-syscon.c BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT); BIT 220 drivers/gpio/gpio-tb10x.c BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0); BIT 42 drivers/gpio/gpio-tc3589x.c u8 mask = BIT(offset % 8); BIT 58 drivers/gpio/gpio-tc3589x.c u8 data[] = {val ? BIT(pos) : 0, BIT(pos)}; BIT 73 drivers/gpio/gpio-tc3589x.c return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos)); BIT 84 drivers/gpio/gpio-tc3589x.c return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0); BIT 100 drivers/gpio/gpio-tc3589x.c return !(ret & BIT(pos)); BIT 121 drivers/gpio/gpio-tc3589x.c ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0); BIT 125 drivers/gpio/gpio-tc3589x.c return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos)); BIT 128 drivers/gpio/gpio-tc3589x.c ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos)); BIT 132 drivers/gpio/gpio-tc3589x.c return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos)); BIT 135 drivers/gpio/gpio-tc3589x.c return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0); BIT 160 drivers/gpio/gpio-tc3589x.c int mask = BIT(offset % 8); BIT 225 drivers/gpio/gpio-tc3589x.c int mask = BIT(offset % 8); BIT 236 drivers/gpio/gpio-tc3589x.c int mask = BIT(offset % 8); BIT 158 drivers/gpio/gpio-tegra.c unsigned int bval = BIT(GPIO_BIT(offset)); BIT 209 drivers/gpio/gpio-tegra.c u32 pin_mask = BIT(GPIO_BIT(offset)); BIT 501 drivers/gpio/gpio-tegra.c mask = BIT(bit); BIT 19 drivers/gpio/gpio-tegra186.c #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) BIT 20 drivers/gpio/gpio-tegra186.c #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) BIT 26 drivers/gpio/gpio-tegra186.c #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) BIT 27 drivers/gpio/gpio-tegra186.c #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) BIT 33 drivers/gpio/gpio-tegra186.c #define TEGRA186_GPIO_INPUT_HIGH BIT(0) BIT 36 drivers/gpio/gpio-tegra186.c #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) BIT 39 drivers/gpio/gpio-tegra186.c #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) BIT 184 drivers/gpio/gpio-tegra186.c return value & BIT(0); BIT 26 drivers/gpio/gpio-thunderx.c #define GPIO_BIT_CFG_TX_OE BIT(0) BIT 27 drivers/gpio/gpio-thunderx.c #define GPIO_BIT_CFG_PIN_XOR BIT(1) BIT 28 drivers/gpio/gpio-thunderx.c #define GPIO_BIT_CFG_INT_EN BIT(2) BIT 29 drivers/gpio/gpio-thunderx.c #define GPIO_BIT_CFG_INT_TYPE BIT(3) BIT 33 drivers/gpio/gpio-thunderx.c #define GPIO_BIT_CFG_TX_OD BIT(12) BIT 36 drivers/gpio/gpio-thunderx.c #define GPIO_INTR_INTR BIT(0) BIT 37 drivers/gpio/gpio-thunderx.c #define GPIO_INTR_INTR_W1S BIT(1) BIT 38 drivers/gpio/gpio-thunderx.c #define GPIO_INTR_ENA_W1C BIT(2) BIT 39 drivers/gpio/gpio-thunderx.c #define GPIO_INTR_ENA_W1S BIT(3) BIT 81 drivers/gpio/gpio-tpic2810.c tpic2810_set_mask_bits(chip, BIT(offset), value ? BIT(offset) : 0); BIT 41 drivers/gpio/gpio-tps65086.c BIT(4 + offset), value ? BIT(4 + offset) : 0); BIT 55 drivers/gpio/gpio-tps65086.c return val & BIT(4 + offset); BIT 64 drivers/gpio/gpio-tps65086.c BIT(4 + offset), value ? BIT(4 + offset) : 0); BIT 47 drivers/gpio/gpio-tps68470.c return !!(val & BIT(offset)); BIT 85 drivers/gpio/gpio-tps68470.c regmap_update_bits(regmap, reg, BIT(offset), value ? BIT(offset) : 0); BIT 30 drivers/gpio/gpio-tqmx86.c #define TQMX86_GPII_FALLING BIT(0) BIT 31 drivers/gpio/gpio-tqmx86.c #define TQMX86_GPII_RISING BIT(1) BIT 32 drivers/gpio/gpio-tqmx86.c #define TQMX86_GPII_MASK (BIT(0) | BIT(1)) BIT 59 drivers/gpio/gpio-tqmx86.c return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset)); BIT 72 drivers/gpio/gpio-tqmx86.c val |= BIT(offset); BIT 74 drivers/gpio/gpio-tqmx86.c val &= ~BIT(offset); BIT 83 drivers/gpio/gpio-tqmx86.c if (BIT(offset) & TQMX86_DIR_INPUT_MASK) BIT 94 drivers/gpio/gpio-tqmx86.c if (BIT(offset) & TQMX86_DIR_INPUT_MASK) BIT 104 drivers/gpio/gpio-tqmx86.c return !!(TQMX86_DIR_INPUT_MASK & BIT(offset)); BIT 63 drivers/gpio/gpio-ts5500.c .value_mask = BIT(vbit), \ BIT 65 drivers/gpio/gpio-ts5500.c .control_mask = BIT(cbit), \ BIT 71 drivers/gpio/gpio-ts5500.c .value_mask = BIT(bit), \ BIT 78 drivers/gpio/gpio-ts5500.c .value_mask = BIT(bit), \ BIT 86 drivers/gpio/gpio-ts5500.c .value_mask = BIT(bit), \ BIT 285 drivers/gpio/gpio-ts5500.c ts5500_set_mask(BIT(7), 0x7a); /* DIO1_13 on IRQ7 */ BIT 287 drivers/gpio/gpio-ts5500.c ts5500_set_mask(BIT(7), 0x7d); /* DIO2_13 on IRQ6 */ BIT 289 drivers/gpio/gpio-ts5500.c ts5500_set_mask(BIT(6), 0x7d); /* LCD_RS on IRQ1 */ BIT 303 drivers/gpio/gpio-ts5500.c ts5500_clear_mask(BIT(7), 0x7a); /* DIO1_13 on IRQ7 */ BIT 305 drivers/gpio/gpio-ts5500.c ts5500_clear_mask(BIT(7), 0x7d); /* DIO2_13 on IRQ6 */ BIT 307 drivers/gpio/gpio-ts5500.c ts5500_clear_mask(BIT(6), 0x7d); /* LCD_RS on IRQ1 */ BIT 398 drivers/gpio/gpio-ts5500.c ts5500_clear_mask(BIT(4), 0x7d); BIT 46 drivers/gpio/gpio-twl4030.c #define MASK_GPIO_CTRL_GPIO0CD1 BIT(0) BIT 47 drivers/gpio/gpio-twl4030.c #define MASK_GPIO_CTRL_GPIO1CD2 BIT(1) BIT 48 drivers/gpio/gpio-twl4030.c #define MASK_GPIO_CTRL_GPIO_ON BIT(2) BIT 88 drivers/gpio/gpio-twl4030.c #define LEDEN_LEDAON BIT(0) BIT 89 drivers/gpio/gpio-twl4030.c #define LEDEN_LEDBON BIT(1) BIT 90 drivers/gpio/gpio-twl4030.c #define LEDEN_LEDAEXT BIT(2) BIT 91 drivers/gpio/gpio-twl4030.c #define LEDEN_LEDBEXT BIT(3) BIT 92 drivers/gpio/gpio-twl4030.c #define LEDEN_LEDAPWM BIT(4) BIT 93 drivers/gpio/gpio-twl4030.c #define LEDEN_LEDBPWM BIT(5) BIT 94 drivers/gpio/gpio-twl4030.c #define LEDEN_PWM_LENGTHA BIT(6) BIT 95 drivers/gpio/gpio-twl4030.c #define LEDEN_PWM_LENGTHB BIT(7) BIT 97 drivers/gpio/gpio-twl4030.c #define PWMxON_LENGTH BIT(7) BIT 140 drivers/gpio/gpio-twl4030.c u8 d_msk = BIT(gpio & 0x7); BIT 160 drivers/gpio/gpio-twl4030.c u8 d_msk = BIT(gpio & 0x7); BIT 177 drivers/gpio/gpio-twl4030.c u8 d_msk = BIT(gpio & 0x7); BIT 267 drivers/gpio/gpio-twl4030.c priv->usage_count |= BIT(offset); BIT 283 drivers/gpio/gpio-twl4030.c priv->usage_count &= ~BIT(offset); BIT 305 drivers/gpio/gpio-twl4030.c priv->direction &= ~BIT(offset); BIT 319 drivers/gpio/gpio-twl4030.c if (!(priv->usage_count & BIT(offset))) { BIT 324 drivers/gpio/gpio-twl4030.c if (priv->direction & BIT(offset)) BIT 325 drivers/gpio/gpio-twl4030.c status = priv->out_state & BIT(offset); BIT 346 drivers/gpio/gpio-twl4030.c priv->out_state |= BIT(offset); BIT 348 drivers/gpio/gpio-twl4030.c priv->out_state &= ~BIT(offset); BIT 371 drivers/gpio/gpio-twl4030.c priv->direction |= BIT(offset); BIT 32 drivers/gpio/gpio-twl6040.c return !!(ret & BIT(offset)); BIT 59 drivers/gpio/gpio-twl6040.c gpoctl = ret | BIT(offset); BIT 61 drivers/gpio/gpio-twl6040.c gpoctl = ret & ~BIT(offset); BIT 59 drivers/gpio/gpio-uniphier.c *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK); BIT 187 drivers/gpio/gpio-uniphier.c u32 mask = BIT(data->hwirq); BIT 197 drivers/gpio/gpio-uniphier.c u32 mask = BIT(data->hwirq); BIT 207 drivers/gpio/gpio-uniphier.c u32 mask = BIT(data->hwirq); BIT 87 drivers/gpio/gpio-vf610.c unsigned long mask = BIT(gpio); BIT 96 drivers/gpio/gpio-vf610.c return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio)); BIT 102 drivers/gpio/gpio-vf610.c unsigned long mask = BIT(gpio); BIT 111 drivers/gpio/gpio-vf610.c unsigned long mask = BIT(gpio); BIT 127 drivers/gpio/gpio-vf610.c unsigned long mask = BIT(gpio); BIT 150 drivers/gpio/gpio-vf610.c vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); BIT 164 drivers/gpio/gpio-vf610.c vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); BIT 48 drivers/gpio/gpio-wcove.c #define UPDATE_IRQ_TYPE BIT(0) BIT 49 drivers/gpio/gpio-wcove.c #define UPDATE_IRQ_MASK BIT(1) BIT 121 drivers/gpio/gpio-wcove.c mask = BIT(gpio % GROUP0_NR_IRQS); BIT 124 drivers/gpio/gpio-wcove.c mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS); BIT 342 drivers/gpio/gpio-wcove.c mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) : BIT 343 drivers/gpio/gpio-wcove.c BIT(gpio); BIT 389 drivers/gpio/gpio-wcove.c irq_mask & BIT(offset) ? "mask " : "unmask", BIT 390 drivers/gpio/gpio-wcove.c irq_status & BIT(offset) ? "pending" : " "); BIT 187 drivers/gpio/gpio-winbond.c val |= BIT(bit); BIT 196 drivers/gpio/gpio-winbond.c val &= ~BIT(bit); BIT 202 drivers/gpio/gpio-winbond.c return winbond_sio_reg_read(base, reg) & BIT(bit); BIT 554 drivers/gpio/gpio-winbond.c if (params.ppgpios & BIT(idx)) BIT 557 drivers/gpio/gpio-winbond.c else if (params.odgpios & BIT(idx)) BIT 676 drivers/gpio/gpio-winbond.c if (params.gpios & BIT(5)) BIT 57 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); BIT 66 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); BIT 85 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); BIT 106 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); BIT 174 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); BIT 240 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); BIT 265 drivers/gpio/gpio-ws16c48.c const unsigned long mask = BIT(offset); BIT 289 drivers/gpio/gpio-ws16c48.c const unsigned long mask = BIT(offset); BIT 313 drivers/gpio/gpio-ws16c48.c const unsigned long mask = BIT(offset); BIT 45 drivers/gpio/gpio-xgene.c return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); BIT 59 drivers/gpio/gpio-xgene.c setval |= BIT(bit_offset); BIT 61 drivers/gpio/gpio-xgene.c setval &= ~BIT(bit_offset); BIT 83 drivers/gpio/gpio-xgene.c return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); BIT 98 drivers/gpio/gpio-xgene.c dirval |= BIT(bit_offset); BIT 119 drivers/gpio/gpio-xgene.c dirval &= ~BIT(bit_offset); BIT 94 drivers/gpio/gpio-xilinx.c return !!(val & BIT(xgpio_offset(chip, gpio))); BIT 117 drivers/gpio/gpio-xilinx.c chip->gpio_state[index] |= BIT(offset); BIT 119 drivers/gpio/gpio-xilinx.c chip->gpio_state[index] &= ~BIT(offset); BIT 162 drivers/gpio/gpio-xilinx.c chip->gpio_state[index] |= BIT(offset); BIT 164 drivers/gpio/gpio-xilinx.c chip->gpio_state[index] &= ~BIT(offset); BIT 193 drivers/gpio/gpio-xilinx.c chip->gpio_dir[index] |= BIT(offset); BIT 225 drivers/gpio/gpio-xilinx.c chip->gpio_state[index] |= BIT(offset); BIT 227 drivers/gpio/gpio-xilinx.c chip->gpio_state[index] &= ~BIT(offset); BIT 232 drivers/gpio/gpio-xilinx.c chip->gpio_dir[index] &= ~BIT(offset); BIT 103 drivers/gpio/gpio-xlp.c return !!(readl(addr + regset) & BIT(pos)); BIT 115 drivers/gpio/gpio-xlp.c value |= BIT(pos); BIT 117 drivers/gpio/gpio-xlp.c value &= ~BIT(pos); BIT 218 drivers/gpio/gpio-xlp.c if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ)) BIT 56 drivers/gpio/gpio-xra1403.c BIT(offset % 8), BIT(offset % 8)); BIT 66 drivers/gpio/gpio-xra1403.c BIT(offset % 8), 0); BIT 71 drivers/gpio/gpio-xra1403.c BIT(offset % 8), value ? BIT(offset % 8) : 0); BIT 86 drivers/gpio/gpio-xra1403.c return !!(val & BIT(offset % 8)); BIT 99 drivers/gpio/gpio-xra1403.c return !!(val & BIT(offset % 8)); BIT 108 drivers/gpio/gpio-xra1403.c BIT(offset % 8), value ? BIT(offset % 8) : 0); BIT 144 drivers/gpio/gpio-xra1403.c (gcr & BIT(i)) ? "in" : "out", BIT 145 drivers/gpio/gpio-xra1403.c (gsr & BIT(i)) ? "hi" : "lo"); BIT 48 drivers/gpio/gpio-xtensa.c xtensa_set_sr(*cpenable | BIT(XCHAL_CP_ID_XTIOP), cpenable); BIT 86 drivers/gpio/gpio-xtensa.c return !!(impwire & BIT(offset)); BIT 109 drivers/gpio/gpio-xtensa.c return !!(expstate & BIT(offset)); BIT 116 drivers/gpio/gpio-xtensa.c u32 mask = BIT(offset); BIT 117 drivers/gpio/gpio-xtensa.c u32 val = value ? BIT(offset) : 0; BIT 82 drivers/gpio/gpio-zevio.c if (dir & BIT(ZEVIO_GPIO_BIT(pin))) BIT 99 drivers/gpio/gpio-zevio.c val |= BIT(ZEVIO_GPIO_BIT(pin)); BIT 101 drivers/gpio/gpio-zevio.c val &= ~BIT(ZEVIO_GPIO_BIT(pin)); BIT 115 drivers/gpio/gpio-zevio.c val |= BIT(ZEVIO_GPIO_BIT(pin)); BIT 132 drivers/gpio/gpio-zevio.c val |= BIT(ZEVIO_GPIO_BIT(pin)); BIT 134 drivers/gpio/gpio-zevio.c val &= ~BIT(ZEVIO_GPIO_BIT(pin)); BIT 138 drivers/gpio/gpio-zevio.c val &= ~BIT(ZEVIO_GPIO_BIT(pin)); BIT 58 drivers/gpio/gpio-zx.c gpiodir &= ~BIT(offset); BIT 77 drivers/gpio/gpio-zx.c gpiodir |= BIT(offset); BIT 81 drivers/gpio/gpio-zx.c writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1); BIT 83 drivers/gpio/gpio-zx.c writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0); BIT 93 drivers/gpio/gpio-zx.c return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset)); BIT 101 drivers/gpio/gpio-zx.c writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1); BIT 103 drivers/gpio/gpio-zx.c writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0); BIT 113 drivers/gpio/gpio-zx.c u16 bit = BIT(offset); BIT 181 drivers/gpio/gpio-zx.c u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR); BIT 196 drivers/gpio/gpio-zx.c u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR); BIT 96 drivers/gpio/gpio-zynq.c #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0) BIT 97 drivers/gpio/gpio-zynq.c #define GPIO_QUIRK_DATA_RO_BUG BIT(1) BIT 314 drivers/gpio/gpio-zynq.c reg &= ~BIT(bank_pin_num); BIT 343 drivers/gpio/gpio-zynq.c reg |= BIT(bank_pin_num); BIT 348 drivers/gpio/gpio-zynq.c reg |= BIT(bank_pin_num); BIT 375 drivers/gpio/gpio-zynq.c return !(reg & BIT(bank_pin_num)); BIT 394 drivers/gpio/gpio-zynq.c writel_relaxed(BIT(bank_pin_num), BIT 415 drivers/gpio/gpio-zynq.c writel_relaxed(BIT(bank_pin_num), BIT 435 drivers/gpio/gpio-zynq.c writel_relaxed(BIT(bank_pin_num), BIT 500 drivers/gpio/gpio-zynq.c int_type |= BIT(bank_pin_num); BIT 501 drivers/gpio/gpio-zynq.c int_pol |= BIT(bank_pin_num); BIT 502 drivers/gpio/gpio-zynq.c int_any &= ~BIT(bank_pin_num); BIT 505 drivers/gpio/gpio-zynq.c int_type |= BIT(bank_pin_num); BIT 506 drivers/gpio/gpio-zynq.c int_pol &= ~BIT(bank_pin_num); BIT 507 drivers/gpio/gpio-zynq.c int_any &= ~BIT(bank_pin_num); BIT 510 drivers/gpio/gpio-zynq.c int_type |= BIT(bank_pin_num); BIT 511 drivers/gpio/gpio-zynq.c int_any |= BIT(bank_pin_num); BIT 514 drivers/gpio/gpio-zynq.c int_type &= ~BIT(bank_pin_num); BIT 515 drivers/gpio/gpio-zynq.c int_pol |= BIT(bank_pin_num); BIT 518 drivers/gpio/gpio-zynq.c int_type &= ~BIT(bank_pin_num); BIT 519 drivers/gpio/gpio-zynq.c int_pol &= ~BIT(bank_pin_num); BIT 15 drivers/gpio/gpiolib-sysfs.c #define GPIO_IRQF_TRIGGER_FALLING BIT(0) BIT 16 drivers/gpio/gpiolib-sysfs.c #define GPIO_IRQF_TRIGGER_RISING BIT(1) BIT 26 drivers/gpio/sgpio-aspeed.c #define ASPEED_SGPIO_ENABLE BIT(0) BIT 116 drivers/gpio/sgpio-aspeed.c #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) BIT 391 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c return con->hw_supported & BIT(head->block); BIT 399 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c return con->features & BIT(head->block); BIT 432 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c con->features |= BIT(head->block); BIT 435 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c con->features &= ~BIT(head->block); BIT 1355 drivers/gpu/drm/amd/amdkfd/kfd_topology.c (((ctx->features & BIT(AMDGPU_RAS_BLOCK__SDMA)) != 0) || BIT 1356 drivers/gpu/drm/amd/amdkfd/kfd_topology.c ((ctx->features & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0)) ? BIT 1358 drivers/gpu/drm/amd/amdkfd/kfd_topology.c dev->node_props.capability |= ((ctx->features & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ? BIT 4753 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | BIT 4754 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c BIT(DRM_MODE_BLEND_PREMULTI); BIT 4765 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c BIT(DRM_COLOR_YCBCR_BT601) | BIT 4766 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c BIT(DRM_COLOR_YCBCR_BT709), BIT 4767 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT 4768 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c BIT(DRM_COLOR_YCBCR_FULL_RANGE), BIT 13 drivers/gpu/drm/arm/display/include/malidp_utils.h #define has_bit(nr, mask) (BIT(nr) & (mask)) BIT 67 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c valid_inputs |= BIT(comp_id); BIT 522 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c if (state->active_inputs & BIT(index)) { BIT 1010 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c improc->supported_color_depths = BIT(8) | BIT(10); BIT 1129 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c 1, BIT(KOMEDA_COMPONENT_IPS0 + pipe_id), BIT 441 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c #define LYT_NM BIT(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16) BIT 442 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c #define LYT_WB BIT(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8) BIT 45 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BLK_CTRL_EN BIT(0) BIT 55 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define AD_AEN BIT(0) BIT 56 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define AD_YT BIT(1) BIT 57 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define AD_BS BIT(2) BIT 58 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define AD_WB BIT(3) BIT 59 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define AD_TH BIT(4) BIT 72 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GCU_CONTROL_SRST BIT(16) BIT 83 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_GCU BIT(0) BIT 84 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_LPU0 BIT(8) BIT 85 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_LPU1 BIT(9) BIT 86 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_ATU0 BIT(10) BIT 87 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_ATU1 BIT(11) BIT 88 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_ATU2 BIT(12) BIT 89 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_ATU3 BIT(13) BIT 90 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_CU0 BIT(16) BIT 91 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_CU1 BIT(17) BIT 92 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_DOU0 BIT(24) BIT 93 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GLB_IRQ_STATUS_DOU1 BIT(25) BIT 113 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GCU_IRQ_CVAL0 BIT(0) BIT 114 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GCU_IRQ_CVAL1 BIT(1) BIT 115 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GCU_IRQ_MODE BIT(4) BIT 116 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GCU_IRQ_ERR BIT(11) BIT 120 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GCU_STATUS_MERR BIT(4) BIT 121 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GCU_STATUS_TCS0 BIT(8) BIT 122 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GCU_STATUS_TCS1 BIT(9) BIT 123 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GCU_STATUS_ACTIVE BIT(31) BIT 126 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define GCU_CONFIG_CVAL BIT(0) BIT 129 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define PERIPH_MAX_LINE_SIZE BIT(0) BIT 130 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define PERIPH_NUM_RICH_LAYERS BIT(4) BIT 131 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define PERIPH_SPLIT_EN BIT(8) BIT 132 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define PERIPH_TBU_EN BIT(12) BIT 133 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define PERIPH_AFBC_DMA_EN BIT(16) BIT 153 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define RAXI_BEN_MASK BIT(15) BIT 156 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define xAXI_ORD_MASK BIT(31) BIT 164 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_IRQ_IBSY BIT(10) BIT 165 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_IRQ_ERR BIT(11) BIT 166 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_IRQ_EOW BIT(12) BIT 167 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_IRQ_PL0 BIT(13) BIT 171 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_STATUS_AXIE BIT(4) BIT 172 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_STATUS_AXIRP BIT(5) BIT 173 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_STATUS_AXIWP BIT(6) BIT 174 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_STATUS_ACE0 BIT(16) BIT 175 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_STATUS_ACE1 BIT(17) BIT 176 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_STATUS_ACE2 BIT(18) BIT 177 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_STATUS_ACE3 BIT(19) BIT 178 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_STATUS_ACTIVE BIT(31) BIT 191 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_TBU_STATUS_TCF BIT(1) BIT 192 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_TBU_STATUS_TTNG BIT(2) BIT 193 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_TBU_STATUS_TITR BIT(8) BIT 194 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_TBU_STATUS_TEMR BIT(16) BIT 195 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_TBU_STATUS_TTF BIT(31) BIT 198 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LPU_TBU_CTRL_TLBPEN BIT(16) BIT 201 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CBU_INPUT_CTRL_EN BIT(0) BIT 229 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CU_CTRL_COPROC BIT(0) BIT 232 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CU_IRQ_OVR BIT(9) BIT 233 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CU_IRQ_ERR BIT(11) BIT 236 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CU_STATUS_CPE BIT(0) BIT 237 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CU_STATUS_ZME BIT(1) BIT 238 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CU_STATUS_CFGE BIT(2) BIT 239 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CU_STATUS_ACTIVE BIT(31) BIT 242 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CU_INPUT_CTRL_EN BIT(0) BIT 243 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CU_INPUT_CTRL_PAD BIT(1) BIT 244 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define CU_INPUT_CTRL_PMUL BIT(2) BIT 250 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define DOU_IRQ_UND BIT(8) BIT 251 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define DOU_IRQ_ERR BIT(11) BIT 252 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define DOU_IRQ_PL0 BIT(13) BIT 253 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define DOU_IRQ_PL1 BIT(14) BIT 256 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define DOU_STATUS_DRIFTTO BIT(0) BIT 257 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define DOU_STATUS_FRAMETO BIT(1) BIT 258 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define DOU_STATUS_TETO BIT(2) BIT 259 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define DOU_STATUS_CSCE BIT(8) BIT 260 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define DOU_STATUS_ACTIVE BIT(31) BIT 277 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define L_EN BIT(0) BIT 278 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define L_IT BIT(4) BIT 279 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define L_R2R BIT(5) BIT 280 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define L_FT BIT(6) BIT 282 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define L_HFLIP BIT(10) BIT 283 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define L_VFLIP BIT(11) BIT 284 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define L_TBU_EN BIT(16) BIT 307 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LW_OFM BIT(4) BIT 310 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define LW_TBU_EN BIT(16) BIT 315 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define AxCACHE_B BIT(0) /* Bufferable */ BIT 316 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define AxCACHE_M BIT(1) /* Modifiable */ BIT 317 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define AxCACHE_RA BIT(2) /* Read-Allocate */ BIT 318 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define AxCACHE_WA BIT(3) /* Write-Allocate */ BIT 321 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define L_INFO_RF BIT(0) BIT 322 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define L_INFO_CM BIT(1) BIT 340 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define SC_CTRL_SCL BIT(0) BIT 341 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define SC_CTRL_LS BIT(1) BIT 342 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define SC_CTRL_AP BIT(4) BIT 343 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define SC_CTRL_IENH BIT(8) BIT 344 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define SC_CTRL_RGBSM BIT(16) BIT 345 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define SC_CTRL_ASM BIT(17) BIT 385 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_EN BIT(0) BIT 386 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_VM BIT(1) BIT 387 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_BM BIT(2) BIT 388 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_HMASK BIT(4) BIT 389 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_VD BIT(5) BIT 390 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_TE BIT(8) BIT 391 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_TS BIT(9) BIT 392 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_TM BIT(12) BIT 393 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_DL BIT(16) BIT 394 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_SBS BIT(17) BIT 395 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_CRC BIT(18) BIT 396 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_CTRL_PM BIT(20) BIT 404 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_SYNC_HSP BIT(12) BIT 406 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define BS_SYNC_VSP BIT(28) BIT 419 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define IPS_CTRL_RGB BIT(0) BIT 420 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define IPS_CTRL_FT BIT(4) BIT 421 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define IPS_CTRL_YUV BIT(8) BIT 422 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define IPS_CTRL_CHD422 BIT(9) BIT 423 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define IPS_CTRL_CHD420 BIT(10) BIT 424 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define IPS_CTRL_LPF BIT(11) BIT 425 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define IPS_CTRL_DITH BIT(12) BIT 426 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define IPS_CTRL_CLAMP BIT(16) BIT 427 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define IPS_CTRL_SBS BIT(17) BIT 430 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define IPS_INFO_CHD420 BIT(10) BIT 447 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define SC_COEFF_R_ADDR BIT(18) BIT 448 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define SC_COEFF_G_ADDR BIT(17) BIT 449 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define SC_COEFF_B_ADDR BIT(16) BIT 93 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c new_mode = mdev->dpmode | BIT(master->id); BIT 144 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c new_mode = mdev->dpmode & (~BIT(master->id)); BIT 139 drivers/gpu/drm/arm/display/komeda/komeda_dev.h KOMEDA_MODE_DISP0 = BIT(0), BIT 140 drivers/gpu/drm/arm/display/komeda/komeda_dev.h KOMEDA_MODE_DISP1 = BIT(1), BIT 30 drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h #define KOMEDA_FMT_RICH_LAYER BIT(0) BIT 31 drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h #define KOMEDA_FMT_SIMPLE_LAYER BIT(1) BIT 32 drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h #define KOMEDA_FMT_WB_LAYER BIT(2) BIT 141 drivers/gpu/drm/arm/display/komeda/komeda_kms.h return conn && (st->connector_mask == BIT(drm_connector_index(conn))); BIT 153 drivers/gpu/drm/arm/display/komeda/komeda_kms.h return BIT(drm_connector_index(conn)) == changed_connectors; BIT 220 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c pipe->avail_comps |= BIT(c->id); BIT 238 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c c->name, c->id, BIT(c->id)); BIT 276 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c c->supported_inputs &= ~(BIT(id)); BIT 282 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c input->supported_outputs |= BIT(c->id); BIT 38 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define KOMEDA_PIPELINE_LAYERS (BIT(KOMEDA_COMPONENT_LAYER0) |\ BIT 39 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h BIT(KOMEDA_COMPONENT_LAYER1) |\ BIT 40 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h BIT(KOMEDA_COMPONENT_LAYER2) |\ BIT 41 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h BIT(KOMEDA_COMPONENT_LAYER3)) BIT 43 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define KOMEDA_PIPELINE_SCALERS (BIT(KOMEDA_COMPONENT_SCALER0) |\ BIT 44 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h BIT(KOMEDA_COMPONENT_SCALER1)) BIT 46 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define KOMEDA_PIPELINE_COMPIZS (BIT(KOMEDA_COMPONENT_COMPIZ0) |\ BIT 47 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h BIT(KOMEDA_COMPONENT_COMPIZ1)) BIT 49 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define KOMEDA_PIPELINE_IMPROCS (BIT(KOMEDA_COMPONENT_IPS0) |\ BIT 50 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h BIT(KOMEDA_COMPONENT_IPS1)) BIT 92 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c kcrtc_st->active_pipes |= BIT(pipe->id); BIT 93 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c kcrtc_st->affected_pipes |= BIT(pipe->id); BIT 178 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c pipe_st->active_comps |= BIT(c->id); BIT 200 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c state->changed_active_inputs |= BIT(idx); BIT 202 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c state->active_inputs |= BIT(idx); BIT 203 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c state->affected_inputs |= BIT(idx); BIT 694 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st->changed_active_inputs |= BIT(idx); BIT 1271 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c if (new->active_comps & BIT(c->id)) BIT 217 drivers/gpu/drm/arm/display/komeda/komeda_plane.c possible_crtcs |= BIT(i); BIT 235 drivers/gpu/drm/arm/display/komeda/komeda_plane.c kcrtc->slave_planes |= BIT(drm_plane_index(plane)); BIT 292 drivers/gpu/drm/arm/display/komeda/komeda_plane.c BIT(DRM_MODE_BLEND_PIXEL_NONE) | BIT 293 drivers/gpu/drm/arm/display/komeda/komeda_plane.c BIT(DRM_MODE_BLEND_PREMULTI) | BIT 294 drivers/gpu/drm/arm/display/komeda/komeda_plane.c BIT(DRM_MODE_BLEND_COVERAGE)); BIT 299 drivers/gpu/drm/arm/display/komeda/komeda_plane.c BIT(DRM_COLOR_YCBCR_BT601) | BIT 300 drivers/gpu/drm/arm/display/komeda/komeda_plane.c BIT(DRM_COLOR_YCBCR_BT709) | BIT 301 drivers/gpu/drm/arm/display/komeda/komeda_plane.c BIT(DRM_COLOR_YCBCR_BT2020), BIT 302 drivers/gpu/drm/arm/display/komeda/komeda_plane.c BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT 303 drivers/gpu/drm/arm/display/komeda/komeda_plane.c BIT(DRM_COLOR_YCBCR_FULL_RANGE), BIT 157 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c wb_conn->encoder.possible_crtcs = BIT(drm_crtc_index(&kcrtc->base)); BIT 239 drivers/gpu/drm/arm/malidp_crtc.c if (!!(val & BIT_ULL(63)) != !!(mag & BIT(14))) BIT 27 drivers/gpu/drm/arm/malidp_hw.h DE_VIDEO1 = BIT(0), BIT 28 drivers/gpu/drm/arm/malidp_hw.h DE_GRAPHICS1 = BIT(1), BIT 29 drivers/gpu/drm/arm/malidp_hw.h DE_GRAPHICS2 = BIT(2), /* used only in DP500 */ BIT 30 drivers/gpu/drm/arm/malidp_hw.h DE_VIDEO2 = BIT(3), BIT 31 drivers/gpu/drm/arm/malidp_hw.h DE_SMART = BIT(4), BIT 32 drivers/gpu/drm/arm/malidp_hw.h SE_MEMWRITE = BIT(5), BIT 94 drivers/gpu/drm/arm/malidp_hw.h #define MALIDP_REGMAP_HAS_CLEARIRQ BIT(0) BIT 95 drivers/gpu/drm/arm/malidp_hw.h #define MALIDP_DEVICE_AFBC_SUPPORT_SPLIT BIT(1) BIT 96 drivers/gpu/drm/arm/malidp_hw.h #define MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT BIT(2) BIT 97 drivers/gpu/drm/arm/malidp_hw.h #define MALIDP_DEVICE_AFBC_YUYV_USE_422_P2 BIT(3) BIT 133 drivers/gpu/drm/arm/malidp_hw.h #define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0) BIT 934 drivers/gpu/drm/arm/malidp_planes.c unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | BIT 935 drivers/gpu/drm/arm/malidp_planes.c BIT(DRM_MODE_BLEND_PREMULTI) | BIT 936 drivers/gpu/drm/arm/malidp_planes.c BIT(DRM_MODE_BLEND_COVERAGE); BIT 1018 drivers/gpu/drm/arm/malidp_planes.c BIT(DRM_COLOR_YCBCR_BT601) | \ BIT 1019 drivers/gpu/drm/arm/malidp_planes.c BIT(DRM_COLOR_YCBCR_BT709) | \ BIT 1020 drivers/gpu/drm/arm/malidp_planes.c BIT(DRM_COLOR_YCBCR_BT2020), BIT 1021 drivers/gpu/drm/arm/malidp_planes.c BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \ BIT 1022 drivers/gpu/drm/arm/malidp_planes.c BIT(DRM_COLOR_YCBCR_FULL_RANGE), BIT 271 drivers/gpu/drm/arm/malidp_regs.h #define MALIDP_AD_EN BIT(0) BIT 272 drivers/gpu/drm/arm/malidp_regs.h #define MALIDP_AD_YTR BIT(4) BIT 273 drivers/gpu/drm/arm/malidp_regs.h #define MALIDP_AD_BS BIT(8) BIT 89 drivers/gpu/drm/armada/armada_510.c .settable = BIT(0) | BIT(1), BIT 846 drivers/gpu/drm/armada/armada_crtc.c if (params->settable & BIT(i)) { BIT 90 drivers/gpu/drm/armada/armada_hw.h CFG_SRAM_WAIT = BIT(11), BIT 91 drivers/gpu/drm/armada/armada_hw.h CFG_SMPN_FASTTX = BIT(10), BIT 92 drivers/gpu/drm/armada/armada_hw.h CFG_DMA_ARB = BIT(9), BIT 93 drivers/gpu/drm/armada/armada_hw.h CFG_DMA_WM_EN = BIT(8), BIT 589 drivers/gpu/drm/armada/armada_overlay.c BIT(DRM_COLOR_YCBCR_BT601) | BIT 590 drivers/gpu/drm/armada/armada_overlay.c BIT(DRM_COLOR_YCBCR_BT709), BIT 591 drivers/gpu/drm/armada/armada_overlay.c BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), BIT 58 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_EN BIT(0) BIT 59 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_HW_CURSOR_EN BIT(1) BIT 60 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_OSD_EN BIT(2) BIT 61 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_INTERLACED BIT(3) BIT 69 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_HSYNC_NEGATIVE BIT(16) BIT 70 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_VSYNC_NEGATIVE BIT(17) BIT 71 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_VERTICAL_INTR_EN BIT(30) BIT 72 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_VERTICAL_INTR_STS BIT(31) BIT 75 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_DAC_EN BIT(0) BIT 63 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c regmap_update_bits(priv->scu, 0x2c, BIT(16), BIT(16)); BIT 77 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c regmap_update_bits(priv->scu, 0x2c, BIT(16), 0); BIT 238 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c #define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) BIT 239 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c #define ATMEL_HLCDC_RGB565_OUTPUT BIT(1) BIT 240 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c #define ATMEL_HLCDC_RGB666_OUTPUT BIT(2) BIT 241 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c #define ATMEL_HLCDC_RGB888_OUTPUT BIT(3) BIT 21 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_EN BIT(0) BIT 22 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_UPDATE BIT(1) BIT 23 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_A2Q BIT(2) BIT 24 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_RST BIT(8) BIT 30 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DFETCH BIT(0) BIT 31 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_LFETCH BIT(1) BIT 32 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DMA_IRQ(p) BIT(2 + (8 * (p))) BIT 33 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DSCR_IRQ(p) BIT(3 + (8 * (p))) BIT 34 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_ADD_IRQ(p) BIT(4 + (8 * (p))) BIT 35 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DONE_IRQ(p) BIT(5 + (8 * (p))) BIT 36 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_OVR_IRQ(p) BIT(6 + (8 * (p))) BIT 44 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0) BIT 50 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8) BIT 51 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12) BIT 52 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13) BIT 64 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_YUV422ROT BIT(16) BIT 65 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_YUV422SWP BIT(17) BIT 66 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_DSCALEOPT BIT(20) BIT 96 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_CRKEY BIT(0) BIT 97 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_INV BIT(1) BIT 98 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_ITER2BL BIT(2) BIT 99 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_ITER BIT(3) BIT 100 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_REVALPHA BIT(4) BIT 101 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_GAEN BIT(5) BIT 102 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_LAEN BIT(6) BIT 103 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_OVR BIT(7) BIT 104 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DMA BIT(8) BIT 105 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_REP BIT(9) BIT 106 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DSTKEY BIT(10) BIT 107 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DISCEN BIT(11) BIT 118 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_SCALER_ENABLE BIT(31) BIT 122 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0) BIT 123 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1) BIT 124 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2) BIT 125 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3) BIT 102 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_CSC_ENABLE BIT(7) BIT 103 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_CSC_UPDATE_MODE BIT(5) BIT 105 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT0_HPD BIT(7) BIT 106 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT0_VSYNC BIT(5) BIT 107 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4) BIT 108 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT0_EDID_READY BIT(2) BIT 109 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT0_HDCP_AUTHENTICATED BIT(1) BIT 111 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT1_DDC_ERROR BIT(7) BIT 112 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT1_BKSV BIT(6) BIT 113 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT1_CEC_TX_READY BIT(5) BIT 114 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT1_CEC_TX_ARBIT_LOST BIT(4) BIT 115 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT1_CEC_TX_RETRY_TIMEOUT BIT(3) BIT 116 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT1_CEC_RX_READY3 BIT(2) BIT 117 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT1_CEC_RX_READY2 BIT(1) BIT 118 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_INT1_CEC_RX_READY1 BIT(0) BIT 120 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_ARC_CTRL_POWER_DOWN BIT(0) BIT 122 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_CEC_CTRL_POWER_DOWN BIT(0) BIT 124 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_POWER_POWER_DOWN BIT(6) BIT 154 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_STATUS_POWER_DOWN_POLARITY BIT(7) BIT 155 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_STATUS_HPD BIT(6) BIT 156 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_STATUS_MONITOR_SENSE BIT(5) BIT 157 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_STATUS_I2S_32BIT_MODE BIT(3) BIT 159 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_N_CTS BIT(8+6) BIT 160 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_AUDIO_SAMPLE BIT(8+5) BIT 161 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_AVI_INFOFRAME BIT(8+4) BIT 162 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME BIT(8+3) BIT 163 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_GC BIT(7) BIT 164 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_SPD BIT(6) BIT 165 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_MPEG BIT(5) BIT 166 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_ACP BIT(4) BIT 167 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_ISRC BIT(3) BIT 168 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_GM BIT(2) BIT 169 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_SPARE2 BIT(1) BIT 170 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_PACKET_ENABLE_SPARE1 BIT(0) BIT 177 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_REG_POWER2_TDMS_ENABLE BIT(4) BIT 178 drivers/gpu/drm/bridge/adv7511/adv7511.h #define ADV7511_REG_POWER2_GATE_INPUT_CLK BIT(0) BIT 130 drivers/gpu/drm/bridge/adv7511/adv7511_audio.c regmap_update_bits(adv7511->regmap, ADV7511_REG_AUDIO_CONFIG, BIT(6), BIT 155 drivers/gpu/drm/bridge/adv7511/adv7511_audio.c BIT(7), 0); BIT 159 drivers/gpu/drm/bridge/adv7511/adv7511_audio.c BIT(5), BIT(5)); BIT 162 drivers/gpu/drm/bridge/adv7511/adv7511_audio.c BIT(5), BIT(5)); BIT 165 drivers/gpu/drm/bridge/adv7511/adv7511_audio.c BIT(6), BIT(6)); BIT 168 drivers/gpu/drm/bridge/adv7511/adv7511_audio.c BIT(5), BIT(5)); BIT 171 drivers/gpu/drm/bridge/adv7511/adv7511_audio.c BIT(3), BIT(3)); BIT 174 drivers/gpu/drm/bridge/adv7511/adv7511_audio.c BIT(7) | BIT(6), BIT(7)); BIT 177 drivers/gpu/drm/bridge/adv7511/adv7511_audio.c BIT(5), 0); BIT 324 drivers/gpu/drm/bridge/analogix-anx78xx.c SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) | BIT 325 drivers/gpu/drm/bridge/analogix-anx78xx.c BIT(6)); BIT 26 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VIDEO_RST BIT(4) BIT 27 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDCP_MAN_RST BIT(2) BIT 28 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_TMDS_RST BIT(1) BIT 29 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_SW_MAN_RST BIT(0) BIT 33 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_TMDS_CLOCK_DET BIT(1) BIT 34 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_TMDS_DE_DET BIT(0) BIT 38 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDMI_AUD_LAYOUT BIT(3) BIT 39 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDMI_DET BIT(0) BIT 45 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUD_MUTE BIT(1) BIT 46 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VID_MUTE BIT(0) BIT 50 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_PWDN_CTRL BIT(0) BIT 58 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AVC_OE BIT(7) BIT 59 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AAC_OE BIT(6) BIT 60 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AVC_EN BIT(1) BIT 61 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AAC_EN BIT(0) BIT 66 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AEC_EN21 BIT(5) BIT 75 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDMI_DVI BIT(7) BIT 76 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_CKDT_CHG BIT(6) BIT 77 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_SCDT_CHG BIT(5) BIT 78 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_PCLK_CHG BIT(4) BIT 79 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_PLL_UNLOCK BIT(3) BIT 80 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_CABLE_PLUG_CHG BIT(2) BIT 81 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_SET_MUTE BIT(1) BIT 82 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_SW_INTR BIT(0) BIT 84 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDCP_ERR BIT(5) BIT 85 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUDIO_SAMPLE_CHG BIT(0) /* undocumented */ BIT 87 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUD_MODE_CHG BIT(0) BIT 89 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUDIO_RCV BIT(0) BIT 92 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_CTS_RCV BIT(7) BIT 93 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_NEW_AUD_PKT BIT(4) BIT 94 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_NEW_AVI_PKT BIT(1) BIT 95 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_NEW_CP_PKT BIT(0) BIT 97 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_NO_VSI BIT(7) BIT 98 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_NEW_VS BIT(4) BIT 114 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_PD_RT BIT(0) BIT 132 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_R2Y_INPUT_LIMIT BIT(1) BIT 163 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_MAN_HDMI5V_DET BIT(3) BIT 164 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_PLLLOCK_CKDT_EN BIT(2) BIT 165 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_ANALOG_CKDT_EN BIT(1) BIT 166 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_DIGITAL_CKDT_EN BIT(0) BIT 170 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AVI_RCVD BIT(5) BIT 171 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VSI_RCVD BIT(1) BIT 179 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_BCAPS_REPEATER BIT(5) BIT 183 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUTH_EN BIT(4) BIT 216 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_CLEAR_AVMUTE BIT(4) BIT 217 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_SET_AVMUTE BIT(0) BIT 225 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUTH_FAIL BIT(5) BIT 226 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUTHEN_PASS BIT(1) BIT 230 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_RX_REPEATER BIT(6) BIT 231 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_RE_AUTH BIT(5) BIT 232 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_SW_AUTH_OK BIT(4) BIT 233 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HARD_AUTH_EN BIT(3) BIT 234 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDCP_ENC_EN BIT(2) BIT 235 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_BKSV_SRM_PASS BIT(1) BIT 236 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_KSVLIST_VLD BIT(0) BIT 238 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDCP_FUNCTION_ENABLED (BIT(0) | BIT(1) | BIT(2) | BIT(3)) BIT 267 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_DISABLE_SYNC_HDCP BIT(2) BIT 280 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_CHA_STA BIT(2) BIT 282 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HPD_STATUS BIT(6) BIT 283 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_STRM_VALID BIT(2) BIT 285 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_ENHANCED_MODE BIT(3) BIT 300 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUD_EN BIT(0) BIT 308 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUD_IF_UP BIT(7) BIT 309 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AVI_IF_UD BIT(6) BIT 310 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_MPEG_IF_UD BIT(5) BIT 311 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_SPD_IF_UD BIT(4) BIT 312 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUD_IF_EN BIT(3) BIT 313 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AVI_IF_EN BIT(2) BIT 314 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_MPEG_IF_EN BIT(1) BIT 315 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_SPD_IF_EN BIT(0) BIT 319 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUTO_EN BIT(7) BIT 320 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUTO_START BIT(5) BIT 321 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_LINK_POLLING BIT(1) BIT 326 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_INITIAL_SLIM_M_AUD_SEL BIT(5) BIT 334 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_MAX_PRE_REACH BIT(5) BIT 335 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_MAX_DRIVE_REACH BIT(4) BIT 336 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_PRE_EMP_LEVEL1 BIT(3) BIT 337 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_DRVIE_CURRENT_LEVEL1 BIT(0) BIT 349 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_LT_EN BIT(0) BIT 357 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_DEBUG_PLL_LOCK BIT(4) BIT 358 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_POLLING_EN BIT(1) BIT 362 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUTO_POLLING_DISABLE BIT(0) BIT 366 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_M_VID_DEBUG BIT(5) BIT 367 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_NEW_PRBS7 BIT(4) BIT 368 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_INSERT_ER BIT(1) BIT 369 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_PRBS31_EN BIT(0) BIT 376 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_PLL_RST BIT(6) BIT 380 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_CH0_PD BIT(0) BIT 384 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_EQ_TRAINING_LOOP BIT(6) BIT 388 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_I2C_STRETCH_DISABLE BIT(7) BIT 397 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_M_GEN_CLK_SEL BIT(0) BIT 405 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_DEFER_CTRL_EN BIT(7) BIT 410 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_BUF_CLR BIT(7) BIT 430 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUX_SEL_RXCM BIT(6) BIT 431 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUX_CHSEL BIT(3) BIT 432 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUX_PN_INV BIT(2) BIT 433 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_ADDR_ONLY BIT(1) BIT 434 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUX_EN BIT(0) BIT 438 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_INFO_FRAME_VSC_EN BIT(0) BIT 472 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_REGISTER_PD BIT(7) BIT 473 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDCP_PD BIT(5) BIT 474 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUDIO_PD BIT(4) BIT 475 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VIDEO_PD BIT(3) BIT 476 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_LINK_PD BIT(2) BIT 477 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_TOTAL_PD BIT(1) BIT 481 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_MISC_RST BIT(7) BIT 482 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VIDCAP_RST BIT(6) BIT 483 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VIDFIF_RST BIT(5) BIT 484 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUDFIF_RST BIT(4) BIT 485 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUDCAP_RST BIT(3) BIT 486 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDCP_RST BIT(2) BIT 487 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_SW_RST BIT(1) BIT 488 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HW_RST BIT(0) BIT 492 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUX_RST BIT(2) BIT 493 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_SERDES_FIFO_RST BIT(1) BIT 494 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_I2C_REG_RST BIT(0) BIT 498 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VIDEO_EN BIT(7) BIT 499 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VIDEO_MUTE BIT(2) BIT 500 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_DE_GEN BIT(1) BIT 501 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_DEMUX BIT(0) BIT 506 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_IN_YC_BIT_SEL BIT(2) BIT 513 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_IN_D_RANGE BIT(7) BIT 517 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HPD_OUT BIT(6) BIT 521 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_CSC_STD_SEL BIT(7) BIT 522 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_XVYCC_RNG_LMT BIT(6) BIT 523 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_RANGE_Y2R BIT(5) BIT 524 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_CSPACE_Y2R BIT(4) BIT 525 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_RGB_RNG_LMT BIT(3) BIT 526 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_Y_RNG_LMT BIT(2) BIT 527 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_RANGE_R2Y BIT(1) BIT 528 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_CSPACE_R2Y BIT(0) BIT 532 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_TEST_PATTERN_EN BIT(7) BIT 533 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VIDEO_PROCESS_EN BIT(6) BIT 534 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VID_US_MODE BIT(3) BIT 535 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VID_DS_MODE BIT(2) BIT 536 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_UP_SAMPLE BIT(1) BIT 537 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_DOWN_SAMPLE BIT(0) BIT 541 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VID_VRES_TH BIT(0) BIT 600 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_ENABLE_BIT_CTRL BIT(0) BIT 621 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_EXT_VUCP BIT(2) BIT 622 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_VBIT BIT(1) BIT 623 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_AUDIO_LAYOUT BIT(0) BIT 647 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDCP_AUTH_CHG BIT(1) BIT 648 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDCP_AUTH_DONE BIT(0) BIT 650 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HDCP_LINK_CHECK_FAIL BIT(0) BIT 654 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HPD_IRQ BIT(6) BIT 655 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HPD_ESYNC_ERR BIT(4) BIT 656 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HPD_CHG BIT(2) BIT 657 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HPD_LOST BIT(1) BIT 658 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_HPD_PLUG BIT(0) BIT 662 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_TRAINING_FINISH BIT(5) BIT 663 drivers/gpu/drm/bridge/analogix-anx78xx.h #define SP_POLLING_ERR BIT(4) BIT 124 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), BIT 125 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), BIT 126 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h DP_IRQ_TYPE_HP_CHANGE = BIT(2), BIT 127 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h DP_IRQ_TYPE_UNKNOWN = BIT(3), BIT 34 drivers/gpu/drm/bridge/cdns-dsi.c #define SDI_IFACE_32 BIT(12) BIT 44 drivers/gpu/drm/bridge/cdns-dsi.c #define TE_MIPI_POLLING_EN BIT(25) BIT 45 drivers/gpu/drm/bridge/cdns-dsi.c #define TE_HW_POLLING_EN BIT(24) BIT 46 drivers/gpu/drm/bridge/cdns-dsi.c #define DISP_EOT_GEN BIT(18) BIT 47 drivers/gpu/drm/bridge/cdns-dsi.c #define HOST_EOT_GEN BIT(17) BIT 48 drivers/gpu/drm/bridge/cdns-dsi.c #define DISP_GEN_CHECKSUM BIT(16) BIT 49 drivers/gpu/drm/bridge/cdns-dsi.c #define DISP_GEN_ECC BIT(15) BIT 50 drivers/gpu/drm/bridge/cdns-dsi.c #define BTA_EN BIT(14) BIT 51 drivers/gpu/drm/bridge/cdns-dsi.c #define READ_EN BIT(13) BIT 52 drivers/gpu/drm/bridge/cdns-dsi.c #define REG_TE_EN BIT(12) BIT 53 drivers/gpu/drm/bridge/cdns-dsi.c #define IF_TE_EN(x) BIT(8 + (x)) BIT 54 drivers/gpu/drm/bridge/cdns-dsi.c #define TVG_SEL BIT(6) BIT 55 drivers/gpu/drm/bridge/cdns-dsi.c #define VID_EN BIT(5) BIT 58 drivers/gpu/drm/bridge/cdns-dsi.c #define IF_VID_MODE BIT(1) BIT 59 drivers/gpu/drm/bridge/cdns-dsi.c #define LINK_EN BIT(0) BIT 62 drivers/gpu/drm/bridge/cdns-dsi.c #define HS_INVERT_DAT(x) BIT(19 + ((x) * 2)) BIT 63 drivers/gpu/drm/bridge/cdns-dsi.c #define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2)) BIT 64 drivers/gpu/drm/bridge/cdns-dsi.c #define HS_INVERT_CLK BIT(17) BIT 65 drivers/gpu/drm/bridge/cdns-dsi.c #define SWAP_PINS_CLK BIT(16) BIT 66 drivers/gpu/drm/bridge/cdns-dsi.c #define HS_SKEWCAL_EN BIT(15) BIT 68 drivers/gpu/drm/bridge/cdns-dsi.c #define DATA_ULPM_EN(x) BIT(6 + (x)) BIT 69 drivers/gpu/drm/bridge/cdns-dsi.c #define CLK_ULPM_EN BIT(5) BIT 70 drivers/gpu/drm/bridge/cdns-dsi.c #define CLK_CONTINUOUS BIT(4) BIT 71 drivers/gpu/drm/bridge/cdns-dsi.c #define DATA_LANE_EN(x) BIT((x) - 1) BIT 74 drivers/gpu/drm/bridge/cdns-dsi.c #define DATA_FORCE_STOP BIT(17) BIT 75 drivers/gpu/drm/bridge/cdns-dsi.c #define CLK_FORCE_STOP BIT(16) BIT 76 drivers/gpu/drm/bridge/cdns-dsi.c #define IF_EN(x) BIT(13 + (x)) BIT 77 drivers/gpu/drm/bridge/cdns-dsi.c #define DATA_LANE_ULPM_REQ(l) BIT(9 + (l)) BIT 78 drivers/gpu/drm/bridge/cdns-dsi.c #define CLK_LANE_ULPM_REQ BIT(8) BIT 79 drivers/gpu/drm/bridge/cdns-dsi.c #define DATA_LANE_START(x) BIT(4 + (x)) BIT 80 drivers/gpu/drm/bridge/cdns-dsi.c #define CLK_LANE_EN BIT(3) BIT 81 drivers/gpu/drm/bridge/cdns-dsi.c #define PLL_START BIT(0) BIT 84 drivers/gpu/drm/bridge/cdns-dsi.c #define DPHY_C_RSTB BIT(20) BIT 86 drivers/gpu/drm/bridge/cdns-dsi.c #define DPHY_PLL_PDN BIT(10) BIT 87 drivers/gpu/drm/bridge/cdns-dsi.c #define DPHY_CMN_PDN BIT(9) BIT 88 drivers/gpu/drm/bridge/cdns-dsi.c #define DPHY_C_PDN BIT(8) BIT 91 drivers/gpu/drm/bridge/cdns-dsi.c #define DPHY_PLL_PSO BIT(1) BIT 92 drivers/gpu/drm/bridge/cdns-dsi.c #define DPHY_CMN_PSO BIT(0) BIT 108 drivers/gpu/drm/bridge/cdns-dsi.c #define VID_VSYNC_3D_EN BIT(7) BIT 109 drivers/gpu/drm/bridge/cdns-dsi.c #define VID_VSYNC_3D_LR BIT(5) BIT 110 drivers/gpu/drm/bridge/cdns-dsi.c #define VID_VSYNC_3D_SECOND_EN BIT(4) BIT 122 drivers/gpu/drm/bridge/cdns-dsi.c #define HS_SKEWCAL_DONE BIT(11) BIT 123 drivers/gpu/drm/bridge/cdns-dsi.c #define IF_UNTERM_PKT_ERR(x) BIT(8 + (x)) BIT 124 drivers/gpu/drm/bridge/cdns-dsi.c #define LPRX_TIMEOUT_ERR BIT(7) BIT 125 drivers/gpu/drm/bridge/cdns-dsi.c #define HSTX_TIMEOUT_ERR BIT(6) BIT 126 drivers/gpu/drm/bridge/cdns-dsi.c #define DATA_LANE_RDY(l) BIT(2 + (l)) BIT 127 drivers/gpu/drm/bridge/cdns-dsi.c #define CLK_LANE_RDY BIT(1) BIT 128 drivers/gpu/drm/bridge/cdns-dsi.c #define PLL_LOCKED BIT(0) BIT 134 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l)) BIT 135 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_CONTROL(l) BIT(14 + (l)) BIT 136 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_SYNESC(l) BIT(10 + (l)) BIT 137 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_ESC(l) BIT(6 + (l)) BIT 140 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_CONT_LP_EDGE(x, l) BIT(12 + ((x) * 4) + (l)) BIT 141 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_CONTROL_EDGE(l) BIT(8 + (l)) BIT 142 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_SYN_ESC_EDGE(l) BIT(4 + (l)) BIT 143 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_ESC_EDGE(l) BIT(0 + (l)) BIT 146 drivers/gpu/drm/bridge/cdns-dsi.c #define PPI_C_TX_READY_HS BIT(18) BIT 147 drivers/gpu/drm/bridge/cdns-dsi.c #define DPHY_PLL_LOCK BIT(17) BIT 160 drivers/gpu/drm/bridge/cdns-dsi.c #define DSC_MODE_EN BIT(0) BIT 163 drivers/gpu/drm/bridge/cdns-dsi.c #define DSC_SEND_PPS BIT(0) BIT 164 drivers/gpu/drm/bridge/cdns-dsi.c #define DSC_EXECUTE_QUEUE BIT(1) BIT 169 drivers/gpu/drm/bridge/cdns-dsi.c #define DSC_PPS_DONE BIT(1) BIT 170 drivers/gpu/drm/bridge/cdns-dsi.c #define DSC_EXEC_DONE BIT(2) BIT 173 drivers/gpu/drm/bridge/cdns-dsi.c #define IF_LP_EN(x) BIT(9 + (x)) BIT 180 drivers/gpu/drm/bridge/cdns-dsi.c #define ARB_ROUND_ROBIN_MODE BIT(0) BIT 186 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_IF_UNDERRUN(x) BIT(4 + (x)) BIT 187 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_UNWANTED_READ BIT(3) BIT 188 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_TE_MISS BIT(2) BIT 189 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_NO_TE BIT(1) BIT 190 drivers/gpu/drm/bridge/cdns-dsi.c #define CSM_RUNNING BIT(0) BIT 196 drivers/gpu/drm/bridge/cdns-dsi.c #define CMD_LP_EN BIT(24) BIT 200 drivers/gpu/drm/bridge/cdns-dsi.c #define CMD_LONG BIT(3) BIT 213 drivers/gpu/drm/bridge/cdns-dsi.c #define READ_COMPLETED_WITH_ERR BIT(10) BIT 214 drivers/gpu/drm/bridge/cdns-dsi.c #define BTA_FINISHED BIT(9) BIT 215 drivers/gpu/drm/bridge/cdns-dsi.c #define BTA_COMPLETED BIT(8) BIT 216 drivers/gpu/drm/bridge/cdns-dsi.c #define TE_RCVD BIT(7) BIT 217 drivers/gpu/drm/bridge/cdns-dsi.c #define TRIGGER_RCVD BIT(6) BIT 218 drivers/gpu/drm/bridge/cdns-dsi.c #define ACK_WITH_ERR_RCVD BIT(5) BIT 219 drivers/gpu/drm/bridge/cdns-dsi.c #define ACK_RCVD BIT(4) BIT 220 drivers/gpu/drm/bridge/cdns-dsi.c #define READ_COMPLETED BIT(3) BIT 221 drivers/gpu/drm/bridge/cdns-dsi.c #define TRIGGER_COMPLETED BIT(2) BIT 222 drivers/gpu/drm/bridge/cdns-dsi.c #define WRITE_COMPLETED BIT(1) BIT 223 drivers/gpu/drm/bridge/cdns-dsi.c #define SENDING_CMD BIT(0) BIT 234 drivers/gpu/drm/bridge/cdns-dsi.c #define RD_DCS BIT(18) BIT 242 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_EOT_WITH_ERR BIT(8) BIT 243 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_MISSING_EOT BIT(7) BIT 244 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_WRONG_LENGTH BIT(6) BIT 245 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_OVERSIZE BIT(5) BIT 246 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_RECEIVE BIT(4) BIT 247 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_UNDECODABLE BIT(3) BIT 248 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_CHECKSUM BIT(2) BIT 249 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_UNCORRECTABLE BIT(1) BIT 250 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_FIXED BIT(0) BIT 253 drivers/gpu/drm/bridge/cdns-dsi.c #define VID_IGNORE_MISS_VSYNC BIT(31) BIT 254 drivers/gpu/drm/bridge/cdns-dsi.c #define VID_FIELD_SW BIT(28) BIT 255 drivers/gpu/drm/bridge/cdns-dsi.c #define VID_INTERLACED_EN BIT(27) BIT 265 drivers/gpu/drm/bridge/cdns-dsi.c #define SYNC_PULSE_HORIZONTAL BIT(20) BIT 266 drivers/gpu/drm/bridge/cdns-dsi.c #define SYNC_PULSE_ACTIVE BIT(19) BIT 267 drivers/gpu/drm/bridge/cdns-dsi.c #define BURST_MODE BIT(18) BIT 335 drivers/gpu/drm/bridge/cdns-dsi.c #define VSG_RECOVERY BIT(10) BIT 336 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_VRS_WRONG_LEN BIT(9) BIT 337 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_LONG_READ BIT(8) BIT 338 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_LINE_WRITE BIT(7) BIT 339 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_BURST_WRITE BIT(6) BIT 340 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_SMALL_HEIGHT BIT(5) BIT 341 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_SMALL_LEN BIT(4) BIT 342 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_MISSING_VSYNC BIT(3) BIT 343 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_MISSING_HSYNC BIT(2) BIT 344 drivers/gpu/drm/bridge/cdns-dsi.c #define ERR_MISSING_DATA BIT(1) BIT 345 drivers/gpu/drm/bridge/cdns-dsi.c #define VSG_RUNNING BIT(0) BIT 348 drivers/gpu/drm/bridge/cdns-dsi.c #define BURST_LP BIT(16) BIT 365 drivers/gpu/drm/bridge/cdns-dsi.c #define TVG_RUN BIT(0) BIT 389 drivers/gpu/drm/bridge/cdns-dsi.c #define TVG_STS_RUNNING BIT(0) BIT 399 drivers/gpu/drm/bridge/cdns-dsi.c #define PIXEL_BUF_OVERFLOW BIT(0) BIT 33 drivers/gpu/drm/bridge/sii902x.c #define SII902X_TPI_AVI_PIXEL_REP_BUS_24BIT BIT(5) BIT 34 drivers/gpu/drm/bridge/sii902x.c #define SII902X_TPI_AVI_PIXEL_REP_RISING_EDGE BIT(4) BIT 44 drivers/gpu/drm/bridge/sii902x.c #define SII902X_TPI_AVI_INPUT_BITMODE_12BIT BIT(7) BIT 45 drivers/gpu/drm/bridge/sii902x.c #define SII902X_TPI_AVI_INPUT_DITHER BIT(6) BIT 57 drivers/gpu/drm/bridge/sii902x.c #define SII902X_SYS_CTRL_PWR_DWN BIT(4) BIT 58 drivers/gpu/drm/bridge/sii902x.c #define SII902X_SYS_CTRL_AV_MUTE BIT(3) BIT 59 drivers/gpu/drm/bridge/sii902x.c #define SII902X_SYS_CTRL_DDC_BUS_REQ BIT(2) BIT 60 drivers/gpu/drm/bridge/sii902x.c #define SII902X_SYS_CTRL_DDC_BUS_GRTD BIT(1) BIT 61 drivers/gpu/drm/bridge/sii902x.c #define SII902X_SYS_CTRL_OUTPUT_MODE BIT(0) BIT 144 drivers/gpu/drm/bridge/sii902x.c #define SII902X_HOTPLUG_EVENT BIT(0) BIT 145 drivers/gpu/drm/bridge/sii902x.c #define SII902X_PLUGGED_STATUS BIT(2) BIT 37 drivers/gpu/drm/bridge/sii9234.c #define BIT_TMDS_CCTRL_TMDS_OE BIT(4) BIT 38 drivers/gpu/drm/bridge/sii9234.c #define MHL_HPD_OUT_OVR_EN BIT(4) BIT 39 drivers/gpu/drm/bridge/sii9234.c #define MHL_HPD_OUT_OVR_VAL BIT(5) BIT 66 drivers/gpu/drm/bridge/sii9234.c #define RSEN_STATUS BIT(2) BIT 67 drivers/gpu/drm/bridge/sii9234.c #define HPD_CHANGE_INT BIT(6) BIT 68 drivers/gpu/drm/bridge/sii9234.c #define RSEN_CHANGE_INT BIT(5) BIT 69 drivers/gpu/drm/bridge/sii9234.c #define RGND_READY_INT BIT(6) BIT 70 drivers/gpu/drm/bridge/sii9234.c #define VBUS_LOW_INT BIT(5) BIT 71 drivers/gpu/drm/bridge/sii9234.c #define CBUS_LKOUT_INT BIT(4) BIT 72 drivers/gpu/drm/bridge/sii9234.c #define MHL_DISC_FAIL_INT BIT(3) BIT 73 drivers/gpu/drm/bridge/sii9234.c #define MHL_EST_INT BIT(2) BIT 74 drivers/gpu/drm/bridge/sii9234.c #define HPD_CHANGE_INT_MASK BIT(6) BIT 75 drivers/gpu/drm/bridge/sii9234.c #define RSEN_CHANGE_INT_MASK BIT(5) BIT 77 drivers/gpu/drm/bridge/sii9234.c #define RGND_READY_MASK BIT(6) BIT 78 drivers/gpu/drm/bridge/sii9234.c #define CBUS_LKOUT_MASK BIT(4) BIT 79 drivers/gpu/drm/bridge/sii9234.c #define MHL_DISC_FAIL_MASK BIT(3) BIT 80 drivers/gpu/drm/bridge/sii9234.c #define MHL_EST_MASK BIT(2) BIT 82 drivers/gpu/drm/bridge/sii9234.c #define SKIP_GND BIT(6) BIT 86 drivers/gpu/drm/bridge/sii9234.c #define USB_D_OEN BIT(3) BIT 97 drivers/gpu/drm/bridge/sii9234.c #define USB_D_OVR BIT(7) BIT 98 drivers/gpu/drm/bridge/sii9234.c #define USB_ID_OVR BIT(6) BIT 99 drivers/gpu/drm/bridge/sii9234.c #define DVRFLT_SEL BIT(5) BIT 100 drivers/gpu/drm/bridge/sii9234.c #define BLOCK_RGND_INT BIT(4) BIT 101 drivers/gpu/drm/bridge/sii9234.c #define SKIP_DEG BIT(3) BIT 102 drivers/gpu/drm/bridge/sii9234.c #define CI2CA_POL BIT(2) BIT 103 drivers/gpu/drm/bridge/sii9234.c #define CI2CA_WKUP BIT(1) BIT 104 drivers/gpu/drm/bridge/sii9234.c #define SINGLE_ATT BIT(0) BIT 106 drivers/gpu/drm/bridge/sii9234.c #define USB_D_ODN BIT(5) BIT 107 drivers/gpu/drm/bridge/sii9234.c #define VBUS_CHECK BIT(2) BIT 138 drivers/gpu/drm/bridge/sii9234.c #define BIT_CBUS_RESET BIT(3) BIT 139 drivers/gpu/drm/bridge/sii9234.c #define SET_HPD_DOWNSTREAM BIT(6) BIT 1075 drivers/gpu/drm/bridge/sil-sii8620.c ptr[7] |= frame->sep_audio ? BIT(5) : 0; BIT 1087 drivers/gpu/drm/bridge/sil-sii8620.c ptr[12] |= BIT(4); BIT 35 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7) BIT 36 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SYS_CTRL1_VSYNCPIN BIT(6) BIT 37 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5) BIT 38 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4) BIT 39 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3) BIT 40 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2) BIT 41 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1) BIT 42 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0) BIT 46 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DPD_PWRON_PLL BIT(7) BIT 47 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DPD_PDNTX12 BIT(6) BIT 48 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DPD_PDNRX12 BIT(5) BIT 49 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DPD_OSC_EN BIT(4) BIT 50 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DPD_PWRON_HSIC BIT(3) BIT 51 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DPD_PDIDCK_N BIT(2) BIT 52 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DPD_PD_MHL_CLK_N BIT(1) BIT 56 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DCTL_TDM_LCLK_PHASE BIT(7) BIT 57 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DCTL_HSIC_CLK_PHASE BIT(6) BIT 58 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DCTL_CTS_TCK_PHASE BIT(5) BIT 59 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DCTL_EXT_DDC_SEL BIT(4) BIT 60 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DCTL_TRANSCODE BIT(3) BIT 61 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DCTL_HSIC_RX_STROBE_PHASE BIT(2) BIT 62 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DCTL_HSIC_TX_BIST_START_SEL BIT(1) BIT 63 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DCTL_TCLKNX_PHASE BIT(0) BIT 67 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PWD_SRST_COC_DOC_RST BIT(7) BIT 68 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PWD_SRST_CBUS_RST_SW BIT(6) BIT 69 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PWD_SRST_CBUS_RST_SW_EN BIT(5) BIT 70 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PWD_SRST_MHLFIFO_RST BIT(4) BIT 71 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PWD_SRST_CBUS_RST BIT(3) BIT 72 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PWD_SRST_SW_RST_AUTO BIT(2) BIT 73 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PWD_SRST_HDCP2X_SW_RST BIT(1) BIT 74 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PWD_SRST_SW_RST BIT(0) BIT 84 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_VID_MODE_M1080P BIT(6) BIT 88 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_VID_OVRRD_PP_AUTO_DISABLE BIT(7) BIT 89 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_VID_OVRRD_M1080P_OVRRD BIT(6) BIT 90 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_VID_OVRRD_MINIVSYNC_ON BIT(5) BIT 91 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK BIT(4) BIT 92 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN BIT(3) BIT 93 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD BIT(2) BIT 94 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD BIT(0) BIT 124 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL1_GPIO_I_8 BIT(5) BIT 125 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL1_GPIO_OEN_8 BIT(4) BIT 126 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL1_GPIO_I_7 BIT(3) BIT 127 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL1_GPIO_OEN_7 BIT(2) BIT 128 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL1_GPIO_I_6 BIT(1) BIT 129 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL1_GPIO_OEN_6 BIT(0) BIT 133 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_INT_CTRL_SOFTWARE_WP BIT(7) BIT 134 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_INT_CTRL_INTR_OD BIT(2) BIT 135 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_INT_CTRL_INTR_POLARITY BIT(1) BIT 139 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_INTR_STATE_INTR_STATE BIT(0) BIT 149 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_CMD_DONE BIT(3) BIT 165 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_INTR_SCDT_CHANGE BIT(0) BIT 169 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HPD_CTRL_HPD_DS_SIGNAL BIT(7) BIT 170 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HPD_CTRL_HPD_OUT_OD_EN BIT(6) BIT 171 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HPD_CTRL_HPD_HIGH BIT(5) BIT 172 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HPD_CTRL_HPD_OUT_OVR_EN BIT(4) BIT 173 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HPD_CTRL_GPIO_I_1 BIT(3) BIT 174 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HPD_CTRL_GPIO_OEN_1 BIT(2) BIT 175 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HPD_CTRL_GPIO_I_0 BIT(1) BIT 176 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HPD_CTRL_GPIO_OEN_0 BIT(0) BIT 180 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL_GPIO_I_5 BIT(7) BIT 181 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL_GPIO_OEN_5 BIT(6) BIT 182 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL_GPIO_I_4 BIT(5) BIT 183 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL_GPIO_OEN_4 BIT(4) BIT 184 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL_GPIO_I_3 BIT(3) BIT 185 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL_GPIO_OEN_3 BIT(2) BIT 186 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL_GPIO_I_2 BIT(1) BIT 187 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CTRL_GPIO_OEN_2 BIT(0) BIT 200 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CEA_NEW_VSI BIT(2) BIT 201 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CEA_NEW_AVI BIT(1) BIT 205 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CCTRL_TMDS_OE BIT(4) BIT 209 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CTRL4_SCDT_CKDT_SEL BIT(1) BIT 210 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CTRL4_TX_EN_BY_SCDT BIT(0) BIT 214 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RXBIST_VGB_EN BIT(7) BIT 215 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TXBIST_VGB_EN BIT(6) BIT 216 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_BIST_START_SEL BIT(5) BIT 217 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_BIST_START_BIT BIT(4) BIT 218 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_BIST_ALWAYS_ON BIT(3) BIT 219 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_BIST_TRANS BIT(2) BIT 220 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_BIST_RESET BIT(1) BIT 221 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_BIST_EN BIT(0) BIT 245 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_LM_DDC_SW_TPI_EN_DISABLED BIT(7) BIT 247 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_LM_DDC_VIDEO_MUTE_EN BIT(5) BIT 248 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_LM_DDC_DDC_TPI_SW BIT(2) BIT 249 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_LM_DDC_DDC_GRANT BIT(1) BIT 250 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_LM_DDC_DDC_GPU_REQUEST BIT(0) BIT 254 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_MANUAL_MAN_DDC BIT(7) BIT 255 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_MANUAL_VP_SEL BIT(6) BIT 256 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_MANUAL_DSDA BIT(5) BIT 257 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_MANUAL_DSCL BIT(4) BIT 258 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_MANUAL_GCP_HW_CTL_EN BIT(3) BIT 259 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_MANUAL_DDCM_ABORT_WP BIT(2) BIT 260 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_MANUAL_IO_DSDA BIT(1) BIT 261 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_MANUAL_IO_DSCL BIT(0) BIT 282 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_STATUS_DDC_BUS_LOW BIT(6) BIT 283 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_STATUS_DDC_NO_ACK BIT(5) BIT 284 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_STATUS_DDC_I2C_IN_PROG BIT(4) BIT 285 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_STATUS_DDC_FIFO_FULL BIT(3) BIT 286 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_STATUS_DDC_FIFO_EMPTY BIT(2) BIT 287 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_STATUS_DDC_FIFO_READ_IN_SUE BIT(1) BIT 288 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_STATUS_DDC_FIFO_WRITE_IN_USE BIT(0) BIT 292 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_CMD_HDCP_DDC_EN BIT(6) BIT 293 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_CMD_SDA_DEL_EN BIT(5) BIT 294 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_CMD_DDC_FLT_EN BIT(4) BIT 306 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DDC_DOUT_CNT_DDC_DELAY_CNT_8 BIT(7) BIT 314 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TEST_TXCTRL_RCLK_REF_SEL BIT(7) BIT 315 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TEST_TXCTRL_PCLK_REF_SEL BIT(6) BIT 317 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TEST_TXCTRL_HDMI_MODE BIT(1) BIT 318 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TEST_TXCTRL_TST_PLLCK BIT(0) BIT 331 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_UTSRST_FC_SRST BIT(5) BIT 332 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_UTSRST_KEEPER_SRST BIT(4) BIT 333 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_UTSRST_HTX_SRST BIT(3) BIT 334 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_UTSRST_TRX_SRST BIT(2) BIT 335 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_UTSRST_TTX_SRST BIT(1) BIT 336 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_UTSRST_HRX_SRST BIT(0) BIT 341 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HRXCTRL3_HRX_OUT_EN BIT(2) BIT 342 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HRXCTRL3_STATUS_EN BIT(1) BIT 343 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HRXCTRL3_HRX_STAY_RESET BIT(0) BIT 352 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXNUMB_TTX_COM1_AT_SYNC_WAIT BIT(3) BIT 366 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTL_TTX_INTR7 BIT(7) BIT 367 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTL_TTX_INTR6 BIT(6) BIT 368 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTL_TTX_INTR5 BIT(5) BIT 369 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTL_TTX_INTR4 BIT(4) BIT 370 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTL_TTX_INTR3 BIT(3) BIT 371 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTL_TTX_INTR2 BIT(2) BIT 372 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTL_TTX_INTR1 BIT(1) BIT 373 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTL_TTX_INTR0 BIT(0) BIT 377 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTH_TTX_INTR15 BIT(7) BIT 378 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTH_TTX_INTR14 BIT(6) BIT 379 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTH_TTX_INTR13 BIT(5) BIT 380 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTH_TTX_INTR12 BIT(4) BIT 381 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTH_TTX_INTR11 BIT(3) BIT 382 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTH_TTX_INTR10 BIT(2) BIT 383 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTH_TTX_INTR9 BIT(1) BIT 384 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TTXINTH_TTX_INTR8 BIT(0) BIT 388 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TRXCTRL_TRX_CLR_WVALLOW BIT(4) BIT 389 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TRXCTRL_TRX_FROM_SE_COC BIT(3) BIT 411 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TDM_INTR_SYNC_DATA BIT(0) BIT 412 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TDM_INTR_SYNC_WAIT BIT(1) BIT 419 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HTXCTRL_HTX_ALLSBE_SOP BIT(4) BIT 420 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HTXCTRL_HTX_RGDINV_USB BIT(3) BIT 421 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HTXCTRL_HTX_RSPTDM_BUSY BIT(2) BIT 422 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HTXCTRL_HTX_DRVCONN1 BIT(1) BIT 423 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HTXCTRL_HTX_DRVRST1 BIT(0) BIT 439 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_FCGC_HSIC_HOSTMODE BIT(1) BIT 440 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_FCGC_HSIC_ENABLE BIT(0) BIT 469 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TDMLLCTL_TTX_LL_TIE_LOW BIT(1) BIT 470 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TDMLLCTL_TTX_LL_SEL_MODE BIT(0) BIT 479 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CLK_EN_CLK_EN BIT(0) BIT 483 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CH_EN_CH0_EN BIT(4) BIT 484 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CH_EN_CH12_EN BIT(0) BIT 488 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_BGR_BIAS_BGR_EN BIT(7) BIT 496 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_ALICE0_ZONE_CTRL_ICRST_N BIT(7) BIT 497 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_ALICE0_ZONE_CTRL_USE_INT_DIV20 BIT(6) BIT 513 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT BIT(7) BIT 514 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_0_DROP_CEA_CP_PKT BIT(6) BIT 515 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_0_DROP_MPEG_PKT BIT(5) BIT 516 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_0_DROP_SPIF_PKT BIT(4) BIT 517 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_0_DROP_AIF_PKT BIT(3) BIT 518 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_0_DROP_AVI_PKT BIT(2) BIT 519 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_0_DROP_CTS_PKT BIT(1) BIT 520 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_0_DROP_GCP_PKT BIT(0) BIT 524 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS BIT(7) BIT 525 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_1_AVI_OVERRIDE_DIS BIT(6) BIT 526 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_1_DROP_AUDIO_PKT BIT(3) BIT 527 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_1_DROP_GEN2_PKT BIT(2) BIT 528 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_1_DROP_GEN_PKT BIT(1) BIT 529 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_PKT_FILTER_1_DROP_VSIF_PKT BIT(0) BIT 533 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_CLR_MUTE BIT(7) BIT 534 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_SET_MUTE BIT(6) BIT 535 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_NEW_CP BIT(5) BIT 536 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CSTAT_P3_CLR_AVI BIT(3) BIT 537 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS BIT(2) BIT 538 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CSTAT_P3_SCDT BIT(1) BIT 539 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TMDS_CSTAT_P3_CKDT BIT(0) BIT 543 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CTRL0_BYP_DVIFILT_SYNC BIT(5) BIT 544 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CTRL0_HDMI_MODE_EN_ITSELF_CLR BIT(4) BIT 545 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CTRL0_HDMI_MODE_SW_VALUE BIT(3) BIT 546 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CTRL0_HDMI_MODE_OVERWRITE BIT(2) BIT 547 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE_EN BIT(1) BIT 548 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE BIT(0) BIT 554 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CTRL2_USE_AV_MUTE BIT(3) BIT 555 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI BIT(0) BIT 564 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CLR_BUFFER_USE_AIF4VSI BIT(5) BIT 565 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_W_AVI BIT(4) BIT 566 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CLR_BUFFER_VSI_IEEE_ID_CHK_EN BIT(3) BIT 567 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CLR_BUFFER_SWAP_VSI_IEEE_ID BIT(2) BIT 568 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CLR_BUFFER_AIF_CLR_EN BIT(1) BIT 569 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN BIT(0) BIT 582 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_INTR9_EDID_ERROR BIT(6) BIT 583 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_INTR9_EDID_DONE BIT(5) BIT 584 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_INTR9_DEVCAP_DONE BIT(4) BIT 591 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_CBUS_START_RCP_REQ_START BIT(7) BIT 592 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_CBUS_START_RCPK_REPLY_START BIT(6) BIT 593 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_CBUS_START_RCPE_REPLY_START BIT(5) BIT 594 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_CBUS_START_PUT_LINK_MODE_START BIT(4) BIT 595 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_CBUS_START_PUT_DCAPCHG_START BIT(3) BIT 596 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_CBUS_START_PUT_DCAPRDY_START BIT(2) BIT 597 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_CBUS_START_GET_EDID_START_0 BIT(1) BIT 598 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_CBUS_START_GET_DEVCAP_START BIT(0) BIT 602 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EDID_CTRL_EDID_PRIME_VALID BIT(7) BIT 603 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EDID_CTRL_XDEVCAP_EN BIT(6) BIT 604 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP BIT(5) BIT 605 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO BIT(4) BIT 606 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EDID_CTRL_EDID_FIFO_ACCESS_ALWAYS_EN BIT(3) BIT 607 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EDID_CTRL_EDID_FIFO_BLOCK_SEL BIT(2) BIT 608 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EDID_CTRL_INVALID_BKSV BIT(1) BIT 609 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EDID_CTRL_EDID_MODE_EN BIT(0) BIT 628 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_QUARTER_CLK_SEL BIT(6) BIT 629 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_DONE BIT(5) BIT 630 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_ON BIT(4) BIT 631 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_RUN BIT(3) BIT 632 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TX_IP_BIST_CNTLSTA_TXCLK_HALF_SEL BIT(2) BIT 633 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_EN BIT(1) BIT 634 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_SEL BIT(0) BIT 650 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_GENCTL_SPEC_TRANS_DIS BIT(7) BIT 651 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_GENCTL_DIS_XMIT_ERR_STATE BIT(6) BIT 652 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_GENCTL_SPI_MISO_EDGE BIT(5) BIT 653 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_GENCTL_SPI_MOSI_EDGE BIT(4) BIT 654 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_GENCTL_CLR_EMSC_RFIFO BIT(3) BIT 655 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_GENCTL_CLR_EMSC_XFIFO BIT(2) BIT 656 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_GENCTL_START_TRAIN_SEQ BIT(1) BIT 657 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_GENCTL_EMSC_EN BIT(0) BIT 661 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COMMECNT_I2C_TO_EMSC_EN BIT(7) BIT 673 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SPIBURSTSTAT_SPI_HDCPRST BIT(7) BIT 674 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SPIBURSTSTAT_SPI_CBUSRST BIT(6) BIT 675 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SPIBURSTSTAT_SPI_SRST BIT(5) BIT 676 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE BIT(0) BIT 680 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EMSCINTR_EMSC_XFIFO_EMPTY BIT(7) BIT 681 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EMSCINTR_EMSC_XMIT_ACK_TOUT BIT(6) BIT 682 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EMSCINTR_EMSC_RFIFO_READ_ERR BIT(5) BIT 683 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EMSCINTR_EMSC_XFIFO_WRITE_ERR BIT(4) BIT 684 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EMSCINTR_EMSC_COMMA_CHAR_ERR BIT(3) BIT 685 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EMSCINTR_EMSC_XMIT_DONE BIT(2) BIT 686 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EMSCINTR_EMSC_XMIT_GNT_TOUT BIT(1) BIT 687 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EMSCINTR_SPI_DVLD BIT(0) BIT 700 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR BIT(0) BIT 704 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_EMSCINTRMASK1_EMSC_INTRMASK1_0 BIT(0) BIT 708 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_TOP_CTL_MHL3_DOC_SEL BIT(7) BIT 709 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_TOP_CTL_MHL_PP_SEL BIT(6) BIT 714 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL0_DP_OE BIT(7) BIT 715 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL0_TX_OE_OVR BIT(6) BIT 725 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL2_CLK_BYPASS_EN BIT(7) BIT 742 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL5_RSEN_EN_OVR BIT(7) BIT 743 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL5_RSEN_EN BIT(6) BIT 750 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_PLL_CTL0_AUD_CLK_EN BIT(7) BIT 768 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL BIT(1) BIT 769 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_PLL_CTL0_ZONE_MASK_OE BIT(0) BIT 773 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_PLL_CTL2_CLKDETECT_EN BIT(7) BIT 774 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_PLL_CTL2_MEAS_FVCO BIT(3) BIT 775 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_PLL_CTL2_PLL_FAST_LOCK BIT(2) BIT 780 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_CBUS_CTL0_CBUS_RGND_TEST_MODE BIT(7) BIT 805 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_COC_CTL0_COC_BIAS_EN BIT(7) BIT 811 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_COC_CTL1_COC_EN BIT(7) BIT 816 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_COC_CTL3_COC_AECHO_EN BIT(0) BIT 828 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DOC_CTL0_DOC_RXDATA_EN BIT(7) BIT 831 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DOC_CTL0_DOC_RXBIAS_EN BIT(0) BIT 835 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL6_DP_TAP2_SGN BIT(5) BIT 836 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL6_DP_TAP2_EN BIT(4) BIT 837 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL6_DP_TAP1_SGN BIT(3) BIT 838 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL6_DP_TAP1_EN BIT(2) BIT 839 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN BIT(1) BIT 840 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_DP_CTL6_DP_PRE_POST_SEL BIT(0) BIT 855 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL3_TX_ZONE_CTL_MHL2_INTPLT_ZONE_MANU_EN BIT(7) BIT 866 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_POLL_CS_HDCP2X_MSG_SZ_CLR_OPTION BIT(6) BIT 867 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_POLL_CS_HDCP2X_RPT_READY_CLR_OPTION BIT(5) BIT 868 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_POLL_CS_HDCP2X_REAUTH_REQ_CLR_OPTION BIT(4) BIT 870 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_GNT BIT(1) BIT 871 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_EN BIT(0) BIT 881 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_0_HDCP2X_ENCRYPT_EN BIT(7) BIT 882 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_SEL BIT(6) BIT 883 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_OVR BIT(5) BIT 884 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_0_HDCP2X_PRECOMPUTE BIT(4) BIT 885 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_0_HDCP2X_HDMIMODE BIT(3) BIT 886 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_0_HDCP2X_REPEATER BIT(2) BIT 887 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX BIT(1) BIT 888 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_0_HDCP2X_EN BIT(0) BIT 893 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_SW BIT(3) BIT 894 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_OVR BIT(2) BIT 895 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_1_HDCP2X_CTL3MSK BIT(1) BIT 896 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_CTRL_1_HDCP2X_REAUTH_SW BIT(0) BIT 900 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_XFER_START BIT(4) BIT 901 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR_START BIT(3) BIT 902 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR BIT(2) BIT 903 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD_START BIT(1) BIT 904 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD BIT(0) BIT 934 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_CTRL_H2M_SWRST BIT(4) BIT 935 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_CTRL_SW_MHL3_SEL BIT(3) BIT 936 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_CTRL_M3AV_EN BIT(2) BIT 937 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_CTRL_ENC_TMDS BIT(1) BIT 938 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_CTRL_MHL3_MASTER_EN BIT(0) BIT 949 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_P0CTRL_MHL3_P0_HDCP_ENC_EN BIT(4) BIT 950 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN BIT(3) BIT 951 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_P0CTRL_MHL3_P0_HDCP_EN BIT(2) BIT 952 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED BIT(1) BIT 953 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_P0CTRL_MHL3_P0_PORT_EN BIT(0) BIT 962 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_M3_SCTRL_MHL3_SCRAMBLER_EN BIT(0) BIT 1001 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INPUT_EXTENDEDBITMODE BIT(7) BIT 1002 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INPUT_ENDITHER BIT(6) BIT 1008 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_OUTPUT_CSCMODE709 BIT(4) BIT 1017 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_SC_TPI_UPDATE_FLG BIT(7) BIT 1018 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_SC_TPI_REAUTH_CTL BIT(6) BIT 1019 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_SC_TPI_OUTPUT_MODE_1 BIT(5) BIT 1020 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN BIT(4) BIT 1021 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_SC_TPI_AV_MUTE BIT(3) BIT 1022 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_SC_DDC_GPU_REQUEST BIT(2) BIT 1023 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_SC_DDC_TPI_SW BIT(1) BIT 1024 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI BIT(0) BIT 1028 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA1_COPP_GPROT BIT(7) BIT 1029 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA1_COPP_LPROT BIT(6) BIT 1035 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA1_COPP_HDCP_REP BIT(3) BIT 1036 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_0 BIT(2) BIT 1037 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA1_COPP_PROTYPE BIT(1) BIT 1038 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_1 BIT(0) BIT 1042 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA2_INTR_ENCRYPTION BIT(5) BIT 1043 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA2_KSV_FORWARD BIT(4) BIT 1044 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA2_INTERM_RI_CHECK_EN BIT(3) BIT 1045 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA2_DOUBLE_RI_CHECK BIT(2) BIT 1046 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA2_DDC_SHORT_RI_RD BIT(1) BIT 1047 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_COPP_DATA2_COPP_PROTLEVEL BIT(0) BIT 1054 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INTR_ST0_TPI_AUTH_CHNGE_STAT BIT(7) BIT 1055 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INTR_ST0_TPI_V_RDY_STAT BIT(6) BIT 1056 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INTR_ST0_TPI_COPP_CHNGE_STAT BIT(5) BIT 1057 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INTR_ST0_KSV_FIFO_FIRST_STAT BIT(3) BIT 1058 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_DONE_STAT BIT(2) BIT 1059 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_ERR_STAT BIT(1) BIT 1060 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INTR_ST0_READ_BKSV_ERR_STAT BIT(0) BIT 1067 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_BSTATUS1_DS_DEV_EXCEED BIT(7) BIT 1073 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_BSTATUS2_DS_HDMI_MODE BIT(4) BIT 1074 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_BSTATUS2_DS_CASC_EXCEED BIT(3) BIT 1079 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_HW_OPT3_DDC_DEBUG BIT(7) BIT 1080 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_HW_OPT3_RI_CHECK_SKIP BIT(3) BIT 1081 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_HW_OPT3_TPI_DDC_BURST_MODE BIT(2) BIT 1086 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INFO_FSEL_EN BIT(7) BIT 1087 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INFO_FSEL_RPT BIT(6) BIT 1088 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_TPI_INFO_FSEL_READ_FLAG BIT(5) BIT 1103 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_STAT_0_PLL_LOCKED BIT(7) BIT 1127 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_CTL3_COC_CTRL3_7 BIT(7) BIT 1132 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_CTL6_COC_CTRL6_7 BIT(7) BIT 1133 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_CTL6_COC_CTRL6_6 BIT(6) BIT 1138 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_CTL7_COC_CTRL7_7 BIT(7) BIT 1139 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_CTL7_COC_CTRL7_6 BIT(6) BIT 1140 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_CTL7_COC_CTRL7_5 BIT(5) BIT 1158 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_CTLD_COC_CTRLD_7 BIT(7) BIT 1163 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_CTLE_COC_CTRLE_7 BIT(7) BIT 1183 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_CTL15_COC_CTRL15_7 BIT(7) BIT 1192 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_PLL_LOCK_STATUS_CHANGE BIT(0) BIT 1193 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_CALIBRATION_DONE BIT(1) BIT 1197 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_COC_MISC_CTL0_FSM_MON BIT(7) BIT 1234 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DOC_CTL6_DOC_CTRL6_7 BIT(7) BIT 1235 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DOC_CTL6_DOC_CTRL6_6 BIT(6) BIT 1241 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DOC_CTL7_DOC_CTRL7_7 BIT(7) BIT 1242 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DOC_CTL7_DOC_CTRL7_6 BIT(6) BIT 1243 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DOC_CTL7_DOC_CTRL7_5 BIT(5) BIT 1249 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DOC_CTL8_DOC_CTRL8_7 BIT(7) BIT 1262 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DOC_CTLE_DOC_CTRLE_7 BIT(7) BIT 1263 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DOC_CTLE_DOC_CTRLE_6 BIT(6) BIT 1287 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RCV_CTRL_MDT_RCV_EN BIT(7) BIT 1288 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN BIT(6) BIT 1289 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN BIT(4) BIT 1290 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RCV_CTRL_MDT_XFIFO_OVER_WR_EN BIT(3) BIT 1291 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RCV_CTRL_MDT_DISABLE BIT(2) BIT 1292 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL BIT(1) BIT 1293 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR BIT(0) BIT 1300 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_CTRL_EN BIT(7) BIT 1301 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_CTRL_CMD_MERGE_EN BIT(6) BIT 1302 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN BIT(5) BIT 1303 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_CTRL_FIXED_AID BIT(4) BIT 1304 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_CTRL_SINGLE_RUN_EN BIT(3) BIT 1305 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_CTRL_CLR_ABORT_WAIT BIT(2) BIT 1306 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_ALL BIT(1) BIT 1307 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_CUR BIT(0) BIT 1320 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XFIFO_STAT_MDT_XMIT_PRE_HS_EN BIT(4) BIT 1325 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RFIFO_DATA_RDY BIT(0) BIT 1326 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_IDLE_AFTER_HAWB_DISABLE BIT(2) BIT 1327 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XFIFO_EMPTY BIT(3) BIT 1334 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RCV_TIMEOUT BIT(0) BIT 1335 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RCV_SM_ABORT_PKT_RCVD BIT(1) BIT 1336 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_RCV_SM_ERROR BIT(2) BIT 1337 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_TIMEOUT BIT(5) BIT 1338 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_SM_ABORT_PKT_RCVD BIT(6) BIT 1339 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MDT_XMIT_SM_ERROR BIT(7) BIT 1349 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_STATUS_MHL_CABLE_PRESENT BIT(4) BIT 1350 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_STATUS_MSC_HB_SUCCESS BIT(3) BIT 1351 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_STATUS_CBUS_HPD BIT(2) BIT 1352 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_STATUS_MHL_MODE BIT(1) BIT 1353 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_STATUS_CBUS_CONNECTED BIT(0) BIT 1357 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_MT_DONE_NACK BIT(7) BIT 1358 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_MR_SET_INT BIT(6) BIT 1359 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_MR_WRITE_BURST BIT(5) BIT 1360 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_MR_MSC_MSG BIT(4) BIT 1361 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_MR_WRITE_STAT BIT(3) BIT 1362 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_HPD_CHG BIT(2) BIT 1363 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_MT_DONE BIT(1) BIT 1364 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_CNX_CHG BIT(0) BIT 1371 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_CMD_ABORT BIT(6) BIT 1372 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_ABORT_RCVD BIT(3) BIT 1373 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_DDC_ABORT BIT(2) BIT 1374 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_CEC_ABORT BIT(1) BIT 1413 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MSC_COMMAND_START_DEBUG BIT(5) BIT 1414 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MSC_COMMAND_START_WRITE_BURST BIT(4) BIT 1415 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MSC_COMMAND_START_WRITE_STAT BIT(3) BIT 1416 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MSC_COMMAND_START_READ_DEVCAP BIT(2) BIT 1417 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MSC_COMMAND_START_MSC_MSG BIT(1) BIT 1418 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MSC_COMMAND_START_PEER BIT(0) BIT 1437 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MSC_HEARTBEAT_CTRL_MSC_HB_EN BIT(7) BIT 1443 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN BIT(7) BIT 1444 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_MSC_ON_CBUS BIT(6) BIT 1445 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS BIT(5) BIT 1446 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_DDC_ERRORCODE BIT(3) BIT 1447 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_VS1_ERRORCODE BIT(2) BIT 1453 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS3_CNVT_TEARCBUS_EN BIT(1) BIT 1454 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS3_CNVT_CBUS3CNVT_EN BIT(0) BIT 1458 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL1_CBUS_INTR_EN BIT(7) BIT 1459 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL1_HB_ONLY BIT(6) BIT 1462 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL1_DISC_EN BIT(0) BIT 1476 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL5_DSM_OVRIDE BIT(3) BIT 1481 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL8_NOMHLINT_CLR_BYPASS BIT(7) BIT 1482 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL8_DELAY_CBUS_INTR_EN BIT(0) BIT 1486 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL9_MHL3_RSEN_BYP BIT(7) BIT 1487 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL9_MHL3DISC_EN BIT(6) BIT 1488 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL9_WAKE_DRVFLT BIT(4) BIT 1489 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL9_NOMHL_EST BIT(3) BIT 1490 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL9_DISC_PULSE_PROCEED BIT(2) BIT 1491 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL9_WAKE_PULSE_BYPASS BIT(1) BIT 1492 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_CTRL9_VBUS_OUTPUT_CAPABILITY_SRC BIT(0) BIT 1496 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_STAT1_PSM_OVRIDE BIT(5) BIT 1501 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_STAT2_CBUS_OE_POL BIT(6) BIT 1502 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_STAT2_CBUS_SATUS BIT(5) BIT 1503 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_DISC_STAT2_RSEN BIT(4) BIT 1519 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_RGND_READY_INT BIT(6) BIT 1520 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MHL12_DISCON_INT BIT(5) BIT 1521 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_CBUS_MHL3_DISCON_INT BIT(4) BIT 1522 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_NOT_MHL_EST_INT BIT(3) BIT 1523 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL_EST_INT BIT(2) BIT 1524 drivers/gpu/drm/bridge/sil-sii8620.h #define BIT_MHL3_EST_INT BIT(1) BIT 27 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_AHB_DMA_CONF0_SW_FIFO_RST = BIT(7), BIT 28 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_AHB_DMA_CONF0_EN_HLOCK = BIT(3), BIT 29 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_AHB_DMA_START_START = BIT(0), BIT 30 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_AHB_DMA_STOP_STOP = BIT(0), BIT 31 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = BIT(5), BIT 32 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = BIT(4), BIT 33 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = BIT(3), BIT 34 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = BIT(2), BIT 35 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = BIT(1), BIT 36 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0), BIT 44 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_AHBDMAAUD_STAT0_ERROR = BIT(5), BIT 45 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_AHBDMAAUD_STAT0_LOST = BIT(4), BIT 46 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_AHBDMAAUD_STAT0_RETRY = BIT(3), BIT 47 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_AHBDMAAUD_STAT0_DONE = BIT(2), BIT 48 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = BIT(1), BIT 49 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0), BIT 60 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_AHB_DMA_CONF0_BURST_MODE = BIT(0), BIT 61 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c HDMI_AHB_DMA_MASK_DONE = BIT(7), BIT 230 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c dw->cs[0][0] |= BIT(4); BIT 26 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c CEC_CTRL_START = BIT(0), BIT 33 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c CEC_STAT_DONE = BIT(0), BIT 34 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c CEC_STAT_EOM = BIT(1), BIT 35 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c CEC_STAT_NACK = BIT(2), BIT 36 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c CEC_STAT_ARBLOST = BIT(3), BIT 37 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c CEC_STAT_ERROR_INIT = BIT(4), BIT 38 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c CEC_STAT_ERROR_FOLL = BIT(5), BIT 39 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c CEC_STAT_WAKEUP = BIT(6), BIT 84 drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c cec->addresses |= BIT(logical_addr) | BIT(15); BIT 1095 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE BIT(15) BIT 1098 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_MSM_CTRL_MPLL_PH_SEL_CK BIT(13) BIT 1103 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_MSM_CTRL_SCOPE_CK_SEL BIT(0) BIT 1106 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_PTRPT_ENBL_OVERRIDE BIT(15) BIT 1107 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT2 BIT(8) BIT 1108 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT1 BIT(7) BIT 1109 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT0 BIT(6) BIT 1110 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_PTRPT_ENBL_CK_REF_ENB BIT(5) BIT 1111 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_PTRPT_ENBL_RCAL_ENB BIT(4) BIT 1112 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_CLK_ALIGN_ENB BIT(3) BIT 1113 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_PTRPT_ENBL_TX_READY BIT(2) BIT 1114 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_PTRPT_ENBL_CKO_WORD_ENB BIT(1) BIT 1115 drivers/gpu/drm/bridge/synopsys/dw-hdmi.h #define HDMI_3D_TX_PHY_PTRPT_ENBL_REFCLK_ENB BIT(0) BIT 39 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define POWERUP BIT(0) BIT 49 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define LOOSELY18_EN BIT(8) BIT 58 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define COLORM_ACTIVE_LOW BIT(4) BIT 59 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define SHUTD_ACTIVE_LOW BIT(3) BIT 60 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define HSYNC_ACTIVE_LOW BIT(2) BIT 61 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define VSYNC_ACTIVE_LOW BIT(1) BIT 62 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define DATAEN_ACTIVE_LOW BIT(0) BIT 74 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define CRC_RX_EN BIT(4) BIT 75 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define ECC_RX_EN BIT(3) BIT 76 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define BTA_EN BIT(2) BIT 77 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define EOTP_RX_EN BIT(1) BIT 78 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define EOTP_TX_EN BIT(0) BIT 84 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define ENABLE_CMD_MODE BIT(0) BIT 93 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define VID_MODE_VPG_ENABLE BIT(16) BIT 94 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define VID_MODE_VPG_HORIZONTAL BIT(24) BIT 115 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define MAX_RD_PKT_SIZE_LP BIT(24) BIT 116 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define DCS_LW_TX_LP BIT(19) BIT 117 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define DCS_SR_0P_TX_LP BIT(18) BIT 118 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define DCS_SW_1P_TX_LP BIT(17) BIT 119 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define DCS_SW_0P_TX_LP BIT(16) BIT 120 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_LW_TX_LP BIT(14) BIT 121 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_SR_2P_TX_LP BIT(13) BIT 122 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_SR_1P_TX_LP BIT(12) BIT 123 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_SR_0P_TX_LP BIT(11) BIT 124 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_SW_2P_TX_LP BIT(10) BIT 125 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_SW_1P_TX_LP BIT(9) BIT 126 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_SW_0P_TX_LP BIT(8) BIT 127 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define ACK_RQST_EN BIT(1) BIT 128 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define TEAR_FX_EN BIT(0) BIT 147 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_RD_CMD_BUSY BIT(6) BIT 148 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_PLD_R_FULL BIT(5) BIT 149 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_PLD_R_EMPTY BIT(4) BIT 150 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_PLD_W_FULL BIT(3) BIT 151 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_PLD_W_EMPTY BIT(2) BIT 152 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_CMD_FULL BIT(1) BIT 153 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define GEN_CMD_EMPTY BIT(0) BIT 166 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define AUTO_CLKLANE_CTRL BIT(1) BIT 167 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define PHY_TXREQUESTCLKHS BIT(0) BIT 182 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define PHY_ENFORCEPLL BIT(3) BIT 184 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define PHY_ENABLECLK BIT(2) BIT 186 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define PHY_UNRSTZ BIT(1) BIT 188 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define PHY_UNSHUTDOWNZ BIT(0) BIT 198 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define PHY_STOP_STATE_CLK_LANE BIT(2) BIT 199 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define PHY_LOCK BIT(0) BIT 202 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define PHY_TESTCLK BIT(1) BIT 204 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define PHY_TESTCLR BIT(0) BIT 208 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define PHY_TESTEN BIT(16) BIT 53 drivers/gpu/drm/bridge/tc358764.c #define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ BIT 54 drivers/gpu/drm/bridge/tc358764.c #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */ BIT 55 drivers/gpu/drm/bridge/tc358764.c #define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ BIT 124 drivers/gpu/drm/bridge/tc358764.c #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */ BIT 125 drivers/gpu/drm/bridge/tc358764.c #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */ BIT 126 drivers/gpu/drm/bridge/tc358764.c #define SYS_RST_LCD BIT(2) /* Reset LCD controller */ BIT 127 drivers/gpu/drm/bridge/tc358764.c #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */ BIT 128 drivers/gpu/drm/bridge/tc358764.c #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */ BIT 129 drivers/gpu/drm/bridge/tc358764.c #define SYS_RST_REG BIT(5) /* Reset Register module */ BIT 136 drivers/gpu/drm/bridge/tc358764.c #define LANEENABLE_CLEN BIT(0) BIT 137 drivers/gpu/drm/bridge/tc358764.c #define LANEENABLE_L0EN BIT(1) BIT 138 drivers/gpu/drm/bridge/tc358764.c #define LANEENABLE_L1EN BIT(2) BIT 139 drivers/gpu/drm/bridge/tc358764.c #define LANEENABLE_L2EN BIT(3) BIT 140 drivers/gpu/drm/bridge/tc358764.c #define LANEENABLE_L3EN BIT(4) BIT 143 drivers/gpu/drm/bridge/tc358764.c #define LV_CFG_LVEN BIT(0) BIT 144 drivers/gpu/drm/bridge/tc358764.c #define LV_CFG_LVDLINK BIT(1) BIT 145 drivers/gpu/drm/bridge/tc358764.c #define LV_CFG_CLKPOL1 BIT(2) BIT 146 drivers/gpu/drm/bridge/tc358764.c #define LV_CFG_CLKPOL2 BIT(3) BIT 71 drivers/gpu/drm/bridge/tc358767.c #define VFUEN BIT(0) /* Video Frame Timing Upload */ BIT 97 drivers/gpu/drm/bridge/tc358767.c #define INT_SYSERR BIT(16) BIT 106 drivers/gpu/drm/bridge/tc358767.c #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */ BIT 107 drivers/gpu/drm/bridge/tc358767.c #define EF_EN BIT(5) /* Enable Enhanced Framing */ BIT 108 drivers/gpu/drm/bridge/tc358767.c #define VID_EN BIT(1) /* Video transmission enable */ BIT 109 drivers/gpu/drm/bridge/tc358767.c #define DP_EN BIT(0) /* Enable DPTX function */ BIT 147 drivers/gpu/drm/bridge/tc358767.c #define DP0_AUXCFG0_ADDR_ONLY BIT(4) BIT 149 drivers/gpu/drm/bridge/tc358767.c #define AUX_RX_FILTER_EN BIT(16) BIT 157 drivers/gpu/drm/bridge/tc358767.c #define AUX_TIMEOUT BIT(1) BIT 158 drivers/gpu/drm/bridge/tc358767.c #define AUX_BUSY BIT(0) BIT 163 drivers/gpu/drm/bridge/tc358767.c #define DP0_SRCCTRL_SCRMBLDIS BIT(13) BIT 164 drivers/gpu/drm/bridge/tc358767.c #define DP0_SRCCTRL_EN810B BIT(12) BIT 168 drivers/gpu/drm/bridge/tc358767.c #define DP0_SRCCTRL_LANESKEW BIT(7) BIT 169 drivers/gpu/drm/bridge/tc358767.c #define DP0_SRCCTRL_SSCG BIT(3) BIT 174 drivers/gpu/drm/bridge/tc358767.c #define DP0_SRCCTRL_AUTOCORRECT BIT(0) BIT 176 drivers/gpu/drm/bridge/tc358767.c #define LT_LOOPDONE BIT(13) BIT 179 drivers/gpu/drm/bridge/tc358767.c #define LT_INTERLANE_ALIGN_DONE BIT(3) BIT 189 drivers/gpu/drm/bridge/tc358767.c #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ BIT 190 drivers/gpu/drm/bridge/tc358767.c #define BGREN BIT(25) /* AUX PHY BGR Enable */ BIT 191 drivers/gpu/drm/bridge/tc358767.c #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */ BIT 192 drivers/gpu/drm/bridge/tc358767.c #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ BIT 193 drivers/gpu/drm/bridge/tc358767.c #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ BIT 194 drivers/gpu/drm/bridge/tc358767.c #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ BIT 195 drivers/gpu/drm/bridge/tc358767.c #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */ BIT 196 drivers/gpu/drm/bridge/tc358767.c #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ BIT 197 drivers/gpu/drm/bridge/tc358767.c #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ BIT 203 drivers/gpu/drm/bridge/tc358767.c #define PLLUPDATE BIT(2) BIT 204 drivers/gpu/drm/bridge/tc358767.c #define PLLBYP BIT(1) BIT 205 drivers/gpu/drm/bridge/tc358767.c #define PLLEN BIT(0) BIT 222 drivers/gpu/drm/bridge/tc358767.c #define ENI2CFILTER BIT(4) BIT 1369 drivers/gpu/drm/bridge/tc358767.c conn = val & BIT(tc->hpd_pin); BIT 1634 drivers/gpu/drm/bridge/tc358767.c regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); BIT 29 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define DPPLL_CLK_SRC_DSICLK BIT(0) BIT 32 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define DPPLL_SRC_DP_PLL_LOCK BIT(7) BIT 42 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define CHA_HSYNC_POLARITY BIT(7) BIT 45 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define CHA_VSYNC_POLARITY BIT(7) BIT 51 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define VSTREAM_ENABLE BIT(3) BIT 54 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define HPD_DISABLE BIT(0) BIT 61 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define AUX_CMD_SEND BIT(0) BIT 72 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define ML_TX_NORMAL_MODE BIT(0) BIT 74 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) BIT 75 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define AUX_IRQ_STATUS_AUX_SHORT BIT(5) BIT 76 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) BIT 695 drivers/gpu/drm/drm_atomic_helper.c connectors_mask |= BIT(i); BIT 729 drivers/gpu/drm/drm_atomic_helper.c if (connectors_mask & BIT(i)) BIT 1615 drivers/gpu/drm/drm_atomic_helper.c new_self_refresh_mask |= BIT(i); BIT 311 drivers/gpu/drm/drm_blend.c BIT((ffs(rotation & DRM_MODE_ROTATE_MASK) + 1) BIT 562 drivers/gpu/drm/drm_blend.c unsigned int valid_mode_mask = BIT(DRM_MODE_BLEND_PIXEL_NONE) | BIT 563 drivers/gpu/drm/drm_blend.c BIT(DRM_MODE_BLEND_PREMULTI) | BIT 564 drivers/gpu/drm/drm_blend.c BIT(DRM_MODE_BLEND_COVERAGE); BIT 568 drivers/gpu/drm/drm_blend.c ((supported_modes & BIT(DRM_MODE_BLEND_PREMULTI)) == 0))) BIT 580 drivers/gpu/drm/drm_blend.c if (!(BIT(props[i].type) & supported_modes)) BIT 545 drivers/gpu/drm/drm_client_modeset.c if (conn_configured & BIT(i)) BIT 557 drivers/gpu/drm/drm_client_modeset.c conn_configured |= BIT(i); BIT 576 drivers/gpu/drm/drm_client_modeset.c conn_configured |= BIT(i); BIT 645 drivers/gpu/drm/drm_client_modeset.c conn_configured |= BIT(i); BIT 419 drivers/gpu/drm/drm_color_mgmt.c (supported_encodings & -BIT(DRM_COLOR_ENCODING_MAX)) != 0 || BIT 420 drivers/gpu/drm/drm_color_mgmt.c (supported_encodings & BIT(default_encoding)) == 0)) BIT 424 drivers/gpu/drm/drm_color_mgmt.c (supported_ranges & -BIT(DRM_COLOR_RANGE_MAX)) != 0 || BIT 425 drivers/gpu/drm/drm_color_mgmt.c (supported_ranges & BIT(default_range)) == 0)) BIT 430 drivers/gpu/drm/drm_color_mgmt.c if ((supported_encodings & BIT(i)) == 0) BIT 449 drivers/gpu/drm/drm_color_mgmt.c if ((supported_ranges & BIT(i)) == 0) BIT 1623 drivers/gpu/drm/drm_connector.c if (!(BIT(i) & scaling_mode_mask)) BIT 1256 drivers/gpu/drm/drm_dp_helper.c { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, BIT 1258 drivers/gpu/drm/drm_dp_helper.c { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, BIT 1260 drivers/gpu/drm/drm_dp_helper.c { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }, BIT 1262 drivers/gpu/drm/drm_dp_helper.c { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, BIT 3954 drivers/gpu/drm/drm_edid.c (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | BIT 3955 drivers/gpu/drm/drm_edid.c BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | BIT 3956 drivers/gpu/drm/drm_edid.c BIT(HDMI_EOTF_SMPTE_ST2084) | BIT 3957 drivers/gpu/drm/drm_edid.c BIT(HDMI_EOTF_BT_2100_HLG)); BIT 3963 drivers/gpu/drm/drm_edid.c BIT(HDMI_STATIC_METADATA_TYPE1); BIT 5005 drivers/gpu/drm/drm_edid.c return sink_eotf & BIT(output_eotf); BIT 32 drivers/gpu/drm/drm_mipi_dbi.c #define DCS_POWER_MODE_DISPLAY BIT(2) BIT 33 drivers/gpu/drm/drm_mipi_dbi.c #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3) BIT 34 drivers/gpu/drm/drm_mipi_dbi.c #define DCS_POWER_MODE_SLEEP_MODE BIT(4) BIT 35 drivers/gpu/drm/drm_mipi_dbi.c #define DCS_POWER_MODE_PARTIAL_MODE BIT(5) BIT 36 drivers/gpu/drm/drm_mipi_dbi.c #define DCS_POWER_MODE_IDLE_MODE BIT(6) BIT 37 drivers/gpu/drm/drm_mipi_dbi.c #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7)) BIT 829 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = carry | BIT(8 - i) | (val >> i); BIT 833 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = carry | BIT(8 - i) | (val >> i); BIT 841 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = carry | BIT(8 - i) | (val >> i); BIT 852 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = BIT(7) | (src[1] >> 1); BIT 853 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2); BIT 854 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3); BIT 855 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4); BIT 856 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5); BIT 857 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6); BIT 858 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7); BIT 859 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[7] << 1) | BIT(0); BIT 862 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = BIT(7) | (src[0] >> 1); BIT 863 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2); BIT 864 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3); BIT 865 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4); BIT 866 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5); BIT 867 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6); BIT 868 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7); BIT 869 drivers/gpu/drm/drm_mipi_dbi.c *dst++ = (src[6] << 1) | BIT(0); BIT 1024 drivers/gpu/drm/drm_mipi_dbi.c data[i] = (buf[i] << 1) | !!(buf[i + 1] & BIT(7)); BIT 154 drivers/gpu/drm/drm_self_refresh_helper.c bool new_self_refresh_active = new_self_refresh_mask & BIT(i); BIT 585 drivers/gpu/drm/etnaviv/etnaviv_gpu.c pmc |= BIT(15); /* Unknown bit */ BIT 637 drivers/gpu/drm/etnaviv/etnaviv_gpu.c pulse_eater |= BIT(23); BIT 643 drivers/gpu/drm/etnaviv/etnaviv_gpu.c pulse_eater &= ~BIT(16); BIT 644 drivers/gpu/drm/etnaviv/etnaviv_gpu.c pulse_eater |= BIT(17); BIT 652 drivers/gpu/drm/etnaviv/etnaviv_gpu.c pulse_eater |= BIT(18); BIT 19 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c #define MMUv2_PTE_PRESENT BIT(0) BIT 20 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c #define MMUv2_PTE_EXCEPTION BIT(1) BIT 21 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c #define MMUv2_PTE_WRITEABLE BIT(2) BIT 31 drivers/gpu/drm/exynos/exynos5433_drm_decon.c #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13) BIT 176 drivers/gpu/drm/exynos/exynos_drm_drv.c #define DRM_COMPONENT_DRIVER BIT(0) /* supports component framework */ BIT 177 drivers/gpu/drm/exynos/exynos_drm_drv.c #define DRM_VIRTUAL_DEVICE BIT(1) /* create virtual platform device */ BIT 178 drivers/gpu/drm/exynos/exynos_drm_drv.c #define DRM_FIMC_DEVICE BIT(2) /* devices shared with V4L2 subsystem */ BIT 235 drivers/gpu/drm/exynos/exynos_drm_dsi.c #define DSIM_STATE_ENABLED BIT(0) BIT 236 drivers/gpu/drm/exynos/exynos_drm_dsi.c #define DSIM_STATE_INITIALIZED BIT(1) BIT 237 drivers/gpu/drm/exynos/exynos_drm_dsi.c #define DSIM_STATE_CMD_LPM BIT(2) BIT 238 drivers/gpu/drm/exynos/exynos_drm_dsi.c #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) BIT 681 drivers/gpu/drm/exynos/exynos_drm_dsi.c | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) BIT 853 drivers/gpu/drm/exynos/exynos_drm_dsi.c lanes_mask = BIT(dsi->lanes) - 1; BIT 1319 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); BIT 1213 drivers/gpu/drm/exynos/exynos_drm_fimc.c if (id >= 0 && (BIT(id) & fimc_mask)) BIT 299 drivers/gpu/drm/exynos/exynos_drm_plane.c unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) | BIT 300 drivers/gpu/drm/exynos/exynos_drm_plane.c BIT(DRM_MODE_BLEND_PREMULTI) | BIT 301 drivers/gpu/drm/exynos/exynos_drm_plane.c BIT(DRM_MODE_BLEND_COVERAGE); BIT 603 drivers/gpu/drm/exynos/regs-hdmi.h #define PMU_HDMI_PHY_ENABLE_BIT BIT(0) BIT 19 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_MODE_RASTER_EN BIT(14) BIT 48 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_SYN_POL_INV_PXCK BIT(6) BIT 49 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_SYN_POL_NEG BIT(5) BIT 50 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_SYN_POL_INV_VS_LOW BIT(1) BIT 51 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_SYN_POL_INV_HS_LOW BIT(0) BIT 62 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_VSYNC BIT(0) BIT 63 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_UNDRUN BIT(1) BIT 64 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_LSBFVS BIT(2) BIT 65 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_VBLANK BIT(3) BIT 66 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_CRCREADY BIT(4) BIT 67 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_CRCOVERFLOW BIT(5) BIT 68 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P1FIFOLO BIT(6) BIT 69 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P1FIFOHI BIT(7) BIT 70 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P2FIFOLO BIT(8) BIT 71 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P2FIFOHI BIT(9) BIT 72 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_PROGEND BIT(10) BIT 73 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_IPMERROR BIT(11) BIT 74 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_LYRTRANS BIT(12) BIT 75 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_DMATRANS BIT(14) BIT 76 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P3FIFOLO BIT(16) BIT 77 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P3FIFOHI BIT(17) BIT 78 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P4FIFOLO BIT(18) BIT 79 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P4FIFOHI BIT(19) BIT 80 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P1EMPTY BIT(26) BIT 81 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P2EMPTY BIT(27) BIT 82 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P3EMPTY BIT(28) BIT 83 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_STATUS_P4EMPTY BIT(29) BIT 86 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_VSYNC BIT(0) BIT 87 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_UNDRUN BIT(1) BIT 88 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_LSBFVS BIT(2) BIT 89 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_VBLANK BIT(3) BIT 90 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_CRCREADY BIT(4) BIT 91 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_CRCOVERFLOW BIT(5) BIT 92 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P1FIFOLO BIT(6) BIT 93 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P1FIFOHI BIT(7) BIT 94 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P2FIFOLO BIT(8) BIT 95 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P2FIFOHI BIT(9) BIT 96 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_PROGEND BIT(10) BIT 97 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_IPMERROR BIT(11) BIT 98 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_LYRTRANS BIT(12) BIT 99 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_DMATRANS BIT(14) BIT 100 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P3FIFOLO BIT(16) BIT 101 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P3FIFOHI BIT(17) BIT 102 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P4FIFOLO BIT(18) BIT 103 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P4FIFOHI BIT(19) BIT 104 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P1EMPTY BIT(26) BIT 105 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P2EMPTY BIT(27) BIT 106 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P3EMPTY BIT(28) BIT 107 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_INT_MASK_P4EMPTY BIT(29) BIT 112 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_UPDATE_MODE_MODE BIT(31) BIT 113 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_UPDATE_MODE_READREG BIT(30) BIT 125 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_LAYER_EN BIT(31) BIT 126 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_LAYER_TILE_EN BIT(30) BIT 127 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_LAYER_DATA_SEL_CLUT BIT(29) BIT 128 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_LAYER_SAFETY_EN BIT(28) BIT 131 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_LAYER_RLE_EN BIT(15) BIT 133 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_LAYER_BB_ON BIT(2) BIT 16 drivers/gpu/drm/fsl-dcu/fsl_tcon.h #define FSL_TCON_CTRL1_TCON_BYPASS BIT(29) BIT 136 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_WRITE(pipeconf_reg, BIT(31)); BIT 658 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(MIPI_PORT_CONTROL(pipe)) | BIT(31)); BIT 675 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(MIPI_PORT_CONTROL(pipe)) & ~BIT(31)); BIT 151 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_INTR_STATE_RXSOTERROR BIT(0) BIT 153 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_INTR_STATE_SPL_PKG_SENT BIT(30) BIT 154 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_INTR_STATE_TE BIT(31) BIT 190 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_HS_DATA_FULL BIT(0) BIT 191 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_HS_DATA_HALF_EMPTY BIT(1) BIT 192 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_HS_DATA_EMPTY BIT(2) BIT 193 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_LP_DATA_FULL BIT(8) BIT 194 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_LP_DATA_HALF_EMPTY BIT(9) BIT 195 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_LP_DATA_EMPTY BIT(10) BIT 196 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_HS_CTRL_FULL BIT(16) BIT 197 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY BIT(17) BIT 198 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_HS_CTRL_EMPTY BIT(18) BIT 199 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_LP_CTRL_FULL BIT(24) BIT 200 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY BIT(25) BIT 201 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_GEN_LP_CTRL_EMPTY BIT(26) BIT 202 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_DBI_EMPTY BIT(27) BIT 203 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_FIFO_DPI_EMPTY BIT(28) BIT 214 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_POWER_MODE_DISPLAY_ON BIT(2) BIT 215 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_POWER_MODE_NORMAL_ON BIT(3) BIT 216 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_POWER_MODE_SLEEP_OUT BIT(4) BIT 217 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_POWER_MODE_PARTIAL_ON BIT(5) BIT 218 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_POWER_MODE_IDLE_ON BIT(6) BIT 226 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_DPI_COMPLETE_LAST_LINE BIT(2) BIT 227 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define DSI_DPI_DISABLE_BTA BIT(3) BIT 100 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c return wait_for_gen_fifo_empty(sender, (BIT(2) | BIT(10) | BIT(18) | BIT 101 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c BIT(26) | BIT(27) | BIT(28))); BIT 106 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c return wait_for_gen_fifo_empty(sender, (BIT(10) | BIT(26))); BIT 111 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c return wait_for_gen_fifo_empty(sender, (BIT(2) | BIT(18))); BIT 122 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(0): BIT 123 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(1): BIT 124 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(2): BIT 125 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(3): BIT 126 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(4): BIT 127 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(5): BIT 128 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(6): BIT 129 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(7): BIT 130 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(8): BIT 131 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(9): BIT 132 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(10): BIT 133 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(11): BIT 134 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(12): BIT 135 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(13): BIT 138 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(14): BIT 142 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(15): BIT 145 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(16): BIT 147 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(17): BIT 149 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(18): BIT 150 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(19): BIT 158 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(20): BIT 161 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(21): BIT 165 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(22): BIT 167 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(23): BIT 168 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(24): BIT 169 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(25): BIT 170 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(26): BIT 171 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(27): BIT 176 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(28): BIT 181 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(29): BIT 182 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(30): BIT 183 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c case BIT(31): BIT 545 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c REG_WRITE(sender->mipi_intr_stat_reg, BIT(29)); BIT 547 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c if ((REG_READ(sender->mipi_intr_stat_reg) & BIT(29))) BIT 554 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c while (retry && !(REG_READ(sender->mipi_intr_stat_reg) & BIT(29))) { BIT 564 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c REG_WRITE(sender->mipi_intr_stat_reg, BIT(29)); BIT 376 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)); BIT 378 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)); BIT 379 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c tc35876x_regw(i2c, PPI_STARTPPI, BIT(0)); BIT 380 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c tc35876x_regw(i2c, DSI_STARTDSI, BIT(0)); BIT 387 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c tc35876x_regw(i2c, VPCTRL, BIT(8) | BIT(5)); BIT 402 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c tc35876x_regw(i2c, VFUEN, BIT(0)); BIT 405 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c tc35876x_regw(i2c, SYSRST, BIT(2)); BIT 424 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c tc35876x_regw(i2c, LVCFG, BIT(0)); BIT 435 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c if ((BIT(0) | BIT(2)) & val) BIT 10 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h #define MASK(x) (BIT(x) - 1) BIT 17 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h #define POWERUP BIT(0) BIT 21 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h #define PHY_ENABLECLK BIT(2) BIT 22 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h #define PHY_UNRSTZ BIT(1) BIT 23 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h #define PHY_UNSHUTDOWNZ BIT(0) BIT 60 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h #define PHY_TXREQUESTCLKHS BIT(0) BIT 13 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define MASK(x) (BIT(x) - 1) BIT 19 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define AUTO_CLK_GATE_EN BIT(0) BIT 78 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define FLAG_NVSYNC BIT(0) BIT 79 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define FLAG_NHSYNC BIT(1) BIT 80 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define FLAG_NPIXCLK BIT(2) BIT 81 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define FLAG_NDE BIT(3) BIT 88 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define DATA_GATE_EN BIT(2) BIT 89 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define LDI_EN BIT(0) BIT 101 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define SOCKET_QOS_EN BIT(0) BIT 113 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c return !!(BIT(bit_ofst) & tmp); BIT 316 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c if (status & BIT(FRAME_END_INT_EN_OFST)) { BIT 683 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) | BIT 25 drivers/gpu/drm/i2c/tda9950.c CSR_BUSY = BIT(7), BIT 26 drivers/gpu/drm/i2c/tda9950.c CSR_INT = BIT(6), BIT 27 drivers/gpu/drm/i2c/tda9950.c CSR_ERR = BIT(5), BIT 34 drivers/gpu/drm/i2c/tda9950.c CCR_RESET = BIT(7), BIT 35 drivers/gpu/drm/i2c/tda9950.c CCR_ON = BIT(6), BIT 41 drivers/gpu/drm/i2c/tda9950.c CCONR_ENABLE_ERROR = BIT(4), BIT 242 drivers/gpu/drm/i2c/tda9950.c addresses = priv->addresses |= BIT(addr); BIT 128 drivers/gpu/drm/i2c/tda998x_drv.c # define FEAT_POWERDOWN_PREFILT BIT(0) BIT 129 drivers/gpu/drm/i2c/tda998x_drv.c # define FEAT_POWERDOWN_CSC BIT(1) BIT 369 drivers/gpu/drm/i2c/tda998x_drv.c # define CEC_CAL_XOSC_CTRL1_ENA_CAL BIT(0) BIT 371 drivers/gpu/drm/i2c/tda998x_drv.c # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7) BIT 381 drivers/gpu/drm/i2c/tda998x_drv.c # define CEC_RXSHPDINT_RXSENS BIT(0) BIT 382 drivers/gpu/drm/i2c/tda998x_drv.c # define CEC_RXSHPDINT_HPD BIT(1) BIT 1380 drivers/gpu/drm/i2c/tda998x_drv.c if (mode->htotal >= BIT(13)) BIT 1382 drivers/gpu/drm/i2c/tda998x_drv.c if (mode->vtotal >= BIT(11)) BIT 1257 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); BIT 1281 drivers/gpu/drm/i915/display/icl_dsi.c if (intel_dsi->ports == BIT(PORT_B)) BIT 1530 drivers/gpu/drm/i915/display/icl_dsi.c allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT 1531 drivers/gpu/drm/i915/display/icl_dsi.c BIT(DRM_MODE_SCALE_FULLSCREEN) | BIT 1532 drivers/gpu/drm/i915/display/icl_dsi.c BIT(DRM_MODE_SCALE_CENTER); BIT 1587 drivers/gpu/drm/i915/display/icl_dsi.c encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); BIT 1616 drivers/gpu/drm/i915/display/icl_dsi.c intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); BIT 1618 drivers/gpu/drm/i915/display/icl_dsi.c intel_dsi->ports = BIT(port); BIT 149 drivers/gpu/drm/i915/display/intel_atomic_plane.c new_crtc_state->active_planes &= ~BIT(plane->id); BIT 150 drivers/gpu/drm/i915/display/intel_atomic_plane.c new_crtc_state->nv12_planes &= ~BIT(plane->id); BIT 151 drivers/gpu/drm/i915/display/intel_atomic_plane.c new_crtc_state->c8_planes &= ~BIT(plane->id); BIT 164 drivers/gpu/drm/i915/display/intel_atomic_plane.c new_crtc_state->active_planes |= BIT(plane->id); BIT 168 drivers/gpu/drm/i915/display/intel_atomic_plane.c new_crtc_state->nv12_planes |= BIT(plane->id); BIT 172 drivers/gpu/drm/i915/display/intel_atomic_plane.c new_crtc_state->c8_planes |= BIT(plane->id); BIT 175 drivers/gpu/drm/i915/display/intel_atomic_plane.c new_crtc_state->update_planes |= BIT(plane->id); BIT 245 drivers/gpu/drm/i915/display/intel_atomic_plane.c !(*update_mask & BIT(plane_id))) BIT 256 drivers/gpu/drm/i915/display/intel_atomic_plane.c *update_mask &= ~BIT(plane_id); BIT 358 drivers/gpu/drm/i915/display/intel_atomic_plane.c !(update_mask & BIT(plane->id))) BIT 798 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.bl_ports = BIT(port); BIT 800 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.cabc_ports = BIT(port); BIT 807 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.bl_ports = BIT(PORT_A); BIT 810 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.bl_ports = BIT(PORT_C); BIT 814 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C); BIT 823 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A); BIT 826 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C); BIT 831 drivers/gpu/drm/i915/display/intel_bios.c BIT(PORT_A) | BIT(PORT_C); BIT 262 drivers/gpu/drm/i915/display/intel_bw.c return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR)); BIT 469 drivers/gpu/drm/i915/display/intel_cdclk.c BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); BIT 479 drivers/gpu/drm/i915/display/intel_cdclk.c BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); BIT 554 drivers/gpu/drm/i915/display/intel_cdclk.c BIT(VLV_IOSF_SB_CCK) | BIT 555 drivers/gpu/drm/i915/display/intel_cdclk.c BIT(VLV_IOSF_SB_BUNIT) | BIT 556 drivers/gpu/drm/i915/display/intel_cdclk.c BIT(VLV_IOSF_SB_PUNIT)); BIT 601 drivers/gpu/drm/i915/display/intel_cdclk.c BIT(VLV_IOSF_SB_CCK) | BIT 602 drivers/gpu/drm/i915/display/intel_cdclk.c BIT(VLV_IOSF_SB_BUNIT) | BIT 603 drivers/gpu/drm/i915/display/intel_cdclk.c BIT(VLV_IOSF_SB_PUNIT)); BIT 1067 drivers/gpu/drm/i915/display/intel_color.c return crtc_state->active_planes & BIT(plane->id) || BIT 1101 drivers/gpu/drm/i915/display/intel_color.c new_crtc_state->update_planes |= BIT(plane->id); BIT 133 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); BIT 2001 drivers/gpu/drm/i915/display/intel_ddi.c *pipe_mask = BIT(PIPE_A); BIT 2004 drivers/gpu/drm/i915/display/intel_ddi.c *pipe_mask = BIT(PIPE_B); BIT 2007 drivers/gpu/drm/i915/display/intel_ddi.c *pipe_mask = BIT(PIPE_C); BIT 2042 drivers/gpu/drm/i915/display/intel_ddi.c mst_pipe_mask |= BIT(p); BIT 2044 drivers/gpu/drm/i915/display/intel_ddi.c *pipe_mask |= BIT(p); BIT 2054 drivers/gpu/drm/i915/display/intel_ddi.c *pipe_mask = BIT(ffs(*pipe_mask) - 1); BIT 2868 drivers/gpu/drm/i915/display/intel_ddi.c port_mask = BIT(encoder->port); BIT 2883 drivers/gpu/drm/i915/display/intel_ddi.c if (WARN_ON(port_mask & BIT(other_encoder->port))) BIT 3884 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); BIT 3888 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); BIT 3892 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); BIT 3894 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); BIT 3900 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); BIT 4336 drivers/gpu/drm/i915/display/intel_ddi.c intel_encoder->crtc_mask |= BIT(pipe); BIT 1773 drivers/gpu/drm/i915/display/intel_display.c (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT))) BIT 3139 drivers/gpu/drm/i915/display/intel_display.c crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); BIT 5683 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); BIT 6051 drivers/gpu/drm/i915/display/intel_display.c !(update_mask & BIT(plane->id))) BIT 7351 drivers/gpu/drm/i915/display/intel_display.c if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))) BIT 9352 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL); BIT 9357 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1); BIT 9362 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2); BIT 9487 drivers/gpu/drm/i915/display/intel_display.c BIT(PLANE_CURSOR))) == 0) BIT 10216 drivers/gpu/drm/i915/display/intel_display.c BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); BIT 10219 drivers/gpu/drm/i915/display/intel_display.c panel_transcoder_mask |= BIT(TRANSCODER_EDP); BIT 10246 drivers/gpu/drm/i915/display/intel_display.c enabled_panel_transcoders |= BIT(panel_transcoder); BIT 10247 drivers/gpu/drm/i915/display/intel_display.c if (enabled_panel_transcoders != BIT(panel_transcoder)) BIT 10278 drivers/gpu/drm/i915/display/intel_display.c WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) && BIT 10279 drivers/gpu/drm/i915/display/intel_display.c enabled_panel_transcoders != BIT(TRANSCODER_EDP)); BIT 10309 drivers/gpu/drm/i915/display/intel_display.c for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { BIT 11540 drivers/gpu/drm/i915/display/intel_display.c crtc_state->active_planes &= ~BIT(plane->id); BIT 11706 drivers/gpu/drm/i915/display/intel_display.c crtc_state->active_planes &= ~BIT(plane->id); BIT 11707 drivers/gpu/drm/i915/display/intel_display.c crtc_state->update_planes |= BIT(plane->id); BIT 11720 drivers/gpu/drm/i915/display/intel_display.c !(crtc_state->nv12_planes & BIT(plane->id))) BIT 11727 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->active_planes & BIT(linked->id)) BIT 11748 drivers/gpu/drm/i915/display/intel_display.c crtc_state->active_planes |= BIT(linked->id); BIT 11749 drivers/gpu/drm/i915/display/intel_display.c crtc_state->update_planes |= BIT(linked->id); BIT 12014 drivers/gpu/drm/i915/display/intel_display.c if ((output_types & BIT(i)) == 0) BIT 12024 drivers/gpu/drm/i915/display/intel_display.c output_types &= ~BIT(i); BIT 12341 drivers/gpu/drm/i915/display/intel_display.c BIT(encoder->compute_output_type(encoder, pipe_config, BIT 12344 drivers/gpu/drm/i915/display/intel_display.c pipe_config->output_types |= BIT(encoder->type); BIT 14904 drivers/gpu/drm/i915/display/intel_display.c possible_crtcs = BIT(pipe); BIT 14985 drivers/gpu/drm/i915/display/intel_display.c possible_crtcs = BIT(pipe); BIT 15128 drivers/gpu/drm/i915/display/intel_display.c intel_crtc->plane_ids_mask |= BIT(primary->id); BIT 15138 drivers/gpu/drm/i915/display/intel_display.c intel_crtc->plane_ids_mask |= BIT(plane->id); BIT 15146 drivers/gpu/drm/i915/display/intel_display.c intel_crtc->plane_ids_mask |= BIT(cursor->id); BIT 183 drivers/gpu/drm/i915/display/intel_display.h for_each_if((__crtc)->plane_ids_mask & BIT(__p)) BIT 296 drivers/gpu/drm/i915/display/intel_display.h for_each_if((__mask) & BIT(__p)) BIT 314 drivers/gpu/drm/i915/display/intel_display.h for_each_if((__ports_mask) & BIT(__port)) BIT 318 drivers/gpu/drm/i915/display/intel_display.h for_each_if((__phys_mask) & BIT(__phy)) BIT 2750 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), BIT 2951 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), BIT 3033 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), BIT 3093 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), BIT 3262 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), BIT 3401 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B), BIT 3583 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_C), BIT 3634 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B), BIT 3900 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_C), BIT 3912 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_D), BIT 515 drivers/gpu/drm/i915/display/intel_display_types.h #define PLANE_HAS_FENCE BIT(0) BIT 3152 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); BIT 3154 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); BIT 6359 drivers/gpu/drm/i915/display/intel_dp.c allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); BIT 6361 drivers/gpu/drm/i915/display/intel_dp.c allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); BIT 164 drivers/gpu/drm/i915/display/intel_dpio_phy.c .pwron_mask = BIT(0), BIT 174 drivers/gpu/drm/i915/display/intel_dpio_phy.c .pwron_mask = BIT(1), BIT 186 drivers/gpu/drm/i915/display/intel_dpio_phy.c .pwron_mask = BIT(0), BIT 196 drivers/gpu/drm/i915/display/intel_dpio_phy.c .pwron_mask = BIT(3), BIT 206 drivers/gpu/drm/i915/display/intel_dpio_phy.c .pwron_mask = BIT(1), BIT 580 drivers/gpu/drm/i915/display/intel_dpio_phy.c return BIT(2) | BIT(0); BIT 582 drivers/gpu/drm/i915/display/intel_dpio_phy.c return BIT(3) | BIT(2) | BIT(0); BIT 609 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (lane_lat_optim_mask & BIT(lane)) BIT 633 drivers/gpu/drm/i915/display/intel_dpio_phy.c mask |= BIT(lane); BIT 533 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (dev_priv->pch_ssc_use & BIT(id)) BIT 551 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (dev_priv->pch_ssc_use & BIT(id)) BIT 249 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); BIT 258 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); BIT 304 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); BIT 309 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); BIT 169 drivers/gpu/drm/i915/display/intel_dvo.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); BIT 587 drivers/gpu/drm/i915/display/intel_hdmi.c return BIT(i); BIT 609 drivers/gpu/drm/i915/display/intel_hdmi.c ret |= BIT(i); BIT 612 drivers/gpu/drm/i915/display/intel_hdmi.c ret |= BIT(i); BIT 1786 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); BIT 332 drivers/gpu/drm/i915/display/intel_hotplug.c long_hpd = long_port_mask & BIT(port); BIT 333 drivers/gpu/drm/i915/display/intel_hotplug.c short_hpd = short_port_mask & BIT(port); BIT 343 drivers/gpu/drm/i915/display/intel_hotplug.c old_bits |= BIT(encoder->hpd_pin); BIT 395 drivers/gpu/drm/i915/display/intel_hotplug.c hpd_bit = BIT(intel_encoder->hpd_pin); BIT 476 drivers/gpu/drm/i915/display/intel_hotplug.c if (!(BIT(pin) & pin_mask)) BIT 482 drivers/gpu/drm/i915/display/intel_hotplug.c long_hpd = long_mask & BIT(pin); BIT 489 drivers/gpu/drm/i915/display/intel_hotplug.c long_hpd_pulse_mask |= BIT(pin); BIT 490 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.long_port_mask |= BIT(port); BIT 492 drivers/gpu/drm/i915/display/intel_hotplug.c short_hpd_pulse_mask |= BIT(pin); BIT 493 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.short_port_mask |= BIT(port); BIT 501 drivers/gpu/drm/i915/display/intel_hotplug.c if (!(BIT(pin) & pin_mask)) BIT 524 drivers/gpu/drm/i915/display/intel_hotplug.c if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) { BIT 525 drivers/gpu/drm/i915/display/intel_hotplug.c long_hpd = long_hpd_pulse_mask & BIT(pin); BIT 527 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.event_bits |= BIT(pin); BIT 533 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.event_bits &= ~BIT(pin); BIT 126 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); BIT 917 drivers/gpu/drm/i915/display/intel_lvds.c allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT); BIT 918 drivers/gpu/drm/i915/display/intel_lvds.c allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN); BIT 919 drivers/gpu/drm/i915/display/intel_lvds.c allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); BIT 112 drivers/gpu/drm/i915/display/intel_psr.c u32 transcoders = BIT(TRANSCODER_EDP); BIT 115 drivers/gpu/drm/i915/display/intel_psr.c transcoders |= BIT(TRANSCODER_A) | BIT 116 drivers/gpu/drm/i915/display/intel_psr.c BIT(TRANSCODER_B) | BIT 117 drivers/gpu/drm/i915/display/intel_psr.c BIT(TRANSCODER_C); BIT 174 drivers/gpu/drm/i915/display/intel_psr.c u32 transcoders = BIT(TRANSCODER_EDP); BIT 180 drivers/gpu/drm/i915/display/intel_psr.c transcoders |= BIT(TRANSCODER_A) | BIT 181 drivers/gpu/drm/i915/display/intel_psr.c BIT(TRANSCODER_B) | BIT 182 drivers/gpu/drm/i915/display/intel_psr.c BIT(TRANSCODER_C); BIT 1608 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); BIT 337 drivers/gpu/drm/i915/display/intel_sprite.c icl_hdr_plane_mask() & BIT(plane_id); BIT 2486 drivers/gpu/drm/i915/display/intel_sprite.c possible_crtcs = BIT(pipe); BIT 2509 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_COLOR_YCBCR_BT601) | BIT 2510 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_COLOR_YCBCR_BT709), BIT 2511 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT 2512 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_COLOR_YCBCR_FULL_RANGE), BIT 2518 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_MODE_BLEND_PIXEL_NONE) | BIT 2519 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_MODE_BLEND_PREMULTI) | BIT 2520 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_MODE_BLEND_COVERAGE)); BIT 2611 drivers/gpu/drm/i915/display/intel_sprite.c possible_crtcs = BIT(pipe); BIT 2626 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_COLOR_YCBCR_BT601) | BIT 2627 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_COLOR_YCBCR_BT709), BIT 2628 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT 2629 drivers/gpu/drm/i915/display/intel_sprite.c BIT(DRM_COLOR_YCBCR_FULL_RANGE), BIT 47 drivers/gpu/drm/i915/display/intel_sprite.h return BIT(PLANE_PRIMARY) | BIT 48 drivers/gpu/drm/i915/display/intel_sprite.h BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1); BIT 135 drivers/gpu/drm/i915/display/intel_tc.c valid_hpd_mask = BIT(TC_PORT_LEGACY); BIT 137 drivers/gpu/drm/i915/display/intel_tc.c valid_hpd_mask = BIT(TC_PORT_DP_ALT) | BIT 138 drivers/gpu/drm/i915/display/intel_tc.c BIT(TC_PORT_TBT_ALT); BIT 168 drivers/gpu/drm/i915/display/intel_tc.c mask |= BIT(TC_PORT_TBT_ALT); BIT 170 drivers/gpu/drm/i915/display/intel_tc.c mask |= BIT(TC_PORT_DP_ALT); BIT 173 drivers/gpu/drm/i915/display/intel_tc.c mask |= BIT(TC_PORT_LEGACY); BIT 288 drivers/gpu/drm/i915/display/intel_tc.c if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) { BIT 467 drivers/gpu/drm/i915/display/intel_tc.c BIT(dig_port->tc_mode); BIT 1097 drivers/gpu/drm/i915/display/intel_tv.c pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); BIT 300 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_dsi->ports == BIT(PORT_C)) BIT 660 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { BIT 1197 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); BIT 1626 drivers/gpu/drm/i915/display/vlv_dsi.c allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); BIT 1628 drivers/gpu/drm/i915/display/vlv_dsi.c allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); BIT 1873 drivers/gpu/drm/i915/display/vlv_dsi.c intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); BIT 1875 drivers/gpu/drm/i915/display/vlv_dsi.c intel_encoder->crtc_mask = BIT(PIPE_A); BIT 1877 drivers/gpu/drm/i915/display/vlv_dsi.c intel_encoder->crtc_mask = BIT(PIPE_B); BIT 1880 drivers/gpu/drm/i915/display/vlv_dsi.c intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); BIT 1882 drivers/gpu/drm/i915/display/vlv_dsi.c intel_dsi->ports = BIT(port); BIT 17 drivers/gpu/drm/i915/gem/i915_gem_clflush.h #define I915_CLFLUSH_FORCE BIT(0) BIT 18 drivers/gpu/drm/i915/gem/i915_gem_clflush.h #define I915_CLFLUSH_SYNC BIT(1) BIT 146 drivers/gpu/drm/i915/gem/i915_gem_context.c #define LOOKUP_USER_INDEX BIT(0) BIT 2055 drivers/gpu/drm/i915/gem/i915_gem_context.c if (!(local.flags & BIT(bit))) BIT 36 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c #define __EXEC_OBJECT_HAS_REF BIT(31) BIT 37 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c #define __EXEC_OBJECT_HAS_PIN BIT(30) BIT 38 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c #define __EXEC_OBJECT_HAS_FENCE BIT(29) BIT 39 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c #define __EXEC_OBJECT_NEEDS_MAP BIT(28) BIT 40 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c #define __EXEC_OBJECT_NEEDS_BIAS BIT(27) BIT 44 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c #define __EXEC_HAS_RELOC BIT(31) BIT 45 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c #define __EXEC_VALIDATED BIT(30) BIT 358 drivers/gpu/drm/i915/gem/i915_gem_object.h #define CLFLUSH_BEFORE BIT(0) BIT 359 drivers/gpu/drm/i915/gem/i915_gem_object.h #define CLFLUSH_AFTER BIT(1) BIT 32 drivers/gpu/drm/i915/gem/i915_gem_object_types.h #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0) BIT 33 drivers/gpu/drm/i915/gem/i915_gem_object_types.h #define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1) BIT 34 drivers/gpu/drm/i915/gem/i915_gem_object_types.h #define I915_GEM_OBJECT_IS_PROXY BIT(2) BIT 35 drivers/gpu/drm/i915/gem/i915_gem_object_types.h #define I915_GEM_OBJECT_NO_GGTT BIT(3) BIT 36 drivers/gpu/drm/i915/gem/i915_gem_object_types.h #define I915_GEM_OBJECT_ASYNC_CANCEL BIT(4) BIT 127 drivers/gpu/drm/i915/gem/i915_gem_object_types.h #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0) BIT 128 drivers/gpu/drm/i915/gem/i915_gem_object_types.h #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1) BIT 55 drivers/gpu/drm/i915/gem/i915_gem_pages.c obj->mm.page_sizes.sg |= BIT(i); BIT 19 drivers/gpu/drm/i915/gem/i915_gem_shrinker.h #define I915_SHRINK_UNBOUND BIT(0) BIT 20 drivers/gpu/drm/i915/gem/i915_gem_shrinker.h #define I915_SHRINK_BOUND BIT(1) BIT 21 drivers/gpu/drm/i915/gem/i915_gem_shrinker.h #define I915_SHRINK_ACTIVE BIT(2) BIT 22 drivers/gpu/drm/i915/gem/i915_gem_shrinker.h #define I915_SHRINK_VMAPS BIT(3) BIT 23 drivers/gpu/drm/i915/gem/i915_gem_shrinker.h #define I915_SHRINK_WRITEBACK BIT(4) BIT 86 drivers/gpu/drm/i915/gem/selftests/huge_pages.c unsigned int page_size = BIT(bit); BIT 156 drivers/gpu/drm/i915/gem/selftests/huge_pages.c GEM_BUG_ON(!IS_ALIGNED(size, BIT(__ffs(page_mask)))); BIT 386 drivers/gpu/drm/i915/gem/selftests/huge_pages.c for (i = 1; i < BIT(ARRAY_SIZE(page_sizes)); i++) { BIT 390 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (i & BIT(j)) BIT 470 drivers/gpu/drm/i915/gem/selftests/huge_pages.c unsigned int page_size = BIT(bit); BIT 1104 drivers/gpu/drm/i915/gem/selftests/huge_pages.c pages[n++] = BIT(i); BIT 1106 drivers/gpu/drm/i915/gem/selftests/huge_pages.c for (size_mask = 2; size_mask < BIT(n); size_mask++) { BIT 1110 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (size_mask & BIT(i)) BIT 1122 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (page_mask & BIT(i)) BIT 1130 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (!IS_ALIGNED(size, BIT(__ffs(page_sizes)))) BIT 1344 drivers/gpu/drm/i915/gem/selftests/huge_pages.c unsigned int page_size = BIT(first); BIT 709 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c #define TEST_IDLE BIT(0) BIT 710 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c #define TEST_BUSY BIT(1) BIT 711 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c #define TEST_RESET BIT(2) BIT 1554 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c context_barrier_inject_fault = BIT(RCS0); BIT 277 drivers/gpu/drm/i915/gt/intel_engine_cs.c BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); BIT 278 drivers/gpu/drm/i915/gt/intel_engine_cs.c BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); BIT 296 drivers/gpu/drm/i915/gt/intel_engine_cs.c engine->mask = BIT(id); BIT 315 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (WARN_ON(engine->context_size > BIT(20))) BIT 421 drivers/gpu/drm/i915/gt/intel_engine_cs.c mask |= BIT(i); BIT 426 drivers/gpu/drm/i915/gt/intel_engine_types.h #define EMIT_INVALIDATE BIT(0) BIT 427 drivers/gpu/drm/i915/gt/intel_engine_types.h #define EMIT_FLUSH BIT(1) BIT 432 drivers/gpu/drm/i915/gt/intel_engine_types.h #define I915_DISPATCH_SECURE BIT(0) BIT 433 drivers/gpu/drm/i915/gt/intel_engine_types.h #define I915_DISPATCH_PINNED BIT(1) BIT 479 drivers/gpu/drm/i915/gt/intel_engine_types.h #define I915_ENGINE_USING_CMD_PARSER BIT(0) BIT 480 drivers/gpu/drm/i915/gt/intel_engine_types.h #define I915_ENGINE_SUPPORTS_STATS BIT(1) BIT 481 drivers/gpu/drm/i915/gt/intel_engine_types.h #define I915_ENGINE_HAS_PREEMPTION BIT(2) BIT 482 drivers/gpu/drm/i915/gt/intel_engine_types.h #define I915_ENGINE_HAS_SEMAPHORES BIT(3) BIT 483 drivers/gpu/drm/i915/gt/intel_engine_types.h #define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4) BIT 484 drivers/gpu/drm/i915/gt/intel_engine_types.h #define I915_ENGINE_IS_VIRTUAL BIT(5) BIT 485 drivers/gpu/drm/i915/gt/intel_engine_types.h #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7) BIT 600 drivers/gpu/drm/i915/gt/intel_engine_types.h for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \ BIT 601 drivers/gpu/drm/i915/gt/intel_engine_types.h (BIT(subslice__) & instdone_subslice_mask(dev_priv__))) BIT 118 drivers/gpu/drm/i915/gt/intel_engine_user.c if (engine->flags & BIT(map[i].engine)) BIT 119 drivers/gpu/drm/i915/gt/intel_engine_user.c enabled |= BIT(map[i].sched); BIT 121 drivers/gpu/drm/i915/gt/intel_engine_user.c disabled |= BIT(map[i].sched); BIT 275 drivers/gpu/drm/i915/gt/intel_engine_user.c unsigned int bit = BIT(engine->uabi_class); BIT 300 drivers/gpu/drm/i915/gt/intel_engine_user.c which |= BIT(engine->uabi_class); BIT 48 drivers/gpu/drm/i915/gt/intel_gt_irq.c raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); BIT 168 drivers/gpu/drm/i915/gt/intel_gt_irq.c if (dw & BIT(bit)) { BIT 181 drivers/gpu/drm/i915/gt/intel_gt_irq.c raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit)); BIT 435 drivers/gpu/drm/i915/gt/intel_lrc.c BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH))); BIT 436 drivers/gpu/drm/i915/gt/intel_lrc.c BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH))); BIT 455 drivers/gpu/drm/i915/gt/intel_lrc.c GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH)); BIT 467 drivers/gpu/drm/i915/gt/intel_lrc.c GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH)); BIT 2692 drivers/gpu/drm/i915/gt/intel_lrc.c (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); BIT 2714 drivers/gpu/drm/i915/gt/intel_lrc.c (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); BIT 3288 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_END] |= BIT(0); BIT 322 drivers/gpu/drm/i915/gt/intel_reset.c if ((BIT(engine->instance) & vdbox_sfc_access) == 0) BIT 386 drivers/gpu/drm/i915/gt/intel_reset.c if ((BIT(engine->instance) & vdbox_sfc_access) == 0) BIT 31 drivers/gpu/drm/i915/gt/intel_reset.h #define I915_ERROR_CAPTURE BIT(0) BIT 497 drivers/gpu/drm/i915/gt/intel_ringbuffer.c mask &= ~BIT(0); BIT 1732 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (!(ctx->remap_slice & BIT(i))) BIT 15 drivers/gpu/drm/i915/gt/intel_timeline.c #define ptr_set_bit(ptr, bit) ((typeof(ptr))((unsigned long)(ptr) | BIT(bit))) BIT 16 drivers/gpu/drm/i915/gt/intel_timeline.c #define ptr_test_bit(ptr, bit) ((unsigned long)(ptr) & BIT(bit)) BIT 164 drivers/gpu/drm/i915/gt/intel_timeline.c GEM_BUG_ON(cacheline >= BIT(CACHELINE_BITS)); BIT 253 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.mask = BIT(id); BIT 684 drivers/gpu/drm/i915/gt/selftest_hangcheck.c #define TEST_ACTIVE BIT(0) BIT 685 drivers/gpu/drm/i915/gt/selftest_hangcheck.c #define TEST_OTHERS BIT(1) BIT 686 drivers/gpu/drm/i915/gt/selftest_hangcheck.c #define TEST_SELF BIT(2) BIT 687 drivers/gpu/drm/i915/gt/selftest_hangcheck.c #define TEST_PRIORITY BIT(3) BIT 1482 drivers/gpu/drm/i915/gt/selftest_hangcheck.c reset_count = fake_hangcheck(gt, BIT(id)); BIT 1508 drivers/gpu/drm/i915/gt/selftest_lrc.c #define BATCH BIT(0) BIT 1676 drivers/gpu/drm/i915/gt/selftest_lrc.c #define CHAIN BIT(0) BIT 1985 drivers/gpu/drm/i915/gt/selftest_lrc.c #define BOND_SCHEDULE BIT(0) BIT 45 drivers/gpu/drm/i915/gt/selftest_timeline.c SHUFFLE = BIT(0), BIT 375 drivers/gpu/drm/i915/gt/selftest_timeline.c unsigned int mask = BIT(order) - 1; BIT 57 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) BIT 58 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) BIT 59 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) BIT 60 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) BIT 61 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h #define GUC_STAGE_DESC_ATTR_RESET BIT(4) BIT 62 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) BIT 63 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h #define GUC_STAGE_DESC_ATTR_PCH BIT(6) BIT 64 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) BIT 600 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), BIT 601 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) BIT 126 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_GUC2HOST BIT(15) BIT 127 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_EXEC_ERROR BIT(14) BIT 128 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_DISPLAY_EVENT BIT(13) BIT 129 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_SEM_SIG BIT(12) BIT 130 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_IOMMU2GUC BIT(11) BIT 131 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_DOORBELL_RANG BIT(10) BIT 132 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_DMA_DONE BIT(9) BIT 133 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_FATAL_ERROR BIT(8) BIT 134 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_NOTIF_ERROR BIT(7) BIT 135 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_SW_INT_6 BIT(6) BIT 136 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_SW_INT_5 BIT(5) BIT 137 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_SW_INT_4 BIT(4) BIT 138 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_SW_INT_3 BIT(3) BIT 139 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_SW_INT_2 BIT(2) BIT 140 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_SW_INT_1 BIT(1) BIT 141 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_INTR_SW_INT_0 BIT(0) BIT 410 drivers/gpu/drm/i915/gvt/cmd_parser.c #define R_RCS BIT(RCS0) BIT 411 drivers/gpu/drm/i915/gvt/cmd_parser.c #define R_VCS1 BIT(VCS0) BIT 412 drivers/gpu/drm/i915/gvt/cmd_parser.c #define R_VCS2 BIT(VCS1) BIT 414 drivers/gpu/drm/i915/gvt/cmd_parser.c #define R_BCS BIT(BCS0) BIT 415 drivers/gpu/drm/i915/gvt/cmd_parser.c #define R_VECS BIT(VECS0) BIT 653 drivers/gpu/drm/i915/gvt/cmd_parser.c if (opcode == e->info->opcode && e->info->rings & BIT(ring_id)) BIT 1601 drivers/gpu/drm/i915/gvt/cmd_parser.c if (cmd_val(s, 0) & BIT(18)) BIT 413 drivers/gpu/drm/i915/gvt/execlist.c if (workload->status || (vgpu->resetting_eng & BIT(ring_id))) BIT 358 drivers/gpu/drm/i915/gvt/gtt.c #define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */ BIT 326 drivers/gpu/drm/i915/gvt/handlers.c engine_mask |= BIT(RCS0); BIT 330 drivers/gpu/drm/i915/gvt/handlers.c engine_mask |= BIT(VCS0); BIT 334 drivers/gpu/drm/i915/gvt/handlers.c engine_mask |= BIT(BCS0); BIT 338 drivers/gpu/drm/i915/gvt/handlers.c engine_mask |= BIT(VECS0); BIT 342 drivers/gpu/drm/i915/gvt/handlers.c engine_mask |= BIT(VCS1); BIT 1608 drivers/gpu/drm/i915/gvt/handlers.c if (v & BIT(0)) { BIT 1615 drivers/gpu/drm/i915/gvt/handlers.c if (v & BIT(1)) { BIT 1736 drivers/gpu/drm/i915/gvt/handlers.c BIT(ring_id), BIT 250 drivers/gpu/drm/i915/gvt/mmio.c ~(BIT(0) | BIT(1)); BIT 256 drivers/gpu/drm/i915/gvt/mmio.c ~BIT(30); BIT 258 drivers/gpu/drm/i915/gvt/mmio.c ~BIT(30); BIT 938 drivers/gpu/drm/i915/gvt/scheduler.c !(vgpu->resetting_eng & BIT(ring_id))) { BIT 956 drivers/gpu/drm/i915/gvt/scheduler.c if (workload->status || vgpu->resetting_eng & BIT(ring_id)) { BIT 970 drivers/gpu/drm/i915/gvt/scheduler.c intel_vgpu_clean_workloads(vgpu, BIT(ring_id)); BIT 3576 drivers/gpu/drm/i915/i915_debugfs.c #define DROP_UNBOUND BIT(0) BIT 3577 drivers/gpu/drm/i915/i915_debugfs.c #define DROP_BOUND BIT(1) BIT 3578 drivers/gpu/drm/i915/i915_debugfs.c #define DROP_RETIRE BIT(2) BIT 3579 drivers/gpu/drm/i915/i915_debugfs.c #define DROP_ACTIVE BIT(3) BIT 3580 drivers/gpu/drm/i915/i915_debugfs.c #define DROP_FREED BIT(4) BIT 3581 drivers/gpu/drm/i915/i915_debugfs.c #define DROP_SHRINK_ALL BIT(5) BIT 3582 drivers/gpu/drm/i915/i915_debugfs.c #define DROP_IDLE BIT(6) BIT 3583 drivers/gpu/drm/i915/i915_debugfs.c #define DROP_RESET_ACTIVE BIT(7) BIT 3584 drivers/gpu/drm/i915/i915_debugfs.c #define DROP_RESET_SEQNO BIT(8) BIT 3748 drivers/gpu/drm/i915/i915_debugfs.c sseu->slice_mask = BIT(0); BIT 3749 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[0] |= BIT(ss); BIT 3796 drivers/gpu/drm/i915/i915_debugfs.c sseu->slice_mask |= BIT(s); BIT 3845 drivers/gpu/drm/i915/i915_debugfs.c sseu->slice_mask |= BIT(s); BIT 3859 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[s] |= BIT(ss); BIT 1827 drivers/gpu/drm/i915/i915_drv.h BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ BIT 1830 drivers/gpu/drm/i915/i915_drv.h BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) BIT 1907 drivers/gpu/drm/i915/i915_drv.h return info->platform_mask[pi] & BIT(pb); BIT 1925 drivers/gpu/drm/i915/i915_drv.h return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); BIT 2067 drivers/gpu/drm/i915/i915_drv.h #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) BIT 2296 drivers/gpu/drm/i915/i915_drv.h #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) BIT 93 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= BIT(I965_FENCE_TILING_Y_SHIFT); BIT 143 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= BIT(I830_FENCE_TILING_Y_SHIFT); BIT 176 drivers/gpu/drm/i915/i915_gem_fence_reg.c val |= BIT(I830_FENCE_TILING_Y_SHIFT); BIT 684 drivers/gpu/drm/i915/i915_gem_gtt.c dma_unmap_page(vm->dma, p->daddr, BIT(order) << PAGE_SHIFT, BIT 148 drivers/gpu/drm/i915/i915_gem_gtt.h #define GEN8_PDE_IPS_64K BIT(11) BIT 149 drivers/gpu/drm/i915/i915_gem_gtt.h #define GEN8_PDE_PS_2M BIT(7) BIT 1549 drivers/gpu/drm/i915/i915_irq.c *pin_mask |= BIT(pin); BIT 1552 drivers/gpu/drm/i915/i915_irq.c *long_mask |= BIT(pin); BIT 33 drivers/gpu/drm/i915/i915_params.h #define ENABLE_GUC_SUBMISSION BIT(0) BIT 34 drivers/gpu/drm/i915/i915_params.h #define ENABLE_GUC_LOAD_HUC BIT(1) BIT 38 drivers/gpu/drm/i915/i915_pci.c #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) BIT 158 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0), \ BIT 175 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0), \ BIT 209 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0), \ BIT 294 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0), \ BIT 324 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0), BIT 334 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0), BIT 342 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0), \ BIT 369 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ BIT 417 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ BIT 483 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), BIT 493 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ BIT 557 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), BIT 566 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), BIT 616 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) BIT 633 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ BIT 690 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), BIT 711 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), BIT 760 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), BIT 767 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), BIT 799 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), BIT 3612 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.gen8_valid_ctx_bit = BIT(25); BIT 3617 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.gen8_valid_ctx_bit = BIT(16); BIT 3637 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.gen8_valid_ctx_bit = BIT(16); BIT 24 drivers/gpu/drm/i915/i915_pmu.c (BIT(I915_SAMPLE_BUSY) | \ BIT 25 drivers/gpu/drm/i915/i915_pmu.c BIT(I915_SAMPLE_WAIT) | \ BIT 26 drivers/gpu/drm/i915/i915_pmu.c BIT(I915_SAMPLE_SEMA)) BIT 111 drivers/gpu/drm/i915/i915_pmu.c enable &= ~BIT(I915_SAMPLE_BUSY); BIT 634 drivers/gpu/drm/i915/i915_pmu.c engine->pmu.enable |= BIT(sample); BIT 675 drivers/gpu/drm/i915/i915_pmu.c engine->pmu.enable &= ~BIT(sample); BIT 24 drivers/gpu/drm/i915/i915_priolist_types.h #define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT) BIT 27 drivers/gpu/drm/i915/i915_priolist_types.h #define I915_PRIORITY_WAIT ((u8)BIT(0)) BIT 28 drivers/gpu/drm/i915/i915_priolist_types.h #define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(1)) BIT 57 drivers/gpu/drm/i915/i915_pvinfo.h #define VGT_CAPS_FULL_PPGTT BIT(2) BIT 58 drivers/gpu/drm/i915/i915_pvinfo.h #define VGT_CAPS_HWSP_EMULATION BIT(3) BIT 59 drivers/gpu/drm/i915/i915_pvinfo.h #define VGT_CAPS_HUGE_GTT BIT(4) BIT 128 drivers/gpu/drm/i915/i915_reg.h ((u32)(BIT(__n) + \ BIT 3933 drivers/gpu/drm/i915/i915_reg.h #define CCID_EN BIT(0) BIT 3934 drivers/gpu/drm/i915/i915_reg.h #define CCID_EXTENDED_STATE_RESTORE BIT(2) BIT 3935 drivers/gpu/drm/i915/i915_reg.h #define CCID_EXTENDED_STATE_SAVE BIT(3) BIT 8602 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_KERNEL BIT(0) BIT 8603 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_USER BIT(1) BIT 8604 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_KERNEL_FALLBACK BIT(15) BIT 9261 drivers/gpu/drm/i915/i915_reg.h #define HDCP_AKSV_SEND_TRIGGER BIT(31) BIT 9262 drivers/gpu/drm/i915/i915_reg.h #define HDCP_CLEAR_KEYS_TRIGGER BIT(30) BIT 9263 drivers/gpu/drm/i915/i915_reg.h #define HDCP_KEY_LOAD_TRIGGER BIT(8) BIT 9265 drivers/gpu/drm/i915/i915_reg.h #define HDCP_FUSE_IN_PROGRESS BIT(7) BIT 9266 drivers/gpu/drm/i915/i915_reg.h #define HDCP_FUSE_ERROR BIT(6) BIT 9267 drivers/gpu/drm/i915/i915_reg.h #define HDCP_FUSE_DONE BIT(5) BIT 9268 drivers/gpu/drm/i915/i915_reg.h #define HDCP_KEY_LOAD_STATUS BIT(1) BIT 9269 drivers/gpu/drm/i915/i915_reg.h #define HDCP_KEY_LOAD_DONE BIT(0) BIT 9275 drivers/gpu/drm/i915/i915_reg.h #define HDCP_DDIB_REP_PRESENT BIT(30) BIT 9276 drivers/gpu/drm/i915/i915_reg.h #define HDCP_DDIA_REP_PRESENT BIT(29) BIT 9277 drivers/gpu/drm/i915/i915_reg.h #define HDCP_DDIC_REP_PRESENT BIT(28) BIT 9278 drivers/gpu/drm/i915/i915_reg.h #define HDCP_DDID_REP_PRESENT BIT(27) BIT 9279 drivers/gpu/drm/i915/i915_reg.h #define HDCP_DDIF_REP_PRESENT BIT(26) BIT 9280 drivers/gpu/drm/i915/i915_reg.h #define HDCP_DDIE_REP_PRESENT BIT(25) BIT 9287 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA1_BUSY BIT(16) BIT 9288 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA1_READY BIT(17) BIT 9289 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA1_COMPLETE BIT(18) BIT 9290 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA1_V_MATCH BIT(19) BIT 9320 drivers/gpu/drm/i915/i915_reg.h #define HDCP_CONF_CAPTURE_AN BIT(0) BIT 9321 drivers/gpu/drm/i915/i915_reg.h #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0)) BIT 9329 drivers/gpu/drm/i915/i915_reg.h #define HDCP_STATUS_STREAM_A_ENC BIT(31) BIT 9330 drivers/gpu/drm/i915/i915_reg.h #define HDCP_STATUS_STREAM_B_ENC BIT(30) BIT 9331 drivers/gpu/drm/i915/i915_reg.h #define HDCP_STATUS_STREAM_C_ENC BIT(29) BIT 9332 drivers/gpu/drm/i915/i915_reg.h #define HDCP_STATUS_STREAM_D_ENC BIT(28) BIT 9333 drivers/gpu/drm/i915/i915_reg.h #define HDCP_STATUS_AUTH BIT(21) BIT 9334 drivers/gpu/drm/i915/i915_reg.h #define HDCP_STATUS_ENC BIT(20) BIT 9335 drivers/gpu/drm/i915/i915_reg.h #define HDCP_STATUS_RI_MATCH BIT(19) BIT 9336 drivers/gpu/drm/i915/i915_reg.h #define HDCP_STATUS_R0_READY BIT(18) BIT 9337 drivers/gpu/drm/i915/i915_reg.h #define HDCP_STATUS_AN_READY BIT(17) BIT 9338 drivers/gpu/drm/i915/i915_reg.h #define HDCP_STATUS_CIPHER BIT(16) BIT 9357 drivers/gpu/drm/i915/i915_reg.h #define AUTH_LINK_AUTHENTICATED BIT(31) BIT 9358 drivers/gpu/drm/i915/i915_reg.h #define AUTH_LINK_TYPE BIT(30) BIT 9359 drivers/gpu/drm/i915/i915_reg.h #define AUTH_FORCE_CLR_INPUTCTR BIT(19) BIT 9360 drivers/gpu/drm/i915/i915_reg.h #define AUTH_CLR_KEYS BIT(18) BIT 9363 drivers/gpu/drm/i915/i915_reg.h #define CTL_LINK_ENCRYPTION_REQ BIT(31) BIT 9366 drivers/gpu/drm/i915/i915_reg.h #define STREAM_ENCRYPTION_STATUS_A BIT(31) BIT 9367 drivers/gpu/drm/i915/i915_reg.h #define STREAM_ENCRYPTION_STATUS_B BIT(30) BIT 9368 drivers/gpu/drm/i915/i915_reg.h #define STREAM_ENCRYPTION_STATUS_C BIT(29) BIT 9369 drivers/gpu/drm/i915/i915_reg.h #define LINK_TYPE_STATUS BIT(22) BIT 9370 drivers/gpu/drm/i915/i915_reg.h #define LINK_AUTH_STATUS BIT(21) BIT 9371 drivers/gpu/drm/i915/i915_reg.h #define LINK_ENCRYPTION_STATUS BIT(20) BIT 222 drivers/gpu/drm/i915/i915_request.h #define I915_REQUEST_WAITBOOST BIT(0) BIT 223 drivers/gpu/drm/i915/i915_request.h #define I915_REQUEST_NOPREEMPT BIT(1) BIT 313 drivers/gpu/drm/i915/i915_request.h #define I915_WAIT_INTERRUPTIBLE BIT(0) BIT 314 drivers/gpu/drm/i915/i915_request.h #define I915_WAIT_LOCKED BIT(1) /* struct_mutex held, handle GPU reset */ BIT 315 drivers/gpu/drm/i915/i915_request.h #define I915_WAIT_PRIORITY BIT(2) /* small priority bump for the request */ BIT 316 drivers/gpu/drm/i915/i915_request.h #define I915_WAIT_ALL BIT(3) /* used by i915_gem_object_wait() */ BIT 317 drivers/gpu/drm/i915/i915_request.h #define I915_WAIT_FOR_IDLE_BOOST BIT(4) BIT 66 drivers/gpu/drm/i915/i915_scheduler.c GEM_BUG_ON(!(p->used & BIT(i))); BIT 135 drivers/gpu/drm/i915/i915_scheduler.c p->used |= BIT(idx); BIT 23 drivers/gpu/drm/i915/i915_scheduler.h (plist)->used &= ~BIT(idx)) \ BIT 59 drivers/gpu/drm/i915/i915_scheduler_types.h #define I915_SCHED_HAS_SEMAPHORE_CHAIN BIT(0) BIT 70 drivers/gpu/drm/i915/i915_scheduler_types.h #define I915_DEPENDENCY_ALLOC BIT(0) BIT 71 drivers/gpu/drm/i915/i915_scheduler_types.h #define I915_DEPENDENCY_EXTERNAL BIT(1) BIT 15 drivers/gpu/drm/i915/i915_sw_fence.c #define I915_SW_FENCE_FLAG_ALLOC BIT(3) /* after WQ_FLAG_* for safety */ BIT 192 drivers/gpu/drm/i915/i915_syncmap.c if (!(p->bitmap & BIT(idx))) BIT 218 drivers/gpu/drm/i915/i915_syncmap.c p->bitmap |= BIT(idx); BIT 226 drivers/gpu/drm/i915/i915_syncmap.c p->bitmap |= BIT(idx); BIT 300 drivers/gpu/drm/i915/i915_syncmap.c GEM_BUG_ON(!(p->parent->bitmap & BIT(idx))); BIT 65 drivers/gpu/drm/i915/i915_sysfs.c mask |= BIT(0); BIT 67 drivers/gpu/drm/i915/i915_sysfs.c mask |= BIT(1); BIT 69 drivers/gpu/drm/i915/i915_sysfs.c mask |= BIT(2); BIT 147 drivers/gpu/drm/i915/i915_utils.h (typeof(ptr))(__v & -BIT(n)); \ BIT 150 drivers/gpu/drm/i915/i915_utils.h #define ptr_unmask_bits(ptr, n) ((unsigned long)(ptr) & (BIT(n) - 1)) BIT 154 drivers/gpu/drm/i915/i915_utils.h *(bits) = __v & (BIT(n) - 1); \ BIT 155 drivers/gpu/drm/i915/i915_utils.h (typeof(ptr))(__v & -BIT(n)); \ BIT 160 drivers/gpu/drm/i915/i915_utils.h GEM_BUG_ON(__bits & -BIT(n)); \ BIT 232 drivers/gpu/drm/i915/i915_utils.h mask &= ~BIT(__idx); \ BIT 100 drivers/gpu/drm/i915/i915_vma.h #define I915_VMA_PIN_OVERFLOW BIT(8) BIT 103 drivers/gpu/drm/i915/i915_vma.h #define I915_VMA_GLOBAL_BIND BIT(9) BIT 104 drivers/gpu/drm/i915/i915_vma.h #define I915_VMA_LOCAL_BIND BIT(10) BIT 107 drivers/gpu/drm/i915/i915_vma.h #define I915_VMA_GGTT BIT(11) BIT 108 drivers/gpu/drm/i915/i915_vma.h #define I915_VMA_CAN_FENCE BIT(12) BIT 110 drivers/gpu/drm/i915/i915_vma.h #define I915_VMA_USERFAULT BIT(I915_VMA_USERFAULT_BIT) BIT 111 drivers/gpu/drm/i915/i915_vma.h #define I915_VMA_GGTT_WRITE BIT(14) BIT 154 drivers/gpu/drm/i915/i915_vma.h #define I915_VMA_RELEASE_MAP BIT(0) BIT 206 drivers/gpu/drm/i915/intel_device_info.c ss_en_mask = BIT(sseu->max_subslices) - 1; BIT 210 drivers/gpu/drm/i915/intel_device_info.c if (s_en & BIT(s)) { BIT 214 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask |= BIT(s); BIT 217 drivers/gpu/drm/i915/intel_device_info.c if (sseu->subslice_mask[s] & BIT(ss)) BIT 286 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] &= ~BIT(ss); BIT 316 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = BIT(0); BIT 328 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] |= BIT(0); BIT 339 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] |= BIT(1); BIT 392 drivers/gpu/drm/i915/intel_device_info.c if (!(sseu->slice_mask & BIT(s))) BIT 403 drivers/gpu/drm/i915/intel_device_info.c if (!(sseu->subslice_mask[s] & BIT(ss))) BIT 420 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_7eu[s] |= BIT(ss); BIT 452 drivers/gpu/drm/i915/intel_device_info.c #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) BIT 501 drivers/gpu/drm/i915/intel_device_info.c if (!(sseu->slice_mask & BIT(s))) BIT 511 drivers/gpu/drm/i915/intel_device_info.c if (!(sseu->subslice_mask[s] & BIT(ss))) BIT 566 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = BIT(0); BIT 567 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = BIT(0); BIT 570 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = BIT(0); BIT 571 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = BIT(0) | BIT(1); BIT 574 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = BIT(0) | BIT(1); BIT 575 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = BIT(0) | BIT(1); BIT 576 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[1] = BIT(0) | BIT(1); BIT 820 drivers/gpu/drm/i915/intel_device_info.c RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); BIT 825 drivers/gpu/drm/i915/intel_device_info.c mask = BIT(INTEL_SUBPLATFORM_ULT); BIT 828 drivers/gpu/drm/i915/intel_device_info.c mask = BIT(INTEL_SUBPLATFORM_ULX); BIT 831 drivers/gpu/drm/i915/intel_device_info.c mask |= BIT(INTEL_SUBPLATFORM_ULT); BIT 835 drivers/gpu/drm/i915/intel_device_info.c mask = BIT(INTEL_SUBPLATFORM_PORTF); BIT 933 drivers/gpu/drm/i915/intel_device_info.c u8 enabled_mask = BIT(info->num_pipes) - 1; BIT 936 drivers/gpu/drm/i915/intel_device_info.c enabled_mask &= ~BIT(PIPE_A); BIT 938 drivers/gpu/drm/i915/intel_device_info.c enabled_mask &= ~BIT(PIPE_B); BIT 940 drivers/gpu/drm/i915/intel_device_info.c enabled_mask &= ~BIT(PIPE_C); BIT 943 drivers/gpu/drm/i915/intel_device_info.c enabled_mask &= ~BIT(PIPE_D); BIT 1016 drivers/gpu/drm/i915/intel_device_info.c if (!(BIT(i) & vdbox_mask)) { BIT 1017 drivers/gpu/drm/i915/intel_device_info.c info->engine_mask &= ~BIT(_VCS(i)); BIT 1028 drivers/gpu/drm/i915/intel_device_info.c RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); BIT 1038 drivers/gpu/drm/i915/intel_device_info.c if (!(BIT(i) & vebox_mask)) { BIT 1039 drivers/gpu/drm/i915/intel_device_info.c info->engine_mask &= ~BIT(_VECS(i)); BIT 1339 drivers/gpu/drm/i915/intel_pm.c ~BIT(PLANE_CURSOR)); BIT 1356 drivers/gpu/drm/i915/intel_pm.c dirty |= BIT(plane->id); BIT 1380 drivers/gpu/drm/i915/intel_pm.c wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY); BIT 1659 drivers/gpu/drm/i915/intel_pm.c return (active_planes & (BIT(PLANE_SPRITE0) | BIT 1660 drivers/gpu/drm/i915/intel_pm.c BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1); BIT 1669 drivers/gpu/drm/i915/intel_pm.c unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); BIT 1702 drivers/gpu/drm/i915/intel_pm.c if ((active_planes & BIT(plane_id)) == 0) { BIT 1726 drivers/gpu/drm/i915/intel_pm.c if ((active_planes & BIT(plane_id)) == 0) BIT 1860 drivers/gpu/drm/i915/intel_pm.c ~BIT(PLANE_CURSOR)); BIT 1877 drivers/gpu/drm/i915/intel_pm.c dirty |= BIT(plane->id); BIT 1893 drivers/gpu/drm/i915/intel_pm.c if (dirty & ~BIT(PLANE_CURSOR)) { BIT 5302 drivers/gpu/drm/i915/intel_pm.c new_crtc_state->update_planes |= BIT(plane_id); BIT 5594 drivers/gpu/drm/i915/intel_pm.c new_crtc_state->update_planes |= BIT(plane_id); BIT 7783 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_PUNIT) | BIT 7784 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_NC) | BIT 7785 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_CCK)); BIT 7826 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_PUNIT) | BIT 7827 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_NC) | BIT 7828 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_CCK)); BIT 7839 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_PUNIT) | BIT 7840 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_NC) | BIT 7841 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_CCK)); BIT 7879 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_PUNIT) | BIT 7880 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_NC) | BIT 7881 drivers/gpu/drm/i915/intel_pm.c BIT(VLV_IOSF_SB_CCK)); BIT 8683 drivers/gpu/drm/i915/intel_pm.c if (params & BIT(31)) { /* OC supported */ BIT 78 drivers/gpu/drm/i915/intel_sideband.c if (ports & BIT(VLV_IOSF_SB_PUNIT)) BIT 88 drivers/gpu/drm/i915/intel_sideband.c if (ports & BIT(VLV_IOSF_SB_PUNIT)) BIT 298 drivers/gpu/drm/i915/intel_sideband.c cmd |= BIT(8); BIT 36 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT)); BIT 44 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT)); BIT 49 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK)); BIT 57 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK)); BIT 62 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU)); BIT 70 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU)); BIT 75 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO)); BIT 84 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO)); BIT 89 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI)); BIT 97 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI)); BIT 102 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC)); BIT 109 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC)); BIT 114 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT)); BIT 122 drivers/gpu/drm/i915/intel_sideband.h vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT)); BIT 1394 drivers/gpu/drm/i915/intel_uncore.c d->mask = BIT(domain_id); BIT 1399 drivers/gpu/drm/i915/intel_uncore.c uncore->fw_domains |= BIT(domain_id); BIT 1419 drivers/gpu/drm/i915/intel_uncore.c uncore->fw_domains &= ~BIT(domain_id); BIT 1773 drivers/gpu/drm/i915/intel_uncore.c if (fw_domains & BIT(domain_id)) BIT 1783 drivers/gpu/drm/i915/intel_uncore.c if (fw_domains & BIT(domain_id)) BIT 61 drivers/gpu/drm/i915/intel_uncore.h FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER), BIT 62 drivers/gpu/drm/i915/intel_uncore.h FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER), BIT 63 drivers/gpu/drm/i915/intel_uncore.h FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA), BIT 64 drivers/gpu/drm/i915/intel_uncore.h FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0), BIT 65 drivers/gpu/drm/i915/intel_uncore.h FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1), BIT 66 drivers/gpu/drm/i915/intel_uncore.h FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2), BIT 67 drivers/gpu/drm/i915/intel_uncore.h FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3), BIT 68 drivers/gpu/drm/i915/intel_uncore.h FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0), BIT 69 drivers/gpu/drm/i915/intel_uncore.h FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1), BIT 71 drivers/gpu/drm/i915/intel_uncore.h FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1 BIT 118 drivers/gpu/drm/i915/intel_uncore.h #define UNCORE_HAS_FORCEWAKE BIT(0) BIT 119 drivers/gpu/drm/i915/intel_uncore.h #define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1) BIT 120 drivers/gpu/drm/i915/intel_uncore.h #define UNCORE_HAS_DBG_UNCLAIMED BIT(2) BIT 121 drivers/gpu/drm/i915/intel_uncore.h #define UNCORE_HAS_FIFO BIT(3) BIT 34 drivers/gpu/drm/i915/intel_wakeref.h #define INTEL_WAKEREF_PUT_ASYNC BIT(0) BIT 70 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c rem = round_up(obj->base.size, BIT(31)) >> 31; BIT 79 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c unsigned long len = min_t(typeof(rem), rem, BIT(31)); BIT 42 drivers/gpu/drm/i915/selftests/i915_syncmap.c if (last & BIT(depth - d - 1)) BIT 432 drivers/gpu/drm/i915/selftests/i915_syncmap.c if (sync->bitmap != BIT(idx + 1) - 1) { BIT 436 drivers/gpu/drm/i915/selftests/i915_syncmap.c BIT(idx + 1) - 1, idx + 1); BIT 498 drivers/gpu/drm/i915/selftests/i915_syncmap.c if (sync->bitmap != BIT(KSYNCMAP) - 1) { BIT 501 drivers/gpu/drm/i915/selftests/i915_syncmap.c BIT(KSYNCMAP) - 1, KSYNCMAP); BIT 530 drivers/gpu/drm/i915/selftests/i915_syncmap.c if (leaf->bitmap != BIT(idx)) { BIT 203 drivers/gpu/drm/i915/selftests/mock_gem_device.c mkwrite_device_info(i915)->engine_mask = BIT(0); BIT 199 drivers/gpu/drm/i915/selftests/scatterlist.c BIT(12) >> PAGE_SHIFT, BIT 200 drivers/gpu/drm/i915/selftests/scatterlist.c BIT(16) >> PAGE_SHIFT, BIT 201 drivers/gpu/drm/i915/selftests/scatterlist.c BIT(21) >> PAGE_SHIFT, BIT 283 drivers/gpu/drm/i915/selftests/scatterlist.c unsigned long size = BIT(prime); BIT 38 drivers/gpu/drm/imx/imx-tve.c #define TVE_SYNC_CH_2_EN BIT(22) BIT 39 drivers/gpu/drm/imx/imx-tve.c #define TVE_SYNC_CH_1_EN BIT(21) BIT 40 drivers/gpu/drm/imx/imx-tve.c #define TVE_SYNC_CH_0_EN BIT(20) BIT 52 drivers/gpu/drm/imx/imx-tve.c #define TVE_P2I_CONV_EN BIT(7) BIT 53 drivers/gpu/drm/imx/imx-tve.c #define TVE_INP_VIDEO_FORM BIT(6) BIT 62 drivers/gpu/drm/imx/imx-tve.c #define TVE_IPU_CLK_EN BIT(3) BIT 69 drivers/gpu/drm/imx/imx-tve.c #define TVE_EN BIT(0) BIT 75 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_CH_2_SM_EN BIT(22) BIT 76 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_CH_1_SM_EN BIT(21) BIT 77 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_CH_0_SM_EN BIT(20) BIT 78 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_CH_2_LM_EN BIT(18) BIT 79 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_CH_1_LM_EN BIT(17) BIT 80 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_CH_0_LM_EN BIT(16) BIT 81 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_CH_2_REF_LVL BIT(10) BIT 82 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_CH_1_REF_LVL BIT(9) BIT 83 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_CH_0_REF_LVL BIT(8) BIT 84 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_EN BIT(0) BIT 87 drivers/gpu/drm/imx/imx-tve.c #define TVE_FRAME_END_IEN BIT(13) BIT 88 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_MON_END_IEN BIT(2) BIT 89 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_SM_IEN BIT(1) BIT 90 drivers/gpu/drm/imx/imx-tve.c #define TVE_CD_LM_IEN BIT(0) BIT 280 drivers/gpu/drm/imx/ipuv3-crtc.c encoder_types |= BIT(encoder->encoder_type); BIT 291 drivers/gpu/drm/imx/ipuv3-crtc.c if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) | BIT 292 drivers/gpu/drm/imx/ipuv3-crtc.c BIT(DRM_MODE_ENCODER_LVDS))) BIT 294 drivers/gpu/drm/imx/ipuv3-crtc.c else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC)) BIT 54 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_SLCD BIT(31) BIT 55 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_PS_DISABLE BIT(23) BIT 56 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_CLS_DISABLE BIT(22) BIT 57 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_SPL_DISABLE BIT(21) BIT 58 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_REV_DISABLE BIT(20) BIT 59 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_HSYNCM BIT(19) BIT 60 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_PCLKM BIT(18) BIT 61 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_INV BIT(17) BIT 62 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_SYNC_DIR BIT(16) BIT 63 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_PS_POLARITY BIT(15) BIT 64 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_CLS_POLARITY BIT(14) BIT 65 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_SPL_POLARITY BIT(13) BIT 66 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_REV_POLARITY BIT(12) BIT 67 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) BIT 68 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) BIT 69 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) BIT 70 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) BIT 71 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_18_BIT BIT(7) BIT 72 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) BIT 75 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7) BIT 76 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6) BIT 111 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_RGB555 BIT(27) BIT 112 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_OFUP BIT(26) BIT 117 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_EOF_IRQ BIT(13) BIT 118 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_SOF_IRQ BIT(12) BIT 119 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_OFU_IRQ BIT(11) BIT 120 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_IFU0_IRQ BIT(10) BIT 121 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_IFU1_IRQ BIT(9) BIT 122 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_DD_IRQ BIT(8) BIT 123 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_QDD_IRQ BIT(7) BIT 124 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6) BIT 125 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_LSB_FISRT BIT(5) BIT 126 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_DISABLE BIT(4) BIT 127 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CTRL_ENABLE BIT(3) BIT 136 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CMD_SOF_IRQ BIT(31) BIT 137 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CMD_EOF_IRQ BIT(30) BIT 138 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_CMD_ENABLE_PAL BIT(28) BIT 142 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_STATE_EOF_IRQ BIT(5) BIT 143 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_STATE_SOF_IRQ BIT(4) BIT 144 drivers/gpu/drm/ingenic/ingenic-drm.c #define JZ_LCD_STATE_DISABLED BIT(0) BIT 16 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PMU_POWER_GP0_MASK BIT(0) BIT 17 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PMU_POWER_L2_MASK BIT(1) BIT 18 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PMU_POWER_PP_MASK(i) BIT(2 + i) BIT 25 drivers/gpu/drm/lima/lima_regs.h #define LIMA450_PMU_POWER_PP0_MASK BIT(1) BIT 26 drivers/gpu/drm/lima/lima_regs.h #define LIMA450_PMU_POWER_PP13_MASK BIT(2) BIT 27 drivers/gpu/drm/lima/lima_regs.h #define LIMA450_PMU_POWER_PP47_MASK BIT(3) BIT 33 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PMU_INT_CMD_MASK BIT(0) BIT 39 drivers/gpu/drm/lima/lima_regs.h #define LIMA_L2_CACHE_STATUS_COMMAND_BUSY BIT(0) BIT 40 drivers/gpu/drm/lima/lima_regs.h #define LIMA_L2_CACHE_STATUS_DATA_BUSY BIT(1) BIT 42 drivers/gpu/drm/lima/lima_regs.h #define LIMA_L2_CACHE_COMMAND_CLEAR_ALL BIT(0) BIT 46 drivers/gpu/drm/lima/lima_regs.h #define LIMA_L2_CACHE_ENABLE_ACCESS BIT(0) BIT 47 drivers/gpu/drm/lima/lima_regs.h #define LIMA_L2_CACHE_ENABLE_READ_ALLOCATE BIT(1) BIT 61 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_CMD_START_VS BIT(0) BIT 62 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_CMD_START_PLBU BIT(1) BIT 63 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_CMD_UPDATE_PLBU_ALLOC BIT(4) BIT 64 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_CMD_RESET BIT(5) BIT 65 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_CMD_FORCE_HANG BIT(6) BIT 66 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_CMD_STOP_BUS BIT(9) BIT 67 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_CMD_SOFT_RESET BIT(10) BIT 72 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_VS_END_CMD_LST BIT(0) BIT 73 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_PLBU_END_CMD_LST BIT(1) BIT 74 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_PLBU_OUT_OF_MEM BIT(2) BIT 75 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_VS_SEM_IRQ BIT(3) BIT 76 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_PLBU_SEM_IRQ BIT(4) BIT 77 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_HANG BIT(5) BIT 78 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_FORCE_HANG BIT(6) BIT 79 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_PERF_CNT_0_LIMIT BIT(7) BIT 80 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_PERF_CNT_1_LIMIT BIT(8) BIT 81 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_WRITE_BOUND_ERR BIT(9) BIT 82 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_SYNC_ERROR BIT(10) BIT 83 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_AXI_BUS_ERROR BIT(11) BIT 84 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_AXI_BUS_STOPPED BIT(12) BIT 85 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_VS_INVALID_CMD BIT(13) BIT 86 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_PLB_INVALID_CMD BIT(14) BIT 87 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_RESET_COMPLETED BIT(19) BIT 88 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW BIT(20) BIT 89 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_SEMAPHORE_OVERFLOW BIT(21) BIT 90 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS BIT(22) BIT 100 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_STATUS_VS_ACTIVE BIT(1) BIT 101 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_STATUS_BUS_STOPPED BIT(2) BIT 102 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_STATUS_PLBU_ACTIVE BIT(3) BIT 103 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_STATUS_BUS_ERROR BIT(6) BIT 104 drivers/gpu/drm/lima/lima_regs.h #define LIMA_GP_STATUS_WRITE_BOUND_ERR BIT(8) BIT 164 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_STATUS_RENDERING_ACTIVE BIT(0) BIT 165 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_STATUS_BUS_STOPPED BIT(4) BIT 167 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_CTRL_STOP_BUS BIT(0) BIT 168 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_CTRL_FLUSH_CACHES BIT(3) BIT 169 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_CTRL_FORCE_RESET BIT(5) BIT 170 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_CTRL_START_RENDERING BIT(6) BIT 171 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_CTRL_SOFT_RESET BIT(7) BIT 176 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_END_OF_FRAME BIT(0) BIT 177 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_END_OF_TILE BIT(1) BIT 178 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_HANG BIT(2) BIT 179 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_FORCE_HANG BIT(3) BIT 180 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_BUS_ERROR BIT(4) BIT 181 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_BUS_STOP BIT(5) BIT 182 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_CNT_0_LIMIT BIT(6) BIT 183 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_CNT_1_LIMIT BIT(7) BIT 184 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR BIT(8) BIT 185 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_INVALID_PLIST_COMMAND BIT(9) BIT 186 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_CALL_STACK_UNDERFLOW BIT(10) BIT 187 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_CALL_STACK_OVERFLOW BIT(11) BIT 188 drivers/gpu/drm/lima/lima_regs.h #define LIMA_PP_IRQ_RESET_COMPLETED BIT(12) BIT 235 drivers/gpu/drm/lima/lima_regs.h #define LIMA_MMU_STATUS_PAGING_ENABLED BIT(0) BIT 236 drivers/gpu/drm/lima/lima_regs.h #define LIMA_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) BIT 237 drivers/gpu/drm/lima/lima_regs.h #define LIMA_MMU_STATUS_STALL_ACTIVE BIT(2) BIT 238 drivers/gpu/drm/lima/lima_regs.h #define LIMA_MMU_STATUS_IDLE BIT(3) BIT 239 drivers/gpu/drm/lima/lima_regs.h #define LIMA_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) BIT 240 drivers/gpu/drm/lima/lima_regs.h #define LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) BIT 255 drivers/gpu/drm/lima/lima_regs.h #define LIMA_MMU_INT_PAGE_FAULT BIT(0) BIT 256 drivers/gpu/drm/lima/lima_regs.h #define LIMA_MMU_INT_READ_BUS_ERROR BIT(1) BIT 259 drivers/gpu/drm/lima/lima_regs.h #define LIMA_VM_FLAG_PRESENT BIT(0) BIT 260 drivers/gpu/drm/lima/lima_regs.h #define LIMA_VM_FLAG_READ_PERMISSION BIT(1) BIT 261 drivers/gpu/drm/lima/lima_regs.h #define LIMA_VM_FLAG_WRITE_PERMISSION BIT(2) BIT 262 drivers/gpu/drm/lima/lima_regs.h #define LIMA_VM_FLAG_OVERRIDE_CACHE BIT(3) BIT 263 drivers/gpu/drm/lima/lima_regs.h #define LIMA_VM_FLAG_WRITE_CACHEABLE BIT(4) BIT 264 drivers/gpu/drm/lima/lima_regs.h #define LIMA_VM_FLAG_WRITE_ALLOCATE BIT(5) BIT 265 drivers/gpu/drm/lima/lima_regs.h #define LIMA_VM_FLAG_WRITE_BUFFERABLE BIT(6) BIT 266 drivers/gpu/drm/lima/lima_regs.h #define LIMA_VM_FLAG_READ_CACHEABLE BIT(7) BIT 267 drivers/gpu/drm/lima/lima_regs.h #define LIMA_VM_FLAG_READ_ALLOCATE BIT(8) BIT 11 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_PP_VCMPA BIT(0) BIT 12 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_PP_VCMPB BIT(1) BIT 13 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_PP_VSCC0 BIT(2) BIT 14 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_PP_VSCC1 BIT(3) BIT 15 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_PP_VCMPC0 BIT(4) BIT 16 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_PP_VCMPC1 BIT(5) BIT 17 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_PP_ROTFD_A BIT(6) BIT 18 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_PP_ROTFD_B BIT(7) BIT 75 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_EXTSRCXCONF_BGR BIT(12) BIT 76 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_EXTSRCXCONF_BEBO BIT(13) BIT 77 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_EXTSRCXCONF_BEPO BIT(14) BIT 97 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_EXTSRCXCR_MULTIOVL_CTRL_PRIMARY BIT(2) /* 0 = all */ BIT 98 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_EXTSRCXCR_FS_DIV_DISABLE BIT(3) BIT 99 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_EXTSRCXCR_FORCE_FS_DIV BIT(4) BIT 111 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_OVLXCR_OVLEN BIT(0) BIT 115 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_OVLXCR_CKEYGEN BIT(3) BIT 116 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_OVLXCR_ALPHAPMEN BIT(4) BIT 117 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_OVLXCR_OVLF BIT(5) BIT 118 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_OVLXCR_OVLR BIT(6) BIT 119 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_OVLXCR_OVLB BIT(7) BIT 176 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_OVLXCONF2_BP_CONSTANT_ALPHA BIT(0) BIT 179 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_OVLXCONF2_OPQ BIT(9) BIT 219 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_C1EN BIT(2) BIT 220 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_C2EN BIT(3) BIT 221 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_SYCEN0 BIT(7) BIT 222 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_SYCEN1 BIT(8) BIT 223 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_SIZE1 BIT(9) BIT 224 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_SIZE2 BIT(10) BIT 225 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_YUVCONVC1EN BIT(15) BIT 226 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_CS1EN BIT(16) BIT 227 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_CS2EN BIT(17) BIT 228 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_CS1POL BIT(19) BIT 229 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_CS2POL BIT(20) BIT 230 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_CD1POL BIT(21) BIT 231 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_CD2POL BIT(22) BIT 232 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_WR1POL BIT(23) BIT 233 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_WR2POL BIT(24) BIT 234 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_RD1POL BIT(25) BIT 235 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_RD2POL BIT(26) BIT 242 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRC_CLAMPC1EN BIT(31) BIT 259 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_VSCRC_VSPOL BIT(27) /* 0 active high, 1 active low */ BIT 260 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_VSCRC_VSSEL BIT(28) /* 0 VSYNC0, 1 VSYNC1 */ BIT 261 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_VSCRC_VSDBL BIT(29) BIT 279 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CHNLXSTAT_CHNLRD BIT(0) BIT 280 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CHNLXSTAT_CHNLA BIT(1) BIT 281 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CHNLXSTAT_CHNLBLBCKGND_EN BIT(16) BIT 282 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CHNLXSTAT_PPLX2_V422 BIT(17) BIT 283 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CHNLXSTAT_LPFX2_V422 BIT(18) BIT 307 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CHNLXSYNCHSW_SW_TRIG BIT(0) BIT 332 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_FLOEN BIT(0) BIT 333 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_POWEREN BIT(1) BIT 334 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_BLENDEN BIT(2) BIT 335 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_AFLICKEN BIT(3) BIT 336 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_PALEN BIT(4) BIT 337 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_DITHEN BIT(5) BIT 338 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_GAMEN BIT(6) BIT 346 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_BLENDCTRL BIT(10) BIT 352 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_FLOCKFORMAT_RGB BIT(13) /* 0 = YCVCR */ BIT 353 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_PALMODE_GAMMA BIT(14) /* 0 = palette */ BIT 354 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_OLEDEN BIT(15) BIT 357 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX0_ROTEN BIT(24) BIT 393 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRX1_BCD BIT(29) BIT 394 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CRA1_CLKTYPE_TVXCLKSEL1 BIT(30) /* 0 = TVXCLKSEL1 */ BIT 432 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CTRLX_FIFOEMPTY BIT(12) BIT 433 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_CTRLX_FIFOFULL BIT(13) BIT 459 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_DSICONF0_VID_MODE_VID BIT(12) BIT 460 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_DSICONF0_CMD8 BIT(13) BIT 461 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_DSICONF0_BIT_SWAP BIT(16) BIT 462 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_DSICONF0_BYTE_SWAP BIT(17) BIT 463 drivers/gpu/drm/mcde/mcde_display_regs.h #define MCDE_DSICONF0_DCSVID_NOTGEN BIT(18) BIT 86 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CR_IFIFOCTRLEN BIT(15) BIT 87 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CR_UFRECOVERY_MODE_V422 BIT(16) BIT 88 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CR_WRAP_MODE_V422_SHIFT BIT(17) BIT 89 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CR_AUTOCLKG_EN BIT(30) BIT 90 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CR_MCDEEN BIT(31) BIT 93 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CONF0_SYNCMUX0 BIT(0) BIT 94 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CONF0_SYNCMUX1 BIT(1) BIT 95 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CONF0_SYNCMUX2 BIT(2) BIT 96 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CONF0_SYNCMUX3 BIT(3) BIT 97 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CONF0_SYNCMUX4 BIT(4) BIT 98 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CONF0_SYNCMUX5 BIT(5) BIT 99 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CONF0_SYNCMUX6 BIT(6) BIT 100 drivers/gpu/drm/mcde/mcde_drv.c #define MCDE_CONF0_SYNCMUX7 BIT(7) BIT 34 drivers/gpu/drm/mcde/mcde_dsi.c #define PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0) BIT 35 drivers/gpu/drm/mcde/mcde_dsi.c #define PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1) BIT 36 drivers/gpu/drm/mcde/mcde_dsi.c #define PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2) BIT 8 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0) BIT 9 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1) BIT 10 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2) BIT 11 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3) BIT 12 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4) BIT 13 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5) BIT 14 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6) BIT 15 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7) BIT 16 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8) BIT 17 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_BTA_EN BIT(9) BIT 18 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC BIT(10) BIT 19 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM BIT(11) BIT 20 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN BIT(12) BIT 21 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN BIT(13) BIT 22 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_DLX_REMAP_EN BIT(14) BIT 23 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_DATA_CTL_TE_POLLING_EN BIT(15) BIT 26 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0) BIT 27 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE BIT(1) BIT 28 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS BIT(2) BIT 29 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN BIT(3) BIT 30 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN BIT(4) BIT 31 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN BIT(5) BIT 34 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_PHY_CTL_CLOCK_FORCE_STOP_MODE BIT(10) BIT 54 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK BIT(0) BIT 55 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK BIT(1) BIT 56 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1 BIT(2) BIT 57 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1 BIT(3) BIT 58 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2 BIT(4) BIT 59 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2 BIT(5) BIT 64 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_EN_PLL_START BIT(0) BIT 65 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_EN_CKLANE_EN BIT(3) BIT 66 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_EN_DAT1_EN BIT(4) BIT 67 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_EN_DAT2_EN BIT(5) BIT 68 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ BIT(6) BIT 69 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ BIT(7) BIT 70 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ BIT(8) BIT 71 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_EN_IF1_EN BIT(9) BIT 72 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_EN_IF2_EN BIT(10) BIT 75 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_STS_PLL_LOCK BIT(0) BIT 76 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_STS_CLKLANE_READY BIT(1) BIT 77 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_STS_DAT1_READY BIT(2) BIT 78 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_STS_DAT2_READY BIT(3) BIT 79 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_STS_HSTX_TO_ERR BIT(4) BIT 80 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_STS_LPRX_TO_ERR BIT(5) BIT 81 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK BIT(6) BIT 82 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK BIT(7) BIT 96 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_CTL_IF1_LP_EN BIT(4) BIT 97 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_CTL_IF2_LP_EN BIT(5) BIT 98 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_CTL_ARB_MODE BIT(6) BIT 99 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_CTL_ARB_PRI BIT(7) BIT 106 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_ERR_NO_TE BIT(0) BIT 107 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_ERR_TE_MISS BIT(1) BIT 108 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN BIT(2) BIT 109 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN BIT(3) BIT 110 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_ERR_UNWANTED_RD BIT(4) BIT 111 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CSM_RUNNING BIT(5) BIT 123 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT BIT(3) BIT 139 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN BIT(21) BIT 144 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION BIT(0) BIT 145 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_WRITE_COMPLETED BIT(1) BIT 146 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED BIT(2) BIT 147 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_READ_COMPLETED BIT(3) BIT 148 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_SHIFT BIT(4) BIT 149 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED BIT(5) BIT 150 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED BIT(6) BIT 151 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_TE_RECEIVED BIT(7) BIT 152 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_BTA_COMPLETED BIT(8) BIT 153 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_BTA_FINISHED BIT(9) BIT 154 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR BIT(10) BIT 191 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS BIT(12) BIT 192 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE BIT(13) BIT 193 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS (BIT(12) | BIT(13)) BIT 194 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_BURST_MODE BIT(14) BIT 195 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE BIT(15) BIT 196 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL BIT(16) BIT 198 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING BIT(17) BIT 199 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0 BIT(18) BIT 200 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_1 (BIT(17) | BIT(18)) BIT 202 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_BLANKING BIT(19) BIT 203 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 BIT(20) BIT 204 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_1 (BIT(19) | BIT(20)) BIT 250 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_VSG_RUNNING BIT(0) BIT 255 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_VCA_SETTING1_BURST_LP BIT(16) BIT 264 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN BIT(0) BIT 265 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN BIT(1) BIT 266 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN BIT(2) BIT 267 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN BIT(3) BIT 268 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN BIT(4) BIT 269 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN BIT(5) BIT 270 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE BIT(16) BIT 271 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE BIT(17) BIT 272 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE BIT(18) BIT 273 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE BIT(19) BIT 274 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE BIT(20) BIT 275 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE BIT(21) BIT 278 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN BIT(0) BIT 279 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN BIT(1) BIT 280 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN BIT(2) BIT 281 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN BIT(3) BIT 282 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN BIT(4) BIT 283 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN BIT(5) BIT 284 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN BIT(6) BIT 285 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN BIT(7) BIT 286 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN BIT(8) BIT 287 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN BIT(9) BIT 288 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN BIT(10) BIT 289 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE BIT(16) BIT 290 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE BIT(17) BIT 291 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE BIT(18) BIT 292 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE BIT(19) BIT 293 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE BIT(20) BIT 294 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE BIT(21) BIT 295 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE BIT(22) BIT 296 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE BIT(23) BIT 297 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE BIT(24) BIT 298 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE BIT(25) BIT 299 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE BIT(26) BIT 302 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_VSG_RUNNING BIT(0) BIT 303 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA BIT(1) BIT 304 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC BIT(2) BIT 305 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC BIT(3) BIT 306 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH BIT(4) BIT 307 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT BIT(5) BIT 308 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE BIT(6) BIT 309 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE BIT(7) BIT 310 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_LONGREAD BIT(8) BIT 311 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH BIT(9) BIT 312 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE BIT(16) BIT 313 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE BIT(17) BIT 314 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE BIT(18) BIT 315 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE BIT(19) BIT 316 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE BIT(20) BIT 317 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE BIT(21) BIT 318 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE BIT(22) BIT 319 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE BIT(23) BIT 320 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE BIT(24) BIT 321 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE BIT(25) BIT 322 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE BIT(26) BIT 329 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR BIT(0) BIT 330 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR BIT(1) BIT 331 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR BIT(2) BIT 332 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR BIT(3) BIT 333 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR BIT(4) BIT 334 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR BIT(5) BIT 337 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR BIT(0) BIT 338 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR BIT(1) BIT 339 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR BIT(2) BIT 340 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR BIT(3) BIT 341 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR BIT(4) BIT 342 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR BIT(5) BIT 343 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR BIT(6) BIT 344 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR BIT(7) BIT 345 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR BIT(8) BIT 346 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR BIT(9) BIT 347 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR BIT(10) BIT 363 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1 BIT(2) BIT 364 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1 BIT(3) BIT 365 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1 BIT(4) BIT 366 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1 BIT(5) BIT 374 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90 BIT(12) BIT 375 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK BIT(13) BIT 376 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK BIT(14) BIT 377 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK BIT(15) BIT 378 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2 BIT(16) BIT 379 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2 BIT(18) BIT 380 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2 BIT(19) BIT 381 drivers/gpu/drm/mcde/mcde_dsi_regs.h #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2 BIT(20) BIT 16 drivers/gpu/drm/mediatek/mtk_cec.c #define CLEAR_CEC_IRQ BIT(15) BIT 19 drivers/gpu/drm/mediatek/mtk_cec.c #define CEC_32K_PDN BIT(19) BIT 20 drivers/gpu/drm/mediatek/mtk_cec.c #define PDN BIT(16) BIT 23 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_PORD BIT(25) BIT 24 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_HTPLG BIT(24) BIT 25 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_PORD_INT_EN BIT(9) BIT 26 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_HTPLG_INT_EN BIT(8) BIT 29 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_PORD_INT_32K_STATUS BIT(26) BIT 30 drivers/gpu/drm/mediatek/mtk_cec.c #define RX_RISC_INT_32K_STATUS BIT(25) BIT 31 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_HTPLG_INT_32K_STATUS BIT(24) BIT 32 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_PORD_INT_32K_CLR BIT(18) BIT 33 drivers/gpu/drm/mediatek/mtk_cec.c #define RX_INT_32K_CLR BIT(17) BIT 34 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_HTPLG_INT_32K_CLR BIT(16) BIT 35 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_PORD_INT_32K_STA_MASK BIT(10) BIT 36 drivers/gpu/drm/mediatek/mtk_cec.c #define RX_RISC_INT_32K_STA_MASK BIT(9) BIT 37 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_HTPLG_INT_32K_STA_MASK BIT(8) BIT 38 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_PORD_INT_32K_EN BIT(2) BIT 39 drivers/gpu/drm/mediatek/mtk_cec.c #define RX_INT_32K_EN BIT(1) BIT 40 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_HTPLG_INT_32K_EN BIT(0) BIT 43 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_HTPLG_INT_STA BIT(0) BIT 44 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_PORD_INT_STA BIT(1) BIT 45 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_HTPLG_INT_CLR BIT(16) BIT 46 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_PORD_INT_CLR BIT(17) BIT 47 drivers/gpu/drm/mediatek/mtk_cec.c #define HDMI_FULL_INT_CLR BIT(20) BIT 23 drivers/gpu/drm/mediatek/mtk_disp_color.c #define COLOR_BYPASS_ALL BIT(7) BIT 24 drivers/gpu/drm/mediatek/mtk_disp_color.c #define COLOR_SEQ_SEL BIT(13) BIT 17 drivers/gpu/drm/mediatek/mtk_disp_ovl.c #define OVL_FME_CPL_INT BIT(1) BIT 36 drivers/gpu/drm/mediatek/mtk_disp_ovl.c #define OVL_CON_BYTE_SWAP BIT(24) BIT 47 drivers/gpu/drm/mediatek/mtk_disp_ovl.c #define OVL_CON_AEN BIT(8) BIT 140 drivers/gpu/drm/mediatek/mtk_disp_ovl.c reg = reg | BIT(idx); BIT 149 drivers/gpu/drm/mediatek/mtk_disp_ovl.c reg = reg & ~BIT(idx); BIT 18 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_TARGET_LINE_INT BIT(5) BIT 19 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_FIFO_UNDERFLOW_INT BIT(4) BIT 20 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_EOF_ABNORMAL_INT BIT(3) BIT 21 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_FRAME_END_INT BIT(2) BIT 22 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_FRAME_START_INT BIT(1) BIT 23 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_REG_UPDATE_INT BIT(0) BIT 25 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_ENGINE_EN BIT(0) BIT 26 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_MODE_MEMORY BIT(1) BIT 28 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_MATRIX_ENABLE BIT(17) BIT 40 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define MEM_MODE_INPUT_SWAP BIT(8) BIT 44 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_FIFO_UNDERFLOW_EN BIT(31) BIT 607 drivers/gpu/drm/mediatek/mtk_dpi.c dpi->encoder.possible_crtcs = BIT(1); BIT 10 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define EN BIT(0) BIT 13 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define RST BIT(0) BIT 16 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define INT_VSYNC_EN BIT(0) BIT 17 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define INT_VDE_EN BIT(1) BIT 18 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define INT_UNDERFLOW_EN BIT(2) BIT 21 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define INT_VSYNC_STA BIT(0) BIT 22 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define INT_VDE_STA BIT(1) BIT 23 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define INT_UNDERFLOW_STA BIT(2) BIT 26 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define BG_ENABLE BIT(0) BIT 27 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define IN_RB_SWAP BIT(1) BIT 28 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define INTL_EN BIT(2) BIT 29 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define TDFP_EN BIT(3) BIT 30 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define CLPF_EN BIT(4) BIT 31 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define YUV422_EN BIT(5) BIT 32 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define CSC_ENABLE BIT(6) BIT 33 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define R601_SEL BIT(7) BIT 34 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define EMBSYNC_EN BIT(8) BIT 35 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define VS_LODD_EN BIT(16) BIT 36 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define VS_LEVEN_EN BIT(17) BIT 37 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define VS_RODD_EN BIT(18) BIT 38 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define VS_REVEN BIT(19) BIT 39 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define FAKE_DE_LODD BIT(20) BIT 40 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define FAKE_DE_LEVEN BIT(21) BIT 41 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define FAKE_DE_RODD BIT(22) BIT 42 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define FAKE_DE_REVEN BIT(23) BIT 53 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define BIT_SWAP BIT(3) BIT 54 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define B_MASK BIT(4) BIT 55 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define G_MASK BIT(5) BIT 56 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define R_MASK BIT(6) BIT 57 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define DE_MASK BIT(8) BIT 58 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define HS_MASK BIT(9) BIT 59 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define VS_MASK BIT(10) BIT 60 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define DE_POL BIT(12) BIT 61 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define HSYNC_POL BIT(13) BIT 62 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define VSYNC_POL BIT(14) BIT 63 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define CK_POL BIT(15) BIT 64 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define OEN_OFF BIT(16) BIT 65 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define EDGE_SEL BIT(17) BIT 87 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define DDR_EN BIT(0) BIT 88 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define DDDR_SEL BIT(1) BIT 89 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define DDR_4PHASE BIT(2) BIT 109 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define VSYNC_HALF_LINE_MASK BIT(16) BIT 134 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define DPI_BUSY BIT(16) BIT 135 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define OUTEN BIT(17) BIT 136 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define FIELD BIT(20) BIT 137 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define TDLR BIT(21) BIT 140 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define DPI_OEN_ON BIT(0) BIT 144 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define DPI_CHECKSUM_READY BIT(30) BIT 145 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define DPI_CHECKSUM_EN BIT(31) BIT 179 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define ROUND_EN BIT(4) BIT 194 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define UV_SWAP BIT(0) BIT 195 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define CR_DELSEL BIT(4) BIT 196 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define CB_DELSEL BIT(5) BIT 197 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define Y_DELSEL BIT(6) BIT 198 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define DE_DELSEL BIT(7) BIT 201 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define EMBSYNC_R_CR_EN BIT(0) BIT 202 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define EMPSYNC_G_Y_EN BIT(1) BIT 203 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define EMPSYNC_B_CB_EN BIT(2) BIT 204 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define ESAV_F_INV BIT(4) BIT 205 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define ESAV_V_INV BIT(5) BIT 206 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define ESAV_H_INV BIT(6) BIT 207 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define ESAV_CODE_MAN BIT(8) BIT 216 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define ESAV_CODE3_MSB BIT(16) BIT 218 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define EDGE_SEL_EN BIT(5) BIT 219 drivers/gpu/drm/mediatek/mtk_dpi_regs.h #define H_FRE_2N BIT(25) BIT 460 drivers/gpu/drm/mediatek/mtk_drm_crtc.c pending_planes |= BIT(i); BIT 614 drivers/gpu/drm/mediatek/mtk_drm_crtc.c BIT(pipe), type); BIT 43 drivers/gpu/drm/mediatek/mtk_drm_ddp.c #define INT_MUTEX BIT(1) BIT 96 drivers/gpu/drm/mediatek/mtk_drm_ddp.c #define OD1_MOUT_EN_RDMA1 BIT(16) BIT 43 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c #define OD_RELAYMODE BIT(0) BIT 45 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c #define UFO_BYPASS BIT(2) BIT 47 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c #define AAL_EN BIT(0) BIT 49 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c #define GAMMA_EN BIT(0) BIT 50 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c #define GAMMA_LUT_EN BIT(1) BIT 52 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c #define DISP_DITHERING BIT(2) BIT 57 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c #define DITHER_NEW_BIT_MODE BIT(0) BIT 32 drivers/gpu/drm/mediatek/mtk_dsi.c #define LPRX_RD_RDY_INT_FLAG BIT(0) BIT 33 drivers/gpu/drm/mediatek/mtk_dsi.c #define CMD_DONE_INT_FLAG BIT(1) BIT 34 drivers/gpu/drm/mediatek/mtk_dsi.c #define TE_RDY_INT_FLAG BIT(2) BIT 35 drivers/gpu/drm/mediatek/mtk_dsi.c #define VM_DONE_INT_FLAG BIT(3) BIT 36 drivers/gpu/drm/mediatek/mtk_dsi.c #define EXT_TE_RDY_INT_FLAG BIT(4) BIT 37 drivers/gpu/drm/mediatek/mtk_dsi.c #define DSI_BUSY BIT(31) BIT 40 drivers/gpu/drm/mediatek/mtk_dsi.c #define DSI_RESET BIT(0) BIT 41 drivers/gpu/drm/mediatek/mtk_dsi.c #define DSI_EN BIT(1) BIT 49 drivers/gpu/drm/mediatek/mtk_dsi.c #define FRM_MODE BIT(16) BIT 50 drivers/gpu/drm/mediatek/mtk_dsi.c #define MIX_MODE BIT(17) BIT 53 drivers/gpu/drm/mediatek/mtk_dsi.c #define VC_NUM BIT(1) BIT 55 drivers/gpu/drm/mediatek/mtk_dsi.c #define DIS_EOT BIT(6) BIT 56 drivers/gpu/drm/mediatek/mtk_dsi.c #define NULL_EN BIT(7) BIT 57 drivers/gpu/drm/mediatek/mtk_dsi.c #define TE_FREERUN BIT(8) BIT 58 drivers/gpu/drm/mediatek/mtk_dsi.c #define EXT_TE_EN BIT(9) BIT 59 drivers/gpu/drm/mediatek/mtk_dsi.c #define EXT_TE_EDGE BIT(10) BIT 61 drivers/gpu/drm/mediatek/mtk_dsi.c #define HSTX_CKLP_EN BIT(16) BIT 90 drivers/gpu/drm/mediatek/mtk_dsi.c #define RACK BIT(0) BIT 93 drivers/gpu/drm/mediatek/mtk_dsi.c #define LC_HS_TX_EN BIT(0) BIT 94 drivers/gpu/drm/mediatek/mtk_dsi.c #define LC_ULPM_EN BIT(1) BIT 95 drivers/gpu/drm/mediatek/mtk_dsi.c #define LC_WAKEUP_EN BIT(2) BIT 98 drivers/gpu/drm/mediatek/mtk_dsi.c #define LD0_HS_TX_EN BIT(0) BIT 99 drivers/gpu/drm/mediatek/mtk_dsi.c #define LD0_ULPM_EN BIT(1) BIT 100 drivers/gpu/drm/mediatek/mtk_dsi.c #define LD0_WAKEUP_EN BIT(2) BIT 125 drivers/gpu/drm/mediatek/mtk_dsi.c #define VM_CMD_EN BIT(0) BIT 126 drivers/gpu/drm/mediatek/mtk_dsi.c #define TS_VFP_EN BIT(5) BIT 132 drivers/gpu/drm/mediatek/mtk_dsi.c #define BTA BIT(2) BIT 24 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c #define DDCM_ODRAIN BIT(31) BIT 27 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c #define DDCM_CS_STATUS BIT(4) BIT 28 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c #define DDCM_SCL_STATE BIT(3) BIT 29 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c #define DDCM_SDA_STATE BIT(2) BIT 30 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c #define DDCM_SM0EN BIT(1) BIT 31 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c #define DDCM_SCL_STRECH BIT(0) BIT 44 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c #define DDCM_TRI BIT(0) BIT 12 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define LR_SWAP BIT(0) BIT 13 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define LFE_CC_SWAP BIT(1) BIT 14 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define LSRS_SWAP BIT(2) BIT 15 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define RLS_RRS_SWAP BIT(3) BIT 16 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define LR_STATUS_SWAP BIT(4) BIT 23 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define I2S_UV_V BIT(0) BIT 24 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define I2S_UV_U BIT(1) BIT 26 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define I2S_UV_CH_EN(x) BIT((x) + 2) BIT 27 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define I2S_UV_TMDS_DEBUG BIT(6) BIT 28 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define I2S_UV_NORMAL_INFO_INV BIT(7) BIT 30 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define VS_EN BIT(0) BIT 31 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define ACP_EN BIT(1) BIT 32 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define ISRC1_EN BIT(2) BIT 33 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define ISRC2_EN BIT(3) BIT 34 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define GAMUT_EN BIT(4) BIT 36 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CTS_CTRL_SOFT BIT(0) BIT 38 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define INT_MDI BIT(0) BIT 39 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define INT_HDCP BIT(1) BIT 40 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define INT_FIFO_O BIT(2) BIT 41 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define INT_FIFO_U BIT(3) BIT 42 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define INT_IFM_ERR BIT(4) BIT 43 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define INT_INF_DONE BIT(5) BIT 44 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define INT_NCTS_DONE BIT(6) BIT 45 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define INT_CTRL_PKT_DONE BIT(7) BIT 48 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CTRL_GEN_EN BIT(2) BIT 49 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CTRL_SPD_EN BIT(3) BIT 50 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CTRL_MPEG_EN BIT(4) BIT 51 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CTRL_AUDIO_EN BIT(5) BIT 52 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CTRL_AVI_EN BIT(6) BIT 53 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CTRL_AVMUTE BIT(7) BIT 55 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define STATUS_HTPLG BIT(0) BIT 56 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define STATUS_PORD BIT(1) BIT 58 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define NCTS_WRI_ANYTIME BIT(6) BIT 60 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define AUDIO_ZERO BIT(0) BIT 61 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define HIGH_BIT_RATE BIT(1) BIT 62 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define SACD_DST BIT(2) BIT 63 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define DST_NORMAL_DOUBLE BIT(3) BIT 64 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define DSD_INV BIT(4) BIT 65 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define LR_INV BIT(5) BIT 66 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define LR_MIX BIT(6) BIT 67 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define DSD_SEL BIT(7) BIT 77 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define MIX_CTRL_SRC_EN BIT(0) BIT 78 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define BYPASS_VOLUME BIT(1) BIT 79 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define MIX_CTRL_FLAT BIT(7) BIT 85 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define AOUT_FIFO_ADAP_CTRL BIT(6) BIT 86 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define AOUT_BURST_PREAMBLE_EN BIT(7) BIT 91 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define AUDIO_PACKET_OFF BIT(6) BIT 101 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG1_EDG_SEL BIT(0) BIT 102 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG1_SPDIF BIT(1) BIT 103 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG1_DVI BIT(2) BIT 104 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG1_HDCP_DEBUG BIT(3) BIT 106 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG2_MHL_DE_SEL BIT(3) BIT 107 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG2_MHL_FAKE_DE_SEL BIT(4) BIT 108 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG2_MHL_DATA_REMAP BIT(5) BIT 109 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG2_NOTICE_EN BIT(6) BIT 110 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG2_ACLK_INV BIT(7) BIT 113 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG3_CONTROL_PACKET_DELAY BIT(6) BIT 114 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG3_KSV_LOAD_START BIT(7) BIT 116 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG4_AES_KEY_LOAD BIT(4) BIT 117 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG4_AV_UNMUTE_EN BIT(5) BIT 118 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG4_AV_UNMUTE_SET BIT(6) BIT 119 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG4_MHL_MODE BIT(7) BIT 131 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define AUDIO_I2S_NCTS_SEL BIT(1) BIT 134 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define NEW_GCP_CTRL BIT(0) BIT 135 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define NEW_GCP_CTRL_MERGE BIT(0) BIT 186 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define ABIST_EN BIT(7) BIT 193 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define VIDEO_SOURCE_SEL BIT(7) BIT 198 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define HDMI_ON BIT(0) BIT 199 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define HDMI_RST BIT(1) BIT 200 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define ANLG_ON BIT(2) BIT 201 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define CFG10_DVI BIT(3) BIT 202 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define HDMI_TST BIT(3) BIT 205 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define AUD_OUTSYNC_EN BIT(24) BIT 206 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define AUD_OUTSYNC_PRE_EN BIT(25) BIT 207 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define I2CM_ON BIT(26) BIT 208 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define E2PROM_TYPE_8BIT BIT(27) BIT 209 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define MCM_E2PROM_ON BIT(28) BIT 210 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define EXT_E2PROM_ON BIT(29) BIT 211 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define HTPLG_PIN_SEL_OFF BIT(30) BIT 212 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define AES_EFUSE_ENABLE BIT(31) BIT 219 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define DEEP_COLOR_EN BIT(0) BIT 220 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define HDMI_AUDIO_TEST_SEL BIT(8) BIT 221 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define HDMI2P0_EN BIT(11) BIT 222 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define HDMI_OUT_FIFO_EN BIT(16) BIT 223 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define HDMI_OUT_FIFO_CLK_INV BIT(17) BIT 224 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define MHL_MODE_ON BIT(28) BIT 225 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define MHL_PP_MODE BIT(29) BIT 226 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define MHL_SYNC_AUTO_EN BIT(30) BIT 227 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h #define HDMI_PCLK_FREE_RUN BIT(31) BIT 16 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LDOCORE_EN BIT(0) BIT 17 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_CKG_LDOOUT_EN BIT(1) BIT 21 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_DSICLK_FREQ_SEL BIT(10) BIT 22 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LPTX_CLMP_EN BIT(11) BIT 29 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNTx_LDOOUT_EN BIT(0) BIT 30 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNTx_CKLANE_EN BIT(1) BIT 31 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2) BIT 32 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3) BIT 33 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNTx_LPTX_IMINUS BIT(4) BIT 34 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNTx_LPCD_IPLUS BIT(5) BIT 35 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNTx_LPCD_IMINUS BIT(6) BIT 39 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNT_INTR_EN BIT(0) BIT 40 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNT_HS_BIAS_EN BIT(1) BIT 41 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNT_IMP_CAL_EN BIT(2) BIT 42 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_LNT_TESTMODE_EN BIT(3) BIT 45 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_PAD_TIE_LOW_EN BIT(11) BIT 46 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_DEBUG_INPUT_EN BIT(12) BIT 50 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_BG_CORE_EN BIT(0) BIT 51 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_BG_CKEN BIT(1) BIT 53 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_BG_FAST_CHARGE BIT(4) BIT 65 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_MPPLL_PLL_EN BIT(0) BIT 71 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_MPPLL_MONVC_EN BIT(10) BIT 72 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_MPPLL_MONREF_EN BIT(11) BIT 73 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_MPPLL_VOD_EN BIT(12) BIT 76 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_MPPLL_SDM_FRA_EN BIT(0) BIT 77 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1) BIT 78 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_MPPLL_SDM_SSC_EN BIT(2) BIT 87 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0) BIT 88 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_MPPLL_SDM_ISO_EN BIT(1) BIT 89 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8) BIT 92 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_CTRL_EN BIT(0) BIT 95 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNTC_LPTX_PRE_OE BIT(0) BIT 96 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNTC_LPTX_OE BIT(1) BIT 97 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNTC_LPTX_P BIT(2) BIT 98 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNTC_LPTX_N BIT(3) BIT 99 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNTC_HSTX_PRE_OE BIT(4) BIT 100 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNTC_HSTX_OE BIT(5) BIT 101 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNTC_HSTX_ZEROCLK BIT(6) BIT 102 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT0_LPTX_PRE_OE BIT(7) BIT 103 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT0_LPTX_OE BIT(8) BIT 104 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT0_LPTX_P BIT(9) BIT 105 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT0_LPTX_N BIT(10) BIT 106 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT0_HSTX_PRE_OE BIT(11) BIT 107 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT0_HSTX_OE BIT(12) BIT 108 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT0_LPRX_EN BIT(13) BIT 109 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT1_LPTX_PRE_OE BIT(14) BIT 110 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT1_LPTX_OE BIT(15) BIT 111 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT1_LPTX_P BIT(16) BIT 112 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT1_LPTX_N BIT(17) BIT 113 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT1_HSTX_PRE_OE BIT(18) BIT 114 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT1_HSTX_OE BIT(19) BIT 115 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT2_LPTX_PRE_OE BIT(20) BIT 116 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT2_LPTX_OE BIT(21) BIT 117 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT2_LPTX_P BIT(22) BIT 118 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT2_LPTX_N BIT(23) BIT 119 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT2_HSTX_PRE_OE BIT(24) BIT 120 drivers/gpu/drm/mediatek/mtk_mipi_tx.c #define SW_LNT2_HSTX_OE BIT(25) BIT 10 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_EN BIT(31) BIT 33 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_AUTOK_EN BIT(28) BIT 36 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_AUTOK_LOAD BIT(23) BIT 38 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_REF_SEL BIT(15) BIT 39 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_BIAS_EN BIT(14) BIT 40 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13) BIT 41 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_TXDIV_EN BIT(12) BIT 44 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_LVROD_EN BIT(9) BIT 45 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_MONVC_EN BIT(8) BIT 46 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_MONCK_EN BIT(7) BIT 47 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_MONREF_EN BIT(6) BIT 48 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_TST_EN BIT(5) BIT 49 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_PLL_TST_CK_EN BIT(4) BIT 53 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1) BIT 54 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_EN_TX_CKLDO BIT(0) BIT 62 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_MHLCK_FORCE BIT(10) BIT 63 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_MHLCK_PPIX_EN BIT(9) BIT 64 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_MHLCK_EN BIT(8) BIT 66 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_SER_5T1_BIST_EN BIT(3) BIT 67 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_SER_BIST_TOG BIT(2) BIT 68 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_SER_DIN_TOG BIT(1) BIT 69 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RG_HDMITX_SER_CLKDIG_INV BIT(0) BIT 108 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c #define RGS_HDMITX_PLUG_TST BIT(0) BIT 438 drivers/gpu/drm/meson/meson_dw_hdmi.c dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); BIT 470 drivers/gpu/drm/meson/meson_dw_hdmi.c BIT(17), 0); BIT 473 drivers/gpu/drm/meson/meson_dw_hdmi.c BIT(17), BIT(17)); BIT 924 drivers/gpu/drm/meson/meson_dw_hdmi.c encoder->possible_crtcs = BIT(0); BIT 941 drivers/gpu/drm/meson/meson_dw_hdmi.c writel_bits_relaxed(BIT(15), BIT(15), BIT 943 drivers/gpu/drm/meson/meson_dw_hdmi.c writel_bits_relaxed(BIT(15), BIT(15), BIT 97 drivers/gpu/drm/meson/meson_dw_hdmi.h #define HDMITX_TOP_INTR_CORE BIT(0) BIT 98 drivers/gpu/drm/meson/meson_dw_hdmi.h #define HDMITX_TOP_INTR_HPD_RISE BIT(1) BIT 99 drivers/gpu/drm/meson/meson_dw_hdmi.h #define HDMITX_TOP_INTR_HPD_FALL BIT(2) BIT 100 drivers/gpu/drm/meson/meson_dw_hdmi.h #define HDMITX_TOP_INTR_RXSENSE_RISE BIT(6) BIT 101 drivers/gpu/drm/meson/meson_dw_hdmi.h #define HDMITX_TOP_INTR_RXSENSE_FALL BIT(7) BIT 25 drivers/gpu/drm/meson/meson_overlay.c #define VD_URGENT_CHROMA BIT(28) BIT 26 drivers/gpu/drm/meson/meson_overlay.c #define VD_URGENT_LUMA BIT(27) BIT 28 drivers/gpu/drm/meson/meson_overlay.c #define VD_DEMUX_MODE_RGB BIT(16) BIT 30 drivers/gpu/drm/meson/meson_overlay.c #define VD_CHRO_RPT_LASTL_CTRL BIT(6) BIT 31 drivers/gpu/drm/meson/meson_overlay.c #define VD_LITTLE_ENDIAN BIT(4) BIT 32 drivers/gpu/drm/meson/meson_overlay.c #define VD_SEPARATE_EN BIT(1) BIT 33 drivers/gpu/drm/meson/meson_overlay.c #define VD_ENABLE BIT(0) BIT 53 drivers/gpu/drm/meson/meson_overlay.c #define VD_HORZ_FMT_EN BIT(20) BIT 54 drivers/gpu/drm/meson/meson_overlay.c #define VD_VERT_RPT_LINE0 BIT(16) BIT 57 drivers/gpu/drm/meson/meson_overlay.c #define VD_VERT_FMT_EN BIT(0) BIT 37 drivers/gpu/drm/meson/meson_plane.c #define SC_CTRL0_PATH_EN BIT(3) BIT 38 drivers/gpu/drm/meson/meson_plane.c #define SC_CTRL0_SEL_OSD1 BIT(2) BIT 46 drivers/gpu/drm/meson/meson_plane.c #define VSC_PROG_INTERLACE BIT(23) BIT 47 drivers/gpu/drm/meson/meson_plane.c #define VSC_VERTICAL_SCALER_EN BIT(24) BIT 57 drivers/gpu/drm/meson/meson_plane.c #define HSC_HORIZ_SCALER_EN BIT(22) BIT 141 drivers/gpu/drm/meson/meson_registers.h #define VIU_SW_RESET_OSD1 BIT(0) BIT 148 drivers/gpu/drm/meson/meson_registers.h #define VIU_OSD1_OSD_BLK_ENABLE BIT(0) BIT 153 drivers/gpu/drm/meson/meson_registers.h #define VIU_OSD1_OSD_ENABLE BIT(21) BIT 243 drivers/gpu/drm/meson/meson_registers.h #define VIU_OSD_DDR_PRIORITY_URGENT BIT(0) BIT 358 drivers/gpu/drm/meson/meson_registers.h #define VPP_SCALE_HORIZONTAL_COEF BIT(8) BIT 380 drivers/gpu/drm/meson/meson_registers.h #define VPP_SC_VD_EN_ENABLE BIT(15) BIT 381 drivers/gpu/drm/meson/meson_registers.h #define VPP_SC_TOP_EN_ENABLE BIT(16) BIT 382 drivers/gpu/drm/meson/meson_registers.h #define VPP_SC_HSC_EN_ENABLE BIT(17) BIT 383 drivers/gpu/drm/meson/meson_registers.h #define VPP_SC_VSC_EN_ENABLE BIT(18) BIT 401 drivers/gpu/drm/meson/meson_registers.h #define VPP_PREBLEND_ENABLE BIT(6) BIT 402 drivers/gpu/drm/meson/meson_registers.h #define VPP_POSTBLEND_ENABLE BIT(7) BIT 403 drivers/gpu/drm/meson/meson_registers.h #define VPP_OSD2_ALPHA_PREMULT BIT(8) BIT 404 drivers/gpu/drm/meson/meson_registers.h #define VPP_OSD1_ALPHA_PREMULT BIT(9) BIT 405 drivers/gpu/drm/meson/meson_registers.h #define VPP_VD1_POSTBLEND BIT(10) BIT 406 drivers/gpu/drm/meson/meson_registers.h #define VPP_VD2_POSTBLEND BIT(11) BIT 407 drivers/gpu/drm/meson/meson_registers.h #define VPP_OSD1_POSTBLEND BIT(12) BIT 408 drivers/gpu/drm/meson/meson_registers.h #define VPP_OSD2_POSTBLEND BIT(13) BIT 409 drivers/gpu/drm/meson/meson_registers.h #define VPP_VD1_PREBLEND BIT(14) BIT 410 drivers/gpu/drm/meson/meson_registers.h #define VPP_VD2_PREBLEND BIT(15) BIT 411 drivers/gpu/drm/meson/meson_registers.h #define VPP_OSD1_PREBLEND BIT(16) BIT 412 drivers/gpu/drm/meson/meson_registers.h #define VPP_OSD2_PREBLEND BIT(17) BIT 413 drivers/gpu/drm/meson/meson_registers.h #define VPP_COLOR_MNG_ENABLE BIT(28) BIT 432 drivers/gpu/drm/meson/meson_registers.h #define VPP_MINUS_BLACK_LVL_VADJ1_ENABLE BIT(1) BIT 738 drivers/gpu/drm/meson/meson_registers.h #define VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO BIT(0) BIT 739 drivers/gpu/drm/meson/meson_registers.h #define VENC_UPSAMPLE_CTRL_F1_EN BIT(5) BIT 740 drivers/gpu/drm/meson/meson_registers.h #define VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN BIT(6) BIT 765 drivers/gpu/drm/meson/meson_registers.h #define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1) BIT 776 drivers/gpu/drm/meson/meson_registers.h #define VENC_VDAC_SEL_ATV_DMD BIT(5) BIT 797 drivers/gpu/drm/meson/meson_registers.h #define VENC_VDAC_FIFO_EN_ENCI_ENABLE BIT(13) BIT 813 drivers/gpu/drm/meson/meson_registers.h #define ENCP_VIDEO_MODE_DE_V_HIGH BIT(14) BIT 893 drivers/gpu/drm/meson/meson_registers.h #define ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 BIT(2) BIT 967 drivers/gpu/drm/meson/meson_registers.h #define ENCI_MACV_MAX_AMP_ENABLE_CHANGE BIT(15) BIT 973 drivers/gpu/drm/meson/meson_registers.h #define ENCI_CFILT_CMPT_SEL_HIGH BIT(1) BIT 977 drivers/gpu/drm/meson/meson_registers.h #define ENCI_VIDEO_EN_ENABLE BIT(0) BIT 1007 drivers/gpu/drm/meson/meson_registers.h #define ENCI_VFIFO2VD_CTL_ENABLE BIT(0) BIT 1071 drivers/gpu/drm/meson/meson_registers.h #define VENC_VDAC_DAC0_FILT_CTRL0_EN BIT(0) BIT 1477 drivers/gpu/drm/meson/meson_registers.h #define VPU_HDMI_ENCI_DATA_TO_HDMI BIT(0) BIT 1478 drivers/gpu/drm/meson/meson_registers.h #define VPU_HDMI_ENCP_DATA_TO_HDMI BIT(1) BIT 1479 drivers/gpu/drm/meson/meson_registers.h #define VPU_HDMI_INV_HSYNC BIT(2) BIT 1480 drivers/gpu/drm/meson/meson_registers.h #define VPU_HDMI_INV_VSYNC BIT(3) BIT 1685 drivers/gpu/drm/meson/meson_registers.h #define VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 BIT(24) BIT 1686 drivers/gpu/drm/meson/meson_registers.h #define VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 BIT(25) BIT 1687 drivers/gpu/drm/meson/meson_registers.h #define VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 BIT(26) BIT 1723 drivers/gpu/drm/meson/meson_registers.h #define VD_BLEND_PREBLD_PREMULT_EN BIT(4) BIT 1728 drivers/gpu/drm/meson/meson_registers.h #define VD_BLEND_POSTBLD_PREMULT_EN BIT(16) BIT 1735 drivers/gpu/drm/meson/meson_registers.h #define OSD_BLEND_PATH_SEL_ENABLE BIT(20) BIT 51 drivers/gpu/drm/meson/meson_vclk.c #define VID_PLL_EN BIT(19) BIT 52 drivers/gpu/drm/meson/meson_vclk.c #define VID_PLL_BYPASS BIT(18) BIT 53 drivers/gpu/drm/meson/meson_vclk.c #define VID_PLL_PRESET BIT(15) BIT 56 drivers/gpu/drm/meson/meson_vclk.c #define VCLK2_DIV_EN BIT(16) BIT 57 drivers/gpu/drm/meson/meson_vclk.c #define VCLK2_DIV_RESET BIT(17) BIT 61 drivers/gpu/drm/meson/meson_vclk.c #define VCLK2_EN BIT(19) BIT 64 drivers/gpu/drm/meson/meson_vclk.c #define VCLK2_SOFT_RESET BIT(15) BIT 65 drivers/gpu/drm/meson/meson_vclk.c #define VCLK2_DIV1_EN BIT(0) BIT 68 drivers/gpu/drm/meson/meson_vclk.c #define VCLK_DIV_EN BIT(16) BIT 69 drivers/gpu/drm/meson/meson_vclk.c #define VCLK_DIV_RESET BIT(17) BIT 75 drivers/gpu/drm/meson/meson_vclk.c #define VCLK_EN BIT(19) BIT 78 drivers/gpu/drm/meson/meson_vclk.c #define VCLK_SOFT_RESET BIT(15) BIT 79 drivers/gpu/drm/meson/meson_vclk.c #define VCLK_DIV1_EN BIT(0) BIT 80 drivers/gpu/drm/meson/meson_vclk.c #define VCLK_DIV2_EN BIT(1) BIT 81 drivers/gpu/drm/meson/meson_vclk.c #define VCLK_DIV4_EN BIT(2) BIT 82 drivers/gpu/drm/meson/meson_vclk.c #define VCLK_DIV6_EN BIT(3) BIT 83 drivers/gpu/drm/meson/meson_vclk.c #define VCLK_DIV12_EN BIT(4) BIT 85 drivers/gpu/drm/meson/meson_vclk.c #define CTS_ENCI_EN BIT(0) BIT 86 drivers/gpu/drm/meson/meson_vclk.c #define CTS_ENCP_EN BIT(2) BIT 87 drivers/gpu/drm/meson/meson_vclk.c #define CTS_VDAC_EN BIT(4) BIT 88 drivers/gpu/drm/meson/meson_vclk.c #define HDMI_TX_PIXEL_EN BIT(5) BIT 94 drivers/gpu/drm/meson/meson_vclk.c #define CTS_HDMI_SYS_EN BIT(8) BIT 100 drivers/gpu/drm/meson/meson_vclk.c #define HHI_HDMI_PLL_CNTL_EN BIT(30) BIT 108 drivers/gpu/drm/meson/meson_vclk.c #define HDMI_PLL_RESET BIT(28) BIT 109 drivers/gpu/drm/meson/meson_vclk.c #define HDMI_PLL_RESET_G12A BIT(29) BIT 110 drivers/gpu/drm/meson/meson_vclk.c #define HDMI_PLL_LOCK BIT(31) BIT 1743 drivers/gpu/drm/meson/meson_venc.c return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29); BIT 1750 drivers/gpu/drm/meson/meson_venc.c regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); BIT 1755 drivers/gpu/drm/meson/meson_venc.c regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); BIT 288 drivers/gpu/drm/meson/meson_venc_cvbs.c encoder->possible_crtcs = BIT(0); BIT 102 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, BIT 152 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, BIT 154 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(1), 0, BIT 165 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0, BIT 167 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0, BIT 251 drivers/gpu/drm/meson/meson_viu.c writel_bits_relaxed(BIT(31), BIT(31), BIT 15 drivers/gpu/drm/meson/meson_viu.h #define OSD_ENDIANNESS_LE BIT(15) BIT 23 drivers/gpu/drm/meson/meson_viu.h #define OSD_OUTPUT_COLOR_RGB BIT(7) BIT 36 drivers/gpu/drm/meson/meson_viu.h #define OSD_INTERLACE_ENABLED BIT(1) BIT 37 drivers/gpu/drm/meson/meson_viu.h #define OSD_INTERLACE_ODD BIT(0) BIT 41 drivers/gpu/drm/meson/meson_viu.h #define OSD_ENABLE BIT(21) BIT 42 drivers/gpu/drm/meson/meson_viu.h #define OSD_BLK0_ENABLE BIT(0) BIT 47 drivers/gpu/drm/meson/meson_viu.h #define OSD_REPLACE_EN BIT(14) BIT 672 drivers/gpu/drm/msm/adreno/a5xx_gpu.c gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, BIT(23)); BIT 673 drivers/gpu/drm/msm/adreno/a5xx_gpu.c gpu_rmw(gpu, REG_A5XX_HLSQ_DBG_ECO_CNTL, BIT(18), 0); BIT 444 drivers/gpu/drm/msm/adreno/a6xx_gmu.c gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); BIT 461 drivers/gpu/drm/msm/adreno/adreno_gpu.c OUT_RING(ring, CACHE_FLUSH_TS | BIT(31)); BIT 14 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h #define DPU_ENCODER_FRAME_EVENT_DONE BIT(0) BIT 15 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h #define DPU_ENCODER_FRAME_EVENT_ERROR BIT(1) BIT 16 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h #define DPU_ENCODER_FRAME_EVENT_PANEL_DEAD BIT(2) BIT 17 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h #define DPU_ENCODER_FRAME_EVENT_IDLE BIT(3) BIT 15 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_SCALER_QSEED3) | BIT(DPU_SSPP_QOS) |\ BIT 16 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT 17 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) BIT 20 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT 21 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ BIT 22 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) BIT 25 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) BIT 28 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) BIT 30 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER) BIT 33 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) BIT 95 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .features = BIT(DPU_CTL_SPLIT_DISPLAY) BIT 100 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .features = BIT(DPU_CTL_SPLIT_DISPLAY) BIT 304 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .features = BIT(DPU_VBIF_QOS_REMAP), BIT 26 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c #define CTL_MIXER_BORDER_OUT BIT(24) BIT 27 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c #define CTL_FLUSH_MASK_CTL BIT(17) BIT 122 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(0); BIT 125 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(1); BIT 128 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(2); BIT 131 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(18); BIT 134 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(3); BIT 137 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(4); BIT 140 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(5); BIT 143 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(19); BIT 146 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(11); BIT 149 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(12); BIT 152 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(24); BIT 155 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(25); BIT 158 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(22); BIT 161 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(23); BIT 177 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(6); BIT 180 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(7); BIT 183 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(8); BIT 186 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(9); BIT 189 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(10); BIT 192 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c flushbits = BIT(20); BIT 208 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c *flushbits |= BIT(31); BIT 211 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c *flushbits |= BIT(30); BIT 214 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c *flushbits |= BIT(29); BIT 217 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c *flushbits |= BIT(28); BIT 434 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c intf_cfg |= BIT(19); BIT 440 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c intf_cfg &= ~BIT(17); BIT 444 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c intf_cfg |= BIT(17); BIT 32 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_WB_0_DONE BIT(0) BIT 33 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_WB_1_DONE BIT(1) BIT 34 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_WB_2_DONE BIT(4) BIT 39 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_WD_TIMER_0_DONE BIT(2) BIT 40 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_WD_TIMER_1_DONE BIT(3) BIT 41 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_WD_TIMER_2_DONE BIT(5) BIT 42 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_WD_TIMER_3_DONE BIT(6) BIT 43 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_WD_TIMER_4_DONE BIT(7) BIT 48 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_0_DONE BIT(8) BIT 49 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_1_DONE BIT(9) BIT 50 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_2_DONE BIT(10) BIT 51 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_3_DONE BIT(11) BIT 52 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_0_RD_PTR BIT(12) BIT 53 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_1_RD_PTR BIT(13) BIT 54 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_2_RD_PTR BIT(14) BIT 55 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_3_RD_PTR BIT(15) BIT 56 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_0_WR_PTR BIT(16) BIT 57 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_1_WR_PTR BIT(17) BIT 58 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_2_WR_PTR BIT(18) BIT 59 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_3_WR_PTR BIT(19) BIT 60 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20) BIT 61 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21) BIT 62 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22) BIT 63 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23) BIT 68 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_INTF_0_UNDERRUN BIT(24) BIT 69 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_INTF_1_UNDERRUN BIT(26) BIT 70 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_INTF_2_UNDERRUN BIT(28) BIT 71 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_INTF_3_UNDERRUN BIT(30) BIT 72 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_INTF_0_VSYNC BIT(25) BIT 73 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_INTF_1_VSYNC BIT(27) BIT 74 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_INTF_2_VSYNC BIT(29) BIT 75 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_INTF_3_VSYNC BIT(31) BIT 80 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0) BIT 81 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_S0_WR_PTR BIT(4) BIT 82 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_S0_RD_PTR BIT(8) BIT 83 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22) BIT 84 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_S0_TE_DETECTED BIT(28) BIT 89 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_0_TEAR_DETECTED BIT(16) BIT 90 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_1_TEAR_DETECTED BIT(17) BIT 91 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_2_TEAR_DETECTED BIT(18) BIT 92 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_3_TEAR_DETECTED BIT(19) BIT 97 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_0_TE_DETECTED BIT(24) BIT 98 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_1_TE_DETECTED BIT(25) BIT 99 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_2_TE_DETECTED BIT(26) BIT 100 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PING_PONG_3_TE_DETECTED BIT(27) BIT 105 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_CTL_0_START BIT(9) BIT 106 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_CTL_1_START BIT(10) BIT 107 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_CTL_2_START BIT(11) BIT 108 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_CTL_3_START BIT(12) BIT 109 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_CTL_4_START BIT(13) BIT 114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_CWB_2_OVERFLOW BIT(14) BIT 115 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_CWB_3_OVERFLOW BIT(15) BIT 120 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_VIG_0_DONE BIT(0) BIT 121 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_VIG_1_DONE BIT(4) BIT 122 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_VIG_2_DONE BIT(8) BIT 123 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_VIG_3_DONE BIT(10) BIT 128 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1) BIT 129 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5) BIT 130 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9) BIT 131 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11) BIT 136 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_DSPP_0_DONE BIT(12) BIT 137 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_DSPP_1_DONE BIT(16) BIT 138 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_DSPP_2_DONE BIT(20) BIT 139 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_DSPP_3_DONE BIT(22) BIT 144 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13) BIT 145 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17) BIT 146 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21) BIT 147 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23) BIT 152 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_VIDEO_INTO_STATIC BIT(0) BIT 153 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_VIDEO_OUTOF_STATIC BIT(1) BIT 154 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_DSICMD_0_INTO_STATIC BIT(2) BIT 155 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_DSICMD_0_OUTOF_STATIC BIT(3) BIT 156 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_DSICMD_1_INTO_STATIC BIT(4) BIT 157 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_DSICMD_1_OUTOF_STATIC BIT(5) BIT 158 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_DSICMD_2_INTO_STATIC BIT(6) BIT 159 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_DSICMD_2_OUTOF_STATIC BIT(7) BIT 160 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_PROG_LINE BIT(8) BIT 165 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c #define DPU_INTR_BACKLIGHT_UPDATED BIT(0) BIT 134 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */ BIT 140 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */ BIT 211 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c fetch_enable |= BIT(31); BIT 215 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c fetch_enable &= ~BIT(31); BIT 77 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c op_mode |= BIT(31); BIT 79 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c op_mode &= ~BIT(31); BIT 145 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode; BIT 45 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) BIT 46 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) BIT 47 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) BIT 62 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c cfg = BIT(19); /*VSYNC_COUNTER_EN */ BIT 64 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c cfg |= BIT(20); BIT 123 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c orig = (bool)(cfg & BIT(20)); BIT 125 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c cfg |= BIT(20); BIT 127 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c cfg &= ~BIT(20); BIT 41 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define MDSS_MDP_OP_DEINTERLACE BIT(22) BIT 42 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) BIT 43 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define MDSS_MDP_OP_IGC_ROM_1 BIT(18) BIT 44 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define MDSS_MDP_OP_IGC_ROM_0 BIT(17) BIT 45 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define MDSS_MDP_OP_IGC_EN BIT(16) BIT 46 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define MDSS_MDP_OP_FLIP_UD BIT(14) BIT 47 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define MDSS_MDP_OP_FLIP_LR BIT(13) BIT 48 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define MDSS_MDP_OP_BWC_EN BIT(0) BIT 49 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define MDSS_MDP_OP_PE_OVERRIDE BIT(31) BIT 88 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define SSPP_QOS_CTRL_VBLANK_EN BIT(16) BIT 89 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0) BIT 110 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_CSC_DST_DATAFMT BIT(19) BIT 111 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_CSC_SRC_DATAFMT BIT(18) BIT 112 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_CSC_EN BIT(17) BIT 113 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_MEM_PROT_CONT BIT(15) BIT 114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_MEM_PROT_VAL BIT(14) BIT 115 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_MEM_PROT_SAT BIT(13) BIT 116 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_MEM_PROT_HUE BIT(12) BIT 117 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_HIST BIT(8) BIT 118 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_SKY_COL BIT(7) BIT 119 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_FOIL BIT(6) BIT 120 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_SKIN_COL BIT(5) BIT 121 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_PA_EN BIT(4) BIT 122 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_PA_SAT_ZERO_EXP BIT(2) BIT 123 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_OP_MEM_PROT_BLEND BIT(1) BIT 128 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_CSC_10_SRC_DATAFMT BIT(1) BIT 129 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c #define VIG_CSC_10_EN BIT(0) BIT 186 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c mode_mask |= BIT(2); BIT 188 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c mode_mask &= ~BIT(2); BIT 283 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c src_format |= BIT(11); /* ROT90 */ BIT 286 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c src_format |= BIT(8); /* SRCC3_EN */ BIT 289 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c src_format |= BIT(22); BIT 306 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c fast_clear = fmt->alpha_enable ? BIT(31) : 0; BIT 317 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c src_format |= BIT(15); BIT 320 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c src_format |= BIT(14); BIT 336 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); BIT 623 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c cdp_cntl |= BIT(0); BIT 625 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c cdp_cntl |= BIT(1); BIT 627 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c cdp_cntl |= BIT(2); BIT 629 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c cdp_cntl |= BIT(3); BIT 19 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h #define DPU_SSPP_FLIP_LR BIT(0) BIT 20 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h #define DPU_SSPP_FLIP_UD BIT(1) BIT 21 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h #define DPU_SSPP_SOURCE_ROTATED_90 BIT(2) BIT 22 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h #define DPU_SSPP_ROT_90 BIT(3) BIT 23 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h #define DPU_SSPP_SOLID_FILL BIT(4) BIT 13 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c #define FLD_SPLIT_DISPLAY_CMD BIT(1) BIT 14 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c #define FLD_SMART_PANEL_FREE_RUN BIT(2) BIT 15 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c #define FLD_INTF_1_SW_TRG_MUX BIT(4) BIT 16 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c #define FLD_INTF_2_SW_TRG_MUX BIT(8) BIT 24 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c #define TRAFFIC_SHAPER_EN BIT(31) BIT 114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c new_val = reg_val | BIT(bit_off); BIT 116 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c new_val = reg_val & ~BIT(bit_off); BIT 120 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c clk_forced_on = !(reg_val & BIT(bit_off)); BIT 212 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */ BIT 214 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg |= BIT(8); /* enable heartbeat timer */ BIT 215 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg |= BIT(0); /* enable WD timer */ BIT 155 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0)); BIT 214 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c op_mode |= BIT(0); BIT 218 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c op_mode |= BIT(12); BIT 223 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0; BIT 242 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c op_mode |= BIT(8); BIT 289 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c op_mode |= BIT(14); BIT 292 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c op_mode |= BIT(10); BIT 12 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h #define REG_MASK(n) ((BIT(n)) - 1) BIT 137 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val |= BIT(xin_id); BIT 139 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val &= ~BIT(xin_id); BIT 152 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c return (reg_val & BIT(xin_id)) ? true : false; BIT 195 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val |= BIT(xin_id); BIT 527 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) BIT 537 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); BIT 46 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) BIT 70 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c DPU_PLANE_QOS_VBLANK_CTRL = BIT(0), BIT 71 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), BIT 72 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c DPU_PLANE_QOS_PANIC_CTRL = BIT(2), BIT 537 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features) BIT 885 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c !(pdpu->features & (BIT(DPU_SSPP_CSC) BIT 886 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | BIT(DPU_SSPP_CSC_10BIT))))) { BIT 1339 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || BIT 1340 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c cfg->features & BIT(DPU_SSPP_SCALER_QSEED2)) { BIT 1354 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c if (cfg->features & BIT(DPU_SSPP_CSC) || BIT 1355 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c cfg->features & BIT(DPU_SSPP_CSC_10BIT)) { BIT 455 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features; BIT 69 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c if (!vbif || !(vbif->cap->features & BIT(DPU_VBIF_QOS_OTLIM))) BIT 54 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h #define MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT BIT(0) BIT 93 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_CAP_SMP BIT(0) /* Shared Memory Pool */ BIT 94 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_CAP_DSC BIT(1) /* VESA Display Stream Compression */ BIT 95 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_CAP_CDM BIT(2) /* Chroma Down Module (HDMI 2.0 YUV) */ BIT 96 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_CAP_SRC_SPLIT BIT(3) /* Source Split of SSPPs */ BIT 99 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_PIPE_CAP_HFLIP BIT(0) BIT 100 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_PIPE_CAP_VFLIP BIT(1) BIT 101 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_PIPE_CAP_SCALE BIT(2) BIT 102 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_PIPE_CAP_CSC BIT(3) BIT 103 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_PIPE_CAP_DECIMATION BIT(4) BIT 104 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_PIPE_CAP_SW_PIX_EXT BIT(5) BIT 105 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_PIPE_CAP_CURSOR BIT(6) BIT 108 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_LM_CAP_DISPLAY BIT(0) BIT 109 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_LM_CAP_WB BIT(1) BIT 110 drivers/gpu/drm/msm/disp/mdp_kms.h #define MDP_LM_CAP_PAIR BIT(2) BIT 1177 drivers/gpu/drm/msm/dsi/dsi_host.c data[3] = BIT(7); /* Last packet */ BIT 1179 drivers/gpu/drm/msm/dsi/dsi_host.c data[3] |= BIT(6); BIT 1181 drivers/gpu/drm/msm/dsi/dsi_host.c data[3] |= BIT(5); BIT 17 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h #define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0) BIT 19 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c return (data & BIT(0)); BIT 111 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c status, (status & BIT(0)), BIT 119 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c data = BIT(6) | BIT(5); BIT 20 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c if (timing->clk_zero & BIT(8)) BIT 20 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c if (timing->clk_zero & BIT(8)) BIT 197 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c #define SSC_CENTER BIT(0) BIT 198 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c #define SSC_EN BIT(1) BIT 356 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ((status & BIT(0)) > 0), BIT 372 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c data & ~BIT(5)); BIT 381 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c data | BIT(5)); BIT 392 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c data & ~BIT(5)); BIT 401 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c data | BIT(5)); BIT 187 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_locked = !!(val & BIT(5)); BIT 200 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_locked = !!(val & BIT(0)); BIT 303 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u64 multiplier = BIT(20); BIT 630 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u64 vco_rate, multiplier = BIT(20); BIT 292 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c mult_frac(ref_clk, sdm_freq_seed, BIT(16)); BIT 56 drivers/gpu/drm/msm/edp/edp_aux.c data[0] |= BIT(4); /* R/W */ BIT 29 drivers/gpu/drm/msm/edp/edp_ctrl.c #define EDP_CLK_MASK_AHB BIT(0) BIT 30 drivers/gpu/drm/msm/edp/edp_ctrl.c #define EDP_CLK_MASK_AUX BIT(1) BIT 31 drivers/gpu/drm/msm/edp/edp_ctrl.c #define EDP_CLK_MASK_LINK BIT(2) BIT 32 drivers/gpu/drm/msm/edp/edp_ctrl.c #define EDP_CLK_MASK_PIXEL BIT(3) BIT 33 drivers/gpu/drm/msm/edp/edp_ctrl.c #define EDP_CLK_MASK_MDP_CORE BIT(4) BIT 742 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdcp_ctrl->ds_type = (bcaps & BIT(6)) ? DS_REPEATER : DS_RECEIVER; BIT 884 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c max_devs_exceeded = (bstatus & BIT(7)) ? true : false; BIT 885 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c max_cascade_exceeded = (bstatus & BIT(11)) ? true : false; BIT 953 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c if (bcaps & BIT(5)) BIT 554 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c phy_ready = status & BIT(0); BIT 579 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c pll_locked = status & BIT(0); BIT 680 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c pll_locked = status & BIT(0); BIT 32 drivers/gpu/drm/msm/msm_atomic.c unsigned crtc_mask = BIT(crtc_idx); BIT 80 drivers/gpu/drm/msm/msm_drv.h MSM_DISPLAY_CAP_VID_MODE = BIT(0), BIT 81 drivers/gpu/drm/msm/msm_drv.h MSM_DISPLAY_CAP_CMD_MODE = BIT(1), BIT 82 drivers/gpu/drm/msm/msm_drv.h MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), BIT 83 drivers/gpu/drm/msm/msm_drv.h MSM_DISPLAY_CAP_EDID = BIT(3), BIT 34 drivers/gpu/drm/mxsfb/mxsfb_crtc.c #define MODULE_CLKGATE BIT(30) BIT 35 drivers/gpu/drm/mxsfb/mxsfb_crtc.c #define MODULE_SFTRST BIT(31) BIT 343 drivers/gpu/drm/nouveau/dispnv04/overlay.c BIT(DRM_COLOR_YCBCR_BT601) | BIT 344 drivers/gpu/drm/nouveau/dispnv04/overlay.c BIT(DRM_COLOR_YCBCR_BT709), BIT 345 drivers/gpu/drm/nouveau/dispnv04/overlay.c BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), BIT 270 drivers/gpu/drm/nouveau/dispnv50/base507c.c "base", head, format, BIT(head), BIT 121 drivers/gpu/drm/nouveau/dispnv50/curs507a.c "curs", head, curs507a_format, BIT(head), BIT 1414 drivers/gpu/drm/nouveau/dispnv50/disp.c nv_encoder->ctrl &= ~BIT(head); BIT 1419 drivers/gpu/drm/nouveau/dispnv50/disp.c nv_encoder->ctrl |= BIT(head); BIT 181 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c "ovly", head, format, BIT(head), BIT 347 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh->wndw.olut |= BIT(wndw->id); BIT 349 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh->wndw.olut &= ~BIT(wndw->id); BIT 437 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh->wndw.mask |= BIT(wndw->id); BIT 441 drivers/gpu/drm/nouveau/dispnv50/wndw.c harm->wndw.mask &= ~BIT(wndw->id); BIT 683 drivers/gpu/drm/nouveau/dispnv50/wndw.c BIT(DRM_MODE_BLEND_PIXEL_NONE) | BIT 684 drivers/gpu/drm/nouveau/dispnv50/wndw.c BIT(DRM_MODE_BLEND_PREMULTI) | BIT 685 drivers/gpu/drm/nouveau/dispnv50/wndw.c BIT(DRM_MODE_BLEND_COVERAGE)); BIT 290 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c BIT(index), &wndw); BIT 313 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c BIT(index >> 1), pwndw); BIT 202 drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c BIT(index >> 1), pwndw); BIT 98 drivers/gpu/drm/nouveau/include/nvkm/core/memory.h for (; _c; _c--, _a += BIT(s)) \ BIT 207 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_wr32(device, 0x611850, BIT(wndw)); BIT 209 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c stat &= ~BIT(wndw); BIT 227 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_wr32(device, 0x61184c, BIT(wndw)); BIT 229 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c stat &= ~BIT(wndw); BIT 275 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c stat &= ~BIT(head); BIT 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c if (sublinks & BIT(s)) { BIT 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c if (!(disp->wndw.mask & BIT(args->v0.index))) BIT 167 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c if (!(disp->wndw.mask & BIT(args->v0.index))) BIT 293 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT(engn)) { BIT 300 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c for (todo = runm; runl = __ffs(todo), todo; todo &= ~BIT(runl)) BIT 314 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const u32 runm = BIT(runl); BIT 402 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const u32 engm = BIT(engn); BIT 455 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_wr32(device, 0x00259c, BIT(mmui)); BIT 599 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c engm |= BIT(engn); BIT 48 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_mask(device, 0x002630, BIT(chan->runl), BIT(chan->runl)); BIT 60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_mask(device, 0x002630, BIT(chan->runl), 0); BIT 1702 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c secboot_mask |= BIT(NVKM_SECBOOT_FALCON_FECS); BIT 1707 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c secboot_mask |= BIT(NVKM_SECBOOT_FALCON_GPCCS); BIT 315 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c #define CMD_FLAGS_STATUS BIT(0) BIT 317 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c #define CMD_FLAGS_INTR BIT(1) BIT 315 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c falcon_treated |= BIT(falcon_id); BIT 38 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c reg = start | BIT(24) | (secure ? BIT(28) : 0); BIT 58 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c extra & (BIT(rem * 8) - 1)); BIT 88 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c extra & (BIT(rem * 8) - 1)); BIT 120 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c extra & (BIT(rem * 8) - 1)); BIT 285 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c if (reg & BIT(6)) BIT 226 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), BIT 227 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); BIT 237 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), BIT 238 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT)); BIT 248 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | BIT 249 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); BIT 277 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), BIT 278 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); BIT 289 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); BIT 36 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPCPLL_CFG_ENABLE BIT(0) BIT 37 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPCPLL_CFG_IDDQ BIT(1) BIT 38 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPCPLL_CFG_LOCK_DET_OFF BIT(4) BIT 39 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPCPLL_CFG_LOCK BIT(17) BIT 32 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define GPCPLL_CFG_SYNC_MODE BIT(2) BIT 72 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define GPCPLL_DVFS1_EN_SDM_BIT BIT(28) BIT 75 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define GPCPLL_DVFS1_EN_DFS_BIT BIT(29) BIT 78 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define GPCPLL_DVFS1_EN_DFS_CAL_BIT BIT(30) BIT 81 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define GPCPLL_DVFS1_DFS_CAL_DONE_BIT BIT(31) BIT 84 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define GPC_BCAST_GPCPLL_DVFS2_DFS_EXT_STROBE_BIT BIT(16) BIT 206 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (abs(dvfs->dfs_ext_cal) >= BIT(DFS_DET_RANGE)) BIT 257 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c rem = (rem << rem_range) - BIT(SDM_DIN_RANGE); BIT 285 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), BIT 286 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); BIT 299 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), BIT 300 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT)); BIT 314 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | BIT 315 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); BIT 338 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), BIT 339 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); BIT 350 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); BIT 399 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll.base.pl = min(old | BIT(ffs(new) - 1), BIT 400 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c new | BIT(ffs(old) - 1)); BIT 541 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (!(val & BIT(25))) { BIT 543 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c val |= BIT(25) | BIT(16); BIT 104 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c base->post = ((nvkm_rd32(device, 0x2240c) & BIT(1)) == 0); BIT 475 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c if (!(fbpao & BIT(fbp))) { BIT 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.c if (!(fbpao & BIT(fbpa))) BIT 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.c if (!(nvkm_rd32(device, 0x021d38) & BIT(fbp))) { BIT 332 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c r->offset &= ~BIT(imem->iommu_bit - imem->iommu_pgshift); BIT 491 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c r->offset |= BIT(imem->iommu_bit - imem->iommu_pgshift); BIT 52 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c ptp->free |= BIT(slot); BIT 102 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c ptp->free &= ~BIT(slot); BIT 313 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c map->type |= BIT(0); BIT 381 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c map->type |= BIT(0); BIT 316 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c map->type |= BIT(0); /* Valid. */ BIT 317 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->lazy_bootstrap & BIT(_img->falcon_id)) BIT 502 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->base.optional_falcons & BIT(falcon_id)) { BIT 503 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c managed_falcons &= ~BIT(falcon_id); BIT 524 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c (managed_falcons & BIT(acr->base.boot_falcon))) { BIT 530 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->lazy_bootstrap |= BIT(falcon_id); BIT 969 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (!(falcon_mask & BIT(NVKM_SECBOOT_FALCON_FECS))) BIT 176 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c if (acr->lazy_bootstrap & BIT(_img->falcon_id)) BIT 125 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c return sb->acr->managed_falcons & BIT(fid); BIT 180 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c acr = acr_r361_new(BIT(NVKM_SECBOOT_FALCON_FECS) | BIT 181 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c BIT(NVKM_SECBOOT_FALCON_GPCCS)); BIT 112 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | BIT 113 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c BIT(NVKM_SECBOOT_FALCON_PMU)); BIT 117 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c acr->optional_falcons = BIT(NVKM_SECBOOT_FALCON_PMU); BIT 43 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c return (reg & BIT(4)); BIT 153 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c BIT(NVKM_SECBOOT_FALCON_FECS) | BIT 154 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c BIT(NVKM_SECBOOT_FALCON_GPCCS) | BIT 155 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c BIT(NVKM_SECBOOT_FALCON_SEC2)); BIT 33 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c BIT(NVKM_SECBOOT_FALCON_FECS) | BIT 34 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c BIT(NVKM_SECBOOT_FALCON_GPCCS) | BIT 35 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c BIT(NVKM_SECBOOT_FALCON_SEC2)); BIT 57 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | BIT 58 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c BIT(NVKM_SECBOOT_FALCON_GPCCS) | BIT 59 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c BIT(NVKM_SECBOOT_FALCON_PMU)); BIT 68 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c return BIT(info->reset); BIT 84 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c return BIT(info->intr); BIT 102 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c if (intr & BIT(info->intr)) { BIT 104 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c handled |= BIT(info->intr); BIT 58 drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c dssdev->of_ports = BIT(0); BIT 142 drivers/gpu/drm/omapdrm/displays/connector-hdmi.c dssdev->of_ports = BIT(0); BIT 89 drivers/gpu/drm/omapdrm/displays/encoder-opa362.c dssdev->of_ports = BIT(1) | BIT(0); BIT 168 drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c dssdev->of_ports = BIT(1) | BIT(0); BIT 1268 drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c dssdev->of_ports = BIT(0); BIT 628 drivers/gpu/drm/omapdrm/dss/dpi.c out->of_ports = BIT(port_num); BIT 5120 drivers/gpu/drm/omapdrm/dss/dsi.c out->of_ports = BIT(0); BIT 676 drivers/gpu/drm/omapdrm/dss/hdmi4.c out->of_ports = BIT(0); BIT 660 drivers/gpu/drm/omapdrm/dss/hdmi5.c out->of_ports = BIT(0); BIT 389 drivers/gpu/drm/omapdrm/dss/omapdss.h OMAP_DSS_DEVICE_OP_DETECT = BIT(0), BIT 390 drivers/gpu/drm/omapdrm/dss/omapdss.h OMAP_DSS_DEVICE_OP_HPD = BIT(1), BIT 391 drivers/gpu/drm/omapdrm/dss/omapdss.h OMAP_DSS_DEVICE_OP_EDID = BIT(2), BIT 392 drivers/gpu/drm/omapdrm/dss/omapdss.h OMAP_DSS_DEVICE_OP_MODES = BIT(3), BIT 505 drivers/gpu/drm/omapdrm/dss/pll.c (cinfo->mX[0] ? BIT(7) : 0) | BIT 506 drivers/gpu/drm/omapdrm/dss/pll.c (cinfo->mX[1] ? BIT(8) : 0) | BIT 507 drivers/gpu/drm/omapdrm/dss/pll.c (cinfo->mX[2] ? BIT(10) : 0) | BIT 508 drivers/gpu/drm/omapdrm/dss/pll.c (cinfo->mX[3] ? BIT(11) : 0)); BIT 268 drivers/gpu/drm/omapdrm/dss/sdi.c out->of_ports = BIT(1); BIT 757 drivers/gpu/drm/omapdrm/dss/venc.c out->of_ports = BIT(0); BIT 293 drivers/gpu/drm/omapdrm/omap_plane.c drm_plane_create_blend_mode_property(plane, BIT(DRM_MODE_BLEND_PREMULTI) | BIT 294 drivers/gpu/drm/omapdrm/omap_plane.c BIT(DRM_MODE_BLEND_COVERAGE)); BIT 52 drivers/gpu/drm/panel/panel-arm-versatile.c #define SYS_CLCD_CLCDID_MASK (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) BIT 61 drivers/gpu/drm/panel/panel-arm-versatile.c #define IB2_CTRL_LCD_SD BIT(1) /* 1 = shut down LCD */ BIT 62 drivers/gpu/drm/panel/panel-arm-versatile.c #define IB2_CTRL_LCD_BL_ON BIT(0) BIT 63 drivers/gpu/drm/panel/panel-arm-versatile.c #define IB2_CTRL_LCD_MASK (BIT(0)|BIT(1)) BIT 65 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_ENTRY_HDIR BIT(0) BIT 67 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_ENTRY_VDIR BIT(1) BIT 88 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POW_CTRL_STB BIT(0) /* 0 = standby, 1 = normal */ BIT 89 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POW_CTRL_VGL BIT(1) /* 0 = off, 1 = on */ BIT 90 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POW_CTRL_VGH BIT(2) /* 0 = off, 1 = on */ BIT 91 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POW_CTRL_DDVDH BIT(3) /* 0 = off, 1 = on */ BIT 92 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POW_CTRL_VCOM BIT(4) /* 0 = off, 1 = on */ BIT 93 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POW_CTRL_VCL BIT(5) /* 0 = off, 1 = on */ BIT 94 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POW_CTRL_AUTO BIT(6) /* 0 = interactive, 1 = auto */ BIT 100 drivers/gpu/drm/panel/panel-ilitek-ili9322.c BIT(7)) BIT 116 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POL_DCLK BIT(0) /* 1 default */ BIT 117 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POL_HSYNC BIT(1) /* 0 default */ BIT 118 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POL_VSYNC BIT(2) /* 0 default */ BIT 119 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POL_DE BIT(3) /* 1 default */ BIT 126 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POL_YCBCR_MODE BIT(4) BIT 128 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POL_FORMULA BIT(5) BIT 130 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_POL_REV BIT(6) BIT 134 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_IF_CTRL_HSYNC_VSYNC_DE BIT(2) BIT 135 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_IF_CTRL_DE_ONLY BIT(3) BIT 136 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_IF_CTRL_SYNC_DISABLED (BIT(2) | BIT(3)) BIT 137 drivers/gpu/drm/panel/panel-ilitek-ili9322.c #define ILI9322_IF_CTRL_LINE_INVERSION BIT(0) /* Not set means frame inv */ BIT 48 drivers/gpu/drm/panel/panel-novatek-nt39016.c #define NT39016_SYSTEM_RESET_N BIT(0) BIT 49 drivers/gpu/drm/panel/panel-novatek-nt39016.c #define NT39016_SYSTEM_STANDBY BIT(1) BIT 125 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c # define DSI_LANEENABLE_CLOCK BIT(0) BIT 126 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c # define DSI_LANEENABLE_D0 BIT(1) BIT 127 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c # define DSI_LANEENABLE_D1 BIT(2) BIT 309 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c rpi_touchscreen_i2c_write(ts, REG_PORTA, BIT(2)); BIT 57 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_LINESET_LDE_EN BIT(7) BIT 73 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_CMD2_BK1_TESTCMD_VAL BIT(7) BIT 74 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_VGLS_DEFAULT BIT(6) BIT 77 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_PWCTLR1_AP BIT(7) /* Gamma OP bias, max */ BIT 78 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_PWCTLR1_APIS BIT(2) /* Source OP input bias, min */ BIT 79 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_PWCTLR1_APOS BIT(0) /* Source OP output bias, min */ BIT 82 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_PWCTLR2_AVDD BIT(5) /* AVDD 6.6v */ BIT 85 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_SPD1_T2D BIT(3) BIT 88 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_MIPISET1_EOT_EN BIT(3) BIT 89 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_CMD2_BK1_MIPISET1_SET (BIT(7) | DSI_MIPISET1_EOT_EN) BIT 23 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_RAMCTRL_RM_RGB BIT(4) BIT 24 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_RAMCTRL_DM_RGB BIT(0) BIT 29 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_RGBCTRL_WO BIT(7) BIT 31 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_RGBCTRL_VSYNC_HIGH BIT(3) BIT 32 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_RGBCTRL_HSYNC_HIGH BIT(2) BIT 33 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_RGBCTRL_PCLK_HIGH BIT(1) BIT 50 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_LCMCTRL_XBGR BIT(5) BIT 51 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_LCMCTRL_XMX BIT(3) BIT 52 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_LCMCTRL_XMH BIT(2) BIT 55 drivers/gpu/drm/panel/panel-sitronix-st7789v.c #define ST7789V_VDVVRHEN_CMDEN BIT(0) BIT 34 drivers/gpu/drm/panel/panel-sony-acx565akm.c #define CTRL_DISP_BRIGHTNESS_CTRL_ON BIT(5) BIT 35 drivers/gpu/drm/panel/panel-sony-acx565akm.c #define CTRL_DISP_AMBIENT_LIGHT_CTRL_ON BIT(4) BIT 36 drivers/gpu/drm/panel/panel-sony-acx565akm.c #define CTRL_DISP_BACKLIGHT_ON BIT(2) BIT 37 drivers/gpu/drm/panel/panel-sony-acx565akm.c #define CTRL_DISP_AUTO_BRIGHTNESS_ON BIT(1) BIT 23 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R02_NCLK_RISING BIT(3) BIT 24 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R02_HSYNC_HIGH BIT(4) BIT 25 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R02_VSYNC_HIGH BIT(5) BIT 27 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R03_NSTANDBY BIT(0) BIT 28 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R03_EN_CP_CLK BIT(1) BIT 29 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R03_EN_VGL_PUMP BIT(2) BIT 30 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R03_EN_PWM BIT(3) BIT 31 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R03_DRIVING_CAP_100 BIT(4) BIT 32 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R03_EN_PRE_CHARGE BIT(6) BIT 33 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R03_SOFTWARE_CTL BIT(7) BIT 35 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R04_NFLIP_H BIT(0) BIT 36 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R04_NFLIP_V BIT(1) BIT 37 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R04_CP_CLK_FREQ_1H BIT(2) BIT 38 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c #define TPO_R04_VGL_FREQ_1H BIT(4) BIT 38 drivers/gpu/drm/panel/panel-tpo-tpg110.c #define TPG110_CTRL2_PM BIT(0) BIT 39 drivers/gpu/drm/panel/panel-tpo-tpg110.c #define TPG110_CTRL2_RES_PM_CTRL BIT(7) BIT 167 drivers/gpu/drm/panfrost/panfrost_mmu.c if (!(BIT(as) & pfdev->features.as_present)) { BIT 584 drivers/gpu/drm/panfrost/panfrost_mmu.c u32 mask = BIT(i) | BIT(i + 16); BIT 605 drivers/gpu/drm/panfrost/panfrost_mmu.c if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0) BIT 16 drivers/gpu/drm/panfrost/panfrost_regs.h #define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */ BIT 26 drivers/gpu/drm/panfrost/panfrost_regs.h #define GPU_IRQ_FAULT BIT(0) BIT 27 drivers/gpu/drm/panfrost/panfrost_regs.h #define GPU_IRQ_MULTIPLE_FAULT BIT(7) BIT 28 drivers/gpu/drm/panfrost/panfrost_regs.h #define GPU_IRQ_RESET_COMPLETED BIT(8) BIT 29 drivers/gpu/drm/panfrost/panfrost_regs.h #define GPU_IRQ_POWER_CHANGED BIT(9) BIT 30 drivers/gpu/drm/panfrost/panfrost_regs.h #define GPU_IRQ_POWER_CHANGED_ALL BIT(10) BIT 31 drivers/gpu/drm/panfrost/panfrost_regs.h #define GPU_IRQ_PERFCNT_SAMPLE_COMPLETED BIT(16) BIT 32 drivers/gpu/drm/panfrost/panfrost_regs.h #define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17) BIT 52 drivers/gpu/drm/panfrost/panfrost_regs.h #define GPU_STATUS_PRFCNT_ACTIVE BIT(2) BIT 91 drivers/gpu/drm/panfrost/panfrost_regs.h #define COHERENCY_ACE_LITE BIT(0) BIT 92 drivers/gpu/drm/panfrost/panfrost_regs.h #define COHERENCY_ACE BIT(1) BIT 185 drivers/gpu/drm/panfrost/panfrost_regs.h #define SC_ALT_COUNTERS BIT(3) BIT 186 drivers/gpu/drm/panfrost/panfrost_regs.h #define SC_OVERRIDE_FWD_PIXEL_KILL BIT(4) BIT 187 drivers/gpu/drm/panfrost/panfrost_regs.h #define SC_SDC_DISABLE_OQ_DISCARD BIT(6) BIT 188 drivers/gpu/drm/panfrost/panfrost_regs.h #define SC_LS_ALLOW_ATTR_TYPES BIT(16) BIT 189 drivers/gpu/drm/panfrost/panfrost_regs.h #define SC_LS_PAUSEBUFFER_DISABLE BIT(16) BIT 190 drivers/gpu/drm/panfrost/panfrost_regs.h #define SC_TLS_HASH_ENABLE BIT(17) BIT 191 drivers/gpu/drm/panfrost/panfrost_regs.h #define SC_LS_ATTR_CHECK_DISABLE BIT(18) BIT 192 drivers/gpu/drm/panfrost/panfrost_regs.h #define SC_ENABLE_TEXGRD_FLAGS BIT(25) BIT 196 drivers/gpu/drm/panfrost/panfrost_regs.h #define TC_CLOCK_GATE_OVERRIDE BIT(0) BIT 199 drivers/gpu/drm/panfrost/panfrost_regs.h #define JM_TIMESTAMP_OVERRIDE BIT(0) BIT 200 drivers/gpu/drm/panfrost/panfrost_regs.h #define JM_CLOCK_GATE_OVERRIDE BIT(1) BIT 201 drivers/gpu/drm/panfrost/panfrost_regs.h #define JM_JOB_THROTTLE_ENABLE BIT(2) BIT 218 drivers/gpu/drm/panfrost/panfrost_regs.h #define JOB_INT_MASK_ERR(j) BIT((j) + 16) BIT 219 drivers/gpu/drm/panfrost/panfrost_regs.h #define JOB_INT_MASK_DONE(j) BIT(j) BIT 241 drivers/gpu/drm/panfrost/panfrost_regs.h #define JS_CONFIG_START_FLUSH_CLEAN BIT(8) BIT 243 drivers/gpu/drm/panfrost/panfrost_regs.h #define JS_CONFIG_START_MMU BIT(10) BIT 244 drivers/gpu/drm/panfrost/panfrost_regs.h #define JS_CONFIG_JOB_CHAIN_FLAG BIT(11) BIT 245 drivers/gpu/drm/panfrost/panfrost_regs.h #define JS_CONFIG_END_FLUSH_CLEAN BIT(12) BIT 247 drivers/gpu/drm/panfrost/panfrost_regs.h #define JS_CONFIG_ENABLE_FLUSH_REDUCTION BIT(14) BIT 248 drivers/gpu/drm/panfrost/panfrost_regs.h #define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK BIT(15) BIT 306 drivers/gpu/drm/panfrost/panfrost_regs.h #define AS_TRANSTAB_LPAE_READ_INNER BIT(2) BIT 307 drivers/gpu/drm/panfrost/panfrost_regs.h #define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4) BIT 26 drivers/gpu/drm/pl111/pl111_drm.h #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2) BIT 10 drivers/gpu/drm/pl111/pl111_nomadik.c #define PMU_CTRL_LCDNDIF BIT(26) BIT 74 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCDBIASEN BIT(8) BIT 75 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCDBIASUP BIT(9) BIT 76 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCDBIASDN BIT(10) BIT 78 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCDMUX_LCD24 BIT(11) BIT 79 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCDMUX_SHARP (BIT(11)|BIT(12)) BIT 80 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCDMUX_VGA555 BIT(13) BIT 81 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCDMUX_VGA24 (BIT(11)|BIT(12)|BIT(13)) BIT 82 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCD0_EN BIT(14) BIT 83 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCD1_EN BIT(15) BIT 85 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCD_STATIC1 BIT(16) BIT 87 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCD_STATIC2 BIT(17) BIT 89 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCD_STATIC BIT(18) BIT 91 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_LCD_N24BITEN BIT(19) BIT 134 drivers/gpu/drm/pl111/pl111_versatile.c #define SYS_CLCD_MODE_MASK (BIT(0)|BIT(1)) BIT 136 drivers/gpu/drm/pl111/pl111_versatile.c #define SYS_CLCD_MODE_5551 BIT(0) BIT 137 drivers/gpu/drm/pl111/pl111_versatile.c #define SYS_CLCD_MODE_565_R_LSB BIT(1) BIT 138 drivers/gpu/drm/pl111/pl111_versatile.c #define SYS_CLCD_MODE_565_B_LSB (BIT(0)|BIT(1)) BIT 139 drivers/gpu/drm/pl111/pl111_versatile.c #define SYS_CLCD_CONNECTOR_MASK (BIT(2)|BIT(3)|BIT(4)|BIT(5)) BIT 140 drivers/gpu/drm/pl111/pl111_versatile.c #define SYS_CLCD_NLCDIOON BIT(2) BIT 141 drivers/gpu/drm/pl111/pl111_versatile.c #define SYS_CLCD_VDDPOSSWITCH BIT(3) BIT 142 drivers/gpu/drm/pl111/pl111_versatile.c #define SYS_CLCD_PWR3V5SWITCH BIT(4) BIT 143 drivers/gpu/drm/pl111/pl111_versatile.c #define SYS_CLCD_VDDNEGSWITCH BIT(5) BIT 262 drivers/gpu/drm/rcar-du/rcar_du_crtc.c } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) { BIT 657 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rstate->outputs |= BIT(renc->output); BIT 677 drivers/gpu/drm/rcar-du/rcar_du_crtc.c if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) && BIT 678 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) { BIT 701 drivers/gpu/drm/rcar-du/rcar_du_crtc.c if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) && BIT 702 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) { BIT 1165 drivers/gpu/drm/rcar-du/rcar_du_crtc.c } else if (rcdu->info->dpll_mask & BIT(hwindex)) { BIT 41 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(1) | BIT(0), BIT 47 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1) | BIT(0), BIT 51 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 63 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(1) | BIT(0), BIT 69 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 73 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1), BIT 84 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(1) | BIT(0), BIT 91 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 95 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1), BIT 99 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0) | BIT(1), BIT 111 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(2) | BIT(1) | BIT(0), BIT 118 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(2), BIT 122 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1), BIT 126 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 131 drivers/gpu/drm/rcar-du/rcar_du_drv.c .dpll_mask = BIT(1), BIT 138 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(1) | BIT(0), BIT 144 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0) | BIT(1), BIT 148 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 152 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1), BIT 157 drivers/gpu/drm/rcar-du/rcar_du_drv.c .lvds_clk_mask = BIT(1) | BIT(0), BIT 164 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(1) | BIT(0), BIT 171 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 175 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1) | BIT(0), BIT 187 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(2) | BIT(1) | BIT(0), BIT 194 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(2) | BIT(1) | BIT(0), BIT 198 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 202 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(2) | BIT(1), BIT 215 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(1) | BIT(0), BIT 222 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1) | BIT(0), BIT 226 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 238 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(1) | BIT(0), BIT 242 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 246 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1), BIT 257 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(1) | BIT(0), BIT 264 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 268 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1), BIT 280 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), BIT 287 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(3), BIT 291 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1), BIT 295 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(2), BIT 299 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 304 drivers/gpu/drm/rcar-du/rcar_du_drv.c .dpll_mask = BIT(2) | BIT(1), BIT 313 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(2) | BIT(1) | BIT(0), BIT 320 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(2), BIT 324 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1), BIT 328 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 333 drivers/gpu/drm/rcar-du/rcar_du_drv.c .dpll_mask = BIT(1), BIT 342 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(3) | BIT(1) | BIT(0), BIT 349 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(2), BIT 353 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1), BIT 357 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 362 drivers/gpu/drm/rcar-du/rcar_du_drv.c .dpll_mask = BIT(1), BIT 371 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(0), BIT 375 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 379 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 390 drivers/gpu/drm/rcar-du/rcar_du_drv.c .channels_mask = BIT(1) | BIT(0), BIT 397 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0) | BIT(1), BIT 401 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(0), BIT 405 drivers/gpu/drm/rcar-du/rcar_du_drv.c .possible_crtcs = BIT(1), BIT 410 drivers/gpu/drm/rcar-du/rcar_du_drv.c .lvds_clk_mask = BIT(1) | BIT(0), BIT 27 drivers/gpu/drm/rcar-du/rcar_du_drv.h #define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK BIT(0) /* Per-CRTC IRQ and clock */ BIT 28 drivers/gpu/drm/rcar-du/rcar_du_drv.h #define RCAR_DU_FEATURE_VSP1_SOURCE BIT(1) /* Has inputs from VSP1 */ BIT 29 drivers/gpu/drm/rcar-du/rcar_du_drv.h #define RCAR_DU_FEATURE_INTERLACED BIT(2) /* HW supports interlaced */ BIT 30 drivers/gpu/drm/rcar-du/rcar_du_drv.h #define RCAR_DU_FEATURE_TVM_SYNC BIT(3) /* Has TV switch/sync modes */ BIT 32 drivers/gpu/drm/rcar-du/rcar_du_drv.h #define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */ BIT 47 drivers/gpu/drm/rcar-du/rcar_du_group.c if (rgrp->channels_mask & BIT(0)) BIT 50 drivers/gpu/drm/rcar-du/rcar_du_group.c if (rgrp->channels_mask & BIT(1)) BIT 124 drivers/gpu/drm/rcar-du/rcar_du_group.c if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) BIT 215 drivers/gpu/drm/rcar-du/rcar_du_group.c if (rcdu->info->channels_mask & BIT(rgrp->index * 2)) { BIT 298 drivers/gpu/drm/rcar-du/rcar_du_group.c static const u32 dpad_mask = BIT(RCAR_DU_OUTPUT_DPAD1) BIT 299 drivers/gpu/drm/rcar-du/rcar_du_group.c | BIT(RCAR_DU_OUTPUT_DPAD0); BIT 404 drivers/gpu/drm/rcar-du/rcar_du_kms.c if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0)) BIT 407 drivers/gpu/drm/rcar-du/rcar_du_kms.c if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1)) BIT 586 drivers/gpu/drm/rcar-du/rcar_du_kms.c vsps[j].crtcs_mask |= BIT(i); BIT 712 drivers/gpu/drm/rcar-du/rcar_du_kms.c if (!(rcdu->info->channels_mask & BIT(hwindex))) BIT 39 drivers/gpu/drm/rcar-du/rcar_lvds.c #define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */ BIT 40 drivers/gpu/drm/rcar-du/rcar_lvds.c #define RCAR_LVDS_QUIRK_GEN3_LVEN BIT(1) /* LVEN bit needs to be set on R8A77970/R8A7799x */ BIT 41 drivers/gpu/drm/rcar-du/rcar_lvds.c #define RCAR_LVDS_QUIRK_PWD BIT(2) /* PWD bit available (all of Gen3 but E3) */ BIT 42 drivers/gpu/drm/rcar-du/rcar_lvds.c #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */ BIT 43 drivers/gpu/drm/rcar-du/rcar_lvds.c #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */ BIT 34 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c #define RK3288_EDP_LCDC_SEL BIT(5) BIT 36 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c #define RK3399_EDP_LCDC_SEL BIT(5) BIT 35 drivers/gpu/drm/rockchip/cdn-dp-core.c #define DP_SEL_VOP_LIT BIT(12) BIT 260 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_FRMR_DATA_CLK_RSTN_EN BIT(11) BIT 261 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_FRMR_DATA_CLK_EN BIT(10) BIT 262 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_PHY_DATA_RSTN_EN BIT(9) BIT 263 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_PHY_DATA_CLK_EN BIT(8) BIT 264 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_PHY_CHAR_RSTN_EN BIT(7) BIT 265 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_PHY_CHAR_CLK_EN BIT(6) BIT 266 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_AUX_SYS_CLK_RSTN_EN BIT(5) BIT 267 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_AUX_SYS_CLK_EN BIT(4) BIT 268 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_SYS_CLK_RSTN_EN BIT(3) BIT 269 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_SYS_CLK_EN BIT(2) BIT 270 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define CFG_DPTX_VIF_CLK_RSTN_EN BIT(1) BIT 271 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define CFG_DPTX_VIF_CLK_EN BIT(0) BIT 273 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_PHY_RSTN_EN BIT(1) BIT 274 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_PHY_CLK_EN BIT(0) BIT 276 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_PKT_SYS_RSTN_EN BIT(3) BIT 277 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_PKT_SYS_CLK_EN BIT(2) BIT 278 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_PKT_DATA_RSTN_EN BIT(1) BIT 279 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_PKT_DATA_CLK_EN BIT(0) BIT 281 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SPDIF_CDR_CLK_RSTN_EN BIT(5) BIT 282 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SPDIF_CDR_CLK_EN BIT(4) BIT 283 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_AIF_SYS_RSTN_EN BIT(3) BIT 284 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_AIF_SYS_CLK_EN BIT(2) BIT 285 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_AIF_CLK_RSTN_EN BIT(1) BIT 286 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_AIF_CLK_EN BIT(0) BIT 288 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN BIT(3) BIT 289 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_CIPHER_SYS_CLK_EN BIT(2) BIT 290 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_CIPHER_CHAR_CLK_RSTN_EN BIT(1) BIT 291 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_CIPHER_CHAR_CLK_EN BIT(0) BIT 293 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_CRYPTO_SYS_CLK_RSTN_EN BIT(1) BIT 294 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SOURCE_CRYPTO_SYS_CLK_EN BIT(0) BIT 296 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define APB_IRAM_PATH BIT(2) BIT 297 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define APB_DRAM_PATH BIT(1) BIT 298 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define APB_XT_RESET BIT(0) BIT 300 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define MAILBOX_INT_MASK_BIT BIT(1) BIT 301 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define PIF_INT_MASK_BIT BIT(0) BIT 345 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_EVENT_ENABLE_HPD BIT(0) BIT 346 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_EVENT_ENABLE_TRAINING BIT(1) BIT 355 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define TU_CNT_RST_EN BIT(15) BIT 356 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define VIF_BYPASS_INTERLACE BIT(13) BIT 357 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define INTERLACE_FMT_DET BIT(12) BIT 360 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DP_FRAMER_SP_INTERLACE_EN BIT(2) BIT 361 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DP_FRAMER_SP_HSP BIT(1) BIT 362 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DP_FRAMER_SP_VSP BIT(0) BIT 371 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SCRAMBLER_EN BIT(4) BIT 373 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define FULL_LT_STARTED BIT(0) BIT 374 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define FASE_LT_STARTED BIT(1) BIT 375 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define CLK_RECOVERY_FINISHED BIT(2) BIT 376 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define EQ_PHASE_FINISHED BIT(3) BIT 377 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define FASE_LT_START_FINISHED BIT(4) BIT 378 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define CLK_RECOVERY_FAILED BIT(5) BIT 379 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define EQ_PHASE_FAILED BIT(6) BIT 380 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define FASE_LT_FAILED BIT(7) BIT 382 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_HPD_EVENT BIT(0) BIT 383 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define DPTX_TRAINING_EVENT BIT(1) BIT 384 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define HDCP_TX_STATUS_EVENT BIT(4) BIT 385 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define HDCP2_TX_IS_KM_STORED_EVENT BIT(5) BIT 386 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define HDCP2_TX_STORE_KM_EVENT BIT(6) BIT 387 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT BIT(7) BIT 393 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define AUDIO_PACK_EN BIT(8) BIT 396 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SYNC_WR_TO_CH_ZERO BIT(1) BIT 397 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define I2S_DEC_START BIT(1) BIT 398 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define AUDIO_SW_RST BIT(0) BIT 399 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SMPL2PKT_EN BIT(1) BIT 406 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define TRANS_SMPL_WIDTH_24 BIT(11) BIT 409 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SPDIF_ENABLE BIT(21) BIT 410 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SPDIF_AVG_SEL BIT(20) BIT 411 drivers/gpu/drm/rockchip/cdn-dp-reg.h #define SPDIF_JITTER_BYPASS BIT(19) BIT 434 drivers/gpu/drm/rockchip/cdn-dp-reg.h PTS1 = BIT(0), BIT 435 drivers/gpu/drm/rockchip/cdn-dp-reg.h PTS2 = BIT(1), BIT 436 drivers/gpu/drm/rockchip/cdn-dp-reg.h PTS3 = BIT(2), BIT 437 drivers/gpu/drm/rockchip/cdn-dp-reg.h PTS4 = BIT(3), BIT 438 drivers/gpu/drm/rockchip/cdn-dp-reg.h DP_NONE = BIT(4) BIT 29 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define PHY_ENFORCEPLL BIT(3) BIT 31 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define PHY_ENABLECLK BIT(2) BIT 33 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define PHY_UNRSTZ BIT(1) BIT 35 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define PHY_UNSHUTDOWNZ BIT(0) BIT 42 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define LOCK BIT(0) BIT 43 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define STOP_STATE_CLK_LANE BIT(2) BIT 46 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define PHY_TESTCLK BIT(1) BIT 48 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define PHY_TESTCLR BIT(0) BIT 52 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define PHY_TESTEN BIT(16) BIT 65 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define BYPASS_VCO_RANGE BIT(7) BIT 70 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define REF_BIAS_CUR_SEL BIT(0) BIT 78 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define CP_PROGRAM_EN BIT(7) BIT 85 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define LPF_PROGRAM_EN BIT(6) BIT 92 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define HIGH_PROGRAM_EN BIT(7) BIT 95 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define PLL_LOOP_DIV_EN BIT(5) BIT 96 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define PLL_INPUT_DIV_EN BIT(4) BIT 98 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define POWER_CONTROL BIT(6) BIT 99 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define INTERNAL_REG_CURRENT BIT(3) BIT 100 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define BIAS_BLOCK_ON BIT(2) BIT 101 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define BANDGAP_ON BIT(0) BIT 103 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define TER_RESISTOR_HIGH BIT(7) BIT 105 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define LEVEL_SHIFTERS_ON BIT(6) BIT 106 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define TER_CAL_DONE BIT(5) BIT 108 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define POWER_MANAGE BIT(1) BIT 109 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define TER_RESISTORS_ON BIT(0) BIT 113 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define TLP_PROGRAM_EN BIT(7) BIT 114 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define THS_PRE_PROGRAM_EN BIT(7) BIT 115 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define THS_ZERO_PROGRAM_EN BIT(6) BIT 139 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) BIT 140 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define DW_MIPI_NEEDS_GRF_CLK BIT(1) BIT 143 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define RK3288_DSI0_LCDC_SEL BIT(6) BIT 144 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define RK3288_DSI1_LCDC_SEL BIT(9) BIT 147 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define RK3399_DSI0_LCDC_SEL BIT(0) BIT 148 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define RK3399_DSI1_LCDC_SEL BIT(4) BIT 163 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define RK3399_TXRX_MASTERSLAVEZ BIT(7) BIT 164 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define RK3399_TXRX_ENABLECLK BIT(6) BIT 165 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define RK3399_TXRX_BASEDIR BIT(5) BIT 450 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c BIT(5) | ns2bc(dsi, 100)); BIT 452 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c BIT(5) | (ns2bc(dsi, 60) + 7)); BIT 463 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c BIT(5) | ns2bc(dsi, 100)); BIT 22 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3228_HDMI_SDAIN_MSK BIT(14) BIT 23 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3228_HDMI_SCLIN_MSK BIT(13) BIT 25 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3228_HDMI_HPD_VSEL BIT(6) BIT 26 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3228_HDMI_SDA_VSEL BIT(5) BIT 27 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3228_HDMI_SCL_VSEL BIT(4) BIT 30 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3288_HDMI_LCDC_SEL BIT(4) BIT 33 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_SDAIN_MSK BIT(11) BIT 34 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_SCLIN_MSK BIT(10) BIT 35 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_HPD_IOE BIT(2) BIT 38 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_SDA5V_GRF BIT(15) BIT 39 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_SCL5V_GRF BIT(14) BIT 40 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_HPD5V_GRF BIT(13) BIT 41 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_CEC5V_GRF BIT(12) BIT 43 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_HPD_SARADC BIT(13) BIT 44 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_CEC_5V BIT(11) BIT 45 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_SDA_5V BIT(10) BIT 46 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_SCL_5V BIT(9) BIT 47 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3328_HDMI_HPD_5V BIT(8) BIT 50 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define RK3399_HDMI_LCDC_SEL BIT(6) BIT 11 drivers/gpu/drm/rockchip/rk3066_hdmi.h #define HDMI_VIDEO_SEL BIT(14) BIT 135 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_AUDIO_EXTERNAL_CTS = BIT(7), BIT 185 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_VIDEO_VSYNC_ACTIVE_HIGH = BIT(3), BIT 187 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_VIDEO_HSYNC_ACTIVE_HIGH = BIT(2), BIT 189 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_VIDEO_MODE_INTERLACE = BIT(1), BIT 191 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_EXT_VIDEO_SET_EN = BIT(0), BIT 197 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_VIDEO_CLR_AV_MUTE = BIT(7), BIT 198 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_VIDEO_SET_AV_MUTE = BIT(6), BIT 199 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_AUDIO_CP_LOGIC_RESET_MASK = BIT(2), BIT 200 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_AUDIO_CP_LOGIC_RESET = BIT(2), BIT 202 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_AUDIO_DISABLE = BIT(1), BIT 203 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_VIDEO_DISABLE = BIT(0), BIT 212 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_INTR_HOTPLUG = BIT(7), BIT 213 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_INTR_MSENS = BIT(6), BIT 214 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_INTR_VSYNC = BIT(5), BIT 215 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_INTR_AUDIO_FIFO_FULL = BIT(4), BIT 217 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_INTR_EDID_READY = BIT(2), BIT 218 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_INTR_EDID_ERR = BIT(1), BIT 221 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_VIDEO_MODE_MASK = BIT(1), BIT 222 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_VIDEO_MODE_HDMI = BIT(1), BIT 225 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_HPG_IN_STATUS_HIGH = BIT(7), BIT 226 drivers/gpu/drm/rockchip/rk3066_hdmi.h HDMI_MSENS_IN_STATUS_HIGH = BIT(6), BIT 545 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); BIT 640 drivers/gpu/drm/rockchip/rockchip_drm_vop.c enabled && (vop->win_enabled & BIT(i))); BIT 913 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop->win_enabled |= BIT(win_index); BIT 1120 drivers/gpu/drm/rockchip/rockchip_drm_vop.c pin_pol = BIT(DCLK_INVERT); BIT 1122 drivers/gpu/drm/rockchip/rockchip_drm_vop.c BIT(HSYNC_POSITIVE) : 0; BIT 1124 drivers/gpu/drm/rockchip/rockchip_drm_vop.c BIT(VSYNC_POSITIVE) : 0; BIT 1148 drivers/gpu/drm/rockchip/rockchip_drm_vop.c pin_pol &= ~BIT(DCLK_INVERT); BIT 174 drivers/gpu/drm/rockchip/rockchip_drm_vop.h #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) BIT 175 drivers/gpu/drm/rockchip/rockchip_drm_vop.h #define VOP_FEATURE_INTERNAL_RGB BIT(1) BIT 228 drivers/gpu/drm/rockchip/rockchip_drm_vop.h #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) BIT 13 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7) BIT 14 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6) BIT 15 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5) BIT 16 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4) BIT 17 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3) BIT 18 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2) BIT 19 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1) BIT 20 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0) BIT 23 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5) BIT 24 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4) BIT 25 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG1_LANE3_BIAS BIT(3) BIT 26 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG1_LANE2_BIAS BIT(2) BIT 27 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG1_LANE1_BIAS BIT(1) BIT 28 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0) BIT 31 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG2_RESERVE_ON BIT(7) BIT 32 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE BIT(6) BIT 33 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE BIT(5) BIT 34 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE BIT(4) BIT 35 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE BIT(3) BIT 36 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE BIT(2) BIT 37 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE BIT(1) BIT 38 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0) BIT 44 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE BIT(5) BIT 45 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4) BIT 46 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3) BIT 47 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2) BIT 48 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1) BIT 49 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0) BIT 52 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA BIT(5) BIT 53 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4) BIT 54 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3) BIT 55 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2) BIT 56 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1) BIT 57 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0) BIT 77 drivers/gpu/drm/rockchip/rockchip_lvds.h (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0) BIT 83 drivers/gpu/drm/rockchip/rockchip_lvds.h #define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3) BIT 86 drivers/gpu/drm/rockchip/rockchip_lvds.h #define LVDS_MSB BIT(3) BIT 87 drivers/gpu/drm/rockchip/rockchip_lvds.h #define LVDS_DUAL BIT(4) BIT 88 drivers/gpu/drm/rockchip/rockchip_lvds.h #define LVDS_FMT_1 BIT(5) BIT 89 drivers/gpu/drm/rockchip/rockchip_lvds.h #define LVDS_TTL_EN BIT(6) BIT 90 drivers/gpu/drm/rockchip/rockchip_lvds.h #define LVDS_START_PHASE_RST_1 BIT(7) BIT 91 drivers/gpu/drm/rockchip/rockchip_lvds.h #define LVDS_DCLK_INV BIT(8) BIT 92 drivers/gpu/drm/rockchip/rockchip_lvds.h #define LVDS_CH0_EN BIT(11) BIT 93 drivers/gpu/drm/rockchip/rockchip_lvds.h #define LVDS_CH1_EN BIT(12) BIT 94 drivers/gpu/drm/rockchip/rockchip_lvds.h #define LVDS_PWRDN BIT(15) BIT 501 drivers/gpu/drm/selftests/test-drm_mm.c const unsigned int count = min_t(unsigned int, BIT(10), max_iterations); BIT 704 drivers/gpu/drm/selftests/test-drm_mm.c const unsigned int count = min_t(unsigned int, BIT(10), max_iterations); BIT 731 drivers/gpu/drm/selftests/test-drm_mm.c const unsigned int count = min_t(unsigned int, BIT(10), max_iterations); BIT 993 drivers/gpu/drm/selftests/test-drm_mm.c const unsigned int count = min_t(unsigned int, BIT(13), max_iterations); BIT 32 drivers/gpu/drm/sti/sti_cursor.c #define CUR_CTL_CLUT_UPDATE BIT(1) BIT 32 drivers/gpu/drm/sti/sti_dvo.c #define DVO_AWG_CTRL_EN BIT(0) BIT 33 drivers/gpu/drm/sti/sti_dvo.c #define DVO_AWG_FRAME_BASED_SYNC BIT(2) BIT 35 drivers/gpu/drm/sti/sti_dvo.c #define DVO_DOF_EN_LOWBYTE BIT(0) BIT 36 drivers/gpu/drm/sti/sti_dvo.c #define DVO_DOF_EN_MIDBYTE BIT(1) BIT 37 drivers/gpu/drm/sti/sti_dvo.c #define DVO_DOF_EN_HIGHBYTE BIT(2) BIT 38 drivers/gpu/drm/sti/sti_dvo.c #define DVO_DOF_EN BIT(6) BIT 23 drivers/gpu/drm/sti/sti_gdp.c #define ALPHASWITCH BIT(6) BIT 24 drivers/gpu/drm/sti/sti_gdp.c #define ENA_COLOR_FILL BIT(8) BIT 25 drivers/gpu/drm/sti/sti_gdp.c #define BIGNOTLITTLE BIT(23) BIT 26 drivers/gpu/drm/sti/sti_gdp.c #define WAIT_NEXT_VSYNC BIT(31) BIT 70 drivers/gpu/drm/sti/sti_gdp.c #define GAM_GDP_ALPHARANGE_255 BIT(5) BIT 72 drivers/gpu/drm/sti/sti_gdp.c #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) BIT 48 drivers/gpu/drm/sti/sti_hda.c #define CFG_AWG_ASYNC_EN BIT(0) BIT 49 drivers/gpu/drm/sti/sti_hda.c #define CFG_AWG_ASYNC_HSYNC_MTD BIT(1) BIT 50 drivers/gpu/drm/sti/sti_hda.c #define CFG_AWG_ASYNC_VSYNC_MTD BIT(2) BIT 51 drivers/gpu/drm/sti/sti_hda.c #define CFG_AWG_SYNC_DEL BIT(3) BIT 57 drivers/gpu/drm/sti/sti_hda.c #define CFG_SYNC_ON_PBPR_MASK BIT(8) BIT 58 drivers/gpu/drm/sti/sti_hda.c #define CFG_PREFILTER_EN_MASK BIT(9) BIT 69 drivers/gpu/drm/sti/sti_hda.c #define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1) BIT 96 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_CFG_DEVICE_EN BIT(0) BIT 97 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_CFG_HDMI_NOT_DVI BIT(1) BIT 98 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_CFG_HDCP_EN BIT(2) BIT 99 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_CFG_ESS_NOT_OESS BIT(3) BIT 100 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_CFG_H_SYNC_POL_NEG BIT(4) BIT 101 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_CFG_V_SYNC_POL_NEG BIT(6) BIT 102 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_CFG_422_EN BIT(8) BIT 103 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12) BIT 104 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13) BIT 105 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_CFG_SW_RST_EN BIT(31) BIT 107 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_INT_GLOBAL BIT(0) BIT 108 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_INT_SW_RST BIT(1) BIT 109 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_INT_PIX_CAP BIT(3) BIT 110 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_INT_HOT_PLUG BIT(4) BIT 111 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_INT_DLL_LCK BIT(5) BIT 112 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_INT_NEW_FRAME BIT(6) BIT 113 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_INT_GENCTRL_PKT BIT(7) BIT 114 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_INT_AUDIO_FIFO_XRUN BIT(8) BIT 115 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_INT_SINK_TERM_PRESENT BIT(11) BIT 132 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_STA_SW_RST BIT(1) BIT 134 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_8CH BIT(0) BIT 135 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_SPDIF_DIV_2 BIT(1) BIT 136 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_SPDIF_DIV_3 BIT(2) BIT 137 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_SPDIF_CLK_DIV_4 (BIT(1) | BIT(2)) BIT 138 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_CTS_CLK_256FS BIT(12) BIT 139 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_DTS_INVALID BIT(16) BIT 140 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_ONE_BIT_INVALID (BIT(18) | BIT(19) | BIT(20) | BIT(21)) BIT 141 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_CH12_VALID BIT(28) BIT 142 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_CH34_VALID BIT(29) BIT 143 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_CH56_VALID BIT(30) BIT 144 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_AUD_CFG_CH78_VALID BIT(31) BIT 148 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_SAMPLE_FLAT_SP0 BIT(0) BIT 149 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_SAMPLE_FLAT_SP1 BIT(1) BIT 150 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_SAMPLE_FLAT_SP2 BIT(2) BIT 151 drivers/gpu/drm/sti/sti_hdmi.c #define HDMI_SAMPLE_FLAT_SP3 BIT(3) BIT 19 drivers/gpu/drm/sti/sti_hdmi.h #define HDMI_STA_DLL_LCK BIT(5) BIT 20 drivers/gpu/drm/sti/sti_hdmi.h #define HDMI_STA_HOT_PLUG BIT(4) BIT 16 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c #define HDMI_SRZ_CFG_EN BIT(0) BIT 17 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c #define HDMI_SRZ_CFG_DISABLE_BYPASS_SINK_CURRENT BIT(1) BIT 18 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c #define HDMI_SRZ_CFG_EXTERNAL_DATA BIT(16) BIT 19 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c #define HDMI_SRZ_CFG_RBIAS_EXT BIT(17) BIT 20 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c #define HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION BIT(18) BIT 21 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c #define HDMI_SRZ_CFG_EN_BIASRES_DETECTION BIT(19) BIT 22 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c #define HDMI_SRZ_CFG_EN_SRC_TERMINATION BIT(24) BIT 32 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c #define PLL_CFG_EN BIT(0) BIT 73 drivers/gpu/drm/sti/sti_hqvdp.c #define SW_RESET_CTRL_FULL BIT(0) BIT 74 drivers/gpu/drm/sti/sti_hqvdp.c #define SW_RESET_CTRL_CORE BIT(1) BIT 77 drivers/gpu/drm/sti/sti_hqvdp.c #define STARTUP_CTRL1_RST_DONE BIT(0) BIT 78 drivers/gpu/drm/sti/sti_hqvdp.c #define STARTUP_CTRL1_AUTH_IDLE BIT(2) BIT 81 drivers/gpu/drm/sti/sti_hqvdp.c #define STARTUP_CTRL2_FETCH_EN BIT(1) BIT 84 drivers/gpu/drm/sti/sti_hqvdp.c #define INFO_XP70_FW_READY BIT(15) BIT 85 drivers/gpu/drm/sti/sti_hqvdp.c #define INFO_XP70_FW_PROCESSING BIT(14) BIT 86 drivers/gpu/drm/sti/sti_hqvdp.c #define INFO_XP70_FW_INITQUEUES BIT(13) BIT 45 drivers/gpu/drm/sti/sti_mixer.c #define GAM_CTL_BACK_MASK BIT(0) BIT 46 drivers/gpu/drm/sti/sti_mixer.c #define GAM_CTL_VID0_MASK BIT(1) BIT 47 drivers/gpu/drm/sti/sti_mixer.c #define GAM_CTL_VID1_MASK BIT(2) BIT 48 drivers/gpu/drm/sti/sti_mixer.c #define GAM_CTL_GDP0_MASK BIT(3) BIT 49 drivers/gpu/drm/sti/sti_mixer.c #define GAM_CTL_GDP1_MASK BIT(4) BIT 50 drivers/gpu/drm/sti/sti_mixer.c #define GAM_CTL_GDP2_MASK BIT(5) BIT 51 drivers/gpu/drm/sti/sti_mixer.c #define GAM_CTL_GDP3_MASK BIT(6) BIT 52 drivers/gpu/drm/sti/sti_mixer.c #define GAM_CTL_CURSOR_MASK BIT(9) BIT 62 drivers/gpu/drm/sti/sti_tvout.c #define TVO_IN_FMT_SIGNED BIT(0) BIT 63 drivers/gpu/drm/sti/sti_tvout.c #define TVO_SYNC_EXT BIT(4) BIT 102 drivers/gpu/drm/sti/sti_tvout.c #define ENCODER_CRTC_MASK (BIT(0) | BIT(1)) BIT 34 drivers/gpu/drm/sti/sti_vid.c #define VID_CTL_IGNORE (BIT(31) | BIT(30)) BIT 35 drivers/gpu/drm/sti/sti_vid.c #define VID_CTL_PSI_ENABLE (BIT(2) | BIT(1) | BIT(0)) BIT 63 drivers/gpu/drm/sti/sti_vtg.c #define VTG_IRQ_BOTTOM BIT(0) BIT 64 drivers/gpu/drm/sti/sti_vtg.c #define VTG_IRQ_TOP BIT(1) BIT 32 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WCFGR_DSIM BIT(0) /* DSI Mode */ BIT 36 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WCR_DSIEN BIT(3) /* DSI ENable */ BIT 39 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WISR_PLLLS BIT(8) /* PLL Lock Status */ BIT 40 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WISR_RRS BIT(12) /* Regulator Ready Status */ BIT 44 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */ BIT 47 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WRPCR_PLLEN BIT(0) /* PLL ENable */ BIT 51 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WRPCR_REGEN BIT(24) /* REGulator ENable */ BIT 52 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */ BIT 115 drivers/gpu/drm/stm/ltdc.c #define GCR_LTDCEN BIT(0) /* LTDC ENable */ BIT 116 drivers/gpu/drm/stm/ltdc.c #define GCR_DEN BIT(16) /* Dither ENable */ BIT 117 drivers/gpu/drm/stm/ltdc.c #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ BIT 118 drivers/gpu/drm/stm/ltdc.c #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ BIT 119 drivers/gpu/drm/stm/ltdc.c #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ BIT 120 drivers/gpu/drm/stm/ltdc.c #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ BIT 125 drivers/gpu/drm/stm/ltdc.c #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ BIT 128 drivers/gpu/drm/stm/ltdc.c #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ BIT 129 drivers/gpu/drm/stm/ltdc.c #define GC1R_BCP BIT(22) /* Background Colour Programmable */ BIT 130 drivers/gpu/drm/stm/ltdc.c #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ BIT 131 drivers/gpu/drm/stm/ltdc.c #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ BIT 132 drivers/gpu/drm/stm/ltdc.c #define GC1R_TP BIT(25) /* Timing Programmable */ BIT 133 drivers/gpu/drm/stm/ltdc.c #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ BIT 134 drivers/gpu/drm/stm/ltdc.c #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ BIT 135 drivers/gpu/drm/stm/ltdc.c #define GC1R_DWP BIT(28) /* Dither Width Programmable */ BIT 136 drivers/gpu/drm/stm/ltdc.c #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ BIT 137 drivers/gpu/drm/stm/ltdc.c #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ BIT 139 drivers/gpu/drm/stm/ltdc.c #define GC2R_EDCA BIT(0) /* External Display Control Ability */ BIT 140 drivers/gpu/drm/stm/ltdc.c #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ BIT 141 drivers/gpu/drm/stm/ltdc.c #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ BIT 142 drivers/gpu/drm/stm/ltdc.c #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ BIT 144 drivers/gpu/drm/stm/ltdc.c #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ BIT 146 drivers/gpu/drm/stm/ltdc.c #define SRCR_IMR BIT(0) /* IMmediate Reload */ BIT 147 drivers/gpu/drm/stm/ltdc.c #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ BIT 155 drivers/gpu/drm/stm/ltdc.c #define IER_LIE BIT(0) /* Line Interrupt Enable */ BIT 156 drivers/gpu/drm/stm/ltdc.c #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ BIT 157 drivers/gpu/drm/stm/ltdc.c #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ BIT 158 drivers/gpu/drm/stm/ltdc.c #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ BIT 162 drivers/gpu/drm/stm/ltdc.c #define ISR_LIF BIT(0) /* Line Interrupt Flag */ BIT 163 drivers/gpu/drm/stm/ltdc.c #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ BIT 164 drivers/gpu/drm/stm/ltdc.c #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ BIT 165 drivers/gpu/drm/stm/ltdc.c #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ BIT 167 drivers/gpu/drm/stm/ltdc.c #define LXCR_LEN BIT(0) /* Layer ENable */ BIT 168 drivers/gpu/drm/stm/ltdc.c #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ BIT 169 drivers/gpu/drm/stm/ltdc.c #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ BIT 21 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_MODCTL_LINE_SEL BIT(29) BIT 22 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_MODCTL_ITLMOD_EN BIT(28) BIT 28 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_MODCTL_HWC_EN BIT(16) BIT 29 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_MODCTL_LAY_EN(l) BIT(8 + l) BIT 30 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_MODCTL_OCSC_EN BIT(5) BIT 31 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_MODCTL_DFLK_EN BIT(4) BIT 32 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_MODCTL_DLP_START_CTL BIT(2) BIT 33 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_MODCTL_START_CTL BIT(1) BIT 34 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0) BIT 60 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS BIT(1) BIT 61 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_REGBUFFCTL_LOADCTL BIT(0) BIT 69 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK BIT(15) BIT 73 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN BIT(2) BIT 74 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN BIT(1) BIT 75 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN BIT(0) BIT 103 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_REG_LOAD_FINISHED BIT(1) BIT 128 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_IYUVCTL_EN BIT(0) BIT 146 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_OCCTL_ENABLE BIT(0) BIT 31 drivers/gpu/drm/sun4i/sun4i_dotclock.c BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0); BIT 39 drivers/gpu/drm/sun4i/sun4i_dotclock.c BIT(SUN4I_TCON0_DCLK_GATE_BIT), BIT 40 drivers/gpu/drm/sun4i/sun4i_dotclock.c BIT(SUN4I_TCON0_DCLK_GATE_BIT)); BIT 50 drivers/gpu/drm/sun4i/sun4i_dotclock.c return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT); BIT 13 drivers/gpu/drm/sun4i/sun4i_frontend.h #define SUN4I_FRONTEND_EN_EN BIT(0) BIT 16 drivers/gpu/drm/sun4i/sun4i_frontend.h #define SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL BIT(23) BIT 17 drivers/gpu/drm/sun4i/sun4i_frontend.h #define SUN4I_FRONTEND_FRM_CTRL_FRM_START BIT(16) BIT 18 drivers/gpu/drm/sun4i/sun4i_frontend.h #define SUN4I_FRONTEND_FRM_CTRL_COEF_RDY BIT(1) BIT 19 drivers/gpu/drm/sun4i/sun4i_frontend.h #define SUN4I_FRONTEND_FRM_CTRL_REG_RDY BIT(0) BIT 22 drivers/gpu/drm/sun4i/sun4i_frontend.h #define SUN4I_FRONTEND_BYPASS_CSC_EN BIT(1) BIT 18 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_CTRL_ENABLE BIT(31) BIT 22 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1) BIT 23 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0) BIT 26 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_HPD_HIGH BIT(0) BIT 29 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31) BIT 30 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_VID_CTRL_HDMI_MODE BIT(30) BIT 42 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_VID_TIMING_POL_VSYNC BIT(1) BIT 43 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0) BIT 48 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL0_BIASEN BIT(31) BIT 49 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL0_LDOCEN BIT(30) BIT 50 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL0_LDODEN BIT(29) BIT 51 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL0_PWENC BIT(28) BIT 52 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL0_PWEND BIT(27) BIT 53 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL0_PWENG BIT(26) BIT 54 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL0_CKEN BIT(25) BIT 55 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL0_TXEN BIT(23) BIT 58 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_UNKNOWN BIT(24) /* set on A31 */ BIT 59 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23) BIT 60 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22) BIT 61 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20) BIT 62 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19) BIT 63 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_PWSCK BIT(18) BIT 64 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_PWSDT BIT(17) BIT 65 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15) BIT 66 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14) BIT 68 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6) BIT 72 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_INVERT_R BIT(2) BIT 73 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_INVERT_G BIT(1) BIT 74 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PAD_CTRL1_INVERT_B BIT(0) BIT 77 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PLL_CTRL_PLL_EN BIT(31) BIT 78 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PLL_CTRL_BWS BIT(30) BIT 79 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PLL_CTRL_HV_IS_33 BIT(29) BIT 80 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PLL_CTRL_LDO1_EN BIT(28) BIT 81 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PLL_CTRL_LDO2_EN BIT(27) BIT 82 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PLL_CTRL_SDIV2 BIT(25) BIT 93 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21) BIT 97 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_CEC_ENABLE BIT(11) BIT 98 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_CEC_TX BIT(9) BIT 99 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_CEC_RX BIT(8) BIT 105 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_UNKNOWN_INPUT_SYNC BIT(27) BIT 108 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31) BIT 109 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30) BIT 110 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8) BIT 113 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_CTRL_RESET BIT(0) BIT 122 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION BIT(7) BIT 123 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW BIT(6) BIT 124 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW BIT(5) BIT 125 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST BIT(4) BIT 126 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR BIT(3) BIT 127 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR BIT(2) BIT 128 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR BIT(1) BIT 129 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0) BIT 132 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31) BIT 135 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1) BIT 138 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1) BIT 143 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1) BIT 155 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE BIT(9) BIT 156 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE BIT(8) BIT 162 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN6I_HDMI_DDC_CTRL_RESET BIT(31) BIT 163 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN6I_HDMI_DDC_CTRL_START_CMD BIT(27) BIT 164 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE BIT(6) BIT 165 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE BIT(4) BIT 166 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN6I_HDMI_DDC_CTRL_ENABLE BIT(0) BIT 179 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN6I_HDMI_DDC_INT_STATUS_TIMEOUT BIT(8) BIT 183 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(15) BIT 20 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31) BIT 21 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0) BIT 26 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe)) BIT 27 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE BIT(27) BIT 28 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_ENABLE BIT(26) BIT 29 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe)) BIT 30 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT BIT(11) BIT 31 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT BIT(10) BIT 36 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_FRM_CTL_EN BIT(31) BIT 37 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_FRM_CTL_MODE_R BIT(6) BIT 38 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_FRM_CTL_MODE_G BIT(5) BIT 39 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_FRM_CTL_MODE_B BIT(4) BIT 53 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31) BIT 86 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH BIT(16) BIT 87 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_CPU_IF_TRI_FIFO_EN BIT(2) BIT 88 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_CPU_IF_TRI_EN BIT(0) BIT 100 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_LVDS_IF_EN BIT(31) BIT 101 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK BIT(26) BIT 104 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_LVDS_IF_CLK_SEL_MASK BIT(20) BIT 106 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK BIT(4) BIT 115 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27) BIT 116 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25) BIT 117 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24) BIT 120 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE BIT(25) BIT 121 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE BIT(24) BIT 125 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON1_CTL_TCON_ENABLE BIT(31) BIT 126 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON1_CTL_INTERLACE_ENABLE BIT(20) BIT 159 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON_ECC_FIFO_EN BIT(3) BIT 196 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN6I_TCON0_LVDS_ANA0_EN_MB BIT(31) BIT 197 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN6I_TCON0_LVDS_ANA0_EN_LDO BIT(30) BIT 198 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN6I_TCON0_LVDS_ANA0_EN_DRVC BIT(24) BIT 30 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_EN_ENABLE BIT(0) BIT 33 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_CFG0_DAC_CONTROL_54M BIT(26) BIT 34 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_CFG0_CORE_DATAPATH_54M BIT(25) BIT 35 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_CFG0_CORE_CONTROL_54M BIT(24) BIT 36 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_CFG0_YC_EN BIT(17) BIT 37 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_CFG0_COMP_EN BIT(16) BIT 43 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_DAC0_CLOCK_INVERT BIT(24) BIT 50 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_DAC0_DAC_EN(dac) BIT(dac) BIT 73 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_DETECT_STA_DAC(dac) BIT((dac * 8)) BIT 106 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_12C_NOTCH_WIDTH_WIDE BIT(8) BIT 107 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_12C_COMP_YUV_EN BIT(0) BIT 110 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_RESYNC_FIELD BIT(31) BIT 401 drivers/gpu/drm/sun4i/sun4i_tv.c (tv_mode->dac_bit25_en ? BIT(25) : 0) | BIT 402 drivers/gpu/drm/sun4i/sun4i_tv.c BIT(30)); BIT 36 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_CTL_EN BIT(0) BIT 40 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL_TRAIL_FILL BIT(3) BIT 41 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL_HBP_DIS BIT(2) BIT 42 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS BIT(1) BIT 43 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL_VIDEO_BURST BIT(0) BIT 46 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN BIT(18) BIT 47 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL0_CRC_EN BIT(17) BIT 48 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL0_ECC_EN BIT(16) BIT 49 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL0_INST_ST BIT(0) BIT 53 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL1_VIDEO_FILL BIT(2) BIT 54 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION BIT(1) BIT 55 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_BASIC_CTL1_VIDEO_MODE BIT(0) BIT 69 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_INST_FUNC_LANE_CEN BIT(4) BIT 90 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_TCON_DRQ_ENABLE_MODE BIT(28) BIT 94 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE BIT(16) BIT 151 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_CMD_CTL_RX_OVERFLOW BIT(26) BIT 152 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_CMD_CTL_RX_FLAG BIT(25) BIT 153 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c #define SUN6I_DSI_CMD_CTL_TX_FLAG BIT(9) BIT 208 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c [0] = (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(7) | BIT(10) | BIT 209 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c BIT(11) | BIT(13) | BIT(16) | BIT(20) | BIT(21) | BIT(22) | BIT 210 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c BIT(23)), BIT 211 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c [1] = (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(8) | BIT(10) | BIT 212 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c BIT(12) | BIT(14) | BIT(17) | BIT(20) | BIT(21) | BIT(22) | BIT 213 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c BIT(23)), BIT 214 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c [2] = (BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(9) | BIT(11) | BIT 215 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)), BIT 216 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c [3] = (BIT(1) | BIT(2) | BIT(3) | BIT(7) | BIT(8) | BIT(9) | BIT(13) | BIT 217 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c BIT(14) | BIT(15) | BIT(19) | BIT(20) | BIT(21) | BIT(23)), BIT 218 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c [4] = (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(16) | BIT 219 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)), BIT 220 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c [5] = (BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT 221 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) | BIT 222 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c BIT(23)), BIT 237 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c if (!(BIT(j) & field)) BIT 241 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val = (BIT(j) & data) ? 1 : 0; BIT 244 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c val ^= (BIT(j) & data) ? 1 : 0; BIT 1044 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c dsi->encoder.possible_crtcs = BIT(0); BIT 22 drivers/gpu/drm/sun4i/sun8i_csc.h #define SUN8I_CSC_CTRL_EN BIT(0) BIT 18 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0) BIT 20 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8) BIT 21 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9) BIT 26 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31) BIT 35 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SWI BIT(31) BIT 36 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWEND BIT(30) BIT 37 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWENC BIT(29) BIT 38 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW BIT(28) BIT 41 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT BIT(23) BIT 42 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT BIT(22) BIT 43 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT BIT(21) BIT 44 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT BIT(20) BIT 45 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL BIT(19) BIT 46 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG BIT(18) BIT 47 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS BIT(17) BIT 48 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN BIT(16) BIT 51 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK BIT(11) BIT 52 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 BIT(10) BIT 53 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 BIT(9) BIT 54 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 BIT(8) BIT 55 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK BIT(7) BIT 56 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 BIT(6) BIT 57 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 BIT(5) BIT 58 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 BIT(4) BIT 59 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_CKEN BIT(3) BIT 60 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_LDOEN BIT(2) BIT 61 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_ENVBS BIT(1) BIT 62 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_ENBI BIT(0) BIT 65 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG2_M_EN BIT(31) BIT 66 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG2_PLLDBEN BIT(30) BIT 67 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG2_SEN BIT(29) BIT 68 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDPD BIT(28) BIT 69 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDEN BIT(27) BIT 70 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLRCK BIT(26) BIT 72 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK BIT(22) BIT 73 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN BIT(21) BIT 76 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK BIT(16) BIT 77 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW BIT(15) BIT 92 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG3_SDAPD BIT(3) BIT 93 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG3_SDAEN BIT(2) BIT 94 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG3_SCLPD BIT(1) BIT 95 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG3_SCLEN BIT(0) BIT 98 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 BIT(31) BIT 99 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD BIT(30) BIT 100 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN BIT(29) BIT 101 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28) BIT 102 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27) BIT 103 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26) BIT 105 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25) BIT 108 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN BIT(19) BIT 109 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_CS BIT(18) BIT 112 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_BWS BIT(6) BIT 117 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_SV_H BIT(31) BIT 121 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_PCLK_SEL BIT(23) BIT 122 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_AUTOSYNC_DIS BIT(22) BIT 123 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_VREG2_OUT_EN BIT(21) BIT 124 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_VREG1_OUT_EN BIT(20) BIT 125 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN BIT(19) BIT 128 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_VCO_RST_IN BIT(11) BIT 129 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_SINT_FRAC BIT(10) BIT 130 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_SDIV2 BIT(9) BIT 132 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_S6P25_7P5 BIT(5) BIT 133 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_S5_7 BIT(4) BIT 139 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2 BIT(0) BIT 144 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_STS_RCALEND2D BIT(7) BIT 24 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0) BIT 26 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0) BIT 60 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe) BIT 61 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe) BIT 71 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1) BIT 73 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch) BIT 254 drivers/gpu/drm/sun4i/sun8i_ui_layer.c if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { BIT 38 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN BIT(0) BIT 35 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h #define SUN8I_SCALER_GSU_CTRL_EN BIT(0) BIT 36 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h #define SUN8I_SCALER_GSU_CTRL_COEFF_RDY BIT(4) BIT 339 drivers/gpu/drm/sun4i/sun8i_vi_layer.c if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { BIT 524 drivers/gpu/drm/sun4i/sun8i_vi_layer.c supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) | BIT 525 drivers/gpu/drm/sun4i/sun8i_vi_layer.c BIT(DRM_COLOR_YCBCR_BT709); BIT 527 drivers/gpu/drm/sun4i/sun8i_vi_layer.c supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT 528 drivers/gpu/drm/sun4i/sun8i_vi_layer.c BIT(DRM_COLOR_YCBCR_FULL_RANGE); BIT 32 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN BIT(0) BIT 34 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE BIT(15) BIT 54 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CTRL_EN BIT(0) BIT 55 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CTRL_COEFF_RDY BIT(4) BIT 1137 drivers/gpu/drm/tegra/dsi.c if (errors & BIT(i)) BIT 394 drivers/gpu/drm/tegra/hdmi.c cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1); BIT 95 drivers/gpu/drm/tilcdc/tilcdc_external.c priv->external_encoder->possible_crtcs = BIT(0); BIT 17 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_END_OF_FRAME1 BIT(9) BIT 18 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_END_OF_FRAME0 BIT(8) BIT 19 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_PL_LOAD_DONE BIT(6) BIT 20 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_FIFO_UNDERFLOW BIT(5) BIT 21 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_SYNC_LOST BIT(2) BIT 22 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_FRAME_DONE BIT(0) BIT 34 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V1_END_OF_FRAME_INT_ENA BIT(2) BIT 35 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V2_END_OF_FRAME0_INT_ENA BIT(8) BIT 36 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V2_END_OF_FRAME1_INT_ENA BIT(9) BIT 37 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_DUAL_FRAME_BUFFER_ENABLE BIT(0) BIT 51 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_MONO_8BIT_MODE BIT(9) BIT 52 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_RASTER_ORDER BIT(8) BIT 53 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_TFT_MODE BIT(7) BIT 54 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V1_UNDERFLOW_INT_ENA BIT(6) BIT 55 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V2_UNDERFLOW_INT_ENA BIT(5) BIT 56 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V1_PL_INT_ENA BIT(4) BIT 57 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V2_PL_INT_ENA BIT(6) BIT 58 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V1_SYNC_LOST_INT_ENA BIT(5) BIT 59 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V1_FRAME_DONE_INT_ENA BIT(3) BIT 60 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_MONOCHROME_MODE BIT(1) BIT 61 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_RASTER_ENABLE BIT(0) BIT 62 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_TFT_ALT_ENABLE BIT(23) BIT 63 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_STN_565_ENABLE BIT(24) BIT 64 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V2_DMA_CLK_EN BIT(2) BIT 65 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V2_LIDD_CLK_EN BIT(1) BIT 66 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V2_CORE_CLK_EN BIT(0) BIT 68 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V2_TFT_24BPP_MODE BIT(25) BIT 69 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_V2_TFT_24BPP_UNPACK BIT(26) BIT 76 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_SYNC_CTRL BIT(25) BIT 77 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_SYNC_EDGE BIT(24) BIT 78 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_INVERT_PIXEL_CLOCK BIT(22) BIT 79 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_INVERT_HSYNC BIT(21) BIT 80 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_INVERT_VSYNC BIT(20) BIT 81 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_LPP_B10 BIT(26) BIT 107 drivers/gpu/drm/tilcdc/tilcdc_regs.h #define LCDC_CLK_MAIN_RESET BIT(3) BIT 47 drivers/gpu/drm/tiny/ili9341.c #define ILI9341_MADCTL_BGR BIT(3) BIT 48 drivers/gpu/drm/tiny/ili9341.c #define ILI9341_MADCTL_MV BIT(5) BIT 49 drivers/gpu/drm/tiny/ili9341.c #define ILI9341_MADCTL_MX BIT(6) BIT 50 drivers/gpu/drm/tiny/ili9341.c #define ILI9341_MADCTL_MY BIT(7) BIT 45 drivers/gpu/drm/tiny/mi0283qt.c #define ILI9341_MADCTL_BGR BIT(3) BIT 46 drivers/gpu/drm/tiny/mi0283qt.c #define ILI9341_MADCTL_MV BIT(5) BIT 47 drivers/gpu/drm/tiny/mi0283qt.c #define ILI9341_MADCTL_MX BIT(6) BIT 48 drivers/gpu/drm/tiny/mi0283qt.c #define ILI9341_MADCTL_MY BIT(7) BIT 525 drivers/gpu/drm/tiny/repaper.c byte |= BIT(7); BIT 45 drivers/gpu/drm/tiny/st7586.c #define ST7586_DISP_CTRL_MX BIT(6) BIT 46 drivers/gpu/drm/tiny/st7586.c #define ST7586_DISP_CTRL_MY BIT(7) BIT 37 drivers/gpu/drm/tiny/st7735r.c #define ST7735R_MY BIT(7) BIT 38 drivers/gpu/drm/tiny/st7735r.c #define ST7735R_MX BIT(6) BIT 39 drivers/gpu/drm/tiny/st7735r.c #define ST7735R_MV BIT(5) BIT 36 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_INT_BUS_ERR BIT(7) BIT 37 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_INT_V_STATUS BIT(6) /* vertical blank */ BIT 38 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_INT_V_NEXT_FRAME BIT(5) BIT 39 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_INT_U_NEXT_FRAME BIT(4) BIT 40 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_INT_Y_NEXT_FRAME BIT(3) BIT 41 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_INT_V_FIFO_UNDERRUN BIT(2) BIT 42 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_INT_U_FIFO_UNDERRUN BIT(1) BIT 43 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_INT_Y_FIFO_UNDERRUN BIT(0) BIT 49 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_CTRL_YUV420 BIT(31) BIT 50 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_CTRL_CSMODE BIT(30) BIT 51 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_CTRL_NONINTERLACE BIT(28) /* 0 = non-interlace CCIR656 */ BIT 52 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_CTRL_TVCLKP BIT(27) /* Inverted clock phase */ BIT 68 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_CTRL_BBBP BIT(15) /* 0 = little-endian */ BIT 82 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_CTRL_NTSC BIT(9) /* 0 = PAL, 1 = NTSC */ BIT 83 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_CTRL_INTERLACE BIT(8) /* 1 = interlace, only for D1 */ BIT 94 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_VSTSTYPE_BITS (BIT(4) | BIT(5)) BIT 95 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_BGR BIT(1) /* 0 = RGB, 1 = BGR */ BIT 96 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_TVEEN BIT(0) /* Enable TVE block */ BIT 102 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_CTRL_4_RESET BIT(0) /* triggers reset of TVE200 */ BIT 29 drivers/gpu/drm/v3d/v3d_mmu.c #define V3D_PTE_SUPERPAGE BIT(31) BIT 30 drivers/gpu/drm/v3d/v3d_mmu.c #define V3D_PTE_WRITEABLE BIT(29) BIT 31 drivers/gpu/drm/v3d/v3d_mmu.c #define V3D_PTE_VALID BIT(28) BIT 102 drivers/gpu/drm/v3d/v3d_mmu.c BIT(24)); BIT 30 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_IDENT1_WITH_MSO BIT(19) BIT 31 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_IDENT1_WITH_TSY BIT(18) BIT 32 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_IDENT1_WITH_TFU BIT(17) BIT 33 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_IDENT1_WITH_L3C BIT(16) BIT 44 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_IDENT2_WITH_MMU BIT(8) BIT 60 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_INT_MMU_WRV BIT(5) BIT 61 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_INT_MMU_PTI BIT(4) BIT 62 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_INT_MMU_CAP BIT(3) BIT 63 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_INT_MSO BIT(2) BIT 64 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_INT_TFUC BIT(1) BIT 65 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_HUB_INT_TFUF BIT(0) BIT 68 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GCA_CACHE_CTRL_FLUSH BIT(0) BIT 71 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GCA_SAFE_SHUTDOWN_EN BIT(0) BIT 84 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT BIT(0) BIT 87 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0) BIT 91 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_TFU_CS_TFURST BIT(31) BIT 96 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_TFU_CS_BUSY BIT(0) BIT 103 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_TFU_SU_CRCCHAIN BIT(4) BIT 105 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_TFU_SU_CRC BIT(3) BIT 111 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_TFU_ICFG_IOC BIT(0) BIT 128 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_TFU_COEF0_USECOEF BIT(31) BIT 141 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMUC_CONTROL_CLEAR BIT(3) BIT 142 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMUC_CONTROL_FLUSHING BIT(2) BIT 143 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMUC_CONTROL_FLUSH BIT(1) BIT 144 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMUC_CONTROL_ENABLE BIT(0) BIT 147 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_CAP_EXCEEDED BIT(27) BIT 148 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_CAP_EXCEEDED_ABORT BIT(26) BIT 149 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_CAP_EXCEEDED_INT BIT(25) BIT 150 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_CAP_EXCEEDED_EXCEPTION BIT(24) BIT 151 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_PT_INVALID BIT(20) BIT 152 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_PT_INVALID_ABORT BIT(19) BIT 153 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_PT_INVALID_INT BIT(18) BIT 154 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_PT_INVALID_EXCEPTION BIT(17) BIT 155 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_PT_INVALID_ENABLE BIT(16) BIT 156 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_WRITE_VIOLATION BIT(12) BIT 157 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_WRITE_VIOLATION_ABORT BIT(11) BIT 158 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_WRITE_VIOLATION_INT BIT(10) BIT 159 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION BIT(9) BIT 160 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_TLB_CLEARING BIT(7) BIT 161 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_TLB_STATS_CLEAR BIT(3) BIT 162 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_TLB_CLEAR BIT(2) BIT 163 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_TLB_STATS_ENABLE BIT(1) BIT 164 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_CTL_ENABLE BIT(0) BIT 172 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_ADDR_CAP_ENABLE BIT(31) BIT 177 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_SHOOT_DOWN_SHOOTING BIT(29) BIT 178 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_SHOOT_DOWN_SHOOT BIT(28) BIT 190 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MMU_ILLEGAL_ADDR_ENABLE BIT(31) BIT 225 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_IDENT2_BCG_INT BIT(28) BIT 230 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_MISCCFG_OVRTMUOUT BIT(0) BIT 233 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_L2CACTL_L2CCLR BIT(2) BIT 234 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_L2CACTL_L2CDIS BIT(1) BIT 235 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_L2CACTL_L2CENA BIT(0) BIT 248 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_L2TCACTL_TMUWCF BIT(8) BIT 249 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_L2TCACTL_L2T_NO_WM BIT(4) BIT 258 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_L2TCACTL_L2TFLS BIT(0) BIT 270 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_INT_CSDDONE BIT(7) BIT 271 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_INT_PCTR BIT(6) BIT 272 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_INT_GMPV BIT(5) BIT 273 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_INT_TRFB BIT(4) BIT 274 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_INT_SPILLUSE BIT(3) BIT 275 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_INT_OUTOMEM BIT(2) BIT 276 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_INT_FLDONE BIT(1) BIT 277 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_INT_FRDONE BIT(0) BIT 307 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_CLE_CT0QTS_ENABLE BIT(1) BIT 318 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_CLE_QCFG_ETFILT BIT(7) BIT 322 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_CLE_QCFG_ETPROC BIT(6) BIT 323 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_CLE_QCFG_ETSFLUSH BIT(1) BIT 324 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_CLE_QCFG_MCDIS BIT(0) BIT 332 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_PTB_BXCF_RWORDERDISA BIT(1) BIT 333 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_PTB_BXCF_CLIPDISA BIT(0) BIT 336 drivers/gpu/drm/v3d/v3d_regs.h #define V3D_V3_PCTR_0_EN_ENABLE BIT(31) BIT 366 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_STATUS_GMPRST BIT(31) BIT 371 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_STATUS_WR_ACTIVE BIT(5) BIT 372 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_STATUS_RD_ACTIVE BIT(4) BIT 373 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_STATUS_CFG_BUSY BIT(3) BIT 374 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_STATUS_CNTOVF BIT(2) BIT 375 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_STATUS_INVPROT BIT(1) BIT 376 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_STATUS_VIO BIT(0) BIT 379 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_CFG_LBURSTEN BIT(3) BIT 380 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_CFG_PGCRSEN BIT() BIT 381 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_CFG_STOP_REQ BIT(1) BIT 382 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_GMP_CFG_PROT_ENABLE BIT(0) BIT 396 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_CSD_STATUS_HAVE_CURRENT_DISPATCH BIT(1) BIT 397 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH BIT(0) BIT 418 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_CSD_QUEUED_CFG3_OVERLAP_WITH_PREV BIT(26) BIT 464 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_INTERPZ_IP_STALL BIT(17) BIT 465 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL BIT(16) BIT 466 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_XYNRM_IP_STALL BIT(14) BIT 467 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID BIT(13) BIT 468 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID BIT(12) BIT 469 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST BIT(11) BIT 470 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_EZTEST_ANYQVALID BIT(7) BIT 471 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_EZTEST_PASS BIT(6) BIT 472 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_EZTEST_QREADY BIT(5) BIT 473 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID BIT(4) BIT 474 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_EZTEST_QSTALL BIT(3) BIT 475 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL BIT(2) BIT 476 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL BIT(1) BIT 477 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0) BIT 480 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_L2CARE BIT(15) BIT 481 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VCMBE BIT(14) BIT 482 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VCMRE BIT(13) BIT 483 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VCDI BIT(12) BIT 484 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VCDE BIT(11) BIT 485 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VDWE BIT(10) BIT 486 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VPMEAS BIT(9) BIT 487 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VPMEFNA BIT(8) BIT 488 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VPMEWNA BIT(7) BIT 489 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VPMERNA BIT(6) BIT 490 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VPMERR BIT(5) BIT 491 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VPMEWR BIT(4) BIT 492 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VPAERRGL BIT(3) BIT 493 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VPAEBRGL BIT(2) BIT 494 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VPAERGS BIT(1) BIT 495 drivers/gpu/drm/v3d/v3d_regs.h # define V3D_ERR_VPAEABB BIT(0) BIT 210 drivers/gpu/drm/vboxvideo/vboxvideo.h #define VBOX_VBVA_CURSOR_CAPABILITY_RESERVED0 BIT(0) BIT 215 drivers/gpu/drm/vboxvideo/vboxvideo.h #define VBOX_VBVA_CURSOR_CAPABILITY_HARDWARE BIT(1) BIT 217 drivers/gpu/drm/vboxvideo/vboxvideo.h #define VBOX_VBVA_CURSOR_CAPABILITY_RESERVED2 BIT(2) BIT 219 drivers/gpu/drm/vboxvideo/vboxvideo.h #define VBOX_VBVA_CURSOR_CAPABILITY_RESERVED3 BIT(3) BIT 221 drivers/gpu/drm/vboxvideo/vboxvideo.h #define VBOX_VBVA_CURSOR_CAPABILITY_RESERVED4 BIT(4) BIT 223 drivers/gpu/drm/vboxvideo/vboxvideo.h #define VBOX_VBVA_CURSOR_CAPABILITY_RESERVED5 BIT(5) BIT 28 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_OUTPUT_ENABLE_MODE BIT(16) BIT 61 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_PIXEL_CLK_INVERT BIT(10) BIT 62 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_HSYNC_INVERT BIT(9) BIT 63 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_VSYNC_INVERT BIT(8) BIT 64 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_OUTPUT_ENABLE_INVERT BIT(7) BIT 67 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_HSYNC_NEGATE BIT(6) BIT 68 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_VSYNC_NEGATE BIT(5) BIT 69 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_OUTPUT_ENABLE_NEGATE BIT(4) BIT 72 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_HSYNC_DISABLE BIT(3) BIT 73 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_VSYNC_DISABLE BIT(2) BIT 74 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_OUTPUT_ENABLE_DISABLE BIT(1) BIT 77 drivers/gpu/drm/vc4/vc4_dpi.c # define DPI_ENABLE BIT(0) BIT 86 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_TXPKT1C_CMD_MODE_LP BIT(3) BIT 87 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2) BIT 88 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_TXPKT1C_CMD_TE_EN BIT(1) BIT 89 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_TXPKT1C_CMD_EN BIT(0) BIT 103 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_RXPKT1H_CRC_ERR BIT(31) BIT 104 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_RXPKT1H_DET_ERR BIT(30) BIT 105 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_RXPKT1H_ECC_ERR BIT(29) BIT 106 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_RXPKT1H_COR_ERR BIT(28) BIT 107 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_RXPKT1H_INCOMP_PKT BIT(25) BIT 108 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24) BIT 122 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_RXPKT1H_DET_ERR BIT(30) BIT 123 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_RXPKT1H_ECC_ERR BIT(29) BIT 124 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_RXPKT1H_COR_ERR BIT(28) BIT 125 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_RXPKT1H_INCOMP_PKT BIT(25) BIT 146 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_DISP_HACTIVE_NULL BIT(10) BIT 148 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_DISP_VBLP_CTRL BIT(9) BIT 150 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_DISP_HFP_CTRL BIT(8) BIT 152 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_DISP_HBP_CTRL BIT(7) BIT 156 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_DISP0_ST_END BIT(4) BIT 164 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_DISP0_COMMAND_MODE BIT(1) BIT 165 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_DISP0_ENABLE BIT(0) BIT 178 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_DISP1_ENABLE BIT(0) BIT 184 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_D3_ULPS BIT(30) BIT 185 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_D3_STOP BIT(29) BIT 186 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_D2_ULPS BIT(28) BIT 187 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_D2_STOP BIT(27) BIT 188 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_D1_ULPS BIT(26) BIT 189 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_D1_STOP BIT(25) BIT 190 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_D0_ULPS BIT(24) BIT 191 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_D0_STOP BIT(23) BIT 192 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_FIFO_ERR BIT(22) BIT 193 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_DIR_RTF BIT(21) BIT 194 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_RXLPDT BIT(20) BIT 195 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_RXTRIG BIT(19) BIT 196 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_D0_LPDT BIT(18) BIT 197 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_DIR_FTR BIT(17) BIT 200 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_CLOCK_ULPS BIT(16) BIT 201 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_CLOCK_HS BIT(15) BIT 202 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PHY_CLOCK_STOP BIT(14) BIT 205 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_PR_TO BIT(13) BIT 206 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_TA_TO BIT(12) BIT 207 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_LPRX_TO BIT(11) BIT 208 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_HSTX_TO BIT(10) BIT 211 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_ERR_CONT_LP1 BIT(9) BIT 212 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_ERR_CONT_LP0 BIT(8) BIT 215 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_ERR_CONTROL BIT(7) BIT 218 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_ERR_SYNC_ESC BIT(6) BIT 222 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_RXPKT2 BIT(5) BIT 227 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_RXPKT1 BIT(4) BIT 228 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_TXPKT2_DONE BIT(3) BIT 229 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_TXPKT2_END BIT(2) BIT 231 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_TXPKT1_DONE BIT(1) BIT 233 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_INT_TXPKT1_END BIT(0) BIT 252 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18) BIT 255 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHYC_CLANE_ULPS BIT(17) BIT 256 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHYC_CLANE_ENABLE BIT(16) BIT 257 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_PHYC_DLANE3_ULPS BIT(13) BIT 258 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_PHYC_DLANE3_ENABLE BIT(12) BIT 259 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10) BIT 260 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_PHYC_CLANE_ULPS BIT(9) BIT 261 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_PHYC_DLANE2_ULPS BIT(9) BIT 262 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_PHYC_CLANE_ENABLE BIT(8) BIT 263 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_PHYC_DLANE2_ENABLE BIT(8) BIT 264 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_PHYC_DLANE1_ULPS BIT(5) BIT 265 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_PHYC_DLANE1_ENABLE BIT(4) BIT 266 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_PHYC_DLANE0_FORCE_STOP BIT(2) BIT 267 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_PHYC_DLANE0_ULPS BIT(1) BIT 268 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_PHYC_DLANE0_ENABLE BIT(0) BIT 280 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26) BIT 281 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25) BIT 282 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24) BIT 299 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16) BIT 300 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15) BIT 301 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14) BIT 302 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHY_AFEC0_RESET BIT(13) BIT 303 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHY_AFEC0_PD BIT(12) BIT 304 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_PHY_AFEC0_RESET BIT(11) BIT 305 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHY_AFEC0_PD_BG BIT(11) BIT 306 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_PHY_AFEC0_PD BIT(10) BIT 307 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10) BIT 308 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_PHY_AFEC0_PD_BG BIT(9) BIT 309 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9) BIT 310 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8) BIT 311 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8) BIT 337 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13) BIT 338 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_CTRL_LPDT_EOT_DISABLE BIT(12) BIT 339 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_CTRL_HSDT_EOT_DISABLE BIT(11) BIT 340 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_CTRL_SOFT_RESET_CFG BIT(10) BIT 341 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_CTRL_CAL_BYTE BIT(9) BIT 342 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_CTRL_INV_BYTE BIT(8) BIT 343 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI_CTRL_CLR_LDF BIT(7) BIT 344 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_CTRL_CLR_PBCF BIT(6) BIT 345 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_CTRL_CLR_RXF BIT(6) BIT 346 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_CTRL_CLR_CPBCF BIT(5) BIT 347 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_CTRL_CLR_PDF BIT(5) BIT 348 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_CTRL_CLR_PDF BIT(4) BIT 349 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_CTRL_CLR_CDF BIT(4) BIT 350 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_CTRL_CLR_CDF BIT(3) BIT 351 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_CTRL_CTRL2 BIT(2) BIT 352 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2) BIT 353 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_CTRL_CTRL1 BIT(1) BIT 354 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1) BIT 355 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI0_CTRL_CTRL0 BIT(0) BIT 356 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_CTRL_EN BIT(0) BIT 378 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_D3_ULPS BIT(31) BIT 379 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_D3_STOP BIT(30) BIT 380 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_D2_ULPS BIT(29) BIT 381 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_D2_STOP BIT(28) BIT 382 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_D1_ULPS BIT(27) BIT 383 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_D1_STOP BIT(26) BIT 384 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_D0_ULPS BIT(25) BIT 385 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_D0_STOP BIT(24) BIT 386 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_FIFO_ERR BIT(23) BIT 387 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_RXLPDT BIT(22) BIT 388 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_RXTRIG BIT(21) BIT 389 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_D0_LPDT BIT(20) BIT 391 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_DIR BIT(19) BIT 392 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_CLOCK_ULPS BIT(18) BIT 393 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_CLOCK_HS BIT(17) BIT 394 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PHY_CLOCK_STOP BIT(16) BIT 395 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_PR_TO BIT(15) BIT 396 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_TA_TO BIT(14) BIT 397 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_LPRX_TO BIT(13) BIT 398 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_HSTX_TO BIT(12) BIT 399 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_ERR_CONT_LP1 BIT(11) BIT 400 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_ERR_CONT_LP0 BIT(10) BIT 401 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_ERR_CONTROL BIT(9) BIT 402 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_ERR_SYNC_ESC BIT(8) BIT 403 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_RXPKT2 BIT(7) BIT 404 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_RXPKT1 BIT(6) BIT 405 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_TXPKT2_BUSY BIT(5) BIT 406 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_TXPKT2_DONE BIT(4) BIT 407 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_TXPKT2_END BIT(3) BIT 408 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_TXPKT1_BUSY BIT(2) BIT 409 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_TXPKT1_DONE BIT(1) BIT 410 drivers/gpu/drm/vc4/vc4_dsi.c # define DSI1_STAT_TXPKT1_END BIT(0) BIT 323 drivers/gpu/drm/vc4/vc4_hdmi.c HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); BIT 326 drivers/gpu/drm/vc4/vc4_hdmi.c BIT(packet_id)), 100); BIT 370 drivers/gpu/drm/vc4/vc4_hdmi.c HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); BIT 372 drivers/gpu/drm/vc4/vc4_hdmi.c BIT(packet_id)), 100); BIT 896 drivers/gpu/drm/vc4/vc4_hdmi.c if (channel_mask & BIT(i)) BIT 101 drivers/gpu/drm/vc4/vc4_irq.c vc4->bin_alloc_overflow = BIT(bin_bo_slot); BIT 100 drivers/gpu/drm/vc4/vc4_kms.c r = in & BIT_ULL(63) ? BIT(9) : 0; BIT 145 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_FULL_RES_EOF BIT(3) BIT 146 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2) BIT 147 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1) BIT 148 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0) BIT 155 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_FULL_RES_EOF BIT(3) BIT 156 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2) BIT 157 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1) BIT 158 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0) BIT 166 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_TILE_BUFFER_EOF BIT(3) BIT 167 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK BIT(2) BIT 168 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS BIT(1) BIT 169 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR BIT(0) BIT 178 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR BIT(15) BIT 179 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR BIT(14) BIT 180 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR BIT(13) BIT 181 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_STORE_TILE_BUFFER_DISABLE_SWAP BIT(12) BIT 219 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_SHADER_FLAG_SHADED_CLIP_COORDS BIT(3) BIT 220 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_SHADER_FLAG_ENABLE_CLIPPING BIT(2) BIT 221 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_SHADER_FLAG_VS_POINT_SIZE BIT(1) BIT 222 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_SHADER_FLAG_FS_SINGLE_THREAD BIT(0) BIT 225 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_CONFIG_BITS_EARLY_Z_UPDATE BIT(1) BIT 226 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_CONFIG_BITS_EARLY_Z BIT(0) BIT 230 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_CONFIG_BITS_Z_UPDATE BIT(7) BIT 233 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE BIT(3) BIT 240 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT BIT(0) BIT 248 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_CONFIG_BITS_AA_POINTS_AND_LINES BIT(4) BIT 249 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET BIT(3) BIT 250 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_CONFIG_BITS_CW_PRIMITIVES BIT(2) BIT 251 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_CONFIG_BITS_ENABLE_PRIM_BACK BIT(1) BIT 252 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT BIT(0) BIT 256 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_BIN_CONFIG_DB_NON_MS BIT(7) BIT 272 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_BIN_CONFIG_AUTO_INIT_TSDA BIT(2) BIT 273 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_BIN_CONFIG_TILE_BUFFER_64BIT BIT(1) BIT 274 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_BIN_CONFIG_MS_MODE_4X BIT(0) BIT 278 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_RENDER_CONFIG_DB_NON_MS BIT(12) BIT 279 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE BIT(11) BIT 280 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G BIT(10) BIT 281 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_RENDER_CONFIG_COVERAGE_MODE BIT(9) BIT 282 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_RENDER_CONFIG_ENABLE_VG_MASK BIT(8) BIT 298 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT BIT(1) BIT 299 drivers/gpu/drm/vc4/vc4_packet.h #define VC4_RENDER_CONFIG_MS_MODE_4X BIT(0) BIT 48 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_L2CACTL_L2CCLR BIT(2) BIT 49 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_L2CACTL_L2CDIS BIT(1) BIT 50 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_L2CACTL_L2CENA BIT(0) BIT 65 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_INT_SPILLUSE BIT(3) BIT 66 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_INT_OUTOMEM BIT(2) BIT 67 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_INT_FLDONE BIT(1) BIT 68 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_INT_FRDONE BIT(0) BIT 73 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_CTRSTA BIT(15) BIT 74 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_CTSEMA BIT(12) BIT 75 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_CTRTSD BIT(8) BIT 76 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_CTRUN BIT(5) BIT 77 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_CTSUBS BIT(4) BIT 78 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_CTERR BIT(3) BIT 79 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_CTMODE BIT(0) BIT 98 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_BMOOM BIT(8) BIT 99 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_RMBUSY BIT(3) BIT 100 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_RMACTIVE BIT(2) BIT 101 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_BMBUSY BIT(1) BIT 102 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_BMACTIVE BIT(0) BIT 122 drivers/gpu/drm/vc4/vc4_regs.h # define V3D_PCTRE_EN BIT(31) BIT 143 drivers/gpu/drm/vc4/vc4_regs.h # define PV_CONTROL_CLR_AT_START BIT(14) BIT 144 drivers/gpu/drm/vc4/vc4_regs.h # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13) BIT 145 drivers/gpu/drm/vc4/vc4_regs.h # define PV_CONTROL_WAIT_HSTART BIT(12) BIT 153 drivers/gpu/drm/vc4/vc4_regs.h # define PV_CONTROL_FIFO_CLR BIT(1) BIT 154 drivers/gpu/drm/vc4/vc4_regs.h # define PV_CONTROL_EN BIT(0) BIT 159 drivers/gpu/drm/vc4/vc4_regs.h # define PV_VCONTROL_ODD_FIRST BIT(5) BIT 160 drivers/gpu/drm/vc4/vc4_regs.h # define PV_VCONTROL_INTERLACE BIT(4) BIT 161 drivers/gpu/drm/vc4/vc4_regs.h # define PV_VCONTROL_DSI BIT(3) BIT 162 drivers/gpu/drm/vc4/vc4_regs.h # define PV_VCONTROL_COMMAND BIT(2) BIT 163 drivers/gpu/drm/vc4/vc4_regs.h # define PV_VCONTROL_CONTINUOUS BIT(1) BIT 164 drivers/gpu/drm/vc4/vc4_regs.h # define PV_VCONTROL_VIDEN BIT(0) BIT 197 drivers/gpu/drm/vc4/vc4_regs.h # define PV_INT_VID_IDLE BIT(9) BIT 198 drivers/gpu/drm/vc4/vc4_regs.h # define PV_INT_VFP_END BIT(8) BIT 199 drivers/gpu/drm/vc4/vc4_regs.h # define PV_INT_VFP_START BIT(7) BIT 200 drivers/gpu/drm/vc4/vc4_regs.h # define PV_INT_VACT_START BIT(6) BIT 201 drivers/gpu/drm/vc4/vc4_regs.h # define PV_INT_VBP_START BIT(5) BIT 202 drivers/gpu/drm/vc4/vc4_regs.h # define PV_INT_VSYNC_START BIT(4) BIT 203 drivers/gpu/drm/vc4/vc4_regs.h # define PV_INT_HFP_START BIT(3) BIT 204 drivers/gpu/drm/vc4/vc4_regs.h # define PV_INT_HACT_START BIT(2) BIT 205 drivers/gpu/drm/vc4/vc4_regs.h # define PV_INT_HBP_START BIT(1) BIT 206 drivers/gpu/drm/vc4/vc4_regs.h # define PV_INT_HSYNC_START BIT(0) BIT 216 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRL_ENABLE BIT(31) BIT 224 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x)) BIT 228 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2)) BIT 230 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2)) BIT 232 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) BIT 233 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRL_SLVWREIRQ BIT(5) BIT 234 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRL_DMAEIRQ BIT(4) BIT 238 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x)) BIT 240 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRL_SCLEIRQ BIT(0) BIT 250 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8)) BIT 252 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8)) BIT 256 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8)) BIT 260 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8)) BIT 264 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8)) BIT 266 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8)) BIT 272 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_DMA_ERROR BIT(7) BIT 274 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_IRQSLVRD BIT(6) BIT 276 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_IRQSLVWR BIT(5) BIT 280 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_IRQDMA BIT(4) BIT 284 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x)) BIT 286 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTAT_IRQSCL BIT(0) BIT 309 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRLX_ENABLE BIT(31) BIT 310 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRLX_RESET BIT(30) BIT 314 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRLX_ONESHOT BIT(29) BIT 318 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRLX_ONECTX BIT(28) BIT 320 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRLX_FIFO32 BIT(27) BIT 324 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPCTRLX_FIFOREG BIT(26) BIT 332 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPBKGND_AUTOHS BIT(31) BIT 333 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPBKGND_INTERLACE BIT(30) BIT 334 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPBKGND_GAMMA BIT(29) BIT 341 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPBKGND_FILL BIT(24) BIT 350 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTATX_FULL BIT(29) BIT 351 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSTATX_EMPTY BIT(28) BIT 392 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_GAMADDR_AUTOINC BIT(31) BIT 396 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_GAMADDR_SRAMENB BIT(30) BIT 400 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_OLEDOFFS_YUVCLAMP BIT(31) BIT 449 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31) BIT 450 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30) BIT 452 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSLAVE_EOL BIT(26) BIT 454 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSLAVE_EMPTY BIT(25) BIT 456 drivers/gpu/drm/vc4/vc4_regs.h # define SCALER_DISPSLAVE_VALID BIT(24) BIT 467 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1) BIT 468 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_SW_RESET_HDMI BIT(0) BIT 473 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0) BIT 481 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27) BIT 482 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26) BIT 490 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29) BIT 491 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24) BIT 492 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19) BIT 493 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18) BIT 497 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9) BIT 499 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8) BIT 504 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16) BIT 512 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26) BIT 514 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CRP_CFG_DISABLE BIT(25) BIT 518 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24) BIT 532 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_HORZA_VPOS BIT(14) BIT 533 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_HORZA_HPOS BIT(13) BIT 550 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14) BIT 551 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13) BIT 552 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7) BIT 553 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6) BIT 554 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5) BIT 555 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4) BIT 556 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3) BIT 557 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2) BIT 558 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1) BIT 559 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0) BIT 563 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15) BIT 564 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5) BIT 565 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3) BIT 566 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1) BIT 567 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0) BIT 592 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_TX_EOM BIT(31) BIT 597 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30) BIT 598 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_RX_EOM BIT(29) BIT 599 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28) BIT 610 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_RX_CONTINUE BIT(23) BIT 611 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_TX_CONTINUE BIT(22) BIT 613 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21) BIT 617 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20) BIT 664 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_TX_SW_RESET BIT(27) BIT 665 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_RX_SW_RESET BIT(26) BIT 666 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25) BIT 667 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24) BIT 668 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CEC_RX_CEC_INT BIT(23) BIT 691 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25) BIT 697 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CPU_CEC BIT(6) BIT 698 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HDMI_CPU_HOTPLUG BIT(0) BIT 710 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_CECRXD BIT(9) BIT 712 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_CECOVR BIT(8) BIT 715 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_M_SW_RST BIT(2) BIT 716 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_M_ENABLE BIT(0) BIT 722 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_DLATE BIT(15) BIT 723 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_BUSY BIT(14) BIT 724 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_CHALIGN BIT(13) BIT 725 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_WHOLSMP BIT(12) BIT 726 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_FULL BIT(11) BIT 727 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_EMPTY BIT(10) BIT 728 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_FLUSH BIT(9) BIT 732 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_PAREN BIT(8) BIT 735 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_ENABLE BIT(3) BIT 737 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_ERRORE BIT(2) BIT 739 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_ERRORF BIT(1) BIT 741 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_MAI_CTL_RESET BIT(0) BIT 771 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_VID_CTL_ENABLE BIT(31) BIT 772 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30) BIT 773 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29) BIT 774 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28) BIT 775 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27) BIT 786 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_CSC_CTL_PADMSB BIT(4) BIT 792 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_CSC_CTL_RGB2YCC BIT(1) BIT 793 drivers/gpu/drm/vc4/vc4_regs.h # define VC4_HD_CSC_CTL_ENABLE BIT(0) BIT 849 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_CTL0_END BIT(31) BIT 850 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_CTL0_VALID BIT(30) BIT 862 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_CTL0_ALPHA_MASK BIT(19) BIT 863 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_CTL0_HFLIP BIT(16) BIT 864 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_CTL0_VFLIP BIT(15) BIT 899 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_CTL0_UNITY BIT(4) BIT 925 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_POS2_ALPHA_PREMULT BIT(29) BIT 926 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_POS2_ALPHA_MIX BIT(28) BIT 983 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_TPZ0_VERT_RECALC BIT(31) BIT 994 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_PPF_NOINTERP BIT(31) BIT 998 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_PPF_AGC BIT(30) BIT 1006 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_PPF_KERNEL_UNCACHED BIT(31) BIT 1025 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_PITCH0_TILE_LINE_DIR BIT(15) BIT 1026 drivers/gpu/drm/vc4/vc4_regs.h #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14) BIT 70 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_POWERDOWN BIT(21) BIT 75 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_ALPHA_ENABLE BIT(20) BIT 84 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_VSTART_AT_EOF BIT(15) BIT 89 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_ABORT BIT(14) BIT 91 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_DITHER BIT(13) BIT 96 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_ALPHA_INVERT BIT(12) BIT 118 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_LINEAR_UTILE BIT(7) BIT 121 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_TRANSPOSE BIT(6) BIT 124 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_TFORMAT BIT(5) BIT 127 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_TEST_MODE BIT(4) BIT 130 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_FIELD BIT(3) BIT 133 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_EI BIT(2) BIT 136 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_BUSY BIT(1) BIT 139 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_GO BIT(0) BIT 183 drivers/gpu/drm/vc4/vc4_v3d.c vc4->bin_alloc_used |= BIT(slot); BIT 394 drivers/gpu/drm/vc4/vc4_validate.c exec->bin_slots |= BIT(bin_slot); BIT 33 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_WSE_WSS_ENABLE BIT(7) BIT 47 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_PBPR_FIL BIT(18) BIT 58 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_CHRBW1 BIT(11) BIT 59 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_CHRBW0 BIT(10) BIT 60 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_SYNCDIS BIT(9) BIT 61 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_BURDIS BIT(8) BIT 62 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_CHRDIS BIT(7) BIT 63 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_PDEN BIT(6) BIT 64 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_YCDELAY BIT(4) BIT 65 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_RAMPEN BIT(2) BIT 66 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_YCDIS BIT(2) BIT 80 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG_VEC_RESYNC_OFF BIT(18) BIT 81 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG_RGB219 BIT(17) BIT 82 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG_CBAR_EN BIT(16) BIT 83 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG_TC_OBB BIT(15) BIT 92 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG1_DIS_CHR BIT(9) BIT 93 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG1_DIS_LUMA BIT(8) BIT 94 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG1_YCBCR_IN BIT(6) BIT 96 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5) BIT 97 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG1_DITHER_EN BIT(4) BIT 98 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG1_CYDELAY BIT(3) BIT 99 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG1_LUMADIS BIT(2) BIT 100 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG1_COMPDIS BIT(1) BIT 101 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG1_CUSTOM_FREQ BIT(0) BIT 104 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG2_PROG_SCAN BIT(15) BIT 107 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG2_PBPR_EN BIT(10) BIT 108 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG2_UV_DIG_DIS BIT(6) BIT 109 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG2_RGB_DIG_DIS BIT(5) BIT 124 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1) BIT 132 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CFG_SG_EN BIT(4) BIT 133 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CFG_VEC_EN BIT(3) BIT 134 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CFG_MB_EN BIT(2) BIT 135 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CFG_ENABLE BIT(1) BIT 136 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CFG_TB_EN BIT(0) BIT 148 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_DAC_MISC_VID_ACT BIT(8) BIT 149 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_DAC_MISC_VCD_PWRDN BIT(6) BIT 150 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_DAC_MISC_BIAS_PWRDN BIT(5) BIT 151 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_DAC_MISC_DAC_PWRDN BIT(2) BIT 152 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_DAC_MISC_LDO_PWRDN BIT(1) BIT 153 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_DAC_MISC_DAC_RST_N BIT(0) BIT 38 drivers/gpu/drm/vmwgfx/vmwgfx_validation.h #define VMW_RES_DIRTY_SET BIT(0) BIT 39 drivers/gpu/drm/vmwgfx/vmwgfx_validation.h #define VMW_RES_DIRTY_CLEAR BIT(1) BIT 26 drivers/gpu/drm/zte/zx_common_regs.h #define CSC_WORK_ENABLE BIT(0) BIT 11 drivers/gpu/drm/zte/zx_hdmi_regs.h #define FUNC_HDMI_EN BIT(0) BIT 13 drivers/gpu/drm/zte/zx_hdmi_regs.h #define CLKPWD_PDIDCK BIT(2) BIT 15 drivers/gpu/drm/zte/zx_hdmi_regs.h #define P2T_DC_PKT_EN BIT(7) BIT 17 drivers/gpu/drm/zte/zx_hdmi_regs.h #define L1_INTR_STAT_INTR1 BIT(0) BIT 20 drivers/gpu/drm/zte/zx_hdmi_regs.h #define INTR1_MONITOR_DETECT (BIT(5) | BIT(6)) BIT 34 drivers/gpu/drm/zte/zx_hdmi_regs.h #define TEST_TXCTRL_HDMI_MODE BIT(1) BIT 37 drivers/gpu/drm/zte/zx_hdmi_regs.h #define TPI_HPD_CONNECTION (BIT(1) | BIT(2)) BIT 47 drivers/gpu/drm/zte/zx_hdmi_regs.h #define TPI_INFO_TRANS_EN BIT(7) BIT 48 drivers/gpu/drm/zte/zx_hdmi_regs.h #define TPI_INFO_TRANS_RPT BIT(6) BIT 50 drivers/gpu/drm/zte/zx_hdmi_regs.h #define HW_DDC_MASTER BIT(7) BIT 55 drivers/gpu/drm/zte/zx_hdmi_regs.h #define AUD_IN_EN BIT(0) BIT 57 drivers/gpu/drm/zte/zx_hdmi_regs.h #define SPDIF_EN BIT(1) BIT 64 drivers/gpu/drm/zte/zx_hdmi_regs.h #define TPI_AUD_MUTE BIT(4) BIT 12 drivers/gpu/drm/zte/zx_plane_regs.h #define GL_UPDATE BIT(5) BIT 25 drivers/gpu/drm/zte/zx_plane_regs.h #define GL_SCALER_BYPASS_MODE BIT(0) BIT 47 drivers/gpu/drm/zte/zx_plane_regs.h #define VL_UPDATE BIT(3) BIT 49 drivers/gpu/drm/zte/zx_plane_regs.h #define VL_YUV420_PLANAR BIT(5) BIT 62 drivers/gpu/drm/zte/zx_plane_regs.h #define VL_SCALER_BYPASS_MODE BIT(0) BIT 118 drivers/gpu/drm/zte/zx_plane_regs.h #define HBSC_CTRL_EN BIT(2) BIT 286 drivers/gpu/drm/zte/zx_tvenc.c encoder->possible_crtcs = BIT(1); BIT 11 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_CMD_TRANS BIT(6) BIT 12 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_CMD_COMBO BIT(5) BIT 13 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_CMD_RW BIT(4) BIT 18 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_RX_FIFO_CLEAR BIT(7) BIT 21 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_DEVICE_DISCONNECTED BIT(7) BIT 22 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_DEVICE_CONNECTED BIT(6) BIT 23 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_CLEAR_IRQ BIT(4) BIT 24 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_TRANS_DONE BIT(0) BIT 30 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_DETECT_SEL_HAS_DEVICE BIT(1) BIT 31 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_DETECT_SEL_NO_DEVICE BIT(0) BIT 201 drivers/gpu/drm/zte/zx_vou.c .clocks_en_bits = BIT(24) | BIT(18) | BIT(6), BIT 202 drivers/gpu/drm/zte/zx_vou.c .clocks_sel_bits = BIT(13) | BIT(2), BIT 206 drivers/gpu/drm/zte/zx_vou.c .clocks_en_bits = BIT(15), BIT 207 drivers/gpu/drm/zte/zx_vou.c .clocks_sel_bits = BIT(11) | BIT(0), BIT 211 drivers/gpu/drm/zte/zx_vou.c .clocks_en_bits = BIT(1), BIT 212 drivers/gpu/drm/zte/zx_vou.c .clocks_sel_bits = BIT(10), BIT 23 drivers/gpu/drm/zte/zx_vou.h VOU_HDMI_AUD_SPDIF = BIT(0), BIT 24 drivers/gpu/drm/zte/zx_vou.h VOU_HDMI_AUD_I2S = BIT(1), BIT 25 drivers/gpu/drm/zte/zx_vou.h VOU_HDMI_AUD_DSD = BIT(2), BIT 26 drivers/gpu/drm/zte/zx_vou.h VOU_HDMI_AUD_HBR = BIT(3), BIT 27 drivers/gpu/drm/zte/zx_vou.h VOU_HDMI_AUD_PARALLEL = BIT(4), BIT 38 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_INT_AUX_UPT BIT(14) BIT 39 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_INT_MAIN_UPT BIT(13) BIT 40 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_INT_GL1_LBW BIT(10) BIT 41 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_INT_GL0_LBW BIT(9) BIT 42 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_INT_VL2_LBW BIT(8) BIT 43 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_INT_VL1_LBW BIT(7) BIT 44 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_INT_VL0_LBW BIT(6) BIT 45 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_INT_BUS_ERR BIT(3) BIT 46 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_INT_CFG_ERR BIT(2) BIT 54 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_CTRL0_VL0_EN BIT(13) BIT 55 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_CTRL0_VL0_SEL BIT(12) BIT 56 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_CTRL0_VL1_EN BIT(11) BIT 57 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_CTRL0_VL1_SEL BIT(10) BIT 58 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_CTRL0_VL2_EN BIT(9) BIT 59 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_CTRL0_VL2_SEL BIT(8) BIT 60 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_CTRL0_GL0_EN BIT(7) BIT 61 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_CTRL0_GL0_SEL BIT(6) BIT 62 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_CTRL0_GL1_EN BIT(5) BIT 63 drivers/gpu/drm/zte/zx_vou_regs.h #define OSD_CTRL0_GL1_SEL BIT(4) BIT 65 drivers/gpu/drm/zte/zx_vou_regs.h #define RST_PER_FRAME BIT(19) BIT 71 drivers/gpu/drm/zte/zx_vou_regs.h #define CHN_ENABLE BIT(0) BIT 79 drivers/gpu/drm/zte/zx_vou_regs.h #define CHN_INTERLACE_EN BIT(2) BIT 83 drivers/gpu/drm/zte/zx_vou_regs.h #define DITHER_BYSPASS BIT(31) BIT 87 drivers/gpu/drm/zte/zx_vou_regs.h #define AUX_TC_EN BIT(1) BIT 88 drivers/gpu/drm/zte/zx_vou_regs.h #define MAIN_TC_EN BIT(0) BIT 115 drivers/gpu/drm/zte/zx_vou_regs.h #define TIMING_INT_AUX_FRAME BIT(3) BIT 116 drivers/gpu/drm/zte/zx_vou_regs.h #define TIMING_INT_MAIN_FRAME BIT(1) BIT 128 drivers/gpu/drm/zte/zx_vou_regs.h #define AUX_PI_EN BIT(19) BIT 129 drivers/gpu/drm/zte/zx_vou_regs.h #define MAIN_PI_EN BIT(18) BIT 130 drivers/gpu/drm/zte/zx_vou_regs.h #define AUX_INTERLACE_SEL BIT(1) BIT 131 drivers/gpu/drm/zte/zx_vou_regs.h #define MAIN_INTERLACE_SEL BIT(0) BIT 153 drivers/gpu/drm/zte/zx_vou_regs.h #define DTRC_DECOMPRESS_BYPASS BIT(17) BIT 155 drivers/gpu/drm/zte/zx_vou_regs.h #define TILE2RASTESCAN_BYPASS_MODE BIT(30) BIT 187 drivers/gpu/drm/zte/zx_vou_regs.h #define VOU_CLK_VL2_SEL BIT(8) BIT 188 drivers/gpu/drm/zte/zx_vou_regs.h #define VOU_CLK_VL1_SEL BIT(7) BIT 189 drivers/gpu/drm/zte/zx_vou_regs.h #define VOU_CLK_VL0_SEL BIT(6) BIT 190 drivers/gpu/drm/zte/zx_vou_regs.h #define VOU_CLK_GL1_SEL BIT(5) BIT 191 drivers/gpu/drm/zte/zx_vou_regs.h #define VOU_CLK_GL0_SEL BIT(4) BIT 193 drivers/gpu/drm/zte/zx_vou_regs.h #define DIV_PARA_UPDATE BIT(31) BIT 178 drivers/gpu/host1x/hw/cdma_hw.c cmdproc_stop |= BIT(ch->id); BIT 180 drivers/gpu/host1x/hw/cdma_hw.c cmdproc_stop &= ~BIT(ch->id); BIT 190 drivers/gpu/host1x/hw/cdma_hw.c host1x_sync_writel(host, BIT(ch->id), HOST1X_SYNC_CH_TEARDOWN); BIT 220 drivers/gpu/host1x/hw/channel_hw.c val |= BIT(ch->id % 32); BIT 122 drivers/gpu/host1x/hw/host1x01_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | count; BIT 127 drivers/gpu/host1x/hw/host1x01_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; BIT 121 drivers/gpu/host1x/hw/host1x02_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | count; BIT 126 drivers/gpu/host1x/hw/host1x02_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; BIT 121 drivers/gpu/host1x/hw/host1x04_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | count; BIT 126 drivers/gpu/host1x/hw/host1x04_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; BIT 121 drivers/gpu/host1x/hw/host1x05_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | count; BIT 126 drivers/gpu/host1x/hw/host1x05_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; BIT 122 drivers/gpu/host1x/hw/host1x06_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | count; BIT 127 drivers/gpu/host1x/hw/host1x06_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; BIT 122 drivers/gpu/host1x/hw/host1x07_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | count; BIT 127 drivers/gpu/host1x/hw/host1x07_hardware.h return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; BIT 7 drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h #define HOST1X_HV_SYNCPT_PROT_EN_CH_EN BIT(1) BIT 12 drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h #define HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE BIT(31) BIT 15 drivers/gpu/host1x/hw/hw_host1x06_vm.h #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0) BIT 16 drivers/gpu/host1x/hw/hw_host1x06_vm.h #define HOST1X_CHANNEL_DMACTRL_DMAGETRST BIT(1) BIT 17 drivers/gpu/host1x/hw/hw_host1x06_vm.h #define HOST1X_CHANNEL_DMACTRL_DMAINITGET BIT(2) BIT 19 drivers/gpu/host1x/hw/hw_host1x06_vm.h #define HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY BIT(13) BIT 7 drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h #define HOST1X_HV_SYNCPT_PROT_EN_CH_EN BIT(1) BIT 12 drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h #define HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE BIT(31) BIT 15 drivers/gpu/host1x/hw/hw_host1x07_vm.h #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0) BIT 16 drivers/gpu/host1x/hw/hw_host1x07_vm.h #define HOST1X_CHANNEL_DMACTRL_DMAGETRST BIT(1) BIT 17 drivers/gpu/host1x/hw/hw_host1x07_vm.h #define HOST1X_CHANNEL_DMACTRL_DMAINITGET BIT(2) BIT 19 drivers/gpu/host1x/hw/hw_host1x07_vm.h #define HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY BIT(13) BIT 25 drivers/gpu/host1x/hw/intr_hw.c host1x_sync_writel(host, BIT(id % 32), BIT 27 drivers/gpu/host1x/hw/intr_hw.c host1x_sync_writel(host, BIT(id % 32), BIT 116 drivers/gpu/host1x/hw/intr_hw.c host1x_sync_writel(host, BIT(id % 32), BIT 123 drivers/gpu/host1x/hw/intr_hw.c host1x_sync_writel(host, BIT(id % 32), BIT 125 drivers/gpu/host1x/hw/intr_hw.c host1x_sync_writel(host, BIT(id % 32), BIT 85 drivers/gpu/host1x/hw/syncpt_hw.c host1x_sync_writel(host, BIT(sp->id % 32), BIT 340 drivers/gpu/host1x/mipi.c if (device->pads & BIT(i)) { BIT 637 drivers/gpu/ipu-v3/ipu-cpmem.c val |= BIT(ch->num); BIT 264 drivers/hid/hid-appleir.c input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_REP); BIT 50 drivers/hid/hid-asus.c #define SUPPORT_KBD_BACKLIGHT BIT(0) BIT 69 drivers/hid/hid-asus.c #define QUIRK_FIX_NOTEBOOK_REPORT BIT(0) BIT 70 drivers/hid/hid-asus.c #define QUIRK_NO_INIT_REPORTS BIT(1) BIT 71 drivers/hid/hid-asus.c #define QUIRK_SKIP_INPUT_MAPPING BIT(2) BIT 72 drivers/hid/hid-asus.c #define QUIRK_IS_MULTITOUCH BIT(3) BIT 73 drivers/hid/hid-asus.c #define QUIRK_NO_CONSUMER_USAGES BIT(4) BIT 74 drivers/hid/hid-asus.c #define QUIRK_USE_KBD_BACKLIGHT BIT(5) BIT 75 drivers/hid/hid-asus.c #define QUIRK_T100_KEYBOARD BIT(6) BIT 76 drivers/hid/hid-asus.c #define QUIRK_T100CHI BIT(7) BIT 77 drivers/hid/hid-asus.c #define QUIRK_G752_KEYBOARD BIT(8) BIT 78 drivers/hid/hid-asus.c #define QUIRK_T101HA_DOCK BIT(9) BIT 79 drivers/hid/hid-asus.c #define QUIRK_T90CHI BIT(10) BIT 236 drivers/hid/hid-asus.c bool down = !!(data[1] & BIT(i+3)); BIT 271 drivers/hid/hid-bigbenff.c work = (bigben->led_state & BIT(n)); BIT 272 drivers/hid/hid-bigbenff.c bigben->led_state &= ~BIT(n); BIT 274 drivers/hid/hid-bigbenff.c work = !(bigben->led_state & BIT(n)); BIT 275 drivers/hid/hid-bigbenff.c bigben->led_state |= BIT(n); BIT 301 drivers/hid/hid-bigbenff.c return (bigben->led_state & BIT(n)) ? LED_ON : LED_OFF; BIT 389 drivers/hid/hid-bigbenff.c bigben->led_state = BIT(0); BIT 87 drivers/hid/hid-cmedia.c input_dev->evbit[0] = BIT(EV_SW); BIT 1107 drivers/hid/hid-cp2112.c virqs &= ~BIT(virq); BIT 1120 drivers/hid/hid-cp2112.c if (gpio_mask & BIT(virq)) { BIT 1127 drivers/hid/hid-cp2112.c !(dev->gpio_prev_state & BIT(virq))) BIT 1136 drivers/hid/hid-cp2112.c (dev->gpio_prev_state & BIT(virq))) BIT 198 drivers/hid/hid-creative-sb0540.c input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_REP); BIT 38 drivers/hid/hid-elan.c #define ELAN_HAS_LED BIT(0) BIT 274 drivers/hid/hid-elan.c if (data[2] & BIT(i + 3)) BIT 301 drivers/hid/hid-elan.c if (prev_report[2] & BIT(i + 3)) { BIT 346 drivers/hid/hid-elan.c if (data[1] & BIT(i + 3)) { BIT 49 drivers/hid/hid-google-hammer.c return !!(switches & BIT(EC_MKBP_BASE_ATTACHED)); BIT 189 drivers/hid/hid-gt683r.c leds |= BIT(i); BIT 37 drivers/hid/hid-lg4ff.c #define LG4FF_MODE_NATIVE BIT(LG4FF_MODE_NATIVE_IDX) BIT 38 drivers/hid/hid-lg4ff.c #define LG4FF_MODE_DFEX BIT(LG4FF_MODE_DFEX_IDX) BIT 39 drivers/hid/hid-lg4ff.c #define LG4FF_MODE_DFP BIT(LG4FF_MODE_DFP_IDX) BIT 40 drivers/hid/hid-lg4ff.c #define LG4FF_MODE_G25 BIT(LG4FF_MODE_G25_IDX) BIT 41 drivers/hid/hid-lg4ff.c #define LG4FF_MODE_DFGT BIT(LG4FF_MODE_DFGT_IDX) BIT 42 drivers/hid/hid-lg4ff.c #define LG4FF_MODE_G27 BIT(LG4FF_MODE_G27_IDX) BIT 43 drivers/hid/hid-lg4ff.c #define LG4FF_MODE_G29 BIT(LG4FF_MODE_G29_IDX) BIT 824 drivers/hid/hid-lg4ff.c if (entry->wdata.alternate_modes & BIT(i)) { BIT 887 drivers/hid/hid-lg4ff.c if (entry->wdata.alternate_modes & BIT(i)) { BIT 1195 drivers/hid/hid-lg4ff.c current_mode = BIT(i); BIT 83 drivers/hid/hid-logitech-dj.c #define STD_KEYBOARD BIT(1) BIT 84 drivers/hid/hid-logitech-dj.c #define STD_MOUSE BIT(2) BIT 85 drivers/hid/hid-logitech-dj.c #define MULTIMEDIA BIT(3) BIT 86 drivers/hid/hid-logitech-dj.c #define POWER_KEYS BIT(4) BIT 87 drivers/hid/hid-logitech-dj.c #define MEDIA_CENTER BIT(8) BIT 88 drivers/hid/hid-logitech-dj.c #define KBD_LEDS BIT(14) BIT 100 drivers/hid/hid-logitech-dj.c #define HIDPP_LINK_STATUS_MASK BIT(6) BIT 101 drivers/hid/hid-logitech-dj.c #define HIDPP_MANUFACTURER_MASK BIT(7) BIT 1072 drivers/hid/hid-logitech-dj.c if (dj_dev && (dj_dev->reports_supported & BIT(report))) { BIT 56 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_CLASS_WTP BIT(0) BIT 57 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_CLASS_M560 BIT(1) BIT 58 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_CLASS_K400 BIT(2) BIT 59 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_CLASS_G920 BIT(3) BIT 60 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_CLASS_K750 BIT(4) BIT 64 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_WTP_PHYSICAL_BUTTONS BIT(22) BIT 65 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_NO_HIDINPUT BIT(23) BIT 66 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_FORCE_OUTPUT_REPORTS BIT(24) BIT 67 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_UNIFYING BIT(25) BIT 68 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_HI_RES_SCROLL_1P0 BIT(26) BIT 69 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_HI_RES_SCROLL_X2120 BIT(27) BIT 70 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_HI_RES_SCROLL_X2121 BIT(28) BIT 71 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_HIDPP_WHEELS BIT(29) BIT 72 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_HIDPP_EXTRA_MOUSE_BTNS BIT(30) BIT 73 drivers/hid/hid-logitech-hidpp.c #define HIDPP_QUIRK_HIDPP_CONSUMER_VENDOR_KEYS BIT(31) BIT 86 drivers/hid/hid-logitech-hidpp.c #define HIDPP_CAPABILITY_HIDPP10_BATTERY BIT(0) BIT 87 drivers/hid/hid-logitech-hidpp.c #define HIDPP_CAPABILITY_HIDPP20_BATTERY BIT(1) BIT 88 drivers/hid/hid-logitech-hidpp.c #define HIDPP_CAPABILITY_BATTERY_MILEAGE BIT(2) BIT 89 drivers/hid/hid-logitech-hidpp.c #define HIDPP_CAPABILITY_BATTERY_LEVEL_STATUS BIT(3) BIT 537 drivers/hid/hid-logitech-hidpp.c #define HIDPP_ENABLE_CONSUMER_REPORT BIT(0) BIT 538 drivers/hid/hid-logitech-hidpp.c #define HIDPP_ENABLE_WHEEL_REPORT BIT(2) BIT 539 drivers/hid/hid-logitech-hidpp.c #define HIDPP_ENABLE_MOUSE_EXTRA_BTN_REPORT BIT(3) BIT 540 drivers/hid/hid-logitech-hidpp.c #define HIDPP_ENABLE_BAT_REPORT BIT(4) BIT 541 drivers/hid/hid-logitech-hidpp.c #define HIDPP_ENABLE_HWHEEL_REPORT BIT(5) BIT 550 drivers/hid/hid-logitech-hidpp.c #define HIDPP_ENABLE_SPECIAL_BUTTON_FUNC BIT(1) BIT 551 drivers/hid/hid-logitech-hidpp.c #define HIDPP_ENABLE_FAST_SCROLL BIT(6) BIT 1029 drivers/hid/hid-logitech-hidpp.c #define FLAG_BATTERY_LEVEL_DISABLE_OSD BIT(0) BIT 1030 drivers/hid/hid-logitech-hidpp.c #define FLAG_BATTERY_LEVEL_MILEAGE BIT(1) BIT 1031 drivers/hid/hid-logitech-hidpp.c #define FLAG_BATTERY_LEVEL_RECHARGEABLE BIT(2) BIT 1303 drivers/hid/hid-logitech-hidpp.c params[0] = enabled ? BIT(0) : 0; BIT 1363 drivers/hid/hid-logitech-hidpp.c params[0] = (invert ? BIT(2) : 0) | BIT 1364 drivers/hid/hid-logitech-hidpp.c (high_resolution ? BIT(1) : 0) | BIT 1365 drivers/hid/hid-logitech-hidpp.c (use_hidpp ? BIT(0) : 0); BIT 22 drivers/hid/hid-microsoft.c #define MS_HIDINPUT BIT(0) BIT 23 drivers/hid/hid-microsoft.c #define MS_ERGONOMY BIT(1) BIT 24 drivers/hid/hid-microsoft.c #define MS_PRESENTER BIT(2) BIT 25 drivers/hid/hid-microsoft.c #define MS_RDESC BIT(3) BIT 26 drivers/hid/hid-microsoft.c #define MS_NOGET BIT(4) BIT 27 drivers/hid/hid-microsoft.c #define MS_DUPLICATE_USAGES BIT(5) BIT 28 drivers/hid/hid-microsoft.c #define MS_SURFACE_DIAL BIT(6) BIT 29 drivers/hid/hid-microsoft.c #define MS_QUIRK_FF BIT(7) BIT 41 drivers/hid/hid-microsoft.c #define ENABLE_WEAK BIT(0) BIT 42 drivers/hid/hid-microsoft.c #define ENABLE_STRONG BIT(1) BIT 52 drivers/hid/hid-multitouch.c #define MT_QUIRK_NOT_SEEN_MEANS_UP BIT(0) BIT 53 drivers/hid/hid-multitouch.c #define MT_QUIRK_SLOT_IS_CONTACTID BIT(1) BIT 54 drivers/hid/hid-multitouch.c #define MT_QUIRK_CYPRESS BIT(2) BIT 55 drivers/hid/hid-multitouch.c #define MT_QUIRK_SLOT_IS_CONTACTNUMBER BIT(3) BIT 56 drivers/hid/hid-multitouch.c #define MT_QUIRK_ALWAYS_VALID BIT(4) BIT 57 drivers/hid/hid-multitouch.c #define MT_QUIRK_VALID_IS_INRANGE BIT(5) BIT 58 drivers/hid/hid-multitouch.c #define MT_QUIRK_VALID_IS_CONFIDENCE BIT(6) BIT 59 drivers/hid/hid-multitouch.c #define MT_QUIRK_CONFIDENCE BIT(7) BIT 60 drivers/hid/hid-multitouch.c #define MT_QUIRK_SLOT_IS_CONTACTID_MINUS_ONE BIT(8) BIT 61 drivers/hid/hid-multitouch.c #define MT_QUIRK_NO_AREA BIT(9) BIT 62 drivers/hid/hid-multitouch.c #define MT_QUIRK_IGNORE_DUPLICATES BIT(10) BIT 63 drivers/hid/hid-multitouch.c #define MT_QUIRK_HOVERING BIT(11) BIT 64 drivers/hid/hid-multitouch.c #define MT_QUIRK_CONTACT_CNT_ACCURATE BIT(12) BIT 65 drivers/hid/hid-multitouch.c #define MT_QUIRK_FORCE_GET_FEATURE BIT(13) BIT 66 drivers/hid/hid-multitouch.c #define MT_QUIRK_FIX_CONST_CONTACT_ID BIT(14) BIT 67 drivers/hid/hid-multitouch.c #define MT_QUIRK_TOUCH_SIZE_SCALING BIT(15) BIT 68 drivers/hid/hid-multitouch.c #define MT_QUIRK_STICKY_FINGERS BIT(16) BIT 69 drivers/hid/hid-multitouch.c #define MT_QUIRK_ASUS_CUSTOM_UP BIT(17) BIT 70 drivers/hid/hid-multitouch.c #define MT_QUIRK_WIN8_PTP_BUTTONS BIT(18) BIT 71 drivers/hid/hid-multitouch.c #define MT_QUIRK_SEPARATE_APP_REPORT BIT(19) BIT 72 drivers/hid/hid-multitouch.c #define MT_QUIRK_FORCE_MULTI_INPUT BIT(20) BIT 36 drivers/hid/hid-rmi.c #define RMI_DEVICE BIT(0) BIT 37 drivers/hid/hid-rmi.c #define RMI_DEVICE_HAS_PHYS_BUTTONS BIT(1) BIT 38 drivers/hid/hid-rmi.c #define RMI_DEVICE_OUTPUT_SET_REPORT BIT(2) BIT 42 drivers/hid/hid-sony.c #define VAIO_RDESC_CONSTANT BIT(0) BIT 43 drivers/hid/hid-sony.c #define SIXAXIS_CONTROLLER_USB BIT(1) BIT 44 drivers/hid/hid-sony.c #define SIXAXIS_CONTROLLER_BT BIT(2) BIT 45 drivers/hid/hid-sony.c #define BUZZ_CONTROLLER BIT(3) BIT 46 drivers/hid/hid-sony.c #define PS3REMOTE BIT(4) BIT 47 drivers/hid/hid-sony.c #define DUALSHOCK4_CONTROLLER_USB BIT(5) BIT 48 drivers/hid/hid-sony.c #define DUALSHOCK4_CONTROLLER_BT BIT(6) BIT 49 drivers/hid/hid-sony.c #define DUALSHOCK4_DONGLE BIT(7) BIT 50 drivers/hid/hid-sony.c #define MOTION_CONTROLLER_USB BIT(8) BIT 51 drivers/hid/hid-sony.c #define MOTION_CONTROLLER_BT BIT(9) BIT 52 drivers/hid/hid-sony.c #define NAVIGATION_CONTROLLER_USB BIT(10) BIT 53 drivers/hid/hid-sony.c #define NAVIGATION_CONTROLLER_BT BIT(11) BIT 54 drivers/hid/hid-sony.c #define SINO_LITE_CONTROLLER BIT(12) BIT 55 drivers/hid/hid-sony.c #define FUTUREMAX_DANCE_MAT BIT(13) BIT 56 drivers/hid/hid-sony.c #define NSG_MR5U_REMOTE_BT BIT(14) BIT 57 drivers/hid/hid-sony.c #define NSG_MR7U_REMOTE_BT BIT(15) BIT 58 drivers/hid/hid-sony.c #define SHANWAN_GAMEPAD BIT(16) BIT 55 drivers/hid/hid-steam.c #define STEAM_QUIRK_WIRELESS BIT(0) BIT 938 drivers/hid/hid-steam.c lpad_touched = b10 & BIT(3); BIT 939 drivers/hid/hid-steam.c lpad_and_joy = b10 & BIT(7); BIT 959 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_TR2, !!(b8 & BIT(0))); BIT 960 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_TL2, !!(b8 & BIT(1))); BIT 961 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_TR, !!(b8 & BIT(2))); BIT 962 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_TL, !!(b8 & BIT(3))); BIT 963 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_Y, !!(b8 & BIT(4))); BIT 964 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_B, !!(b8 & BIT(5))); BIT 965 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_X, !!(b8 & BIT(6))); BIT 966 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_A, !!(b8 & BIT(7))); BIT 967 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_SELECT, !!(b9 & BIT(4))); BIT 968 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_MODE, !!(b9 & BIT(5))); BIT 969 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_START, !!(b9 & BIT(6))); BIT 970 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_GEAR_DOWN, !!(b9 & BIT(7))); BIT 971 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_GEAR_UP, !!(b10 & BIT(0))); BIT 972 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_THUMBR, !!(b10 & BIT(2))); BIT 973 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_THUMBL, !!(b10 & BIT(6))); BIT 975 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_THUMB2, !!(b10 & BIT(4))); BIT 976 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_DPAD_UP, !!(b9 & BIT(0))); BIT 977 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_DPAD_RIGHT, !!(b9 & BIT(1))); BIT 978 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_DPAD_LEFT, !!(b9 & BIT(2))); BIT 979 drivers/hid/hid-steam.c input_event(input, EV_KEY, BTN_DPAD_DOWN, !!(b9 & BIT(3))); BIT 311 drivers/hid/hid-udraw-ps3.c input_dev->evbit[0] = BIT(EV_ABS) | BIT(EV_KEY); BIT 338 drivers/hid/hid-udraw-ps3.c input_dev->evbit[0] = BIT(EV_ABS) | BIT(EV_KEY); BIT 366 drivers/hid/hid-udraw-ps3.c input_dev->evbit[0] = BIT(EV_ABS); BIT 389 drivers/hid/hid-udraw-ps3.c input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_ABS); BIT 48 drivers/hid/i2c-hid/i2c-hid-core.c #define I2C_HID_QUIRK_SET_PWR_WAKEUP_DEV BIT(0) BIT 49 drivers/hid/i2c-hid/i2c-hid-core.c #define I2C_HID_QUIRK_NO_IRQ_AFTER_RESET BIT(1) BIT 50 drivers/hid/i2c-hid/i2c-hid-core.c #define I2C_HID_QUIRK_BOGUS_IRQ BIT(4) BIT 51 drivers/hid/i2c-hid/i2c-hid-core.c #define I2C_HID_QUIRK_RESET_ON_RESUME BIT(5) BIT 52 drivers/hid/i2c-hid/i2c-hid-core.c #define I2C_HID_QUIRK_BAD_INPUT_SIZE BIT(6) BIT 50 drivers/hid/intel-ish-hid/ishtp-fw-loader.c #define IS_RESPONSE BIT(7) BIT 75 drivers/hid/intel-ish-hid/ishtp-fw-loader.c #define LOADER_XFER_MODE_DIRECT_DMA BIT(0) BIT 76 drivers/hid/intel-ish-hid/ishtp-fw-loader.c #define LOADER_XFER_MODE_ISHTP BIT(1) BIT 3097 drivers/hid/wacom_wac.c valid = !!(prefix & BIT(id)) && BIT 3917 drivers/hid/wacom_wac.c if (!updated && mask & BIT(i)) { BIT 22 drivers/hwmon/adt7411.c #define ADT7411_STAT_1_INT_TEMP_HIGH BIT(0) BIT 23 drivers/hwmon/adt7411.c #define ADT7411_STAT_1_INT_TEMP_LOW BIT(1) BIT 24 drivers/hwmon/adt7411.c #define ADT7411_STAT_1_EXT_TEMP_HIGH_AIN1 BIT(2) BIT 25 drivers/hwmon/adt7411.c #define ADT7411_STAT_1_EXT_TEMP_LOW BIT(3) BIT 26 drivers/hwmon/adt7411.c #define ADT7411_STAT_1_EXT_TEMP_FAULT BIT(4) BIT 27 drivers/hwmon/adt7411.c #define ADT7411_STAT_1_AIN2 BIT(5) BIT 28 drivers/hwmon/adt7411.c #define ADT7411_STAT_1_AIN3 BIT(6) BIT 29 drivers/hwmon/adt7411.c #define ADT7411_STAT_1_AIN4 BIT(7) BIT 31 drivers/hwmon/adt7411.c #define ADT7411_STAT_2_AIN5 BIT(0) BIT 32 drivers/hwmon/adt7411.c #define ADT7411_STAT_2_AIN6 BIT(1) BIT 33 drivers/hwmon/adt7411.c #define ADT7411_STAT_2_AIN7 BIT(2) BIT 34 drivers/hwmon/adt7411.c #define ADT7411_STAT_2_AIN8 BIT(3) BIT 35 drivers/hwmon/adt7411.c #define ADT7411_STAT_2_VDD BIT(4) BIT 43 drivers/hwmon/adt7411.c #define ADT7411_CFG1_START_MONITOR BIT(0) BIT 44 drivers/hwmon/adt7411.c #define ADT7411_CFG1_RESERVED_BIT1 BIT(1) BIT 45 drivers/hwmon/adt7411.c #define ADT7411_CFG1_EXT_TDM BIT(2) BIT 46 drivers/hwmon/adt7411.c #define ADT7411_CFG1_RESERVED_BIT3 BIT(3) BIT 49 drivers/hwmon/adt7411.c #define ADT7411_CFG2_DISABLE_AVG BIT(5) BIT 52 drivers/hwmon/adt7411.c #define ADT7411_CFG3_ADC_CLK_225 BIT(0) BIT 53 drivers/hwmon/adt7411.c #define ADT7411_CFG3_RESERVED_BIT1 BIT(1) BIT 54 drivers/hwmon/adt7411.c #define ADT7411_CFG3_RESERVED_BIT2 BIT(2) BIT 55 drivers/hwmon/adt7411.c #define ADT7411_CFG3_RESERVED_BIT3 BIT(3) BIT 56 drivers/hwmon/adt7411.c #define ADT7411_CFG3_REF_VDD BIT(4) BIT 824 drivers/hwmon/adt7475.c u8 mask = BIT(5 + sattr->index); BIT 837 drivers/hwmon/adt7475.c u8 mask = BIT(5 + sattr->index); BIT 17 drivers/hwmon/as370-hwmon.c #define PD BIT(0) BIT 18 drivers/hwmon/as370-hwmon.c #define EN BIT(1) BIT 19 drivers/hwmon/as370-hwmon.c #define T_SEL BIT(2) BIT 20 drivers/hwmon/as370-hwmon.c #define V_SEL BIT(3) BIT 21 drivers/hwmon/as370-hwmon.c #define NMOS_SEL BIT(8) BIT 22 drivers/hwmon/as370-hwmon.c #define PMOS_SEL BIT(9) BIT 25 drivers/hwmon/as370-hwmon.c #define EOC BIT(12) BIT 51 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15)) BIT 55 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14)) BIT 59 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13)) BIT 63 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12)) BIT 65 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x) BIT(16 + (x)) BIT 67 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_PWMD_EN BIT(11) BIT 68 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_PWMC_EN BIT(10) BIT 69 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_PWMB_EN BIT(9) BIT 70 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_PWMA_EN BIT(8) BIT 72 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_CLK_SRC BIT(1) BIT 73 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_CLK_EN BIT(0) BIT 111 drivers/hwmon/aspeed-pwm-tacho.c #define TACH_PWM_SOURCE_MASK_BIT2(x) BIT((x) * 2) BIT 114 drivers/hwmon/aspeed-pwm-tacho.c #define RESULT_STATUS_MASK BIT(31) BIT 120 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15)) BIT 124 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14)) BIT 128 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13)) BIT 132 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12)) BIT 134 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_PWMH_EN BIT(11) BIT 135 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_PWMG_EN BIT(10) BIT 136 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_PWMF_EN BIT(9) BIT 137 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CTRL_PWME_EN BIT(8) BIT 339 drivers/hwmon/fam15h_power.c if ((val & BIT(29)) && ((val >> 30) & 3)) BIT 177 drivers/hwmon/ftsteutates.c if (data->fan_present & BIT(i)) { BIT 234 drivers/hwmon/ftsteutates.c if ((resolution == seconds && ret & BIT(1)) || BIT 235 drivers/hwmon/ftsteutates.c (resolution == minutes && (ret & BIT(1)) == 0)) { BIT 241 drivers/hwmon/ftsteutates.c ret |= BIT(1); BIT 243 drivers/hwmon/ftsteutates.c ret &= ~BIT(1); BIT 325 drivers/hwmon/ftsteutates.c data->resolution = ret & BIT(1) ? seconds : minutes; BIT 399 drivers/hwmon/ftsteutates.c return sprintf(buf, "%u\n", !!(data->temp_alarm & BIT(index))); BIT 473 drivers/hwmon/ftsteutates.c return sprintf(buf, "%d\n", !!(data->fan_alarm & BIT(index))); BIT 534 drivers/hwmon/hwmon.c attr_mask &= ~BIT(attr); BIT 902 drivers/hwmon/hwmon.c if (base == 0 && !(enable & BIT(2))) { BIT 907 drivers/hwmon/hwmon.c enable | BIT(2)); BIT 38 drivers/hwmon/ina3221.c #define INA3221_CONFIG_MODE_SHUNT BIT(0) BIT 39 drivers/hwmon/ina3221.c #define INA3221_CONFIG_MODE_BUS BIT(1) BIT 40 drivers/hwmon/ina3221.c #define INA3221_CONFIG_MODE_CONTINUOUS BIT(2) BIT 51 drivers/hwmon/ina3221.c #define INA3221_CONFIG_CHx_EN(x) BIT(14 - (x)) BIT 277 drivers/hwmon/it87.c #define FEAT_12MV_ADC BIT(0) BIT 278 drivers/hwmon/it87.c #define FEAT_NEWER_AUTOPWM BIT(1) BIT 279 drivers/hwmon/it87.c #define FEAT_OLD_AUTOPWM BIT(2) BIT 280 drivers/hwmon/it87.c #define FEAT_16BIT_FANS BIT(3) BIT 281 drivers/hwmon/it87.c #define FEAT_TEMP_OFFSET BIT(4) BIT 282 drivers/hwmon/it87.c #define FEAT_TEMP_PECI BIT(5) BIT 283 drivers/hwmon/it87.c #define FEAT_TEMP_OLD_PECI BIT(6) BIT 284 drivers/hwmon/it87.c #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ BIT 285 drivers/hwmon/it87.c #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */ BIT 286 drivers/hwmon/it87.c #define FEAT_VID BIT(9) /* Set if chip supports VID */ BIT 287 drivers/hwmon/it87.c #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */ BIT 288 drivers/hwmon/it87.c #define FEAT_SIX_FANS BIT(11) /* Supports six fans */ BIT 289 drivers/hwmon/it87.c #define FEAT_10_9MV_ADC BIT(12) BIT 290 drivers/hwmon/it87.c #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */ BIT 291 drivers/hwmon/it87.c #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */ BIT 292 drivers/hwmon/it87.c #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */ BIT 293 drivers/hwmon/it87.c #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */ BIT 294 drivers/hwmon/it87.c #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */ BIT 295 drivers/hwmon/it87.c #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */ BIT 472 drivers/hwmon/it87.c ((data)->peci_mask & BIT(nr))) BIT 475 drivers/hwmon/it87.c ((data)->old_peci_mask & BIT(nr))) BIT 576 drivers/hwmon/it87.c if (data->in_scaled & BIT(nr)) BIT 642 drivers/hwmon/it87.c #define DIV_FROM_REG(val) BIT(val) BIT 755 drivers/hwmon/it87.c if (!(data->has_in & BIT(i))) BIT 773 drivers/hwmon/it87.c if (!(data->has_fan & BIT(i))) BIT 789 drivers/hwmon/it87.c if (!(data->has_temp & BIT(i))) BIT 826 drivers/hwmon/it87.c if (!(data->has_pwm & BIT(i))) BIT 1098 drivers/hwmon/it87.c if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr))) BIT 1319 drivers/hwmon/it87.c it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr)); BIT 1321 drivers/hwmon/it87.c data->fan_main_ctrl &= ~BIT(nr); BIT 1357 drivers/hwmon/it87.c data->fan_main_ctrl |= BIT(nr); BIT 1458 drivers/hwmon/it87.c return sprintf(buf, "%d\n", (int)BIT(map)); BIT 1478 drivers/hwmon/it87.c case BIT(0): BIT 1481 drivers/hwmon/it87.c case BIT(1): BIT 1484 drivers/hwmon/it87.c case BIT(2): BIT 1834 drivers/hwmon/it87.c config |= BIT(5); BIT 1886 drivers/hwmon/it87.c data->beeps |= BIT(bitnr); BIT 1888 drivers/hwmon/it87.c data->beeps &= ~BIT(bitnr); BIT 1994 drivers/hwmon/it87.c if (!(data->has_in & BIT(i))) BIT 2078 drivers/hwmon/it87.c if (!(data->has_temp & BIT(i))) BIT 2135 drivers/hwmon/it87.c if (index > 3 && !(data->in_internal & BIT(index - 4))) BIT 2171 drivers/hwmon/it87.c if (!(data->has_fan & BIT(i))) BIT 2237 drivers/hwmon/it87.c if (!(data->has_pwm & BIT(i))) BIT 2303 drivers/hwmon/it87.c if (!(data->has_pwm & BIT(i))) BIT 2495 drivers/hwmon/it87.c sio_data->internal |= BIT(1); BIT 2498 drivers/hwmon/it87.c sio_data->internal |= BIT(2); BIT 2502 drivers/hwmon/it87.c sio_data->internal |= BIT(3); /* in9 is AVCC */ BIT 2504 drivers/hwmon/it87.c sio_data->skip_in |= BIT(9); BIT 2507 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5); BIT 2509 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(5); BIT 2532 drivers/hwmon/it87.c if ((reg27 & BIT(0)) || !(reg2c & BIT(2))) BIT 2533 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(2); BIT 2534 drivers/hwmon/it87.c if ((reg25 & BIT(4)) || BIT 2535 drivers/hwmon/it87.c (!(reg2a & BIT(1)) && (regef & BIT(0)))) BIT 2536 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(2); BIT 2539 drivers/hwmon/it87.c if (reg27 & BIT(7)) BIT 2540 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(1); BIT 2541 drivers/hwmon/it87.c if (reg27 & BIT(3)) BIT 2542 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(1); BIT 2545 drivers/hwmon/it87.c if ((reg27 & BIT(0)) || (reg2c & BIT(2))) BIT 2546 drivers/hwmon/it87.c sio_data->skip_in |= BIT(5); /* No VIN5 */ BIT 2549 drivers/hwmon/it87.c if (reg27 & BIT(1)) BIT 2550 drivers/hwmon/it87.c sio_data->skip_in |= BIT(6); /* No VIN6 */ BIT 2556 drivers/hwmon/it87.c if (reg27 & BIT(2)) { BIT 2570 drivers/hwmon/it87.c if (!(reg2c & BIT(1))) { BIT 2571 drivers/hwmon/it87.c reg2c |= BIT(1); BIT 2581 drivers/hwmon/it87.c if (reg2c & BIT(0)) BIT 2582 drivers/hwmon/it87.c sio_data->internal |= BIT(0); BIT 2583 drivers/hwmon/it87.c if (reg2c & BIT(1)) BIT 2584 drivers/hwmon/it87.c sio_data->internal |= BIT(1); BIT 2596 drivers/hwmon/it87.c if (reg27 & BIT(6)) BIT 2597 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(2); BIT 2598 drivers/hwmon/it87.c if (reg27 & BIT(7)) BIT 2599 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(2); BIT 2603 drivers/hwmon/it87.c if (reg29 & BIT(1)) BIT 2604 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(1); BIT 2605 drivers/hwmon/it87.c if (reg29 & BIT(2)) BIT 2606 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(1); BIT 2608 drivers/hwmon/it87.c sio_data->skip_in |= BIT(5); /* No VIN5 */ BIT 2609 drivers/hwmon/it87.c sio_data->skip_in |= BIT(6); /* No VIN6 */ BIT 2620 drivers/hwmon/it87.c if (reg & BIT(6)) BIT 2621 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(4); BIT 2625 drivers/hwmon/it87.c if (!(reg & BIT(5))) BIT 2626 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(3); BIT 2627 drivers/hwmon/it87.c if (!(reg & BIT(4))) BIT 2628 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(4); BIT 2632 drivers/hwmon/it87.c if (reg & BIT(6)) BIT 2633 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(2); BIT 2634 drivers/hwmon/it87.c if (reg & BIT(7)) BIT 2635 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(2); BIT 2639 drivers/hwmon/it87.c if (reg & BIT(2)) BIT 2640 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(3); BIT 2644 drivers/hwmon/it87.c if (reg & BIT(1)) BIT 2645 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(1); BIT 2646 drivers/hwmon/it87.c if (reg & BIT(2)) BIT 2647 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(1); BIT 2649 drivers/hwmon/it87.c if (!(reg & BIT(7))) { BIT 2650 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(5); BIT 2651 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(5); BIT 2656 drivers/hwmon/it87.c if (reg & BIT(0)) BIT 2657 drivers/hwmon/it87.c sio_data->internal |= BIT(0); BIT 2659 drivers/hwmon/it87.c sio_data->skip_in |= BIT(9); BIT 2670 drivers/hwmon/it87.c if (reg & BIT(6)) BIT 2671 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(3); BIT 2672 drivers/hwmon/it87.c if (reg & BIT(5)) BIT 2673 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(3); BIT 2677 drivers/hwmon/it87.c if (reg & BIT(6)) BIT 2678 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(2); BIT 2679 drivers/hwmon/it87.c if (reg & BIT(7)) BIT 2680 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(2); BIT 2681 drivers/hwmon/it87.c if (reg & BIT(3)) BIT 2682 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(4); BIT 2683 drivers/hwmon/it87.c if (reg & BIT(1)) BIT 2684 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(4); BIT 2688 drivers/hwmon/it87.c if (reg & BIT(1)) BIT 2689 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(1); BIT 2690 drivers/hwmon/it87.c if (reg & BIT(2)) BIT 2691 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(1); BIT 2695 drivers/hwmon/it87.c if (!(reg & BIT(0))) BIT 2696 drivers/hwmon/it87.c sio_data->skip_in |= BIT(9); BIT 2711 drivers/hwmon/it87.c if (reg & BIT(5)) BIT 2712 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(3); BIT 2713 drivers/hwmon/it87.c if (reg & BIT(4)) BIT 2714 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(4); BIT 2719 drivers/hwmon/it87.c if (!(reg & BIT(5))) BIT 2720 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(3); BIT 2721 drivers/hwmon/it87.c if (!(reg & BIT(4))) BIT 2722 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(4); BIT 2739 drivers/hwmon/it87.c if (reg & BIT(6)) BIT 2740 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(2); BIT 2741 drivers/hwmon/it87.c if (reg & BIT(7)) BIT 2742 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(2); BIT 2746 drivers/hwmon/it87.c if (reg & BIT(1)) BIT 2747 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(1); BIT 2748 drivers/hwmon/it87.c if (reg & BIT(2)) BIT 2749 drivers/hwmon/it87.c sio_data->skip_fan |= BIT(1); BIT 2758 drivers/hwmon/it87.c uart6 = sio_data->type == it8782 && (reg & BIT(2)); BIT 2774 drivers/hwmon/it87.c if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) { BIT 2775 drivers/hwmon/it87.c reg |= BIT(1); BIT 2780 drivers/hwmon/it87.c if (reg & BIT(0)) BIT 2781 drivers/hwmon/it87.c sio_data->internal |= BIT(0); BIT 2782 drivers/hwmon/it87.c if (reg & BIT(1)) BIT 2783 drivers/hwmon/it87.c sio_data->internal |= BIT(1); BIT 2795 drivers/hwmon/it87.c sio_data->skip_in |= BIT(5) | BIT(6); BIT 2796 drivers/hwmon/it87.c sio_data->skip_temp |= BIT(2); BIT 2820 drivers/hwmon/it87.c sio_data->skip_pwm = BIT(1); BIT 2954 drivers/hwmon/it87.c if (tmp & BIT(4)) BIT 2955 drivers/hwmon/it87.c data->has_fan |= BIT(3); /* fan4 enabled */ BIT 2956 drivers/hwmon/it87.c if (tmp & BIT(5)) BIT 2957 drivers/hwmon/it87.c data->has_fan |= BIT(4); /* fan5 enabled */ BIT 2958 drivers/hwmon/it87.c if (has_six_fans(data) && (tmp & BIT(2))) BIT 2959 drivers/hwmon/it87.c data->has_fan |= BIT(5); /* fan6 enabled */ BIT 2970 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(4); BIT 2971 drivers/hwmon/it87.c if (!(tmp & BIT(3))) BIT 2972 drivers/hwmon/it87.c sio_data->skip_pwm |= BIT(5); BIT 3102 drivers/hwmon/it87.c if (sio_data->internal & BIT(0)) BIT 3103 drivers/hwmon/it87.c data->in_scaled |= BIT(3); /* in3 is AVCC */ BIT 3104 drivers/hwmon/it87.c if (sio_data->internal & BIT(1)) BIT 3105 drivers/hwmon/it87.c data->in_scaled |= BIT(7); /* in7 is VSB */ BIT 3106 drivers/hwmon/it87.c if (sio_data->internal & BIT(2)) BIT 3107 drivers/hwmon/it87.c data->in_scaled |= BIT(8); /* in8 is Vbat */ BIT 3108 drivers/hwmon/it87.c if (sio_data->internal & BIT(3)) BIT 3109 drivers/hwmon/it87.c data->in_scaled |= BIT(9); /* in9 is AVCC */ BIT 3112 drivers/hwmon/it87.c if (sio_data->internal & BIT(0)) BIT 3113 drivers/hwmon/it87.c data->in_scaled |= BIT(3); /* in3 is VCC5V */ BIT 3114 drivers/hwmon/it87.c if (sio_data->internal & BIT(1)) BIT 3115 drivers/hwmon/it87.c data->in_scaled |= BIT(7); /* in7 is VCCH5V */ BIT 3119 drivers/hwmon/it87.c if (sio_data->skip_temp & BIT(2)) { BIT 3122 drivers/hwmon/it87.c data->has_temp &= ~BIT(2); BIT 3134 drivers/hwmon/it87.c data->has_temp |= BIT(3); BIT 3136 drivers/hwmon/it87.c data->has_temp |= BIT(4); BIT 3138 drivers/hwmon/it87.c data->has_temp |= BIT(5); BIT 3142 drivers/hwmon/it87.c data->has_in |= BIT(10); BIT 3144 drivers/hwmon/it87.c data->has_in |= BIT(11); BIT 3146 drivers/hwmon/it87.c data->has_in |= BIT(12); BIT 3168 drivers/hwmon/it87.c data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1; BIT 3202 drivers/hwmon/it87.c if (!(reg2c & BIT(1))) { BIT 3206 drivers/hwmon/it87.c reg2c |= BIT(1); BIT 68 drivers/hwmon/jc42.c #define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */ BIT 41 drivers/hwmon/lm73.c #define LM73_CTRL_RES_MASK (BIT(5) | BIT(6)) BIT 42 drivers/hwmon/lm73.c #define LM73_CTRL_TO_MASK BIT(7) BIT 492 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp2_fault, alarm, BIT(0) | BIT(1)); BIT 493 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp3_fault, alarm, BIT(2) | BIT(3)); BIT 494 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp4_fault, alarm, BIT(4) | BIT(5)); BIT 495 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp5_fault, alarm, BIT(6) | BIT(7)); BIT 497 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RW(temp2_type, type, BIT(1)); BIT 498 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RW(temp3_type, type, BIT(2)); BIT 499 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RW(temp4_type, type, BIT(3)); BIT 500 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RW(temp5_type, type, BIT(4)); BIT 514 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp1_max_alarm, alarm, BIT(0 + 8)); BIT 515 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp2_max_alarm, alarm, BIT(1 + 16)); BIT 516 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp3_max_alarm, alarm, BIT(2 + 16)); BIT 517 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp4_max_alarm, alarm, BIT(3 + 8)); BIT 518 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp5_max_alarm, alarm, BIT(4 + 8)); BIT 526 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp2_crit_alarm, alarm, BIT(1 + 8)); BIT 527 drivers/hwmon/lm95234.c static SENSOR_DEVICE_ATTR_RO(temp3_crit_alarm, alarm, BIT(2 + 8)); BIT 43 drivers/hwmon/lm95241.c #define CFG_STOP BIT(6) BIT 45 drivers/hwmon/lm95241.c #define CFG_CR0182 BIT(4) BIT 46 drivers/hwmon/lm95241.c #define CFG_CR1000 BIT(5) BIT 47 drivers/hwmon/lm95241.c #define CFG_CR2700 (BIT(4) | BIT(5)) BIT 48 drivers/hwmon/lm95241.c #define CFG_CRMASK (BIT(4) | BIT(5)) BIT 49 drivers/hwmon/lm95241.c #define R1MS_MASK BIT(0) BIT 50 drivers/hwmon/lm95241.c #define R2MS_MASK BIT(2) BIT 51 drivers/hwmon/lm95241.c #define R1DF_MASK BIT(1) BIT 52 drivers/hwmon/lm95241.c #define R2DF_MASK BIT(2) BIT 53 drivers/hwmon/lm95241.c #define R1FE_MASK BIT(0) BIT 54 drivers/hwmon/lm95241.c #define R2FE_MASK BIT(2) BIT 55 drivers/hwmon/lm95241.c #define R1DM BIT(0) BIT 56 drivers/hwmon/lm95241.c #define R2DM BIT(1) BIT 150 drivers/hwmon/lm95241.c if (!channel || (data->config & BIT(channel - 1))) BIT 28 drivers/hwmon/ltc2990.c #define LTC2990_IN0 BIT(0) BIT 29 drivers/hwmon/ltc2990.c #define LTC2990_IN1 BIT(1) BIT 30 drivers/hwmon/ltc2990.c #define LTC2990_IN2 BIT(2) BIT 31 drivers/hwmon/ltc2990.c #define LTC2990_IN3 BIT(3) BIT 32 drivers/hwmon/ltc2990.c #define LTC2990_IN4 BIT(4) BIT 33 drivers/hwmon/ltc2990.c #define LTC2990_CURR1 BIT(5) BIT 34 drivers/hwmon/ltc2990.c #define LTC2990_CURR2 BIT(6) BIT 35 drivers/hwmon/ltc2990.c #define LTC2990_TEMP1 BIT(7) BIT 36 drivers/hwmon/ltc2990.c #define LTC2990_TEMP2 BIT(8) BIT 37 drivers/hwmon/ltc2990.c #define LTC2990_TEMP3 BIT(9) BIT 40 drivers/hwmon/ltc4222.c #define FAULT_OV BIT(0) BIT 41 drivers/hwmon/ltc4222.c #define FAULT_UV BIT(1) BIT 42 drivers/hwmon/ltc4222.c #define FAULT_OC BIT(2) BIT 43 drivers/hwmon/ltc4222.c #define FAULT_POWER_BAD BIT(3) BIT 44 drivers/hwmon/ltc4222.c #define FAULT_FET_BAD BIT(5) BIT 278 drivers/hwmon/ltc4245.c *val = !!(data->cregs[LTC4245_FAULT1] & BIT(channel + 4)); BIT 304 drivers/hwmon/ltc4245.c *val = !!(data->cregs[LTC4245_FAULT1] & BIT(channel)); BIT 307 drivers/hwmon/ltc4245.c BIT(channel - 4)); BIT 19 drivers/hwmon/ltq-cputemp.c #define CGU_TEMP_PD BIT(19) BIT 57 drivers/hwmon/max6621.c BIT(MAX6621_ENABLE_LOCKUP_TO) | \ BIT 58 drivers/hwmon/max6621.c BIT(MAX6621_ENABLE_I2C_CRC_BIT) | \ BIT 1043 drivers/hwmon/nct6775.c return BIT(reg); BIT 1520 drivers/hwmon/nct6775.c if (data->has_fan & BIT(3)) BIT 1542 drivers/hwmon/nct6775.c if (!(data->has_fan & BIT(i))) BIT 1565 drivers/hwmon/nct6775.c if (data->has_fan_min & BIT(i)) { BIT 1600 drivers/hwmon/nct6775.c if (data->has_fan_min & BIT(nr)) { BIT 1631 drivers/hwmon/nct6775.c if (!(data->has_pwm & BIT(i))) BIT 1701 drivers/hwmon/nct6775.c if (!(data->has_pwm & BIT(i))) BIT 1783 drivers/hwmon/nct6775.c if (!(data->have_in & BIT(i))) BIT 1798 drivers/hwmon/nct6775.c if (!(data->has_fan & BIT(i))) BIT 1805 drivers/hwmon/nct6775.c if (data->has_fan_min & BIT(i)) BIT 1824 drivers/hwmon/nct6775.c if (!(data->have_temp & BIT(i))) BIT 1833 drivers/hwmon/nct6775.c !(data->have_temp_fixed & BIT(i))) BIT 2054 drivers/hwmon/nct6775.c if (!(data->have_in & BIT(in))) BIT 2261 drivers/hwmon/nct6775.c if (!(data->has_fan & BIT(fan))) BIT 2270 drivers/hwmon/nct6775.c if (nr == 4 && !(data->has_fan_min & BIT(fan))) BIT 2448 drivers/hwmon/nct6775.c if (!(data->have_temp & BIT(temp))) BIT 2473 drivers/hwmon/nct6775.c if (nr > 7 && !(data->have_temp_fixed & BIT(temp))) BIT 2742 drivers/hwmon/nct6775.c if (!(data->have_temp & BIT(i))) BIT 2778 drivers/hwmon/nct6775.c if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1]) BIT 2821 drivers/hwmon/nct6775.c if (val && (!(data->have_temp & BIT(val - 1)) || BIT 3265 drivers/hwmon/nct6775.c if (!(data->has_pwm & BIT(pwm))) BIT 3516 drivers/hwmon/nct6775.c if (!(data->have_temp & BIT(i))) BIT 3534 drivers/hwmon/nct6775.c if (!(data->have_temp_fixed & BIT(i))) BIT 3561 drivers/hwmon/nct6775.c fan3pin = cr2c & BIT(6); BIT 3562 drivers/hwmon/nct6775.c pwm3pin = cr2c & BIT(7); BIT 3641 drivers/hwmon/nct6775.c bool dsw_en = cr2f & BIT(3); BIT 3642 drivers/hwmon/nct6775.c bool ddr4_en = cr2f & BIT(4); BIT 3652 drivers/hwmon/nct6775.c fan3pin = !(cr1c & BIT(5)); BIT 3653 drivers/hwmon/nct6775.c fan4pin = !(cr1c & BIT(6)); BIT 3654 drivers/hwmon/nct6775.c fan5pin = !(cr1c & BIT(7)); BIT 3656 drivers/hwmon/nct6775.c pwm3pin = !(cr1c & BIT(0)); BIT 3657 drivers/hwmon/nct6775.c pwm4pin = !(cr1c & BIT(1)); BIT 3658 drivers/hwmon/nct6775.c pwm5pin = !(cr1c & BIT(2)); BIT 3662 drivers/hwmon/nct6775.c fan6pin = cr2d & BIT(1); BIT 3663 drivers/hwmon/nct6775.c pwm6pin = cr2d & BIT(0); BIT 3666 drivers/hwmon/nct6775.c fan6pin = !dsw_en && (cr2d & BIT(1)); BIT 3667 drivers/hwmon/nct6775.c pwm6pin = !dsw_en && (cr2d & BIT(0)); BIT 3670 drivers/hwmon/nct6775.c fan5pin |= cr1b & BIT(5); BIT 3671 drivers/hwmon/nct6775.c fan5pin |= creb & BIT(5); BIT 3673 drivers/hwmon/nct6775.c fan6pin = !dsw_en && (cr2d & BIT(1)); BIT 3674 drivers/hwmon/nct6775.c fan6pin |= creb & BIT(3); BIT 3676 drivers/hwmon/nct6775.c pwm5pin |= cr2d & BIT(7); BIT 3677 drivers/hwmon/nct6775.c pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0)); BIT 3679 drivers/hwmon/nct6775.c pwm6pin = !dsw_en && (cr2d & BIT(0)); BIT 3680 drivers/hwmon/nct6775.c pwm6pin |= creb & BIT(2); BIT 3683 drivers/hwmon/nct6775.c fan5pin |= cr1b & BIT(5); BIT 3684 drivers/hwmon/nct6775.c fan5pin |= creb & BIT(5); BIT 3686 drivers/hwmon/nct6775.c fan6pin = (cr2a & BIT(4)) && BIT 3687 drivers/hwmon/nct6775.c (!dsw_en || (cred & BIT(4))); BIT 3688 drivers/hwmon/nct6775.c fan6pin |= creb & BIT(3); BIT 3690 drivers/hwmon/nct6775.c pwm5pin |= cr2d & BIT(7); BIT 3691 drivers/hwmon/nct6775.c pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0)); BIT 3693 drivers/hwmon/nct6775.c pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2)); BIT 3694 drivers/hwmon/nct6775.c pwm6pin |= creb & BIT(2); BIT 3697 drivers/hwmon/nct6775.c fan5pin |= cr1b & BIT(5); BIT 3698 drivers/hwmon/nct6775.c fan5pin |= (cre0 & BIT(3)) && !(cr1b & BIT(0)); BIT 3699 drivers/hwmon/nct6775.c fan5pin |= creb & BIT(5); BIT 3701 drivers/hwmon/nct6775.c fan6pin = (cr2a & BIT(4)) && BIT 3702 drivers/hwmon/nct6775.c (!dsw_en || (cred & BIT(4))); BIT 3703 drivers/hwmon/nct6775.c fan6pin |= creb & BIT(3); BIT 3705 drivers/hwmon/nct6775.c fan7pin = !(cr2b & BIT(2)); BIT 3707 drivers/hwmon/nct6775.c pwm5pin |= cr2d & BIT(7); BIT 3708 drivers/hwmon/nct6775.c pwm5pin |= (cre0 & BIT(4)) && !(cr1b & BIT(0)); BIT 3709 drivers/hwmon/nct6775.c pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0)); BIT 3711 drivers/hwmon/nct6775.c pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2)); BIT 3712 drivers/hwmon/nct6775.c pwm6pin |= creb & BIT(2); BIT 3714 drivers/hwmon/nct6775.c pwm7pin = !(cr1d & (BIT(2) | BIT(3))); BIT 3717 drivers/hwmon/nct6775.c fan5pin |= !ddr4_en && (cr1b & BIT(5)); BIT 3718 drivers/hwmon/nct6775.c fan5pin |= creb & BIT(5); BIT 3720 drivers/hwmon/nct6775.c fan6pin = cr2a & BIT(4); BIT 3721 drivers/hwmon/nct6775.c fan6pin |= creb & BIT(3); BIT 3723 drivers/hwmon/nct6775.c fan7pin = cr1a & BIT(1); BIT 3725 drivers/hwmon/nct6775.c pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0)); BIT 3726 drivers/hwmon/nct6775.c pwm5pin |= !ddr4_en && (cr2d & BIT(7)); BIT 3728 drivers/hwmon/nct6775.c pwm6pin = creb & BIT(2); BIT 3729 drivers/hwmon/nct6775.c pwm6pin |= cred & BIT(2); BIT 3731 drivers/hwmon/nct6775.c pwm7pin = cr1d & BIT(4); BIT 3734 drivers/hwmon/nct6775.c fan6pin = !(cr1b & BIT(0)) && (cre0 & BIT(3)); BIT 3735 drivers/hwmon/nct6775.c fan6pin |= cr2a & BIT(4); BIT 3736 drivers/hwmon/nct6775.c fan6pin |= creb & BIT(5); BIT 3738 drivers/hwmon/nct6775.c fan7pin = cr1b & BIT(5); BIT 3739 drivers/hwmon/nct6775.c fan7pin |= !(cr2b & BIT(2)); BIT 3740 drivers/hwmon/nct6775.c fan7pin |= creb & BIT(3); BIT 3742 drivers/hwmon/nct6775.c pwm6pin = !(cr1b & BIT(0)) && (cre0 & BIT(4)); BIT 3743 drivers/hwmon/nct6775.c pwm6pin |= !(cred & BIT(2)) && (cr2a & BIT(3)); BIT 3744 drivers/hwmon/nct6775.c pwm6pin |= (creb & BIT(4)) && !(cr2a & BIT(0)); BIT 3746 drivers/hwmon/nct6775.c pwm7pin = !(cr1d & (BIT(2) | BIT(3))); BIT 3747 drivers/hwmon/nct6775.c pwm7pin |= cr2d & BIT(7); BIT 3748 drivers/hwmon/nct6775.c pwm7pin |= creb & BIT(2); BIT 3779 drivers/hwmon/nct6775.c if (!src || (*mask & BIT(src))) BIT 3781 drivers/hwmon/nct6775.c if (!(data->temp_mask & BIT(src))) BIT 3786 drivers/hwmon/nct6775.c *available &= ~BIT(index); BIT 3787 drivers/hwmon/nct6775.c *mask |= BIT(src); BIT 4323 drivers/hwmon/nct6775.c data->have_in = BIT(data->in_num) - 1; BIT 4341 drivers/hwmon/nct6775.c if (!src || (mask & BIT(src))) BIT 4342 drivers/hwmon/nct6775.c available |= BIT(i); BIT 4344 drivers/hwmon/nct6775.c mask |= BIT(src); BIT 4361 drivers/hwmon/nct6775.c if (!src || (mask & BIT(src))) BIT 4364 drivers/hwmon/nct6775.c if (!(data->temp_mask & BIT(src))) { BIT 4371 drivers/hwmon/nct6775.c mask |= BIT(src); BIT 4375 drivers/hwmon/nct6775.c data->have_temp |= BIT(src - 1); BIT 4376 drivers/hwmon/nct6775.c data->have_temp_fixed |= BIT(src - 1); BIT 4396 drivers/hwmon/nct6775.c data->have_temp |= BIT(s); BIT 4424 drivers/hwmon/nct6775.c if (!(data->temp_mask & BIT(src))) { BIT 4437 drivers/hwmon/nct6775.c if (!(data->virt_temp_mask & BIT(src))) { BIT 4438 drivers/hwmon/nct6775.c if (mask & BIT(src)) BIT 4440 drivers/hwmon/nct6775.c mask |= BIT(src); BIT 4445 drivers/hwmon/nct6775.c if (data->have_temp & BIT(src - 1)) BIT 4447 drivers/hwmon/nct6775.c data->have_temp |= BIT(src - 1); BIT 4448 drivers/hwmon/nct6775.c data->have_temp_fixed |= BIT(src - 1); BIT 4458 drivers/hwmon/nct6775.c data->have_temp |= BIT(s); BIT 4472 drivers/hwmon/nct6775.c if (!(data->temp_mask & BIT(i + 1))) BIT 4476 drivers/hwmon/nct6775.c if (mask & BIT(i + 1)) BIT 4479 drivers/hwmon/nct6775.c if (data->have_temp & BIT(i)) BIT 4481 drivers/hwmon/nct6775.c data->have_temp |= BIT(i); BIT 4482 drivers/hwmon/nct6775.c data->have_temp_fixed |= BIT(i); BIT 4495 drivers/hwmon/nct6775.c data->have_temp |= BIT(s); BIT 4672 drivers/hwmon/nct6775.c if (!(data->have_in & BIT(i))) BIT 4682 drivers/hwmon/nct6775.c if (!(data->has_fan_min & BIT(i))) BIT 4690 drivers/hwmon/nct6775.c if (!(data->have_temp & BIT(i))) BIT 89 drivers/hwmon/nct7904.c #define ENABLE_TSI BIT(1) BIT 338 drivers/hwmon/nct7904.c if (channel > 0 && (data->vsen_mask & BIT(index))) BIT 343 drivers/hwmon/nct7904.c if (channel > 0 && (data->vsen_mask & BIT(index))) BIT 479 drivers/hwmon/nct7904.c if (data->tcpu_mask & BIT(channel)) BIT 482 drivers/hwmon/nct7904.c if (data->has_dts & BIT(channel - 5)) BIT 491 drivers/hwmon/nct7904.c if (data->tcpu_mask & BIT(channel)) BIT 494 drivers/hwmon/nct7904.c if (data->has_dts & BIT(channel - 5)) BIT 33 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3) BIT 34 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11) BIT 35 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15) BIT 36 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19) BIT 38 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2) BIT 39 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10) BIT 40 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14) BIT 41 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18) BIT 43 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0) BIT 44 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8) BIT 45 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12) BIT 46 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16) BIT 99 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0) BIT 100 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3) BIT 102 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TMCTRL_TBEN BIT(6) BIT 103 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TMCTRL_TAEN BIT(5) BIT 104 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4) BIT 105 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3) BIT 106 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2) BIT 109 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICLR_TFCLR BIT(5) BIT 110 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICLR_TECLR BIT(4) BIT 111 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICLR_TDCLR BIT(3) BIT 112 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICLR_TCCLR BIT(2) BIT 113 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICLR_TBCLR BIT(1) BIT 114 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICLR_TACLR BIT(0) BIT 117 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TIEN_TFIEN BIT(5) BIT 118 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TIEN_TEIEN BIT(4) BIT 119 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TIEN_TDIEN BIT(3) BIT 120 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TIEN_TCIEN BIT(2) BIT 121 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TIEN_TBIEN BIT(1) BIT 122 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TIEN_TAIEN BIT(0) BIT 124 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICTRL_TFPND BIT(5) BIT 125 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICTRL_TEPND BIT(4) BIT 126 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICTRL_TDPND BIT(3) BIT 127 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICTRL_TCPND BIT(2) BIT 128 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICTRL_TBPND BIT(1) BIT 129 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICTRL_TAPND BIT(0) BIT 131 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7) BIT 132 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6) BIT 133 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5) BIT 134 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4) BIT 135 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3) BIT 136 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2) BIT 137 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1) BIT 138 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0) BIT 83 drivers/hwmon/nsa320-hwmon.c for (mask = BIT(31); mask; mask >>= 1) { BIT 18 drivers/hwmon/occ/common.c #define EXTN_FLAG_SENSOR_ID BIT(7) BIT 14 drivers/hwmon/occ/sysfs.c #define OCC_STAT_MASTER BIT(7) BIT 15 drivers/hwmon/occ/sysfs.c #define OCC_STAT_ACTIVE BIT(0) BIT 18 drivers/hwmon/occ/sysfs.c #define OCC_EXT_STAT_DVFS_OT BIT(7) BIT 19 drivers/hwmon/occ/sysfs.c #define OCC_EXT_STAT_DVFS_POWER BIT(6) BIT 20 drivers/hwmon/occ/sysfs.c #define OCC_EXT_STAT_MEM_THROTTLE BIT(5) BIT 21 drivers/hwmon/occ/sysfs.c #define OCC_EXT_STAT_QUICK_DROP BIT(4) BIT 23 drivers/hwmon/pmbus/adm1275.c #define ADM1275_MFR_STATUS_IOUT_WARN2 BIT(0) BIT 24 drivers/hwmon/pmbus/adm1275.c #define ADM1293_MFR_STATUS_VAUX_UV_WARN BIT(5) BIT 25 drivers/hwmon/pmbus/adm1275.c #define ADM1293_MFR_STATUS_VAUX_OV_WARN BIT(6) BIT 32 drivers/hwmon/pmbus/adm1275.c #define ADM1275_VIN_VOUT_SELECT BIT(6) BIT 33 drivers/hwmon/pmbus/adm1275.c #define ADM1275_VRANGE BIT(5) BIT 34 drivers/hwmon/pmbus/adm1275.c #define ADM1075_IRANGE_50 BIT(4) BIT 35 drivers/hwmon/pmbus/adm1275.c #define ADM1075_IRANGE_25 BIT(3) BIT 36 drivers/hwmon/pmbus/adm1275.c #define ADM1075_IRANGE_MASK (BIT(3) | BIT(4)) BIT 38 drivers/hwmon/pmbus/adm1275.c #define ADM1272_IRANGE BIT(0) BIT 40 drivers/hwmon/pmbus/adm1275.c #define ADM1278_TEMP1_EN BIT(3) BIT 41 drivers/hwmon/pmbus/adm1275.c #define ADM1278_VIN_EN BIT(2) BIT 42 drivers/hwmon/pmbus/adm1275.c #define ADM1278_VOUT_EN BIT(1) BIT 45 drivers/hwmon/pmbus/adm1275.c #define ADM1293_IRANGE_50 BIT(6) BIT 46 drivers/hwmon/pmbus/adm1275.c #define ADM1293_IRANGE_100 BIT(7) BIT 47 drivers/hwmon/pmbus/adm1275.c #define ADM1293_IRANGE_200 (BIT(6) | BIT(7)) BIT 48 drivers/hwmon/pmbus/adm1275.c #define ADM1293_IRANGE_MASK (BIT(6) | BIT(7)) BIT 50 drivers/hwmon/pmbus/adm1275.c #define ADM1293_VIN_SEL_012 BIT(2) BIT 51 drivers/hwmon/pmbus/adm1275.c #define ADM1293_VIN_SEL_074 BIT(3) BIT 52 drivers/hwmon/pmbus/adm1275.c #define ADM1293_VIN_SEL_210 (BIT(2) | BIT(3)) BIT 53 drivers/hwmon/pmbus/adm1275.c #define ADM1293_VIN_SEL_MASK (BIT(2) | BIT(3)) BIT 55 drivers/hwmon/pmbus/adm1275.c #define ADM1293_VAUX_EN BIT(1) BIT 61 drivers/hwmon/pmbus/adm1275.c #define ADM1275_IOUT_WARN2_SELECT BIT(4) BIT 71 drivers/hwmon/pmbus/adm1275.c #define ADM1075_VAUX_OV_WARN BIT(7) BIT 72 drivers/hwmon/pmbus/adm1275.c #define ADM1075_VAUX_UV_WARN BIT(6) BIT 313 drivers/hwmon/pmbus/adm1275.c ret = BIT(ret); BIT 320 drivers/hwmon/pmbus/adm1275.c ret = BIT(ret); BIT 33 drivers/hwmon/pmbus/ibm-cffps.c #define CFFPS_MFR_FAN_FAULT BIT(0) BIT 34 drivers/hwmon/pmbus/ibm-cffps.c #define CFFPS_MFR_THERMAL_FAULT BIT(1) BIT 35 drivers/hwmon/pmbus/ibm-cffps.c #define CFFPS_MFR_OV_FAULT BIT(2) BIT 36 drivers/hwmon/pmbus/ibm-cffps.c #define CFFPS_MFR_UV_FAULT BIT(3) BIT 37 drivers/hwmon/pmbus/ibm-cffps.c #define CFFPS_MFR_PS_KILL BIT(4) BIT 38 drivers/hwmon/pmbus/ibm-cffps.c #define CFFPS_MFR_OC_FAULT BIT(5) BIT 39 drivers/hwmon/pmbus/ibm-cffps.c #define CFFPS_MFR_VAUX_FAULT BIT(6) BIT 40 drivers/hwmon/pmbus/ibm-cffps.c #define CFFPS_MFR_CURRENT_SHARE_WARNING BIT(7) BIT 47 drivers/hwmon/pmbus/ibm-cffps.c #define CFFPS_LED_BLINK BIT(0) BIT 48 drivers/hwmon/pmbus/ibm-cffps.c #define CFFPS_LED_ON BIT(1) BIT 35 drivers/hwmon/pmbus/lm25066.c #define LM25066_DEV_SETUP_CL BIT(4) /* Current limit */ BIT 44 drivers/hwmon/pmbus/lm25066.c #define LM25056_MFR_STS_VAUX_OV_WARN BIT(1) BIT 45 drivers/hwmon/pmbus/lm25066.c #define LM25056_MFR_STS_VAUX_UV_WARN BIT(0) BIT 85 drivers/hwmon/pmbus/ltc2978.c #define LTC_NOT_BUSY BIT(6) BIT 86 drivers/hwmon/pmbus/ltc2978.c #define LTC_NOT_PENDING BIT(5) BIT 110 drivers/hwmon/pmbus/ltc2978.c #define FEAT_CLEAR_PEAKS BIT(0) BIT 111 drivers/hwmon/pmbus/ltc2978.c #define FEAT_NEEDS_POLLING BIT(1) BIT 21 drivers/hwmon/pmbus/max31785.c #define MFR_FAN_CONFIG_DUAL_TACH BIT(12) BIT 29 drivers/hwmon/pmbus/max34440.c #define MAX34440_STATUS_OC_WARN BIT(0) BIT 30 drivers/hwmon/pmbus/max34440.c #define MAX34440_STATUS_OC_FAULT BIT(1) BIT 31 drivers/hwmon/pmbus/max34440.c #define MAX34440_STATUS_OT_FAULT BIT(5) BIT 32 drivers/hwmon/pmbus/max34440.c #define MAX34440_STATUS_OT_WARN BIT(6) BIT 21 drivers/hwmon/pmbus/max8688.c #define MAX8688_STATUS_OC_FAULT BIT(4) BIT 22 drivers/hwmon/pmbus/max8688.c #define MAX8688_STATUS_OV_FAULT BIT(5) BIT 23 drivers/hwmon/pmbus/max8688.c #define MAX8688_STATUS_OV_WARNING BIT(8) BIT 24 drivers/hwmon/pmbus/max8688.c #define MAX8688_STATUS_UV_FAULT BIT(9) BIT 25 drivers/hwmon/pmbus/max8688.c #define MAX8688_STATUS_UV_WARNING BIT(10) BIT 26 drivers/hwmon/pmbus/max8688.c #define MAX8688_STATUS_UC_FAULT BIT(11) BIT 27 drivers/hwmon/pmbus/max8688.c #define MAX8688_STATUS_OC_WARNING BIT(12) BIT 28 drivers/hwmon/pmbus/max8688.c #define MAX8688_STATUS_OT_FAULT BIT(13) BIT 29 drivers/hwmon/pmbus/max8688.c #define MAX8688_STATUS_OT_WARNING BIT(14) BIT 226 drivers/hwmon/pmbus/pmbus.h #define PB_OPERATION_CONTROL_ON BIT(7) BIT 231 drivers/hwmon/pmbus/pmbus.h #define PB_CAPABILITY_SMBALERT BIT(4) BIT 232 drivers/hwmon/pmbus/pmbus.h #define PB_CAPABILITY_ERROR_CHECK BIT(7) BIT 247 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_2_PULSE_MASK (BIT(0) | BIT(1)) BIT 248 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_2_RPM BIT(2) BIT 249 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_2_INSTALLED BIT(3) BIT 250 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_1_PULSE_MASK (BIT(4) | BIT(5)) BIT 251 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_1_RPM BIT(6) BIT 252 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_1_INSTALLED BIT(7) BIT 259 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_NONE_ABOVE BIT(0) BIT 260 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_CML BIT(1) BIT 261 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_TEMPERATURE BIT(2) BIT 262 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_VIN_UV BIT(3) BIT 263 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_IOUT_OC BIT(4) BIT 264 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_VOUT_OV BIT(5) BIT 265 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_OFF BIT(6) BIT 266 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_BUSY BIT(7) BIT 271 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_UNKNOWN BIT(8) BIT 272 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_OTHER BIT(9) BIT 273 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_FANS BIT(10) BIT 274 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_POWER_GOOD_N BIT(11) BIT 275 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_WORD_MFR BIT(12) BIT 276 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_INPUT BIT(13) BIT 277 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_IOUT_POUT BIT(14) BIT 278 drivers/hwmon/pmbus/pmbus.h #define PB_STATUS_VOUT BIT(15) BIT 283 drivers/hwmon/pmbus/pmbus.h #define PB_POUT_OP_WARNING BIT(0) BIT 284 drivers/hwmon/pmbus/pmbus.h #define PB_POUT_OP_FAULT BIT(1) BIT 285 drivers/hwmon/pmbus/pmbus.h #define PB_POWER_LIMITING BIT(2) BIT 286 drivers/hwmon/pmbus/pmbus.h #define PB_CURRENT_SHARE_FAULT BIT(3) BIT 287 drivers/hwmon/pmbus/pmbus.h #define PB_IOUT_UC_FAULT BIT(4) BIT 288 drivers/hwmon/pmbus/pmbus.h #define PB_IOUT_OC_WARNING BIT(5) BIT 289 drivers/hwmon/pmbus/pmbus.h #define PB_IOUT_OC_LV_FAULT BIT(6) BIT 290 drivers/hwmon/pmbus/pmbus.h #define PB_IOUT_OC_FAULT BIT(7) BIT 295 drivers/hwmon/pmbus/pmbus.h #define PB_VOLTAGE_UV_FAULT BIT(4) BIT 296 drivers/hwmon/pmbus/pmbus.h #define PB_VOLTAGE_UV_WARNING BIT(5) BIT 297 drivers/hwmon/pmbus/pmbus.h #define PB_VOLTAGE_OV_WARNING BIT(6) BIT 298 drivers/hwmon/pmbus/pmbus.h #define PB_VOLTAGE_OV_FAULT BIT(7) BIT 303 drivers/hwmon/pmbus/pmbus.h #define PB_PIN_OP_WARNING BIT(0) BIT 304 drivers/hwmon/pmbus/pmbus.h #define PB_IIN_OC_WARNING BIT(1) BIT 305 drivers/hwmon/pmbus/pmbus.h #define PB_IIN_OC_FAULT BIT(2) BIT 310 drivers/hwmon/pmbus/pmbus.h #define PB_TEMP_UT_FAULT BIT(4) BIT 311 drivers/hwmon/pmbus/pmbus.h #define PB_TEMP_UT_WARNING BIT(5) BIT 312 drivers/hwmon/pmbus/pmbus.h #define PB_TEMP_OT_WARNING BIT(6) BIT 313 drivers/hwmon/pmbus/pmbus.h #define PB_TEMP_OT_FAULT BIT(7) BIT 318 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_AIRFLOW_WARNING BIT(0) BIT 319 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_AIRFLOW_FAULT BIT(1) BIT 320 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_FAN2_SPEED_OVERRIDE BIT(2) BIT 321 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_FAN1_SPEED_OVERRIDE BIT(3) BIT 322 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_FAN2_WARNING BIT(4) BIT 323 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_FAN1_WARNING BIT(5) BIT 324 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_FAN2_FAULT BIT(6) BIT 325 drivers/hwmon/pmbus/pmbus.h #define PB_FAN_FAN1_FAULT BIT(7) BIT 330 drivers/hwmon/pmbus/pmbus.h #define PB_CML_FAULT_OTHER_MEM_LOGIC BIT(0) BIT 331 drivers/hwmon/pmbus/pmbus.h #define PB_CML_FAULT_OTHER_COMM BIT(1) BIT 332 drivers/hwmon/pmbus/pmbus.h #define PB_CML_FAULT_PROCESSOR BIT(3) BIT 333 drivers/hwmon/pmbus/pmbus.h #define PB_CML_FAULT_MEMORY BIT(4) BIT 334 drivers/hwmon/pmbus/pmbus.h #define PB_CML_FAULT_PACKET_ERROR BIT(5) BIT 335 drivers/hwmon/pmbus/pmbus.h #define PB_CML_FAULT_INVALID_DATA BIT(6) BIT 336 drivers/hwmon/pmbus/pmbus.h #define PB_CML_FAULT_INVALID_COMMAND BIT(7) BIT 353 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_VIN BIT(0) BIT 354 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_VCAP BIT(1) BIT 355 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_VOUT BIT(2) BIT 356 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_IIN BIT(3) BIT 357 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_IOUT BIT(4) BIT 358 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_PIN BIT(5) BIT 359 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_POUT BIT(6) BIT 360 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_FAN12 BIT(7) BIT 361 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_FAN34 BIT(8) BIT 362 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_TEMP BIT(9) BIT 363 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_TEMP2 BIT(10) BIT 364 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_TEMP3 BIT(11) BIT 365 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_STATUS_VOUT BIT(12) BIT 366 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_STATUS_IOUT BIT(13) BIT 367 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_STATUS_INPUT BIT(14) BIT 368 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_STATUS_TEMP BIT(15) BIT 369 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_STATUS_FAN12 BIT(16) BIT 370 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_STATUS_FAN34 BIT(17) BIT 371 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_VMON BIT(18) BIT 372 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_STATUS_VMON BIT(19) BIT 373 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_PWM12 BIT(20) BIT 374 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_PWM34 BIT(21) BIT 375 drivers/hwmon/pmbus/pmbus.h #define PMBUS_HAVE_SAMPLES BIT(22) BIT 377 drivers/hwmon/pmbus/pmbus.h #define PMBUS_PAGE_VIRTUAL BIT(31) BIT 33 drivers/hwmon/pmbus/ucd9000.c #define UCD9000_GPIO_CONFIG_ENABLE BIT(0) BIT 34 drivers/hwmon/pmbus/ucd9000.c #define UCD9000_GPIO_CONFIG_OUT_ENABLE BIT(1) BIT 35 drivers/hwmon/pmbus/ucd9000.c #define UCD9000_GPIO_CONFIG_OUT_VALUE BIT(2) BIT 36 drivers/hwmon/pmbus/ucd9000.c #define UCD9000_GPIO_CONFIG_STATUS BIT(3) BIT 385 drivers/hwmon/pmbus/ucd9000.c *val = !!(buffer[1] & BIT(entry->index)); BIT 35 drivers/hwmon/pmbus/zl6100.c #define ZL6100_MFR_XTEMP_ENABLE BIT(7) BIT 41 drivers/hwmon/pmbus/zl6100.c #define VMON_UV_WARNING BIT(5) BIT 42 drivers/hwmon/pmbus/zl6100.c #define VMON_OV_WARNING BIT(4) BIT 43 drivers/hwmon/pmbus/zl6100.c #define VMON_UV_FAULT BIT(1) BIT 44 drivers/hwmon/pmbus/zl6100.c #define VMON_OV_FAULT BIT(0) BIT 18 drivers/hwmon/raspberrypi-hwmon.c #define UNDERVOLTAGE_STICKY_BIT BIT(16) BIT 38 drivers/hwmon/stts751.c #define STTS751_STATUS_TRIPT BIT(0) BIT 39 drivers/hwmon/stts751.c #define STTS751_STATUS_TRIPL BIT(5) BIT 40 drivers/hwmon/stts751.c #define STTS751_STATUS_TRIPH BIT(6) BIT 45 drivers/hwmon/stts751.c #define STTS751_CONF_EVENT_DIS BIT(7) BIT 46 drivers/hwmon/stts751.c #define STTS751_CONF_STOP BIT(6) BIT 37 drivers/hwmon/tc654.c #define TC654_REG_CONFIG_RES BIT(6) /* Resolution Selection */ BIT 38 drivers/hwmon/tc654.c #define TC654_REG_CONFIG_DUTYC BIT(5) /* Duty Cycle Control */ BIT 39 drivers/hwmon/tc654.c #define TC654_REG_CONFIG_SDM BIT(0) /* Shutdown Mode */ BIT 42 drivers/hwmon/tc654.c #define TC654_REG_STATUS_F2F BIT(1) /* Fan 2 Fault */ BIT 43 drivers/hwmon/tc654.c #define TC654_REG_STATUS_F1F BIT(0) /* Fan 1 Fault */ BIT 279 drivers/hwmon/tc654.c val = BIT((data->config >> TC654_FAN_PULSE_SHIFT[nr]) & 0x03); BIT 58 drivers/hwmon/tc74.c if (!(value & BIT(6))) { BIT 138 drivers/hwmon/tc74.c if (conf & BIT(7)) { BIT 141 drivers/hwmon/tc74.c conf &= ~BIT(7); BIT 91 drivers/hwmon/tmp401.c #define TMP401_CONFIG_RANGE BIT(2) BIT 92 drivers/hwmon/tmp401.c #define TMP401_CONFIG_SHUTDOWN BIT(6) BIT 93 drivers/hwmon/tmp401.c #define TMP401_STATUS_LOCAL_CRIT BIT(0) BIT 94 drivers/hwmon/tmp401.c #define TMP401_STATUS_REMOTE_CRIT BIT(1) BIT 95 drivers/hwmon/tmp401.c #define TMP401_STATUS_REMOTE_OPEN BIT(2) BIT 96 drivers/hwmon/tmp401.c #define TMP401_STATUS_REMOTE_LOW BIT(3) BIT 97 drivers/hwmon/tmp401.c #define TMP401_STATUS_REMOTE_HIGH BIT(4) BIT 98 drivers/hwmon/tmp401.c #define TMP401_STATUS_LOCAL_LOW BIT(5) BIT 99 drivers/hwmon/tmp401.c #define TMP401_STATUS_LOCAL_HIGH BIT(6) BIT 102 drivers/hwmon/tmp401.c #define TMP432_STATUS_LOCAL BIT(0) BIT 103 drivers/hwmon/tmp401.c #define TMP432_STATUS_REMOTE1 BIT(1) BIT 104 drivers/hwmon/tmp401.c #define TMP432_STATUS_REMOTE2 BIT(2) BIT 49 drivers/hwmon/xgene-hwmon.c #define SENSOR_INVALID_DATA BIT(15) BIT 62 drivers/hwmon/xgene-hwmon.c #define PCCC_GENERATE_DB_INT BIT(15) BIT 63 drivers/hwmon/xgene-hwmon.c #define PCCS_CMD_COMPLETE BIT(0) BIT 64 drivers/hwmon/xgene-hwmon.c #define PCCS_SCI_DOORBEL BIT(1) BIT 65 drivers/hwmon/xgene-hwmon.c #define PCCS_PLATFORM_NOTIFICATION BIT(3) BIT 19 drivers/hwspinlock/stm32_hwspinlock.c #define STM32_MUTEX_COREID BIT(8) BIT 20 drivers/hwspinlock/stm32_hwspinlock.c #define STM32_MUTEX_LOCK_BIT BIT(31) BIT 419 drivers/hwtracing/coresight/coresight-catu.c if (control & BIT(CATU_CONTROL_ENABLE)) { BIT 428 drivers/hwtracing/coresight/coresight-catu.c control |= BIT(CATU_CONTROL_ENABLE); BIT 41 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDPCSR_THUMB BIT(0) BIT 46 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDPRCR_COREPURQ BIT(3) BIT 47 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDPRCR_CORENPDRQ BIT(0) BIT 50 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDPRSR_DLK BIT(6) BIT 51 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDPRSR_PU BIT(0) BIT 54 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDVIDSR_NS BIT(31) BIT 55 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDVIDSR_E2 BIT(30) BIT 56 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDVIDSR_E3 BIT(29) BIT 57 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDVIDSR_HV BIT(28) BIT 275 drivers/hwtracing/coresight/coresight-cpu-debug.c if (pc & BIT(1)) BIT 53 drivers/hwtracing/coresight/coresight-etb10.c #define ETB_STATUS_RAM_FULL BIT(0) BIT 55 drivers/hwtracing/coresight/coresight-etb10.c #define ETB_CTL_CAPT_EN BIT(0) BIT 57 drivers/hwtracing/coresight/coresight-etb10.c #define ETB_FFCR_EN_FTC BIT(0) BIT 58 drivers/hwtracing/coresight/coresight-etb10.c #define ETB_FFCR_FON_MAN BIT(6) BIT 59 drivers/hwtracing/coresight/coresight-etb10.c #define ETB_FFCR_STOP_FI BIT(12) BIT 60 drivers/hwtracing/coresight/coresight-etb10.c #define ETB_FFCR_STOP_TRIGGER BIT(13) BIT 83 drivers/hwtracing/coresight/coresight-etm.h #define ETMCR_PWD_DWN BIT(0) BIT 84 drivers/hwtracing/coresight/coresight-etm.h #define ETMCR_STALL_MODE BIT(7) BIT 85 drivers/hwtracing/coresight/coresight-etm.h #define ETMCR_BRANCH_BROADCAST BIT(8) BIT 86 drivers/hwtracing/coresight/coresight-etm.h #define ETMCR_ETM_PRG BIT(10) BIT 87 drivers/hwtracing/coresight/coresight-etm.h #define ETMCR_ETM_EN BIT(11) BIT 88 drivers/hwtracing/coresight/coresight-etm.h #define ETMCR_CYC_ACC BIT(12) BIT 89 drivers/hwtracing/coresight/coresight-etm.h #define ETMCR_CTXID_SIZE (BIT(14)|BIT(15)) BIT 90 drivers/hwtracing/coresight/coresight-etm.h #define ETMCR_TIMESTAMP_EN BIT(28) BIT 91 drivers/hwtracing/coresight/coresight-etm.h #define ETMCR_RETURN_STACK BIT(29) BIT 93 drivers/hwtracing/coresight/coresight-etm.h #define ETMCCR_FIFOFULL BIT(23) BIT 95 drivers/hwtracing/coresight/coresight-etm.h #define ETMPDCR_PWD_UP BIT(3) BIT 97 drivers/hwtracing/coresight/coresight-etm.h #define ETMTECR1_ADDR_COMP_1 BIT(0) BIT 98 drivers/hwtracing/coresight/coresight-etm.h #define ETMTECR1_INC_EXC BIT(24) BIT 99 drivers/hwtracing/coresight/coresight-etm.h #define ETMTECR1_START_STOP BIT(25) BIT 101 drivers/hwtracing/coresight/coresight-etm.h #define ETMCCER_TIMESTAMP BIT(22) BIT 102 drivers/hwtracing/coresight/coresight-etm.h #define ETMCCER_RETSTACK BIT(23) BIT 104 drivers/hwtracing/coresight/coresight-etm.h #define ETM_MODE_EXCLUDE BIT(0) BIT 105 drivers/hwtracing/coresight/coresight-etm.h #define ETM_MODE_CYCACC BIT(1) BIT 106 drivers/hwtracing/coresight/coresight-etm.h #define ETM_MODE_STALL BIT(2) BIT 107 drivers/hwtracing/coresight/coresight-etm.h #define ETM_MODE_TIMESTAMP BIT(3) BIT 108 drivers/hwtracing/coresight/coresight-etm.h #define ETM_MODE_CTXID BIT(4) BIT 109 drivers/hwtracing/coresight/coresight-etm.h #define ETM_MODE_BBROAD BIT(5) BIT 110 drivers/hwtracing/coresight/coresight-etm.h #define ETM_MODE_RET_STACK BIT(6) BIT 137 drivers/hwtracing/coresight/coresight-etm.h #define ETM_EVENT_NOT_A BIT(14) /* NOT(A) */ BIT 477 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c config->enable_ctrl1 |= BIT(25); BIT 134 drivers/hwtracing/coresight/coresight-etm3x.c if (val & BIT(position)) BIT 138 drivers/hwtracing/coresight/coresight-etm3x.c if (!(val & BIT(position))) BIT 209 drivers/hwtracing/coresight/coresight-etm3x.c config->enable_ctrl1 = BIT(24); BIT 42 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->viiectlr |= BIT(idx / 2 + 16); BIT 43 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->viiectlr &= ~BIT(idx / 2); BIT 49 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->viiectlr |= BIT(idx / 2); BIT 50 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->viiectlr &= ~BIT(idx / 2 + 16); BIT 182 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~(BIT(1) | BIT(2)); BIT 187 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~(BIT(16) | BIT(17)); BIT 208 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl |= BIT(0); BIT 212 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl |= BIT(9); BIT 304 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~(BIT(1) | BIT(2)); BIT 307 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(1); BIT 310 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(2); BIT 316 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(1) | BIT(2); BIT 321 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(3); BIT 323 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~BIT(3); BIT 328 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(4); BIT 330 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~BIT(4); BIT 334 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(6); BIT 336 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~BIT(6); BIT 339 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(7); BIT 341 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~BIT(7); BIT 346 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~(BIT(8) | BIT(9) | BIT(10)); BIT 352 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(11); BIT 354 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~BIT(11); BIT 359 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(12); BIT 361 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~BIT(12); BIT 366 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg &= ~(BIT(13) | BIT(14)); BIT 368 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if ((mode & BIT(0)) && (drvdata->q_support & BIT(0))) BIT 369 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(13); BIT 374 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if ((mode & BIT(1)) && (drvdata->q_support & BIT(1))) BIT 375 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->cfg |= BIT(14); BIT 380 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 |= BIT(11); BIT 382 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 &= ~BIT(11); BIT 387 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 |= BIT(12); BIT 389 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 &= ~BIT(12); BIT 393 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->stall_ctrl |= BIT(8); BIT 395 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->stall_ctrl &= ~BIT(8); BIT 399 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->stall_ctrl |= BIT(10); BIT 401 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->stall_ctrl &= ~BIT(10); BIT 406 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->stall_ctrl |= BIT(13); BIT 408 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->stall_ctrl &= ~BIT(13); BIT 412 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl |= BIT(9); BIT 414 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl &= ~BIT(9); BIT 418 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl |= BIT(10); BIT 420 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl &= ~BIT(10); BIT 425 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl |= BIT(11); BIT 427 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl &= ~BIT(11); BIT 547 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 &= ~(BIT(0) | BIT(1) | BIT(2) | BIT(3)); BIT 551 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 |= val & BIT(1); BIT 555 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 |= val & (BIT(0) | BIT(1)); BIT 559 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->eventctrl1 |= val & (BIT(0) | BIT(1) | BIT(2)); BIT 698 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0)) BIT 763 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19)); BIT 798 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22)); BIT 882 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_acc[idx] &= ~(BIT(0) | BIT(1)); BIT 1061 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vissctlr |= BIT(idx); BIT 1063 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl |= BIT(9); BIT 1118 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vissctlr |= BIT(idx + 16); BIT 1120 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->vinst_ctrl |= BIT(9); BIT 1164 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_acc[idx] &= ~(BIT(2) | BIT(3)); BIT 1168 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_acc[idx] |= BIT(2); BIT 1169 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_acc[idx] &= ~BIT(3); BIT 1174 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_acc[idx] &= ~BIT(2); BIT 1175 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_acc[idx] |= BIT(3); BIT 1183 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_acc[idx] |= BIT(2); BIT 1185 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_acc[idx] |= BIT(3); BIT 1229 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c config->addr_acc[idx] &= ~(BIT(4) | BIT(5) | BIT(6)); BIT 1587 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c val &= ~BIT(21); BIT 331 drivers/hwtracing/coresight/coresight-etm4x.c if (attr->config & BIT(ETM_OPT_CYCACC)) { BIT 332 drivers/hwtracing/coresight/coresight-etm4x.c config->cfg |= BIT(4); BIT 336 drivers/hwtracing/coresight/coresight-etm4x.c if (attr->config & BIT(ETM_OPT_TS)) { BIT 352 drivers/hwtracing/coresight/coresight-etm4x.c config->cfg |= BIT(11); BIT 355 drivers/hwtracing/coresight/coresight-etm4x.c if (attr->config & BIT(ETM_OPT_CTXTID)) BIT 357 drivers/hwtracing/coresight/coresight-etm4x.c config->cfg |= BIT(ETM4_CFG_BIT_CTXTID); BIT 360 drivers/hwtracing/coresight/coresight-etm4x.c if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) BIT 362 drivers/hwtracing/coresight/coresight-etm4x.c config->cfg |= BIT(12); BIT 501 drivers/hwtracing/coresight/coresight-etm4x.c filters->ssstatus = (control & BIT(9)); BIT 750 drivers/hwtracing/coresight/coresight-etm4x.c config->vinst_ctrl |= BIT(0); BIT 825 drivers/hwtracing/coresight/coresight-etm4x.c config->viiectlr |= BIT(comparator / 2); BIT 846 drivers/hwtracing/coresight/coresight-etm4x.c config->vissctlr |= BIT(shift + comparator); BIT 867 drivers/hwtracing/coresight/coresight-etm4x.c config->vinst_ctrl |= BIT(9); BIT 972 drivers/hwtracing/coresight/coresight-etm4x.c config->vinst_ctrl |= BIT(9); BIT 1000 drivers/hwtracing/coresight/coresight-etm4x.c config->vinst_ctrl |= BIT(9); BIT 148 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_EXCLUDE BIT(0) BIT 149 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_LOAD BIT(1) BIT 150 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_STORE BIT(2) BIT 151 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_LOAD_STORE BIT(3) BIT 152 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_BB BIT(4) BIT 153 drivers/hwtracing/coresight/coresight-etm4x.h #define ETMv4_MODE_CYCACC BIT(5) BIT 154 drivers/hwtracing/coresight/coresight-etm4x.h #define ETMv4_MODE_CTXID BIT(6) BIT 155 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_VMID BIT(7) BIT 157 drivers/hwtracing/coresight/coresight-etm4x.h #define ETMv4_MODE_TIMESTAMP BIT(11) BIT 158 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_RETURNSTACK BIT(12) BIT 160 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_DATA_TRACE_ADDR BIT(15) BIT 161 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_DATA_TRACE_VAL BIT(16) BIT 162 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_ISTALL BIT(17) BIT 163 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_DSTALL BIT(18) BIT 164 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_ATB_TRIGGER BIT(19) BIT 165 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_LPOVERRIDE BIT(20) BIT 166 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_ISTALL_EN BIT(21) BIT 167 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_DSTALL_EN BIT(22) BIT 168 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_INSTPRIO BIT(23) BIT 169 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_NOOVERFLOW BIT(24) BIT 170 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_TRACE_RESET BIT(25) BIT 171 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_TRACE_ERR BIT(26) BIT 172 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_MODE_VIEWINST_STARTSTOP BIT(27) BIT 181 drivers/hwtracing/coresight/coresight-etm4x.h #define TRCPDCR_PU BIT(3) BIT 184 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_EXLEVEL_S_APP BIT(8) BIT 185 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_EXLEVEL_S_OS BIT(9) BIT 186 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_EXLEVEL_S_NA BIT(10) BIT 187 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_EXLEVEL_S_HYP BIT(11) BIT 189 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_EXLEVEL_NS_APP BIT(12) BIT 190 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_EXLEVEL_NS_OS BIT(13) BIT 191 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_EXLEVEL_NS_HYP BIT(14) BIT 192 drivers/hwtracing/coresight/coresight-etm4x.h #define ETM_EXLEVEL_NS_NA BIT(15) BIT 34 drivers/hwtracing/coresight/coresight-priv.h #define CORESIGHT_CLAIM_SELF_HOSTED BIT(1) BIT 39 drivers/hwtracing/coresight/coresight-priv.h #define ETM_MODE_EXCL_KERN BIT(30) BIT 40 drivers/hwtracing/coresight/coresight-priv.h #define ETM_MODE_EXCL_USER BIT(31) BIT 51 drivers/hwtracing/coresight/coresight-tmc.c ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT); BIT 46 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_CTL_CAPT_EN BIT(0) BIT 49 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_STS_FULL BIT(0) BIT 50 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_STS_TRIGGERED BIT(1) BIT 51 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_STS_MEMERR BIT(5) BIT 70 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_AXICTL_PROT_CTL_B0 BIT(0) BIT 71 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_AXICTL_PROT_CTL_B1 BIT(1) BIT 72 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_AXICTL_SCT_GAT_MODE BIT(7) BIT 80 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_FFCR_EN_FMT BIT(0) BIT 81 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_FFCR_EN_TI BIT(1) BIT 82 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_FFCR_FON_FLIN BIT(4) BIT 83 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_FFCR_FON_TRIG_EVT BIT(5) BIT 84 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_FFCR_TRIGON_TRIGIN BIT(8) BIT 85 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_FFCR_STOP_ON_FLUSH BIT(12) BIT 88 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_DEVID_NOSCAT BIT(24) BIT 90 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_DEVID_AXIAW_VALID BIT(16) BIT 47 drivers/hwtracing/coresight/coresight-tpiu.c #define FFCR_FON_MAN BIT(6) BIT 48 drivers/hwtracing/coresight/coresight-tpiu.c #define FFCR_STOP_FI BIT(12) BIT 1125 drivers/hwtracing/coresight/coresight.c if (val & BIT(position)) BIT 1129 drivers/hwtracing/coresight/coresight.c if (!(val & BIT(position))) BIT 243 drivers/hwtracing/intel_th/gth.c OUTPUT_PARM(null, BIT(3), 1, 1, output), BIT 244 drivers/hwtracing/intel_th/gth.c OUTPUT_PARM(drop, BIT(4), 1, 1, output), BIT 245 drivers/hwtracing/intel_th/gth.c OUTPUT_PARM(reset, BIT(5), 1, 0, output), BIT 246 drivers/hwtracing/intel_th/gth.c OUTPUT_PARM(flush, BIT(7), 0, 1, output), BIT 490 drivers/hwtracing/intel_th/gth.c count && !(reg & BIT(output->port)); count--) { BIT 622 drivers/hwtracing/intel_th/gth.c count && !(reg & BIT(4)); count--) { BIT 63 drivers/hwtracing/intel_th/gth.h #define TSUCTRL_CTCRESYNC BIT(0) BIT 64 drivers/hwtracing/intel_th/gth.h #define TSCUSTAT_CTCSYNCING BIT(1) BIT 69 drivers/hwtracing/intel_th/gth.h #define CTS_EVENT_ENABLE_IF_ANYTHING BIT(31) BIT 73 drivers/hwtracing/intel_th/gth.h #define CTS_ACTION_CONTROL_TRIGGER BIT(4) BIT 77 drivers/hwtracing/intel_th/gth.h #define CTS_CTL_SEQUENCER_ENABLE BIT(0) BIT 346 drivers/hwtracing/intel_th/intel_th.h SCRPD_MEM_IS_PRIM_DEST = BIT(0), BIT 348 drivers/hwtracing/intel_th/intel_th.h SCRPD_DBC_IS_PRIM_DEST = BIT(1), BIT 350 drivers/hwtracing/intel_th/intel_th.h SCRPD_PTI_IS_PRIM_DEST = BIT(2), BIT 352 drivers/hwtracing/intel_th/intel_th.h SCRPD_BSSB_IS_PRIM_DEST = BIT(3), BIT 354 drivers/hwtracing/intel_th/intel_th.h SCRPD_PTI_IS_ALT_DEST = BIT(4), BIT 356 drivers/hwtracing/intel_th/intel_th.h SCRPD_BSSB_IS_ALT_DEST = BIT(5), BIT 358 drivers/hwtracing/intel_th/intel_th.h SCRPD_DEEPSX_EXIT = BIT(6), BIT 360 drivers/hwtracing/intel_th/intel_th.h SCRPD_S4_EXIT = BIT(7), BIT 362 drivers/hwtracing/intel_th/intel_th.h SCRPD_S5_EXIT = BIT(8), BIT 364 drivers/hwtracing/intel_th/intel_th.h SCRPD_MSC0_IS_ENABLED = BIT(9), BIT 365 drivers/hwtracing/intel_th/intel_th.h SCRPD_MSC1_IS_ENABLED = BIT(10), BIT 367 drivers/hwtracing/intel_th/intel_th.h SCRPD_SX_EXIT = BIT(11), BIT 369 drivers/hwtracing/intel_th/intel_th.h SCRPD_TRIGGER_IS_ENABLED = BIT(12), BIT 370 drivers/hwtracing/intel_th/intel_th.h SCRPD_ODLA_IS_ENABLED = BIT(13), BIT 371 drivers/hwtracing/intel_th/intel_th.h SCRPD_SOCHAP_IS_ENABLED = BIT(14), BIT 372 drivers/hwtracing/intel_th/intel_th.h SCRPD_STH_IS_ENABLED = BIT(15), BIT 373 drivers/hwtracing/intel_th/intel_th.h SCRPD_DCIH_IS_ENABLED = BIT(16), BIT 374 drivers/hwtracing/intel_th/intel_th.h SCRPD_VER_IS_ENABLED = BIT(17), BIT 376 drivers/hwtracing/intel_th/intel_th.h SCRPD_DEBUGGER_IN_USE = BIT(24), BIT 31 drivers/hwtracing/intel_th/msu.h #define MSUSTS_MSU_INT BIT(0) BIT 32 drivers/hwtracing/intel_th/msu.h #define MSUSTS_MSC0BLAST BIT(16) BIT 33 drivers/hwtracing/intel_th/msu.h #define MSUSTS_MSC1BLAST BIT(24) BIT 36 drivers/hwtracing/intel_th/msu.h #define MSC_EN BIT(0) BIT 37 drivers/hwtracing/intel_th/msu.h #define MSC_WRAPEN BIT(1) BIT 38 drivers/hwtracing/intel_th/msu.h #define MSC_RD_HDR_OVRD BIT(2) BIT 39 drivers/hwtracing/intel_th/msu.h #define MSC_MODE (BIT(4) | BIT(5)) BIT 40 drivers/hwtracing/intel_th/msu.h #define MSC_LEN (BIT(8) | BIT(9) | BIT(10)) BIT 43 drivers/hwtracing/intel_th/msu.h #define MICDE BIT(0) BIT 44 drivers/hwtracing/intel_th/msu.h #define M0BLIE BIT(16) BIT 45 drivers/hwtracing/intel_th/msu.h #define M1BLIE BIT(24) BIT 48 drivers/hwtracing/intel_th/msu.h #define MSCSTS_WRAPSTAT BIT(1) /* Wrap occurred */ BIT 49 drivers/hwtracing/intel_th/msu.h #define MSCSTS_PLE BIT(2) /* Pipeline Empty */ BIT 71 drivers/hwtracing/intel_th/msu.h #define MSC_SW_TAG_LASTBLK BIT(0) BIT 72 drivers/hwtracing/intel_th/msu.h #define MSC_SW_TAG_LASTWIN BIT(1) BIT 75 drivers/hwtracing/intel_th/msu.h #define MSC_HW_TAG_TRIGGER BIT(0) BIT 76 drivers/hwtracing/intel_th/msu.h #define MSC_HW_TAG_BLOCKWRAP BIT(1) BIT 77 drivers/hwtracing/intel_th/msu.h #define MSC_HW_TAG_WINWRAP BIT(2) BIT 78 drivers/hwtracing/intel_th/msu.h #define MSC_HW_TAG_ENDBIT BIT(3) BIT 26 drivers/hwtracing/intel_th/pci.c #define BAR_MASK (BIT(TH_PCI_CONFIG_BAR) | BIT(TH_PCI_STH_SW_BAR)) BIT 29 drivers/hwtracing/intel_th/pci.c #define NPKDSC_TSACT BIT(5) BIT 258 drivers/hwtracing/intel_th/pti.c if (!(pti->lpp_dest_mask & BIT(i))) BIT 281 drivers/hwtracing/intel_th/pti.c if (!(pti->lpp_dest_mask & BIT(i))) BIT 15 drivers/hwtracing/intel_th/pti.h #define PTI_EN BIT(0) BIT 16 drivers/hwtracing/intel_th/pti.h #define PTI_FCEN BIT(1) BIT 18 drivers/hwtracing/intel_th/pti.h #define LPP_PTIPRESENT BIT(8) BIT 19 drivers/hwtracing/intel_th/pti.h #define LPP_BSSBPRESENT BIT(9) BIT 22 drivers/hwtracing/intel_th/pti.h #define LPP_DEST BIT(25) BIT 23 drivers/hwtracing/intel_th/pti.h #define LPP_BSSBACT BIT(30) BIT 24 drivers/hwtracing/intel_th/pti.h #define LPP_LPPBUSY BIT(31) BIT 26 drivers/hwtracing/intel_th/pti.h #define LPP_DEST_PTI BIT(0) BIT 27 drivers/hwtracing/intel_th/pti.h #define LPP_DEST_EXI BIT(1) BIT 58 drivers/hwtracing/stm/p_sys-t.c #define MIPI_SYST_OPT_LOC BIT(8) BIT 59 drivers/hwtracing/stm/p_sys-t.c #define MIPI_SYST_OPT_LEN BIT(9) BIT 60 drivers/hwtracing/stm/p_sys-t.c #define MIPI_SYST_OPT_CHK BIT(10) BIT 61 drivers/hwtracing/stm/p_sys-t.c #define MIPI_SYST_OPT_TS BIT(11) BIT 64 drivers/hwtracing/stm/p_sys-t.c #define MIPI_SYST_OPT_GUID BIT(23) BIT 19 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_TFR_CMD_STA BIT(9) /* send START before byte */ BIT 20 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */ BIT 21 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */ BIT 26 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_CTRL_BSPEED BIT(1) /* Bus Speed (1=Fast) */ BIT 27 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_CTRL_EN BIT(0) /* Enable Core (1=Enable) */ BIT 29 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_ISER_RXOF_EN BIT(4) /* Enable RX OVERFLOW IRQ */ BIT 30 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_ISER_ARB_EN BIT(3) /* Enable ARB LOST IRQ */ BIT 31 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_ISER_NACK_EN BIT(2) /* Enable NACK DET IRQ */ BIT 32 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_ISER_RXRDY_EN BIT(1) /* Enable RX Ready IRQ */ BIT 33 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_ISER_TXRDY_EN BIT(0) /* Enable TX Ready IRQ */ BIT 35 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW IRQ */ BIT 36 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_ISR_ARB BIT(3) /* ARB LOST IRQ */ BIT 37 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_ISR_NACK BIT(2) /* NACK DET IRQ */ BIT 38 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_ISR_RXRDY BIT(1) /* RX Ready IRQ */ BIT 39 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_ISR_TXRDY BIT(0) /* TX Ready IRQ */ BIT 41 drivers/i2c/busses/i2c-altera.c #define ALTR_I2C_STAT_CORE BIT(0) /* Core Status (0=idle) */ BIT 46 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15) BIT 47 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8) BIT 48 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7) BIT 49 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6) BIT 50 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_SLAVE_EN BIT(1) BIT 51 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_MASTER_EN BIT(0) BIT 72 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14) BIT 73 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13) BIT 74 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7) BIT 75 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6) BIT 76 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_INTR_ABNORMAL BIT(5) BIT 77 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4) BIT 78 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3) BIT 79 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_INTR_RX_DONE BIT(2) BIT 80 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_INTR_TX_NAK BIT(1) BIT 81 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_INTR_TX_ACK BIT(0) BIT 99 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_SCL_LINE_STS BIT(18) BIT 100 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_SDA_LINE_STS BIT(17) BIT 101 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_BUS_BUSY_STS BIT(16) BIT 102 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11) BIT 105 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_M_STOP_CMD BIT(5) BIT 106 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4) BIT 107 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_M_RX_CMD BIT(3) BIT 108 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_S_TX_CMD BIT(2) BIT 109 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_M_TX_CMD BIT(1) BIT 110 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_M_START_CMD BIT(0) BIT 31 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_START BIT(0) /* Send a Start Condition */ BIT 32 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */ BIT 33 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */ BIT 34 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */ BIT 35 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */ BIT 36 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */ BIT 37 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_QUICK BIT(6) /* SMBus quick command */ BIT 38 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_SWRST BIT(7) /* Software Reset */ BIT 39 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */ BIT 40 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */ BIT 41 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */ BIT 42 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */ BIT 43 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */ BIT 44 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */ BIT 45 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */ BIT 49 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_MREAD BIT(12) /* Master Read Direction */ BIT 62 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */ BIT 63 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */ BIT 64 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */ BIT 65 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_SVREAD BIT(3) /* Slave Read */ BIT 66 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_SVACC BIT(4) /* Slave Access */ BIT 67 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_OVRE BIT(6) /* Overrun Error */ BIT 68 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_UNRE BIT(7) /* Underrun Error */ BIT 69 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_NACK BIT(8) /* Not Acknowledged */ BIT 70 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_EOSACC BIT(11) /* End Of Slave Access */ BIT 71 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */ BIT 85 drivers/i2c/busses/i2c-at91.h #define AT91_TWI_ACR_DIR BIT(8) BIT 29 drivers/i2c/busses/i2c-axxia.c #define GLOBAL_MST_EN BIT(0) BIT 30 drivers/i2c/busses/i2c-axxia.c #define GLOBAL_SLV_EN BIT(1) BIT 31 drivers/i2c/busses/i2c-axxia.c #define GLOBAL_IBML_EN BIT(2) BIT 34 drivers/i2c/busses/i2c-axxia.c #define INT_SLV BIT(1) BIT 35 drivers/i2c/busses/i2c-axxia.c #define INT_MST BIT(0) BIT 37 drivers/i2c/busses/i2c-axxia.c #define WT_EN BIT(15) BIT 44 drivers/i2c/busses/i2c-axxia.c #define BM_SDAC BIT(3) BIT 45 drivers/i2c/busses/i2c-axxia.c #define BM_SCLC BIT(2) BIT 46 drivers/i2c/busses/i2c-axxia.c #define BM_SDAS BIT(1) BIT 47 drivers/i2c/busses/i2c-axxia.c #define BM_SCLS BIT(0) BIT 81 drivers/i2c/busses/i2c-axxia.c #define SLV_ADDR_DEC_GCE BIT(0) /* ACK to General Call Address from own master (loopback) */ BIT 82 drivers/i2c/busses/i2c-axxia.c #define SLV_ADDR_DEC_OGCE BIT(1) /* ACK to General Call Address from external masters */ BIT 83 drivers/i2c/busses/i2c-axxia.c #define SLV_ADDR_DEC_SA1E BIT(2) /* ACK to addr_1 enabled */ BIT 84 drivers/i2c/busses/i2c-axxia.c #define SLV_ADDR_DEC_SA1M BIT(3) /* 10-bit addressing for addr_1 enabled */ BIT 85 drivers/i2c/busses/i2c-axxia.c #define SLV_ADDR_DEC_SA2E BIT(4) /* ACK to addr_2 enabled */ BIT 86 drivers/i2c/busses/i2c-axxia.c #define SLV_ADDR_DEC_SA2M BIT(5) /* 10-bit addressing for addr_2 enabled */ BIT 90 drivers/i2c/busses/i2c-axxia.c #define SLV_RX_ACSA1 BIT(0) /* Generate ACK for writes to addr_1 */ BIT 91 drivers/i2c/busses/i2c-axxia.c #define SLV_RX_ACSA2 BIT(1) /* Generate ACK for writes to addr_2 */ BIT 92 drivers/i2c/busses/i2c-axxia.c #define SLV_RX_ACGCA BIT(2) /* ACK data phase transfers to General Call Address */ BIT 95 drivers/i2c/busses/i2c-axxia.c #define SLV_FIFO_DV1 BIT(0) /* Data Valid for addr_1 */ BIT 96 drivers/i2c/busses/i2c-axxia.c #define SLV_FIFO_DV2 BIT(1) /* Data Valid for addr_2 */ BIT 97 drivers/i2c/busses/i2c-axxia.c #define SLV_FIFO_AS BIT(2) /* (N)ACK Sent */ BIT 98 drivers/i2c/busses/i2c-axxia.c #define SLV_FIFO_TNAK BIT(3) /* Timeout NACK */ BIT 99 drivers/i2c/busses/i2c-axxia.c #define SLV_FIFO_STRC BIT(4) /* First byte after start condition received */ BIT 100 drivers/i2c/busses/i2c-axxia.c #define SLV_FIFO_RSC BIT(5) /* Repeated Start Condition */ BIT 101 drivers/i2c/busses/i2c-axxia.c #define SLV_FIFO_STPC BIT(6) /* Stop Condition */ BIT 105 drivers/i2c/busses/i2c-axxia.c #define SLV_STATUS_RFH BIT(0) /* FIFO service */ BIT 106 drivers/i2c/busses/i2c-axxia.c #define SLV_STATUS_WTC BIT(1) /* Write transfer complete */ BIT 107 drivers/i2c/busses/i2c-axxia.c #define SLV_STATUS_SRS1 BIT(2) /* Slave read from addr 1 */ BIT 108 drivers/i2c/busses/i2c-axxia.c #define SLV_STATUS_SRRS1 BIT(3) /* Repeated start from addr 1 */ BIT 109 drivers/i2c/busses/i2c-axxia.c #define SLV_STATUS_SRND1 BIT(4) /* Read request not following start condition */ BIT 110 drivers/i2c/busses/i2c-axxia.c #define SLV_STATUS_SRC1 BIT(5) /* Read canceled */ BIT 111 drivers/i2c/busses/i2c-axxia.c #define SLV_STATUS_SRAT1 BIT(6) /* Slave Read timed out */ BIT 112 drivers/i2c/busses/i2c-axxia.c #define SLV_STATUS_SRDRE1 BIT(7) /* Data written after timed out */ BIT 211 drivers/i2c/busses/i2c-bcm-iproc.c #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\ BIT 212 drivers/i2c/busses/i2c-bcm-iproc.c | BIT(IS_M_RX_THLD_SHIFT)) BIT 214 drivers/i2c/busses/i2c-bcm-iproc.c #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\ BIT 215 drivers/i2c/busses/i2c-bcm-iproc.c | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\ BIT 216 drivers/i2c/busses/i2c-bcm-iproc.c | BIT(IS_S_TX_UNDERRUN_SHIFT)) BIT 263 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(CFG_RESET_SHIFT); BIT 270 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~(BIT(CFG_RESET_SHIFT)); BIT 275 drivers/i2c/busses/i2c-bcm-iproc.c val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); BIT 286 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); BIT 295 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(IE_S_RX_EVENT_SHIFT); BIT 297 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(IE_S_START_BUSY_SHIFT); BIT 308 drivers/i2c/busses/i2c-bcm-iproc.c if (val & BIT(S_CMD_START_BUSY_SHIFT)) BIT 329 drivers/i2c/busses/i2c-bcm-iproc.c if (status & BIT(IS_S_RX_EVENT_SHIFT)) { BIT 341 drivers/i2c/busses/i2c-bcm-iproc.c } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) { BIT 347 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(S_CMD_START_BUSY_SHIFT); BIT 355 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(IE_S_TX_UNDERRUN_SHIFT); BIT 366 drivers/i2c/busses/i2c-bcm-iproc.c } else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) { BIT 372 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(S_CMD_START_BUSY_SHIFT); BIT 377 drivers/i2c/busses/i2c-bcm-iproc.c if (status & BIT(IS_S_START_BUSY_SHIFT)) { BIT 384 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT); BIT 431 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(M_TX_WR_STATUS_SHIFT); BIT 441 drivers/i2c/busses/i2c-bcm-iproc.c tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT); BIT 466 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~BIT(IS_M_RX_THLD_SHIFT); BIT 488 drivers/i2c/busses/i2c-bcm-iproc.c if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) BIT 492 drivers/i2c/busses/i2c-bcm-iproc.c if (status & BIT(IS_M_RX_THLD_SHIFT)) BIT 496 drivers/i2c/busses/i2c-bcm-iproc.c if (status & BIT(IS_M_START_BUSY_SHIFT)) { BIT 535 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(CFG_RESET_SHIFT); BIT 536 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~(BIT(CFG_EN_SHIFT)); BIT 543 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~(BIT(CFG_RESET_SHIFT)); BIT 547 drivers/i2c/busses/i2c-bcm-iproc.c val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT)); BIT 568 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(CFG_EN_SHIFT); BIT 570 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~BIT(CFG_EN_SHIFT); BIT 665 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); BIT 673 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); BIT 691 drivers/i2c/busses/i2c-bcm-iproc.c M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) { BIT 714 drivers/i2c/busses/i2c-bcm-iproc.c val |= BIT(M_TX_WR_STATUS_SHIFT); BIT 732 drivers/i2c/busses/i2c-bcm-iproc.c val_intr_en = BIT(IE_M_START_BUSY_SHIFT); BIT 741 drivers/i2c/busses/i2c-bcm-iproc.c val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT); BIT 747 drivers/i2c/busses/i2c-bcm-iproc.c val = BIT(M_CMD_START_BUSY_SHIFT); BIT 762 drivers/i2c/busses/i2c-bcm-iproc.c val_intr_en |= BIT(IE_M_RX_THLD_SHIFT); BIT 844 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~BIT(TIM_CFG_MODE_400_SHIFT); BIT 997 drivers/i2c/busses/i2c-bcm-iproc.c val &= ~BIT(TIM_CFG_MODE_400_SHIFT); BIT 1050 drivers/i2c/busses/i2c-bcm-iproc.c tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); BIT 28 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_C_READ BIT(0) BIT 29 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_C_CLEAR BIT(4) /* bits 4 and 5 both clear */ BIT 30 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_C_ST BIT(7) BIT 31 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_C_INTD BIT(8) BIT 32 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_C_INTT BIT(9) BIT 33 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_C_INTR BIT(10) BIT 34 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_C_I2CEN BIT(15) BIT 36 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_TA BIT(0) BIT 37 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_DONE BIT(1) BIT 38 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_TXW BIT(2) BIT 39 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_RXR BIT(3) BIT 40 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_TXD BIT(4) BIT 41 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_RXD BIT(5) BIT 42 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_TXE BIT(6) BIT 43 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_RXF BIT(7) BIT 44 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_ERR BIT(8) BIT 45 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_CLKT BIT(9) BIT 46 drivers/i2c/busses/i2c-bcm2835.c #define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */ BIT 30 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */ BIT 31 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_CR_ACK_EN BIT(3) BIT 32 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_CR_NEA BIT(2) BIT 33 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_CR_MS BIT(1) BIT 35 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_CR_RW BIT(0) BIT 37 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_CR_CLR_FIFO BIT(6) BIT 44 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_SR_BA BIT(8) BIT 45 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_SR_RXDV BIT(5) BIT 60 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_IXR_ARB_LOST BIT(9) BIT 61 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_IXR_RX_UNF BIT(7) BIT 62 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_IXR_TX_OVF BIT(6) BIT 63 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_IXR_RX_OVF BIT(5) BIT 64 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_IXR_SLV_RDY BIT(4) BIT 65 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_IXR_TO BIT(3) BIT 66 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_IXR_NACK BIT(2) BIT 67 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_IXR_DATA BIT(1) BIT 68 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_IXR_COMP BIT(0) BIT 115 drivers/i2c/busses/i2c-cadence.c #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) BIT 24 drivers/i2c/busses/i2c-cht-wc.c #define CHT_WC_I2C_CTRL_WR BIT(0) BIT 25 drivers/i2c/busses/i2c-cht-wc.c #define CHT_WC_I2C_CTRL_RD BIT(1) BIT 32 drivers/i2c/busses/i2c-cht-wc.c #define CHT_WC_EXTCHGRIRQ_CLIENT_IRQ BIT(0) BIT 33 drivers/i2c/busses/i2c-cht-wc.c #define CHT_WC_EXTCHGRIRQ_WRITE_IRQ BIT(1) BIT 34 drivers/i2c/busses/i2c-cht-wc.c #define CHT_WC_EXTCHGRIRQ_READ_IRQ BIT(2) BIT 35 drivers/i2c/busses/i2c-cht-wc.c #define CHT_WC_EXTCHGRIRQ_NACK_IRQ BIT(3) BIT 70 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_STR_BB BIT(12) BIT 71 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_STR_RSFULL BIT(11) BIT 72 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_STR_SCD BIT(5) BIT 73 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_STR_ARDY BIT(2) BIT 74 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_STR_NACK BIT(1) BIT 75 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_STR_AL BIT(0) BIT 77 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_MDR_NACK BIT(15) BIT 78 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_MDR_STT BIT(13) BIT 79 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_MDR_STP BIT(11) BIT 80 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_MDR_MST BIT(10) BIT 81 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_MDR_TRX BIT(9) BIT 82 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_MDR_XA BIT(8) BIT 83 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_MDR_RM BIT(7) BIT 84 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_MDR_IRS BIT(5) BIT 86 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_IMR_AAS BIT(6) BIT 87 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_IMR_SCD BIT(5) BIT 88 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_IMR_XRDY BIT(4) BIT 89 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_IMR_RRDY BIT(3) BIT 90 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_IMR_ARDY BIT(2) BIT 91 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_IMR_NACK BIT(1) BIT 92 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_IMR_AL BIT(0) BIT 95 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0) BIT 98 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_DIR_PDIR0 BIT(0) BIT 100 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_DIR_PDIR1 BIT(1) BIT 103 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_DIN_PDIN0 BIT(0) BIT 105 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_DIN_PDIN1 BIT(1) BIT 108 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_DSET_PDSET0 BIT(0) BIT 110 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_DSET_PDSET1 BIT(1) BIT 113 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0) BIT 115 drivers/i2c/busses/i2c-davinci.c #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1) BIT 102 drivers/i2c/busses/i2c-designware-core.h #define DW_IC_STATUS_TFE BIT(2) BIT 103 drivers/i2c/busses/i2c-designware-core.h #define DW_IC_STATUS_MASTER_ACTIVITY BIT(5) BIT 104 drivers/i2c/busses/i2c-designware-core.h #define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6) BIT 111 drivers/i2c/busses/i2c-designware-core.h #define DW_IC_TAR_10BITADDR_MASTER BIT(12) BIT 113 drivers/i2c/busses/i2c-designware-core.h #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3)) BIT 302 drivers/i2c/busses/i2c-designware-master.c cmd |= BIT(9); BIT 305 drivers/i2c/busses/i2c-designware-master.c cmd |= BIT(10); BIT 145 drivers/i2c/busses/i2c-designware-platdrv.c #define MSCC_ICPU_CFG_TWI_DELAY_ENABLE BIT(0) BIT 25 drivers/i2c/busses/i2c-digicolor.c #define II_CONTROL_LOCAL_RESET BIT(0) BIT 36 drivers/i2c/busses/i2c-digicolor.c #define II_COMMAND_GO BIT(7) BIT 54 drivers/i2c/busses/i2c-fsi.c #define I2C_CMD_WITH_START BIT(31) BIT 55 drivers/i2c/busses/i2c-fsi.c #define I2C_CMD_WITH_ADDR BIT(30) BIT 56 drivers/i2c/busses/i2c-fsi.c #define I2C_CMD_RD_CONT BIT(29) BIT 57 drivers/i2c/busses/i2c-fsi.c #define I2C_CMD_WITH_STOP BIT(28) BIT 58 drivers/i2c/busses/i2c-fsi.c #define I2C_CMD_FORCELAUNCH BIT(27) BIT 60 drivers/i2c/busses/i2c-fsi.c #define I2C_CMD_READ BIT(16) BIT 66 drivers/i2c/busses/i2c-fsi.c #define I2C_MODE_ENHANCED BIT(3) BIT 67 drivers/i2c/busses/i2c-fsi.c #define I2C_MODE_DIAG BIT(2) BIT 68 drivers/i2c/busses/i2c-fsi.c #define I2C_MODE_PACE_ALLOW BIT(1) BIT 69 drivers/i2c/busses/i2c-fsi.c #define I2C_MODE_WRAP BIT(0) BIT 79 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_INV_CMD BIT(15) BIT 80 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_PARITY BIT(14) BIT 81 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_BE_OVERRUN BIT(13) BIT 82 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_BE_ACCESS BIT(12) BIT 83 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_LOST_ARB BIT(11) BIT 84 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_NACK BIT(10) BIT 85 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_DAT_REQ BIT(9) BIT 86 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_CMD_COMP BIT(8) BIT 87 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_STOP_ERR BIT(7) BIT 88 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_BUSY BIT(6) BIT 89 drivers/i2c/busses/i2c-fsi.c #define I2C_INT_IDLE BIT(5) BIT 92 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_INV_CMD BIT(31) BIT 93 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_PARITY BIT(30) BIT 94 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_BE_OVERRUN BIT(29) BIT 95 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_BE_ACCESS BIT(28) BIT 96 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_LOST_ARB BIT(27) BIT 97 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_NACK BIT(26) BIT 98 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_DAT_REQ BIT(25) BIT 99 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_CMD_COMP BIT(24) BIT 100 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_STOP_ERR BIT(23) BIT 102 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_ANY_INT BIT(15) BIT 103 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_SCL_IN BIT(11) BIT 104 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_SDA_IN BIT(10) BIT 105 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_PORT_BUSY BIT(9) BIT 106 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_SELF_BUSY BIT(8) BIT 122 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_SCL_IN_SY BIT(15) BIT 123 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_SDA_IN_SY BIT(14) BIT 124 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_S_SCL BIT(13) BIT 125 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_S_SDA BIT(12) BIT 126 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_M_SCL BIT(11) BIT 127 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_M_SDA BIT(10) BIT 128 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_HI_WATER BIT(9) BIT 129 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_LO_WATER BIT(8) BIT 130 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_PORT_BUSY BIT(7) BIT 131 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_SELF_BUSY BIT(6) BIT 135 drivers/i2c/busses/i2c-fsi.c #define I2C_PORT_BUSY_RESET BIT(31) BIT 30 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_ENABLE BIT(8) BIT 31 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_UNMASK_TOTAL BIT(7) BIT 32 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_UNMASK_START BIT(6) BIT 33 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_UNMASK_END BIT(5) BIT 34 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_UNMASK_SEND BIT(4) BIT 35 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_UNMASK_RECEIVE BIT(3) BIT 36 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_UNMASK_ACK BIT(2) BIT 37 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_UNMASK_ARBITRATE BIT(1) BIT 38 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_UNMASK_OVER BIT(0) BIT 42 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_NO_ACK BIT(4) BIT 43 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_START BIT(3) BIT 44 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_READ BIT(2) BIT 45 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_WRITE BIT(1) BIT 46 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_STOP BIT(0) BIT 49 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_CLEAR_START BIT(6) BIT 50 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_CLEAR_END BIT(5) BIT 51 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_CLEAR_SEND BIT(4) BIT 52 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_CLEAR_RECEIVE BIT(3) BIT 53 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_CLEAR_ACK BIT(2) BIT 54 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_CLEAR_ARBITRATE BIT(1) BIT 55 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_CLEAR_OVER BIT(0) BIT 62 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_BUSY BIT(7) BIT 63 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_START_INTR BIT(6) BIT 64 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_END_INTR BIT(5) BIT 65 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_SEND_INTR BIT(4) BIT 66 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_RECEIVE_INTR BIT(3) BIT 67 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_ACK_INTR BIT(2) BIT 68 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_ARBITRATE_INTR BIT(1) BIT 69 drivers/i2c/busses/i2c-hix5hd2.c #define I2C_OVER_INTR BIT(0) BIT 137 drivers/i2c/busses/i2c-i801.c #define SMBPCISTS_INTS BIT(3) BIT 140 drivers/i2c/busses/i2c-i801.c #define SMBPCICTL_INTDIS BIT(10) BIT 143 drivers/i2c/busses/i2c-i801.c #define SMBHSTCFG_HST_EN BIT(0) BIT 144 drivers/i2c/busses/i2c-i801.c #define SMBHSTCFG_SMB_SMI_EN BIT(1) BIT 145 drivers/i2c/busses/i2c-i801.c #define SMBHSTCFG_I2C_EN BIT(2) BIT 146 drivers/i2c/busses/i2c-i801.c #define SMBHSTCFG_SPD_WD BIT(4) BIT 149 drivers/i2c/busses/i2c-i801.c #define TCOCTL_EN BIT(8) BIT 152 drivers/i2c/busses/i2c-i801.c #define SMBAUXSTS_CRCE BIT(0) BIT 153 drivers/i2c/busses/i2c-i801.c #define SMBAUXSTS_STCO BIT(1) BIT 156 drivers/i2c/busses/i2c-i801.c #define SMBAUXCTL_CRC BIT(0) BIT 157 drivers/i2c/busses/i2c-i801.c #define SMBAUXCTL_E32B BIT(1) BIT 173 drivers/i2c/busses/i2c-i801.c #define SMBHSTCNT_INTREN BIT(0) BIT 174 drivers/i2c/busses/i2c-i801.c #define SMBHSTCNT_KILL BIT(1) BIT 175 drivers/i2c/busses/i2c-i801.c #define SMBHSTCNT_LAST_BYTE BIT(5) BIT 176 drivers/i2c/busses/i2c-i801.c #define SMBHSTCNT_START BIT(6) BIT 177 drivers/i2c/busses/i2c-i801.c #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ BIT 180 drivers/i2c/busses/i2c-i801.c #define SMBHSTSTS_BYTE_DONE BIT(7) BIT 181 drivers/i2c/busses/i2c-i801.c #define SMBHSTSTS_INUSE_STS BIT(6) BIT 182 drivers/i2c/busses/i2c-i801.c #define SMBHSTSTS_SMBALERT_STS BIT(5) BIT 183 drivers/i2c/busses/i2c-i801.c #define SMBHSTSTS_FAILED BIT(4) BIT 184 drivers/i2c/busses/i2c-i801.c #define SMBHSTSTS_BUS_ERR BIT(3) BIT 185 drivers/i2c/busses/i2c-i801.c #define SMBHSTSTS_DEV_ERR BIT(2) BIT 186 drivers/i2c/busses/i2c-i801.c #define SMBHSTSTS_INTR BIT(1) BIT 187 drivers/i2c/busses/i2c-i801.c #define SMBHSTSTS_HOST_BUSY BIT(0) BIT 190 drivers/i2c/busses/i2c-i801.c #define SMBSLVSTS_HST_NTFY_STS BIT(0) BIT 193 drivers/i2c/busses/i2c-i801.c #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) BIT 282 drivers/i2c/busses/i2c-i801.c #define FEATURE_SMBUS_PEC BIT(0) BIT 283 drivers/i2c/busses/i2c-i801.c #define FEATURE_BLOCK_BUFFER BIT(1) BIT 284 drivers/i2c/busses/i2c-i801.c #define FEATURE_BLOCK_PROC BIT(2) BIT 285 drivers/i2c/busses/i2c-i801.c #define FEATURE_I2C_BLOCK_READ BIT(3) BIT 286 drivers/i2c/busses/i2c-i801.c #define FEATURE_IRQ BIT(4) BIT 287 drivers/i2c/busses/i2c-i801.c #define FEATURE_HOST_NOTIFY BIT(5) BIT 289 drivers/i2c/busses/i2c-i801.c #define FEATURE_IDF BIT(15) BIT 290 drivers/i2c/busses/i2c-i801.c #define FEATURE_TCO_SPT BIT(16) BIT 291 drivers/i2c/busses/i2c-i801.c #define FEATURE_TCO_CNL BIT(17) BIT 125 drivers/i2c/busses/i2c-img-scb.c #define FIFO_READ_FULL BIT(0) BIT 126 drivers/i2c/busses/i2c-img-scb.c #define FIFO_READ_EMPTY BIT(1) BIT 127 drivers/i2c/busses/i2c-img-scb.c #define FIFO_WRITE_FULL BIT(2) BIT 128 drivers/i2c/busses/i2c-img-scb.c #define FIFO_WRITE_EMPTY BIT(3) BIT 131 drivers/i2c/busses/i2c-img-scb.c #define SCB_FILT_DISABLE BIT(31) BIT 132 drivers/i2c/busses/i2c-img-scb.c #define SCB_FILT_BYPASS BIT(30) BIT 140 drivers/i2c/busses/i2c-img-scb.c #define INT_BUS_INACTIVE BIT(0) BIT 141 drivers/i2c/busses/i2c-img-scb.c #define INT_UNEXPECTED_START BIT(1) BIT 142 drivers/i2c/busses/i2c-img-scb.c #define INT_SCLK_LOW_TIMEOUT BIT(2) BIT 143 drivers/i2c/busses/i2c-img-scb.c #define INT_SDAT_LOW_TIMEOUT BIT(3) BIT 144 drivers/i2c/busses/i2c-img-scb.c #define INT_WRITE_ACK_ERR BIT(4) BIT 145 drivers/i2c/busses/i2c-img-scb.c #define INT_ADDR_ACK_ERR BIT(5) BIT 146 drivers/i2c/busses/i2c-img-scb.c #define INT_FIFO_FULL BIT(9) BIT 147 drivers/i2c/busses/i2c-img-scb.c #define INT_FIFO_FILLING BIT(10) BIT 148 drivers/i2c/busses/i2c-img-scb.c #define INT_FIFO_EMPTY BIT(11) BIT 149 drivers/i2c/busses/i2c-img-scb.c #define INT_FIFO_EMPTYING BIT(12) BIT 150 drivers/i2c/busses/i2c-img-scb.c #define INT_TRANSACTION_DONE BIT(15) BIT 151 drivers/i2c/busses/i2c-img-scb.c #define INT_SLAVE_EVENT BIT(16) BIT 152 drivers/i2c/busses/i2c-img-scb.c #define INT_MASTER_HALTED BIT(17) BIT 153 drivers/i2c/busses/i2c-img-scb.c #define INT_TIMING BIT(18) BIT 154 drivers/i2c/busses/i2c-img-scb.c #define INT_STOP_DETECTED BIT(19) BIT 188 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_SCLK_LINE_STATUS BIT(0) BIT 189 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_SCLK_EN BIT(1) BIT 190 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_SDAT_LINE_STATUS BIT(2) BIT 191 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_SDAT_EN BIT(3) BIT 192 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_DET_START_STATUS BIT(4) BIT 193 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_DET_STOP_STATUS BIT(5) BIT 194 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_DET_ACK_STATUS BIT(6) BIT 195 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_DET_NACK_STATUS BIT(7) BIT 196 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_BUS_IDLE BIT(8) BIT 197 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_T_DONE_STATUS BIT(9) BIT 198 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_SCLK_OUT_STATUS BIT(10) BIT 199 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_SDAT_OUT_STATUS BIT(11) BIT 200 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_GEN_LINE_MASK_STATUS BIT(12) BIT 201 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_START_BIT_DET BIT(13) BIT 202 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_STOP_BIT_DET BIT(14) BIT 203 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_ACK_DET BIT(15) BIT 204 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_NACK_DET BIT(16) BIT 205 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_INPUT_HELD_V BIT(17) BIT 206 drivers/i2c/busses/i2c-img-scb.c #define LINESTAT_ABORT_DET BIT(18) BIT 216 drivers/i2c/busses/i2c-img-scb.c #define OVERRIDE_SCLK_OVR BIT(0) BIT 217 drivers/i2c/busses/i2c-img-scb.c #define OVERRIDE_SCLKEN_OVR BIT(1) BIT 218 drivers/i2c/busses/i2c-img-scb.c #define OVERRIDE_SDAT_OVR BIT(2) BIT 219 drivers/i2c/busses/i2c-img-scb.c #define OVERRIDE_SDATEN_OVR BIT(3) BIT 220 drivers/i2c/busses/i2c-img-scb.c #define OVERRIDE_MASTER BIT(9) BIT 221 drivers/i2c/busses/i2c-img-scb.c #define OVERRIDE_LINE_OVR_EN BIT(10) BIT 222 drivers/i2c/busses/i2c-img-scb.c #define OVERRIDE_DIRECT BIT(11) BIT 274 drivers/i2c/busses/i2c-img-scb.c #define ISR_COMPLETE_M BIT(31) BIT 275 drivers/i2c/busses/i2c-img-scb.c #define ISR_FATAL_M BIT(30) BIT 276 drivers/i2c/busses/i2c-img-scb.c #define ISR_WAITSTOP BIT(29) BIT 54 drivers/i2c/busses/i2c-imx-lpi2c.c #define MCR_MEN BIT(0) BIT 55 drivers/i2c/busses/i2c-imx-lpi2c.c #define MCR_RST BIT(1) BIT 56 drivers/i2c/busses/i2c-imx-lpi2c.c #define MCR_DOZEN BIT(2) BIT 57 drivers/i2c/busses/i2c-imx-lpi2c.c #define MCR_DBGEN BIT(3) BIT 58 drivers/i2c/busses/i2c-imx-lpi2c.c #define MCR_RTF BIT(8) BIT 59 drivers/i2c/busses/i2c-imx-lpi2c.c #define MCR_RRF BIT(9) BIT 60 drivers/i2c/busses/i2c-imx-lpi2c.c #define MSR_TDF BIT(0) BIT 61 drivers/i2c/busses/i2c-imx-lpi2c.c #define MSR_RDF BIT(1) BIT 62 drivers/i2c/busses/i2c-imx-lpi2c.c #define MSR_SDF BIT(9) BIT 63 drivers/i2c/busses/i2c-imx-lpi2c.c #define MSR_NDF BIT(10) BIT 64 drivers/i2c/busses/i2c-imx-lpi2c.c #define MSR_ALF BIT(11) BIT 65 drivers/i2c/busses/i2c-imx-lpi2c.c #define MSR_MBF BIT(24) BIT 66 drivers/i2c/busses/i2c-imx-lpi2c.c #define MSR_BBF BIT(25) BIT 67 drivers/i2c/busses/i2c-imx-lpi2c.c #define MIER_TDIE BIT(0) BIT 68 drivers/i2c/busses/i2c-imx-lpi2c.c #define MIER_RDIE BIT(1) BIT 69 drivers/i2c/busses/i2c-imx-lpi2c.c #define MIER_SDIE BIT(9) BIT 70 drivers/i2c/busses/i2c-imx-lpi2c.c #define MIER_NDIE BIT(10) BIT 71 drivers/i2c/busses/i2c-imx-lpi2c.c #define MCFGR1_AUTOSTOP BIT(8) BIT 72 drivers/i2c/busses/i2c-imx-lpi2c.c #define MCFGR1_IGNACK BIT(9) BIT 73 drivers/i2c/busses/i2c-imx-lpi2c.c #define MRDR_RXEMPTY BIT(14) BIT 59 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_CTRL_STPHLD BIT(7) BIT 60 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_CTRL_SLVDIS BIT(6) BIT 61 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_CTRL_REST BIT(5) BIT 62 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_CTRL_MATP BIT(4) BIT 63 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_CTRL_SATP BIT(3) BIT 64 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_CTRL_SPDF BIT(2) BIT 65 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_CTRL_SPDS BIT(1) BIT 66 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_CTRL_MD BIT(0) BIT 68 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_STA_SLVACT BIT(6) BIT 69 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_STA_MSTACT BIT(5) BIT 70 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_STA_RFF BIT(4) BIT 71 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_STA_RFNE BIT(3) BIT 72 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_STA_TFE BIT(2) BIT 73 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_STA_TFNF BIT(1) BIT 74 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_STA_ACT BIT(0) BIT 76 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_IGC BIT(11) BIT 77 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_ISTT BIT(10) BIT 78 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_ISTP BIT(9) BIT 79 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_IACT BIT(8) BIT 80 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_RXDN BIT(7) BIT 81 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_TXABT BIT(6) BIT 82 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_RDREQ BIT(5) BIT 83 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_TXEMP BIT(4) BIT 84 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_TXOF BIT(3) BIT 85 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_RXFL BIT(2) BIT 86 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_RXOF BIT(1) BIT 87 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTST_RXUF BIT(0) BIT 89 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MIGC BIT(11) BIT 90 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MISTT BIT(10) BIT 91 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MISTP BIT(9) BIT 92 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MIACT BIT(8) BIT 93 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MRXDN BIT(7) BIT 94 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MTXABT BIT(6) BIT 95 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MRDREQ BIT(5) BIT 96 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MTXEMP BIT(4) BIT 97 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MTXOF BIT(3) BIT 98 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MRXFL BIT(2) BIT 99 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MRXOF BIT(1) BIT 100 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_INTM_MRXUF BIT(0) BIT 102 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_DC_READ BIT(8) BIT 104 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_SDAHD_HDENB BIT(8) BIT 106 drivers/i2c/busses/i2c-jz4780.c #define JZ4780_I2C_ENB_I2C BIT(0) BIT 37 drivers/i2c/busses/i2c-lpc2k.c #define LPC24XX_AA BIT(2) BIT 38 drivers/i2c/busses/i2c-lpc2k.c #define LPC24XX_SI BIT(3) BIT 39 drivers/i2c/busses/i2c-lpc2k.c #define LPC24XX_STO BIT(4) BIT 40 drivers/i2c/busses/i2c-lpc2k.c #define LPC24XX_STA BIT(5) BIT 41 drivers/i2c/busses/i2c-lpc2k.c #define LPC24XX_I2EN BIT(6) BIT 31 drivers/i2c/busses/i2c-meson.c #define REG_CTRL_START BIT(0) BIT 32 drivers/i2c/busses/i2c-meson.c #define REG_CTRL_ACK_IGNORE BIT(1) BIT 33 drivers/i2c/busses/i2c-meson.c #define REG_CTRL_STATUS BIT(2) BIT 34 drivers/i2c/busses/i2c-meson.c #define REG_CTRL_ERROR BIT(3) BIT 48 drivers/i2c/busses/i2c-mlxcpld.c #define MLXCPLD_I2C_DATA_SZ_BIT BIT(5) BIT 50 drivers/i2c/busses/i2c-mlxcpld.c #define MLXCPLD_I2C_SMBUS_BLK_BIT BIT(7) BIT 32 drivers/i2c/busses/i2c-mt7621.c #define SM0CFG2_IS_AUTOMODE BIT(0) BIT 35 drivers/i2c/busses/i2c-mt7621.c #define SM0CTL0_ODRAIN BIT(31) BIT 38 drivers/i2c/busses/i2c-mt7621.c #define SM0CTL0_CS_STATUS BIT(4) BIT 39 drivers/i2c/busses/i2c-mt7621.c #define SM0CTL0_SCL_STATE BIT(3) BIT 40 drivers/i2c/busses/i2c-mt7621.c #define SM0CTL0_SDA_STATE BIT(2) BIT 41 drivers/i2c/busses/i2c-mt7621.c #define SM0CTL0_EN BIT(1) BIT 42 drivers/i2c/busses/i2c-mt7621.c #define SM0CTL0_SCL_STRETCH BIT(0) BIT 54 drivers/i2c/busses/i2c-mt7621.c #define SM0CTL1_TRI BIT(0) BIT 185 drivers/i2c/busses/i2c-mt7621.c ret = mtk_i2c_check_ack(i2c, BIT(0)); BIT 33 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2) BIT 34 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3) BIT 35 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4) BIT 36 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_REG_CONTROL_START BIT(5) BIT 37 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6) BIT 38 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7) BIT 71 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0) BIT 72 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1) BIT 74 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12) BIT 77 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19) BIT 78 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20) BIT 81 drivers/i2c/busses/i2c-mv64xxx.c #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0) BIT 22 drivers/i2c/busses/i2c-nvidia-gpu.c #define I2C_MST_CNTL_GEN_START BIT(0) BIT 23 drivers/i2c/busses/i2c-nvidia-gpu.c #define I2C_MST_CNTL_GEN_STOP BIT(1) BIT 27 drivers/i2c/busses/i2c-nvidia-gpu.c #define I2C_MST_CNTL_GEN_NACK BIT(28) BIT 33 drivers/i2c/busses/i2c-nvidia-gpu.c #define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31) BIT 41 drivers/i2c/busses/i2c-nvidia-gpu.c #define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24) BIT 46 drivers/i2c/busses/i2c-nvidia-gpu.c #define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0) BIT 47 drivers/i2c/busses/i2c-nvidia-gpu.c #define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14) BIT 48 drivers/i2c/busses/i2c-nvidia-gpu.c #define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15) BIT 88 drivers/i2c/busses/i2c-ocores.c #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */ BIT 34 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CTL_RB BIT(1) BIT 40 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CTL_IRQE BIT(5) BIT 41 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CTL_EN BIT(7) BIT 42 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CTL_AE BIT(8) BIT 43 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CTL_SHSM BIT(10) BIT 48 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_RACK BIT(0) BIT 49 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_BEB BIT(1) BIT 50 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_IRQP BIT(2) BIT 51 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_LAB BIT(3) BIT 52 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_STPD BIT(4) BIT 53 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_STAD BIT(5) BIT 54 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_BBB BIT(6) BIT 55 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_TCB BIT(7) BIT 56 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_LBST BIT(8) BIT 57 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_SAMB BIT(9) BIT 58 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_STAT_SRGC BIT(10) BIT 61 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CMD_SBE BIT(0) BIT 62 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CMD_RBE BIT(4) BIT 63 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CMD_DE BIT(8) BIT 64 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CMD_NS BIT(9) BIT 65 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CMD_SE BIT(10) BIT 66 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CMD_MSS BIT(11) BIT 67 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CMD_WRS BIT(12) BIT 68 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_CMD_SECL BIT(15) BIT 74 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_FIFOCTL_NIB BIT(0) BIT 75 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_FIFOCTL_RFR BIT(1) BIT 76 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_FIFOCTL_TFR BIT(2) BIT 79 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_FIFOSTAT_RNB BIT(1) BIT 80 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_FIFOSTAT_RFE BIT(2) BIT 81 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_FIFOSTAT_TFF BIT(5) BIT 25 drivers/i2c/busses/i2c-qcom-geni.c #define SE_I2C_ABORT BIT(1) BIT 35 drivers/i2c/busses/i2c-qcom-geni.c #define PRE_CMD_DELAY BIT(0) BIT 36 drivers/i2c/busses/i2c-qcom-geni.c #define TIMESTAMP_BEFORE BIT(1) BIT 37 drivers/i2c/busses/i2c-qcom-geni.c #define STOP_STRETCH BIT(2) BIT 38 drivers/i2c/busses/i2c-qcom-geni.c #define TIMESTAMP_AFTER BIT(3) BIT 39 drivers/i2c/busses/i2c-qcom-geni.c #define POST_COMMAND_DELAY BIT(4) BIT 40 drivers/i2c/busses/i2c-qcom-geni.c #define IGNORE_ADD_NACK BIT(6) BIT 41 drivers/i2c/busses/i2c-qcom-geni.c #define READ_FINISHED_WITH_ACK BIT(7) BIT 42 drivers/i2c/busses/i2c-qcom-geni.c #define BYPASS_ADDR_PHASE BIT(8) BIT 65 drivers/i2c/busses/i2c-qcom-geni.c #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \ BIT 51 drivers/i2c/busses/i2c-qup.c #define QUP_STATE_VALID BIT(2) BIT 52 drivers/i2c/busses/i2c-qup.c #define QUP_I2C_MAST_GEN BIT(4) BIT 53 drivers/i2c/busses/i2c-qup.c #define QUP_I2C_FLUSH BIT(6) BIT 59 drivers/i2c/busses/i2c-qup.c #define QUP_I2C_NACK_FLAG BIT(3) BIT 60 drivers/i2c/busses/i2c-qup.c #define QUP_OUT_NOT_EMPTY BIT(4) BIT 61 drivers/i2c/busses/i2c-qup.c #define QUP_IN_NOT_EMPTY BIT(5) BIT 62 drivers/i2c/busses/i2c-qup.c #define QUP_OUT_FULL BIT(6) BIT 63 drivers/i2c/busses/i2c-qup.c #define QUP_OUT_SVC_FLAG BIT(8) BIT 64 drivers/i2c/busses/i2c-qup.c #define QUP_IN_SVC_FLAG BIT(9) BIT 65 drivers/i2c/busses/i2c-qup.c #define QUP_MX_OUTPUT_DONE BIT(10) BIT 66 drivers/i2c/busses/i2c-qup.c #define QUP_MX_INPUT_DONE BIT(11) BIT 67 drivers/i2c/busses/i2c-qup.c #define OUT_BLOCK_WRITE_REQ BIT(12) BIT 68 drivers/i2c/busses/i2c-qup.c #define IN_BLOCK_READ_REQ BIT(13) BIT 71 drivers/i2c/busses/i2c-qup.c #define QUP_NO_INPUT BIT(7) BIT 72 drivers/i2c/busses/i2c-qup.c #define QUP_CLOCK_AUTO_GATE BIT(13) BIT 86 drivers/i2c/busses/i2c-qup.c #define QUP_UNPACK_EN BIT(14) BIT 87 drivers/i2c/busses/i2c-qup.c #define QUP_PACK_EN BIT(15) BIT 114 drivers/i2c/busses/i2c-qup.c #define I2C_STATUS_WR_BUFFER_FULL BIT(0) BIT 115 drivers/i2c/busses/i2c-qup.c #define I2C_STATUS_BUS_ACTIVE BIT(8) BIT 123 drivers/i2c/busses/i2c-qup.c #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31) BIT 108 drivers/i2c/busses/i2c-rcar.c #define ID_P_REP_AFTER_RD BIT(29) BIT 109 drivers/i2c/busses/i2c-rcar.c #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ BIT 110 drivers/i2c/busses/i2c-rcar.c #define ID_P_PM_BLOCKED BIT(31) BIT 43 drivers/i2c/busses/i2c-rk3x.c #define REG_CON_EN BIT(0) BIT 52 drivers/i2c/busses/i2c-rk3x.c #define REG_CON_MOD_MASK (BIT(1) | BIT(2)) BIT 53 drivers/i2c/busses/i2c-rk3x.c #define REG_CON_START BIT(3) BIT 54 drivers/i2c/busses/i2c-rk3x.c #define REG_CON_STOP BIT(4) BIT 55 drivers/i2c/busses/i2c-rk3x.c #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */ BIT 56 drivers/i2c/busses/i2c-rk3x.c #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */ BIT 65 drivers/i2c/busses/i2c-rk3x.c #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */ BIT 68 drivers/i2c/busses/i2c-rk3x.c #define REG_INT_BTF BIT(0) /* a byte was transmitted */ BIT 69 drivers/i2c/busses/i2c-rk3x.c #define REG_INT_BRF BIT(1) /* a byte was received */ BIT 70 drivers/i2c/busses/i2c-rk3x.c #define REG_INT_MBTF BIT(2) /* master data transmit finished */ BIT 71 drivers/i2c/busses/i2c-rk3x.c #define REG_INT_MBRF BIT(3) /* master data receive finished */ BIT 72 drivers/i2c/busses/i2c-rk3x.c #define REG_INT_START BIT(4) /* START condition generated */ BIT 73 drivers/i2c/busses/i2c-rk3x.c #define REG_INT_STOP BIT(5) /* STOP condition generated */ BIT 74 drivers/i2c/busses/i2c-rk3x.c #define REG_INT_NAKRCV BIT(6) /* NACK received */ BIT 1254 drivers/i2c/busses/i2c-rk3x.c value = BIT(27 + bus_nr) | BIT(11 + bus_nr); BIT 1043 drivers/i2c/busses/i2c-s3c2410.c regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0); BIT 37 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_STAT_BUSY BIT(0) BIT 38 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_STAT_TIP BIT(1) BIT 39 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_STAT_NACK BIT(2) BIT 40 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_STAT_TR_INT BIT(4) BIT 41 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_STAT_STOP BIT(6) BIT 42 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_STAT_CMD_DONE BIT(8) BIT 43 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_STAT_ERR BIT(9) BIT 47 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_RESET BIT(0) BIT 48 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_CORE_EN BIT(1) BIT 49 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_MASTER_MODE BIT(2) BIT 50 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_CMD_DONE_EN BIT(11) BIT 51 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_ERR_INT_EN BIT(12) BIT 56 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_START_CMD BIT(0) BIT 59 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_NACK BIT(3) BIT 60 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_WRITE BIT(4) BIT 61 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_READ BIT(5) BIT 62 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_STOP BIT(6) BIT 63 drivers/i2c/busses/i2c-sirf.c #define SIRFSOC_I2C_START BIT(7) BIT 35 drivers/i2c/busses/i2c-sprd.c #define STP_EN BIT(20) BIT 40 drivers/i2c/busses/i2c-sprd.c #define I2C_DMA_EN BIT(11) BIT 41 drivers/i2c/busses/i2c-sprd.c #define FULL_INTEN BIT(10) BIT 42 drivers/i2c/busses/i2c-sprd.c #define EMPTY_INTEN BIT(9) BIT 43 drivers/i2c/busses/i2c-sprd.c #define I2C_DVD_OPT BIT(8) BIT 44 drivers/i2c/busses/i2c-sprd.c #define I2C_OUT_OPT BIT(7) BIT 45 drivers/i2c/busses/i2c-sprd.c #define I2C_TRIM_OPT BIT(6) BIT 46 drivers/i2c/busses/i2c-sprd.c #define I2C_HS_MODE BIT(4) BIT 47 drivers/i2c/busses/i2c-sprd.c #define I2C_MODE BIT(3) BIT 48 drivers/i2c/busses/i2c-sprd.c #define I2C_EN BIT(2) BIT 49 drivers/i2c/busses/i2c-sprd.c #define I2C_INT_EN BIT(1) BIT 50 drivers/i2c/busses/i2c-sprd.c #define I2C_START BIT(0) BIT 53 drivers/i2c/busses/i2c-sprd.c #define SDA_IN BIT(21) BIT 54 drivers/i2c/busses/i2c-sprd.c #define SCL_IN BIT(20) BIT 55 drivers/i2c/busses/i2c-sprd.c #define FIFO_FULL BIT(4) BIT 56 drivers/i2c/busses/i2c-sprd.c #define FIFO_EMPTY BIT(3) BIT 57 drivers/i2c/busses/i2c-sprd.c #define I2C_INT BIT(2) BIT 58 drivers/i2c/busses/i2c-sprd.c #define I2C_RX_ACK BIT(1) BIT 59 drivers/i2c/busses/i2c-sprd.c #define I2C_BUSY BIT(0) BIT 62 drivers/i2c/busses/i2c-sprd.c #define I2C_RST BIT(0) BIT 51 drivers/i2c/busses/i2c-st.c #define SSC_CTL_HB BIT(4) BIT 52 drivers/i2c/busses/i2c-st.c #define SSC_CTL_PH BIT(5) BIT 53 drivers/i2c/busses/i2c-st.c #define SSC_CTL_PO BIT(6) BIT 54 drivers/i2c/busses/i2c-st.c #define SSC_CTL_SR BIT(7) BIT 55 drivers/i2c/busses/i2c-st.c #define SSC_CTL_MS BIT(8) BIT 56 drivers/i2c/busses/i2c-st.c #define SSC_CTL_EN BIT(9) BIT 57 drivers/i2c/busses/i2c-st.c #define SSC_CTL_LPB BIT(10) BIT 58 drivers/i2c/busses/i2c-st.c #define SSC_CTL_EN_TX_FIFO BIT(11) BIT 59 drivers/i2c/busses/i2c-st.c #define SSC_CTL_EN_RX_FIFO BIT(12) BIT 60 drivers/i2c/busses/i2c-st.c #define SSC_CTL_EN_CLST_RX BIT(13) BIT 63 drivers/i2c/busses/i2c-st.c #define SSC_IEN_RIEN BIT(0) BIT 64 drivers/i2c/busses/i2c-st.c #define SSC_IEN_TIEN BIT(1) BIT 65 drivers/i2c/busses/i2c-st.c #define SSC_IEN_TEEN BIT(2) BIT 66 drivers/i2c/busses/i2c-st.c #define SSC_IEN_REEN BIT(3) BIT 67 drivers/i2c/busses/i2c-st.c #define SSC_IEN_PEEN BIT(4) BIT 68 drivers/i2c/busses/i2c-st.c #define SSC_IEN_AASEN BIT(6) BIT 69 drivers/i2c/busses/i2c-st.c #define SSC_IEN_STOPEN BIT(7) BIT 70 drivers/i2c/busses/i2c-st.c #define SSC_IEN_ARBLEN BIT(8) BIT 71 drivers/i2c/busses/i2c-st.c #define SSC_IEN_NACKEN BIT(10) BIT 72 drivers/i2c/busses/i2c-st.c #define SSC_IEN_REPSTRTEN BIT(11) BIT 73 drivers/i2c/busses/i2c-st.c #define SSC_IEN_TX_FIFO_HALF BIT(12) BIT 74 drivers/i2c/busses/i2c-st.c #define SSC_IEN_RX_FIFO_HALF_FULL BIT(14) BIT 77 drivers/i2c/busses/i2c-st.c #define SSC_STA_RIR BIT(0) BIT 78 drivers/i2c/busses/i2c-st.c #define SSC_STA_TIR BIT(1) BIT 79 drivers/i2c/busses/i2c-st.c #define SSC_STA_TE BIT(2) BIT 80 drivers/i2c/busses/i2c-st.c #define SSC_STA_RE BIT(3) BIT 81 drivers/i2c/busses/i2c-st.c #define SSC_STA_PE BIT(4) BIT 82 drivers/i2c/busses/i2c-st.c #define SSC_STA_CLST BIT(5) BIT 83 drivers/i2c/busses/i2c-st.c #define SSC_STA_AAS BIT(6) BIT 84 drivers/i2c/busses/i2c-st.c #define SSC_STA_STOP BIT(7) BIT 85 drivers/i2c/busses/i2c-st.c #define SSC_STA_ARBL BIT(8) BIT 86 drivers/i2c/busses/i2c-st.c #define SSC_STA_BUSY BIT(9) BIT 87 drivers/i2c/busses/i2c-st.c #define SSC_STA_NACK BIT(10) BIT 88 drivers/i2c/busses/i2c-st.c #define SSC_STA_REPSTRT BIT(11) BIT 89 drivers/i2c/busses/i2c-st.c #define SSC_STA_TX_FIFO_HALF BIT(12) BIT 90 drivers/i2c/busses/i2c-st.c #define SSC_STA_TX_FIFO_FULL BIT(13) BIT 91 drivers/i2c/busses/i2c-st.c #define SSC_STA_RX_FIFO_HALF BIT(14) BIT 94 drivers/i2c/busses/i2c-st.c #define SSC_I2C_I2CM BIT(0) BIT 95 drivers/i2c/busses/i2c-st.c #define SSC_I2C_STRTG BIT(1) BIT 96 drivers/i2c/busses/i2c-st.c #define SSC_I2C_STOPG BIT(2) BIT 97 drivers/i2c/busses/i2c-st.c #define SSC_I2C_ACKG BIT(3) BIT 98 drivers/i2c/busses/i2c-st.c #define SSC_I2C_AD10 BIT(4) BIT 99 drivers/i2c/busses/i2c-st.c #define SSC_I2C_TXENB BIT(5) BIT 100 drivers/i2c/busses/i2c-st.c #define SSC_I2C_REPSTRTG BIT(11) BIT 101 drivers/i2c/busses/i2c-st.c #define SSC_I2C_SLAVE_DISABLE BIT(12) BIT 110 drivers/i2c/busses/i2c-st.c #define SSC_CLR_SSCAAS BIT(6) BIT 111 drivers/i2c/busses/i2c-st.c #define SSC_CLR_SSCSTOP BIT(7) BIT 112 drivers/i2c/busses/i2c-st.c #define SSC_CLR_SSCARBL BIT(8) BIT 113 drivers/i2c/busses/i2c-st.c #define SSC_CLR_NACK BIT(10) BIT 114 drivers/i2c/busses/i2c-st.c #define SSC_CLR_REPSTRT BIT(11) BIT 44 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CR1_POS BIT(11) BIT 45 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CR1_ACK BIT(10) BIT 46 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CR1_STOP BIT(9) BIT 47 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CR1_START BIT(8) BIT 48 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CR1_PE BIT(0) BIT 53 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CR2_ITBUFEN BIT(10) BIT 54 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CR2_ITEVTEN BIT(9) BIT 55 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CR2_ITERREN BIT(8) BIT 61 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_SR1_AF BIT(10) BIT 62 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_SR1_ARLO BIT(9) BIT 63 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_SR1_BERR BIT(8) BIT 64 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_SR1_TXE BIT(7) BIT 65 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_SR1_RXNE BIT(6) BIT 66 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_SR1_BTF BIT(2) BIT 67 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_SR1_ADDR BIT(1) BIT 68 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_SR1_SB BIT(0) BIT 79 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_SR2_BUSY BIT(1) BIT 84 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CCR_FS BIT(15) BIT 85 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CCR_DUTY BIT(14) BIT 51 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_PECEN BIT(23) BIT 52 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_SBC BIT(16) BIT 53 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_RXDMAEN BIT(15) BIT 54 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_TXDMAEN BIT(14) BIT 55 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_ANFOFF BIT(12) BIT 56 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_ERRIE BIT(7) BIT 57 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_TCIE BIT(6) BIT 58 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_STOPIE BIT(5) BIT 59 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_NACKIE BIT(4) BIT 60 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_ADDRIE BIT(3) BIT 61 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_RXIE BIT(2) BIT 62 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_TXIE BIT(1) BIT 63 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR1_PE BIT(0) BIT 77 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_PECBYTE BIT(26) BIT 78 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_RELOAD BIT(24) BIT 81 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_NACK BIT(15) BIT 82 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_STOP BIT(14) BIT 83 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_START BIT(13) BIT 84 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_HEAD10R BIT(12) BIT 85 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_ADD10 BIT(11) BIT 86 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_RD_WRN BIT(10) BIT 94 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_OAR1_OA1EN BIT(15) BIT 95 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_OAR1_OA1MODE BIT(10) BIT 107 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_OAR2_OA2EN BIT(15) BIT 120 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_DIR BIT(16) BIT 121 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_BUSY BIT(15) BIT 122 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_PECERR BIT(11) BIT 123 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_ARLO BIT(9) BIT 124 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_BERR BIT(8) BIT 125 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_TCR BIT(7) BIT 126 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_TC BIT(6) BIT 127 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_STOPF BIT(5) BIT 128 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_NACKF BIT(4) BIT 129 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_ADDR BIT(3) BIT 130 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_RXNE BIT(2) BIT 131 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_TXIS BIT(1) BIT 132 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_TXE BIT(0) BIT 135 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ICR_PECCF BIT(11) BIT 136 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ICR_ARLOCF BIT(9) BIT 137 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ICR_BERRCF BIT(8) BIT 138 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ICR_STOPCF BIT(5) BIT 139 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ICR_NACKCF BIT(4) BIT 140 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ICR_ADDRCF BIT(3) BIT 163 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_PRESC_MAX BIT(4) BIT 164 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_SCLDEL_MAX BIT(4) BIT 165 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_SDADEL_MAX BIT(4) BIT 166 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_SCLH_MAX BIT(8) BIT 167 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_SCLL_MAX BIT(8) BIT 48 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_CTRL_START_TRANS BIT(7) BIT 49 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_CTRL_ABORT_TRANS BIT(6) BIT 50 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_CTRL_GLOBAL_INT_ENB BIT(1) BIT 51 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_CTRL_SOFT_RST BIT(0) BIT 60 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_INTS_LOAD_BSY BIT(2) BIT 61 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_INTS_TRANS_ERR BIT(1) BIT 62 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_INTS_TRANS_OVER BIT(0) BIT 65 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_DLEN_READ BIT(4) BIT 69 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_LCR_SCL_STATE BIT(5) BIT 70 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_LCR_SDA_STATE BIT(4) BIT 71 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_LCR_SCL_CTL BIT(3) BIT 72 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_LCR_SCL_CTL_EN BIT(2) BIT 73 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_LCR_SDA_CTL BIT(1) BIT 74 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_LCR_SDA_CTL_EN BIT(0) BIT 77 drivers/i2c/busses/i2c-sun6i-p2wi.c #define P2WI_PMCR_PMU_INIT_SEND BIT(31) BIT 36 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer BIT 37 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BSR_GCA BIT(1) // General Call Address BIT 38 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BSR_AAS BIT(2) // Address as Slave BIT 39 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive BIT 40 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BSR_LRB BIT(4) // Last Received Bit BIT 41 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BSR_AL BIT(5) // Arbitration Lost BIT 42 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BSR_RSC BIT(6) // Repeated Start Cond. BIT 43 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BSR_BB BIT(7) // Bus Busy BIT 45 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BCR_INT BIT(0) // Interrupt BIT 46 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BCR_INTE BIT(1) // Interrupt Enable BIT 47 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BCR_GCAA BIT(2) // Gen. Call Access Ack. BIT 48 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BCR_ACK BIT(3) // Acknowledge BIT 49 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BCR_MSS BIT(4) // Master Slave Select BIT 50 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BCR_SCC BIT(5) // Start Condition Cont. BIT 51 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BCR_BEIE BIT(6) // Bus Error Int Enable BIT 52 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BCR_BER BIT(7) // Bus Error BIT 55 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_CCR_EN BIT(5) // Enable BIT 56 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_CCR_FM BIT(6) // Speed Mode Select BIT 60 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BC2R_SCLL BIT(0) // SCL Low Drive BIT 61 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BC2R_SDAL BIT(1) // SDA Low Drive BIT 62 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BC2R_SCLS BIT(4) // SCL Status BIT 63 drivers/i2c/busses/i2c-synquacer.c #define SYNQUACER_I2C_BC2R_SDAS BIT(5) // SDA Status BIT 31 drivers/i2c/busses/i2c-tegra.c #define I2C_CNFG_PACKET_MODE_EN BIT(10) BIT 32 drivers/i2c/busses/i2c-tegra.c #define I2C_CNFG_NEW_MASTER_FSM BIT(11) BIT 33 drivers/i2c/busses/i2c-tegra.c #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) BIT 36 drivers/i2c/busses/i2c-tegra.c #define I2C_SL_CNFG_NACK BIT(1) BIT 37 drivers/i2c/busses/i2c-tegra.c #define I2C_SL_CNFG_NEWSL BIT(2) BIT 44 drivers/i2c/busses/i2c-tegra.c #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) BIT 45 drivers/i2c/busses/i2c-tegra.c #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) BIT 55 drivers/i2c/busses/i2c-tegra.c #define I2C_INT_BUS_CLR_DONE BIT(11) BIT 56 drivers/i2c/busses/i2c-tegra.c #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) BIT 57 drivers/i2c/busses/i2c-tegra.c #define I2C_INT_NO_ACK BIT(3) BIT 58 drivers/i2c/busses/i2c-tegra.c #define I2C_INT_ARBITRATION_LOST BIT(2) BIT 59 drivers/i2c/busses/i2c-tegra.c #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) BIT 60 drivers/i2c/busses/i2c-tegra.c #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) BIT 65 drivers/i2c/busses/i2c-tegra.c #define DVC_CTRL_REG1_INTR_EN BIT(10) BIT 67 drivers/i2c/busses/i2c-tegra.c #define DVC_CTRL_REG3_SW_PROG BIT(26) BIT 68 drivers/i2c/busses/i2c-tegra.c #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) BIT 70 drivers/i2c/busses/i2c-tegra.c #define DVC_STATUS_I2C_DONE_INTR BIT(30) BIT 73 drivers/i2c/busses/i2c-tegra.c #define I2C_ERR_NO_ACK BIT(0) BIT 74 drivers/i2c/busses/i2c-tegra.c #define I2C_ERR_ARBITRATION_LOST BIT(1) BIT 75 drivers/i2c/busses/i2c-tegra.c #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) BIT 76 drivers/i2c/busses/i2c-tegra.c #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) BIT 81 drivers/i2c/busses/i2c-tegra.c #define PACKET_HEADER0_PROTOCOL_I2C BIT(4) BIT 83 drivers/i2c/busses/i2c-tegra.c #define I2C_HEADER_CONT_ON_NAK BIT(21) BIT 84 drivers/i2c/busses/i2c-tegra.c #define I2C_HEADER_READ BIT(19) BIT 85 drivers/i2c/busses/i2c-tegra.c #define I2C_HEADER_10BIT_ADDR BIT(18) BIT 86 drivers/i2c/busses/i2c-tegra.c #define I2C_HEADER_IE_ENABLE BIT(17) BIT 87 drivers/i2c/busses/i2c-tegra.c #define I2C_HEADER_REPEAT_START BIT(16) BIT 88 drivers/i2c/busses/i2c-tegra.c #define I2C_HEADER_CONTINUE_XFER BIT(15) BIT 94 drivers/i2c/busses/i2c-tegra.c #define I2C_BC_STOP_COND BIT(2) BIT 95 drivers/i2c/busses/i2c-tegra.c #define I2C_BC_TERMINATE BIT(1) BIT 96 drivers/i2c/busses/i2c-tegra.c #define I2C_BC_ENABLE BIT(0) BIT 98 drivers/i2c/busses/i2c-tegra.c #define I2C_BC_STATUS BIT(0) BIT 101 drivers/i2c/busses/i2c-tegra.c #define I2C_MSTR_CONFIG_LOAD BIT(0) BIT 104 drivers/i2c/busses/i2c-tegra.c #define I2C_MST_CORE_CLKEN_OVR BIT(0) BIT 109 drivers/i2c/busses/i2c-tegra.c #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) BIT 110 drivers/i2c/busses/i2c-tegra.c #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) BIT 15 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */ BIT 16 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */ BIT 17 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */ BIT 18 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */ BIT 20 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */ BIT 21 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */ BIT 31 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */ BIT 32 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */ BIT 33 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */ BIT 34 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */ BIT 35 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */ BIT 36 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */ BIT 37 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */ BIT 38 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */ BIT 40 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */ BIT 41 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */ BIT 42 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */ BIT 43 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */ BIT 44 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */ BIT 45 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */ BIT 46 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */ BIT 48 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */ BIT 49 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */ BIT 50 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */ BIT 52 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */ BIT 53 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */ BIT 54 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */ BIT 55 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */ BIT 62 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */ BIT 63 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */ BIT 70 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_RD BIT(0) BIT 71 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_STOP BIT(1) BIT 72 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_MANUAL_NACK BIT(2) BIT 73 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_BYTE_WISE BIT(3) BIT 74 drivers/i2c/busses/i2c-uniphier-f.c #define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4) BIT 14 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DTRM_IRQEN BIT(11) /* enable interrupt */ BIT 15 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DTRM_STA BIT(10) /* start condition */ BIT 16 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DTRM_STO BIT(9) /* stop condition */ BIT 17 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DTRM_NACK BIT(8) /* do not return ACK */ BIT 18 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DTRM_RD BIT(0) /* read transaction */ BIT 20 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DREC_MST BIT(14) /* 1 = master, 0 = slave */ BIT 21 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DREC_TX BIT(13) /* 1 = transmit, 0 = receive */ BIT 22 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DREC_STS BIT(12) /* stop condition detected */ BIT 23 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DREC_LRB BIT(11) /* no ACK */ BIT 24 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DREC_LAB BIT(9) /* arbitration lost */ BIT 25 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_DREC_BBN BIT(8) /* bus not busy */ BIT 29 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_BRST_FOEN BIT(1) /* normal operation */ BIT 30 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_BRST_RSCL BIT(0) /* release SCL */ BIT 33 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_BSTS_SDA BIT(1) /* readback of SDA line */ BIT 34 drivers/i2c/busses/i2c-uniphier.c #define UNIPHIER_I2C_BSTS_SCL BIT(0) /* readback of SCL line */ BIT 97 drivers/i2c/busses/i2c-xgene-slimpro.c #define PCC_STS_CMD_COMPLETE BIT(0) BIT 98 drivers/i2c/busses/i2c-xgene-slimpro.c #define PCC_STS_SCI_DOORBELL BIT(1) BIT 99 drivers/i2c/busses/i2c-xgene-slimpro.c #define PCC_STS_ERR BIT(2) BIT 100 drivers/i2c/busses/i2c-xgene-slimpro.c #define PCC_STS_PLAT_NOTIFY BIT(3) BIT 101 drivers/i2c/busses/i2c-xgene-slimpro.c #define PCC_CMD_GENERATE_DB_INT BIT(15) BIT 41 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_STATUS_BUSY BIT(0) BIT 43 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_CMD_START BIT(7) BIT 44 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_CMD_STOP BIT(6) BIT 45 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_CMD_READ BIT(5) BIT 46 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_CMD_WRITE BIT(4) BIT 47 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_CMD_ACK BIT(3) BIT 51 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_CTRL_RST BIT(8) BIT 52 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_CTRL_EN BIT(6) BIT 53 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_CTRL_MASTER BIT(4) BIT 54 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_CTRL_FIFORD BIT(1) BIT 55 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_CTRL_ADDMODE BIT(0) BIT 57 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_INTEN_NACKADDR BIT(25) BIT 58 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_INTEN_SADDR BIT(13) BIT 59 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_INTEN_DATADONE BIT(12) BIT 60 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_INTEN_ARLOST BIT(11) BIT 61 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4) BIT 62 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3) BIT 63 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_INTEN_MFIFOHI BIT(2) BIT 64 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_INTEN_BUSERR BIT(0) BIT 68 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_MFIFOCTRL_RST BIT(16) BIT 70 drivers/i2c/busses/i2c-xlp9xx.c #define XLP9XX_I2C_SLAVEADDR_RW BIT(0) BIT 27 drivers/i2c/busses/i2c-zx2967.c #define I2C_MASTER BIT(0) BIT 28 drivers/i2c/busses/i2c-zx2967.c #define I2C_ADDR_MODE_TEN BIT(1) BIT 29 drivers/i2c/busses/i2c-zx2967.c #define I2C_IRQ_MSK_ENABLE BIT(3) BIT 30 drivers/i2c/busses/i2c-zx2967.c #define I2C_RW_READ BIT(4) BIT 31 drivers/i2c/busses/i2c-zx2967.c #define I2C_CMB_RW_EN BIT(5) BIT 32 drivers/i2c/busses/i2c-zx2967.c #define I2C_START BIT(6) BIT 39 drivers/i2c/busses/i2c-zx2967.c #define I2C_WFIFO_RESET BIT(7) BIT 40 drivers/i2c/busses/i2c-zx2967.c #define I2C_RFIFO_RESET BIT(7) BIT 42 drivers/i2c/busses/i2c-zx2967.c #define I2C_IRQ_ACK_CLEAR BIT(7) BIT 45 drivers/i2c/busses/i2c-zx2967.c #define I2C_TRANS_DONE BIT(0) BIT 46 drivers/i2c/busses/i2c-zx2967.c #define I2C_SR_EDEVICE BIT(1) BIT 47 drivers/i2c/busses/i2c-zx2967.c #define I2C_SR_EDATA BIT(2) BIT 41 drivers/i2c/i2c-slave-eeprom.c #define I2C_SLAVE_FLAG_ADDR16 BIT(16) BIT 42 drivers/i2c/i2c-slave-eeprom.c #define I2C_SLAVE_FLAG_RO BIT(17) BIT 168 drivers/i2c/muxes/i2c-mux-gpio.c if (initial_state & BIT(i)) BIT 31 drivers/i2c/muxes/i2c-mux-ltc4306.c #define LTC_DOWNSTREAM_ACCL_EN BIT(6) BIT 32 drivers/i2c/muxes/i2c-mux-ltc4306.c #define LTC_UPSTREAM_ACCL_EN BIT(7) BIT 86 drivers/i2c/muxes/i2c-mux-ltc4306.c return !!(val & BIT(1 - offset)); BIT 94 drivers/i2c/muxes/i2c-mux-ltc4306.c regmap_update_bits(data->regmap, LTC_REG_CONFIG, BIT(5 - offset), BIT 95 drivers/i2c/muxes/i2c-mux-ltc4306.c value ? BIT(5 - offset) : 0); BIT 109 drivers/i2c/muxes/i2c-mux-ltc4306.c return !!(val & BIT(7 - offset)); BIT 118 drivers/i2c/muxes/i2c-mux-ltc4306.c BIT(7 - offset), BIT(7 - offset)); BIT 128 drivers/i2c/muxes/i2c-mux-ltc4306.c BIT(7 - offset), 0); BIT 142 drivers/i2c/muxes/i2c-mux-ltc4306.c val = BIT(4 - offset); BIT 149 drivers/i2c/muxes/i2c-mux-ltc4306.c BIT(4 - offset), val); BIT 183 drivers/i2c/muxes/i2c-mux-ltc4306.c LTC_SWITCH_MASK, BIT(7 - chan)); BIT 335 drivers/i2c/muxes/i2c-mux-pca954x.c if (ret & BIT(PCA954X_IRQ_OFFSET + i)) { BIT 392 drivers/i3c/master.c i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR ^ BIT(i), BIT 1932 drivers/i3c/master.c #define OF_I3C_REG1_IS_I2C_DEV BIT(31) BIT 25 drivers/i3c/master/dw-i3c-master.c #define DEV_CTRL_ENABLE BIT(31) BIT 26 drivers/i3c/master/dw-i3c-master.c #define DEV_CTRL_RESUME BIT(30) BIT 27 drivers/i3c/master/dw-i3c-master.c #define DEV_CTRL_HOT_JOIN_NACK BIT(8) BIT 28 drivers/i3c/master/dw-i3c-master.c #define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7) BIT 31 drivers/i3c/master/dw-i3c-master.c #define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31) BIT 36 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_TOC BIT(30) BIT 37 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_READ_TRANSFER BIT(28) BIT 38 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_SDAP BIT(27) BIT 39 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_ROC BIT(26) BIT 42 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_CP BIT(15) BIT 53 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5) BIT 54 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4) BIT 55 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3) BIT 90 drivers/i3c/master/dw-i3c-master.c #define RESET_CTRL_IBI_QUEUE BIT(5) BIT 91 drivers/i3c/master/dw-i3c-master.c #define RESET_CTRL_RX_FIFO BIT(4) BIT 92 drivers/i3c/master/dw-i3c-master.c #define RESET_CTRL_TX_FIFO BIT(3) BIT 93 drivers/i3c/master/dw-i3c-master.c #define RESET_CTRL_RESP_QUEUE BIT(2) BIT 94 drivers/i3c/master/dw-i3c-master.c #define RESET_CTRL_CMD_QUEUE BIT(1) BIT 95 drivers/i3c/master/dw-i3c-master.c #define RESET_CTRL_SOFT BIT(0) BIT 102 drivers/i3c/master/dw-i3c-master.c #define INTR_BUSOWNER_UPDATE_STAT BIT(13) BIT 103 drivers/i3c/master/dw-i3c-master.c #define INTR_IBI_UPDATED_STAT BIT(12) BIT 104 drivers/i3c/master/dw-i3c-master.c #define INTR_READ_REQ_RECV_STAT BIT(11) BIT 105 drivers/i3c/master/dw-i3c-master.c #define INTR_DEFSLV_STAT BIT(10) BIT 106 drivers/i3c/master/dw-i3c-master.c #define INTR_TRANSFER_ERR_STAT BIT(9) BIT 107 drivers/i3c/master/dw-i3c-master.c #define INTR_DYN_ADDR_ASSGN_STAT BIT(8) BIT 108 drivers/i3c/master/dw-i3c-master.c #define INTR_CCC_UPDATED_STAT BIT(6) BIT 109 drivers/i3c/master/dw-i3c-master.c #define INTR_TRANSFER_ABORT_STAT BIT(5) BIT 110 drivers/i3c/master/dw-i3c-master.c #define INTR_RESP_READY_STAT BIT(4) BIT 111 drivers/i3c/master/dw-i3c-master.c #define INTR_CMD_QUEUE_READY_STAT BIT(3) BIT 112 drivers/i3c/master/dw-i3c-master.c #define INTR_IBI_THLD_STAT BIT(2) BIT 113 drivers/i3c/master/dw-i3c-master.c #define INTR_RX_THLD_STAT BIT(1) BIT 114 drivers/i3c/master/dw-i3c-master.c #define INTR_TX_THLD_STAT BIT(0) BIT 187 drivers/i3c/master/dw-i3c-master.c #define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31) BIT 774 drivers/i3c/master/dw-i3c-master.c if (olddevs & BIT(pos)) BIT 813 drivers/i3c/master/dw-i3c-master.c if (newdevs & BIT(pos)) BIT 929 drivers/i3c/master/dw-i3c-master.c master->free_pos &= ~BIT(pos); BIT 951 drivers/i3c/master/dw-i3c-master.c master->free_pos |= BIT(data->index); BIT 1037 drivers/i3c/master/dw-i3c-master.c master->free_pos &= ~BIT(pos); BIT 1060 drivers/i3c/master/dw-i3c-master.c master->free_pos |= BIT(data->index); BIT 31 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_ECC_CHK BIT(28) BIT 32 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_INTEG_CHK BIT(27) BIT 33 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_CSR_DAP_CHK BIT(26) BIT 34 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_TRANS_TOUT_CHK BIT(25) BIT 35 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_PROT_FAULTS_CHK BIT(24) BIT 39 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_SUPPORTS_DDR BIT(5) BIT 40 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_SEC_MASTER BIT(4) BIT 59 drivers/i3c/master/i3c-master-cdns.c #define CTRL_DEV_EN BIT(31) BIT 60 drivers/i3c/master/i3c-master-cdns.c #define CTRL_HALT_EN BIT(30) BIT 61 drivers/i3c/master/i3c-master-cdns.c #define CTRL_MCS BIT(29) BIT 62 drivers/i3c/master/i3c-master-cdns.c #define CTRL_MCS_EN BIT(28) BIT 63 drivers/i3c/master/i3c-master-cdns.c #define CTRL_HJ_DISEC BIT(8) BIT 64 drivers/i3c/master/i3c-master-cdns.c #define CTRL_MST_ACK BIT(7) BIT 65 drivers/i3c/master/i3c-master-cdns.c #define CTRL_HJ_ACK BIT(6) BIT 66 drivers/i3c/master/i3c-master-cdns.c #define CTRL_HJ_INIT BIT(5) BIT 67 drivers/i3c/master/i3c-master-cdns.c #define CTRL_MST_INIT BIT(4) BIT 68 drivers/i3c/master/i3c-master-cdns.c #define CTRL_AHDR_OPT BIT(3) BIT 90 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_HALTED BIT(18) BIT 91 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_MR_DONE BIT(17) BIT 92 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_IMM_COMP BIT(16) BIT 93 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_TX_THR BIT(15) BIT 94 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_TX_OVF BIT(14) BIT 95 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_IBID_THR BIT(12) BIT 96 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_IBID_UNF BIT(11) BIT 97 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_IBIR_THR BIT(10) BIT 98 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_IBIR_UNF BIT(9) BIT 99 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_IBIR_OVF BIT(8) BIT 100 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_RX_THR BIT(7) BIT 101 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_RX_UNF BIT(6) BIT 102 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_CMDD_EMP BIT(5) BIT 103 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_CMDD_THR BIT(4) BIT 104 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_CMDD_OVF BIT(3) BIT 105 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_CMDR_THR BIT(2) BIT 106 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_CMDR_UNF BIT(1) BIT 107 drivers/i3c/master/i3c-master-cdns.c #define MST_INT_CMDR_OVF BIT(0) BIT 110 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_IDLE BIT(18) BIT 111 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_HALTED BIT(17) BIT 112 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_MASTER_MODE BIT(16) BIT 113 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_TX_FULL BIT(13) BIT 114 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_IBID_FULL BIT(12) BIT 115 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_IBIR_FULL BIT(11) BIT 116 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_RX_FULL BIT(10) BIT 117 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_CMDD_FULL BIT(9) BIT 118 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_CMDR_FULL BIT(8) BIT 119 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_TX_EMP BIT(5) BIT 120 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_IBID_EMP BIT(4) BIT 121 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_IBIR_EMP BIT(3) BIT 122 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_RX_EMP BIT(2) BIT 123 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_CMDD_EMP BIT(1) BIT 124 drivers/i3c/master/i3c-master-cdns.c #define MST_STATUS0_CMDR_EMP BIT(0) BIT 146 drivers/i3c/master/i3c-master-cdns.c #define IBIR_ACKED BIT(12) BIT 148 drivers/i3c/master/i3c-master-cdns.c #define IBIR_ERROR BIT(7) BIT 160 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_TM BIT(20) BIT 161 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_ERROR BIT(19) BIT 162 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_EVENT_UP BIT(18) BIT 163 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_HJ_DONE BIT(17) BIT 164 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_MR_DONE BIT(16) BIT 165 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_DA_UPD BIT(15) BIT 166 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_SDR_FAIL BIT(14) BIT 167 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_DDR_FAIL BIT(13) BIT 168 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_M_RD_ABORT BIT(12) BIT 169 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_DDR_RX_THR BIT(11) BIT 170 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_DDR_TX_THR BIT(10) BIT 171 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_SDR_RX_THR BIT(9) BIT 172 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_SDR_TX_THR BIT(8) BIT 173 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_DDR_RX_UNF BIT(7) BIT 174 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_DDR_TX_OVF BIT(6) BIT 175 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_SDR_RX_UNF BIT(5) BIT 176 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_SDR_TX_OVF BIT(4) BIT 177 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_DDR_RD_COMP BIT(3) BIT 178 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_DDR_WR_COMP BIT(2) BIT 179 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_SDR_RD_COMP BIT(1) BIT 180 drivers/i3c/master/i3c-master-cdns.c #define SLV_INT_SDR_WR_COMP BIT(0) BIT 188 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_VEN_TM BIT(19) BIT 189 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_HJ_DIS BIT(18) BIT 190 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_MR_DIS BIT(17) BIT 191 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_PROT_ERR BIT(16) BIT 193 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_HAS_DA BIT(8) BIT 194 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_DDR_RX_FULL BIT(7) BIT 195 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_DDR_TX_FULL BIT(6) BIT 196 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_DDR_RX_EMPTY BIT(5) BIT 197 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_DDR_TX_EMPTY BIT(4) BIT 198 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_SDR_RX_FULL BIT(3) BIT 199 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_SDR_TX_FULL BIT(2) BIT 200 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_SDR_RX_EMPTY BIT(1) BIT 201 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_SDR_TX_EMPTY BIT(0) BIT 204 drivers/i3c/master/i3c-master-cdns.c #define CMD0_FIFO_IS_DDR BIT(31) BIT 205 drivers/i3c/master/i3c-master-cdns.c #define CMD0_FIFO_IS_CCC BIT(30) BIT 206 drivers/i3c/master/i3c-master-cdns.c #define CMD0_FIFO_BCH BIT(29) BIT 212 drivers/i3c/master/i3c-master-cdns.c #define CMD0_FIFO_SBCA BIT(26) BIT 213 drivers/i3c/master/i3c-master-cdns.c #define CMD0_FIFO_RSBC BIT(25) BIT 214 drivers/i3c/master/i3c-master-cdns.c #define CMD0_FIFO_IS_10B BIT(24) BIT 218 drivers/i3c/master/i3c-master-cdns.c #define CMD0_FIFO_RNW BIT(0) BIT 230 drivers/i3c/master/i3c-master-cdns.c #define IMD_CMD0_RNW BIT(0) BIT 256 drivers/i3c/master/i3c-master-cdns.c #define FLUSH_IBI_RESP BIT(23) BIT 257 drivers/i3c/master/i3c-master-cdns.c #define FLUSH_CMD_RESP BIT(22) BIT 258 drivers/i3c/master/i3c-master-cdns.c #define FLUSH_SLV_DDR_RX_FIFO BIT(22) BIT 259 drivers/i3c/master/i3c-master-cdns.c #define FLUSH_SLV_DDR_TX_FIFO BIT(21) BIT 260 drivers/i3c/master/i3c-master-cdns.c #define FLUSH_IMM_FIFO BIT(20) BIT 261 drivers/i3c/master/i3c-master-cdns.c #define FLUSH_IBI_FIFO BIT(19) BIT 262 drivers/i3c/master/i3c-master-cdns.c #define FLUSH_RX_FIFO BIT(18) BIT 263 drivers/i3c/master/i3c-master-cdns.c #define FLUSH_TX_FIFO BIT(17) BIT 264 drivers/i3c/master/i3c-master-cdns.c #define FLUSH_CMD_FIFO BIT(16) BIT 277 drivers/i3c/master/i3c-master-cdns.c #define DEVS_CTRL_DEV_CLR(dev) BIT(16 + (dev)) BIT 278 drivers/i3c/master/i3c-master-cdns.c #define DEVS_CTRL_DEV_ACTIVE(dev) BIT(dev) BIT 283 drivers/i3c/master/i3c-master-cdns.c #define DEV_ID_RR0_LVR_EXT_ADDR BIT(11) BIT 284 drivers/i3c/master/i3c-master-cdns.c #define DEV_ID_RR0_HDR_CAP BIT(10) BIT 285 drivers/i3c/master/i3c-master-cdns.c #define DEV_ID_RR0_IS_I3C BIT(9) BIT 309 drivers/i3c/master/i3c-master-cdns.c #define SIR_MAP_DEV_SLOW BIT(13) BIT 313 drivers/i3c/master/i3c-master-cdns.c #define SIR_MAP_DEV_ACK BIT(0) BIT 328 drivers/i3c/master/i3c-master-cdns.c #define ASF_INTEGRITY_ERR BIT(6) BIT 329 drivers/i3c/master/i3c-master-cdns.c #define ASF_PROTOCOL_ERR BIT(5) BIT 330 drivers/i3c/master/i3c-master-cdns.c #define ASF_TRANS_TIMEOUT_ERR BIT(4) BIT 331 drivers/i3c/master/i3c-master-cdns.c #define ASF_CSR_ERR BIT(3) BIT 332 drivers/i3c/master/i3c-master-cdns.c #define ASF_DAP_ERR BIT(2) BIT 333 drivers/i3c/master/i3c-master-cdns.c #define ASF_SRAM_UNCORR_ERR BIT(1) BIT 334 drivers/i3c/master/i3c-master-cdns.c #define ASF_SRAM_CORR_ERR BIT(0) BIT 346 drivers/i3c/master/i3c-master-cdns.c #define ASF_TRANS_TOUT_EN BIT(31) BIT 351 drivers/i3c/master/i3c-master-cdns.c #define ASF_TRANS_TOUT_FAULT_APB BIT(3) BIT 352 drivers/i3c/master/i3c-master-cdns.c #define ASF_TRANS_TOUT_FAULT_SCL_LOW BIT(2) BIT 353 drivers/i3c/master/i3c-master-cdns.c #define ASF_TRANS_TOUT_FAULT_SCL_HIGH BIT(1) BIT 354 drivers/i3c/master/i3c-master-cdns.c #define ASF_TRANS_TOUT_FAULT_FSCL_HIGH BIT(0) BIT 358 drivers/i3c/master/i3c-master-cdns.c #define ASF_PROTO_FAULT_SLVSDR_RD_ABORT BIT(31) BIT 359 drivers/i3c/master/i3c-master-cdns.c #define ASF_PROTO_FAULT_SLVDDR_FAIL BIT(30) BIT 360 drivers/i3c/master/i3c-master-cdns.c #define ASF_PROTO_FAULT_S(x) BIT(16 + (x)) BIT 361 drivers/i3c/master/i3c-master-cdns.c #define ASF_PROTO_FAULT_MSTSDR_RD_ABORT BIT(15) BIT 362 drivers/i3c/master/i3c-master-cdns.c #define ASF_PROTO_FAULT_MSTDDR_FAIL BIT(14) BIT 363 drivers/i3c/master/i3c-master-cdns.c #define ASF_PROTO_FAULT_M(x) BIT(x) BIT 918 drivers/i3c/master/i3c-master-cdns.c activedevs &= ~BIT(0); BIT 960 drivers/i3c/master/i3c-master-cdns.c master->free_rr_slots &= ~BIT(slot); BIT 983 drivers/i3c/master/i3c-master-cdns.c master->free_rr_slots |= BIT(data->id); BIT 1003 drivers/i3c/master/i3c-master-cdns.c master->free_rr_slots &= ~BIT(slot); BIT 1025 drivers/i3c/master/i3c-master-cdns.c master->free_rr_slots |= BIT(data->id); BIT 1133 drivers/i3c/master/i3c-master-cdns.c olddevs |= BIT(0); BIT 229 drivers/ide/palm_bk3710.c writew(BIT(15), base + BK3710_IDETIMP); BIT 57 drivers/iio/accel/adis16201.c #define ADIS16201_MSC_CTRL_SELF_TEST_EN BIT(8) BIT 59 drivers/iio/accel/adis16201.c #define ADIS16201_MSC_CTRL_DATA_RDY_EN BIT(2) BIT 61 drivers/iio/accel/adis16201.c #define ADIS16201_MSC_CTRL_ACTIVE_DATA_RDY_HIGH BIT(1) BIT 63 drivers/iio/accel/adis16201.c #define ADIS16201_MSC_CTRL_DATA_RDY_DIO1 BIT(0) BIT 67 drivers/iio/accel/adis16201.c #define ADIS16201_DIAG_STAT_ALARM2 BIT(9) BIT 68 drivers/iio/accel/adis16201.c #define ADIS16201_DIAG_STAT_ALARM1 BIT(8) BIT 78 drivers/iio/accel/adis16201.c #define ADIS16201_GLOB_CMD_SW_RESET BIT(7) BIT 79 drivers/iio/accel/adis16201.c #define ADIS16201_GLOB_CMD_FACTORY_RESET BIT(1) BIT 81 drivers/iio/accel/adis16201.c #define ADIS16201_ERROR_ACTIVE BIT(14) BIT 212 drivers/iio/accel/adis16201.c BIT(IIO_CHAN_INFO_CALIBBIAS), 0, 14), BIT 214 drivers/iio/accel/adis16201.c BIT(IIO_CHAN_INFO_CALIBBIAS), 0, 14), BIT 217 drivers/iio/accel/adis16201.c BIT(IIO_CHAN_INFO_CALIBBIAS), 0, 14), BIT 219 drivers/iio/accel/adis16201.c BIT(IIO_CHAN_INFO_CALIBBIAS), 0, 14), BIT 247 drivers/iio/accel/adis16201.c .status_error_mask = BIT(ADIS16201_DIAG_STAT_SPI_FAIL_BIT) | BIT 248 drivers/iio/accel/adis16201.c BIT(ADIS16201_DIAG_STAT_FLASH_UPT_FAIL_BIT) | BIT 249 drivers/iio/accel/adis16201.c BIT(ADIS16201_DIAG_STAT_POWER_HIGH_BIT) | BIT 250 drivers/iio/accel/adis16201.c BIT(ADIS16201_DIAG_STAT_POWER_LOW_BIT), BIT 60 drivers/iio/accel/adis16209.c #define ADIS16209_MSC_CTRL_PWRUP_SELF_TEST BIT(10) BIT 61 drivers/iio/accel/adis16209.c #define ADIS16209_MSC_CTRL_SELF_TEST_EN BIT(8) BIT 62 drivers/iio/accel/adis16209.c #define ADIS16209_MSC_CTRL_DATA_RDY_EN BIT(2) BIT 64 drivers/iio/accel/adis16209.c #define ADIS16209_MSC_CTRL_ACTIVE_HIGH BIT(1) BIT 65 drivers/iio/accel/adis16209.c #define ADIS16209_MSC_CTRL_DATA_RDY_DIO2 BIT(0) BIT 68 drivers/iio/accel/adis16209.c #define ADIS16209_STAT_ALARM2 BIT(9) BIT 69 drivers/iio/accel/adis16209.c #define ADIS16209_STAT_ALARM1 BIT(8) BIT 79 drivers/iio/accel/adis16209.c #define ADIS16209_CMD_SW_RESET BIT(7) BIT 80 drivers/iio/accel/adis16209.c #define ADIS16209_CMD_CLEAR_STAT BIT(4) BIT 81 drivers/iio/accel/adis16209.c #define ADIS16209_CMD_FACTORY_CAL BIT(1) BIT 83 drivers/iio/accel/adis16209.c #define ADIS16209_ERROR_ACTIVE BIT(14) BIT 220 drivers/iio/accel/adis16209.c BIT(IIO_CHAN_INFO_CALIBBIAS), 0, 14), BIT 222 drivers/iio/accel/adis16209.c BIT(IIO_CHAN_INFO_CALIBBIAS), 0, 14), BIT 257 drivers/iio/accel/adis16209.c .status_error_mask = BIT(ADIS16209_STAT_SELFTEST_FAIL_BIT) | BIT 258 drivers/iio/accel/adis16209.c BIT(ADIS16209_STAT_SPI_FAIL_BIT) | BIT 259 drivers/iio/accel/adis16209.c BIT(ADIS16209_STAT_FLASH_UPT_FAIL_BIT) | BIT 260 drivers/iio/accel/adis16209.c BIT(ADIS16209_STAT_POWER_HIGH_BIT) | BIT 261 drivers/iio/accel/adis16209.c BIT(ADIS16209_STAT_POWER_LOW_BIT), BIT 36 drivers/iio/accel/adxl345_core.c #define ADXL345_POWER_CTL_MEASURE BIT(3) BIT 39 drivers/iio/accel/adxl345_core.c #define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */ BIT 73 drivers/iio/accel/adxl345_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 74 drivers/iio/accel/adxl345_core.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 75 drivers/iio/accel/adxl345_core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 76 drivers/iio/accel/adxl345_core.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 20 drivers/iio/accel/adxl345_spi.c .read_flag_mask = BIT(7) | BIT(6), BIT 104 drivers/iio/accel/adxl372.c #define ADXL372_FIFO_CTL_SAMPLES_MSK BIT(1) BIT 117 drivers/iio/accel/adxl372.c #define ADXL372_INT1_MAP_DATA_RDY_MSK BIT(0) BIT 119 drivers/iio/accel/adxl372.c #define ADXL372_INT1_MAP_FIFO_RDY_MSK BIT(1) BIT 121 drivers/iio/accel/adxl372.c #define ADXL372_INT1_MAP_FIFO_FULL_MSK BIT(2) BIT 123 drivers/iio/accel/adxl372.c #define ADXL372_INT1_MAP_FIFO_OVR_MSK BIT(3) BIT 125 drivers/iio/accel/adxl372.c #define ADXL372_INT1_MAP_INACT_MSK BIT(4) BIT 127 drivers/iio/accel/adxl372.c #define ADXL372_INT1_MAP_ACT_MSK BIT(5) BIT 129 drivers/iio/accel/adxl372.c #define ADXL372_INT1_MAP_AWAKE_MSK BIT(6) BIT 131 drivers/iio/accel/adxl372.c #define ADXL372_INT1_MAP_LOW_MSK BIT(7) BIT 216 drivers/iio/accel/adxl372.c { BIT(0), ADXL372_X_FIFO }, BIT 217 drivers/iio/accel/adxl372.c { BIT(1), ADXL372_Y_FIFO }, BIT 218 drivers/iio/accel/adxl372.c { BIT(2), ADXL372_Z_FIFO }, BIT 219 drivers/iio/accel/adxl372.c { BIT(0) | BIT(1), ADXL372_XY_FIFO }, BIT 220 drivers/iio/accel/adxl372.c { BIT(0) | BIT(2), ADXL372_XZ_FIFO }, BIT 221 drivers/iio/accel/adxl372.c { BIT(1) | BIT(2), ADXL372_YZ_FIFO }, BIT 222 drivers/iio/accel/adxl372.c { BIT(0) | BIT(1) | BIT(2), ADXL372_XYZ_FIFO }, BIT 230 drivers/iio/accel/adxl372.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 231 drivers/iio/accel/adxl372.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 232 drivers/iio/accel/adxl372.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT 233 drivers/iio/accel/adxl372.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ BIT 271 drivers/iio/accel/adxl372.c BIT(0), BIT(1), BIT(2), BIT 272 drivers/iio/accel/adxl372.c BIT(0) | BIT(1), BIT 273 drivers/iio/accel/adxl372.c BIT(0) | BIT(2), BIT 274 drivers/iio/accel/adxl372.c BIT(1) | BIT(2), BIT 275 drivers/iio/accel/adxl372.c BIT(0) | BIT(1) | BIT(2), BIT 20 drivers/iio/accel/adxl372_spi.c .read_flag_mask = BIT(0), BIT 72 drivers/iio/accel/bma180.c #define BMA180_DIS_WAKE_UP BIT(0) /* Disable wake up mode */ BIT 73 drivers/iio/accel/bma180.c #define BMA180_SLEEP BIT(1) /* 1 - chip will sleep */ BIT 74 drivers/iio/accel/bma180.c #define BMA180_EE_W BIT(4) /* Unlock writing to addr from 0x20 */ BIT 75 drivers/iio/accel/bma180.c #define BMA180_RESET_INT BIT(6) /* Reset pending interrupts */ BIT 78 drivers/iio/accel/bma180.c #define BMA180_NEW_DATA_INT BIT(1) /* Intr every new accel data is ready */ BIT 81 drivers/iio/accel/bma180.c #define BMA180_SMP_SKIP BIT(0) BIT 106 drivers/iio/accel/bma180.c #define BMA250_SUSPEND_MASK BIT(7) /* chip will sleep */ BIT 107 drivers/iio/accel/bma180.c #define BMA250_LOWPOWER_MASK BIT(6) BIT 108 drivers/iio/accel/bma180.c #define BMA250_DATA_INTEN_MASK BIT(4) BIT 109 drivers/iio/accel/bma180.c #define BMA250_INT1_DATA_MASK BIT(0) BIT 110 drivers/iio/accel/bma180.c #define BMA250_INT_RESET_MASK BIT(7) /* Reset pending interrupts */ BIT 589 drivers/iio/accel/bma180.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 590 drivers/iio/accel/bma180.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 591 drivers/iio/accel/bma180.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ BIT 604 drivers/iio/accel/bma180.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 605 drivers/iio/accel/bma180.c BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), \ BIT 40 drivers/iio/accel/bma220_spi.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 41 drivers/iio/accel/bma220_spi.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 93 drivers/iio/accel/bma220_spi.c BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), BIT 40 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0) BIT 41 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1) BIT 42 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2) BIT 43 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3) BIT 66 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) BIT 69 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) BIT 70 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1) BIT 71 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2) BIT 79 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0) BIT 80 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1) BIT 81 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) BIT 84 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) BIT 85 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5) BIT 86 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6) BIT 89 drivers/iio/accel/bmc150-accel-core.c #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) BIT 968 drivers/iio/accel/bmc150-accel-core.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 969 drivers/iio/accel/bmc150-accel-core.c BIT(IIO_EV_INFO_ENABLE) | BIT 970 drivers/iio/accel/bmc150-accel-core.c BIT(IIO_EV_INFO_PERIOD) BIT 977 drivers/iio/accel/bmc150-accel-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 978 drivers/iio/accel/bmc150-accel-core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 979 drivers/iio/accel/bmc150-accel-core.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 996 drivers/iio/accel/bmc150-accel-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 997 drivers/iio/accel/bmc150-accel-core.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 998 drivers/iio/accel/bmc150-accel-core.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 1103 drivers/iio/accel/bmc150-accel-core.c BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), BIT 144 drivers/iio/accel/cros_ec_accel_legacy.c BIT(IIO_CHAN_INFO_RAW) | \ BIT 145 drivers/iio/accel/cros_ec_accel_legacy.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 146 drivers/iio/accel/cros_ec_accel_legacy.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \ BIT 40 drivers/iio/accel/da280.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 41 drivers/iio/accel/da280.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 85 drivers/iio/accel/da311.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 86 drivers/iio/accel/da311.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 42 drivers/iio/accel/dmard06.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 43 drivers/iio/accel/dmard06.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 50 drivers/iio/accel/dmard06.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 51 drivers/iio/accel/dmard06.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 36 drivers/iio/accel/dmard09.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 37 drivers/iio/accel/dmard09.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 59 drivers/iio/accel/dmard10.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 60 drivers/iio/accel/dmard10.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 53 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 54 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 55 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 56 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 57 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 63 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 64 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 65 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 66 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 67 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 73 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 74 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 75 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 76 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 77 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 89 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 90 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 91 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 92 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 93 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 99 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 100 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 101 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 102 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 103 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 109 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 110 drivers/iio/accel/hid-sensor-accel-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 111 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 112 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 113 drivers/iio/accel/hid-sensor-accel-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 79 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7) BIT 80 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_CTRL1_BIT_RES BIT(6) BIT 81 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_CTRL1_BIT_DRDY BIT(5) BIT 82 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4) BIT 83 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3) BIT 84 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1) BIT 86 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_CTRL1_BIT_IEU BIT(2) /* KXTF9 */ BIT 87 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3) BIT 88 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4) BIT 89 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5) BIT 91 drivers/iio/accel/kxcjk-1013.c #define KXTF9_REG_TILT_BIT_LEFT_EDGE BIT(5) BIT 92 drivers/iio/accel/kxcjk-1013.c #define KXTF9_REG_TILT_BIT_RIGHT_EDGE BIT(4) BIT 93 drivers/iio/accel/kxcjk-1013.c #define KXTF9_REG_TILT_BIT_LOWER_EDGE BIT(3) BIT 94 drivers/iio/accel/kxcjk-1013.c #define KXTF9_REG_TILT_BIT_UPPER_EDGE BIT(2) BIT 95 drivers/iio/accel/kxcjk-1013.c #define KXTF9_REG_TILT_BIT_FACE_DOWN BIT(1) BIT 96 drivers/iio/accel/kxcjk-1013.c #define KXTF9_REG_TILT_BIT_FACE_UP BIT(0) BIT 103 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC1_BIT_TPS BIT(0) /* KXTF9 */ BIT 104 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1) BIT 105 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC1_MASK_TDTS (BIT(2) | BIT(3)) /* KXTF9 */ BIT 107 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC1_TAP_SINGLE BIT(2) BIT 108 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC1_TAP_DOUBLE BIT(3) BIT 109 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4) BIT 112 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0) BIT 113 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1) BIT 114 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2) BIT 115 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC2_BIT_YN BIT(3) BIT 116 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC2_BIT_XP BIT(4) BIT 117 drivers/iio/accel/kxcjk-1013.c #define KXCJK1013_REG_INT_SRC2_BIT_XN BIT(5) BIT 981 drivers/iio/accel/kxcjk-1013.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 982 drivers/iio/accel/kxcjk-1013.c BIT(IIO_EV_INFO_ENABLE) | BIT 983 drivers/iio/accel/kxcjk-1013.c BIT(IIO_EV_INFO_PERIOD) BIT 990 drivers/iio/accel/kxcjk-1013.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 991 drivers/iio/accel/kxcjk-1013.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 992 drivers/iio/accel/kxcjk-1013.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 44 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_C_MOT_LAT BIT(3) BIT 45 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_C_MOT_LEV BIT(4) BIT 48 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_C_LP_2000HZC BIT(5) BIT 49 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_C_LP_2000HZB BIT(6) BIT 50 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_C_LP_2000HZA (BIT(5)|BIT(6)) BIT 51 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_C_LP_1000HZ BIT(7) BIT 52 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_C_LP_500HZ (BIT(7)|BIT(5)) BIT 53 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_C_LP_100HZ (BIT(7)|BIT(6)) BIT 54 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_C_LP_50HZ (BIT(7)|BIT(6)|BIT(5)) BIT 58 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_B_CLK_HLD BIT(7) BIT 59 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_B_ENABLE BIT(6) BIT 60 drivers/iio/accel/kxsd9.c #define KXSD9_CTRL_B_ST BIT(5) /* Self-test */ BIT 279 drivers/iio/accel/kxsd9.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 280 drivers/iio/accel/kxsd9.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 281 drivers/iio/accel/kxsd9.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 300 drivers/iio/accel/kxsd9.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 45 drivers/iio/accel/mc3230.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 46 drivers/iio/accel/mc3230.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 32 drivers/iio/accel/mma7455_core.c #define MMA7455_STATUS_DRDY BIT(0) BIT 39 drivers/iio/accel/mma7455_core.c #define MMA7455_CTL1_DFBW_MASK BIT(7) BIT 40 drivers/iio/accel/mma7455_core.c #define MMA7455_CTL1_DFBW_125HZ BIT(7) BIT 206 drivers/iio/accel/mma7455_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 207 drivers/iio/accel/mma7455_core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT 208 drivers/iio/accel/mma7455_core.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 21 drivers/iio/accel/mma7660.c #define MMA7660_REG_OUT_BIT_ALERT BIT(6) BIT 24 drivers/iio/accel/mma7660.c #define MMA7660_REG_MODE_BIT_MODE BIT(0) BIT 25 drivers/iio/accel/mma7660.c #define MMA7660_REG_MODE_BIT_TON BIT(2) BIT 46 drivers/iio/accel/mma7660.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 47 drivers/iio/accel/mma7660.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 37 drivers/iio/accel/mma8452.c #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) BIT 48 drivers/iio/accel/mma8452.c #define MMA8452_DATA_CFG_HPF_MASK BIT(4) BIT 52 drivers/iio/accel/mma8452.c #define MMA8452_FF_MT_CFG_OAE BIT(6) BIT 53 drivers/iio/accel/mma8452.c #define MMA8452_FF_MT_CFG_ELE BIT(7) BIT 55 drivers/iio/accel/mma8452.c #define MMA8452_FF_MT_SRC_XHE BIT(1) BIT 56 drivers/iio/accel/mma8452.c #define MMA8452_FF_MT_SRC_YHE BIT(3) BIT 57 drivers/iio/accel/mma8452.c #define MMA8452_FF_MT_SRC_ZHE BIT(5) BIT 63 drivers/iio/accel/mma8452.c #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) BIT 64 drivers/iio/accel/mma8452.c #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) BIT 65 drivers/iio/accel/mma8452.c #define MMA8452_TRANSIENT_CFG_ELE BIT(4) BIT 67 drivers/iio/accel/mma8452.c #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) BIT 68 drivers/iio/accel/mma8452.c #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) BIT 69 drivers/iio/accel/mma8452.c #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) BIT 75 drivers/iio/accel/mma8452.c #define MMA8452_CTRL_ACTIVE BIT(0) BIT 80 drivers/iio/accel/mma8452.c #define MMA8452_CTRL_REG2_RST BIT(6) BIT 91 drivers/iio/accel/mma8452.c #define MMA8452_INT_DRDY BIT(0) BIT 92 drivers/iio/accel/mma8452.c #define MMA8452_INT_FF_MT BIT(2) BIT 93 drivers/iio/accel/mma8452.c #define MMA8452_INT_TRANS BIT(5) BIT 668 drivers/iio/accel/mma8452.c val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); BIT 669 drivers/iio/accel/mma8452.c val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); BIT 670 drivers/iio/accel/mma8452.c val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); BIT 673 drivers/iio/accel/mma8452.c val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); BIT 674 drivers/iio/accel/mma8452.c val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); BIT 675 drivers/iio/accel/mma8452.c val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); BIT 958 drivers/iio/accel/mma8452.c return !!(ret & BIT(chan->scan_index + BIT 993 drivers/iio/accel/mma8452.c val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); BIT 994 drivers/iio/accel/mma8452.c val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); BIT 995 drivers/iio/accel/mma8452.c val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); BIT 998 drivers/iio/accel/mma8452.c val |= BIT(chan->scan_index + BIT 1004 drivers/iio/accel/mma8452.c val &= ~BIT(chan->scan_index + BIT 1136 drivers/iio/accel/mma8452.c .mask_separate = BIT(IIO_EV_INFO_ENABLE), BIT 1137 drivers/iio/accel/mma8452.c .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | BIT 1138 drivers/iio/accel/mma8452.c BIT(IIO_EV_INFO_PERIOD) | BIT 1139 drivers/iio/accel/mma8452.c BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) BIT 1147 drivers/iio/accel/mma8452.c .mask_separate = BIT(IIO_EV_INFO_ENABLE), BIT 1148 drivers/iio/accel/mma8452.c .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | BIT 1149 drivers/iio/accel/mma8452.c BIT(IIO_EV_INFO_PERIOD) BIT 1157 drivers/iio/accel/mma8452.c .mask_separate = BIT(IIO_EV_INFO_ENABLE), BIT 1158 drivers/iio/accel/mma8452.c .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | BIT 1159 drivers/iio/accel/mma8452.c BIT(IIO_EV_INFO_PERIOD) | BIT 1160 drivers/iio/accel/mma8452.c BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) BIT 1168 drivers/iio/accel/mma8452.c .mask_separate = BIT(IIO_EV_INFO_ENABLE), BIT 1169 drivers/iio/accel/mma8452.c .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | BIT 1170 drivers/iio/accel/mma8452.c BIT(IIO_EV_INFO_PERIOD) BIT 1211 drivers/iio/accel/mma8452.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 1212 drivers/iio/accel/mma8452.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 1213 drivers/iio/accel/mma8452.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT 1214 drivers/iio/accel/mma8452.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 1215 drivers/iio/accel/mma8452.c BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ BIT 1216 drivers/iio/accel/mma8452.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ BIT 1233 drivers/iio/accel/mma8452.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 1234 drivers/iio/accel/mma8452.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 1235 drivers/iio/accel/mma8452.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT 1236 drivers/iio/accel/mma8452.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 1237 drivers/iio/accel/mma8452.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ BIT 28 drivers/iio/accel/mma9551.c #define MMA9551_TILT_ANGFLG BIT(7) BIT 303 drivers/iio/accel/mma9551.c .mask_separate = BIT(IIO_EV_INFO_ENABLE), BIT 304 drivers/iio/accel/mma9551.c .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE), BIT 311 drivers/iio/accel/mma9551.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 21 drivers/iio/accel/mma9551_core.c #define MMA9551_RESPONSE_COCO BIT(7) BIT 39 drivers/iio/accel/mma9551_core.c #define MMA9551_SLEEP_CFG_SNCEN BIT(0) BIT 40 drivers/iio/accel/mma9551_core.c #define MMA9551_SLEEP_CFG_FLEEN BIT(1) BIT 41 drivers/iio/accel/mma9551_core.c #define MMA9551_SLEEP_CFG_SCHEN BIT(2) BIT 21 drivers/iio/accel/mma9551_core.h #define MMA9551_RSC_PED BIT(21) BIT 37 drivers/iio/accel/mma9551_core.h .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 38 drivers/iio/accel/mma9551_core.h .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 28 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_CONFIG BIT(15) BIT 29 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_ACT_DBCNTM BIT(14) BIT 30 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_SLP_DBCNTM BIT(13) BIT 39 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_MALE BIT(7) BIT 51 drivers/iio/accel/mma9553.c #define MMA9553_MASK_STATUS_MRGFL BIT(15) BIT 52 drivers/iio/accel/mma9553.c #define MMA9553_MASK_STATUS_SUSPCHG BIT(14) BIT 53 drivers/iio/accel/mma9553.c #define MMA9553_MASK_STATUS_STEPCHG BIT(13) BIT 54 drivers/iio/accel/mma9553.c #define MMA9553_MASK_STATUS_ACTCHG BIT(12) BIT 55 drivers/iio/accel/mma9553.c #define MMA9553_MASK_STATUS_SUSP BIT(11) BIT 71 drivers/iio/accel/mma9553.c #define MMA9553_MAX_BITNUM MMA9553_STATUS_TO_BITNUM(BIT(16)) BIT 889 drivers/iio/accel/mma9553.c .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE), BIT 896 drivers/iio/accel/mma9553.c .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT 897 drivers/iio/accel/mma9553.c BIT(IIO_EV_INFO_VALUE) | BIT 898 drivers/iio/accel/mma9553.c BIT(IIO_EV_INFO_PERIOD), BIT 903 drivers/iio/accel/mma9553.c .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT 904 drivers/iio/accel/mma9553.c BIT(IIO_EV_INFO_VALUE) | BIT 905 drivers/iio/accel/mma9553.c BIT(IIO_EV_INFO_PERIOD), BIT 926 drivers/iio/accel/mma9553.c .info_mask_separate = BIT(IIO_CHAN_INFO_ENABLE) | \ BIT 927 drivers/iio/accel/mma9553.c BIT(IIO_CHAN_INFO_CALIBHEIGHT) | \ BIT 936 drivers/iio/accel/mma9553.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 937 drivers/iio/accel/mma9553.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBHEIGHT) | \ BIT 938 drivers/iio/accel/mma9553.c BIT(IIO_CHAN_INFO_ENABLE), \ BIT 951 drivers/iio/accel/mma9553.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 952 drivers/iio/accel/mma9553.c BIT(IIO_CHAN_INFO_ENABLE) | BIT 953 drivers/iio/accel/mma9553.c BIT(IIO_CHAN_INFO_DEBOUNCE_COUNT) | BIT 954 drivers/iio/accel/mma9553.c BIT(IIO_CHAN_INFO_DEBOUNCE_TIME), BIT 959 drivers/iio/accel/mma9553.c MMA9553_PEDOMETER_CHANNEL(IIO_DISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 964 drivers/iio/accel/mma9553.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 965 drivers/iio/accel/mma9553.c BIT(IIO_CHAN_INFO_SCALE) | BIT 966 drivers/iio/accel/mma9553.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 967 drivers/iio/accel/mma9553.c BIT(IIO_CHAN_INFO_ENABLE), BIT 968 drivers/iio/accel/mma9553.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBHEIGHT), BIT 971 drivers/iio/accel/mma9553.c MMA9553_PEDOMETER_CHANNEL(IIO_ENERGY, BIT(IIO_CHAN_INFO_RAW) | BIT 972 drivers/iio/accel/mma9553.c BIT(IIO_CHAN_INFO_SCALE) | BIT 973 drivers/iio/accel/mma9553.c BIT(IIO_CHAN_INFO_CALIBWEIGHT)), BIT 265 drivers/iio/accel/mxc4005.c BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), BIT 274 drivers/iio/accel/mxc4005.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 275 drivers/iio/accel/mxc4005.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 86 drivers/iio/accel/mxc6255.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 87 drivers/iio/accel/mxc6255.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 33 drivers/iio/accel/sca3000.c #define SCA3000_LOCKED BIT(5) BIT 34 drivers/iio/accel/sca3000.c #define SCA3000_EEPROM_CS_ERROR BIT(1) BIT 35 drivers/iio/accel/sca3000.c #define SCA3000_SPI_FRAME_ERROR BIT(0) BIT 49 drivers/iio/accel/sca3000.c #define SCA3000_REG_MODE_RING_BUF_ENABLE BIT(7) BIT 50 drivers/iio/accel/sca3000.c #define SCA3000_REG_MODE_RING_BUF_8BIT BIT(6) BIT 56 drivers/iio/accel/sca3000.c #define SCA3000_REG_MODE_FREE_FALL_DETECT BIT(4) BIT 72 drivers/iio/accel/sca3000.c #define SCA3000_REG_INT_STATUS_THREE_QUARTERS BIT(7) BIT 73 drivers/iio/accel/sca3000.c #define SCA3000_REG_INT_STATUS_HALF BIT(6) BIT 75 drivers/iio/accel/sca3000.c #define SCA3000_INT_STATUS_FREE_FALL BIT(3) BIT 76 drivers/iio/accel/sca3000.c #define SCA3000_INT_STATUS_Y_TRIGGER BIT(2) BIT 77 drivers/iio/accel/sca3000.c #define SCA3000_INT_STATUS_X_TRIGGER BIT(1) BIT 78 drivers/iio/accel/sca3000.c #define SCA3000_INT_STATUS_Z_TRIGGER BIT(0) BIT 108 drivers/iio/accel/sca3000.c #define SCA3000_MD_CTRL_OR_Y BIT(0) BIT 109 drivers/iio/accel/sca3000.c #define SCA3000_MD_CTRL_OR_X BIT(1) BIT 110 drivers/iio/accel/sca3000.c #define SCA3000_MD_CTRL_OR_Z BIT(2) BIT 112 drivers/iio/accel/sca3000.c #define SCA3000_MD_CTRL_AND_Y BIT(3) BIT 113 drivers/iio/accel/sca3000.c #define SCA3000_MD_CTRL_AND_X BIT(4) BIT 114 drivers/iio/accel/sca3000.c #define SCA3000_MD_CTRL_AND_Z BIT(5) BIT 125 drivers/iio/accel/sca3000.c #define SCA3000_REG_INT_MASK_RING_THREE_QUARTER BIT(7) BIT 126 drivers/iio/accel/sca3000.c #define SCA3000_REG_INT_MASK_RING_HALF BIT(6) BIT 476 drivers/iio/accel/sca3000.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE), BIT 488 drivers/iio/accel/sca3000.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 489 drivers/iio/accel/sca3000.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |\ BIT 490 drivers/iio/accel/sca3000.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),\ BIT 491 drivers/iio/accel/sca3000.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ BIT 508 drivers/iio/accel/sca3000.c .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT 509 drivers/iio/accel/sca3000.c BIT(IIO_EV_INFO_PERIOD), BIT 532 drivers/iio/accel/sca3000.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 533 drivers/iio/accel/sca3000.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | BIT 534 drivers/iio/accel/sca3000.c BIT(IIO_CHAN_INFO_OFFSET), BIT 47 drivers/iio/accel/st_accel_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 51 drivers/iio/accel/st_accel_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 55 drivers/iio/accel/st_accel_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 63 drivers/iio/accel/st_accel_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 67 drivers/iio/accel/st_accel_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 71 drivers/iio/accel/st_accel_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 79 drivers/iio/accel/st_accel_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 83 drivers/iio/accel/st_accel_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 87 drivers/iio/accel/st_accel_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 175 drivers/iio/accel/st_accel_core.c .value = BIT(0), BIT 257 drivers/iio/accel/st_accel_core.c .value = BIT(0), BIT 347 drivers/iio/accel/st_accel_core.c .value = BIT(0), BIT 419 drivers/iio/accel/st_accel_core.c .value = BIT(1), BIT 491 drivers/iio/accel/st_accel_core.c .value = BIT(7), BIT 562 drivers/iio/accel/st_accel_core.c .value = BIT(0), BIT 619 drivers/iio/accel/st_accel_core.c .value = BIT(1), BIT 694 drivers/iio/accel/st_accel_core.c .value = BIT(0), BIT 775 drivers/iio/accel/st_accel_core.c .value = BIT(0), BIT 903 drivers/iio/accel/st_accel_core.c .value = BIT(0), BIT 36 drivers/iio/accel/stk8312.c #define STK8312_MODE_ACTIVE BIT(0) BIT 39 drivers/iio/accel/stk8312.c #define STK8312_DREADY_BIT BIT(4) BIT 79 drivers/iio/accel/stk8312.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 80 drivers/iio/accel/stk8312.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 81 drivers/iio/accel/stk8312.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 142 drivers/iio/accel/stk8312.c } while (!(ret & BIT(7)) && count > 0); BIT 34 drivers/iio/accel/stk8ba50.c #define STK8BA50_MODE_POWERBIT BIT(7) BIT 107 drivers/iio/accel/stk8ba50.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 108 drivers/iio/accel/stk8ba50.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 109 drivers/iio/accel/stk8ba50.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 39 drivers/iio/adc/ad7124.c #define AD7124_STATUS_POR_FLAG_MSK BIT(4) BIT 42 drivers/iio/adc/ad7124.c #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8) BIT 50 drivers/iio/adc/ad7124.c #define AD7124_CHANNEL_EN_MSK BIT(15) BIT 60 drivers/iio/adc/ad7124.c #define AD7124_CONFIG_BIPOLAR_MSK BIT(11) BIT 137 drivers/iio/adc/ad7124.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 138 drivers/iio/adc/ad7124.c BIT(IIO_CHAN_INFO_SCALE) | BIT 139 drivers/iio/adc/ad7124.c BIT(IIO_CHAN_INFO_OFFSET) | BIT 140 drivers/iio/adc/ad7124.c BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 225 drivers/iio/adc/ad7124.c .read_mask = BIT(6), BIT 120 drivers/iio/adc/ad7266.c gpio_set_value(st->gpios[i].gpio, (bool)(nr & BIT(i))); BIT 193 drivers/iio/adc/ad7266.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 194 drivers/iio/adc/ad7266.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ BIT 195 drivers/iio/adc/ad7266.c | BIT(IIO_CHAN_INFO_OFFSET), \ BIT 241 drivers/iio/adc/ad7266.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 242 drivers/iio/adc/ad7266.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ BIT 243 drivers/iio/adc/ad7266.c | BIT(IIO_CHAN_INFO_OFFSET), \ BIT 55 drivers/iio/adc/ad7291.c #define AD7291_AUTOCYCLE BIT(0) BIT 56 drivers/iio/adc/ad7291.c #define AD7291_RESET BIT(1) BIT 57 drivers/iio/adc/ad7291.c #define AD7291_ALERT_CLEAR BIT(2) BIT 58 drivers/iio/adc/ad7291.c #define AD7291_ALERT_POLARITY BIT(3) BIT 59 drivers/iio/adc/ad7291.c #define AD7291_EXT_REF BIT(4) BIT 60 drivers/iio/adc/ad7291.c #define AD7291_NOISE_DELAY BIT(5) BIT 61 drivers/iio/adc/ad7291.c #define AD7291_T_SENSE_MASK BIT(7) BIT 73 drivers/iio/adc/ad7291.c #define AD7291_T_LOW BIT(0) BIT 74 drivers/iio/adc/ad7291.c #define AD7291_T_HIGH BIT(1) BIT 75 drivers/iio/adc/ad7291.c #define AD7291_T_AVG_LOW BIT(2) BIT 76 drivers/iio/adc/ad7291.c #define AD7291_T_AVG_HIGH BIT(3) BIT 77 drivers/iio/adc/ad7291.c #define AD7291_V_LOW(x) BIT((x) * 2) BIT 78 drivers/iio/adc/ad7291.c #define AD7291_V_HIGH(x) BIT((x) * 2 + 1) BIT 260 drivers/iio/adc/ad7291.c return !!(chip->c_mask & BIT(15 - chan->channel)); BIT 289 drivers/iio/adc/ad7291.c mask = BIT(15 - chan->channel); BIT 342 drivers/iio/adc/ad7291.c regval |= BIT(15 - chan->channel); BIT 411 drivers/iio/adc/ad7291.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 412 drivers/iio/adc/ad7291.c BIT(IIO_EV_INFO_ENABLE), BIT 416 drivers/iio/adc/ad7291.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 417 drivers/iio/adc/ad7291.c BIT(IIO_EV_INFO_ENABLE), BIT 421 drivers/iio/adc/ad7291.c .mask_separate = BIT(IIO_EV_INFO_HYSTERESIS), BIT 428 drivers/iio/adc/ad7291.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 429 drivers/iio/adc/ad7291.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 447 drivers/iio/adc/ad7291.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 448 drivers/iio/adc/ad7291.c BIT(IIO_CHAN_INFO_AVERAGE_RAW) | BIT 449 drivers/iio/adc/ad7291.c BIT(IIO_CHAN_INFO_SCALE), BIT 28 drivers/iio/adc/ad7298.c #define AD7298_WRITE BIT(15) /* write to the control register */ BIT 29 drivers/iio/adc/ad7298.c #define AD7298_REPEAT BIT(14) /* repeated conversion enable */ BIT 30 drivers/iio/adc/ad7298.c #define AD7298_CH(x) BIT(13 - (x)) /* channel select */ BIT 31 drivers/iio/adc/ad7298.c #define AD7298_TSENSE BIT(5) /* temperature conversion enable */ BIT 32 drivers/iio/adc/ad7298.c #define AD7298_EXTREF BIT(2) /* external reference enable */ BIT 33 drivers/iio/adc/ad7298.c #define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */ BIT 34 drivers/iio/adc/ad7298.c #define AD7298_PDD BIT(0) /* partial power down enable */ BIT 62 drivers/iio/adc/ad7298.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 63 drivers/iio/adc/ad7298.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 79 drivers/iio/adc/ad7298.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 80 drivers/iio/adc/ad7298.c BIT(IIO_CHAN_INFO_SCALE) | BIT 81 drivers/iio/adc/ad7298.c BIT(IIO_CHAN_INFO_OFFSET), BIT 146 drivers/iio/adc/ad7476.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 157 drivers/iio/adc/ad7476.c BIT(IIO_CHAN_INFO_RAW)) BIT 159 drivers/iio/adc/ad7476.c BIT(IIO_CHAN_INFO_RAW)) BIT 161 drivers/iio/adc/ad7476.c BIT(IIO_CHAN_INFO_RAW)) BIT 164 drivers/iio/adc/ad7476.c BIT(IIO_CHAN_INFO_RAW)) BIT 29 drivers/iio/adc/ad7606.h AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \ BIT 30 drivers/iio/adc/ad7606.h BIT(IIO_CHAN_INFO_SCALE), 0) BIT 33 drivers/iio/adc/ad7606.h AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \ BIT 34 drivers/iio/adc/ad7606.h BIT(IIO_CHAN_INFO_SCALE), \ BIT 35 drivers/iio/adc/ad7606.h BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) BIT 38 drivers/iio/adc/ad7606.h AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),\ BIT 39 drivers/iio/adc/ad7606.h 0, BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) BIT 20 drivers/iio/adc/ad7606_spi.c #define AD7616_BURST_MODE BIT(6) BIT 21 drivers/iio/adc/ad7606_spi.c #define AD7616_SEQEN_MODE BIT(5) BIT 155 drivers/iio/adc/ad7766.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 156 drivers/iio/adc/ad7766.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 79 drivers/iio/adc/ad7768-1.c #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F)) BIT 138 drivers/iio/adc/ad7768-1.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 139 drivers/iio/adc/ad7768-1.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 140 drivers/iio/adc/ad7768-1.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 26 drivers/iio/adc/ad7780.c #define AD7780_RDY BIT(7) BIT 27 drivers/iio/adc/ad7780.c #define AD7780_FILTER BIT(6) BIT 28 drivers/iio/adc/ad7780.c #define AD7780_ERR BIT(5) BIT 29 drivers/iio/adc/ad7780.c #define AD7780_ID1 BIT(4) BIT 30 drivers/iio/adc/ad7780.c #define AD7780_ID0 BIT(3) BIT 31 drivers/iio/adc/ad7780.c #define AD7780_GAIN BIT(2) BIT 61 drivers/iio/adc/ad7791.c #define AD7791_MODE_BUFFER BIT(1) BIT 62 drivers/iio/adc/ad7791.c #define AD7791_MODE_UNIPOLAR BIT(2) BIT 63 drivers/iio/adc/ad7791.c #define AD7791_MODE_BURNOUT BIT(3) BIT 207 drivers/iio/adc/ad7791.c .read_mask = BIT(3), BIT 136 drivers/iio/adc/ad7793.c #define AD7793_FLAG_HAS_CLKSEL BIT(0) BIT 137 drivers/iio/adc/ad7793.c #define AD7793_FLAG_HAS_REFSEL BIT(1) BIT 138 drivers/iio/adc/ad7793.c #define AD7793_FLAG_HAS_VBIAS BIT(2) BIT 139 drivers/iio/adc/ad7793.c #define AD7793_HAS_EXITATION_CURRENT BIT(3) BIT 140 drivers/iio/adc/ad7793.c #define AD7793_FLAG_HAS_GAIN BIT(4) BIT 141 drivers/iio/adc/ad7793.c #define AD7793_FLAG_HAS_BUFFER BIT(5) BIT 208 drivers/iio/adc/ad7793.c .read_mask = BIT(6), BIT 28 drivers/iio/adc/ad7887.c #define AD7887_REF_DIS BIT(5) /* on-chip reference disable */ BIT 29 drivers/iio/adc/ad7887.c #define AD7887_DUAL BIT(4) /* dual-channel mode */ BIT 30 drivers/iio/adc/ad7887.c #define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */ BIT 196 drivers/iio/adc/ad7887.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 197 drivers/iio/adc/ad7887.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 212 drivers/iio/adc/ad7887.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 213 drivers/iio/adc/ad7887.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 26 drivers/iio/adc/ad7923.c #define AD7923_WRITE_CR BIT(11) /* write control register */ BIT 27 drivers/iio/adc/ad7923.c #define AD7923_RANGE BIT(1) /* range to REFin */ BIT 28 drivers/iio/adc/ad7923.c #define AD7923_CODING BIT(0) /* coding is straight binary */ BIT 88 drivers/iio/adc/ad7923.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 89 drivers/iio/adc/ad7923.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 144 drivers/iio/adc/ad7949.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 145 drivers/iio/adc/ad7949.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 55 drivers/iio/adc/ad799x.c #define AD7998_FLTR BIT(3) BIT 56 drivers/iio/adc/ad799x.c #define AD7998_ALERT_EN BIT(2) BIT 57 drivers/iio/adc/ad799x.c #define AD7998_BUSY_ALERT BIT(1) BIT 58 drivers/iio/adc/ad799x.c #define AD7998_BUSY_ALERT_POL BIT(0) BIT 85 drivers/iio/adc/ad799x.c #define AD7997_8_READ_SINGLE BIT(7) BIT 86 drivers/iio/adc/ad799x.c #define AD7997_8_READ_SEQUENCE (BIT(6) | BIT(5) | BIT(4)) BIT 252 drivers/iio/adc/ad799x.c cmd = st->config | (BIT(ch) << AD799X_CHANNEL_SHIFT); BIT 257 drivers/iio/adc/ad799x.c cmd = BIT(ch) << AD799X_CHANNEL_SHIFT; BIT 378 drivers/iio/adc/ad799x.c if ((st->config >> AD799X_CHANNEL_SHIFT) & BIT(chan->scan_index)) BIT 398 drivers/iio/adc/ad799x.c st->config |= BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT; BIT 400 drivers/iio/adc/ad799x.c st->config &= ~(BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT); BIT 490 drivers/iio/adc/ad799x.c if (ret & BIT(i)) BIT 547 drivers/iio/adc/ad799x.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 548 drivers/iio/adc/ad799x.c BIT(IIO_EV_INFO_ENABLE), BIT 552 drivers/iio/adc/ad799x.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 553 drivers/iio/adc/ad799x.c BIT(IIO_EV_INFO_ENABLE), BIT 557 drivers/iio/adc/ad799x.c .mask_separate = BIT(IIO_EV_INFO_HYSTERESIS), BIT 565 drivers/iio/adc/ad799x.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 566 drivers/iio/adc/ad799x.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 37 drivers/iio/adc/aspeed_adc.c #define ASPEED_ENGINE_ENABLE BIT(0) BIT 39 drivers/iio/adc/aspeed_adc.c #define ASPEED_ADC_CTRL_INIT_RDY BIT(8) BIT 66 drivers/iio/adc/aspeed_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 67 drivers/iio/adc/aspeed_adc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 68 drivers/iio/adc/aspeed_adc.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 32 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_CR_SWRST BIT(0) BIT 34 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_CR_START BIT(1) BIT 36 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_CR_TSCALIB BIT(2) BIT 38 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_CR_CMPRST BIT(4) BIT 61 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_MR_SLEEP BIT(5) BIT 63 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_MR_FWUP BIT(6) BIT 73 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_MR_ANACH BIT(23) BIT 81 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_MR_USEQ BIT(31) BIT 98 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_IER_XRDY BIT(20) BIT 100 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_IER_YRDY BIT(21) BIT 102 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_IER_PRDY BIT(22) BIT 104 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_IER_GOVRE BIT(25) BIT 106 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_IER_PEN BIT(29) BIT 108 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_IER_NOPEN BIT(30) BIT 116 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_ISR_PENS BIT(31) BIT 173 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22) BIT 177 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24) BIT 268 drivers/iio/adc/at91-sama5d2_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 269 drivers/iio/adc/at91-sama5d2_adc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 270 drivers/iio/adc/at91-sama5d2_adc.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT 271 drivers/iio/adc/at91-sama5d2_adc.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ BIT 289 drivers/iio/adc/at91-sama5d2_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 290 drivers/iio/adc/at91-sama5d2_adc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 291 drivers/iio/adc/at91-sama5d2_adc.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT 292 drivers/iio/adc/at91-sama5d2_adc.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ BIT 309 drivers/iio/adc/at91-sama5d2_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 310 drivers/iio/adc/at91-sama5d2_adc.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT 311 drivers/iio/adc/at91-sama5d2_adc.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ BIT 324 drivers/iio/adc/at91-sama5d2_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 325 drivers/iio/adc/at91-sama5d2_adc.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT 326 drivers/iio/adc/at91-sama5d2_adc.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ BIT 739 drivers/iio/adc/at91-sama5d2_adc.c cor |= (BIT(chan->channel) | BIT 740 drivers/iio/adc/at91-sama5d2_adc.c BIT(chan->channel2)) << BIT 743 drivers/iio/adc/at91-sama5d2_adc.c cor &= ~(BIT(chan->channel) << BIT 751 drivers/iio/adc/at91-sama5d2_adc.c BIT(chan->channel)); BIT 755 drivers/iio/adc/at91-sama5d2_adc.c BIT(chan->channel)); BIT 761 drivers/iio/adc/at91-sama5d2_adc.c BIT(chan->channel)); BIT 764 drivers/iio/adc/at91-sama5d2_adc.c BIT(chan->channel)); BIT 1352 drivers/iio/adc/at91-sama5d2_adc.c cor = (BIT(chan->channel) | BIT(chan->channel2)) << BIT 1356 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); BIT 1357 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel)); BIT 1374 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel)); BIT 1375 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); BIT 503 drivers/iio/adc/at91_adc.c chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); BIT 504 drivers/iio/adc/at91_adc.c chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); BIT 700 drivers/iio/adc/at91_adc.c at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel)); BIT 712 drivers/iio/adc/at91_adc.c at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel)); BIT 26 drivers/iio/adc/axp20x_adc.c #define AXP20X_ADC_EN2_MASK (GENMASK(3, 2) | BIT(7)) BIT 27 drivers/iio/adc/axp20x_adc.c #define AXP22X_ADC_EN1_MASK (GENMASK(7, 5) | BIT(0)) BIT 29 drivers/iio/adc/axp20x_adc.c #define AXP20X_GPIO10_IN_RANGE_GPIO0 BIT(0) BIT 30 drivers/iio/adc/axp20x_adc.c #define AXP20X_GPIO10_IN_RANGE_GPIO1 BIT(1) BIT 31 drivers/iio/adc/axp20x_adc.c #define AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(x) ((x) & BIT(0)) BIT 32 drivers/iio/adc/axp20x_adc.c #define AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(x) (((x) & BIT(0)) << 1) BIT 49 drivers/iio/adc/axp20x_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 50 drivers/iio/adc/axp20x_adc.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 60 drivers/iio/adc/axp20x_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 61 drivers/iio/adc/axp20x_adc.c BIT(IIO_CHAN_INFO_SCALE) |\ BIT 62 drivers/iio/adc/axp20x_adc.c BIT(IIO_CHAN_INFO_OFFSET),\ BIT 172 drivers/iio/adc/axp20x_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 173 drivers/iio/adc/axp20x_adc.c BIT(IIO_CHAN_INFO_SCALE) | BIT 174 drivers/iio/adc/axp20x_adc.c BIT(IIO_CHAN_INFO_OFFSET), BIT 195 drivers/iio/adc/axp20x_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 196 drivers/iio/adc/axp20x_adc.c BIT(IIO_CHAN_INFO_SCALE) | BIT 197 drivers/iio/adc/axp20x_adc.c BIT(IIO_CHAN_INFO_OFFSET), BIT 212 drivers/iio/adc/axp20x_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 213 drivers/iio/adc/axp20x_adc.c BIT(IIO_CHAN_INFO_SCALE) | BIT 214 drivers/iio/adc/axp20x_adc.c BIT(IIO_CHAN_INFO_OFFSET), BIT 63 drivers/iio/adc/axp288_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 70 drivers/iio/adc/axp288_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 77 drivers/iio/adc/axp288_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 84 drivers/iio/adc/axp288_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 91 drivers/iio/adc/axp288_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 98 drivers/iio/adc/axp288_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 40 drivers/iio/adc/bcm_iproc_adc.c #define IPROC_ADC_AUXIN_SCAN_ENA BIT(0) BIT 41 drivers/iio/adc/bcm_iproc_adc.c #define IPROC_ADC_PWR_LDO BIT(5) BIT 42 drivers/iio/adc/bcm_iproc_adc.c #define IPROC_ADC_PWR_ADC BIT(4) BIT 43 drivers/iio/adc/bcm_iproc_adc.c #define IPROC_ADC_PWR_BG BIT(3) BIT 44 drivers/iio/adc/bcm_iproc_adc.c #define IPROC_ADC_CONTROLLER_EN BIT(17) BIT 47 drivers/iio/adc/bcm_iproc_adc.c #define IPROC_ADC_AUXDATA_RDY_INTR BIT(3) BIT 252 drivers/iio/adc/bcm_iproc_adc.c val = (BIT(IPROC_ADC_CHANNEL_ROUNDS) | BIT 277 drivers/iio/adc/bcm_iproc_adc.c val |= (BIT(channel) << IPROC_ADC_INTR); BIT 490 drivers/iio/adc/bcm_iproc_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 491 drivers/iio/adc/bcm_iproc_adc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 27 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_CTRL_SM_SOC_INT BIT(1) BIT 28 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_CTRL_SOC_SM_INT BIT(2) BIT 31 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_CTRL_ADC_POWER BIT(9) BIT 37 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_CTRL_ADC_START BIT(12) BIT 38 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_CTRL_ADC_RESET BIT(13) BIT 39 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_CTRL_ADC_BANDGAP_RDY BIT(14) BIT 42 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_CTRL_ADC_BUFFER_EN BIT(16) BIT 45 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_CTRL_ADC_ROTATE BIT(19) BIT 46 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_CTRL_TSEN_EN BIT(20) BIT 51 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_CTRL_TSEN_RESET BIT(29) BIT 55 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_ADC_STATUS_DATA_RDY(x) BIT(x) /* 0-15 */ BIT 57 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_ADC_STATUS_INT_EN(x) (BIT(x) << 16) /* 0-15 */ BIT 60 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_TSEN_STATUS_DATA_RDY BIT(0) BIT 61 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_TSEN_STATUS_INT_EN BIT(1) BIT 65 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_TSEN_CTRL_START BIT(8) BIT 68 drivers/iio/adc/berlin2-adc.c #define BERLIN2_SM_TSEN_CTRL_SETTLING_MASK BIT(21) BIT 86 drivers/iio/adc/berlin2-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 101 drivers/iio/adc/berlin2-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 26 drivers/iio/adc/cc10001_adc.c #define CC10001_ADC_START_CONV BIT(4) BIT 27 drivers/iio/adc/cc10001_adc.c #define CC10001_ADC_MODE_SINGLE_CONV BIT(5) BIT 31 drivers/iio/adc/cc10001_adc.c #define CC10001_ADC_EOC_SET BIT(0) BIT 35 drivers/iio/adc/cc10001_adc.c #define CC10001_ADC_POWER_DOWN_SET BIT(0) BIT 290 drivers/iio/adc/cc10001_adc.c chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); BIT 291 drivers/iio/adc/cc10001_adc.c chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); BIT 30 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADEN_AUTO_CLR BIT(15) /* Currently unused */ BIT 31 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_CAL_MODE BIT(14) /* Set with BIT_RAND0 */ BIT 32 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADC_CLK_SEL1 BIT(13) /* Currently unused */ BIT 33 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADC_CLK_SEL0 BIT(12) /* Currently unused */ BIT 34 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ATOX BIT(11) BIT 35 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ATO3 BIT(10) BIT 36 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ATO2 BIT(9) BIT 37 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ATO1 BIT(8) BIT 38 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ATO0 BIT(7) BIT 39 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADA2 BIT(6) BIT 40 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADA1 BIT(5) BIT 41 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADA0 BIT(4) BIT 42 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_AD_SEL1 BIT(3) /* Set for bank1 */ BIT 43 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_RAND1 BIT(2) /* Set for channel 16 & 17 */ BIT 44 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_RAND0 BIT(1) /* Set with CAL_MODE */ BIT 45 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADEN BIT(0) /* Currently unused */ BIT 52 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_CAL_FACTOR_ENABLE BIT(15) /* Currently unused */ BIT 53 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_BATDETB_EN BIT(14) /* Currently unused */ BIT 54 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADTRIG_ONESHOT BIT(13) /* Set for !TIMING_IMM */ BIT 55 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ASC BIT(12) /* Set for TIMING_IMM */ BIT 56 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ATOX_PS_FACTOR BIT(11) BIT 57 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADC_PS_FACTOR1 BIT(10) BIT 58 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADC_PS_FACTOR0 BIT(9) BIT 59 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_AD4_SELECT BIT(8) /* Currently unused */ BIT 60 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADC_BUSY BIT(7) /* Currently unused */ BIT 61 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_THERMBIAS_EN BIT(6) /* Bias for AD0_BATTDETB */ BIT 62 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_ADTRIG_DIS BIT(5) /* Disable interrupt */ BIT 63 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_LIADC BIT(4) /* Currently unused */ BIT 64 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_TS_REFEN BIT(3) /* Currently unused */ BIT 65 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_TS_M2 BIT(2) /* Currently unused */ BIT 66 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_TS_M1 BIT(1) /* Currently unused */ BIT 67 drivers/iio/adc/cpcap-adc.c #define CPCAP_BIT_TS_M0 BIT(0) /* Currently unused */ BIT 339 drivers/iio/adc/cpcap-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 340 drivers/iio/adc/cpcap-adc.c BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 263 drivers/iio/adc/da9150-gpadc.c BIT(IIO_CHAN_INFO_RAW), _ext_name) BIT 267 drivers/iio/adc/da9150-gpadc.c BIT(IIO_CHAN_INFO_RAW) | \ BIT 268 drivers/iio/adc/da9150-gpadc.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 269 drivers/iio/adc/da9150-gpadc.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 274 drivers/iio/adc/da9150-gpadc.c BIT(IIO_CHAN_INFO_PROCESSED), _ext_name) BIT 455 drivers/iio/adc/dln2-adc.c lval.info_mask_separate = BIT(IIO_CHAN_INFO_RAW); \ BIT 456 drivers/iio/adc/dln2-adc.c lval.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 457 drivers/iio/adc/dln2-adc.c BIT(IIO_CHAN_INFO_SAMP_FREQ); \ BIT 314 drivers/iio/adc/envelope-detector.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) BIT 315 drivers/iio/adc/envelope-detector.c | BIT(IIO_CHAN_INFO_SCALE), BIT 40 drivers/iio/adc/ep93xx_adc.c #define EP93XX_ADC_SDR BIT(31) BIT 57 drivers/iio/adc/ep93xx_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 58 drivers/iio/adc/ep93xx_adc.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 59 drivers/iio/adc/ep93xx_adc.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 685 drivers/iio/adc/exynos_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 49 drivers/iio/adc/fsl-imx25-gcq.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 50 drivers/iio/adc/fsl-imx25-gcq.c BIT(IIO_CHAN_INFO_SCALE),\ BIT 117 drivers/iio/adc/hi8435.c *val = !!(tmp & BIT(chan->channel)); BIT 131 drivers/iio/adc/hi8435.c return !!(priv->event_scan_mask & BIT(chan->channel)); BIT 147 drivers/iio/adc/hi8435.c if (tmp & BIT(chan->channel)) BIT 148 drivers/iio/adc/hi8435.c priv->event_prev_val |= BIT(chan->channel); BIT 150 drivers/iio/adc/hi8435.c priv->event_prev_val &= ~BIT(chan->channel); BIT 152 drivers/iio/adc/hi8435.c priv->event_scan_mask |= BIT(chan->channel); BIT 154 drivers/iio/adc/hi8435.c priv->event_scan_mask &= ~BIT(chan->channel); BIT 176 drivers/iio/adc/hi8435.c mode = !!(psen & BIT(chan->channel / 8)); BIT 208 drivers/iio/adc/hi8435.c mode = !!(psen & BIT(chan->channel / 8)); BIT 290 drivers/iio/adc/hi8435.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 294 drivers/iio/adc/hi8435.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 298 drivers/iio/adc/hi8435.c .mask_separate = BIT(IIO_EV_INFO_ENABLE), BIT 313 drivers/iio/adc/hi8435.c return !!(reg & BIT(chan->channel / 8)); BIT 332 drivers/iio/adc/hi8435.c reg &= ~BIT(chan->channel / 8); BIT 334 drivers/iio/adc/hi8435.c reg |= BIT(chan->channel / 8); BIT 364 drivers/iio/adc/hi8435.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 426 drivers/iio/adc/hi8435.c if (status & BIT(i)) { BIT 427 drivers/iio/adc/hi8435.c dir = val & BIT(i) ? IIO_EV_DIR_RISING : BIT 444 drivers/iio/adc/hx711.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 445 drivers/iio/adc/hx711.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 458 drivers/iio/adc/hx711.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 459 drivers/iio/adc/hx711.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 48 drivers/iio/adc/imx7d_adc.c #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE BIT(30) BIT 49 drivers/iio/adc/imx7d_adc.c #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN BIT(29) BIT 64 drivers/iio/adc/imx7d_adc.c #define IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN BIT(31) BIT 65 drivers/iio/adc/imx7d_adc.c #define IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN BIT(1) BIT 66 drivers/iio/adc/imx7d_adc.c #define IMX7D_REG_ADC_ADC_CFG_ADC_EN BIT(0) BIT 68 drivers/iio/adc/imx7d_adc.c #define IMX7D_REG_ADC_INT_CHA_COV_INT_EN BIT(8) BIT 69 drivers/iio/adc/imx7d_adc.c #define IMX7D_REG_ADC_INT_CHB_COV_INT_EN BIT(9) BIT 70 drivers/iio/adc/imx7d_adc.c #define IMX7D_REG_ADC_INT_CHC_COV_INT_EN BIT(10) BIT 71 drivers/iio/adc/imx7d_adc.c #define IMX7D_REG_ADC_INT_CHD_COV_INT_EN BIT(11) BIT 145 drivers/iio/adc/imx7d_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 146 drivers/iio/adc/imx7d_adc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 147 drivers/iio/adc/imx7d_adc.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 47 drivers/iio/adc/ina2xx-adc.c #define INA226_CVRF BIT(3) BIT 73 drivers/iio/adc/ina2xx-adc.c #define INA219_BRNG_MASK BIT(13) BIT 93 drivers/iio/adc/ina2xx-adc.c #define INA219_OVF BIT(0) BIT 94 drivers/iio/adc/ina2xx-adc.c #define INA219_CNVR BIT(1) BIT 613 drivers/iio/adc/ina2xx-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 614 drivers/iio/adc/ina2xx-adc.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 615 drivers/iio/adc/ina2xx-adc.c .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 630 drivers/iio/adc/ina2xx-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 631 drivers/iio/adc/ina2xx-adc.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 632 drivers/iio/adc/ina2xx-adc.c .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT 633 drivers/iio/adc/ina2xx-adc.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ BIT 652 drivers/iio/adc/ina2xx-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 653 drivers/iio/adc/ina2xx-adc.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 654 drivers/iio/adc/ina2xx-adc.c BIT(IIO_CHAN_INFO_INT_TIME) | \ BIT 655 drivers/iio/adc/ina2xx-adc.c BIT(IIO_CHAN_INFO_HARDWAREGAIN), \ BIT 657 drivers/iio/adc/ina2xx-adc.c BIT(IIO_CHAN_INFO_HARDWAREGAIN), \ BIT 658 drivers/iio/adc/ina2xx-adc.c .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 674 drivers/iio/adc/ina2xx-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 675 drivers/iio/adc/ina2xx-adc.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 676 drivers/iio/adc/ina2xx-adc.c BIT(IIO_CHAN_INFO_INT_TIME), \ BIT 677 drivers/iio/adc/ina2xx-adc.c .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT 678 drivers/iio/adc/ina2xx-adc.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ BIT 28 drivers/iio/adc/ingenic-adc.c #define JZ_ADC_REG_CFG_BAT_MD BIT(4) BIT 88 drivers/iio/adc/ingenic-adc.c val |= BIT(engine); BIT 90 drivers/iio/adc/ingenic-adc.c val &= ~BIT(engine); BIT 104 drivers/iio/adc/ingenic-adc.c !(val & BIT(engine)), 250, 1000); BIT 310 drivers/iio/adc/ingenic-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 311 drivers/iio/adc/ingenic-adc.c BIT(IIO_CHAN_INFO_SCALE), BIT 318 drivers/iio/adc/ingenic-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 319 drivers/iio/adc/ingenic-adc.c BIT(IIO_CHAN_INFO_SCALE), BIT 320 drivers/iio/adc/ingenic-adc.c .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) | BIT 321 drivers/iio/adc/ingenic-adc.c BIT(IIO_CHAN_INFO_SCALE), BIT 131 drivers/iio/adc/lp8788_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 132 drivers/iio/adc/lp8788_adc.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 30 drivers/iio/adc/lpc18xx_adc.c #define LPC18XX_ADC_CR_PDN BIT(21) BIT 37 drivers/iio/adc/lpc18xx_adc.c #define LPC18XX_ADC_CONV_DONE BIT(31) BIT 55 drivers/iio/adc/lpc18xx_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 56 drivers/iio/adc/lpc18xx_adc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 75 drivers/iio/adc/lpc18xx_adc.c reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW; BIT 104 drivers/iio/adc/lpc32xx_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 114 drivers/iio/adc/lpc32xx_adc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ BIT 83 drivers/iio/adc/ltc2471.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 84 drivers/iio/adc/ltc2471.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 91 drivers/iio/adc/ltc2471.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 92 drivers/iio/adc/ltc2471.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | BIT 93 drivers/iio/adc/ltc2471.c BIT(IIO_CHAN_INFO_OFFSET), BIT 83 drivers/iio/adc/ltc2485.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 84 drivers/iio/adc/ltc2485.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) BIT 20 drivers/iio/adc/ltc2497.c #define LTC2497_SGL BIT(4) BIT 22 drivers/iio/adc/ltc2497.c #define LTC2497_SIGN BIT(3) BIT 135 drivers/iio/adc/ltc2497.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 136 drivers/iio/adc/ltc2497.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 146 drivers/iio/adc/ltc2497.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 147 drivers/iio/adc/ltc2497.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 26 drivers/iio/adc/max1027.c #define MAX1027_CONV_REG BIT(7) BIT 27 drivers/iio/adc/max1027.c #define MAX1027_SETUP_REG BIT(6) BIT 28 drivers/iio/adc/max1027.c #define MAX1027_AVG_REG BIT(5) BIT 29 drivers/iio/adc/max1027.c #define MAX1027_RST_REG BIT(4) BIT 32 drivers/iio/adc/max1027.c #define MAX1027_TEMP BIT(0) BIT 60 drivers/iio/adc/max1027.c #define MAX1027_AVG_EN BIT(4) BIT 91 drivers/iio/adc/max1027.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 92 drivers/iio/adc/max1027.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 107 drivers/iio/adc/max1027.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 108 drivers/iio/adc/max1027.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 43 drivers/iio/adc/max11100.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 44 drivers/iio/adc/max11100.c BIT(IIO_CHAN_INFO_SCALE), BIT 47 drivers/iio/adc/max1118.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 48 drivers/iio/adc/max1118.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 450 drivers/iio/adc/max1363.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 451 drivers/iio/adc/max1363.c BIT(IIO_EV_INFO_ENABLE), BIT 455 drivers/iio/adc/max1363.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 456 drivers/iio/adc/max1363.c BIT(IIO_EV_INFO_ENABLE), BIT 466 drivers/iio/adc/max1363.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 467 drivers/iio/adc/max1363.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 489 drivers/iio/adc/max1363.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 490 drivers/iio/adc/max1363.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 176 drivers/iio/adc/max9611.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 177 drivers/iio/adc/max9611.c BIT(IIO_CHAN_INFO_SCALE), BIT 182 drivers/iio/adc/max9611.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 189 drivers/iio/adc/max9611.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 190 drivers/iio/adc/max9611.c BIT(IIO_CHAN_INFO_SCALE) | BIT 191 drivers/iio/adc/max9611.c BIT(IIO_CHAN_INFO_OFFSET), BIT 198 drivers/iio/adc/max9611.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 203 drivers/iio/adc/max9611.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 178 drivers/iio/adc/mcp320x.c if (raw & BIT(22) && raw & BIT(23)) BIT 180 drivers/iio/adc/mcp320x.c else if (raw & BIT(22)) BIT 181 drivers/iio/adc/mcp320x.c raw &= ~BIT(22); /* overrange */ BIT 182 drivers/iio/adc/mcp320x.c else if (raw & BIT(23) || raw & BIT(21)) BIT 239 drivers/iio/adc/mcp320x.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 240 drivers/iio/adc/mcp320x.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ BIT 251 drivers/iio/adc/mcp320x.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 252 drivers/iio/adc/mcp320x.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ BIT 53 drivers/iio/adc/mcp3422.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ BIT 54 drivers/iio/adc/mcp3422.c | BIT(IIO_CHAN_INFO_SCALE), \ BIT 55 drivers/iio/adc/mcp3422.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 23 drivers/iio/adc/mcp3911.c #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4) BIT 24 drivers/iio/adc/mcp3911.c #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3) BIT 25 drivers/iio/adc/mcp3911.c #define MCP3911_STATUSCOM_EN_OFFCAL BIT(2) BIT 26 drivers/iio/adc/mcp3911.c #define MCP3911_STATUSCOM_EN_GAINCAL BIT(1) BIT 29 drivers/iio/adc/mcp3911.c #define MCP3911_CONFIG_CLKEXT BIT(1) BIT 30 drivers/iio/adc/mcp3911.c #define MCP3911_CONFIG_VREFEXT BIT(2) BIT 188 drivers/iio/adc/mcp3911.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 189 drivers/iio/adc/mcp3911.c BIT(IIO_CHAN_INFO_OFFSET) | \ BIT 190 drivers/iio/adc/mcp3911.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 17 drivers/iio/adc/men_z188_adc.c #define Z188_MODE_VOLTAGE BIT(27) BIT 33 drivers/iio/adc/men_z188_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 26 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31) BIT 28 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30) BIT 29 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29) BIT 30 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28) BIT 31 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27) BIT 32 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26) BIT 36 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15) BIT 37 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14) BIT 39 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10) BIT 40 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9) BIT 42 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3) BIT 43 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2) BIT 44 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1) BIT 45 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0) BIT 63 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31) BIT 64 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG3_CLK_EN BIT(30) BIT 65 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28) BIT 66 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27) BIT 67 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26) BIT 69 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22) BIT 70 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG3_ADC_EN BIT(21) BIT 80 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15) BIT 81 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14) BIT 97 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6) BIT 98 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5) BIT 99 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4) BIT 100 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3) BIT 101 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2) BIT 102 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1) BIT 103 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0) BIT 107 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22) BIT 108 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21) BIT 109 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20) BIT 110 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19) BIT 111 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18) BIT 112 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17) BIT 113 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16) BIT 115 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6) BIT 116 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5) BIT 117 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4) BIT 118 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3) BIT 119 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2) BIT 120 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1) BIT 121 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0) BIT 124 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26) BIT 126 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22) BIT 127 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21) BIT 128 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20) BIT 129 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19) BIT 130 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18) BIT 131 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17) BIT 132 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16) BIT 134 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6) BIT 135 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5) BIT 136 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4) BIT 137 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3) BIT 138 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2) BIT 139 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1) BIT 140 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0) BIT 143 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27) BIT 144 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26) BIT 146 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15) BIT 148 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10) BIT 157 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13) BIT 170 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7) BIT 173 drivers/iio/adc/meson_saradc.c #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9) BIT 183 drivers/iio/adc/meson_saradc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 184 drivers/iio/adc/meson_saradc.c BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ BIT 185 drivers/iio/adc/meson_saradc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 186 drivers/iio/adc/meson_saradc.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ BIT 187 drivers/iio/adc/meson_saradc.c BIT(IIO_CHAN_INFO_CALIBSCALE), \ BIT 195 drivers/iio/adc/meson_saradc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 196 drivers/iio/adc/meson_saradc.c BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ BIT 197 drivers/iio/adc/meson_saradc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \ BIT 198 drivers/iio/adc/meson_saradc.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 199 drivers/iio/adc/meson_saradc.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ BIT 200 drivers/iio/adc/meson_saradc.c BIT(IIO_CHAN_INFO_CALIBSCALE), \ BIT 752 drivers/iio/adc/meson_saradc.c trimming_mask = BIT(trimming_bits) - 1; BIT 874 drivers/iio/adc/meson_saradc.c if (priv->temperature_sensor_coefficient & BIT(4)) BIT 23 drivers/iio/adc/mt6577_auxadc.c #define MT6577_AUXADC_STA BIT(0) BIT 26 drivers/iio/adc/mt6577_auxadc.c #define MT6577_AUXADC_RDY0 BIT(12) BIT 29 drivers/iio/adc/mt6577_auxadc.c #define MT6577_AUXADC_PDN_EN BIT(14) BIT 63 drivers/iio/adc/mt6577_auxadc.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 177 drivers/iio/adc/mxs-lradc-adc.c writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); BIT 582 drivers/iio/adc/mxs-lradc-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 583 drivers/iio/adc/mxs-lradc-adc.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 608 drivers/iio/adc/mxs-lradc-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 609 drivers/iio/adc/mxs-lradc-adc.c BIT(IIO_CHAN_INFO_OFFSET) | BIT 610 drivers/iio/adc/mxs-lradc-adc.c BIT(IIO_CHAN_INFO_SCALE), BIT 644 drivers/iio/adc/mxs-lradc-adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 645 drivers/iio/adc/mxs-lradc-adc.c BIT(IIO_CHAN_INFO_OFFSET) | BIT 646 drivers/iio/adc/mxs-lradc-adc.c BIT(IIO_CHAN_INFO_SCALE), BIT 68 drivers/iio/adc/nau7802.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 69 drivers/iio/adc/nau7802.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 70 drivers/iio/adc/nau7802.c BIT(IIO_CHAN_INFO_SAMP_FREQ) \ BIT 31 drivers/iio/adc/npcm_adc.c #define NPCM7XX_IPSRST1_ADC_RST BIT(27) BIT 38 drivers/iio/adc/npcm_adc.c #define NPCM_ADCCON_ADC_INT_EN BIT(21) BIT 39 drivers/iio/adc/npcm_adc.c #define NPCM_ADCCON_REFSEL BIT(19) BIT 40 drivers/iio/adc/npcm_adc.c #define NPCM_ADCCON_ADC_INT_ST BIT(18) BIT 41 drivers/iio/adc/npcm_adc.c #define NPCM_ADCCON_ADC_EN BIT(17) BIT 42 drivers/iio/adc/npcm_adc.c #define NPCM_ADCCON_ADC_RST BIT(16) BIT 43 drivers/iio/adc/npcm_adc.c #define NPCM_ADCCON_ADC_CONV BIT(13) BIT 61 drivers/iio/adc/npcm_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 62 drivers/iio/adc/npcm_adc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 63 drivers/iio/adc/npcm_adc.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 436 drivers/iio/adc/palmas_gpadc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 437 drivers/iio/adc/palmas_gpadc.c BIT(chan_info), \ BIT 37 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_BTM_CNTRL1_EN_BTM BIT(0) BIT 38 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_BTM_CNTRL1_SEL_OP_MODE BIT(1) BIT 39 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1 BIT(2) BIT 40 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2 BIT(3) BIT 41 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3 BIT(4) BIT 42 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4 BIT(5) BIT 43 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_BTM_CNTRL1_EOC BIT(6) BIT 44 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_BTM_CNTRL1_REQ BIT(7) BIT 61 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_CNTRL_EN_ARB BIT(0) BIT 62 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_CNTRL_RSV1 BIT(1) BIT 63 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_CNTRL_RSV2 BIT(2) BIT 64 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_CNTRL_RSV3 BIT(3) BIT 65 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_CNTRL_RSV4 BIT(4) BIT 66 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_CNTRL_RSV5 BIT(5) BIT 67 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_CNTRL_EOC BIT(6) BIT 68 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_CNTRL_REQ BIT(7) BIT 76 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_AMUX_CNTRL_RSV0 BIT(0) BIT 77 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_AMUX_CNTRL_RSV1 BIT(1) BIT 79 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX0 BIT(2) BIT 80 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX1 BIT(3) BIT 81 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_AMUX_CNTRL_SEL0 BIT(4) BIT 82 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_AMUX_CNTRL_SEL1 BIT(5) BIT 83 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_AMUX_CNTRL_SEL2 BIT(6) BIT 84 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_AMUX_CNTRL_SEL3 BIT(7) BIT 94 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 BIT(0) BIT 95 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 BIT(1) BIT 96 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_DIG_PARAM_CLK_RATE0 BIT(2) BIT 97 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_DIG_PARAM_CLK_RATE1 BIT(3) BIT 98 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_DIG_PARAM_EOC BIT(4) BIT 104 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_DIG_PARAM_DEC_RATE0 BIT(5) BIT 105 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_DIG_PARAM_DEC_RATE1 BIT(6) BIT 106 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_DIG_PARAM_EN BIT(7) BIT 110 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_RSV_RST BIT(0) BIT 111 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_RSV_DTEST0 BIT(1) BIT 112 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_RSV_DTEST1 BIT(2) BIT 113 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_RSV_OP BIT(3) BIT 114 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_RSV_IP_SEL0 BIT(4) BIT 115 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_RSV_IP_SEL1 BIT(5) BIT 116 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_RSV_IP_SEL2 BIT(6) BIT 117 drivers/iio/adc/qcom-pm8xxx-xoadc.c #define ADC_ARB_USRP_RSV_TRM BIT(7) BIT 808 drivers/iio/adc/qcom-pm8xxx-xoadc.c iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 809 drivers/iio/adc/qcom-pm8xxx-xoadc.c BIT(IIO_CHAN_INFO_PROCESSED); BIT 26 drivers/iio/adc/qcom-spmi-adc5.c #define ADC5_USR_STATUS1_REQ_STS BIT(1) BIT 27 drivers/iio/adc/qcom-spmi-adc5.c #define ADC5_USR_STATUS1_EOC BIT(0) BIT 35 drivers/iio/adc/qcom-spmi-adc5.c #define ADC5_USR_IBAT_MEAS_SUPPORTED BIT(0) BIT 38 drivers/iio/adc/qcom-spmi-adc5.c #define ADC5_USR_DIG_PARAM_CAL_VAL BIT(6) BIT 46 drivers/iio/adc/qcom-spmi-adc5.c #define ADC5_USR_FAST_AVG_CTL_EN BIT(7) BIT 55 drivers/iio/adc/qcom-spmi-adc5.c #define ADC5_USR_EN_CTL1_ADC_EN BIT(7) BIT 58 drivers/iio/adc/qcom-spmi-adc5.c #define ADC5_USR_CONV_REQ_REQ BIT(7) BIT 438 drivers/iio/adc/qcom-spmi-adc5.c BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 443 drivers/iio/adc/qcom-spmi-adc5.c BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 33 drivers/iio/adc/qcom-spmi-iadc.c #define IADC_STATUS1_REQ_STS BIT(1) BIT 34 drivers/iio/adc/qcom-spmi-iadc.c #define IADC_STATUS1_EOC BIT(0) BIT 40 drivers/iio/adc/qcom-spmi-iadc.c #define IADC_TRIM_EN BIT(0) BIT 43 drivers/iio/adc/qcom-spmi-iadc.c #define IADC_EN_CTL1_SET BIT(7) BIT 53 drivers/iio/adc/qcom-spmi-iadc.c #define IADC_CONV_REQ_SET BIT(7) BIT 57 drivers/iio/adc/qcom-spmi-iadc.c #define IADC_FAST_AVG_EN_SET BIT(7) BIT 60 drivers/iio/adc/qcom-spmi-iadc.c #define IADC_FOLLOW_WARM_RB BIT(2) BIT 68 drivers/iio/adc/qcom-spmi-iadc.c #define IADC_NOMINAL_RSENSE_SIGN_MASK BIT(7) BIT 286 drivers/iio/adc/qcom-spmi-iadc.c wait = BIT(IADC_DEF_AVG_SAMPLES) * IADC_CONV_TIME_MIN_US * 2; BIT 471 drivers/iio/adc/qcom-spmi-iadc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 472 drivers/iio/adc/qcom-spmi-iadc.c BIT(IIO_CHAN_INFO_SCALE), BIT 479 drivers/iio/adc/qcom-spmi-iadc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 480 drivers/iio/adc/qcom-spmi-iadc.c BIT(IIO_CHAN_INFO_SCALE), BIT 37 drivers/iio/adc/qcom-spmi-vadc.c #define VADC_STATUS1_REQ_STS BIT(1) BIT 38 drivers/iio/adc/qcom-spmi-vadc.c #define VADC_STATUS1_EOC BIT(0) BIT 44 drivers/iio/adc/qcom-spmi-vadc.c #define VADC_AMUX_TRIM_EN BIT(1) BIT 45 drivers/iio/adc/qcom-spmi-vadc.c #define VADC_ADC_TRIM_EN BIT(0) BIT 48 drivers/iio/adc/qcom-spmi-vadc.c #define VADC_EN_CTL1_SET BIT(7) BIT 58 drivers/iio/adc/qcom-spmi-vadc.c #define VADC_CONV_REQ_SET BIT(7) BIT 62 drivers/iio/adc/qcom-spmi-vadc.c #define VADC_FAST_AVG_EN_SET BIT(7) BIT 68 drivers/iio/adc/qcom-spmi-vadc.c #define VADC_FOLLOW_WARM_RB BIT(2) BIT 324 drivers/iio/adc/qcom-spmi-vadc.c timeout = BIT(prop->avg_samples) * VADC_CONV_TIME_MIN_US * 2; BIT 530 drivers/iio/adc/qcom-spmi-vadc.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 535 drivers/iio/adc/qcom-spmi-vadc.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_PROCESSED),\ BIT 540 drivers/iio/adc/qcom-spmi-vadc.c BIT(IIO_CHAN_INFO_RAW), \ BIT 35 drivers/iio/adc/rcar-gyroadc.c #define RCAR_GYROADC_START_STOP_START BIT(0) BIT 45 drivers/iio/adc/rcar-gyroadc.c #define RCAR_GYROADC_FIFO_STATUS_EMPTY(ch) BIT(0 + (4 * (ch))) BIT 46 drivers/iio/adc/rcar-gyroadc.c #define RCAR_GYROADC_FIFO_STATUS_FULL(ch) BIT(1 + (4 * (ch))) BIT 47 drivers/iio/adc/rcar-gyroadc.c #define RCAR_GYROADC_FIFO_STATUS_ERROR(ch) BIT(2 + (4 * (ch))) BIT 50 drivers/iio/adc/rcar-gyroadc.c #define RCAR_GYROADC_INTR_INT BIT(0) BIT 53 drivers/iio/adc/rcar-gyroadc.c #define RCAR_GYROADC_INTENR_INTEN BIT(0) BIT 128 drivers/iio/adc/rcar-gyroadc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 129 drivers/iio/adc/rcar-gyroadc.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 130 drivers/iio/adc/rcar-gyroadc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 218 drivers/iio/adc/rcar-gyroadc.c *val &= BIT(priv->sample_width) - 1; BIT 23 drivers/iio/adc/rockchip_saradc.c #define SARADC_STAS_BUSY BIT(0) BIT 26 drivers/iio/adc/rockchip_saradc.c #define SARADC_CTRL_IRQ_STATUS BIT(6) BIT 27 drivers/iio/adc/rockchip_saradc.c #define SARADC_CTRL_IRQ_ENABLE BIT(5) BIT 28 drivers/iio/adc/rockchip_saradc.c #define SARADC_CTRL_POWER_CTRL BIT(3) BIT 125 drivers/iio/adc/rockchip_saradc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 126 drivers/iio/adc/rockchip_saradc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 16 drivers/iio/adc/sc27xx_adc.c #define SC27XX_MODULE_ADC_EN BIT(5) BIT 18 drivers/iio/adc/sc27xx_adc.c #define SC27XX_CLK_ADC_EN BIT(5) BIT 19 drivers/iio/adc/sc27xx_adc.c #define SC27XX_CLK_ADC_CLK_EN BIT(6) BIT 31 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_EN BIT(0) BIT 32 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_CHN_RUN BIT(1) BIT 33 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_12BIT_MODE BIT(2) BIT 43 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_IRQ_EN BIT(0) BIT 46 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_IRQ_CLR BIT(0) BIT 49 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_IRQ_RAW BIT(0) BIT 391 drivers/iio/adc/sc27xx_adc.c .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \ BIT 397 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 398 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 399 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 400 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 401 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 402 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 403 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 404 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 405 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 406 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 407 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 408 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 409 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 410 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 411 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 412 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 413 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 414 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 415 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 416 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 417 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)), BIT 418 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 419 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 420 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 421 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 422 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 423 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 424 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 425 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 426 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 427 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 428 drivers/iio/adc/sc27xx_adc.c SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)), BIT 31 drivers/iio/adc/spear_adc.c #define SPEAR_ADC_STATUS_START_CONVERSION BIT(0) BIT 33 drivers/iio/adc/spear_adc.c #define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4) BIT 35 drivers/iio/adc/spear_adc.c #define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9) BIT 209 drivers/iio/adc/spear_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 210 drivers/iio/adc/spear_adc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 211 drivers/iio/adc/spear_adc.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ BIT 34 drivers/iio/adc/stm32-adc-core.c #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) BIT 37 drivers/iio/adc/stm32-adc-core.c #define HAS_VBOOSTER BIT(0) BIT 38 drivers/iio/adc/stm32-adc-core.c #define HAS_ANASWVDD BIT(1) BIT 54 drivers/iio/adc/stm32-adc-core.h #define STM32F4_STRT BIT(4) BIT 55 drivers/iio/adc/stm32-adc-core.h #define STM32F4_EOC BIT(1) BIT 60 drivers/iio/adc/stm32-adc-core.h #define STM32F4_SCAN BIT(8) BIT 61 drivers/iio/adc/stm32-adc-core.h #define STM32F4_EOCIE BIT(5) BIT 64 drivers/iio/adc/stm32-adc-core.h #define STM32F4_SWSTART BIT(30) BIT 69 drivers/iio/adc/stm32-adc-core.h #define STM32F4_EOCS BIT(10) BIT 70 drivers/iio/adc/stm32-adc-core.h #define STM32F4_DDS BIT(9) BIT 71 drivers/iio/adc/stm32-adc-core.h #define STM32F4_DMA BIT(8) BIT 72 drivers/iio/adc/stm32-adc-core.h #define STM32F4_ADON BIT(0) BIT 75 drivers/iio/adc/stm32-adc-core.h #define STM32F4_EOC3 BIT(17) BIT 76 drivers/iio/adc/stm32-adc-core.h #define STM32F4_EOC2 BIT(9) BIT 77 drivers/iio/adc/stm32-adc-core.h #define STM32F4_EOC1 BIT(1) BIT 105 drivers/iio/adc/stm32-adc-core.h #define STM32MP1_VREGREADY BIT(12) BIT 106 drivers/iio/adc/stm32-adc-core.h #define STM32H7_EOC BIT(2) BIT 107 drivers/iio/adc/stm32-adc-core.h #define STM32H7_ADRDY BIT(0) BIT 113 drivers/iio/adc/stm32-adc-core.h #define STM32H7_ADCAL BIT(31) BIT 114 drivers/iio/adc/stm32-adc-core.h #define STM32H7_ADCALDIF BIT(30) BIT 115 drivers/iio/adc/stm32-adc-core.h #define STM32H7_DEEPPWD BIT(29) BIT 116 drivers/iio/adc/stm32-adc-core.h #define STM32H7_ADVREGEN BIT(28) BIT 117 drivers/iio/adc/stm32-adc-core.h #define STM32H7_LINCALRDYW6 BIT(27) BIT 118 drivers/iio/adc/stm32-adc-core.h #define STM32H7_LINCALRDYW5 BIT(26) BIT 119 drivers/iio/adc/stm32-adc-core.h #define STM32H7_LINCALRDYW4 BIT(25) BIT 120 drivers/iio/adc/stm32-adc-core.h #define STM32H7_LINCALRDYW3 BIT(24) BIT 121 drivers/iio/adc/stm32-adc-core.h #define STM32H7_LINCALRDYW2 BIT(23) BIT 122 drivers/iio/adc/stm32-adc-core.h #define STM32H7_LINCALRDYW1 BIT(22) BIT 123 drivers/iio/adc/stm32-adc-core.h #define STM32H7_ADCALLIN BIT(16) BIT 124 drivers/iio/adc/stm32-adc-core.h #define STM32H7_BOOST BIT(8) BIT 125 drivers/iio/adc/stm32-adc-core.h #define STM32H7_ADSTP BIT(4) BIT 126 drivers/iio/adc/stm32-adc-core.h #define STM32H7_ADSTART BIT(2) BIT 127 drivers/iio/adc/stm32-adc-core.h #define STM32H7_ADDIS BIT(1) BIT 128 drivers/iio/adc/stm32-adc-core.h #define STM32H7_ADEN BIT(0) BIT 158 drivers/iio/adc/stm32-adc-core.h #define STM32H7_EOC_SLV BIT(18) BIT 159 drivers/iio/adc/stm32-adc-core.h #define STM32H7_EOC_MST BIT(2) BIT 1638 drivers/iio/adc/stm32-adc.c chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); BIT 1639 drivers/iio/adc/stm32-adc.c chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | BIT 1640 drivers/iio/adc/stm32-adc.c BIT(IIO_CHAN_INFO_OFFSET); BIT 1647 drivers/iio/adc/stm32-adc.c adc->pcsel |= BIT(chan->channel); BIT 1650 drivers/iio/adc/stm32-adc.c adc->difsel |= BIT(chan->channel); BIT 1652 drivers/iio/adc/stm32-adc.c adc->pcsel |= BIT(chan->channel2); BIT 43 drivers/iio/adc/stm32-dfsdm-adc.c #define DFSDM_DATA_MAX BIT(30) BIT 264 drivers/iio/adc/stm32-dfsdm-adc.c if (flo->res > BIT(bits - 1)) BIT 570 drivers/iio/adc/stm32-dfsdm-adc.c jchg |= BIT(chan->channel); BIT 1161 drivers/iio/adc/stm32-dfsdm-adc.c adc->smask = BIT(chan->scan_index); BIT 1406 drivers/iio/adc/stm32-dfsdm-adc.c ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); BIT 1407 drivers/iio/adc/stm32-dfsdm-adc.c ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | BIT 1408 drivers/iio/adc/stm32-dfsdm-adc.c BIT(IIO_CHAN_INFO_SAMP_FREQ); BIT 1441 drivers/iio/adc/stm32-dfsdm-adc.c ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ); BIT 51 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_SCDEN_MASK BIT(5) BIT 53 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_CKABEN_MASK BIT(6) BIT 55 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_CHEN_MASK BIT(7) BIT 57 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_CHINSEL_MASK BIT(8) BIT 65 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_CKOUTSRC_MASK BIT(30) BIT 67 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_DFSDMEN_MASK BIT(31) BIT 110 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_DFEN_MASK BIT(0) BIT 112 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_JSWSTART_MASK BIT(1) BIT 114 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_JSYNC_MASK BIT(3) BIT 116 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_JSCAN_MASK BIT(4) BIT 118 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_JDMAEN_MASK BIT(5) BIT 124 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_RSWSTART_MASK BIT(17) BIT 126 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_RCONT_MASK BIT(18) BIT 128 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_RSYNC_MASK BIT(19) BIT 130 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_RDMAEN_MASK BIT(21) BIT 134 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_FAST_MASK BIT(29) BIT 136 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_AWFSEL_MASK BIT(30) BIT 142 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR2_JEOCIE_MASK BIT(0) BIT 144 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR2_REOCIE_MASK BIT(1) BIT 146 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR2_JOVRIE_MASK BIT(2) BIT 148 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR2_ROVRIE_MASK BIT(3) BIT 150 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR2_AWDIE_MASK BIT(4) BIT 152 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR2_SCDIE_MASK BIT(5) BIT 154 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR2_CKABIE_MASK BIT(6) BIT 162 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ISR_JEOCF_MASK BIT(0) BIT 164 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ISR_REOCF_MASK BIT(1) BIT 166 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ISR_JOVRF_MASK BIT(2) BIT 168 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ISR_ROVRF_MASK BIT(3) BIT 170 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ISR_AWDF_MASK BIT(4) BIT 172 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ISR_JCIP_MASK BIT(13) BIT 174 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ISR_RCIP_MASK BIT(14) BIT 182 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ICR_CLRJOVRF_MASK BIT(2) BIT 184 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ICR_CLRROVRF_MASK BIT(3) BIT 188 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ICR_CLRCKABF_CH_MASK(y) BIT(16 + (y)) BIT 193 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ICR_CLRSCDF_CH_MASK(y) BIT(24 + (y)) BIT 31 drivers/iio/adc/stmpe-adc.c #define STMPE_TEMP_CTRL_ENABLE BIT(0) BIT 32 drivers/iio/adc/stmpe-adc.c #define STMPE_TEMP_CTRL_ACQ BIT(1) BIT 33 drivers/iio/adc/stmpe-adc.c #define STMPE_TEMP_CTRL_THRES_EN BIT(3) BIT 215 drivers/iio/adc/stmpe-adc.c ics->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); BIT 216 drivers/iio/adc/stmpe-adc.c ics->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); BIT 224 drivers/iio/adc/stmpe-adc.c ics->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED); BIT 23 drivers/iio/adc/stx104.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 31 drivers/iio/adc/stx104.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_HARDWAREGAIN) | \ BIT 32 drivers/iio/adc/stx104.c BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_SCALE), \ BIT 33 drivers/iio/adc/stx104.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 98 drivers/iio/adc/stx104.c while (inb(priv->base + 8) & BIT(7)); BIT 105 drivers/iio/adc/stx104.c adbu = !(adc_config & BIT(2)); BIT 112 drivers/iio/adc/stx104.c adbu = !(adc_config & BIT(2)); BIT 225 drivers/iio/adc/stx104.c return !!(inb(stx104gpio->base) & BIT(offset)); BIT 242 drivers/iio/adc/stx104.c const unsigned int mask = BIT(offset) >> 4; BIT 313 drivers/iio/adc/stx104.c if (inb(base[id] + 8) & BIT(5)) { BIT 113 drivers/iio/adc/sun4i-gpadc-iio.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 114 drivers/iio/adc/sun4i-gpadc-iio.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 133 drivers/iio/adc/sun4i-gpadc-iio.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 134 drivers/iio/adc/sun4i-gpadc-iio.c BIT(IIO_CHAN_INFO_SCALE) | BIT 135 drivers/iio/adc/sun4i-gpadc-iio.c BIT(IIO_CHAN_INFO_OFFSET), BIT 150 drivers/iio/adc/sun4i-gpadc-iio.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 151 drivers/iio/adc/sun4i-gpadc-iio.c BIT(IIO_CHAN_INFO_SCALE) | BIT 152 drivers/iio/adc/sun4i-gpadc-iio.c BIT(IIO_CHAN_INFO_OFFSET), BIT 75 drivers/iio/adc/ti-adc081c.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 76 drivers/iio/adc/ti-adc081c.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 41 drivers/iio/adc/ti-adc0832.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 42 drivers/iio/adc/ti-adc0832.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 58 drivers/iio/adc/ti-adc0832.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 59 drivers/iio/adc/ti-adc0832.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 49 drivers/iio/adc/ti-adc084s021.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 50 drivers/iio/adc/ti-adc084s021.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\ BIT 88 drivers/iio/adc/ti-adc108s102.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 89 drivers/iio/adc/ti-adc108s102.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 29 drivers/iio/adc/ti-adc12138.c #define ADC12138_STATUS_CAL BIT(6) BIT 60 drivers/iio/adc/ti-adc12138.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 61 drivers/iio/adc/ti-adc12138.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ BIT 62 drivers/iio/adc/ti-adc12138.c | BIT(IIO_CHAN_INFO_OFFSET), \ BIT 80 drivers/iio/adc/ti-adc12138.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 81 drivers/iio/adc/ti-adc12138.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ BIT 82 drivers/iio/adc/ti-adc12138.c | BIT(IIO_CHAN_INFO_OFFSET), \ BIT 97 drivers/iio/adc/ti-adc128s052.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 98 drivers/iio/adc/ti-adc128s052.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ BIT 35 drivers/iio/adc/ti-adc161s626.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 36 drivers/iio/adc/ti-adc161s626.c BIT(IIO_CHAN_INFO_SCALE) | BIT 37 drivers/iio/adc/ti-adc161s626.c BIT(IIO_CHAN_INFO_OFFSET), BIT 52 drivers/iio/adc/ti-adc161s626.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 53 drivers/iio/adc/ti-adc161s626.c BIT(IIO_CHAN_INFO_SCALE) | BIT 54 drivers/iio/adc/ti-adc161s626.c BIT(IIO_CHAN_INFO_OFFSET), BIT 51 drivers/iio/adc/ti-ads1015.c #define ADS1015_CFG_COMP_LAT_MASK BIT(2) BIT 52 drivers/iio/adc/ti-ads1015.c #define ADS1015_CFG_COMP_POL_MASK BIT(3) BIT 53 drivers/iio/adc/ti-ads1015.c #define ADS1015_CFG_COMP_MODE_MASK BIT(4) BIT 55 drivers/iio/adc/ti-ads1015.c #define ADS1015_CFG_MOD_MASK BIT(8) BIT 122 drivers/iio/adc/ti-ads1015.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 123 drivers/iio/adc/ti-ads1015.c BIT(IIO_EV_INFO_ENABLE), BIT 127 drivers/iio/adc/ti-ads1015.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 131 drivers/iio/adc/ti-ads1015.c .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT 132 drivers/iio/adc/ti-ads1015.c BIT(IIO_EV_INFO_PERIOD), BIT 141 drivers/iio/adc/ti-ads1015.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 142 drivers/iio/adc/ti-ads1015.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 143 drivers/iio/adc/ti-ads1015.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 164 drivers/iio/adc/ti-ads1015.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 165 drivers/iio/adc/ti-ads1015.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 166 drivers/iio/adc/ti-ads1015.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 185 drivers/iio/adc/ti-ads1015.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 186 drivers/iio/adc/ti-ads1015.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 187 drivers/iio/adc/ti-ads1015.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 207 drivers/iio/adc/ti-ads1015.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 208 drivers/iio/adc/ti-ads1015.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 209 drivers/iio/adc/ti-ads1015.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 108 drivers/iio/adc/ti-ads124s08.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 40 drivers/iio/adc/ti-ads7950.c #define TI_ADS7950_CR_GPIO BIT(14) BIT 41 drivers/iio/adc/ti-ads7950.c #define TI_ADS7950_CR_MANUAL BIT(12) BIT 42 drivers/iio/adc/ti-ads7950.c #define TI_ADS7950_CR_WRITE BIT(11) BIT 44 drivers/iio/adc/ti-ads7950.c #define TI_ADS7950_CR_RANGE_5V BIT(6) BIT 45 drivers/iio/adc/ti-ads7950.c #define TI_ADS7950_CR_GPIO_DATA BIT(4) BIT 141 drivers/iio/adc/ti-ads7950.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 142 drivers/iio/adc/ti-ads7950.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 414 drivers/iio/adc/ti-ads7950.c st->cmd_settings_bitmask |= BIT(offset); BIT 416 drivers/iio/adc/ti-ads7950.c st->cmd_settings_bitmask &= ~BIT(offset); BIT 432 drivers/iio/adc/ti-ads7950.c if (st->gpio_cmd_settings_bitmask & BIT(offset)) { BIT 433 drivers/iio/adc/ti-ads7950.c ret = st->cmd_settings_bitmask & BIT(offset); BIT 444 drivers/iio/adc/ti-ads7950.c ret = ((st->single_rx >> 12) & BIT(offset)) ? 1 : 0; BIT 465 drivers/iio/adc/ti-ads7950.c return !(st->gpio_cmd_settings_bitmask & BIT(offset)); BIT 477 drivers/iio/adc/ti-ads7950.c if (input && (st->gpio_cmd_settings_bitmask & BIT(offset))) BIT 478 drivers/iio/adc/ti-ads7950.c st->gpio_cmd_settings_bitmask &= ~BIT(offset); BIT 479 drivers/iio/adc/ti-ads7950.c else if (!input && !(st->gpio_cmd_settings_bitmask & BIT(offset))) BIT 480 drivers/iio/adc/ti-ads7950.c st->gpio_cmd_settings_bitmask |= BIT(offset); BIT 17 drivers/iio/adc/ti-ads8344.c #define ADS8344_START BIT(7) BIT 18 drivers/iio/adc/ti-ads8344.c #define ADS8344_SINGLE_END BIT(2) BIT 40 drivers/iio/adc/ti-ads8344.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 41 drivers/iio/adc/ti-ads8344.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 52 drivers/iio/adc/ti-ads8344.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 53 drivers/iio/adc/ti-ads8344.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 30 drivers/iio/adc/ti-ads8688.c #define ADS8688_PROG_WR_BIT BIT(8) BIT 156 drivers/iio/adc/ti-ads8688.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ BIT 157 drivers/iio/adc/ti-ads8688.c | BIT(IIO_CHAN_INFO_SCALE) \ BIT 158 drivers/iio/adc/ti-ads8688.c | BIT(IIO_CHAN_INFO_OFFSET), \ BIT 59 drivers/iio/adc/ti-tlc4541.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 60 drivers/iio/adc/ti-tlc4541.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 449 drivers/iio/adc/ti_am335x_adc.c chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); BIT 184 drivers/iio/adc/twl4030-madc.c req.channels = BIT(chan->channel); BIT 206 drivers/iio/adc/twl4030-madc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 207 drivers/iio/adc/twl4030-madc.c BIT(IIO_CHAN_INFO_AVERAGE_RAW) | \ BIT 208 drivers/iio/adc/twl4030-madc.c BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 48 drivers/iio/adc/twl6030-gpadc.c #define TWL6030_GPADC_CTRL_P1_SP1 BIT(3) BIT 52 drivers/iio/adc/twl6030-gpadc.c #define TWL6030_GPADC_RT_SW1_EOC_MASK BIT(5) BIT 57 drivers/iio/adc/twl6030-gpadc.c #define TWL6030_GPADCS BIT(1) BIT 58 drivers/iio/adc/twl6030-gpadc.c #define TWL6030_GPADCR BIT(0) BIT 792 drivers/iio/adc/twl6030-gpadc.c .info_mask_separate = BIT(chan_info), \ BIT 503 drivers/iio/adc/vf610_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 504 drivers/iio/adc/vf610_adc.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 505 drivers/iio/adc/vf610_adc.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 518 drivers/iio/adc/vf610_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 39 drivers/iio/adc/viperboard_adc.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 47 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_CFG_ENABLE BIT(31) BIT 52 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_CFG_WEDGE BIT(13) BIT 53 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_CFG_REDGE BIT(12) BIT 62 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_INT_CFIFO_LTH BIT(9) BIT 63 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_INT_DFIFO_GTH BIT(8) BIT 71 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_STATUS_CFIFOF BIT(11) BIT 72 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_STATUS_CFIFOE BIT(10) BIT 73 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_STATUS_DFIFOF BIT(9) BIT 74 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_STATUS_DFIFOE BIT(8) BIT 75 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_STATUS_OT BIT(7) BIT 76 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_STATUS_ALM(x) BIT(x) BIT 78 drivers/iio/adc/xilinx-xadc-core.c #define XADC_ZYNQ_CTL_RESET BIT(4) BIT 98 drivers/iio/adc/xilinx-xadc-core.c #define XADC_AXI_GIER_ENABLE BIT(31) BIT 100 drivers/iio/adc/xilinx-xadc-core.c #define XADC_AXI_INT_EOS BIT(4) BIT 103 drivers/iio/adc/xilinx-xadc-core.c #define XADC_FLAGS_BUFFERED BIT(0) BIT 773 drivers/iio/adc/xilinx-xadc-core.c scan_mask |= BIT(indio_dev->channels[i].scan_index); BIT 983 drivers/iio/adc/xilinx-xadc-core.c .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT 984 drivers/iio/adc/xilinx-xadc-core.c BIT(IIO_EV_INFO_VALUE) | BIT 985 drivers/iio/adc/xilinx-xadc-core.c BIT(IIO_EV_INFO_HYSTERESIS), BIT 994 drivers/iio/adc/xilinx-xadc-core.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 998 drivers/iio/adc/xilinx-xadc-core.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 1002 drivers/iio/adc/xilinx-xadc-core.c .mask_separate = BIT(IIO_EV_INFO_ENABLE), BIT 1011 drivers/iio/adc/xilinx-xadc-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 1012 drivers/iio/adc/xilinx-xadc-core.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 1013 drivers/iio/adc/xilinx-xadc-core.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 1014 drivers/iio/adc/xilinx-xadc-core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 1032 drivers/iio/adc/xilinx-xadc-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 1033 drivers/iio/adc/xilinx-xadc-core.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 1034 drivers/iio/adc/xilinx-xadc-core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 1301 drivers/iio/adc/xilinx-xadc-core.c bipolar_mask |= BIT(indio_dev->channels[i].scan_index); BIT 159 drivers/iio/adc/xilinx-xadc.h #define XADC_CONF0_EC BIT(9) BIT 160 drivers/iio/adc/xilinx-xadc.h #define XADC_CONF0_ACQ BIT(8) BIT 161 drivers/iio/adc/xilinx-xadc.h #define XADC_CONF0_MUX BIT(11) BIT 181 drivers/iio/adc/xilinx-xadc.h #define XADC_ALARM_TEMP_MASK BIT(0) BIT 182 drivers/iio/adc/xilinx-xadc.h #define XADC_ALARM_VCCINT_MASK BIT(1) BIT 183 drivers/iio/adc/xilinx-xadc.h #define XADC_ALARM_VCCAUX_MASK BIT(2) BIT 184 drivers/iio/adc/xilinx-xadc.h #define XADC_ALARM_OT_MASK BIT(3) BIT 185 drivers/iio/adc/xilinx-xadc.h #define XADC_ALARM_VCCBRAM_MASK BIT(4) BIT 186 drivers/iio/adc/xilinx-xadc.h #define XADC_ALARM_VCCPINT_MASK BIT(5) BIT 187 drivers/iio/adc/xilinx-xadc.h #define XADC_ALARM_VCCPAUX_MASK BIT(6) BIT 188 drivers/iio/adc/xilinx-xadc.h #define XADC_ALARM_VCCODDR_MASK BIT(7) BIT 139 drivers/iio/afe/iio-rescale.c chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 140 drivers/iio/afe/iio-rescale.c BIT(IIO_CHAN_INFO_SCALE); BIT 143 drivers/iio/afe/iio-rescale.c chan->info_mask_separate_available |= BIT(IIO_CHAN_INFO_RAW); BIT 193 drivers/iio/amplifiers/ad8366.c .info_mask_separate = BIT(IIO_CHAN_INFO_HARDWAREGAIN),\ BIT 41 drivers/iio/chemical/ams-iaq-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 46 drivers/iio/chemical/ams-iaq-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 53 drivers/iio/chemical/ams-iaq-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 35 drivers/iio/chemical/atlas-ph-sensor.c #define ATLAS_REG_INT_CONTROL_EN BIT(3) BIT 41 drivers/iio/chemical/atlas-ph-sensor.c #define ATLAS_REG_PH_CALIB_STATUS_LOW BIT(0) BIT 42 drivers/iio/chemical/atlas-ph-sensor.c #define ATLAS_REG_PH_CALIB_STATUS_MID BIT(1) BIT 43 drivers/iio/chemical/atlas-ph-sensor.c #define ATLAS_REG_PH_CALIB_STATUS_HIGH BIT(2) BIT 47 drivers/iio/chemical/atlas-ph-sensor.c #define ATLAS_REG_EC_CALIB_STATUS_DRY BIT(0) BIT 48 drivers/iio/chemical/atlas-ph-sensor.c #define ATLAS_REG_EC_CALIB_STATUS_SINGLE BIT(1) BIT 49 drivers/iio/chemical/atlas-ph-sensor.c #define ATLAS_REG_EC_CALIB_STATUS_LOW BIT(2) BIT 50 drivers/iio/chemical/atlas-ph-sensor.c #define ATLAS_REG_EC_CALIB_STATUS_HIGH BIT(3) BIT 95 drivers/iio/chemical/atlas-ph-sensor.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 109 drivers/iio/chemical/atlas-ph-sensor.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 122 drivers/iio/chemical/atlas-ph-sensor.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), \ BIT 137 drivers/iio/chemical/atlas-ph-sensor.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 153 drivers/iio/chemical/atlas-ph-sensor.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 164 drivers/iio/chemical/atlas-ph-sensor.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 10 drivers/iio/chemical/bme680.h #define BME680_SPI_MEM_PAGE_BIT BIT(4) BIT 18 drivers/iio/chemical/bme680.h #define BME680_GAS_STAB_BIT BIT(4) BIT 33 drivers/iio/chemical/bme680.h #define BME680_FILTER_COEFF_VAL BIT(1) BIT 53 drivers/iio/chemical/bme680.h #define BME680_RUN_GAS_MASK BIT(4) BIT 57 drivers/iio/chemical/bme680.h #define BME680_GAS_MEAS_BIT BIT(6) BIT 89 drivers/iio/chemical/bme680_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 90 drivers/iio/chemical/bme680_core.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 94 drivers/iio/chemical/bme680_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 95 drivers/iio/chemical/bme680_core.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 99 drivers/iio/chemical/bme680_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 100 drivers/iio/chemical/bme680_core.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 104 drivers/iio/chemical/bme680_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 41 drivers/iio/chemical/ccs811.c #define CCS811_STATUS_ERROR BIT(0) BIT 42 drivers/iio/chemical/ccs811.c #define CCS811_STATUS_DATA_READY BIT(3) BIT 43 drivers/iio/chemical/ccs811.c #define CCS811_STATUS_APP_VALID_MASK BIT(4) BIT 44 drivers/iio/chemical/ccs811.c #define CCS811_STATUS_APP_VALID_LOADED BIT(4) BIT 50 drivers/iio/chemical/ccs811.c #define CCS811_STATUS_FW_MODE_MASK BIT(7) BIT 51 drivers/iio/chemical/ccs811.c #define CCS811_STATUS_FW_MODE_APPLICATION BIT(7) BIT 60 drivers/iio/chemical/ccs811.c #define CCS811_MEAS_MODE_INTERRUPT BIT(3) BIT 83 drivers/iio/chemical/ccs811.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 84 drivers/iio/chemical/ccs811.c BIT(IIO_CHAN_INFO_SCALE), BIT 88 drivers/iio/chemical/ccs811.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 89 drivers/iio/chemical/ccs811.c BIT(IIO_CHAN_INFO_SCALE), BIT 95 drivers/iio/chemical/ccs811.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 96 drivers/iio/chemical/ccs811.c BIT(IIO_CHAN_INFO_SCALE), BIT 108 drivers/iio/chemical/ccs811.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 109 drivers/iio/chemical/ccs811.c BIT(IIO_CHAN_INFO_SCALE), BIT 177 drivers/iio/chemical/pms7003.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 140 drivers/iio/chemical/sgp30.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 147 drivers/iio/chemical/sgp30.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 154 drivers/iio/chemical/sgp30.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 161 drivers/iio/chemical/sgp30.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 171 drivers/iio/chemical/sgp30.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 178 drivers/iio/chemical/sgp30.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 443 drivers/iio/chemical/sps30.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 444 drivers/iio/chemical/sps30.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 70 drivers/iio/chemical/vz89x.c BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_RAW), BIT 77 drivers/iio/chemical/vz89x.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 86 drivers/iio/chemical/vz89x.c BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_RAW), BIT 92 drivers/iio/chemical/vz89x.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 107 drivers/iio/chemical/vz89x.c BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_RAW), BIT 116 drivers/iio/chemical/vz89x.c BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_RAW), BIT 122 drivers/iio/chemical/vz89x.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 35 drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 250 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c BIT(IIO_CHAN_INFO_RAW) | BIT 251 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 252 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c BIT(IIO_CHAN_INFO_CALIBSCALE); BIT 254 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c BIT(IIO_CHAN_INFO_SCALE) | BIT 255 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c BIT(IIO_CHAN_INFO_FREQUENCY) | BIT 256 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c BIT(IIO_CHAN_INFO_SAMP_FREQ); BIT 258 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c BIT(IIO_CHAN_INFO_SAMP_FREQ); BIT 119 drivers/iio/common/hid-sensors/hid-sensor-attributes.c if (value & BIT(size*8 - 1)) { BIT 75 drivers/iio/common/ssp_sensors/ssp_dev.c if (data->available_sensors & BIT(i)) { BIT 242 drivers/iio/common/ssp_sensors/ssp_dev.c data->sensor_enable |= BIT(type); BIT 316 drivers/iio/common/ssp_sensors/ssp_dev.c if (data->sensor_enable & BIT(type)) { BIT 328 drivers/iio/common/ssp_sensors/ssp_dev.c data->sensor_enable &= ~BIT(type); BIT 10 drivers/iio/common/ssp_sensors/ssp_iio_sensor.h .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ BIT 483 drivers/iio/common/ssp_sensors/ssp_spi.c } else if (!(data->available_sensors & BIT(sensor_type)) && BIT 47 drivers/iio/dac/ad5064.c #define AD5064_CONFIG_DAISY_CHAIN_ENABLE BIT(1) BIT 48 drivers/iio/dac/ad5064.c #define AD5064_CONFIG_INT_VREF_ENABLE BIT(0) BIT 401 drivers/iio/dac/ad5064.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 402 drivers/iio/dac/ad5064.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 40 drivers/iio/dac/ad5360.c #define AD5360_SF_CTRL_PWR_DOWN BIT(0) BIT 104 drivers/iio/dac/ad5360.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 105 drivers/iio/dac/ad5360.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 106 drivers/iio/dac/ad5360.c BIT(IIO_CHAN_INFO_OFFSET) | \ BIT 107 drivers/iio/dac/ad5360.c BIT(IIO_CHAN_INFO_CALIBSCALE) | \ BIT 108 drivers/iio/dac/ad5360.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 31 drivers/iio/dac/ad5380.c #define AD5380_CTRL_INT_VREF_2V5 BIT(12) BIT 32 drivers/iio/dac/ad5380.c #define AD5380_CTRL_INT_VREF_EN BIT(10) BIT 258 drivers/iio/dac/ad5380.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 259 drivers/iio/dac/ad5380.c BIT(IIO_CHAN_INFO_CALIBSCALE) | \ BIT 260 drivers/iio/dac/ad5380.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 261 drivers/iio/dac/ad5380.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 37 drivers/iio/dac/ad5421.c #define AD5421_CTRL_WATCHDOG_DISABLE BIT(12) BIT 38 drivers/iio/dac/ad5421.c #define AD5421_CTRL_AUTO_FAULT_READBACK BIT(11) BIT 39 drivers/iio/dac/ad5421.c #define AD5421_CTRL_MIN_CURRENT BIT(9) BIT 40 drivers/iio/dac/ad5421.c #define AD5421_CTRL_ADC_SOURCE_TEMP BIT(8) BIT 41 drivers/iio/dac/ad5421.c #define AD5421_CTRL_ADC_ENABLE BIT(7) BIT 42 drivers/iio/dac/ad5421.c #define AD5421_CTRL_PWR_DOWN_INT_VREF BIT(6) BIT 44 drivers/iio/dac/ad5421.c #define AD5421_FAULT_SPI BIT(15) BIT 45 drivers/iio/dac/ad5421.c #define AD5421_FAULT_PEC BIT(14) BIT 46 drivers/iio/dac/ad5421.c #define AD5421_FAULT_OVER_CURRENT BIT(13) BIT 47 drivers/iio/dac/ad5421.c #define AD5421_FAULT_UNDER_CURRENT BIT(12) BIT 48 drivers/iio/dac/ad5421.c #define AD5421_FAULT_TEMP_OVER_140 BIT(11) BIT 49 drivers/iio/dac/ad5421.c #define AD5421_FAULT_TEMP_OVER_100 BIT(10) BIT 50 drivers/iio/dac/ad5421.c #define AD5421_FAULT_UNDER_VOLTAGE_6V BIT(9) BIT 51 drivers/iio/dac/ad5421.c #define AD5421_FAULT_UNDER_VOLTAGE_12V BIT(8) BIT 86 drivers/iio/dac/ad5421.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 87 drivers/iio/dac/ad5421.c BIT(IIO_EV_INFO_ENABLE), BIT 91 drivers/iio/dac/ad5421.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 92 drivers/iio/dac/ad5421.c BIT(IIO_EV_INFO_ENABLE), BIT 100 drivers/iio/dac/ad5421.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 101 drivers/iio/dac/ad5421.c BIT(IIO_EV_INFO_ENABLE), BIT 111 drivers/iio/dac/ad5421.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 112 drivers/iio/dac/ad5421.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 113 drivers/iio/dac/ad5421.c BIT(IIO_CHAN_INFO_CALIBBIAS), BIT 114 drivers/iio/dac/ad5421.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | BIT 115 drivers/iio/dac/ad5421.c BIT(IIO_CHAN_INFO_OFFSET), BIT 146 drivers/iio/dac/ad5446.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 147 drivers/iio/dac/ad5446.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 35 drivers/iio/dac/ad5449.c #define AD5449_CTRL_DAISY_CHAIN BIT(9) BIT 36 drivers/iio/dac/ad5449.c #define AD5449_CTRL_HCLR_TO_MIDSCALE BIT(8) BIT 37 drivers/iio/dac/ad5449.c #define AD5449_CTRL_SAMPLE_RISING BIT(7) BIT 202 drivers/iio/dac/ad5449.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 203 drivers/iio/dac/ad5449.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 25 drivers/iio/dac/ad5504.c #define AD5504_CMD_READ BIT(15) BIT 254 drivers/iio/dac/ad5504.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 255 drivers/iio/dac/ad5504.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 33 drivers/iio/dac/ad5592r-base.c if (st->gpio_out & BIT(offset)) BIT 43 drivers/iio/dac/ad5592r-base.c return !!(val & BIT(offset)); BIT 53 drivers/iio/dac/ad5592r-base.c st->gpio_val |= BIT(offset); BIT 55 drivers/iio/dac/ad5592r-base.c st->gpio_val &= ~BIT(offset); BIT 69 drivers/iio/dac/ad5592r-base.c st->gpio_out &= ~BIT(offset); BIT 70 drivers/iio/dac/ad5592r-base.c st->gpio_in |= BIT(offset); BIT 93 drivers/iio/dac/ad5592r-base.c st->gpio_val |= BIT(offset); BIT 95 drivers/iio/dac/ad5592r-base.c st->gpio_val &= ~BIT(offset); BIT 97 drivers/iio/dac/ad5592r-base.c st->gpio_in &= ~BIT(offset); BIT 98 drivers/iio/dac/ad5592r-base.c st->gpio_out |= BIT(offset); BIT 120 drivers/iio/dac/ad5592r-base.c if (!(st->gpio_map & BIT(offset))) { BIT 208 drivers/iio/dac/ad5592r-base.c dac |= BIT(i); BIT 212 drivers/iio/dac/ad5592r-base.c adc |= BIT(i); BIT 216 drivers/iio/dac/ad5592r-base.c dac |= BIT(i); BIT 217 drivers/iio/dac/ad5592r-base.c adc |= BIT(i); BIT 221 drivers/iio/dac/ad5592r-base.c st->gpio_map |= BIT(i); BIT 222 drivers/iio/dac/ad5592r-base.c st->gpio_in |= BIT(i); /* Default to input */ BIT 230 drivers/iio/dac/ad5592r-base.c tristate |= BIT(i); BIT 234 drivers/iio/dac/ad5592r-base.c st->gpio_out |= BIT(i); BIT 238 drivers/iio/dac/ad5592r-base.c st->gpio_out |= BIT(i); BIT 239 drivers/iio/dac/ad5592r-base.c st->gpio_val |= BIT(i); BIT 245 drivers/iio/dac/ad5592r-base.c pulldown |= BIT(i); BIT 506 drivers/iio/dac/ad5592r-base.c chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); BIT 507 drivers/iio/dac/ad5592r-base.c chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); BIT 574 drivers/iio/dac/ad5592r-base.c channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 575 drivers/iio/dac/ad5592r-base.c BIT(IIO_CHAN_INFO_SCALE) | BIT 576 drivers/iio/dac/ad5592r-base.c BIT(IIO_CHAN_INFO_OFFSET); BIT 38 drivers/iio/dac/ad5592r-base.h #define AD5592R_REG_PD_EN_REF BIT(9) BIT 39 drivers/iio/dac/ad5592r-base.h #define AD5592R_REG_CTRL_ADC_RANGE BIT(5) BIT 40 drivers/iio/dac/ad5592r-base.h #define AD5592R_REG_CTRL_DAC_RANGE BIT(4) BIT 17 drivers/iio/dac/ad5592r.c #define AD5592R_GPIO_READBACK_EN BIT(10) BIT 18 drivers/iio/dac/ad5592r.c #define AD5592R_LDAC_READBACK_EN BIT(6) BIT 38 drivers/iio/dac/ad5592r.c st->spi_msg = cpu_to_be16(BIT(15) | (chan << 12) | value); BIT 48 drivers/iio/dac/ad5592r.c st->spi_msg = cpu_to_be16((AD5592R_REG_ADC_SEQ << 11) | BIT(chan)); BIT 38 drivers/iio/dac/ad5593r.c AD5593R_MODE_CONF | AD5592R_REG_ADC_SEQ, BIT(chan)); BIT 171 drivers/iio/dac/ad5624r_spi.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 172 drivers/iio/dac/ad5624r_spi.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 196 drivers/iio/dac/ad5686.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 197 drivers/iio/dac/ad5686.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\ BIT 45 drivers/iio/dac/ad5686.h #define AD5310_REF_BIT_MSK BIT(8) BIT 46 drivers/iio/dac/ad5686.h #define AD5683_REF_BIT_MSK BIT(12) BIT 47 drivers/iio/dac/ad5686.h #define AD5693_REF_BIT_MSK BIT(12) BIT 50 drivers/iio/dac/ad5755.c #define AD5755_DAC_INT_EN BIT(8) BIT 51 drivers/iio/dac/ad5755.c #define AD5755_DAC_CLR_EN BIT(7) BIT 52 drivers/iio/dac/ad5755.c #define AD5755_DAC_OUT_EN BIT(6) BIT 53 drivers/iio/dac/ad5755.c #define AD5755_DAC_INT_CURRENT_SENSE_RESISTOR BIT(5) BIT 54 drivers/iio/dac/ad5755.c #define AD5755_DAC_DC_DC_EN BIT(4) BIT 55 drivers/iio/dac/ad5755.c #define AD5755_DAC_VOLTAGE_OVERRANGE_EN BIT(3) BIT 60 drivers/iio/dac/ad5755.c #define AD5755_EXT_DC_DC_COMP_RES BIT(6) BIT 64 drivers/iio/dac/ad5755.c #define AD5755_SLEW_ENABLE BIT(12) BIT 247 drivers/iio/dac/ad5755.c unsigned int mask = BIT(channel); BIT 434 drivers/iio/dac/ad5755.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 435 drivers/iio/dac/ad5755.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 436 drivers/iio/dac/ad5755.c BIT(IIO_CHAN_INFO_OFFSET) | \ BIT 437 drivers/iio/dac/ad5755.c BIT(IIO_CHAN_INFO_CALIBSCALE) | \ BIT 438 drivers/iio/dac/ad5755.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 54 drivers/iio/dac/ad5758.c #define AD5758_DAC_CONFIG_INT_EN_MSK BIT(5) BIT 56 drivers/iio/dac/ad5758.c #define AD5758_DAC_CONFIG_OUT_EN_MSK BIT(6) BIT 58 drivers/iio/dac/ad5758.c #define AD5758_DAC_CONFIG_SR_EN_MSK BIT(8) BIT 81 drivers/iio/dac/ad5758.c #define AD5758_DCDC_CONFIG2_INTR_SAT_3WI_MSK BIT(11) BIT 82 drivers/iio/dac/ad5758.c #define AD5758_DCDC_CONFIG2_BUSY_3WI_MSK BIT(12) BIT 85 drivers/iio/dac/ad5758.c #define AD5758_CAL_MEM_UNREFRESHED_MSK BIT(15) BIT 89 drivers/iio/dac/ad5758.c #define AD5758_ADC_CONFIG_PPC_BUF_MSK BIT(11) BIT 638 drivers/iio/dac/ad5758.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \ BIT 639 drivers/iio/dac/ad5758.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 640 drivers/iio/dac/ad5758.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 26 drivers/iio/dac/ad5761.c #define AD5761_CTRL_USE_INTVREF BIT(5) BIT 27 drivers/iio/dac/ad5761.c #define AD5761_CTRL_ETS BIT(6) BIT 258 drivers/iio/dac/ad5761.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 259 drivers/iio/dac/ad5761.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 260 drivers/iio/dac/ad5761.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 80 drivers/iio/dac/ad5764.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 81 drivers/iio/dac/ad5764.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 82 drivers/iio/dac/ad5764.c BIT(IIO_CHAN_INFO_CALIBSCALE) | \ BIT 83 drivers/iio/dac/ad5764.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 84 drivers/iio/dac/ad5764.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET), \ BIT 26 drivers/iio/dac/ad5791.c #define AD5791_CMD_READ BIT(23) BIT 38 drivers/iio/dac/ad5791.c #define AD5791_CTRL_RBUF BIT(1) BIT 39 drivers/iio/dac/ad5791.c #define AD5791_CTRL_OPGND BIT(2) BIT 40 drivers/iio/dac/ad5791.c #define AD5791_CTRL_DACTRI BIT(3) BIT 41 drivers/iio/dac/ad5791.c #define AD5791_CTRL_BIN2SC BIT(4) BIT 42 drivers/iio/dac/ad5791.c #define AD5791_CTRL_SDODIS BIT(5) BIT 55 drivers/iio/dac/ad5791.c #define AD5791_SWCTRL_LDAC BIT(0) BIT 56 drivers/iio/dac/ad5791.c #define AD5791_SWCTRL_CLR BIT(1) BIT 57 drivers/iio/dac/ad5791.c #define AD5791_SWCTRL_RESET BIT(2) BIT 300 drivers/iio/dac/ad5791.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 301 drivers/iio/dac/ad5791.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 302 drivers/iio/dac/ad5791.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 22 drivers/iio/dac/ad7303.c #define AD7303_CFG_EXTERNAL_VREF BIT(15) BIT 23 drivers/iio/dac/ad7303.c #define AD7303_CFG_POWER_DOWN(ch) BIT(11 + (ch)) BIT 180 drivers/iio/dac/ad7303.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 181 drivers/iio/dac/ad7303.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 94 drivers/iio/dac/ad8801.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 95 drivers/iio/dac/ad8801.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 96 drivers/iio/dac/ad8801.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 25 drivers/iio/dac/cio-dac.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 45 drivers/iio/dac/dpot-dac.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) BIT 46 drivers/iio/dac/dpot-dac.c | BIT(IIO_CHAN_INFO_SCALE), BIT 47 drivers/iio/dac/dpot-dac.c .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW), BIT 31 drivers/iio/dac/ds4424.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 29 drivers/iio/dac/lpc18xx_dac.c #define LPC18XX_DAC_CR_BIAS BIT(16) BIT 31 drivers/iio/dac/lpc18xx_dac.c #define LPC18XX_DAC_CTRL_DMA_ENA BIT(3) BIT 44 drivers/iio/dac/lpc18xx_dac.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 45 drivers/iio/dac/lpc18xx_dac.c BIT(IIO_CHAN_INFO_SCALE), BIT 109 drivers/iio/dac/ltc1660.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 110 drivers/iio/dac/ltc1660.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 179 drivers/iio/dac/ltc2632.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 180 drivers/iio/dac/ltc2632.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 176 drivers/iio/dac/m62332.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 177 drivers/iio/dac/m62332.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 178 drivers/iio/dac/m62332.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 129 drivers/iio/dac/max517.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 130 drivers/iio/dac/max517.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 149 drivers/iio/dac/max5821.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 150 drivers/iio/dac/max5821.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \ BIT 249 drivers/iio/dac/mcp4725.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 250 drivers/iio/dac/mcp4725.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 258 drivers/iio/dac/mcp4725.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 259 drivers/iio/dac/mcp4725.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 40 drivers/iio/dac/mcp4922.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 41 drivers/iio/dac/mcp4922.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 22 drivers/iio/dac/stm32-dac-core.h #define STM32_DAC_CR_EN1 BIT(0) BIT 23 drivers/iio/dac/stm32-dac-core.h #define STM32H7_DAC_CR_HFSEL BIT(15) BIT 24 drivers/iio/dac/stm32-dac-core.h #define STM32_DAC_CR_EN2 BIT(16) BIT 222 drivers/iio/dac/stm32-dac.c BIT(IIO_CHAN_INFO_RAW) | \ BIT 223 drivers/iio/dac/stm32-dac.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 173 drivers/iio/dac/ti-dac082s085.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 174 drivers/iio/dac/ti-dac082s085.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 59 drivers/iio/dac/ti-dac5571.c #define DAC5571_POWERDOWN_FLAG BIT(0) BIT 61 drivers/iio/dac/ti-dac5571.c #define DAC5571_LOADMODE_DIRECT BIT(4) BIT 226 drivers/iio/dac/ti-dac5571.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 227 drivers/iio/dac/ti-dac5571.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 157 drivers/iio/dac/ti-dac7311.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 158 drivers/iio/dac/ti-dac7311.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 36 drivers/iio/dac/ti-dac7612.c priv->data[0] = BIT(DAC7612_START) | (channel << DAC7612_ADDRESS); BIT 58 drivers/iio/dac/ti-dac7612.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 59 drivers/iio/dac/ti-dac7612.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 98 drivers/iio/dac/ti-dac7612.c if ((val >= BIT(DAC7612_RESOLUTION)) || val < 0 || val2) BIT 23 drivers/iio/dac/vf610_dac.c #define VF610_DAC_DACEN BIT(15) BIT 24 drivers/iio/dac/vf610_dac.c #define VF610_DAC_DACRFS BIT(14) BIT 25 drivers/iio/dac/vf610_dac.c #define VF610_DAC_LPEN BIT(11) BIT 106 drivers/iio/dac/vf610_dac.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 107 drivers/iio/dac/vf610_dac.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 57 drivers/iio/dummy/iio_simple_dummy.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE), BIT 66 drivers/iio/dummy/iio_simple_dummy.c .mask_separate = BIT(IIO_EV_INFO_ENABLE), BIT 76 drivers/iio/dummy/iio_simple_dummy.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE), BIT 86 drivers/iio/dummy/iio_simple_dummy.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE), BIT 110 drivers/iio/dummy/iio_simple_dummy.c BIT(IIO_CHAN_INFO_RAW) | BIT 116 drivers/iio/dummy/iio_simple_dummy.c BIT(IIO_CHAN_INFO_OFFSET) | BIT 122 drivers/iio/dummy/iio_simple_dummy.c BIT(IIO_CHAN_INFO_SCALE), BIT 127 drivers/iio/dummy/iio_simple_dummy.c .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 157 drivers/iio/dummy/iio_simple_dummy.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 163 drivers/iio/dummy/iio_simple_dummy.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 183 drivers/iio/dummy/iio_simple_dummy.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 184 drivers/iio/dummy/iio_simple_dummy.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 185 drivers/iio/dummy/iio_simple_dummy.c .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 203 drivers/iio/dummy/iio_simple_dummy.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 210 drivers/iio/dummy/iio_simple_dummy.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 211 drivers/iio/dummy/iio_simple_dummy.c BIT(IIO_CHAN_INFO_CALIBBIAS), BIT 212 drivers/iio/dummy/iio_simple_dummy.c .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 229 drivers/iio/dummy/iio_simple_dummy.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 237 drivers/iio/dummy/iio_simple_dummy.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_ENABLE) | BIT 238 drivers/iio/dummy/iio_simple_dummy.c BIT(IIO_CHAN_INFO_CALIBHEIGHT), BIT 239 drivers/iio/dummy/iio_simple_dummy.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 250 drivers/iio/dummy/iio_simple_dummy.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 261 drivers/iio/dummy/iio_simple_dummy.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 941 drivers/iio/frequency/ad9523.c BIT(IIO_CHAN_INFO_RAW) | BIT 942 drivers/iio/frequency/ad9523.c BIT(IIO_CHAN_INFO_PHASE) | BIT 943 drivers/iio/frequency/ad9523.c BIT(IIO_CHAN_INFO_FREQUENCY); BIT 105 drivers/iio/frequency/adf4350.c st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); BIT 24 drivers/iio/frequency/adf4371.c #define ADF4371_ADDR_ASC_MSK BIT(2) BIT 26 drivers/iio/frequency/adf4371.c #define ADF4371_ADDR_ASC_R_MSK BIT(5) BIT 33 drivers/iio/frequency/adf4371.c #define ADF4371_FRAC1WORD_MSK BIT(0) BIT 49 drivers/iio/frequency/adf4371.c #define ADF4371_MUTE_LD_MSK BIT(7) BIT 76 drivers/iio/frequency/adf4371.c #define ADF4371_MAX_MODULUS2 BIT(14) BIT 149 drivers/iio/frequency/adf4371.c .read_flag_mask = BIT(7), BIT 354 drivers/iio/frequency/adf4371.c val = !(readval & BIT(bit)); BIT 398 drivers/iio/frequency/adf4371.c readval &= ~BIT(bit); BIT 133 drivers/iio/gyro/adis16080.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 134 drivers/iio/gyro/adis16080.c BIT(IIO_CHAN_INFO_SCALE), BIT 140 drivers/iio/gyro/adis16080.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 141 drivers/iio/gyro/adis16080.c BIT(IIO_CHAN_INFO_SCALE) | BIT 142 drivers/iio/gyro/adis16080.c BIT(IIO_CHAN_INFO_OFFSET), BIT 148 drivers/iio/gyro/adis16080.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 149 drivers/iio/gyro/adis16080.c BIT(IIO_CHAN_INFO_SCALE) | BIT 150 drivers/iio/gyro/adis16080.c BIT(IIO_CHAN_INFO_OFFSET), BIT 156 drivers/iio/gyro/adis16080.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 157 drivers/iio/gyro/adis16080.c BIT(IIO_CHAN_INFO_SCALE) | BIT 158 drivers/iio/gyro/adis16080.c BIT(IIO_CHAN_INFO_OFFSET), BIT 122 drivers/iio/gyro/adis16130.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 123 drivers/iio/gyro/adis16130.c BIT(IIO_CHAN_INFO_SCALE) | BIT 124 drivers/iio/gyro/adis16130.c BIT(IIO_CHAN_INFO_OFFSET), BIT 130 drivers/iio/gyro/adis16130.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 131 drivers/iio/gyro/adis16130.c BIT(IIO_CHAN_INFO_SCALE) | BIT 132 drivers/iio/gyro/adis16130.c BIT(IIO_CHAN_INFO_OFFSET), BIT 56 drivers/iio/gyro/adis16136.c #define ADIS16136_MSC_CTRL_MEMORY_TEST BIT(11) BIT 57 drivers/iio/gyro/adis16136.c #define ADIS16136_MSC_CTRL_SELF_TEST BIT(10) BIT 362 drivers/iio/gyro/adis16136.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 363 drivers/iio/gyro/adis16136.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 364 drivers/iio/gyro/adis16136.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), BIT 365 drivers/iio/gyro/adis16136.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 379 drivers/iio/gyro/adis16136.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 380 drivers/iio/gyro/adis16136.c BIT(IIO_CHAN_INFO_SCALE), BIT 469 drivers/iio/gyro/adis16136.c .status_error_mask = BIT(ADIS16136_DIAG_STAT_FLASH_UPDATE_FAIL) | BIT 470 drivers/iio/gyro/adis16136.c BIT(ADIS16136_DIAG_STAT_SPI_FAIL) | BIT 471 drivers/iio/gyro/adis16136.c BIT(ADIS16136_DIAG_STAT_SELF_TEST_FAIL) | BIT 472 drivers/iio/gyro/adis16136.c BIT(ADIS16136_DIAG_STAT_FLASH_CHKSUM_FAIL), BIT 124 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 125 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 126 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_SAMP_FREQ), 14), BIT 128 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_SAMP_FREQ), 14), BIT 130 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_SAMP_FREQ), 12), BIT 132 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_SAMP_FREQ), 12), BIT 134 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_SAMP_FREQ), 12), BIT 140 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 141 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 142 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_SAMP_FREQ), 14), BIT 144 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_SAMP_FREQ), 12), BIT 146 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_SAMP_FREQ), 12), BIT 148 drivers/iio/gyro/adis16260.c BIT(IIO_CHAN_INFO_SAMP_FREQ), 12), BIT 346 drivers/iio/gyro/adis16260.c .status_error_mask = BIT(ADIS16260_DIAG_STAT_FLASH_CHK_BIT) | BIT 347 drivers/iio/gyro/adis16260.c BIT(ADIS16260_DIAG_STAT_SELF_TEST_BIT) | BIT 348 drivers/iio/gyro/adis16260.c BIT(ADIS16260_DIAG_STAT_OVERFLOW_BIT) | BIT 349 drivers/iio/gyro/adis16260.c BIT(ADIS16260_DIAG_STAT_SPI_FAIL_BIT) | BIT 350 drivers/iio/gyro/adis16260.c BIT(ADIS16260_DIAG_STAT_FLASH_UPT_BIT) | BIT 351 drivers/iio/gyro/adis16260.c BIT(ADIS16260_DIAG_STAT_POWER_HIGH_BIT) | BIT 352 drivers/iio/gyro/adis16260.c BIT(ADIS16260_DIAG_STAT_POWER_LOW_BIT), BIT 376 drivers/iio/gyro/adxrs450.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 377 drivers/iio/gyro/adxrs450.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 378 drivers/iio/gyro/adxrs450.c BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW) | BIT 379 drivers/iio/gyro/adxrs450.c BIT(IIO_CHAN_INFO_SCALE), BIT 384 drivers/iio/gyro/adxrs450.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 385 drivers/iio/gyro/adxrs450.c BIT(IIO_CHAN_INFO_SCALE), BIT 393 drivers/iio/gyro/adxrs450.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 394 drivers/iio/gyro/adxrs450.c BIT(IIO_CHAN_INFO_SCALE) | BIT 395 drivers/iio/gyro/adxrs450.c BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW), BIT 400 drivers/iio/gyro/adxrs450.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 401 drivers/iio/gyro/adxrs450.c BIT(IIO_CHAN_INFO_SCALE), BIT 45 drivers/iio/gyro/bmg160_core.c #define BMG160_REG_PMU_BW_RES BIT(7) BIT 51 drivers/iio/gyro/bmg160_core.c #define BMG160_INT_MAP_0_BIT_ANY BIT(1) BIT 54 drivers/iio/gyro/bmg160_core.c #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0) BIT 62 drivers/iio/gyro/bmg160_core.c #define BMG160_DATA_ENABLE_INT BIT(7) BIT 65 drivers/iio/gyro/bmg160_core.c #define BMG160_INT1_BIT_OD BIT(1) BIT 74 drivers/iio/gyro/bmg160_core.c #define BMG160_INT_MOTION_X BIT(0) BIT 75 drivers/iio/gyro/bmg160_core.c #define BMG160_INT_MOTION_Y BIT(1) BIT 76 drivers/iio/gyro/bmg160_core.c #define BMG160_INT_MOTION_Z BIT(2) BIT 82 drivers/iio/gyro/bmg160_core.c #define BMG160_ANY_MOTION_BIT_X BIT(0) BIT 83 drivers/iio/gyro/bmg160_core.c #define BMG160_ANY_MOTION_BIT_Y BIT(1) BIT 84 drivers/iio/gyro/bmg160_core.c #define BMG160_ANY_MOTION_BIT_Z BIT(2) BIT 822 drivers/iio/gyro/bmg160_core.c .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | BIT 823 drivers/iio/gyro/bmg160_core.c BIT(IIO_EV_INFO_ENABLE) BIT 830 drivers/iio/gyro/bmg160_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 831 drivers/iio/gyro/bmg160_core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 832 drivers/iio/gyro/bmg160_core.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT 833 drivers/iio/gyro/bmg160_core.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ BIT 849 drivers/iio/gyro/bmg160_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 850 drivers/iio/gyro/bmg160_core.c BIT(IIO_CHAN_INFO_SCALE) | BIT 851 drivers/iio/gyro/bmg160_core.c BIT(IIO_CHAN_INFO_OFFSET), BIT 871 drivers/iio/gyro/bmg160_core.c BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), BIT 633 drivers/iio/gyro/fxas21002c_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 634 drivers/iio/gyro/fxas21002c_core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 635 drivers/iio/gyro/fxas21002c_core.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ BIT 636 drivers/iio/gyro/fxas21002c_core.c BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ BIT 637 drivers/iio/gyro/fxas21002c_core.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 650 drivers/iio/gyro/fxas21002c_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 51 drivers/iio/gyro/hid-sensor-gyro-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 52 drivers/iio/gyro/hid-sensor-gyro-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 53 drivers/iio/gyro/hid-sensor-gyro-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 54 drivers/iio/gyro/hid-sensor-gyro-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 55 drivers/iio/gyro/hid-sensor-gyro-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 61 drivers/iio/gyro/hid-sensor-gyro-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 62 drivers/iio/gyro/hid-sensor-gyro-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 63 drivers/iio/gyro/hid-sensor-gyro-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 64 drivers/iio/gyro/hid-sensor-gyro-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 65 drivers/iio/gyro/hid-sensor-gyro-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 71 drivers/iio/gyro/hid-sensor-gyro-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 72 drivers/iio/gyro/hid-sensor-gyro-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 73 drivers/iio/gyro/hid-sensor-gyro-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 74 drivers/iio/gyro/hid-sensor-gyro-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 75 drivers/iio/gyro/hid-sensor-gyro-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 263 drivers/iio/gyro/itg3200_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 264 drivers/iio/gyro/itg3200_core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 265 drivers/iio/gyro/itg3200_core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 276 drivers/iio/gyro/itg3200_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 277 drivers/iio/gyro/itg3200_core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 278 drivers/iio/gyro/itg3200_core.c BIT(IIO_CHAN_INFO_SCALE), BIT 279 drivers/iio/gyro/itg3200_core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 72 drivers/iio/gyro/mpu3050-core.c #define MPU3050_MEM_PRFTCH BIT(5) BIT 73 drivers/iio/gyro/mpu3050-core.c #define MPU3050_MEM_USER_BANK BIT(4) BIT 86 drivers/iio/gyro/mpu3050-core.c #define MPU3050_FIFO_EN_FOOTER BIT(0) BIT 87 drivers/iio/gyro/mpu3050-core.c #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1) BIT 88 drivers/iio/gyro/mpu3050-core.c #define MPU3050_FIFO_EN_AUX_YOUT BIT(2) BIT 89 drivers/iio/gyro/mpu3050-core.c #define MPU3050_FIFO_EN_AUX_XOUT BIT(3) BIT 90 drivers/iio/gyro/mpu3050-core.c #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4) BIT 91 drivers/iio/gyro/mpu3050-core.c #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5) BIT 92 drivers/iio/gyro/mpu3050-core.c #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6) BIT 93 drivers/iio/gyro/mpu3050-core.c #define MPU3050_FIFO_EN_TEMP_OUT BIT(7) BIT 130 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_RAW_RDY_EN BIT(0) BIT 131 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_DMP_DONE_EN BIT(1) BIT 132 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_MPU_RDY_EN BIT(2) BIT 133 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_ANYRD_2CLEAR BIT(4) BIT 134 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_LATCH_EN BIT(5) BIT 135 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_OPEN BIT(6) BIT 136 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_ACTL BIT(7) BIT 138 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_STATUS_RAW_RDY BIT(0) BIT 139 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_STATUS_DMP_DONE BIT(1) BIT 140 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_STATUS_MPU_RDY BIT(2) BIT 141 drivers/iio/gyro/mpu3050-core.c #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7) BIT 143 drivers/iio/gyro/mpu3050-core.c #define MPU3050_USR_CTRL_FIFO_EN BIT(6) BIT 144 drivers/iio/gyro/mpu3050-core.c #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5) BIT 145 drivers/iio/gyro/mpu3050-core.c #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3) BIT 146 drivers/iio/gyro/mpu3050-core.c #define MPU3050_USR_CTRL_FIFO_RST BIT(1) BIT 147 drivers/iio/gyro/mpu3050-core.c #define MPU3050_USR_CTRL_GYRO_RST BIT(0) BIT 153 drivers/iio/gyro/mpu3050-core.c #define MPU3050_PWR_MGM_STBY_ZG BIT(3) BIT 154 drivers/iio/gyro/mpu3050-core.c #define MPU3050_PWR_MGM_STBY_YG BIT(4) BIT 155 drivers/iio/gyro/mpu3050-core.c #define MPU3050_PWR_MGM_STBY_XG BIT(5) BIT 156 drivers/iio/gyro/mpu3050-core.c #define MPU3050_PWR_MGM_SLEEP BIT(6) BIT 157 drivers/iio/gyro/mpu3050-core.c #define MPU3050_PWR_MGM_RESET BIT(7) BIT 689 drivers/iio/gyro/mpu3050-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 690 drivers/iio/gyro/mpu3050-core.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 691 drivers/iio/gyro/mpu3050-core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 692 drivers/iio/gyro/mpu3050-core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ BIT 706 drivers/iio/gyro/mpu3050-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 707 drivers/iio/gyro/mpu3050-core.c BIT(IIO_CHAN_INFO_SCALE) | BIT 708 drivers/iio/gyro/mpu3050-core.c BIT(IIO_CHAN_INFO_OFFSET), BIT 709 drivers/iio/gyro/mpu3050-core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 43 drivers/iio/gyro/st_gyro_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 47 drivers/iio/gyro/st_gyro_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 51 drivers/iio/gyro/st_gyro_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 128 drivers/iio/gyro/st_gyro_core.c .value = BIT(0), BIT 206 drivers/iio/gyro/st_gyro_core.c .value = BIT(0), BIT 230 drivers/iio/gyro/st_gyro_core.c .mask = BIT(3), BIT 261 drivers/iio/gyro/st_gyro_core.c .mask = BIT(7), BIT 266 drivers/iio/gyro/st_gyro_core.c .mask = BIT(3), BIT 280 drivers/iio/gyro/st_gyro_core.c .value = BIT(0), BIT 354 drivers/iio/gyro/st_gyro_core.c .value = BIT(0), BIT 44 drivers/iio/health/afe4404.c #define AFE440X_CONTROL2_OSC_ENABLE BIT(9) BIT 129 drivers/iio/health/afe4404.c AFE440X_INTENSITY_CHAN(LED2, BIT(IIO_CHAN_INFO_OFFSET)), BIT 130 drivers/iio/health/afe4404.c AFE440X_INTENSITY_CHAN(ALED2, BIT(IIO_CHAN_INFO_OFFSET)), BIT 131 drivers/iio/health/afe4404.c AFE440X_INTENSITY_CHAN(LED1, BIT(IIO_CHAN_INFO_OFFSET)), BIT 132 drivers/iio/health/afe4404.c AFE440X_INTENSITY_CHAN(ALED1, BIT(IIO_CHAN_INFO_OFFSET)), BIT 58 drivers/iio/health/afe440x.h #define AFE440X_CONTROL0_REG_READ BIT(0) BIT 59 drivers/iio/health/afe440x.h #define AFE440X_CONTROL0_TM_COUNT_RST BIT(1) BIT 60 drivers/iio/health/afe440x.h #define AFE440X_CONTROL0_SW_RESET BIT(3) BIT 63 drivers/iio/health/afe440x.h #define AFE440X_CONTROL1_TIMEREN BIT(8) BIT 66 drivers/iio/health/afe440x.h #define AFE440X_TIAGAIN_ENSEPGAIN BIT(15) BIT 69 drivers/iio/health/afe440x.h #define AFE440X_CONTROL2_PDN_AFE BIT(0) BIT 70 drivers/iio/health/afe440x.h #define AFE440X_CONTROL2_PDN_RX BIT(1) BIT 71 drivers/iio/health/afe440x.h #define AFE440X_CONTROL2_DYNAMIC4 BIT(3) BIT 72 drivers/iio/health/afe440x.h #define AFE440X_CONTROL2_DYNAMIC3 BIT(4) BIT 73 drivers/iio/health/afe440x.h #define AFE440X_CONTROL2_DYNAMIC2 BIT(14) BIT 74 drivers/iio/health/afe440x.h #define AFE440X_CONTROL2_DYNAMIC1 BIT(20) BIT 95 drivers/iio/health/afe440x.h .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 106 drivers/iio/health/afe440x.h .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 107 drivers/iio/health/afe440x.h BIT(IIO_CHAN_INFO_SCALE), \ BIT 29 drivers/iio/health/max30100.c #define MAX30100_REG_INT_STATUS_PWR_RDY BIT(0) BIT 30 drivers/iio/health/max30100.c #define MAX30100_REG_INT_STATUS_SPO2_RDY BIT(4) BIT 31 drivers/iio/health/max30100.c #define MAX30100_REG_INT_STATUS_HR_RDY BIT(5) BIT 32 drivers/iio/health/max30100.c #define MAX30100_REG_INT_STATUS_FIFO_RDY BIT(7) BIT 35 drivers/iio/health/max30100.c #define MAX30100_REG_INT_ENABLE_SPO2_EN BIT(0) BIT 36 drivers/iio/health/max30100.c #define MAX30100_REG_INT_ENABLE_HR_EN BIT(1) BIT 37 drivers/iio/health/max30100.c #define MAX30100_REG_INT_ENABLE_FIFO_EN BIT(3) BIT 49 drivers/iio/health/max30100.c #define MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN BIT(0) BIT 50 drivers/iio/health/max30100.c #define MAX30100_REG_MODE_CONFIG_MODE_HR_EN BIT(1) BIT 52 drivers/iio/health/max30100.c #define MAX30100_REG_MODE_CONFIG_TEMP_EN BIT(3) BIT 53 drivers/iio/health/max30100.c #define MAX30100_REG_MODE_CONFIG_PWR BIT(7) BIT 56 drivers/iio/health/max30100.c #define MAX30100_REG_SPO2_CONFIG_100HZ BIT(2) BIT 57 drivers/iio/health/max30100.c #define MAX30100_REG_SPO2_CONFIG_HI_RES_EN BIT(6) BIT 146 drivers/iio/health/max30100.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 44 drivers/iio/health/max30102.c #define MAX30102_REG_INT_STATUS_PWR_RDY BIT(0) BIT 45 drivers/iio/health/max30102.c #define MAX30102_REG_INT_STATUS_PROX_INT BIT(4) BIT 46 drivers/iio/health/max30102.c #define MAX30102_REG_INT_STATUS_ALC_OVF BIT(5) BIT 47 drivers/iio/health/max30102.c #define MAX30102_REG_INT_STATUS_PPG_RDY BIT(6) BIT 48 drivers/iio/health/max30102.c #define MAX30102_REG_INT_STATUS_FIFO_RDY BIT(7) BIT 51 drivers/iio/health/max30102.c #define MAX30102_REG_INT_ENABLE_PROX_INT_EN BIT(4) BIT 52 drivers/iio/health/max30102.c #define MAX30102_REG_INT_ENABLE_ALC_OVF_EN BIT(5) BIT 53 drivers/iio/health/max30102.c #define MAX30102_REG_INT_ENABLE_PPG_EN BIT(6) BIT 54 drivers/iio/health/max30102.c #define MAX30102_REG_INT_ENABLE_FIFO_EN BIT(7) BIT 65 drivers/iio/health/max30102.c #define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES BIT(1) BIT 67 drivers/iio/health/max30102.c #define MAX30102_REG_FIFO_CONFIG_AFULL BIT(0) BIT 75 drivers/iio/health/max30102.c #define MAX30102_REG_MODE_CONFIG_PWR BIT(7) BIT 87 drivers/iio/health/max30102.c #define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS BIT(0) BIT 95 drivers/iio/health/max30102.c #define MAX30102_REG_TEMP_CONFIG_TEMP_EN BIT(0) BIT 122 drivers/iio/health/max30102.c BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR), BIT 127 drivers/iio/health/max30102.c BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR), BIT 128 drivers/iio/health/max30102.c BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) | BIT 129 drivers/iio/health/max30102.c BIT(MAX30105_LED_GREEN), BIT 153 drivers/iio/health/max30102.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 165 drivers/iio/health/max30102.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 199 drivers/iio/health/max30102.c case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR): BIT 202 drivers/iio/health/max30102.c case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) | BIT 203 drivers/iio/health/max30102.c BIT(MAX30105_LED_GREEN): BIT 47 drivers/iio/humidity/am2315.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 48 drivers/iio/humidity/am2315.c BIT(IIO_CHAN_INFO_SCALE), BIT 59 drivers/iio/humidity/am2315.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 60 drivers/iio/humidity/am2315.c BIT(IIO_CHAN_INFO_SCALE), BIT 282 drivers/iio/humidity/dht11.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), }, BIT 284 drivers/iio/humidity/dht11.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), } BIT 31 drivers/iio/humidity/hdc100x.c #define HDC100X_REG_CONFIG_ACQ_MODE BIT(12) BIT 32 drivers/iio/humidity/hdc100x.c #define HDC100X_REG_CONFIG_HEATER_EN BIT(13) BIT 88 drivers/iio/humidity/hdc100x.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 89 drivers/iio/humidity/hdc100x.c BIT(IIO_CHAN_INFO_SCALE) | BIT 90 drivers/iio/humidity/hdc100x.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 91 drivers/iio/humidity/hdc100x.c BIT(IIO_CHAN_INFO_OFFSET), BIT 103 drivers/iio/humidity/hdc100x.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 104 drivers/iio/humidity/hdc100x.c BIT(IIO_CHAN_INFO_SCALE) | BIT 105 drivers/iio/humidity/hdc100x.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 116 drivers/iio/humidity/hdc100x.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 31 drivers/iio/humidity/hid-sensor-humidity.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 32 drivers/iio/humidity/hid-sensor-humidity.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 33 drivers/iio/humidity/hid-sensor-humidity.c BIT(IIO_CHAN_INFO_SCALE) | BIT 34 drivers/iio/humidity/hid-sensor-humidity.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 35 drivers/iio/humidity/hid-sensor-humidity.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 29 drivers/iio/humidity/hts221_buffer.c #define HTS221_REG_DRDY_HL_MASK BIT(7) BIT 31 drivers/iio/humidity/hts221_buffer.c #define HTS221_REG_DRDY_PP_OD_MASK BIT(6) BIT 33 drivers/iio/humidity/hts221_buffer.c #define HTS221_REG_DRDY_EN_MASK BIT(2) BIT 35 drivers/iio/humidity/hts221_buffer.c #define HTS221_RH_DRDY_MASK BIT(1) BIT 36 drivers/iio/humidity/hts221_buffer.c #define HTS221_TEMP_DRDY_MASK BIT(0) BIT 35 drivers/iio/humidity/hts221_core.c #define HTS221_BDU_MASK BIT(2) BIT 36 drivers/iio/humidity/hts221_core.c #define HTS221_ENABLE_MASK BIT(7) BIT 102 drivers/iio/humidity/hts221_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 103 drivers/iio/humidity/hts221_core.c BIT(IIO_CHAN_INFO_OFFSET) | BIT 104 drivers/iio/humidity/hts221_core.c BIT(IIO_CHAN_INFO_SCALE) | BIT 105 drivers/iio/humidity/hts221_core.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 106 drivers/iio/humidity/hts221_core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 118 drivers/iio/humidity/hts221_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 119 drivers/iio/humidity/hts221_core.c BIT(IIO_CHAN_INFO_OFFSET) | BIT 120 drivers/iio/humidity/hts221_core.c BIT(IIO_CHAN_INFO_SCALE) | BIT 121 drivers/iio/humidity/hts221_core.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 122 drivers/iio/humidity/hts221_core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 19 drivers/iio/humidity/hts221_i2c.c #define HTS221_I2C_AUTO_INCREMENT BIT(7) BIT 18 drivers/iio/humidity/hts221_spi.c #define HTS221_SPI_READ BIT(7) BIT 19 drivers/iio/humidity/hts221_spi.c #define HTS221_SPI_AUTO_INCREMENT BIT(6) BIT 106 drivers/iio/humidity/htu21.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_PROCESSED), BIT 107 drivers/iio/humidity/htu21.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 111 drivers/iio/humidity/htu21.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_PROCESSED), BIT 112 drivers/iio/humidity/htu21.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 123 drivers/iio/humidity/htu21.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_PROCESSED), BIT 124 drivers/iio/humidity/htu21.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 26 drivers/iio/humidity/si7005.c #define SI7005_STATUS_NRDY BIT(0) BIT 27 drivers/iio/humidity/si7005.c #define SI7005_CONFIG_TEMP BIT(4) BIT 28 drivers/iio/humidity/si7005.c #define SI7005_CONFIG_START BIT(0) BIT 112 drivers/iio/humidity/si7005.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 113 drivers/iio/humidity/si7005.c BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), BIT 117 drivers/iio/humidity/si7005.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 118 drivers/iio/humidity/si7005.c BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), BIT 91 drivers/iio/humidity/si7020.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 92 drivers/iio/humidity/si7020.c BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), BIT 96 drivers/iio/humidity/si7020.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 97 drivers/iio/humidity/si7020.c BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), BIT 24 drivers/iio/imu/adis.c #define ADIS_MSC_CTRL_DATA_RDY_EN BIT(2) BIT 25 drivers/iio/imu/adis.c #define ADIS_MSC_CTRL_DATA_RDY_POL_HIGH BIT(1) BIT 26 drivers/iio/imu/adis.c #define ADIS_MSC_CTRL_DATA_RDY_DIO2 BIT(0) BIT 27 drivers/iio/imu/adis.c #define ADIS_GLOB_CMD_SW_RESET BIT(7) BIT 298 drivers/iio/imu/adis.c if (status & BIT(i)) { BIT 143 drivers/iio/imu/adis16400.c #define ADIS16334_RATE_INT_CLK BIT(0) BIT 149 drivers/iio/imu/adis16400.c #define ADIS16400_HAS_PROD_ID BIT(0) BIT 150 drivers/iio/imu/adis16400.c #define ADIS16400_NO_BURST BIT(1) BIT 151 drivers/iio/imu/adis16400.c #define ADIS16400_HAS_SLOW_MODE BIT(2) BIT 152 drivers/iio/imu/adis16400.c #define ADIS16400_HAS_SERIAL_NUMBER BIT(3) BIT 153 drivers/iio/imu/adis16400.c #define ADIS16400_BURST_DIAG_STAT BIT(4) BIT 694 drivers/iio/imu/adis16400.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 695 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 696 drivers/iio/imu/adis16400.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 718 drivers/iio/imu/adis16400.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 719 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 720 drivers/iio/imu/adis16400.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 721 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ BIT 722 drivers/iio/imu/adis16400.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 738 drivers/iio/imu/adis16400.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 739 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 740 drivers/iio/imu/adis16400.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 741 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ BIT 742 drivers/iio/imu/adis16400.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 758 drivers/iio/imu/adis16400.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 759 drivers/iio/imu/adis16400.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 760 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ BIT 761 drivers/iio/imu/adis16400.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 782 drivers/iio/imu/adis16400.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 783 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_OFFSET) | \ BIT 784 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 786 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ BIT 787 drivers/iio/imu/adis16400.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 803 drivers/iio/imu/adis16400.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 804 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_OFFSET) | \ BIT 805 drivers/iio/imu/adis16400.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 806 drivers/iio/imu/adis16400.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 822 drivers/iio/imu/adis16400.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 823 drivers/iio/imu/adis16400.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 824 drivers/iio/imu/adis16400.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 875 drivers/iio/imu/adis16400.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 876 drivers/iio/imu/adis16400.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 877 drivers/iio/imu/adis16400.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 1093 drivers/iio/imu/adis16400.c .status_error_mask = BIT(ADIS16400_DIAG_STAT_ZACCL_FAIL) | BIT 1094 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_YACCL_FAIL) | BIT 1095 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_XACCL_FAIL) | BIT 1096 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_XGYRO_FAIL) | BIT 1097 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_YGYRO_FAIL) | BIT 1098 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_ZGYRO_FAIL) | BIT 1099 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_ALARM2) | BIT 1100 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_ALARM1) | BIT 1101 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_FLASH_CHK) | BIT 1102 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_SELF_TEST) | BIT 1103 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_OVERFLOW) | BIT 1104 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_SPI_FAIL) | BIT 1105 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_FLASH_UPT) | BIT 1106 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_POWER_HIGH) | BIT 1107 drivers/iio/imu/adis16400.c BIT(ADIS16400_DIAG_STAT_POWER_LOW), BIT 1120 drivers/iio/imu/adis16400.c st->avail_scan_mask[0] |= BIT(ch->scan_index); BIT 249 drivers/iio/imu/adis16460.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 250 drivers/iio/imu/adis16460.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 251 drivers/iio/imu/adis16460.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 276 drivers/iio/imu/adis16460.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 277 drivers/iio/imu/adis16460.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 278 drivers/iio/imu/adis16460.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 279 drivers/iio/imu/adis16460.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 346 drivers/iio/imu/adis16460.c ret = adis_write_reg_16(&st->adis, ADIS16460_REG_GLOB_CMD, BIT(1)); BIT 394 drivers/iio/imu/adis16460.c .status_error_mask = BIT(ADIS16460_DIAG_STAT_IN_CLK_OOS) | BIT 395 drivers/iio/imu/adis16460.c BIT(ADIS16460_DIAG_STAT_FLASH_MEM) | BIT 396 drivers/iio/imu/adis16460.c BIT(ADIS16460_DIAG_STAT_SELF_TEST) | BIT 397 drivers/iio/imu/adis16460.c BIT(ADIS16460_DIAG_STAT_OVERRANGE) | BIT 398 drivers/iio/imu/adis16460.c BIT(ADIS16460_DIAG_STAT_SPI_COMM) | BIT 399 drivers/iio/imu/adis16460.c BIT(ADIS16460_DIAG_STAT_FLASH_UPT), BIT 118 drivers/iio/imu/adis16480.c #define ADIS16480_DRDY_POL_MSK BIT(2) BIT 120 drivers/iio/imu/adis16480.c #define ADIS16480_DRDY_EN_MSK BIT(3) BIT 124 drivers/iio/imu/adis16480.c #define ADIS16480_SYNC_EN_MSK BIT(7) BIT 126 drivers/iio/imu/adis16480.c #define ADIS16480_SYNC_MODE_MSK BIT(8) BIT 540 drivers/iio/imu/adis16480.c enable_mask = BIT(offset + 2); BIT 566 drivers/iio/imu/adis16480.c enable_mask = BIT(offset + 2); BIT 679 drivers/iio/imu/adis16480.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 680 drivers/iio/imu/adis16480.c BIT(IIO_CHAN_INFO_CALIBBIAS) | \ BIT 682 drivers/iio/imu/adis16480.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 683 drivers/iio/imu/adis16480.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 697 drivers/iio/imu/adis16480.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ BIT 698 drivers/iio/imu/adis16480.c BIT(IIO_CHAN_INFO_CALIBSCALE), \ BIT 704 drivers/iio/imu/adis16480.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ BIT 705 drivers/iio/imu/adis16480.c BIT(IIO_CHAN_INFO_CALIBSCALE), \ BIT 711 drivers/iio/imu/adis16480.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ BIT 719 drivers/iio/imu/adis16480.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 720 drivers/iio/imu/adis16480.c BIT(IIO_CHAN_INFO_CALIBBIAS) | \ BIT 721 drivers/iio/imu/adis16480.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 722 drivers/iio/imu/adis16480.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 737 drivers/iio/imu/adis16480.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 738 drivers/iio/imu/adis16480.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 739 drivers/iio/imu/adis16480.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 740 drivers/iio/imu/adis16480.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 937 drivers/iio/imu/adis16480.c ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); BIT 970 drivers/iio/imu/adis16480.c ret = adis_write_reg_16(&st->adis, ADIS16480_REG_GLOB_CMD, BIT(1)); BIT 1027 drivers/iio/imu/adis16480.c .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | BIT 1028 drivers/iio/imu/adis16480.c BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | BIT 1029 drivers/iio/imu/adis16480.c BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | BIT 1030 drivers/iio/imu/adis16480.c BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | BIT 1031 drivers/iio/imu/adis16480.c BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | BIT 1032 drivers/iio/imu/adis16480.c BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | BIT 1033 drivers/iio/imu/adis16480.c BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | BIT 1034 drivers/iio/imu/adis16480.c BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | BIT 1035 drivers/iio/imu/adis16480.c BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | BIT 1036 drivers/iio/imu/adis16480.c BIT(ADIS16480_DIAG_STAT_BARO_FAIL), BIT 69 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_DRDY_INT_EN BIT(4) BIT 75 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_EDGE_TRIGGERED BIT(0) BIT 76 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_ACTIVE_HIGH BIT(1) BIT 77 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_OPEN_DRAIN BIT(2) BIT 78 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_OUTPUT_EN BIT(3) BIT 81 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_INT1_LATCH_MASK BIT(4) BIT 82 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_INT2_LATCH_MASK BIT(5) BIT 102 drivers/iio/imu/bmi160/bmi160_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 103 drivers/iio/imu/bmi160/bmi160_core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 104 drivers/iio/imu/bmi160/bmi160_core.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 822 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 823 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 824 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 844 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) BIT 845 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(IIO_CHAN_INFO_OFFSET) BIT 846 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(IIO_CHAN_INFO_SCALE), BIT 860 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c BIT(INV_MPU6050_SCAN_ACCL_X) BIT 861 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_MPU6050_SCAN_ACCL_Y) BIT 862 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_MPU6050_SCAN_ACCL_Z), BIT 864 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c BIT(INV_MPU6050_SCAN_GYRO_X) BIT 865 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_MPU6050_SCAN_GYRO_Y) BIT 866 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_MPU6050_SCAN_GYRO_Z), BIT 868 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c BIT(INV_MPU6050_SCAN_ACCL_X) BIT 869 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_MPU6050_SCAN_ACCL_Y) BIT 870 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_MPU6050_SCAN_ACCL_Z) BIT 871 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_MPU6050_SCAN_GYRO_X) BIT 872 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_MPU6050_SCAN_GYRO_Y) BIT 873 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_MPU6050_SCAN_GYRO_Z), BIT 881 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) BIT 882 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(IIO_CHAN_INFO_OFFSET) BIT 883 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(IIO_CHAN_INFO_SCALE), BIT 905 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c BIT(INV_ICM20602_SCAN_ACCL_X) BIT 906 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_ACCL_Y) BIT 907 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_ACCL_Z) BIT 908 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_TEMP), BIT 910 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c BIT(INV_ICM20602_SCAN_GYRO_X) BIT 911 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_GYRO_Y) BIT 912 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_GYRO_Z) BIT 913 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_TEMP), BIT 915 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c BIT(INV_ICM20602_SCAN_ACCL_X) BIT 916 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_ACCL_Y) BIT 917 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_ACCL_Z) BIT 918 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_GYRO_X) BIT 919 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_GYRO_Y) BIT 920 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_GYRO_Z) BIT 921 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | BIT(INV_ICM20602_SCAN_TEMP), BIT 70 drivers/iio/imu/kmx61.c #define KMX61_ACC_STBY_BIT BIT(0) BIT 71 drivers/iio/imu/kmx61.c #define KMX61_MAG_STBY_BIT BIT(1) BIT 72 drivers/iio/imu/kmx61.c #define KMX61_ACT_STBY_BIT BIT(7) BIT 76 drivers/iio/imu/kmx61.c #define KMX61_REG_INS1_BIT_WUFS BIT(1) BIT 78 drivers/iio/imu/kmx61.c #define KMX61_REG_INS2_BIT_ZP BIT(0) BIT 79 drivers/iio/imu/kmx61.c #define KMX61_REG_INS2_BIT_ZN BIT(1) BIT 80 drivers/iio/imu/kmx61.c #define KMX61_REG_INS2_BIT_YP BIT(2) BIT 81 drivers/iio/imu/kmx61.c #define KMX61_REG_INS2_BIT_YN BIT(3) BIT 82 drivers/iio/imu/kmx61.c #define KMX61_REG_INS2_BIT_XP BIT(4) BIT 83 drivers/iio/imu/kmx61.c #define KMX61_REG_INS2_BIT_XN BIT(5) BIT 87 drivers/iio/imu/kmx61.c #define KMX61_REG_CTRL1_BIT_RES BIT(4) BIT 88 drivers/iio/imu/kmx61.c #define KMX61_REG_CTRL1_BIT_DRDYE BIT(5) BIT 89 drivers/iio/imu/kmx61.c #define KMX61_REG_CTRL1_BIT_WUFE BIT(6) BIT 90 drivers/iio/imu/kmx61.c #define KMX61_REG_CTRL1_BIT_BTSE BIT(7) BIT 92 drivers/iio/imu/kmx61.c #define KMX61_REG_INC1_BIT_WUFS BIT(0) BIT 93 drivers/iio/imu/kmx61.c #define KMX61_REG_INC1_BIT_DRDYM BIT(1) BIT 94 drivers/iio/imu/kmx61.c #define KMX61_REG_INC1_BIT_DRDYA BIT(2) BIT 95 drivers/iio/imu/kmx61.c #define KMX61_REG_INC1_BIT_IEN BIT(5) BIT 224 drivers/iio/imu/kmx61.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 225 drivers/iio/imu/kmx61.c BIT(IIO_EV_INFO_ENABLE) | BIT 226 drivers/iio/imu/kmx61.c BIT(IIO_EV_INFO_PERIOD), BIT 233 drivers/iio/imu/kmx61.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 234 drivers/iio/imu/kmx61.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 235 drivers/iio/imu/kmx61.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 254 drivers/iio/imu/kmx61.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 255 drivers/iio/imu/kmx61.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 256 drivers/iio/imu/kmx61.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 63 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 64 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 65 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 46 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c #define ST_LSM6DSX_REG_HLACTIVE_MASK BIT(5) BIT 48 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c #define ST_LSM6DSX_REG_PP_OD_MASK BIT(4) BIT 52 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c #define ST_LSM6DSX_FIFO_EMPTY_MASK BIT(12) BIT 113 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c if (!(hw->enable_mask & BIT(sensor->id))) BIT 139 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c if (hw->enable_mask & BIT(sensor->id)) { BIT 249 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c if (!(hw->enable_mask & BIT(cur_sensor->id))) BIT 480 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c if (hw->enable_mask & BIT(ST_LSM6DSX_ID_EXT0)) BIT 482 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c else if (hw->enable_mask & BIT(ST_LSM6DSX_ID_EXT1)) BIT 488 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c if ((hw->enable_mask & BIT(ST_LSM6DSX_ID_EXT0)) && BIT 489 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c (hw->enable_mask & BIT(ST_LSM6DSX_ID_EXT1))) BIT 61 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c #define ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK BIT(3) BIT 63 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c #define ST_LSM6DSX_REG_RESET_MASK BIT(0) BIT 64 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c #define ST_LSM6DSX_REG_BOOT_MASK BIT(7) BIT 66 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c #define ST_LSM6DSX_REG_BDU_MASK BIT(6) BIT 261 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(7), BIT 265 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(4), BIT 269 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(7), BIT 375 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(7), BIT 379 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(4), BIT 383 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(7), BIT 498 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(5), BIT 502 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(4), BIT 506 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(7), BIT 615 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(5), BIT 625 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(6), BIT 629 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(2), BIT 633 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(3), BIT 641 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(6), BIT 646 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .batch_en = BIT(3), BIT 747 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(5), BIT 856 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(5), BIT 866 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(6), BIT 870 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(2), BIT 874 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(3), BIT 882 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(6), BIT 887 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .batch_en = BIT(3), BIT 999 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c if (hw->enable_mask & BIT(id)) BIT 1004 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c return (hw->enable_mask & BIT(id)) ? ref->odr : 0; BIT 1070 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c hw->enable_mask |= BIT(sensor->id); BIT 1072 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c hw->enable_mask &= ~BIT(sensor->id); BIT 1559 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c if (!(hw->enable_mask & BIT(sensor->id))) BIT 1571 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c hw->suspend_mask |= BIT(sensor->id); BIT 1591 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c if (!(hw->suspend_mask & BIT(sensor->id))) BIT 1603 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c hw->suspend_mask &= ~BIT(sensor->id); BIT 68 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .mask = BIT(7), BIT 80 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .mask = BIT(1), BIT 84 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .mask = BIT(4), BIT 99 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c odr = (hw->enable_mask & BIT(ST_LSM6DSX_ID_ACC)) ? sensor->odr : 13; BIT 369 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c enable_mask = hw->enable_mask | BIT(sensor->id); BIT 371 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c enable_mask = hw->enable_mask & ~BIT(sensor->id); BIT 378 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c if (!(enable_mask & BIT(cur_sensor->id))) BIT 45 drivers/iio/light/acpi-als.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 46 drivers/iio/light/acpi-als.c BIT(IIO_CHAN_INFO_PROCESSED), BIT 147 drivers/iio/light/adjd_s311.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 148 drivers/iio/light/adjd_s311.c BIT(IIO_CHAN_INFO_HARDWAREGAIN) | \ BIT 149 drivers/iio/light/adjd_s311.c BIT(IIO_CHAN_INFO_INT_TIME), \ BIT 40 drivers/iio/light/al3320a.c #define AL3320A_GAIN_MASK (BIT(2) | BIT(1)) BIT 66 drivers/iio/light/al3320a.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 67 drivers/iio/light/al3320a.c BIT(IIO_CHAN_INFO_SCALE), BIT 23 drivers/iio/light/apds9300.c #define APDS9300_CMD BIT(7) /* Select command register. Must write as 1 */ BIT 24 drivers/iio/light/apds9300.c #define APDS9300_WORD BIT(5) /* I2C write/read: if 1 word, if 0 byte */ BIT 25 drivers/iio/light/apds9300.c #define APDS9300_CLEAR BIT(6) /* Interrupt clear. Clears pending interrupt */ BIT 352 drivers/iio/light/apds9300.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 353 drivers/iio/light/apds9300.c BIT(IIO_EV_INFO_ENABLE), BIT 357 drivers/iio/light/apds9300.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 358 drivers/iio/light/apds9300.c BIT(IIO_EV_INFO_ENABLE), BIT 367 drivers/iio/light/apds9300.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 373 drivers/iio/light/apds9300.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 381 drivers/iio/light/apds9300.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 64 drivers/iio/light/apds9960.c #define APDS9960_REG_STATUS_PS_INT BIT(5) BIT 65 drivers/iio/light/apds9960.c #define APDS9960_REG_STATUS_ALS_INT BIT(4) BIT 66 drivers/iio/light/apds9960.c #define APDS9960_REG_STATUS_GINT BIT(2) BIT 227 drivers/iio/light/apds9960.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 228 drivers/iio/light/apds9960.c BIT(IIO_EV_INFO_ENABLE), BIT 233 drivers/iio/light/apds9960.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 234 drivers/iio/light/apds9960.c BIT(IIO_EV_INFO_ENABLE), BIT 242 drivers/iio/light/apds9960.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 243 drivers/iio/light/apds9960.c BIT(IIO_EV_INFO_ENABLE), BIT 248 drivers/iio/light/apds9960.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 249 drivers/iio/light/apds9960.c BIT(IIO_EV_INFO_ENABLE), BIT 267 drivers/iio/light/apds9960.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 268 drivers/iio/light/apds9960.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 269 drivers/iio/light/apds9960.c BIT(IIO_CHAN_INFO_INT_TIME), \ BIT 282 drivers/iio/light/apds9960.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 283 drivers/iio/light/apds9960.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 299 drivers/iio/light/apds9960.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 300 drivers/iio/light/apds9960.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | BIT 301 drivers/iio/light/apds9960.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 970 drivers/iio/light/apds9960.c BIT(0) << APDS9960_REG_GCONF_1_GFIFO_THRES_MASK_SHIFT); BIT 225 drivers/iio/light/bh1750.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 226 drivers/iio/light/bh1750.c BIT(IIO_CHAN_INFO_SCALE) | BIT 227 drivers/iio/light/bh1750.c BIT(IIO_CHAN_INFO_INT_TIME) BIT 22 drivers/iio/light/bh1780.c #define BH1780_CMD_BIT BIT(7) BIT 139 drivers/iio/light/bh1780.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 140 drivers/iio/light/bh1780.c BIT(IIO_CHAN_INFO_INT_TIME) BIT 273 drivers/iio/light/cm32181.c BIT(IIO_CHAN_INFO_PROCESSED) | BIT 274 drivers/iio/light/cm32181.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 275 drivers/iio/light/cm32181.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 22 drivers/iio/light/cm3232.c #define CM3232_CMD_ALS_DISABLE BIT(0) BIT 25 drivers/iio/light/cm3232.c #define CM3232_CMD_ALS_IT_MASK (BIT(2) | BIT(3) | BIT(4)) BIT 28 drivers/iio/light/cm3232.c #define CM3232_CMD_ALS_RESET BIT(6) BIT 303 drivers/iio/light/cm3232.c BIT(IIO_CHAN_INFO_PROCESSED) | BIT 304 drivers/iio/light/cm3232.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 305 drivers/iio/light/cm3232.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 27 drivers/iio/light/cm3323.c #define CM3323_CONF_SD_BIT BIT(0) /* sensor disable */ BIT 28 drivers/iio/light/cm3323.c #define CM3323_CONF_AF_BIT BIT(1) /* auto/manual force mode */ BIT 55 drivers/iio/light/cm3323.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 56 drivers/iio/light/cm3323.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME), \ BIT 137 drivers/iio/light/cm3605.c .mask_separate = BIT(IIO_EV_INFO_ENABLE), BIT 149 drivers/iio/light/cm3605.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 566 drivers/iio/light/cm36651.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 567 drivers/iio/light/cm36651.c BIT(IIO_CHAN_INFO_INT_TIME), \ BIT 577 drivers/iio/light/cm36651.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 578 drivers/iio/light/cm36651.c BIT(IIO_EV_INFO_ENABLE), BIT 585 drivers/iio/light/cm36651.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 586 drivers/iio/light/cm36651.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 199 drivers/iio/light/cros_ec_light_prox.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 200 drivers/iio/light/cros_ec_light_prox.c BIT(IIO_CHAN_INFO_FREQUENCY); BIT 202 drivers/iio/light/cros_ec_light_prox.c BIT(IIO_CHAN_INFO_SAMP_FREQ); BIT 215 drivers/iio/light/cros_ec_light_prox.c BIT(IIO_CHAN_INFO_PROCESSED) | BIT 216 drivers/iio/light/cros_ec_light_prox.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 217 drivers/iio/light/cros_ec_light_prox.c BIT(IIO_CHAN_INFO_CALIBSCALE); BIT 222 drivers/iio/light/cros_ec_light_prox.c BIT(IIO_CHAN_INFO_RAW) | BIT 223 drivers/iio/light/cros_ec_light_prox.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 224 drivers/iio/light/cros_ec_light_prox.c BIT(IIO_CHAN_INFO_CALIBSCALE); BIT 1302 drivers/iio/light/gp2ap020a00f.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 1303 drivers/iio/light/gp2ap020a00f.c BIT(IIO_EV_INFO_ENABLE), BIT 1307 drivers/iio/light/gp2ap020a00f.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 1308 drivers/iio/light/gp2ap020a00f.c BIT(IIO_EV_INFO_ENABLE), BIT 1316 drivers/iio/light/gp2ap020a00f.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 1317 drivers/iio/light/gp2ap020a00f.c BIT(IIO_EV_INFO_ENABLE), BIT 1321 drivers/iio/light/gp2ap020a00f.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 1322 drivers/iio/light/gp2ap020a00f.c BIT(IIO_EV_INFO_ENABLE), BIT 1331 drivers/iio/light/gp2ap020a00f.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 1348 drivers/iio/light/gp2ap020a00f.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 1362 drivers/iio/light/gp2ap020a00f.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 44 drivers/iio/light/hid-sensor-als.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 45 drivers/iio/light/hid-sensor-als.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 46 drivers/iio/light/hid-sensor-als.c BIT(IIO_CHAN_INFO_SCALE) | BIT 47 drivers/iio/light/hid-sensor-als.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 48 drivers/iio/light/hid-sensor-als.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 53 drivers/iio/light/hid-sensor-als.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 54 drivers/iio/light/hid-sensor-als.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 55 drivers/iio/light/hid-sensor-als.c BIT(IIO_CHAN_INFO_SCALE) | BIT 56 drivers/iio/light/hid-sensor-als.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 57 drivers/iio/light/hid-sensor-als.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 34 drivers/iio/light/hid-sensor-prox.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 35 drivers/iio/light/hid-sensor-prox.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 36 drivers/iio/light/hid-sensor-prox.c BIT(IIO_CHAN_INFO_SCALE) | BIT 37 drivers/iio/light/hid-sensor-prox.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 38 drivers/iio/light/hid-sensor-prox.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 469 drivers/iio/light/isl29018.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | \ BIT 470 drivers/iio/light/isl29018.c BIT(IIO_CHAN_INFO_CALIBSCALE) | \ BIT 471 drivers/iio/light/isl29018.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 472 drivers/iio/light/isl29018.c BIT(IIO_CHAN_INFO_INT_TIME), \ BIT 478 drivers/iio/light/isl29018.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 484 drivers/iio/light/isl29018.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 30 drivers/iio/light/isl29028.c #define ISL29028_CONF_ALS_IR_MODE_IR BIT(0) BIT 31 drivers/iio/light/isl29028.c #define ISL29028_CONF_ALS_IR_MODE_MASK BIT(0) BIT 34 drivers/iio/light/isl29028.c #define ISL29028_CONF_ALS_RANGE_HIGH_LUX BIT(1) BIT 35 drivers/iio/light/isl29028.c #define ISL29028_CONF_ALS_RANGE_MASK BIT(1) BIT 38 drivers/iio/light/isl29028.c #define ISL29028_CONF_ALS_EN BIT(2) BIT 39 drivers/iio/light/isl29028.c #define ISL29028_CONF_ALS_EN_MASK BIT(2) BIT 44 drivers/iio/light/isl29028.c #define ISL29028_CONF_PROX_EN BIT(7) BIT 45 drivers/iio/light/isl29028.c #define ISL29028_CONF_PROX_EN_MASK BIT(7) BIT 514 drivers/iio/light/isl29028.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 515 drivers/iio/light/isl29028.c BIT(IIO_CHAN_INFO_SCALE), BIT 518 drivers/iio/light/isl29028.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 521 drivers/iio/light/isl29028.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 522 drivers/iio/light/isl29028.c BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 47 drivers/iio/light/isl29125.c #define ISL29125_MODE_RANGE BIT(3) BIT 49 drivers/iio/light/isl29125.c #define ISL29125_STATUS_CONV BIT(1) BIT 60 drivers/iio/light/isl29125.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 61 drivers/iio/light/isl29125.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 240 drivers/iio/light/jsa1212.c *val2 = BIT(12); /* Max 12 bit value */ BIT 256 drivers/iio/light/jsa1212.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 257 drivers/iio/light/jsa1212.c BIT(IIO_CHAN_INFO_SCALE), BIT 261 drivers/iio/light/jsa1212.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 230 drivers/iio/light/lm3533-als.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 238 drivers/iio/light/lm3533-als.c .info_mask_separate = BIT(IIO_CHAN_INFO_AVERAGE_RAW) | BIT 239 drivers/iio/light/lm3533-als.c BIT(IIO_CHAN_INFO_RAW), BIT 46 drivers/iio/light/ltr501.c #define LTR501_ALS_CONTR_SW_RESET BIT(2) BIT 47 drivers/iio/light/ltr501.c #define LTR501_CONTR_PS_GAIN_MASK (BIT(3) | BIT(2)) BIT 49 drivers/iio/light/ltr501.c #define LTR501_CONTR_ALS_GAIN_MASK BIT(3) BIT 50 drivers/iio/light/ltr501.c #define LTR501_CONTR_ACTIVE BIT(1) BIT 52 drivers/iio/light/ltr501.c #define LTR501_STATUS_ALS_INTR BIT(3) BIT 53 drivers/iio/light/ltr501.c #define LTR501_STATUS_ALS_RDY BIT(2) BIT 54 drivers/iio/light/ltr501.c #define LTR501_STATUS_PS_INTR BIT(1) BIT 55 drivers/iio/light/ltr501.c #define LTR501_STATUS_PS_RDY BIT(0) BIT 524 drivers/iio/light/ltr501.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 528 drivers/iio/light/ltr501.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 532 drivers/iio/light/ltr501.c .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT 533 drivers/iio/light/ltr501.c BIT(IIO_EV_INFO_PERIOD), BIT 542 drivers/iio/light/ltr501.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 546 drivers/iio/light/ltr501.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 550 drivers/iio/light/ltr501.c .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT 551 drivers/iio/light/ltr501.c BIT(IIO_EV_INFO_PERIOD), BIT 561 drivers/iio/light/ltr501.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 576 drivers/iio/light/ltr501.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ BIT 586 drivers/iio/light/ltr501.c BIT(IIO_CHAN_INFO_SCALE) | BIT 587 drivers/iio/light/ltr501.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 588 drivers/iio/light/ltr501.c BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 593 drivers/iio/light/ltr501.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 594 drivers/iio/light/ltr501.c BIT(IIO_CHAN_INFO_SCALE), BIT 614 drivers/iio/light/ltr501.c BIT(IIO_CHAN_INFO_SCALE) | BIT 615 drivers/iio/light/ltr501.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 616 drivers/iio/light/ltr501.c BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 1193 drivers/iio/light/ltr501.c .als_mode_active = BIT(0) | BIT(1), BIT 1194 drivers/iio/light/ltr501.c .als_gain_mask = BIT(3), BIT 1207 drivers/iio/light/ltr501.c .als_mode_active = BIT(1), BIT 1208 drivers/iio/light/ltr501.c .als_gain_mask = BIT(2) | BIT(3) | BIT(4), BIT 1219 drivers/iio/light/ltr501.c .als_mode_active = BIT(0) | BIT(1), BIT 1220 drivers/iio/light/ltr501.c .als_gain_mask = BIT(3), BIT 470 drivers/iio/light/lv0104cs.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 471 drivers/iio/light/lv0104cs.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 472 drivers/iio/light/lv0104cs.c BIT(IIO_CHAN_INFO_SCALE) | BIT 473 drivers/iio/light/lv0104cs.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 133 drivers/iio/light/max44000.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 134 drivers/iio/light/max44000.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | BIT 135 drivers/iio/light/max44000.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 145 drivers/iio/light/max44000.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 156 drivers/iio/light/max44000.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 157 drivers/iio/light/max44000.c BIT(IIO_CHAN_INFO_SCALE), BIT 39 drivers/iio/light/max44009.c #define MAX44009_CFG_MAN_MODE_MASK BIT(6) BIT 88 drivers/iio/light/max44009.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 89 drivers/iio/light/max44009.c BIT(IIO_EV_INFO_ENABLE), BIT 94 drivers/iio/light/max44009.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 95 drivers/iio/light/max44009.c BIT(IIO_EV_INFO_ENABLE), BIT 102 drivers/iio/light/max44009.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 103 drivers/iio/light/max44009.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 123 drivers/iio/light/noa1305.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 124 drivers/iio/light/noa1305.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 37 drivers/iio/light/opt3001.c #define OPT3001_CONFIGURATION_CT BIT(11) BIT 44 drivers/iio/light/opt3001.c #define OPT3001_CONFIGURATION_OVF BIT(8) BIT 45 drivers/iio/light/opt3001.c #define OPT3001_CONFIGURATION_CRF BIT(7) BIT 46 drivers/iio/light/opt3001.c #define OPT3001_CONFIGURATION_FH BIT(6) BIT 47 drivers/iio/light/opt3001.c #define OPT3001_CONFIGURATION_FL BIT(5) BIT 48 drivers/iio/light/opt3001.c #define OPT3001_CONFIGURATION_L BIT(4) BIT 49 drivers/iio/light/opt3001.c #define OPT3001_CONFIGURATION_POL BIT(3) BIT 50 drivers/iio/light/opt3001.c #define OPT3001_CONFIGURATION_ME BIT(2) BIT 201 drivers/iio/light/opt3001.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 202 drivers/iio/light/opt3001.c BIT(IIO_EV_INFO_ENABLE), BIT 207 drivers/iio/light/opt3001.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 208 drivers/iio/light/opt3001.c BIT(IIO_EV_INFO_ENABLE), BIT 215 drivers/iio/light/opt3001.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 216 drivers/iio/light/opt3001.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 35 drivers/iio/light/pa12203001.c #define PA12203001_ALS_EN_MASK BIT(0) BIT 36 drivers/iio/light/pa12203001.c #define PA12203001_PX_EN_MASK BIT(1) BIT 102 drivers/iio/light/pa12203001.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 103 drivers/iio/light/pa12203001.c BIT(IIO_CHAN_INFO_SCALE), BIT 107 drivers/iio/light/pa12203001.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 38 drivers/iio/light/rpr0521.c #define RPR0521_MODE_ALS_MASK BIT(7) BIT 39 drivers/iio/light/rpr0521.c #define RPR0521_MODE_PXS_MASK BIT(6) BIT 48 drivers/iio/light/rpr0521.c #define RPR0521_INTERRUPT_INT_TRIG_PS_MASK BIT(0) BIT 49 drivers/iio/light/rpr0521.c #define RPR0521_INTERRUPT_INT_TRIG_ALS_MASK BIT(1) BIT 50 drivers/iio/light/rpr0521.c #define RPR0521_INTERRUPT_INT_REASSERT_MASK BIT(3) BIT 51 drivers/iio/light/rpr0521.c #define RPR0521_INTERRUPT_ALS_INT_STATUS_MASK BIT(6) BIT 52 drivers/iio/light/rpr0521.c #define RPR0521_INTERRUPT_PS_INT_STATUS_MASK BIT(7) BIT 54 drivers/iio/light/rpr0521.c #define RPR0521_MODE_ALS_ENABLE BIT(7) BIT 56 drivers/iio/light/rpr0521.c #define RPR0521_MODE_PXS_ENABLE BIT(6) BIT 60 drivers/iio/light/rpr0521.c #define RPR0521_INTERRUPT_INT_TRIG_PS_ENABLE BIT(0) BIT 62 drivers/iio/light/rpr0521.c #define RPR0521_INTERRUPT_INT_TRIG_ALS_ENABLE BIT(1) BIT 64 drivers/iio/light/rpr0521.c #define RPR0521_INTERRUPT_INT_REASSERT_ENABLE BIT(3) BIT 227 drivers/iio/light/rpr0521.c BIT(RPR0521_CHAN_INDEX_PXS) | BIT(RPR0521_CHAN_INDEX_BOTH) | BIT 228 drivers/iio/light/rpr0521.c BIT(RPR0521_CHAN_INDEX_IR), BIT 236 drivers/iio/light/rpr0521.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 237 drivers/iio/light/rpr0521.c BIT(IIO_CHAN_INFO_OFFSET) | BIT 238 drivers/iio/light/rpr0521.c BIT(IIO_CHAN_INFO_SCALE), BIT 239 drivers/iio/light/rpr0521.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 253 drivers/iio/light/rpr0521.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 254 drivers/iio/light/rpr0521.c BIT(IIO_CHAN_INFO_SCALE), BIT 255 drivers/iio/light/rpr0521.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 269 drivers/iio/light/rpr0521.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 270 drivers/iio/light/rpr0521.c BIT(IIO_CHAN_INFO_SCALE), BIT 271 drivers/iio/light/rpr0521.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 46 drivers/iio/light/si1133.c #define SI1133_CMD_ERR_MASK BIT(4) BIT 61 drivers/iio/light/si1133.c #define SI1133_ADCSENS_HSIG_MASK BIT(7) BIT 66 drivers/iio/light/si1133.c #define SI1133_ADCPOST_24BIT_EN BIT(6) BIT 471 drivers/iio/light/si1133.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 472 drivers/iio/light/si1133.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) | \ BIT 473 drivers/iio/light/si1133.c BIT(IIO_CHAN_INFO_SCALE) | \ BIT 474 drivers/iio/light/si1133.c BIT(IIO_CHAN_INFO_HARDWAREGAIN), \ BIT 479 drivers/iio/light/si1133.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 627 drivers/iio/light/si1133.c err = si1133_set_chlist(data, BIT(0)); BIT 804 drivers/iio/light/si1133.c *val = BIT(adc_sens); BIT 93 drivers/iio/light/si1145.c #define SI1145_CHLIST_EN_PS1 BIT(0) BIT 94 drivers/iio/light/si1145.c #define SI1145_CHLIST_EN_PS2 BIT(1) BIT 95 drivers/iio/light/si1145.c #define SI1145_CHLIST_EN_PS3 BIT(2) BIT 96 drivers/iio/light/si1145.c #define SI1145_CHLIST_EN_ALSVIS BIT(4) BIT 97 drivers/iio/light/si1145.c #define SI1145_CHLIST_EN_ALSIR BIT(5) BIT 98 drivers/iio/light/si1145.c #define SI1145_CHLIST_EN_AUX BIT(6) BIT 99 drivers/iio/light/si1145.c #define SI1145_CHLIST_EN_UV BIT(7) BIT 102 drivers/iio/light/si1145.c #define SI1145_PS_ADC_MODE_NORMAL BIT(2) BIT 104 drivers/iio/light/si1145.c #define SI1145_ADC_MISC_RANGE BIT(5) BIT 130 drivers/iio/light/si1145.c #define SI1145_INT_CFG_OE BIT(0) /* enable interrupt */ BIT 131 drivers/iio/light/si1145.c #define SI1145_INT_CFG_MODE BIT(1) /* auto reset interrupt pin */ BIT 134 drivers/iio/light/si1145.c #define SI1145_MASK_ALL_IE (BIT(4) | BIT(3) | BIT(2) | BIT(0)) BIT 567 drivers/iio/light/si1145.c ret = si1145_set_chlist(indio_dev, BIT(chan->scan_index)); BIT 806 drivers/iio/light/si1145.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 807 drivers/iio/light/si1145.c BIT(IIO_CHAN_INFO_OFFSET) | \ BIT 808 drivers/iio/light/si1145.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 809 drivers/iio/light/si1145.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 817 drivers/iio/light/si1145.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 818 drivers/iio/light/si1145.c BIT(IIO_CHAN_INFO_OFFSET) | \ BIT 819 drivers/iio/light/si1145.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 820 drivers/iio/light/si1145.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 830 drivers/iio/light/si1145.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 831 drivers/iio/light/si1145.c BIT(IIO_CHAN_INFO_OFFSET) | \ BIT 832 drivers/iio/light/si1145.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 833 drivers/iio/light/si1145.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 841 drivers/iio/light/si1145.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 842 drivers/iio/light/si1145.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 843 drivers/iio/light/si1145.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 853 drivers/iio/light/si1145.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 854 drivers/iio/light/si1145.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 855 drivers/iio/light/si1145.c BIT(IIO_CHAN_INFO_OFFSET), \ BIT 856 drivers/iio/light/si1145.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 864 drivers/iio/light/si1145.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 865 drivers/iio/light/si1145.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 877 drivers/iio/light/si1145.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 29 drivers/iio/light/st_uvis25_core.c #define ST_UVIS25_REG_ODR_MASK BIT(0) BIT 30 drivers/iio/light/st_uvis25_core.c #define ST_UVIS25_REG_BDU_MASK BIT(1) BIT 32 drivers/iio/light/st_uvis25_core.c #define ST_UVIS25_REG_BOOT_MASK BIT(7) BIT 34 drivers/iio/light/st_uvis25_core.c #define ST_UVIS25_REG_HL_MASK BIT(7) BIT 36 drivers/iio/light/st_uvis25_core.c #define ST_UVIS25_REG_UV_DA_MASK BIT(0) BIT 43 drivers/iio/light/st_uvis25_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 19 drivers/iio/light/st_uvis25_i2c.c #define UVIS25_I2C_AUTO_INCREMENT BIT(7) BIT 18 drivers/iio/light/st_uvis25_spi.c #define UVIS25_SENSORS_SPI_READ BIT(7) BIT 19 drivers/iio/light/st_uvis25_spi.c #define UVIS25_SPI_AUTO_INCREMENT BIT(6) BIT 34 drivers/iio/light/stk3310.c #define STK3310_STATE_EN_PS BIT(0) BIT 35 drivers/iio/light/stk3310.c #define STK3310_STATE_EN_ALS BIT(1) BIT 125 drivers/iio/light/stk3310.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 126 drivers/iio/light/stk3310.c BIT(IIO_EV_INFO_ENABLE), BIT 132 drivers/iio/light/stk3310.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 133 drivers/iio/light/stk3310.c BIT(IIO_EV_INFO_ENABLE), BIT 141 drivers/iio/light/stk3310.c BIT(IIO_CHAN_INFO_RAW) | BIT 142 drivers/iio/light/stk3310.c BIT(IIO_CHAN_INFO_SCALE) | BIT 143 drivers/iio/light/stk3310.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 148 drivers/iio/light/stk3310.c BIT(IIO_CHAN_INFO_RAW) | BIT 149 drivers/iio/light/stk3310.c BIT(IIO_CHAN_INFO_SCALE) | BIT 150 drivers/iio/light/stk3310.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 27 drivers/iio/light/tcs3414.c #define TCS3414_COMMAND BIT(7) BIT 28 drivers/iio/light/tcs3414.c #define TCS3414_COMMAND_WORD (TCS3414_COMMAND | BIT(5)) BIT 39 drivers/iio/light/tcs3414.c #define TCS3414_CONTROL_ADC_VALID BIT(4) BIT 40 drivers/iio/light/tcs3414.c #define TCS3414_CONTROL_ADC_EN BIT(1) BIT 41 drivers/iio/light/tcs3414.c #define TCS3414_CONTROL_POWER BIT(0) BIT 62 drivers/iio/light/tcs3414.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 63 drivers/iio/light/tcs3414.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 64 drivers/iio/light/tcs3414.c BIT(IIO_CHAN_INFO_INT_TIME), \ BIT 30 drivers/iio/light/tcs3472.c #define TCS3472_COMMAND BIT(7) BIT 31 drivers/iio/light/tcs3472.c #define TCS3472_AUTO_INCR BIT(5) BIT 32 drivers/iio/light/tcs3472.c #define TCS3472_SPECIAL_FUNC (BIT(5) | BIT(6)) BIT 51 drivers/iio/light/tcs3472.c #define TCS3472_STATUS_AINT BIT(4) BIT 52 drivers/iio/light/tcs3472.c #define TCS3472_STATUS_AVALID BIT(0) BIT 53 drivers/iio/light/tcs3472.c #define TCS3472_ENABLE_AIEN BIT(4) BIT 54 drivers/iio/light/tcs3472.c #define TCS3472_ENABLE_AEN BIT(1) BIT 55 drivers/iio/light/tcs3472.c #define TCS3472_ENABLE_PON BIT(0) BIT 56 drivers/iio/light/tcs3472.c #define TCS3472_CONTROL_AGAIN_MASK (BIT(0) | BIT(1)) BIT 74 drivers/iio/light/tcs3472.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 78 drivers/iio/light/tcs3472.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 82 drivers/iio/light/tcs3472.c .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT 83 drivers/iio/light/tcs3472.c BIT(IIO_EV_INFO_PERIOD), BIT 90 drivers/iio/light/tcs3472.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 91 drivers/iio/light/tcs3472.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBSCALE) | \ BIT 92 drivers/iio/light/tcs3472.c BIT(IIO_CHAN_INFO_INT_TIME), \ BIT 524 drivers/iio/light/tsl2563.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 525 drivers/iio/light/tsl2563.c BIT(IIO_EV_INFO_ENABLE), BIT 529 drivers/iio/light/tsl2563.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 530 drivers/iio/light/tsl2563.c BIT(IIO_EV_INFO_ENABLE), BIT 538 drivers/iio/light/tsl2563.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 544 drivers/iio/light/tsl2563.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 545 drivers/iio/light/tsl2563.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 552 drivers/iio/light/tsl2563.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 553 drivers/iio/light/tsl2563.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 617 drivers/iio/light/tsl2583.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 623 drivers/iio/light/tsl2583.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 627 drivers/iio/light/tsl2583.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 628 drivers/iio/light/tsl2583.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 629 drivers/iio/light/tsl2583.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 630 drivers/iio/light/tsl2583.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 1502 drivers/iio/light/tsl2772.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 1506 drivers/iio/light/tsl2772.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 1510 drivers/iio/light/tsl2772.c .mask_separate = BIT(IIO_EV_INFO_PERIOD) | BIT 1511 drivers/iio/light/tsl2772.c BIT(IIO_EV_INFO_ENABLE), BIT 1522 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 1527 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1528 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1529 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 1530 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBBIAS), BIT 1532 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1533 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1547 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 1552 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1553 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1554 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 1555 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBBIAS), BIT 1557 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1558 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1574 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 1584 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 1596 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 1601 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1602 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1603 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 1604 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBBIAS), BIT 1606 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1607 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1614 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 1619 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 1629 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 1634 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1635 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1636 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 1637 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBBIAS), BIT 1639 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1640 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1645 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 1650 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 1662 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1663 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1665 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1675 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1676 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1678 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1690 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 1695 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1696 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1697 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 1698 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBBIAS), BIT 1700 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1701 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1708 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 1713 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1714 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1716 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1726 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 1731 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1732 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1733 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT 1734 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBBIAS), BIT 1736 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 1737 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1742 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 1747 drivers/iio/light/tsl2772.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1748 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 1750 drivers/iio/light/tsl2772.c BIT(IIO_CHAN_INFO_CALIBSCALE), BIT 24 drivers/iio/light/tsl4531.c #define TSL4531_COMMAND BIT(7) BIT 68 drivers/iio/light/tsl4531.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 69 drivers/iio/light/tsl4531.c BIT(IIO_CHAN_INFO_SCALE) | BIT 70 drivers/iio/light/tsl4531.c BIT(IIO_CHAN_INFO_INT_TIME) BIT 25 drivers/iio/light/us5182d.c #define US5182D_CFG0_ONESHOT_EN BIT(6) BIT 26 drivers/iio/light/us5182d.c #define US5182D_CFG0_SHUTDOWN_EN BIT(7) BIT 27 drivers/iio/light/us5182d.c #define US5182D_CFG0_WORD_ENABLE BIT(0) BIT 28 drivers/iio/light/us5182d.c #define US5182D_CFG0_PROX BIT(3) BIT 29 drivers/iio/light/us5182d.c #define US5182D_CFG0_PX_IRQ BIT(2) BIT 32 drivers/iio/light/us5182d.c #define US5182D_CFG1_ALS_RES16 BIT(4) BIT 36 drivers/iio/light/us5182d.c #define US5182D_CFG2_PX_RES16 BIT(4) BIT 37 drivers/iio/light/us5182d.c #define US5182D_CFG2_PXGAIN_DEFAULT BIT(2) BIT 40 drivers/iio/light/us5182d.c #define US5182D_CFG3_LED_CURRENT100 (BIT(4) | BIT(5)) BIT 41 drivers/iio/light/us5182d.c #define US5182D_CFG3_INT_SOURCE_PX BIT(3) BIT 173 drivers/iio/light/us5182d.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 174 drivers/iio/light/us5182d.c BIT(IIO_EV_INFO_ENABLE), BIT 179 drivers/iio/light/us5182d.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 180 drivers/iio/light/us5182d.c BIT(IIO_EV_INFO_ENABLE), BIT 187 drivers/iio/light/us5182d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 188 drivers/iio/light/us5182d.c BIT(IIO_CHAN_INFO_SCALE), BIT 192 drivers/iio/light/us5182d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 55 drivers/iio/light/vcnl4000.c #define VCNL4000_AL_RDY BIT(6) /* ALS data ready? */ BIT 56 drivers/iio/light/vcnl4000.c #define VCNL4000_PS_RDY BIT(5) /* proximity data ready? */ BIT 57 drivers/iio/light/vcnl4000.c #define VCNL4000_AL_OD BIT(4) /* start on-demand ALS measurement */ BIT 58 drivers/iio/light/vcnl4000.c #define VCNL4000_PS_OD BIT(3) /* start on-demand proximity measurement */ BIT 317 drivers/iio/light/vcnl4000.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 318 drivers/iio/light/vcnl4000.c BIT(IIO_CHAN_INFO_SCALE), BIT 321 drivers/iio/light/vcnl4000.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 38 drivers/iio/light/vcnl4035.c #define VCNL4035_MODE_ALS_MASK BIT(0) BIT 39 drivers/iio/light/vcnl4035.c #define VCNL4035_MODE_ALS_WHITE_CHAN BIT(8) BIT 40 drivers/iio/light/vcnl4035.c #define VCNL4035_MODE_ALS_INT_MASK BIT(1) BIT 43 drivers/iio/light/vcnl4035.c #define VCNL4035_INT_ALS_IF_H_MASK BIT(12) BIT 44 drivers/iio/light/vcnl4035.c #define VCNL4035_INT_ALS_IF_L_MASK BIT(13) BIT 47 drivers/iio/light/vcnl4035.c #define VCNL4035_MODE_ALS_ENABLE BIT(0) BIT 49 drivers/iio/light/vcnl4035.c #define VCNL4035_MODE_ALS_INT_ENABLE BIT(1) BIT 345 drivers/iio/light/vcnl4035.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 349 drivers/iio/light/vcnl4035.c .mask_separate = BIT(IIO_EV_INFO_VALUE), BIT 353 drivers/iio/light/vcnl4035.c .mask_separate = BIT(IIO_EV_INFO_PERIOD), BIT 370 drivers/iio/light/vcnl4035.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 371 drivers/iio/light/vcnl4035.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 372 drivers/iio/light/vcnl4035.c BIT(IIO_CHAN_INFO_SCALE), BIT 388 drivers/iio/light/vcnl4035.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 26 drivers/iio/light/veml6070.c #define VEML6070_COMMAND_ACK BIT(5) /* raise interrupt when over threshold */ BIT 28 drivers/iio/light/veml6070.c #define VEML6070_COMMAND_RSRVD BIT(1) /* reserved, set to 1 */ BIT 29 drivers/iio/light/veml6070.c #define VEML6070_COMMAND_SD BIT(0) /* shutdown mode when set */ BIT 82 drivers/iio/light/veml6070.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 86 drivers/iio/light/veml6070.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 56 drivers/iio/light/vl6180.c #define VL6180_MODE_CONT BIT(1) /* continuous mode */ BIT 57 drivers/iio/light/vl6180.c #define VL6180_STARTSTOP BIT(0) /* start measurement, auto-reset */ BIT 60 drivers/iio/light/vl6180.c #define VL6180_ALS_READY BIT(5) BIT 61 drivers/iio/light/vl6180.c #define VL6180_RANGE_READY BIT(2) BIT 64 drivers/iio/light/vl6180.c #define VL6180_CLEAR_ERROR BIT(2) BIT 65 drivers/iio/light/vl6180.c #define VL6180_CLEAR_ALS BIT(1) BIT 66 drivers/iio/light/vl6180.c #define VL6180_CLEAR_RANGE BIT(0) BIT 69 drivers/iio/light/vl6180.c #define VL6180_HOLD_ON BIT(0) BIT 261 drivers/iio/light/vl6180.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 262 drivers/iio/light/vl6180.c BIT(IIO_CHAN_INFO_INT_TIME) | BIT 263 drivers/iio/light/vl6180.c BIT(IIO_CHAN_INFO_SCALE) | BIT 264 drivers/iio/light/vl6180.c BIT(IIO_CHAN_INFO_HARDWAREGAIN), BIT 268 drivers/iio/light/vl6180.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 269 drivers/iio/light/vl6180.c BIT(IIO_CHAN_INFO_SCALE), BIT 273 drivers/iio/light/vl6180.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 37 drivers/iio/light/zopt2201.c #define ZOPT2201_MAIN_CTRL_LS_MODE BIT(3) /* 0 .. ALS, 1 .. UV B */ BIT 38 drivers/iio/light/zopt2201.c #define ZOPT2201_MAIN_CTRL_LS_EN BIT(1) BIT 66 drivers/iio/light/zopt2201.c #define ZOPT2201_MAIN_STATUS_POWERON BIT(5) BIT 67 drivers/iio/light/zopt2201.c #define ZOPT2201_MAIN_STATUS_INT BIT(4) BIT 68 drivers/iio/light/zopt2201.c #define ZOPT2201_MAIN_STATUS_DRDY BIT(3) BIT 233 drivers/iio/light/zopt2201.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 234 drivers/iio/light/zopt2201.c BIT(IIO_CHAN_INFO_SCALE), BIT 235 drivers/iio/light/zopt2201.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME), BIT 242 drivers/iio/light/zopt2201.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 243 drivers/iio/light/zopt2201.c BIT(IIO_CHAN_INFO_SCALE), BIT 244 drivers/iio/light/zopt2201.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME), BIT 248 drivers/iio/light/zopt2201.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 108 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_X_HIGH BIT(7) /* Axis over +threshold */ BIT 109 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_Y_HIGH BIT(6) BIT 110 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_Z_HIGH BIT(5) BIT 111 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_X_LOW BIT(4) /* Axis below -threshold */ BIT 112 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_Y_LOW BIT(3) BIT 113 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_Z_LOW BIT(2) BIT 114 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_RANGE BIT(1) /* Range overflow (any axis) */ BIT 116 drivers/iio/magnetometer/ak8974.c #define AK8974_STATUS_DRDY BIT(6) /* Data ready */ BIT 117 drivers/iio/magnetometer/ak8974.c #define AK8974_STATUS_OVERRUN BIT(5) /* Data overrun */ BIT 118 drivers/iio/magnetometer/ak8974.c #define AK8974_STATUS_INT BIT(4) /* Interrupt occurred */ BIT 120 drivers/iio/magnetometer/ak8974.c #define AK8974_CTRL1_POWER BIT(7) /* 0 = standby; 1 = active */ BIT 121 drivers/iio/magnetometer/ak8974.c #define AK8974_CTRL1_RATE BIT(4) /* 0 = 10 Hz; 1 = 20 Hz */ BIT 122 drivers/iio/magnetometer/ak8974.c #define AK8974_CTRL1_FORCE_EN BIT(1) /* 0 = normal; 1 = force */ BIT 123 drivers/iio/magnetometer/ak8974.c #define AK8974_CTRL1_MODE2 BIT(0) /* 0 */ BIT 125 drivers/iio/magnetometer/ak8974.c #define AK8974_CTRL2_INT_EN BIT(4) /* 1 = enable interrupts */ BIT 126 drivers/iio/magnetometer/ak8974.c #define AK8974_CTRL2_DRDY_EN BIT(3) /* 1 = enable data ready signal */ BIT 127 drivers/iio/magnetometer/ak8974.c #define AK8974_CTRL2_DRDY_POL BIT(2) /* 1 = data ready active high */ BIT 130 drivers/iio/magnetometer/ak8974.c #define AK8974_CTRL3_RESET BIT(7) /* Software reset */ BIT 131 drivers/iio/magnetometer/ak8974.c #define AK8974_CTRL3_FORCE BIT(6) /* Start forced measurement */ BIT 132 drivers/iio/magnetometer/ak8974.c #define AK8974_CTRL3_SELFTEST BIT(4) /* Set selftest register */ BIT 135 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_CTRL_XEN BIT(7) /* Enable interrupt for this axis */ BIT 136 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_CTRL_YEN BIT(6) BIT 137 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_CTRL_ZEN BIT(5) BIT 138 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_CTRL_XYZEN (BIT(7)|BIT(6)|BIT(5)) BIT 139 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_CTRL_POL BIT(3) /* 0 = active low; 1 = active high */ BIT 140 drivers/iio/magnetometer/ak8974.c #define AK8974_INT_CTRL_PULSE BIT(1) /* 0 = latched; 1 = pulse (50 usec) */ BIT 639 drivers/iio/magnetometer/ak8974.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 751 drivers/iio/magnetometer/ak8975.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 752 drivers/iio/magnetometer/ak8975.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 52 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_POWER_CTL BIT(0) BIT 66 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_DRDY_EN BIT(7) BIT 68 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_DRDY_INT3 BIT(6) BIT 69 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_DRDY_Z_EN BIT(5) BIT 70 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_DRDY_Y_EN BIT(4) BIT 71 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_DRDY_X_EN BIT(3) BIT 72 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_DRDY_DR_POLARITY BIT(2) BIT 73 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_DRDY_LATCHING BIT(1) BIT 74 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_DRDY_INT3_POLARITY BIT(0) BIT 637 drivers/iio/magnetometer/bmc150_magn.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 638 drivers/iio/magnetometer/bmc150_magn.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ BIT 639 drivers/iio/magnetometer/bmc150_magn.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT 640 drivers/iio/magnetometer/bmc150_magn.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 665 drivers/iio/magnetometer/bmc150_magn.c BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), BIT 70 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 71 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 72 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 73 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 74 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 79 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 80 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 81 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 82 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 83 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 88 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 89 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 90 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 91 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 92 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 97 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 98 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 99 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 100 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 101 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 106 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 107 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 108 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 109 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 110 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 115 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 116 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 117 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 118 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 119 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 124 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 125 drivers/iio/magnetometer/hid-sensor-magn-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 126 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 127 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 128 drivers/iio/magnetometer/hid-sensor-magn-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 469 drivers/iio/magnetometer/hmc5843_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 470 drivers/iio/magnetometer/hmc5843_core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 471 drivers/iio/magnetometer/hmc5843_core.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 487 drivers/iio/magnetometer/hmc5843_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 488 drivers/iio/magnetometer/hmc5843_core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 489 drivers/iio/magnetometer/hmc5843_core.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 35 drivers/iio/magnetometer/mag3110.c #define MAG3110_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) BIT 37 drivers/iio/magnetometer/mag3110.c #define MAG3110_CTRL_DR_MASK (BIT(7) | BIT(6) | BIT(5)) BIT 43 drivers/iio/magnetometer/mag3110.c #define MAG3110_CTRL_TM BIT(1) /* trigger single measurement */ BIT 44 drivers/iio/magnetometer/mag3110.c #define MAG3110_CTRL_AC BIT(0) /* continuous measurements */ BIT 46 drivers/iio/magnetometer/mag3110.c #define MAG3110_CTRL_AUTO_MRST_EN BIT(7) /* magnetic auto-reset */ BIT 47 drivers/iio/magnetometer/mag3110.c #define MAG3110_CTRL_RAW BIT(5) /* measurements not user-offset corrected */ BIT 417 drivers/iio/magnetometer/mag3110.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 418 drivers/iio/magnetometer/mag3110.c BIT(IIO_CHAN_INFO_CALIBBIAS), \ BIT 419 drivers/iio/magnetometer/mag3110.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT 420 drivers/iio/magnetometer/mag3110.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 436 drivers/iio/magnetometer/mag3110.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 437 drivers/iio/magnetometer/mag3110.c BIT(IIO_CHAN_INFO_SCALE), BIT 39 drivers/iio/magnetometer/mmc35240.c #define MMC35240_STATUS_MEAS_DONE_BIT BIT(0) BIT 41 drivers/iio/magnetometer/mmc35240.c #define MMC35240_CTRL0_REFILL_BIT BIT(7) BIT 42 drivers/iio/magnetometer/mmc35240.c #define MMC35240_CTRL0_RESET_BIT BIT(6) BIT 43 drivers/iio/magnetometer/mmc35240.c #define MMC35240_CTRL0_SET_BIT BIT(5) BIT 44 drivers/iio/magnetometer/mmc35240.c #define MMC35240_CTRL0_CMM_BIT BIT(1) BIT 45 drivers/iio/magnetometer/mmc35240.c #define MMC35240_CTRL0_TM_BIT BIT(0) BIT 48 drivers/iio/magnetometer/mmc35240.c #define MMC35240_CTRL1_BW0_BIT BIT(0) BIT 49 drivers/iio/magnetometer/mmc35240.c #define MMC35240_CTRL1_BW1_BIT BIT(1) BIT 148 drivers/iio/magnetometer/mmc35240.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 149 drivers/iio/magnetometer/mmc35240.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT 150 drivers/iio/magnetometer/mmc35240.c BIT(IIO_CHAN_INFO_SCALE), \ BIT 34 drivers/iio/magnetometer/rm3100-core.c #define RM3100_POLL_X BIT(4) BIT 35 drivers/iio/magnetometer/rm3100-core.c #define RM3100_POLL_Y BIT(5) BIT 36 drivers/iio/magnetometer/rm3100-core.c #define RM3100_POLL_Z BIT(6) BIT 40 drivers/iio/magnetometer/rm3100-core.c #define RM3100_CMM_START BIT(0) BIT 41 drivers/iio/magnetometer/rm3100-core.c #define RM3100_CMM_X BIT(4) BIT 42 drivers/iio/magnetometer/rm3100-core.c #define RM3100_CMM_Y BIT(5) BIT 43 drivers/iio/magnetometer/rm3100-core.c #define RM3100_CMM_Z BIT(6) BIT 51 drivers/iio/magnetometer/rm3100-core.c #define RM3100_STATUS_DRDY BIT(7) BIT 213 drivers/iio/magnetometer/rm3100-core.c ret = regmap_write(regmap, RM3100_REG_POLL, BIT(4 + idx)); BIT 241 drivers/iio/magnetometer/rm3100-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 242 drivers/iio/magnetometer/rm3100-core.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT 243 drivers/iio/magnetometer/rm3100-core.c BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 482 drivers/iio/magnetometer/rm3100-core.c case BIT(0) | BIT(1) | BIT(2): BIT 491 drivers/iio/magnetometer/rm3100-core.c case BIT(0) | BIT(1): BIT 498 drivers/iio/magnetometer/rm3100-core.c case BIT(1) | BIT(2): BIT 505 drivers/iio/magnetometer/rm3100-core.c case BIT(0) | BIT(2): BIT 59 drivers/iio/magnetometer/st_magn_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 63 drivers/iio/magnetometer/st_magn_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 67 drivers/iio/magnetometer/st_magn_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 75 drivers/iio/magnetometer/st_magn_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 79 drivers/iio/magnetometer/st_magn_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 83 drivers/iio/magnetometer/st_magn_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 91 drivers/iio/magnetometer/st_magn_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 95 drivers/iio/magnetometer/st_magn_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 99 drivers/iio/magnetometer/st_magn_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 330 drivers/iio/magnetometer/st_magn_core.c .value = BIT(2), BIT 261 drivers/iio/multiplexer/iio-mux.c chan->info_mask_separate |= BIT(IIO_CHAN_INFO_RAW); BIT 263 drivers/iio/multiplexer/iio-mux.c chan->info_mask_separate |= BIT(IIO_CHAN_INFO_SCALE); BIT 266 drivers/iio/multiplexer/iio-mux.c chan->info_mask_separate_available |= BIT(IIO_CHAN_INFO_RAW); BIT 52 drivers/iio/orientation/hid-sensor-incl-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 53 drivers/iio/orientation/hid-sensor-incl-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 54 drivers/iio/orientation/hid-sensor-incl-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 55 drivers/iio/orientation/hid-sensor-incl-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 56 drivers/iio/orientation/hid-sensor-incl-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 62 drivers/iio/orientation/hid-sensor-incl-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 63 drivers/iio/orientation/hid-sensor-incl-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 64 drivers/iio/orientation/hid-sensor-incl-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 65 drivers/iio/orientation/hid-sensor-incl-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 66 drivers/iio/orientation/hid-sensor-incl-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 72 drivers/iio/orientation/hid-sensor-incl-3d.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 73 drivers/iio/orientation/hid-sensor-incl-3d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 74 drivers/iio/orientation/hid-sensor-incl-3d.c BIT(IIO_CHAN_INFO_SCALE) | BIT 75 drivers/iio/orientation/hid-sensor-incl-3d.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 76 drivers/iio/orientation/hid-sensor-incl-3d.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 38 drivers/iio/orientation/hid-sensor-rotation.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 39 drivers/iio/orientation/hid-sensor-rotation.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 40 drivers/iio/orientation/hid-sensor-rotation.c BIT(IIO_CHAN_INFO_OFFSET) | BIT 41 drivers/iio/orientation/hid-sensor-rotation.c BIT(IIO_CHAN_INFO_SCALE) | BIT 42 drivers/iio/orientation/hid-sensor-rotation.c BIT(IIO_CHAN_INFO_HYSTERESIS) BIT 24 drivers/iio/potentiometer/ad5272.c #define AD5272_RDAC_WR_EN BIT(1) BIT 58 drivers/iio/potentiometer/ad5272.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 59 drivers/iio/potentiometer/ad5272.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 48 drivers/iio/potentiometer/ds1803.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 49 drivers/iio/potentiometer/ds1803.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 38 drivers/iio/potentiometer/max5432.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 39 drivers/iio/potentiometer/max5432.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 56 drivers/iio/potentiometer/max5481.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 57 drivers/iio/potentiometer/max5481.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 35 drivers/iio/potentiometer/max5487.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 36 drivers/iio/potentiometer/max5487.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 52 drivers/iio/potentiometer/mcp4018.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 53 drivers/iio/potentiometer/mcp4018.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 30 drivers/iio/potentiometer/mcp41010.c #define MCP41010_WRITE BIT(4) BIT 32 drivers/iio/potentiometer/mcp41010.c #define MCP41010_WIPER_CHANNEL BIT(0) BIT 71 drivers/iio/potentiometer/mcp41010.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 72 drivers/iio/potentiometer/mcp41010.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 140 drivers/iio/potentiometer/mcp4131.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 141 drivers/iio/potentiometer/mcp4131.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 129 drivers/iio/potentiometer/mcp4531.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 130 drivers/iio/potentiometer/mcp4531.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 131 drivers/iio/potentiometer/mcp4531.c .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_RAW), \ BIT 53 drivers/iio/potentiometer/tpl0102.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 54 drivers/iio/potentiometer/tpl0102.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 55 drivers/iio/potentiometer/tpl0102.c .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW), \ BIT 83 drivers/iio/potentiostat/lmp91000.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 84 drivers/iio/potentiostat/lmp91000.c BIT(IIO_CHAN_INFO_OFFSET) | BIT 85 drivers/iio/potentiostat/lmp91000.c BIT(IIO_CHAN_INFO_SCALE), BIT 98 drivers/iio/potentiostat/lmp91000.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 95 drivers/iio/pressure/abp060mg.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 96 drivers/iio/pressure/abp060mg.c BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_SCALE), BIT 130 drivers/iio/pressure/bmp280-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 131 drivers/iio/pressure/bmp280-core.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 135 drivers/iio/pressure/bmp280-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 136 drivers/iio/pressure/bmp280-core.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 140 drivers/iio/pressure/bmp280-core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 141 drivers/iio/pressure/bmp280-core.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 35 drivers/iio/pressure/bmp280.h #define BMP280_FILTER_MASK (BIT(4) | BIT(3) | BIT(2)) BIT 37 drivers/iio/pressure/bmp280.h #define BMP280_FILTER_2X BIT(2) BIT 38 drivers/iio/pressure/bmp280.h #define BMP280_FILTER_4X BIT(3) BIT 39 drivers/iio/pressure/bmp280.h #define BMP280_FILTER_8X (BIT(3) | BIT(2)) BIT 40 drivers/iio/pressure/bmp280.h #define BMP280_FILTER_16X BIT(4) BIT 42 drivers/iio/pressure/bmp280.h #define BMP280_OSRS_HUMIDITY_MASK (BIT(2) | BIT(1) | BIT(0)) BIT 51 drivers/iio/pressure/bmp280.h #define BMP280_OSRS_TEMP_MASK (BIT(7) | BIT(6) | BIT(5)) BIT 60 drivers/iio/pressure/bmp280.h #define BMP280_OSRS_PRESS_MASK (BIT(4) | BIT(3) | BIT(2)) BIT 69 drivers/iio/pressure/bmp280.h #define BMP280_MODE_MASK (BIT(1) | BIT(0)) BIT 71 drivers/iio/pressure/bmp280.h #define BMP280_MODE_FORCED BIT(0) BIT 72 drivers/iio/pressure/bmp280.h #define BMP280_MODE_NORMAL (BIT(1) | BIT(0)) BIT 82 drivers/iio/pressure/bmp280.h #define BMP180_MEAS_SCO BIT(5) BIT 148 drivers/iio/pressure/cros_ec_baro.c channel->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); BIT 150 drivers/iio/pressure/cros_ec_baro.c BIT(IIO_CHAN_INFO_SCALE) | BIT 151 drivers/iio/pressure/cros_ec_baro.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 152 drivers/iio/pressure/cros_ec_baro.c BIT(IIO_CHAN_INFO_FREQUENCY); BIT 154 drivers/iio/pressure/cros_ec_baro.c BIT(IIO_CHAN_INFO_SAMP_FREQ); BIT 40 drivers/iio/pressure/dps310.c #define DPS310_TMP_EXT BIT(7) BIT 43 drivers/iio/pressure/dps310.c #define DPS310_PRS_EN BIT(0) BIT 44 drivers/iio/pressure/dps310.c #define DPS310_TEMP_EN BIT(1) BIT 45 drivers/iio/pressure/dps310.c #define DPS310_BACKGROUND BIT(2) BIT 46 drivers/iio/pressure/dps310.c #define DPS310_PRS_RDY BIT(4) BIT 47 drivers/iio/pressure/dps310.c #define DPS310_TMP_RDY BIT(5) BIT 48 drivers/iio/pressure/dps310.c #define DPS310_SENSOR_RDY BIT(6) BIT 49 drivers/iio/pressure/dps310.c #define DPS310_COEF_RDY BIT(7) BIT 51 drivers/iio/pressure/dps310.c #define DPS310_INT_HL BIT(7) BIT 52 drivers/iio/pressure/dps310.c #define DPS310_TMP_SHIFT_EN BIT(3) BIT 53 drivers/iio/pressure/dps310.c #define DPS310_PRS_SHIFT_EN BIT(4) BIT 54 drivers/iio/pressure/dps310.c #define DPS310_FIFO_EN BIT(5) BIT 55 drivers/iio/pressure/dps310.c #define DPS310_SPI_EN BIT(6) BIT 97 drivers/iio/pressure/dps310.c .info_mask_separate = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | BIT 98 drivers/iio/pressure/dps310.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 99 drivers/iio/pressure/dps310.c BIT(IIO_CHAN_INFO_PROCESSED), BIT 103 drivers/iio/pressure/dps310.c .info_mask_separate = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | BIT 104 drivers/iio/pressure/dps310.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 105 drivers/iio/pressure/dps310.c BIT(IIO_CHAN_INFO_PROCESSED), BIT 171 drivers/iio/pressure/dps310.c return BIT(val & GENMASK(2, 0)); BIT 187 drivers/iio/pressure/dps310.c return BIT(val & GENMASK(2, 0)); BIT 265 drivers/iio/pressure/dps310.c return BIT((val & DPS310_PRS_RATE_BITS) >> 4); BIT 277 drivers/iio/pressure/dps310.c return BIT((val & DPS310_TMP_RATE_BITS) >> 4); BIT 698 drivers/iio/pressure/dps310.c if (reg & BIT(1)) BIT 38 drivers/iio/pressure/hid-sensor-press.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 39 drivers/iio/pressure/hid-sensor-press.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 40 drivers/iio/pressure/hid-sensor-press.c BIT(IIO_CHAN_INFO_SCALE) | BIT 41 drivers/iio/pressure/hid-sensor-press.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 42 drivers/iio/pressure/hid-sensor-press.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 50 drivers/iio/pressure/hp03.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 51 drivers/iio/pressure/hp03.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 55 drivers/iio/pressure/hp03.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 56 drivers/iio/pressure/hp03.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 324 drivers/iio/pressure/hp206c.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 325 drivers/iio/pressure/hp206c.c BIT(IIO_CHAN_INFO_SCALE) | BIT 326 drivers/iio/pressure/hp206c.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 330 drivers/iio/pressure/hp206c.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 331 drivers/iio/pressure/hp206c.c BIT(IIO_CHAN_INFO_SCALE) | BIT 332 drivers/iio/pressure/hp206c.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 131 drivers/iio/pressure/mpl115.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 135 drivers/iio/pressure/mpl115.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 137 drivers/iio/pressure/mpl115.c BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_SCALE), BIT 30 drivers/iio/pressure/mpl3115.c #define MPL3115_STATUS_PRESS_RDY BIT(2) BIT 31 drivers/iio/pressure/mpl3115.c #define MPL3115_STATUS_TEMP_RDY BIT(1) BIT 33 drivers/iio/pressure/mpl3115.c #define MPL3115_CTRL_RESET BIT(2) /* software reset */ BIT 34 drivers/iio/pressure/mpl3115.c #define MPL3115_CTRL_OST BIT(1) /* initiate measurement */ BIT 35 drivers/iio/pressure/mpl3115.c #define MPL3115_CTRL_ACTIVE BIT(0) /* continuous measurement */ BIT 36 drivers/iio/pressure/mpl3115.c #define MPL3115_CTRL_OS_258MS (BIT(5) | BIT(4)) /* 64x oversampling */ BIT 189 drivers/iio/pressure/mpl3115.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 190 drivers/iio/pressure/mpl3115.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 202 drivers/iio/pressure/mpl3115.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 203 drivers/iio/pressure/mpl3115.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 353 drivers/iio/pressure/ms5611_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 354 drivers/iio/pressure/ms5611_core.c BIT(IIO_CHAN_INFO_SCALE) | BIT 355 drivers/iio/pressure/ms5611_core.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 366 drivers/iio/pressure/ms5611_core.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 367 drivers/iio/pressure/ms5611_core.c BIT(IIO_CHAN_INFO_SCALE) | BIT 368 drivers/iio/pressure/ms5611_core.c BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), BIT 101 drivers/iio/pressure/ms5637.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 102 drivers/iio/pressure/ms5637.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 106 drivers/iio/pressure/ms5637.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 107 drivers/iio/pressure/ms5637.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 143 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 144 drivers/iio/pressure/st_pressure_core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 157 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_RAW) | BIT 158 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_SCALE) | BIT 159 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_OFFSET), BIT 160 drivers/iio/pressure/st_pressure_core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 177 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_RAW) | BIT 178 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_SCALE), BIT 191 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_RAW) | BIT 192 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_SCALE), BIT 209 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_RAW) | BIT 210 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_SCALE), BIT 211 drivers/iio/pressure/st_pressure_core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 224 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_RAW) | BIT 225 drivers/iio/pressure/st_pressure_core.c BIT(IIO_CHAN_INFO_SCALE), BIT 226 drivers/iio/pressure/st_pressure_core.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 302 drivers/iio/pressure/st_pressure_core.c .value = BIT(0), BIT 352 drivers/iio/pressure/st_pressure_core.c .value = BIT(0), BIT 419 drivers/iio/pressure/st_pressure_core.c .value = BIT(0), BIT 488 drivers/iio/pressure/st_pressure_core.c .value = BIT(0), BIT 539 drivers/iio/pressure/st_pressure_core.c .mask = BIT(1), BIT 544 drivers/iio/pressure/st_pressure_core.c .mask = BIT(2), BIT 546 drivers/iio/pressure/st_pressure_core.c .mask_od = BIT(5), BIT 549 drivers/iio/pressure/st_pressure_core.c .mask_ihl = BIT(6), BIT 557 drivers/iio/pressure/st_pressure_core.c .value = BIT(0), BIT 25 drivers/iio/pressure/t5403.c #define T5403_PT BIT(1) /* 0 .. pressure, 1 .. temperature measurement */ BIT 26 drivers/iio/pressure/t5403.c #define T5403_SCO BIT(0) /* start conversion */ BIT 33 drivers/iio/pressure/t5403.c #define T5403_I2C_MASK (~BIT(7)) BIT 185 drivers/iio/pressure/t5403.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 186 drivers/iio/pressure/t5403.c BIT(IIO_CHAN_INFO_INT_TIME), BIT 190 drivers/iio/pressure/t5403.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 1562 drivers/iio/pressure/zpa2326.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1563 drivers/iio/pressure/zpa2326.c BIT(IIO_CHAN_INFO_SCALE), BIT 1564 drivers/iio/pressure/zpa2326.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 1575 drivers/iio/pressure/zpa2326.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 1576 drivers/iio/pressure/zpa2326.c BIT(IIO_CHAN_INFO_SCALE) | BIT 1577 drivers/iio/pressure/zpa2326.c BIT(IIO_CHAN_INFO_OFFSET), BIT 1578 drivers/iio/pressure/zpa2326.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 21 drivers/iio/pressure/zpa2326.h #define ZPA2326_CTRL_REG0_ONE_SHOT BIT(0) BIT 22 drivers/iio/pressure/zpa2326.h #define ZPA2326_CTRL_REG0_ENABLE BIT(1) BIT 24 drivers/iio/pressure/zpa2326.h #define ZPA2326_CTRL_REG1_MASK_DATA_READY BIT(2) BIT 26 drivers/iio/pressure/zpa2326.h #define ZPA2326_CTRL_REG2_SWRESET BIT(2) BIT 29 drivers/iio/pressure/zpa2326.h #define ZPA2326_CTRL_REG3_ENABLE_MEAS BIT(7) BIT 31 drivers/iio/pressure/zpa2326.h #define ZPA2326_INT_SOURCE_DATA_READY BIT(2) BIT 35 drivers/iio/pressure/zpa2326.h #define ZPA2326_STATUS_P_DA BIT(1) BIT 36 drivers/iio/pressure/zpa2326.h #define ZPA2326_STATUS_FIFO_E BIT(2) BIT 37 drivers/iio/pressure/zpa2326.h #define ZPA2326_STATUS_P_OR BIT(5) BIT 27 drivers/iio/pressure/zpa2326_i2c.c .read_flag_mask = BIT(7), BIT 33 drivers/iio/pressure/zpa2326_i2c.c #define ZPA2326_SA0(_addr) (_addr & BIT(0)) BIT 28 drivers/iio/pressure/zpa2326_spi.c .read_flag_mask = BIT(7) | BIT(6), BIT 31 drivers/iio/proximity/as3935.c #define AS3935_AFE_PWR_BIT BIT(0) BIT 38 drivers/iio/proximity/as3935.c #define AS3935_DISTURB_INT BIT(2) BIT 39 drivers/iio/proximity/as3935.c #define AS3935_EVENT_INT BIT(3) BIT 40 drivers/iio/proximity/as3935.c #define AS3935_NOISE_INT BIT(0) BIT 49 drivers/iio/proximity/as3935.c #define AS3935_READ_DATA BIT(14) BIT 72 drivers/iio/proximity/as3935.c BIT(IIO_CHAN_INFO_RAW) | BIT 73 drivers/iio/proximity/as3935.c BIT(IIO_CHAN_INFO_PROCESSED) | BIT 74 drivers/iio/proximity/as3935.c BIT(IIO_CHAN_INFO_SCALE), BIT 292 drivers/iio/proximity/as3935.c BIT(5) | (st->tune_cap / TUNE_CAP_DIV)); BIT 495 drivers/iio/proximity/isl29501.c BIT(IIO_CHAN_INFO_RAW) | BIT 496 drivers/iio/proximity/isl29501.c BIT(IIO_CHAN_INFO_SCALE) | BIT 497 drivers/iio/proximity/isl29501.c BIT(IIO_CHAN_INFO_CALIBBIAS), BIT 504 drivers/iio/proximity/isl29501.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) | BIT 505 drivers/iio/proximity/isl29501.c BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 511 drivers/iio/proximity/isl29501.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 512 drivers/iio/proximity/isl29501.c BIT(IIO_CHAN_INFO_SCALE), BIT 518 drivers/iio/proximity/isl29501.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 519 drivers/iio/proximity/isl29501.c BIT(IIO_CHAN_INFO_SCALE), BIT 524 drivers/iio/proximity/isl29501.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 525 drivers/iio/proximity/isl29501.c BIT(IIO_CHAN_INFO_SCALE) | BIT 526 drivers/iio/proximity/isl29501.c BIT(IIO_CHAN_INFO_CALIBBIAS), BIT 533 drivers/iio/proximity/isl29501.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 534 drivers/iio/proximity/isl29501.c BIT(IIO_CHAN_INFO_SCALE), BIT 163 drivers/iio/proximity/mb1232.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 164 drivers/iio/proximity/mb1232.c BIT(IIO_CHAN_INFO_SCALE), BIT 25 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c #define LIDAR_REG_CONTROL_ACQUIRE BIT(2) BIT 28 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c #define LIDAR_REG_STATUS_INVALID BIT(3) BIT 29 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c #define LIDAR_REG_STATUS_READY BIT(0) BIT 33 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c #define LIDAR_REG_DATA_WORD_READ BIT(7) BIT 53 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 22 drivers/iio/proximity/rfd77402.c #define RFD77402_ICSR_INT_MODE BIT(2) BIT 23 drivers/iio/proximity/rfd77402.c #define RFD77402_ICSR_INT_POL BIT(3) BIT 24 drivers/iio/proximity/rfd77402.c #define RFD77402_ICSR_RESULT BIT(4) BIT 25 drivers/iio/proximity/rfd77402.c #define RFD77402_ICSR_M2H_MSG BIT(5) BIT 26 drivers/iio/proximity/rfd77402.c #define RFD77402_ICSR_H2M_MSG BIT(6) BIT 27 drivers/iio/proximity/rfd77402.c #define RFD77402_ICSR_RESET BIT(7) BIT 34 drivers/iio/proximity/rfd77402.c #define RFD77402_CMD_RESET BIT(6) BIT 35 drivers/iio/proximity/rfd77402.c #define RFD77402_CMD_VALID BIT(7) BIT 46 drivers/iio/proximity/rfd77402.c #define RFD77402_RESULT_VALID BIT(15) BIT 49 drivers/iio/proximity/rfd77402.c #define RFD77402_PMU_MCPU_INIT BIT(9) BIT 52 drivers/iio/proximity/rfd77402.c #define RFD77402_I2C_ADDR_INCR BIT(0) BIT 53 drivers/iio/proximity/rfd77402.c #define RFD77402_I2C_DATA_INCR BIT(2) BIT 54 drivers/iio/proximity/rfd77402.c #define RFD77402_I2C_HOST_DEBUG BIT(5) BIT 55 drivers/iio/proximity/rfd77402.c #define RFD77402_I2C_MCPU_DEBUG BIT(6) BIT 88 drivers/iio/proximity/rfd77402.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 89 drivers/iio/proximity/rfd77402.c BIT(IIO_CHAN_INFO_SCALE), BIT 219 drivers/iio/proximity/srf04.c BIT(IIO_CHAN_INFO_RAW) | BIT 220 drivers/iio/proximity/srf04.c BIT(IIO_CHAN_INFO_SCALE), BIT 420 drivers/iio/proximity/srf08.c BIT(IIO_CHAN_INFO_RAW) | BIT 421 drivers/iio/proximity/srf08.c BIT(IIO_CHAN_INFO_SCALE), BIT 69 drivers/iio/proximity/sx9500.c #define SX9500_CLOSE_IRQ BIT(6) BIT 70 drivers/iio/proximity/sx9500.c #define SX9500_FAR_IRQ BIT(5) BIT 71 drivers/iio/proximity/sx9500.c #define SX9500_CONVDONE_IRQ BIT(3) BIT 104 drivers/iio/proximity/sx9500.c .mask_separate = BIT(IIO_EV_INFO_ENABLE), BIT 111 drivers/iio/proximity/sx9500.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 112 drivers/iio/proximity/sx9500.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 229 drivers/iio/proximity/sx9500.c SX9500_REG_PROX_CTRL0, BIT(chan)); BIT 235 drivers/iio/proximity/sx9500.c SX9500_REG_PROX_CTRL0, BIT(chan)); BIT 482 drivers/iio/proximity/sx9500.c bool new_prox = val & BIT(chan); BIT 27 drivers/iio/proximity/vl53l0x-i2c.c #define VL_REG_SYSRANGE_MODE_START_STOP BIT(0) BIT 28 drivers/iio/proximity/vl53l0x-i2c.c #define VL_REG_SYSRANGE_MODE_BACKTOBACK BIT(1) BIT 29 drivers/iio/proximity/vl53l0x-i2c.c #define VL_REG_SYSRANGE_MODE_TIMED BIT(2) BIT 30 drivers/iio/proximity/vl53l0x-i2c.c #define VL_REG_SYSRANGE_MODE_HISTOGRAM BIT(3) BIT 34 drivers/iio/proximity/vl53l0x-i2c.c #define VL_REG_RESULT_RANGE_STATUS_COMPLETE BIT(0) BIT 83 drivers/iio/proximity/vl53l0x-i2c.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 84 drivers/iio/proximity/vl53l0x-i2c.c BIT(IIO_CHAN_INFO_SCALE), BIT 117 drivers/iio/resolver/ad2s1200.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 118 drivers/iio/resolver/ad2s1200.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 123 drivers/iio/resolver/ad2s1200.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 124 drivers/iio/resolver/ad2s1200.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), BIT 75 drivers/iio/resolver/ad2s90.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 31 drivers/iio/temperature/hid-sensor-temperature.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 32 drivers/iio/temperature/hid-sensor-temperature.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 33 drivers/iio/temperature/hid-sensor-temperature.c BIT(IIO_CHAN_INFO_SCALE) | BIT 34 drivers/iio/temperature/hid-sensor-temperature.c BIT(IIO_CHAN_INFO_SAMP_FREQ) | BIT 35 drivers/iio/temperature/hid-sensor-temperature.c BIT(IIO_CHAN_INFO_HYSTERESIS), BIT 20 drivers/iio/temperature/max31856.c #define MAX31856_RD_WR_BIT BIT(7) BIT 22 drivers/iio/temperature/max31856.c #define MAX31856_CR0_AUTOCONVERT BIT(7) BIT 23 drivers/iio/temperature/max31856.c #define MAX31856_CR0_1SHOT BIT(6) BIT 24 drivers/iio/temperature/max31856.c #define MAX31856_CR0_OCFAULT BIT(4) BIT 27 drivers/iio/temperature/max31856.c #define MAX31856_FAULT_OVUV BIT(1) BIT 28 drivers/iio/temperature/max31856.c #define MAX31856_FAULT_OPEN BIT(0) BIT 52 drivers/iio/temperature/max31856.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 59 drivers/iio/temperature/max31856.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 33 drivers/iio/temperature/maxim_thermocouple.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 51 drivers/iio/temperature/maxim_thermocouple.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 67 drivers/iio/temperature/maxim_thermocouple.c BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), BIT 97 drivers/iio/temperature/maxim_thermocouple.c .status_bit = BIT(2), BIT 104 drivers/iio/temperature/maxim_thermocouple.c .status_bit = BIT(16), BIT 366 drivers/iio/temperature/mlx90614.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 367 drivers/iio/temperature/mlx90614.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 368 drivers/iio/temperature/mlx90614.c BIT(IIO_CHAN_INFO_SCALE), BIT 374 drivers/iio/temperature/mlx90614.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 375 drivers/iio/temperature/mlx90614.c BIT(IIO_CHAN_INFO_CALIBEMISSIVITY) | BIT 376 drivers/iio/temperature/mlx90614.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), BIT 377 drivers/iio/temperature/mlx90614.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 378 drivers/iio/temperature/mlx90614.c BIT(IIO_CHAN_INFO_SCALE), BIT 386 drivers/iio/temperature/mlx90614.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 387 drivers/iio/temperature/mlx90614.c BIT(IIO_CHAN_INFO_CALIBEMISSIVITY) | BIT 388 drivers/iio/temperature/mlx90614.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), BIT 389 drivers/iio/temperature/mlx90614.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | BIT 390 drivers/iio/temperature/mlx90614.c BIT(IIO_CHAN_INFO_SCALE), BIT 70 drivers/iio/temperature/mlx90632.c #define MLX90632_STAT_BUSY BIT(10) /* Device busy indicator */ BIT 71 drivers/iio/temperature/mlx90632.c #define MLX90632_STAT_EE_BUSY BIT(9) /* EEPROM busy indicator */ BIT 72 drivers/iio/temperature/mlx90632.c #define MLX90632_STAT_BRST BIT(8) /* Brown out reset indicator */ BIT 74 drivers/iio/temperature/mlx90632.c #define MLX90632_STAT_DATA_RDY BIT(0) /* Data ready indicator */ BIT 581 drivers/iio/temperature/mlx90632.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 587 drivers/iio/temperature/mlx90632.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | BIT 588 drivers/iio/temperature/mlx90632.c BIT(IIO_CHAN_INFO_CALIBEMISSIVITY), BIT 32 drivers/iio/temperature/tmp006.c #define TMP006_CONFIG_RESET BIT(15) BIT 33 drivers/iio/temperature/tmp006.c #define TMP006_CONFIG_DRDY_EN BIT(8) BIT 34 drivers/iio/temperature/tmp006.c #define TMP006_CONFIG_DRDY BIT(7) BIT 163 drivers/iio/temperature/tmp006.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 164 drivers/iio/temperature/tmp006.c BIT(IIO_CHAN_INFO_SCALE), BIT 165 drivers/iio/temperature/tmp006.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 169 drivers/iio/temperature/tmp006.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 170 drivers/iio/temperature/tmp006.c BIT(IIO_CHAN_INFO_SCALE), BIT 171 drivers/iio/temperature/tmp006.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 43 drivers/iio/temperature/tmp007.c #define TMP007_CONFIG_CONV_EN BIT(12) BIT 44 drivers/iio/temperature/tmp007.c #define TMP007_CONFIG_TC_EN BIT(6) BIT 46 drivers/iio/temperature/tmp007.c #define TMP007_CONFIG_ALERT_EN BIT(8) BIT 50 drivers/iio/temperature/tmp007.c #define TMP007_STATUS_ALERT BIT(15) BIT 51 drivers/iio/temperature/tmp007.c #define TMP007_STATUS_CONV_READY BIT(14) BIT 52 drivers/iio/temperature/tmp007.c #define TMP007_STATUS_OHF BIT(13) BIT 53 drivers/iio/temperature/tmp007.c #define TMP007_STATUS_OLF BIT(12) BIT 54 drivers/iio/temperature/tmp007.c #define TMP007_STATUS_LHF BIT(11) BIT 55 drivers/iio/temperature/tmp007.c #define TMP007_STATUS_LLF BIT(10) BIT 56 drivers/iio/temperature/tmp007.c #define TMP007_STATUS_DATA_VALID BIT(9) BIT 368 drivers/iio/temperature/tmp007.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 369 drivers/iio/temperature/tmp007.c BIT(IIO_EV_INFO_ENABLE), BIT 374 drivers/iio/temperature/tmp007.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 375 drivers/iio/temperature/tmp007.c BIT(IIO_EV_INFO_ENABLE), BIT 383 drivers/iio/temperature/tmp007.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 384 drivers/iio/temperature/tmp007.c BIT(IIO_EV_INFO_ENABLE), BIT 389 drivers/iio/temperature/tmp007.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 390 drivers/iio/temperature/tmp007.c BIT(IIO_EV_INFO_ENABLE), BIT 399 drivers/iio/temperature/tmp007.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 400 drivers/iio/temperature/tmp007.c BIT(IIO_CHAN_INFO_SCALE), BIT 401 drivers/iio/temperature/tmp007.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 409 drivers/iio/temperature/tmp007.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 410 drivers/iio/temperature/tmp007.c BIT(IIO_CHAN_INFO_SCALE), BIT 411 drivers/iio/temperature/tmp007.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 107 drivers/iio/temperature/tsys01.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_PROCESSED), BIT 89 drivers/iio/temperature/tsys02d.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_PROCESSED), BIT 90 drivers/iio/temperature/tsys02d.c .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 668 drivers/iio/trigger/stm32-timer-trigger.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 669 drivers/iio/trigger/stm32-timer-trigger.c BIT(IIO_CHAN_INFO_ENABLE) | BIT 670 drivers/iio/trigger/stm32-timer-trigger.c BIT(IIO_CHAN_INFO_SCALE), BIT 169 drivers/infiniband/core/cache.c return index < 32 && (BIT(index) & table->default_gid_indices); BIT 883 drivers/infiniband/core/cache.c table->default_gid_indices |= BIT(i); BIT 4273 drivers/infiniband/core/cma.c if ((rec.join_state == BIT(SENDONLY_FULLMEMBER_JOIN)) && BIT 4356 drivers/infiniband/core/cma.c send_only = mc->join_state == BIT(SENDONLY_FULLMEMBER_JOIN); BIT 1436 drivers/infiniband/core/ucma.c join_state = BIT(FULLMEMBER_JOIN); BIT 1438 drivers/infiniband/core/ucma.c join_state = BIT(SENDONLY_FULLMEMBER_JOIN); BIT 525 drivers/infiniband/core/umem_odp.c ib_dma_map_page(dev, page, 0, BIT(umem_odp->page_shift), BIT 611 drivers/infiniband/core/umem_odp.c page_mask = ~(BIT(page_shift) - 1); BIT 733 drivers/infiniband/core/umem_odp.c for (addr = virt; addr < bound; addr += BIT(umem_odp->page_shift)) { BIT 743 drivers/infiniband/core/umem_odp.c BIT(umem_odp->page_shift), BIT 2781 drivers/infiniband/core/uverbs_cmd.c if ((ntohl(ib_spec->ipv6.mask.flow_label)) >= BIT(20) || BIT 2782 drivers/infiniband/core/uverbs_cmd.c (ntohl(ib_spec->ipv6.val.flow_label)) >= BIT(20)) BIT 2808 drivers/infiniband/core/uverbs_cmd.c if ((ntohl(ib_spec->tunnel.mask.tunnel_id)) >= BIT(24) || BIT 2809 drivers/infiniband/core/uverbs_cmd.c (ntohl(ib_spec->tunnel.val.tunnel_id)) >= BIT(24)) BIT 52 drivers/infiniband/hw/bnxt_re/bnxt_re.h #define BNXT_RE_PAGE_SIZE_4K BIT(BNXT_RE_PAGE_SHIFT_4K) BIT 53 drivers/infiniband/hw/bnxt_re/bnxt_re.h #define BNXT_RE_PAGE_SIZE_8K BIT(BNXT_RE_PAGE_SHIFT_8K) BIT 54 drivers/infiniband/hw/bnxt_re/bnxt_re.h #define BNXT_RE_PAGE_SIZE_64K BIT(BNXT_RE_PAGE_SHIFT_64K) BIT 55 drivers/infiniband/hw/bnxt_re/bnxt_re.h #define BNXT_RE_PAGE_SIZE_2M BIT(BNXT_RE_PAGE_SHIFT_2M) BIT 56 drivers/infiniband/hw/bnxt_re/bnxt_re.h #define BNXT_RE_PAGE_SIZE_8M BIT(BNXT_RE_PAGE_SHIFT_8M) BIT 57 drivers/infiniband/hw/bnxt_re/bnxt_re.h #define BNXT_RE_PAGE_SIZE_1G BIT(BNXT_RE_PAGE_SHIFT_1G) BIT 132 drivers/infiniband/hw/bnxt_re/qplib_fp.h #define BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP BIT(0) BIT 133 drivers/infiniband/hw/bnxt_re/qplib_fp.h #define BNXT_QPLIB_SWQE_FLAGS_RD_ATOMIC_FENCE BIT(1) BIT 134 drivers/infiniband/hw/bnxt_re/qplib_fp.h #define BNXT_QPLIB_SWQE_FLAGS_UC_FENCE BIT(2) BIT 135 drivers/infiniband/hw/bnxt_re/qplib_fp.h #define BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT BIT(3) BIT 136 drivers/infiniband/hw/bnxt_re/qplib_fp.h #define BNXT_QPLIB_SWQE_FLAGS_INLINE BIT(4) BIT 214 drivers/infiniband/hw/bnxt_re/qplib_fp.h #define BNXT_QPLIB_BIND_SWQE_ACCESS_LOCAL_WRITE BIT(0) BIT 215 drivers/infiniband/hw/bnxt_re/qplib_fp.h #define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_READ BIT(1) BIT 216 drivers/infiniband/hw/bnxt_re/qplib_fp.h #define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_WRITE BIT(2) BIT 217 drivers/infiniband/hw/bnxt_re/qplib_fp.h #define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_ATOMIC BIT(3) BIT 218 drivers/infiniband/hw/bnxt_re/qplib_fp.h #define BNXT_QPLIB_BIND_SWQE_ACCESS_WINDOW_BIND BIT(4) BIT 188 drivers/infiniband/hw/bnxt_re/qplib_rcfw.c cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG); BIT 128 drivers/infiniband/hw/bnxt_re/qplib_sp.h #define BNXT_QPLIB_ACCESS_LOCAL_WRITE BIT(0) BIT 129 drivers/infiniband/hw/bnxt_re/qplib_sp.h #define BNXT_QPLIB_ACCESS_REMOTE_READ BIT(1) BIT 130 drivers/infiniband/hw/bnxt_re/qplib_sp.h #define BNXT_QPLIB_ACCESS_REMOTE_WRITE BIT(2) BIT 131 drivers/infiniband/hw/bnxt_re/qplib_sp.h #define BNXT_QPLIB_ACCESS_REMOTE_ATOMIC BIT(3) BIT 132 drivers/infiniband/hw/bnxt_re/qplib_sp.h #define BNXT_QPLIB_ACCESS_MW_BIND BIT(4) BIT 133 drivers/infiniband/hw/bnxt_re/qplib_sp.h #define BNXT_QPLIB_ACCESS_ZERO_BASED BIT(5) BIT 134 drivers/infiniband/hw/bnxt_re/qplib_sp.h #define BNXT_QPLIB_ACCESS_ON_DEMAND BIT(6) BIT 65 drivers/infiniband/hw/cxgb4/t4.h #define T4_RQT_ENTRY_SIZE BIT(T4_RQT_ENTRY_SHIFT) BIT 774 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h #define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0) BIT 776 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h #define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1) BIT 781 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h #define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7) BIT 782 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h #define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0) BIT 786 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) BIT 788 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6) BIT 123 drivers/infiniband/hw/efa/efa_admin_defs.h #define EFA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) BIT 125 drivers/infiniband/hw/efa/efa_admin_defs.h #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) BIT 127 drivers/infiniband/hw/efa/efa_admin_defs.h #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) BIT 131 drivers/infiniband/hw/efa/efa_admin_defs.h #define EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) BIT 134 drivers/infiniband/hw/efa/efa_admin_defs.h #define EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) BIT 27 drivers/infiniband/hw/efa/efa_main.c #define EFA_BASE_BAR_MASK (BIT(EFA_REG_BAR) | BIT(EFA_MEM_BAR)) BIT 30 drivers/infiniband/hw/efa/efa_main.c (BIT(EFA_ADMIN_FATAL_ERROR) | BIT(EFA_ADMIN_WARNING) | \ BIT 31 drivers/infiniband/hw/efa/efa_main.c BIT(EFA_ADMIN_NOTIFICATION) | BIT(EFA_ADMIN_KEEP_ALIVE)) BIT 149 drivers/infiniband/hw/efa/efa_main.c if (!(BIT(db_bar_idx) & EFA_BASE_BAR_MASK)) { BIT 150 drivers/infiniband/hw/efa/efa_main.c bars = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(db_bar_idx); BIT 169 drivers/infiniband/hw/efa/efa_main.c if (!(BIT(dev->dev_attr.db_bar) & EFA_BASE_BAR_MASK)) BIT 170 drivers/infiniband/hw/efa/efa_main.c efa_release_bars(dev, BIT(dev->dev_attr.db_bar)); BIT 27 drivers/infiniband/hw/efa/efa_verbs.c (BIT(EFA_ADMIN_FATAL_ERROR) | BIT(EFA_ADMIN_WARNING) | \ BIT 28 drivers/infiniband/hw/efa/efa_verbs.c BIT(EFA_ADMIN_NOTIFICATION) | BIT(EFA_ADMIN_KEEP_ALIVE)) BIT 72 drivers/infiniband/hw/efa/efa_verbs.c #define EFA_CHUNK_PAYLOAD_SIZE BIT(EFA_CHUNK_PAYLOAD_SHIFT) BIT 76 drivers/infiniband/hw/efa/efa_verbs.c #define EFA_CHUNK_SIZE BIT(EFA_CHUNK_SHIFT) BIT 850 drivers/infiniband/hw/efa/efa_verbs.c params.modify_mask |= BIT(EFA_ADMIN_QP_STATE_BIT) | BIT 851 drivers/infiniband/hw/efa/efa_verbs.c BIT(EFA_ADMIN_CUR_QP_STATE_BIT); BIT 858 drivers/infiniband/hw/efa/efa_verbs.c BIT(EFA_ADMIN_SQ_DRAINED_ASYNC_NOTIFY_BIT); BIT 863 drivers/infiniband/hw/efa/efa_verbs.c params.modify_mask |= BIT(EFA_ADMIN_QKEY_BIT); BIT 868 drivers/infiniband/hw/efa/efa_verbs.c params.modify_mask |= BIT(EFA_ADMIN_SQ_PSN_BIT); BIT 1051 drivers/infiniband/hw/efa/efa_verbs.c u32 pages_in_hp = BIT(hp_shift - PAGE_SHIFT); BIT 1059 drivers/infiniband/hw/efa/efa_verbs.c BIT(hp_shift)) BIT 267 drivers/infiniband/hw/hfi1/chip.h #define SPICO_ROM_FAILED BIT(0) BIT 268 drivers/infiniband/hw/hfi1/chip.h #define UNKNOWN_FRAME BIT(1) BIT 269 drivers/infiniband/hw/hfi1/chip.h #define TARGET_BER_NOT_MET BIT(2) BIT 270 drivers/infiniband/hw/hfi1/chip.h #define FAILED_SERDES_INTERNAL_LOOPBACK BIT(3) BIT 271 drivers/infiniband/hw/hfi1/chip.h #define FAILED_SERDES_INIT BIT(4) BIT 272 drivers/infiniband/hw/hfi1/chip.h #define FAILED_LNI_POLLING BIT(5) BIT 273 drivers/infiniband/hw/hfi1/chip.h #define FAILED_LNI_DEBOUNCE BIT(6) BIT 274 drivers/infiniband/hw/hfi1/chip.h #define FAILED_LNI_ESTBCOMM BIT(7) BIT 275 drivers/infiniband/hw/hfi1/chip.h #define FAILED_LNI_OPTEQ BIT(8) BIT 276 drivers/infiniband/hw/hfi1/chip.h #define FAILED_LNI_VERIFY_CAP1 BIT(9) BIT 277 drivers/infiniband/hw/hfi1/chip.h #define FAILED_LNI_VERIFY_CAP2 BIT(10) BIT 278 drivers/infiniband/hw/hfi1/chip.h #define FAILED_LNI_CONFIGLT BIT(11) BIT 279 drivers/infiniband/hw/hfi1/chip.h #define HOST_HANDSHAKE_TIMEOUT BIT(12) BIT 280 drivers/infiniband/hw/hfi1/chip.h #define EXTERNAL_DEVICE_REQ_TIMEOUT BIT(13) BIT 290 drivers/infiniband/hw/hfi1/chip.h #define HOST_REQ_DONE BIT(0) BIT 291 drivers/infiniband/hw/hfi1/chip.h #define BC_PWR_MGM_MSG BIT(1) BIT 292 drivers/infiniband/hw/hfi1/chip.h #define BC_SMA_MSG BIT(2) BIT 293 drivers/infiniband/hw/hfi1/chip.h #define BC_BCC_UNKNOWN_MSG BIT(3) BIT 294 drivers/infiniband/hw/hfi1/chip.h #define BC_IDLE_UNKNOWN_MSG BIT(4) BIT 295 drivers/infiniband/hw/hfi1/chip.h #define EXT_DEVICE_CFG_REQ BIT(5) BIT 296 drivers/infiniband/hw/hfi1/chip.h #define VERIFY_CAP_FRAME BIT(6) BIT 297 drivers/infiniband/hw/hfi1/chip.h #define LINKUP_ACHIEVED BIT(7) BIT 298 drivers/infiniband/hw/hfi1/chip.h #define LINK_GOING_DOWN BIT(8) BIT 299 drivers/infiniband/hw/hfi1/chip.h #define LINK_WIDTH_DOWNGRADED BIT(9) BIT 367 drivers/infiniband/hw/hfi1/chip.h #define RCV_INCREMENT BIT(RCV_SHIFT) BIT 374 drivers/infiniband/hw/hfi1/chip.h #define HDRQ_INCREMENT BIT(HDRQ_SIZE_SHIFT) BIT 345 drivers/infiniband/hw/hfi1/common.h #define HFI1_KDETH_BTH_SEQ_MASK (BIT(HFI1_KDETH_BTH_SEQ_SHIFT) - 1) BIT 58 drivers/infiniband/hw/hfi1/fault.c #define HFI1_FAULT_DIR_TX BIT(0) BIT 59 drivers/infiniband/hw/hfi1/fault.c #define HFI1_FAULT_DIR_RX BIT(1) BIT 385 drivers/infiniband/hw/hfi1/file_ops.c (uctxt->sc->hw_context * BIT(16))) + BIT 622 drivers/infiniband/hw/hfi1/hfi.h #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP) BIT 623 drivers/infiniband/hw/hfi1/hfi.h #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP) BIT 624 drivers/infiniband/hw/hfi1/hfi.h #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP) BIT 625 drivers/infiniband/hw/hfi1/hfi.h #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */ BIT 626 drivers/infiniband/hw/hfi1/hfi.h #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP) BIT 627 drivers/infiniband/hw/hfi1/hfi.h #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP) BIT 628 drivers/infiniband/hw/hfi1/hfi.h #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP) BIT 629 drivers/infiniband/hw/hfi1/hfi.h #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP) BIT 630 drivers/infiniband/hw/hfi1/hfi.h #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP) BIT 631 drivers/infiniband/hw/hfi1/hfi.h #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP) BIT 632 drivers/infiniband/hw/hfi1/hfi.h #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP) BIT 1532 drivers/infiniband/hw/hfi1/hfi.h #define HFI1_JKEY_MASK (BIT(16) - 1) BIT 1548 drivers/infiniband/hw/hfi1/hfi.h jkey |= BIT(HFI1_JKEY_WIDTH - 1); BIT 2149 drivers/infiniband/hw/hfi1/mad.c #define __CI_PAGE_SIZE BIT(7) /* 128 bytes */ BIT 4037 drivers/infiniband/hw/hfi1/mad.c #define OPA_LED_MASK BIT(OPA_LED_SHIFT) BIT 11 drivers/infiniband/hw/hfi1/opfn.c #define IB_BTHE_E BIT(IB_BTHE_E_SHIFT) BIT 13 drivers/infiniband/hw/hfi1/opfn.c #define OPFN_CODE(code) BIT((code) - 1) BIT 80 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), BIT 85 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_RC), BIT 91 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_RC), BIT 97 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_RC), BIT 103 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), BIT 108 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) | BIT 109 drivers/infiniband/hw/hfi1/qp.c BIT(IB_QPT_UC) | BIT(IB_QPT_RC), BIT 114 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) | BIT 115 drivers/infiniband/hw/hfi1/qp.c BIT(IB_QPT_UC) | BIT(IB_QPT_RC), BIT 120 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), BIT 126 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), BIT 132 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_RC), BIT 137 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_RC), BIT 143 drivers/infiniband/hw/hfi1/qp.c .qpt_support = BIT(IB_QPT_RC), BIT 59 drivers/infiniband/hw/hfi1/qsfp.h #define QSFP_HFI0_I2CCLK BIT(0) BIT 60 drivers/infiniband/hw/hfi1/qsfp.h #define QSFP_HFI0_I2CDAT BIT(1) BIT 61 drivers/infiniband/hw/hfi1/qsfp.h #define QSFP_HFI0_RESET_N BIT(2) BIT 62 drivers/infiniband/hw/hfi1/qsfp.h #define QSFP_HFI0_INT_N BIT(3) BIT 63 drivers/infiniband/hw/hfi1/qsfp.h #define QSFP_HFI0_MODPRST_N BIT(4) BIT 113 drivers/infiniband/hw/hfi1/sdma.c #define SDMA_SENDCTRL_OP_ENABLE BIT(0) BIT 114 drivers/infiniband/hw/hfi1/sdma.c #define SDMA_SENDCTRL_OP_INTENABLE BIT(1) BIT 115 drivers/infiniband/hw/hfi1/sdma.c #define SDMA_SENDCTRL_OP_HALT BIT(2) BIT 116 drivers/infiniband/hw/hfi1/sdma.c #define SDMA_SENDCTRL_OP_CLEANUP BIT(3) BIT 38 drivers/infiniband/hw/hfi1/tid_rdma.c #define MAX_TID_FLOW_PSN BIT(HFI1_KDETH_BTH_SEQ_SHIFT) BIT 1308 drivers/infiniband/hw/hfi1/tid_rdma.c if (node->map & BIT(i) || cnt >= node->cnt) { BIT 1356 drivers/infiniband/hw/hfi1/tid_rdma.c grp->map |= BIT(i); BIT 1373 drivers/infiniband/hw/hfi1/tid_rdma.c if (node->map & BIT(i) || cnt >= node->cnt) { BIT 1381 drivers/infiniband/hw/hfi1/tid_rdma.c grp->map &= ~BIT(i); BIT 17 drivers/infiniband/hw/hfi1/tid_rdma.h #define TID_RDMA_MIN_SEGMENT_SIZE BIT(18) /* 256 KiB (for now) */ BIT 18 drivers/infiniband/hw/hfi1/tid_rdma.h #define TID_RDMA_MAX_SEGMENT_SIZE BIT(18) /* 256 KiB (for now) */ BIT 19 drivers/infiniband/hw/hfi1/tid_rdma.h #define TID_RDMA_MAX_PAGES (BIT(18) >> PAGE_SHIFT) BIT 31 drivers/infiniband/hw/hfi1/tid_rdma.h #define HFI1_S_TID_BUSY_SET BIT(0) BIT 33 drivers/infiniband/hw/hfi1/tid_rdma.h #define HFI1_R_TID_RSC_TIMER BIT(2) BIT 36 drivers/infiniband/hw/hfi1/tid_rdma.h #define HFI1_S_TID_WAIT_INTERLCK BIT(5) BIT 37 drivers/infiniband/hw/hfi1/tid_rdma.h #define HFI1_R_TID_WAIT_INTERLCK BIT(6) BIT 40 drivers/infiniband/hw/hfi1/tid_rdma.h #define HFI1_S_TID_RETRY_TIMER BIT(17) BIT 42 drivers/infiniband/hw/hfi1/tid_rdma.h #define HFI1_R_TID_SW_PSN BIT(19) BIT 105 drivers/infiniband/hw/hfi1/user_sdma.h #define TXREQ_FLAGS_REQ_ACK BIT(0) /* Set the ACK bit in the header */ BIT 106 drivers/infiniband/hw/hfi1/user_sdma.h #define TXREQ_FLAGS_REQ_DISABLE_SH BIT(1) /* Disable header suppression */ BIT 287 drivers/infiniband/hw/hfi1/verbs.c static const u32 pio_opmask[BIT(3)] = { BIT 290 drivers/infiniband/hw/hfi1/verbs.c BIT(RC_OP(SEND_ONLY) & OPMASK) | BIT 291 drivers/infiniband/hw/hfi1/verbs.c BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) | BIT 292 drivers/infiniband/hw/hfi1/verbs.c BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) | BIT 293 drivers/infiniband/hw/hfi1/verbs.c BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) | BIT 294 drivers/infiniband/hw/hfi1/verbs.c BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) | BIT 295 drivers/infiniband/hw/hfi1/verbs.c BIT(RC_OP(ACKNOWLEDGE) & OPMASK) | BIT 296 drivers/infiniband/hw/hfi1/verbs.c BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) | BIT 297 drivers/infiniband/hw/hfi1/verbs.c BIT(RC_OP(COMPARE_SWAP) & OPMASK) | BIT 298 drivers/infiniband/hw/hfi1/verbs.c BIT(RC_OP(FETCH_ADD) & OPMASK), BIT 301 drivers/infiniband/hw/hfi1/verbs.c BIT(UC_OP(SEND_ONLY) & OPMASK) | BIT 302 drivers/infiniband/hw/hfi1/verbs.c BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) | BIT 303 drivers/infiniband/hw/hfi1/verbs.c BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) | BIT 304 drivers/infiniband/hw/hfi1/verbs.c BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK), BIT 1235 drivers/infiniband/hw/hfi1/verbs.c (BIT(ps->opcode & OPMASK) & pio_opmask[ps->opcode >> 5]) && BIT 100 drivers/infiniband/hw/hfi1/verbs.h #define OPA_BTH_MIG_REQ BIT(31) BIT 55 drivers/infiniband/hw/hfi1/vnic_sdma.c #define HFI1_VNIC_SDMA_Q_ACTIVE BIT(0) BIT 56 drivers/infiniband/hw/hfi1/vnic_sdma.c #define HFI1_VNIC_SDMA_Q_DEFERRED BIT(1) BIT 215 drivers/infiniband/hw/hns/hns_roce_device.h HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), BIT 216 drivers/infiniband/hw/hns/hns_roce_device.h HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), BIT 217 drivers/infiniband/hw/hns/hns_roce_device.h HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), BIT 218 drivers/infiniband/hw/hns/hns_roce_device.h HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), BIT 219 drivers/infiniband/hw/hns/hns_roce_device.h HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), BIT 220 drivers/infiniband/hw/hns/hns_roce_device.h HNS_ROCE_CAP_FLAG_SRQ = BIT(5), BIT 221 drivers/infiniband/hw/hns/hns_roce_device.h HNS_ROCE_CAP_FLAG_MW = BIT(7), BIT 222 drivers/infiniband/hw/hns/hns_roce_device.h HNS_ROCE_CAP_FLAG_FRMR = BIT(8), BIT 223 drivers/infiniband/hw/hns/hns_roce_device.h HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), BIT 224 drivers/infiniband/hw/hns/hns_roce_device.h HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), BIT 5217 drivers/infiniband/hw/hns/hns_roce_hw_v2.c if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { BIT 5238 drivers/infiniband/hw/hns/hns_roce_hw_v2.c } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) { BIT 5248 drivers/infiniband/hw/hns/hns_roce_hw_v2.c } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) { BIT 124 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT) BIT 125 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT) BIT 126 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT) BIT 127 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT) BIT 128 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT) BIT 129 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT) BIT 140 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT) BIT 62 drivers/infiniband/hw/mlx5/ah.c #define MLX5_ECN_ENABLED BIT(1) BIT 64 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_CLAMP_TGT_RATE_ATTR BIT(1) BIT 65 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_CLAMP_TGT_RATE_ATI_ATTR BIT(2) BIT 66 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_TIME_RESET_ATTR BIT(3) BIT 67 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_BYTE_RESET_ATTR BIT(4) BIT 68 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_THRESHOLD_ATTR BIT(5) BIT 69 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_AI_RATE_ATTR BIT(7) BIT 70 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_HAI_RATE_ATTR BIT(8) BIT 71 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_MIN_DEC_FAC_ATTR BIT(9) BIT 72 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_MIN_RATE_ATTR BIT(10) BIT 73 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_RATE_TO_SET_ON_FIRST_CNP_ATTR BIT(11) BIT 74 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_DCE_TCP_G_ATTR BIT(12) BIT 75 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_DCE_TCP_RTT_ATTR BIT(13) BIT 76 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_RATE_REDUCE_MONITOR_PERIOD_ATTR BIT(14) BIT 77 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_INITIAL_ALPHA_VALUE_ATTR BIT(15) BIT 78 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_RP_GD_ATTR BIT(16) BIT 80 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_NP_CNP_DSCP_ATTR BIT(3) BIT 81 drivers/infiniband/hw/mlx5/cong.c #define MLX5_IB_NP_CNP_PRIO_MODE_ATTR BIT(4) BIT 188 drivers/infiniband/hw/mlx5/flow.c if (flow_context.flow_tag >= BIT(24)) { BIT 1152 drivers/infiniband/hw/mlx5/main.c BIT(IB_QPT_RAW_PACKET); BIT 1169 drivers/infiniband/hw/mlx5/main.c BIT(IB_QPT_RAW_PACKET); BIT 1910 drivers/infiniband/hw/mlx5/main.c resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); BIT 3001 drivers/infiniband/hw/mlx5/main.c if (ib_spec->flow_tag.tag_id >= BIT(24)) BIT 3235 drivers/infiniband/hw/mlx5/main.c #define MLX5_FS_MAX_ENTRIES BIT(16) BIT 3272 drivers/infiniband/hw/mlx5/main.c max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, BIT 3297 drivers/infiniband/hw/mlx5/main.c BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, BIT 3948 drivers/infiniband/hw/mlx5/main.c max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, BIT 3957 drivers/infiniband/hw/mlx5/main.c max_table_size = BIT( BIT 3962 drivers/infiniband/hw/mlx5/main.c max_table_size = BIT( BIT 3972 drivers/infiniband/hw/mlx5/main.c BIT(MLX5_CAP_FLOWTABLE_RDMA_RX(dev->mdev, BIT 107 drivers/infiniband/hw/mlx5/mlx5_ib.h MLX5_IB_INVALID_UAR_INDEX = BIT(31), BIT 108 drivers/infiniband/hw/mlx5/mlx5_ib.h MLX5_IB_INVALID_BFREG = BIT(31), BIT 237 drivers/infiniband/hw/mlx5/mlx5_ib.h #define MLX5_IB_UPD_XLT_ZAP BIT(0) BIT 238 drivers/infiniband/hw/mlx5/mlx5_ib.h #define MLX5_IB_UPD_XLT_ENABLE BIT(1) BIT 239 drivers/infiniband/hw/mlx5/mlx5_ib.h #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) BIT 240 drivers/infiniband/hw/mlx5/mlx5_ib.h #define MLX5_IB_UPD_XLT_ADDR BIT(3) BIT 241 drivers/infiniband/hw/mlx5/mlx5_ib.h #define MLX5_IB_UPD_XLT_PD BIT(4) BIT 242 drivers/infiniband/hw/mlx5/mlx5_ib.h #define MLX5_IB_UPD_XLT_ACCESS BIT(5) BIT 243 drivers/infiniband/hw/mlx5/mlx5_ib.h #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) BIT 280 drivers/infiniband/hw/mlx5/odp.c for (addr = start; addr < end; addr += BIT(umem_odp->page_shift)) { BIT 609 drivers/infiniband/hw/mlx5/odp.c #define MLX5_PF_FLAGS_PREFETCH BIT(0) BIT 610 drivers/infiniband/hw/mlx5/odp.c #define MLX5_PF_FLAGS_DOWNGRADE BIT(1) BIT 638 drivers/infiniband/hw/mlx5/odp.c page_mask = ~(BIT(page_shift) - 1); BIT 583 drivers/infiniband/hw/ocrdma/ocrdma_hw.c cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE); BIT 584 drivers/infiniband/hw/ocrdma/ocrdma_hw.c cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE); BIT 586 drivers/infiniband/hw/ocrdma/ocrdma_hw.c cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_LINK_EVE_CODE); BIT 263 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MQE_HDR_EMB_MASK = BIT(0), BIT 329 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_EQ_VALID = BIT(29), BIT 370 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MCQE_CONS_MASK = BIT(27), BIT 372 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MCQE_CMPL_MASK = BIT(28), BIT 374 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MCQE_AE_MASK = BIT(30), BIT 376 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MCQE_VALID_MASK = BIT(31) BIT 387 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_AE_MCQE_QPVALID = BIT(31), BIT 390 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_AE_MCQE_CQVALID = BIT(31), BIT 392 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_AE_MCQE_VALID = BIT(31), BIT 393 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_AE_MCQE_AE = BIT(30), BIT 434 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = BIT(30), BIT 436 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = BIT(31) BIT 460 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = BIT(30), BIT 462 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = BIT(31) BIT 540 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = BIT(2), BIT 542 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = BIT(3), BIT 768 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_CQ_COALESCWM_MASK = BIT(13) | BIT(12), BIT 769 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_CQ_FLAGS_NODELAY = BIT(14), BIT 770 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = BIT(15), BIT 783 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_CQ_FLAGS_VALID = BIT(29), BIT 784 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = BIT(31), BIT 827 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_MQ_VALID = BIT(31), BIT 828 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = BIT(0) BIT 879 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_REQ_QPT_MASK = BIT(31) | BIT(30) | BIT(29), BIT 894 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = BIT(0), BIT 896 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = BIT(1), BIT 898 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = BIT(2), BIT 900 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = BIT(3), BIT 902 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = BIT(4), BIT 904 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = BIT(5), BIT 906 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = BIT(6), BIT 908 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = BIT(7), BIT 910 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = BIT(8), BIT 1023 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = BIT(0), BIT 1060 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_QPS_VALID = BIT(0), BIT 1061 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_SQD_ASYNC_VALID = BIT(1), BIT 1062 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_PKEY_VALID = BIT(2), BIT 1063 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_QKEY_VALID = BIT(3), BIT 1064 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_PMTU_VALID = BIT(4), BIT 1065 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_ACK_TO_VALID = BIT(5), BIT 1066 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_RETRY_CNT_VALID = BIT(6), BIT 1067 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_RRC_VALID = BIT(7), BIT 1068 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_RQPSN_VALID = BIT(8), BIT 1069 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_MAX_IRD_VALID = BIT(9), BIT 1070 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_MAX_ORD_VALID = BIT(10), BIT 1071 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_RNT_VALID = BIT(11), BIT 1072 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_SQPSN_VALID = BIT(12), BIT 1073 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_DST_QPN_VALID = BIT(13), BIT 1074 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_MAX_WQE_VALID = BIT(14), BIT 1075 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_MAX_RQE_VALID = BIT(15), BIT 1076 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_SGE_SEND_VALID = BIT(16), BIT 1077 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_SGE_RECV_VALID = BIT(17), BIT 1078 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_SGE_WR_VALID = BIT(18), BIT 1079 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_INB_RDEN_VALID = BIT(19), BIT 1080 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_INB_WREN_VALID = BIT(20), BIT 1081 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_FLOW_LBL_VALID = BIT(21), BIT 1082 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_BIND_EN_VALID = BIT(22), BIT 1083 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_ZLKEY_EN_VALID = BIT(23), BIT 1084 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_FMR_EN_VALID = BIT(24), BIT 1085 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_INBAT_EN_VALID = BIT(25), BIT 1086 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARA_VLAN_EN_VALID = BIT(26), BIT 1088 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MODIFY_QP_FLAGS_RD = BIT(0), BIT 1089 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MODIFY_QP_FLAGS_WR = BIT(1), BIT 1090 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MODIFY_QP_FLAGS_SEND = BIT(2), BIT 1091 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_MODIFY_QP_FLAGS_ATOMIC = BIT(3) BIT 1110 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARAMS_FLAGS_FMR_EN = BIT(0), BIT 1111 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = BIT(1), BIT 1112 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = BIT(2), BIT 1113 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = BIT(3), BIT 1114 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = BIT(4), BIT 1116 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARAMS_STATE_MASK = BIT(5) | BIT(6) | BIT(7), BIT 1117 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = BIT(8), BIT 1118 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = BIT(9), BIT 1120 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_MASK = BIT(11) | BIT(12) | BIT(13), BIT 1366 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16), BIT 1377 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_ALLOC_PD_RSP_DPP = BIT(16), BIT 1440 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = BIT(0), BIT 1442 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_ALLOC_LKEY_FMR_MASK = BIT(1), BIT 1444 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = BIT(2), BIT 1446 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = BIT(3), BIT 1448 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = BIT(4), BIT 1450 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = BIT(5), BIT 1451 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = BIT(6), BIT 1510 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = BIT(24), BIT 1512 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_REG_NSMR_ZB_SHIFT_MASK = BIT(25), BIT 1514 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_REG_NSMR_REMOTE_INV_MASK = BIT(26), BIT 1516 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_REG_NSMR_REMOTE_WR_MASK = BIT(27), BIT 1518 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_REG_NSMR_REMOTE_RD_MASK = BIT(28), BIT 1520 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_REG_NSMR_LOCAL_WR_MASK = BIT(29), BIT 1522 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = BIT(30), BIT 1524 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_REG_NSMR_LAST_MASK = BIT(31) BIT 1551 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_REG_NSMR_CONT_LAST_MASK = BIT(31) BIT 1697 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_EQE_VALID_MASK = BIT(0), BIT 1767 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CQE_VALID = BIT(31), BIT 1768 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CQE_INVALIDATE = BIT(30), BIT 1769 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CQE_QTYPE = BIT(29), BIT 1770 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CQE_IMM = BIT(28), BIT 1771 drivers/infiniband/hw/ocrdma/ocrdma_sli.h OCRDMA_CQE_WRITE_IMM = BIT(27), BIT 1915 drivers/infiniband/hw/ocrdma/ocrdma_sli.h #define OCRDMA_AV_VALID BIT(7) BIT 1916 drivers/infiniband/hw/ocrdma/ocrdma_sli.h #define OCRDMA_AV_VLAN_VALID BIT(1) BIT 388 drivers/infiniband/hw/qedr/qedr.h QEDR_IWARP_CM_WAIT_FOR_CONNECT = BIT(0), BIT 389 drivers/infiniband/hw/qedr/qedr.h QEDR_IWARP_CM_WAIT_FOR_DISCONNECT = BIT(1), BIT 631 drivers/infiniband/hw/qedr/verbs.c fw_pg_per_umem_pg = BIT(PAGE_SHIFT - pg_shift); BIT 639 drivers/infiniband/hw/qedr/verbs.c pg_addr += BIT(pg_shift); BIT 67 drivers/infiniband/hw/qib/qib_qp.c .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), BIT 72 drivers/infiniband/hw/qib/qib_qp.c .qpt_support = BIT(IB_QPT_RC), BIT 78 drivers/infiniband/hw/qib/qib_qp.c .qpt_support = BIT(IB_QPT_RC), BIT 84 drivers/infiniband/hw/qib/qib_qp.c .qpt_support = BIT(IB_QPT_RC), BIT 90 drivers/infiniband/hw/qib/qib_qp.c .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC), BIT 95 drivers/infiniband/hw/qib/qib_qp.c .qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) | BIT 96 drivers/infiniband/hw/qib/qib_qp.c BIT(IB_QPT_UC) | BIT(IB_QPT_RC), BIT 101 drivers/infiniband/hw/qib/qib_qp.c .qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) | BIT 102 drivers/infiniband/hw/qib/qib_qp.c BIT(IB_QPT_UC) | BIT(IB_QPT_RC), BIT 100 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_CQ_FLAG_ARMED_SOL BIT(0) /* Armed for solicited-only. */ BIT 101 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_CQ_FLAG_ARMED BIT(1) /* Armed. */ BIT 102 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_MR_FLAG_DMA BIT(0) /* DMA region. */ BIT 103 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_MR_FLAG_FRMR BIT(1) /* Fast reg memory region. */ BIT 110 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_ATOMIC_OP_COMP_SWAP BIT(0) /* Compare and swap. */ BIT 111 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_ATOMIC_OP_FETCH_ADD BIT(1) /* Fetch and add. */ BIT 112 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_ATOMIC_OP_MASK_COMP_SWAP BIT(2) /* Masked compare and swap. */ BIT 113 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_ATOMIC_OP_MASK_FETCH_ADD BIT(3) /* Masked fetch and add. */ BIT 121 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_BMME_FLAG_LOCAL_INV BIT(0) /* Local Invalidate. */ BIT 122 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_BMME_FLAG_REMOTE_INV BIT(1) /* Remote Invalidate. */ BIT 123 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_BMME_FLAG_FAST_REG_WR BIT(2) /* Fast Reg Work Request. */ BIT 132 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_GID_TYPE_FLAG_ROCE_V1 BIT(0) BIT 133 drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h #define PVRDMA_GID_TYPE_FLAG_ROCE_V2 BIT(1) BIT 603 drivers/infiniband/sw/rdmavt/qp.c offset & ((BIT(rdi->dparms.qos_shift - 1) - 1) << 1)); BIT 1911 drivers/infiniband/sw/rdmavt/qp.c if (!(post_parms[wr->opcode].qpt_support & BIT(qp->ibqp.qp_type))) BIT 44 drivers/infiniband/sw/rxe/rxe_opcode.h WR_INLINE_MASK = BIT(0), BIT 45 drivers/infiniband/sw/rxe/rxe_opcode.h WR_ATOMIC_MASK = BIT(1), BIT 46 drivers/infiniband/sw/rxe/rxe_opcode.h WR_SEND_MASK = BIT(2), BIT 47 drivers/infiniband/sw/rxe/rxe_opcode.h WR_READ_MASK = BIT(3), BIT 48 drivers/infiniband/sw/rxe/rxe_opcode.h WR_WRITE_MASK = BIT(4), BIT 49 drivers/infiniband/sw/rxe/rxe_opcode.h WR_LOCAL_MASK = BIT(5), BIT 50 drivers/infiniband/sw/rxe/rxe_opcode.h WR_REG_MASK = BIT(6), BIT 84 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_LRH_MASK = BIT(RXE_LRH), BIT 85 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_GRH_MASK = BIT(RXE_GRH), BIT 86 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_BTH_MASK = BIT(RXE_BTH), BIT 87 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_IMMDT_MASK = BIT(RXE_IMMDT), BIT 88 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_RETH_MASK = BIT(RXE_RETH), BIT 89 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_AETH_MASK = BIT(RXE_AETH), BIT 90 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_ATMETH_MASK = BIT(RXE_ATMETH), BIT 91 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_ATMACK_MASK = BIT(RXE_ATMACK), BIT 92 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_IETH_MASK = BIT(RXE_IETH), BIT 93 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_RDETH_MASK = BIT(RXE_RDETH), BIT 94 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_DETH_MASK = BIT(RXE_DETH), BIT 95 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD), BIT 97 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_REQ_MASK = BIT(NUM_HDR_TYPES + 0), BIT 98 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_ACK_MASK = BIT(NUM_HDR_TYPES + 1), BIT 99 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_SEND_MASK = BIT(NUM_HDR_TYPES + 2), BIT 100 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_WRITE_MASK = BIT(NUM_HDR_TYPES + 3), BIT 101 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_READ_MASK = BIT(NUM_HDR_TYPES + 4), BIT 102 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_ATOMIC_MASK = BIT(NUM_HDR_TYPES + 5), BIT 104 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 6), BIT 105 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 7), BIT 107 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_START_MASK = BIT(NUM_HDR_TYPES + 8), BIT 108 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 9), BIT 109 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_END_MASK = BIT(NUM_HDR_TYPES + 10), BIT 111 drivers/infiniband/sw/rxe/rxe_opcode.h RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12), BIT 41 drivers/infiniband/sw/rxe/rxe_pool.h RXE_POOL_ATOMIC = BIT(0), BIT 42 drivers/infiniband/sw/rxe/rxe_pool.h RXE_POOL_INDEX = BIT(1), BIT 43 drivers/infiniband/sw/rxe/rxe_pool.h RXE_POOL_KEY = BIT(2), BIT 44 drivers/infiniband/sw/rxe/rxe_pool.h RXE_POOL_NO_ALLOC = BIT(4), BIT 402 drivers/infiniband/sw/siw/siw_qp_tx.c if (kmap_mask & BIT(0)) BIT 512 drivers/infiniband/sw/siw/siw_qp_tx.c kmap_mask |= BIT(seg); BIT 271 drivers/infiniband/ulp/opa_vnic/opa_vnic_internal.h #define OPA_VNIC_MAC_TBL_SIZE BIT(OPA_VNIC_MAC_TBL_HASH_BITS) BIT 136 drivers/input/joystick/iforce/iforce-packets.c if (btns & BIT(3)) BIT 138 drivers/input/joystick/iforce/iforce-packets.c else if (btns & BIT(1)) BIT 145 drivers/input/joystick/iforce/iforce-packets.c if (btns & BIT(0)) BIT 147 drivers/input/joystick/iforce/iforce-packets.c else if (btns & BIT(2)) BIT 235 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_DPAD_UP, b_rsp3 & BIT(3)); BIT 236 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_DPAD_DOWN, b_rsp3 & BIT(1)); BIT 237 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_DPAD_LEFT, b_rsp3 & BIT(0)); BIT 238 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_DPAD_RIGHT, b_rsp3 & BIT(2)); BIT 239 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_X, b_rsp4 & BIT(3)); BIT 240 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_A, b_rsp4 & BIT(2)); BIT 241 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_B, b_rsp4 & BIT(1)); BIT 242 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_Y, b_rsp4 & BIT(0)); BIT 243 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_TL, b_rsp4 & BIT(5)); BIT 244 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_TR, b_rsp4 & BIT(4)); BIT 245 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_TL2, b_rsp4 & BIT(7)); BIT 246 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_TR2, b_rsp4 & BIT(6)); BIT 247 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_THUMBL, b_rsp3 & BIT(6)); BIT 248 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_THUMBR, b_rsp3 & BIT(5)); BIT 249 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_SELECT, b_rsp3 & BIT(7)); BIT 250 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_START, b_rsp3 & BIT(4)); BIT 262 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_DPAD_UP, b_rsp3 & BIT(3)); BIT 263 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_DPAD_DOWN, b_rsp3 & BIT(1)); BIT 264 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_DPAD_LEFT, b_rsp3 & BIT(0)); BIT 265 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_DPAD_RIGHT, b_rsp3 & BIT(2)); BIT 266 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_X, b_rsp4 & BIT(3)); BIT 267 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_A, b_rsp4 & BIT(2)); BIT 268 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_B, b_rsp4 & BIT(1)); BIT 269 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_Y, b_rsp4 & BIT(0)); BIT 270 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_TL, b_rsp4 & BIT(5)); BIT 271 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_TR, b_rsp4 & BIT(4)); BIT 272 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_TL2, b_rsp4 & BIT(7)); BIT 273 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_TR2, b_rsp4 & BIT(6)); BIT 276 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_SELECT, b_rsp3 & BIT(7)); BIT 277 drivers/input/joystick/psxpad-spi.c input_report_key(input, BTN_START, b_rsp3 & BIT(4)); BIT 257 drivers/input/joystick/walkera0701.c w->input_dev->evbit[0] = BIT(EV_ABS) | BIT_MASK(EV_KEY); BIT 153 drivers/input/joystick/zhenhua.c input_dev->evbit[0] = BIT(EV_ABS); BIT 1108 drivers/input/keyboard/applespi.c u8 bit = BIT((fnremap - 1) & 0x07); BIT 1168 drivers/input/keyboard/applespi.c if (keyboard_protocol->modifiers & BIT(i)) BIT 13 drivers/input/keyboard/applespi.h ET_CMD_TP_INI = BIT(0), BIT 14 drivers/input/keyboard/applespi.h ET_CMD_BL = BIT(1), BIT 15 drivers/input/keyboard/applespi.h ET_CMD_CL = BIT(2), BIT 16 drivers/input/keyboard/applespi.h ET_RD_KEYB = BIT(8), BIT 17 drivers/input/keyboard/applespi.h ET_RD_TPAD = BIT(9), BIT 18 drivers/input/keyboard/applespi.h ET_RD_UNKN = BIT(10), BIT 19 drivers/input/keyboard/applespi.h ET_RD_IRQ = BIT(11), BIT 20 drivers/input/keyboard/applespi.h ET_RD_CRC = BIT(12), BIT 119 drivers/input/keyboard/bcm-keypad.c key_press = state & BIT(bit_nr); BIT 21 drivers/input/keyboard/cap11xx.c #define CAP11XX_REG_MAIN_CONTROL_DLSEEP BIT(4) BIT 46 drivers/input/keyboard/cap11xx.c #define CAP11XX_REG_CONFIG2_ALT_POL BIT(6) BIT 244 drivers/input/keyboard/cap11xx.c BIT(led->reg), BIT 245 drivers/input/keyboard/cap11xx.c value ? BIT(led->reg) : 0); BIT 219 drivers/input/keyboard/cros_ec_keyb.c !!(mask & BIT(map->bit)) ^ map->inverted); BIT 498 drivers/input/keyboard/cros_ec_keyb.c if ((map->ev_type == EV_KEY && (buttons & BIT(map->bit))) || BIT 499 drivers/input/keyboard/cros_ec_keyb.c (map->ev_type == EV_SW && (switches & BIT(map->bit)))) BIT 207 drivers/input/keyboard/jornada680_kbd.c input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_REP); BIT 109 drivers/input/keyboard/jornada720_kbd.c input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_REP); BIT 709 drivers/input/keyboard/lm8323.c idev->evbit[0] = BIT(EV_KEY) | BIT(EV_MSC); BIT 173 drivers/input/keyboard/maple_keyb.c idev->evbit[0] = BIT(EV_KEY) | BIT(EV_REP); BIT 147 drivers/input/keyboard/mpr121_touchkey.c pressed = reg & BIT(key_num); BIT 41 drivers/input/keyboard/omap4-keypad.c #define OMAP4_DEF_IRQENABLE_EVENTEN BIT(0) BIT 42 drivers/input/keyboard/omap4-keypad.c #define OMAP4_DEF_IRQENABLE_LONGKEY BIT(1) BIT 43 drivers/input/keyboard/omap4-keypad.c #define OMAP4_DEF_WUP_EVENT_ENA BIT(0) BIT 44 drivers/input/keyboard/omap4-keypad.c #define OMAP4_DEF_WUP_LONG_KEY_ENA BIT(1) BIT 45 drivers/input/keyboard/omap4-keypad.c #define OMAP4_DEF_CTRL_NOSOFTMODE BIT(1) BIT 38 drivers/input/keyboard/pmic8xxx-keypad.c #define KEYP_CTRL_EVNTS BIT(0) BIT 49 drivers/input/keyboard/pmic8xxx-keypad.c #define KEYP_CTRL_KEYP_EN BIT(7) BIT 53 drivers/input/keyboard/pmic8xxx-keypad.c #define KEYP_SCAN_READ_STATE BIT(0) BIT 60 drivers/input/keyboard/pmic8xxx-keypad.c #define KEYP_TEST_CLEAR_RECENT_SCAN BIT(6) BIT 61 drivers/input/keyboard/pmic8xxx-keypad.c #define KEYP_TEST_CLEAR_OLD_SCAN BIT(5) BIT 62 drivers/input/keyboard/pmic8xxx-keypad.c #define KEYP_TEST_READ_RESET BIT(4) BIT 63 drivers/input/keyboard/pmic8xxx-keypad.c #define KEYP_TEST_DTEST_EN BIT(3) BIT 64 drivers/input/keyboard/pmic8xxx-keypad.c #define KEYP_TEST_ABORT_READ BIT(0) BIT 92 drivers/input/keyboard/qt1050.c #define QT1050_RES_CAL_RESET BIT(7) BIT 93 drivers/input/keyboard/qt1050.c #define QT1050_RES_CAL_CALIBRATE BIT(1) BIT 298 drivers/input/keyboard/qt1050.c on ? BIT(4) : 0x00); BIT 374 drivers/input/keyboard/qt1050.c ts->reg_keys |= BIT(button.num); BIT 82 drivers/input/keyboard/qt2160.c drive |= BIT(led->id); BIT 83 drivers/input/keyboard/qt2160.c pwmen |= BIT(led->id); BIT 86 drivers/input/keyboard/qt2160.c drive &= ~BIT(led->id); BIT 87 drivers/input/keyboard/qt2160.c pwmen &= ~BIT(led->id); BIT 25 drivers/input/keyboard/snvs_pwrkey.c #define SNVS_HPSR_BTN BIT(6) BIT 26 drivers/input/keyboard/snvs_pwrkey.c #define SNVS_LPSR_SPO BIT(18) BIT 27 drivers/input/keyboard/snvs_pwrkey.c #define SNVS_LPCR_DEP_EN BIT(5) BIT 52 drivers/input/keyboard/st-keyscan.c keycode[bit_nr], state & BIT(bit_nr)); BIT 47 drivers/input/keyboard/sun4i-lradc-keys.c #define CHAN1_KEYUP_IRQ BIT(12) BIT 48 drivers/input/keyboard/sun4i-lradc-keys.c #define CHAN1_ALRDY_HOLD_IRQ BIT(11) BIT 49 drivers/input/keyboard/sun4i-lradc-keys.c #define CHAN1_HOLD_IRQ BIT(10) BIT 50 drivers/input/keyboard/sun4i-lradc-keys.c #define CHAN1_KEYDOWN_IRQ BIT(9) BIT 51 drivers/input/keyboard/sun4i-lradc-keys.c #define CHAN1_DATA_IRQ BIT(8) BIT 52 drivers/input/keyboard/sun4i-lradc-keys.c #define CHAN0_KEYUP_IRQ BIT(4) BIT 53 drivers/input/keyboard/sun4i-lradc-keys.c #define CHAN0_ALRDY_HOLD_IRQ BIT(3) BIT 54 drivers/input/keyboard/sun4i-lradc-keys.c #define CHAN0_HOLD_IRQ BIT(2) BIT 55 drivers/input/keyboard/sun4i-lradc-keys.c #define CHAN0_KEYDOWN_IRQ BIT(1) BIT 56 drivers/input/keyboard/sun4i-lradc-keys.c #define CHAN0_DATA_IRQ BIT(0) BIT 92 drivers/input/keyboard/tca8418_keypad.c #define CFG_AI BIT(7) BIT 93 drivers/input/keyboard/tca8418_keypad.c #define CFG_GPI_E_CFG BIT(6) BIT 94 drivers/input/keyboard/tca8418_keypad.c #define CFG_OVR_FLOW_M BIT(5) BIT 95 drivers/input/keyboard/tca8418_keypad.c #define CFG_INT_CFG BIT(4) BIT 96 drivers/input/keyboard/tca8418_keypad.c #define CFG_OVR_FLOW_IEN BIT(3) BIT 97 drivers/input/keyboard/tca8418_keypad.c #define CFG_K_LCK_IEN BIT(2) BIT 98 drivers/input/keyboard/tca8418_keypad.c #define CFG_GPI_IEN BIT(1) BIT 99 drivers/input/keyboard/tca8418_keypad.c #define CFG_KE_IEN BIT(0) BIT 101 drivers/input/keyboard/tca8418_keypad.c #define INT_STAT_CAD_INT BIT(4) BIT 102 drivers/input/keyboard/tca8418_keypad.c #define INT_STAT_OVR_FLOW_INT BIT(3) BIT 103 drivers/input/keyboard/tca8418_keypad.c #define INT_STAT_K_LCK_INT BIT(2) BIT 104 drivers/input/keyboard/tca8418_keypad.c #define INT_STAT_GPI_INT BIT(1) BIT 105 drivers/input/keyboard/tca8418_keypad.c #define INT_STAT_K_INT BIT(0) BIT 32 drivers/input/keyboard/tm2-touchkey.c #define TM2_TOUCHKEY_BIT_PRESS_EV BIT(3) BIT 91 drivers/input/keyboard/twl4030_keypad.c #define KEYP_CTRL_SOFT_NRST BIT(0) BIT 92 drivers/input/keyboard/twl4030_keypad.c #define KEYP_CTRL_SOFTMODEN BIT(1) BIT 93 drivers/input/keyboard/twl4030_keypad.c #define KEYP_CTRL_LK_EN BIT(2) BIT 94 drivers/input/keyboard/twl4030_keypad.c #define KEYP_CTRL_TOE_EN BIT(3) BIT 95 drivers/input/keyboard/twl4030_keypad.c #define KEYP_CTRL_TOLE_EN BIT(4) BIT 96 drivers/input/keyboard/twl4030_keypad.c #define KEYP_CTRL_RP_EN BIT(5) BIT 97 drivers/input/keyboard/twl4030_keypad.c #define KEYP_CTRL_KBD_ON BIT(6) BIT 106 drivers/input/keyboard/twl4030_keypad.c #define KEYP_IMR1_MIS BIT(3) BIT 107 drivers/input/keyboard/twl4030_keypad.c #define KEYP_IMR1_TO BIT(2) BIT 108 drivers/input/keyboard/twl4030_keypad.c #define KEYP_IMR1_LK BIT(1) BIT 109 drivers/input/keyboard/twl4030_keypad.c #define KEYP_IMR1_KP BIT(0) BIT 16 drivers/input/misc/ad714x-spi.c #define AD714x_SPI_READ BIT(10) BIT 149 drivers/input/misc/atmel_captouch.c if (changed_btn & BIT(i)) BIT 152 drivers/input/misc/atmel_captouch.c new_btn & BIT(i)); BIT 368 drivers/input/misc/axp20x-pek.c BIT(AXP288_IRQ_POKN % 8)); BIT 325 drivers/input/misc/cm109.c keycode = dev->keymap[0xff + BIT(i)]; BIT 329 drivers/input/misc/cm109.c input_report_key(idev, keycode, data & BIT(i)); BIT 330 drivers/input/misc/cm109.c if (data & autorelease & BIT(i)) { BIT 25 drivers/input/misc/drv2665.c #define DRV2665_FIFO_FULL BIT(0) BIT 26 drivers/input/misc/drv2665.c #define DRV2665_FIFO_EMPTY BIT(1) BIT 34 drivers/input/misc/drv2665.c #define DRV2665_ANALOG_IN BIT(2) BIT 37 drivers/input/misc/drv2665.c #define DRV2665_BOOST_EN BIT(1) BIT 38 drivers/input/misc/drv2665.c #define DRV2665_STANDBY BIT(6) BIT 39 drivers/input/misc/drv2665.c #define DRV2665_DEV_RST BIT(7) BIT 16 drivers/input/misc/max77650-onkey.c #define MAX77650_ONKEY_MODE_MASK BIT(3) BIT 18 drivers/input/misc/max77650-onkey.c #define MAX77650_ONKEY_MODE_SLIDE BIT(3) BIT 74 drivers/input/misc/palmas-pwrbutton.c } else if (reg & BIT(1)) { BIT 73 drivers/input/misc/pcf50633-input.c input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR); BIT 23 drivers/input/misc/pm8941-pwrkey.c #define PON_KPDPWR_N_SET BIT(0) BIT 24 drivers/input/misc/pm8941-pwrkey.c #define PON_RESIN_N_SET BIT(1) BIT 28 drivers/input/misc/pm8941-pwrkey.c #define PON_PS_HOLD_ENABLE BIT(7) BIT 34 drivers/input/misc/pm8941-pwrkey.c #define PON_KPDPWR_PULL_UP BIT(1) BIT 35 drivers/input/misc/pm8941-pwrkey.c #define PON_RESIN_PULL_UP BIT(0) BIT 40 drivers/input/misc/pm8xxx-vibrator.c .enable_mask = BIT(7), BIT 18 drivers/input/misc/pmic8xxx-pwrkey.c #define PON_CNTL_PULL_UP BIT(7) BIT 291 drivers/input/misc/pmic8xxx-pwrkey.c REG_PM8058_VREG_EN_MSM, BIT(7)); BIT 294 drivers/input/misc/pmic8xxx-pwrkey.c REG_PM8058_VREG_EN_MSM, BIT(6)); BIT 297 drivers/input/misc/pmic8xxx-pwrkey.c REG_PM8058_VREG_EN_GRP_5_4, BIT(7) | BIT(4)); BIT 301 drivers/input/misc/pmic8xxx-pwrkey.c BIT(1)); BIT 14 drivers/input/misc/sc27xx-vibra.c #define SLP_LDOVIBR_PD_EN BIT(9) BIT 15 drivers/input/misc/sc27xx-vibra.c #define LDO_VIBR_PD BIT(8) BIT 715 drivers/input/mouse/alps.c f->y_map = palm_data & (BIT(priv->y_bits) - 1); BIT 719 drivers/input/mouse/alps.c (BIT(priv->x_bits) - 1); BIT 883 drivers/input/mouse/alps.c packet[3] &= ~BIT(2); BIT 2206 drivers/input/mouse/alps.c reg_val |= BIT(1); BIT 189 drivers/input/mouse/appletouch.c ATP_STATUS_BUTTON = BIT(0), BIT 190 drivers/input/mouse/appletouch.c ATP_STATUS_BASE_UPDATE = BIT(2), BIT 191 drivers/input/mouse/appletouch.c ATP_STATUS_FROM_RESET = BIT(4), BIT 963 drivers/input/mouse/elan_i2c_core.c input_report_key(input, BTN_LEFT, tp_info & BIT(0)); BIT 964 drivers/input/mouse/elan_i2c_core.c input_report_key(input, BTN_MIDDLE, tp_info & BIT(2)); BIT 965 drivers/input/mouse/elan_i2c_core.c input_report_key(input, BTN_RIGHT, tp_info & BIT(1)); BIT 24 drivers/input/mouse/logips2pp.c #define PS2PP_WHEEL BIT(0) BIT 25 drivers/input/mouse/logips2pp.c #define PS2PP_HWHEEL BIT(1) BIT 26 drivers/input/mouse/logips2pp.c #define PS2PP_SIDE_BTN BIT(2) BIT 27 drivers/input/mouse/logips2pp.c #define PS2PP_EXTRA_BTN BIT(3) BIT 28 drivers/input/mouse/logips2pp.c #define PS2PP_TASK_BTN BIT(4) BIT 29 drivers/input/mouse/logips2pp.c #define PS2PP_NAV_BTN BIT(5) BIT 63 drivers/input/mouse/logips2pp.c input_report_key(dev, BTN_SIDE, packet[2] & BIT(4)); BIT 64 drivers/input/mouse/logips2pp.c input_report_key(dev, BTN_EXTRA, packet[2] & BIT(5)); BIT 70 drivers/input/mouse/logips2pp.c input_report_key(dev, BTN_SIDE, packet[2] & BIT(0)); BIT 71 drivers/input/mouse/logips2pp.c input_report_key(dev, BTN_EXTRA, packet[2] & BIT(1)); BIT 72 drivers/input/mouse/logips2pp.c input_report_key(dev, BTN_TASK, packet[2] & BIT(2)); BIT 73 drivers/input/mouse/logips2pp.c input_report_key(dev, BTN_BACK, packet[2] & BIT(3)); BIT 74 drivers/input/mouse/logips2pp.c input_report_key(dev, BTN_FORWARD, packet[2] & BIT(4)); BIT 83 drivers/input/mouse/logips2pp.c packet[0] = packet[2] | BIT(3); BIT 123 drivers/input/mouse/psmouse-base.c input_report_key(dev, BTN_LEFT, buttons & BIT(0)); BIT 124 drivers/input/mouse/psmouse-base.c input_report_key(dev, BTN_MIDDLE, buttons & BIT(2)); BIT 125 drivers/input/mouse/psmouse-base.c input_report_key(dev, BTN_RIGHT, buttons & BIT(1)); BIT 191 drivers/input/mouse/psmouse-base.c input_report_key(dev, BTN_SIDE, packet[3] & BIT(4)); BIT 192 drivers/input/mouse/psmouse-base.c input_report_key(dev, BTN_EXTRA, packet[3] & BIT(5)); BIT 202 drivers/input/mouse/psmouse-base.c input_report_key(dev, BTN_SIDE, packet[0] & BIT(6)); BIT 203 drivers/input/mouse/psmouse-base.c input_report_key(dev, BTN_EXTRA, packet[0] & BIT(7)); BIT 208 drivers/input/mouse/psmouse-base.c input_report_key(dev, BTN_EXTRA, packet[0] & BIT(3)); BIT 222 drivers/input/mouse/psmouse-base.c input_report_key(dev, BTN_SIDE, packet[0] & BIT(3)); BIT 223 drivers/input/mouse/psmouse-base.c packet[0] |= BIT(3); BIT 803 drivers/input/mouse/sentelic.c if (packet[3] & BIT(0)) BIT 805 drivers/input/mouse/sentelic.c if (packet[3] & BIT(1)) BIT 807 drivers/input/mouse/sentelic.c if (packet[3] & BIT(2)) BIT 808 drivers/input/mouse/sentelic.c button_status |= BIT(4);/* horizontal left */ BIT 809 drivers/input/mouse/sentelic.c if (packet[3] & BIT(3)) BIT 810 drivers/input/mouse/sentelic.c button_status |= BIT(5);/* horizontal right */ BIT 17 drivers/input/mouse/sentelic.h #define FSP_BIT_NO_ROTATION BIT(3) BIT 22 drivers/input/mouse/sentelic.h #define FSP_BIT_EN_REG_CLK BIT(5) BIT 25 drivers/input/mouse/sentelic.h #define FSP_BIT_EN_OPC_TAG BIT(7) BIT 31 drivers/input/mouse/sentelic.h #define FSP_BIT_90_DEGREE BIT(0) BIT 32 drivers/input/mouse/sentelic.h #define FSP_BIT_EN_MSID6 BIT(1) BIT 33 drivers/input/mouse/sentelic.h #define FSP_BIT_EN_MSID7 BIT(2) BIT 34 drivers/input/mouse/sentelic.h #define FSP_BIT_EN_MSID8 BIT(3) BIT 35 drivers/input/mouse/sentelic.h #define FSP_BIT_EN_AUTO_MSID8 BIT(5) BIT 36 drivers/input/mouse/sentelic.h #define FSP_BIT_EN_PKT_G0 BIT(6) BIT 39 drivers/input/mouse/sentelic.h #define FSP_BIT_ONPAD_ENABLE BIT(0) BIT 40 drivers/input/mouse/sentelic.h #define FSP_BIT_ONPAD_FBBB BIT(1) BIT 41 drivers/input/mouse/sentelic.h #define FSP_BIT_FIX_VSCR BIT(3) BIT 42 drivers/input/mouse/sentelic.h #define FSP_BIT_FIX_HSCR BIT(5) BIT 43 drivers/input/mouse/sentelic.h #define FSP_BIT_DRAG_LOCK BIT(6) BIT 46 drivers/input/mouse/sentelic.h #define FSP_BIT_SWC1_EN_ABS_1F BIT(0) BIT 47 drivers/input/mouse/sentelic.h #define FSP_BIT_SWC1_EN_GID BIT(1) BIT 48 drivers/input/mouse/sentelic.h #define FSP_BIT_SWC1_EN_ABS_2F BIT(2) BIT 49 drivers/input/mouse/sentelic.h #define FSP_BIT_SWC1_EN_FUP_OUT BIT(3) BIT 50 drivers/input/mouse/sentelic.h #define FSP_BIT_SWC1_EN_ABS_CON BIT(4) BIT 51 drivers/input/mouse/sentelic.h #define FSP_BIT_SWC1_GST_GRP0 BIT(5) BIT 52 drivers/input/mouse/sentelic.h #define FSP_BIT_SWC1_GST_GRP1 BIT(6) BIT 53 drivers/input/mouse/sentelic.h #define FSP_BIT_SWC1_BX_COMPAT BIT(7) BIT 73 drivers/input/mouse/sentelic.h #define FSP_PB0_LBTN BIT(0) BIT 74 drivers/input/mouse/sentelic.h #define FSP_PB0_RBTN BIT(1) BIT 75 drivers/input/mouse/sentelic.h #define FSP_PB0_MBTN BIT(2) BIT 77 drivers/input/mouse/sentelic.h #define FSP_PB0_MUST_SET BIT(3) BIT 78 drivers/input/mouse/sentelic.h #define FSP_PB0_PHY_BTN BIT(4) BIT 79 drivers/input/mouse/sentelic.h #define FSP_PB0_MFMC BIT(5) BIT 937 drivers/input/mouse/synaptics.c hw->ext_buttons & BIT(i)); BIT 939 drivers/input/mouse/synaptics.c hw->ext_buttons & BIT(i + ext_bits)); BIT 25 drivers/input/mouse/synaptics.h #define SYN_BIT_ABSOLUTE_MODE BIT(7) BIT 26 drivers/input/mouse/synaptics.h #define SYN_BIT_HIGH_RATE BIT(6) BIT 27 drivers/input/mouse/synaptics.h #define SYN_BIT_SLEEP_MODE BIT(3) BIT 28 drivers/input/mouse/synaptics.h #define SYN_BIT_DISABLE_GESTURE BIT(2) BIT 29 drivers/input/mouse/synaptics.h #define SYN_BIT_FOUR_BYTE_CLIENT BIT(1) BIT 30 drivers/input/mouse/synaptics.h #define SYN_BIT_W_MODE BIT(0) BIT 33 drivers/input/mouse/synaptics.h #define SYN_MODEL_ROT180(m) ((m) & BIT(23)) BIT 34 drivers/input/mouse/synaptics.h #define SYN_MODEL_PORTRAIT(m) ((m) & BIT(22)) BIT 37 drivers/input/mouse/synaptics.h #define SYN_MODEL_NEWABS(m) ((m) & BIT(7)) BIT 38 drivers/input/mouse/synaptics.h #define SYN_MODEL_PEN(m) ((m) & BIT(6)) BIT 39 drivers/input/mouse/synaptics.h #define SYN_MODEL_SIMPLIC(m) ((m) & BIT(5)) BIT 43 drivers/input/mouse/synaptics.h #define SYN_CAP_EXTENDED(c) ((c) & BIT(23)) BIT 44 drivers/input/mouse/synaptics.h #define SYN_CAP_MIDDLE_BUTTON(c) ((c) & BIT(18)) BIT 45 drivers/input/mouse/synaptics.h #define SYN_CAP_PASS_THROUGH(c) ((c) & BIT(7)) BIT 46 drivers/input/mouse/synaptics.h #define SYN_CAP_SLEEP(c) ((c) & BIT(4)) BIT 47 drivers/input/mouse/synaptics.h #define SYN_CAP_FOUR_BUTTON(c) ((c) & BIT(3)) BIT 48 drivers/input/mouse/synaptics.h #define SYN_CAP_MULTIFINGER(c) ((c) & BIT(1)) BIT 49 drivers/input/mouse/synaptics.h #define SYN_CAP_PALMDETECT(c) ((c) & BIT(0)) BIT 55 drivers/input/mouse/synaptics.h #define SYN_MEXT_CAP_BIT(m) ((m) & BIT(1)) BIT 84 drivers/input/mouse/synaptics.h #define SYN_CAP_CLICKPAD(ex0c) ((ex0c) & BIT(20)) /* 1-button ClickPad */ BIT 85 drivers/input/mouse/synaptics.h #define SYN_CAP_CLICKPAD2BTN(ex0c) ((ex0c) & BIT(8)) /* 2-button ClickPad */ BIT 86 drivers/input/mouse/synaptics.h #define SYN_CAP_MAX_DIMENSIONS(ex0c) ((ex0c) & BIT(17)) BIT 87 drivers/input/mouse/synaptics.h #define SYN_CAP_MIN_DIMENSIONS(ex0c) ((ex0c) & BIT(13)) BIT 88 drivers/input/mouse/synaptics.h #define SYN_CAP_ADV_GESTURE(ex0c) ((ex0c) & BIT(19)) BIT 89 drivers/input/mouse/synaptics.h #define SYN_CAP_REDUCED_FILTERING(ex0c) ((ex0c) & BIT(10)) BIT 90 drivers/input/mouse/synaptics.h #define SYN_CAP_IMAGE_SENSOR(ex0c) ((ex0c) & BIT(11)) BIT 91 drivers/input/mouse/synaptics.h #define SYN_CAP_INTERTOUCH(ex0c) ((ex0c) & BIT(14)) BIT 110 drivers/input/mouse/synaptics.h #define SYN_CAP_EXT_BUTTONS_STICK(ex10) ((ex10) & BIT(16)) BIT 111 drivers/input/mouse/synaptics.h #define SYN_CAP_SECUREPAD(ex10) ((ex10) & BIT(17)) BIT 113 drivers/input/mouse/synaptics.h #define SYN_EXT_BUTTON_STICK_L(eb) (((eb) & BIT(0)) >> 0) BIT 114 drivers/input/mouse/synaptics.h #define SYN_EXT_BUTTON_STICK_M(eb) (((eb) & BIT(1)) >> 1) BIT 115 drivers/input/mouse/synaptics.h #define SYN_EXT_BUTTON_STICK_R(eb) (((eb) & BIT(2)) >> 2) BIT 118 drivers/input/mouse/synaptics.h #define SYN_MODE_ABSOLUTE(m) ((m) & BIT(7)) BIT 119 drivers/input/mouse/synaptics.h #define SYN_MODE_RATE(m) ((m) & BIT(6)) BIT 120 drivers/input/mouse/synaptics.h #define SYN_MODE_BAUD_SLEEP(m) ((m) & BIT(3)) BIT 121 drivers/input/mouse/synaptics.h #define SYN_MODE_DISABLE_GESTURE(m) ((m) & BIT(2)) BIT 122 drivers/input/mouse/synaptics.h #define SYN_MODE_PACKSIZE(m) ((m) & BIT(1)) BIT 123 drivers/input/mouse/synaptics.h #define SYN_MODE_WMODE(m) ((m) & BIT(0)) BIT 582 drivers/input/mousedev.c ps2_data[0] = BIT(3); BIT 583 drivers/input/mousedev.c ps2_data[0] |= ((dx & BIT(7)) >> 3) | ((dy & BIT(7)) >> 2); BIT 193 drivers/input/rmi4/rmi_bus.h #define RMI_DEBUG_CORE BIT(0) BIT 194 drivers/input/rmi4/rmi_bus.h #define RMI_DEBUG_XPORT BIT(1) BIT 195 drivers/input/rmi4/rmi_bus.h #define RMI_DEBUG_FN BIT(2) BIT 196 drivers/input/rmi4/rmi_bus.h #define RMI_DEBUG_2D_SENSOR BIT(3) BIT 759 drivers/input/rmi4/rmi_driver.c if (status & BIT(7)) BIT 769 drivers/input/rmi4/rmi_driver.c if (status & BIT(6)) BIT 29 drivers/input/rmi4/rmi_f01.c #define RMI_F01_QRY1_CUSTOM_MAP BIT(0) BIT 30 drivers/input/rmi4/rmi_f01.c #define RMI_F01_QRY1_NON_COMPLIANT BIT(1) BIT 31 drivers/input/rmi4/rmi_f01.c #define RMI_F01_QRY1_HAS_LTS BIT(2) BIT 32 drivers/input/rmi4/rmi_f01.c #define RMI_F01_QRY1_HAS_SENSOR_ID BIT(3) BIT 33 drivers/input/rmi4/rmi_f01.c #define RMI_F01_QRY1_HAS_CHARGER_INP BIT(4) BIT 34 drivers/input/rmi4/rmi_f01.c #define RMI_F01_QRY1_HAS_ADJ_DOZE BIT(5) BIT 35 drivers/input/rmi4/rmi_f01.c #define RMI_F01_QRY1_HAS_ADJ_DOZE_HOFF BIT(6) BIT 36 drivers/input/rmi4/rmi_f01.c #define RMI_F01_QRY1_HAS_QUERY42 BIT(7) BIT 84 drivers/input/rmi4/rmi_f01.c #define RMI_F01_CTRL0_NOSLEEP_BIT BIT(2) BIT 90 drivers/input/rmi4/rmi_f01.c #define RMI_F01_CTRL0_CHARGER_BIT BIT(5) BIT 97 drivers/input/rmi4/rmi_f01.c #define RMI_F01_CTRL0_REPORTRATE_BIT BIT(6) BIT 103 drivers/input/rmi4/rmi_f01.c #define RMI_F01_CTRL0_CONFIGURED_BIT BIT(7) BIT 196 drivers/input/rmi4/rmi_f01.c has_ds4_queries = !!(queries[0] & BIT(0)); BIT 218 drivers/input/rmi4/rmi_f01.c has_package_id_query = !!(queries[0] & BIT(0)); BIT 219 drivers/input/rmi4/rmi_f01.c has_build_id_query = !!(queries[0] & BIT(1)); BIT 18 drivers/input/rmi4/rmi_f03.c #define RMI_F03_OB_FLAG_TIMEOUT BIT(6) BIT 19 drivers/input/rmi4/rmi_f03.c #define RMI_F03_OB_FLAG_PARITY BIT(7) BIT 49 drivers/input/rmi4/rmi_f03.c bit = BIT(button - BTN_LEFT); BIT 1018 drivers/input/rmi4/rmi_f11.c has_query36 = !!(query_buf[0] & BIT(6)); BIT 1028 drivers/input/rmi4/rmi_f11.c if (!!(query_buf[0] & BIT(5))) BIT 1201 drivers/input/rmi4/rmi_f11.c ctrl->ctrl0_11[0] &= ~BIT(6); BIT 1204 drivers/input/rmi4/rmi_f11.c ctrl->ctrl0_11[0] |= BIT(6); BIT 1215 drivers/input/rmi4/rmi_f11.c ctrl->ctrl0_11[11] &= ~BIT(0); BIT 1218 drivers/input/rmi4/rmi_f11.c ctrl->ctrl0_11[11] |= BIT(0); BIT 272 drivers/input/rmi4/rmi_f12.c buf[subpacket_offset] &= ~BIT(2); BIT 275 drivers/input/rmi4/rmi_f12.c buf[subpacket_offset] |= BIT(2); BIT 344 drivers/input/rmi4/rmi_f12.c if (!(buf & BIT(0))) { BIT 363 drivers/input/rmi4/rmi_f12.c f12->has_dribble = !!(buf & BIT(3)); BIT 16 drivers/input/rmi4/rmi_f30.c #define RMI_F30_HAS_MAPPABLE_BUTTONS BIT(1) BIT 17 drivers/input/rmi4/rmi_f30.c #define RMI_F30_HAS_LED BIT(2) BIT 18 drivers/input/rmi4/rmi_f30.c #define RMI_F30_HAS_GPIO BIT(3) BIT 19 drivers/input/rmi4/rmi_f30.c #define RMI_F30_HAS_HAPTIC BIT(4) BIT 20 drivers/input/rmi4/rmi_f30.c #define RMI_F30_HAS_GPIO_DRV_CTL BIT(5) BIT 21 drivers/input/rmi4/rmi_f30.c #define RMI_F30_HAS_MECH_MOUSE_BTNS BIT(6) BIT 28 drivers/input/rmi4/rmi_f30.c #define RMI_F30_CTRL_1_HALT BIT(4) BIT 29 drivers/input/rmi4/rmi_f30.c #define RMI_F30_CTRL_1_HALTED BIT(5) BIT 107 drivers/input/rmi4/rmi_f30.c bool key_down = !(f30->data_regs[reg_num] & BIT(bit_num)); BIT 219 drivers/input/rmi4/rmi_f30.c return !(ctrl[2].regs[byte_position] & BIT(bit_position)) && BIT 220 drivers/input/rmi4/rmi_f30.c (ctrl[3].regs[byte_position] & BIT(bit_position)); BIT 49 drivers/input/rmi4/rmi_f34.h #define HAS_BSR BIT(5) BIT 50 drivers/input/rmi4/rmi_f34.h #define HAS_CONFIG_ID BIT(3) BIT 51 drivers/input/rmi4/rmi_f34.h #define HAS_GUEST_CODE BIT(6) BIT 52 drivers/input/rmi4/rmi_f34.h #define HAS_DISP_CFG BIT(5) BIT 24 drivers/input/rmi4/rmi_f55.c #define F55_CAP_SENSOR_ASSIGN BIT(0) BIT 58 drivers/input/serio/hyperv-keyboard.c #define PROTOCOL_ACCEPTED BIT(0) BIT 64 drivers/input/serio/hyperv-keyboard.c #define IS_UNICODE BIT(0) BIT 65 drivers/input/serio/hyperv-keyboard.c #define IS_BREAK BIT(1) BIT 66 drivers/input/serio/hyperv-keyboard.c #define IS_E0 BIT(2) BIT 67 drivers/input/serio/hyperv-keyboard.c #define IS_E1 BIT(3) BIT 30 drivers/input/serio/maceps2.c #define PS2_STATUS_CLOCK_SIGNAL BIT(0) /* external clock signal */ BIT 31 drivers/input/serio/maceps2.c #define PS2_STATUS_CLOCK_INHIBIT BIT(1) /* clken output signal */ BIT 32 drivers/input/serio/maceps2.c #define PS2_STATUS_TX_INPROGRESS BIT(2) /* transmission in progress */ BIT 33 drivers/input/serio/maceps2.c #define PS2_STATUS_TX_EMPTY BIT(3) /* empty transmit buffer */ BIT 34 drivers/input/serio/maceps2.c #define PS2_STATUS_RX_FULL BIT(4) /* full receive buffer */ BIT 35 drivers/input/serio/maceps2.c #define PS2_STATUS_RX_INPROGRESS BIT(5) /* reception in progress */ BIT 36 drivers/input/serio/maceps2.c #define PS2_STATUS_ERROR_PARITY BIT(6) /* parity error */ BIT 37 drivers/input/serio/maceps2.c #define PS2_STATUS_ERROR_FRAMING BIT(7) /* framing error */ BIT 39 drivers/input/serio/maceps2.c #define PS2_CONTROL_TX_CLOCK_DISABLE BIT(0) /* inhibit clock signal after TX */ BIT 40 drivers/input/serio/maceps2.c #define PS2_CONTROL_TX_ENABLE BIT(1) /* transmit enable */ BIT 41 drivers/input/serio/maceps2.c #define PS2_CONTROL_TX_INT_ENABLE BIT(2) /* enable transmit interrupt */ BIT 42 drivers/input/serio/maceps2.c #define PS2_CONTROL_RX_INT_ENABLE BIT(3) /* enable receive interrupt */ BIT 43 drivers/input/serio/maceps2.c #define PS2_CONTROL_RX_CLOCK_ENABLE BIT(4) /* pause reception if set to 0 */ BIT 44 drivers/input/serio/maceps2.c #define PS2_CONTROL_RESET BIT(5) /* reset */ BIT 261 drivers/input/serio/ps2-gpio.c data = byte & BIT(cnt - 1); BIT 31 drivers/input/serio/sun4i-ps2.c #define PS2_GCTL_INTFLAG BIT(4) BIT 32 drivers/input/serio/sun4i-ps2.c #define PS2_GCTL_INTEN BIT(3) BIT 33 drivers/input/serio/sun4i-ps2.c #define PS2_GCTL_RESET BIT(2) BIT 34 drivers/input/serio/sun4i-ps2.c #define PS2_GCTL_MASTER BIT(1) BIT 35 drivers/input/serio/sun4i-ps2.c #define PS2_GCTL_BUSEN BIT(0) BIT 38 drivers/input/serio/sun4i-ps2.c #define PS2_LCTL_NOACK BIT(18) BIT 39 drivers/input/serio/sun4i-ps2.c #define PS2_LCTL_TXDTOEN BIT(8) BIT 40 drivers/input/serio/sun4i-ps2.c #define PS2_LCTL_STOPERREN BIT(3) BIT 41 drivers/input/serio/sun4i-ps2.c #define PS2_LCTL_ACKERREN BIT(2) BIT 42 drivers/input/serio/sun4i-ps2.c #define PS2_LCTL_PARERREN BIT(1) BIT 43 drivers/input/serio/sun4i-ps2.c #define PS2_LCTL_RXDTOEN BIT(0) BIT 46 drivers/input/serio/sun4i-ps2.c #define PS2_LSTS_TXTDO BIT(8) BIT 47 drivers/input/serio/sun4i-ps2.c #define PS2_LSTS_STOPERR BIT(3) BIT 48 drivers/input/serio/sun4i-ps2.c #define PS2_LSTS_ACKERR BIT(2) BIT 49 drivers/input/serio/sun4i-ps2.c #define PS2_LSTS_PARERR BIT(1) BIT 50 drivers/input/serio/sun4i-ps2.c #define PS2_LSTS_RXTDO BIT(0) BIT 57 drivers/input/serio/sun4i-ps2.c #define PS2_FCTL_TXRST BIT(17) BIT 58 drivers/input/serio/sun4i-ps2.c #define PS2_FCTL_RXRST BIT(16) BIT 59 drivers/input/serio/sun4i-ps2.c #define PS2_FCTL_TXUFIEN BIT(10) BIT 60 drivers/input/serio/sun4i-ps2.c #define PS2_FCTL_TXOFIEN BIT(9) BIT 61 drivers/input/serio/sun4i-ps2.c #define PS2_FCTL_TXRDYIEN BIT(8) BIT 62 drivers/input/serio/sun4i-ps2.c #define PS2_FCTL_RXUFIEN BIT(2) BIT 63 drivers/input/serio/sun4i-ps2.c #define PS2_FCTL_RXOFIEN BIT(1) BIT 64 drivers/input/serio/sun4i-ps2.c #define PS2_FCTL_RXRDYIEN BIT(0) BIT 67 drivers/input/serio/sun4i-ps2.c #define PS2_FSTS_TXUF BIT(10) BIT 68 drivers/input/serio/sun4i-ps2.c #define PS2_FSTS_TXOF BIT(9) BIT 69 drivers/input/serio/sun4i-ps2.c #define PS2_FSTS_TXRDY BIT(8) BIT 70 drivers/input/serio/sun4i-ps2.c #define PS2_FSTS_RXUF BIT(2) BIT 71 drivers/input/serio/sun4i-ps2.c #define PS2_FSTS_RXOF BIT(1) BIT 72 drivers/input/serio/sun4i-ps2.c #define PS2_FSTS_RXRDY BIT(0) BIT 70 drivers/input/tablet/pegasus_notetaker.c #define PEN_BUTTON_PRESSED BIT(1) BIT 71 drivers/input/tablet/pegasus_notetaker.c #define PEN_TIP BIT(0) BIT 22 drivers/input/touchscreen/ad7879-spi.c #define AD7879_CMD_READ BIT(2) BIT 45 drivers/input/touchscreen/ar1021_i2c.c if (!(data[0] & BIT(7))) BIT 48 drivers/input/touchscreen/ar1021_i2c.c button = data[0] & BIT(0); BIT 86 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T6_STATUS_RESET BIT(7) BIT 87 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T6_STATUS_OFL BIT(6) BIT 88 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T6_STATUS_SIGERR BIT(5) BIT 89 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T6_STATUS_CAL BIT(4) BIT 90 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T6_STATUS_CFGERR BIT(3) BIT 91 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T6_STATUS_COMSERR BIT(2) BIT 110 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_UNGRIP BIT(0) BIT 111 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_SUPPRESS BIT(1) BIT 112 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_AMP BIT(2) BIT 113 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_VECTOR BIT(3) BIT 114 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_MOVE BIT(4) BIT 115 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_RELEASE BIT(5) BIT 116 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_PRESS BIT(6) BIT 117 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_DETECT BIT(7) BIT 125 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_ORIENT_SWITCH BIT(0) BIT 126 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_ORIENT_INVERTX BIT(1) BIT 127 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T9_ORIENT_INVERTY BIT(2) BIT 165 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T100_CFG_SWITCHXY BIT(5) BIT 166 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T100_CFG_INVERTY BIT(6) BIT 167 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T100_CFG_INVERTX BIT(7) BIT 169 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T100_TCHAUX_VECT BIT(0) BIT 170 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T100_TCHAUX_AMPL BIT(1) BIT 171 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T100_TCHAUX_AREA BIT(2) BIT 173 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_T100_DETECT BIT(7) BIT 212 drivers/input/touchscreen/atmel_mxt_ts.c #define MXT_BOOT_EXTENDED_ID BIT(5) BIT 767 drivers/input/touchscreen/atmel_mxt_ts.c !(message[1] & BIT(i))); BIT 66 drivers/input/touchscreen/bcm_iproc_tsc.c #define TS_PEN_INTR_MASK BIT(0) BIT 67 drivers/input/touchscreen/bcm_iproc_tsc.c #define TS_FIFO_INTR_MASK BIT(2) BIT 70 drivers/input/touchscreen/bcm_iproc_tsc.c #define TS_PEN_DOWN BIT(0) BIT 83 drivers/input/touchscreen/bcm_iproc_tsc.c #define TS_CONTROLLER_EN_BIT BIT(16) BIT 86 drivers/input/touchscreen/bcm_iproc_tsc.c #define TS_CONTROLLER_PWR_LDO BIT(5) BIT 87 drivers/input/touchscreen/bcm_iproc_tsc.c #define TS_CONTROLLER_PWR_ADC BIT(4) BIT 88 drivers/input/touchscreen/bcm_iproc_tsc.c #define TS_CONTROLLER_PWR_BGP BIT(3) BIT 89 drivers/input/touchscreen/bcm_iproc_tsc.c #define TS_CONTROLLER_PWR_TS BIT(2) BIT 90 drivers/input/touchscreen/bcm_iproc_tsc.c #define TS_WIRE_MODE_BIT BIT(1) BIT 38 drivers/input/touchscreen/eeti_ts.c #define REPORT_BIT_PRESSED BIT(0) BIT 39 drivers/input/touchscreen/eeti_ts.c #define REPORT_BIT_AD0 BIT(1) BIT 40 drivers/input/touchscreen/eeti_ts.c #define REPORT_BIT_AD1 BIT(2) BIT 41 drivers/input/touchscreen/eeti_ts.c #define REPORT_BIT_HAS_PRESSURE BIT(6) BIT 27 drivers/input/touchscreen/egalax_ts_serial.c #define EGALAX_FORMAT_START_BIT BIT(7) BIT 28 drivers/input/touchscreen/egalax_ts_serial.c #define EGALAX_FORMAT_PRESSURE_BIT BIT(6) BIT 29 drivers/input/touchscreen/egalax_ts_serial.c #define EGALAX_FORMAT_TOUCH_BIT BIT(0) BIT 42 drivers/input/touchscreen/exc3000.c if (buf[0] & BIT(0)) { BIT 82 drivers/input/touchscreen/goodix.c #define GOODIX_BUFFER_STATUS_READY BIT(7) BIT 365 drivers/input/touchscreen/goodix.c input_report_key(ts->input_dev, KEY_LEFTMETA, point_data[0] & BIT(4)); BIT 41 drivers/input/touchscreen/hideep.c #define HIDEEP_MT_RELEASED BIT(4) BIT 42 drivers/input/touchscreen/hideep.c #define HIDEEP_KEY_PRESSED BIT(7) BIT 43 drivers/input/touchscreen/hideep.c #define HIDEEP_KEY_FIRST_PRESSED BIT(8) BIT 112 drivers/input/touchscreen/ili210x.c if (touchdata[0] & BIT(finger)) BIT 129 drivers/input/touchscreen/ili210x.c if (!(*x & BIT(15))) /* Touch indication */ BIT 482 drivers/input/touchscreen/melfas_mip4.c state = packet[0] & BIT(7); BIT 483 drivers/input/touchscreen/melfas_mip4.c hover = packet[0] & BIT(5); BIT 484 drivers/input/touchscreen/melfas_mip4.c palm = packet[0] & BIT(4); BIT 504 drivers/input/touchscreen/melfas_mip4.c hover = packet[1] & BIT(2); BIT 505 drivers/input/touchscreen/melfas_mip4.c palm = packet[1] & BIT(1); BIT 506 drivers/input/touchscreen/melfas_mip4.c state = packet[1] & BIT(0); BIT 603 drivers/input/touchscreen/melfas_mip4.c alert = ts->buf[0] & BIT(7); BIT 21 drivers/input/touchscreen/mms114.c #define MMS114_ACTIVE BIT(1) BIT 149 drivers/input/touchscreen/mxs-lradc-ts.c writel(LRADC_DELAY_TRIGGER(0) | LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | BIT 203 drivers/input/touchscreen/mxs-lradc-ts.c writel(LRADC_DELAY_TRIGGER(0) | LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | BIT 92 drivers/input/touchscreen/raspberrypi-ts.c modified_ids |= BIT(touchid); BIT 106 drivers/input/touchscreen/raspberrypi-ts.c modified_ids &= ~(BIT(i)); BIT 47 drivers/input/touchscreen/s6sy761.c #define S6SY761_MASK_TOUCH BIT(0) BIT 48 drivers/input/touchscreen/s6sy761.c #define S6SY761_MASK_HOVER BIT(1) BIT 49 drivers/input/touchscreen/s6sy761.c #define S6SY761_MASK_COVER BIT(2) BIT 50 drivers/input/touchscreen/s6sy761.c #define S6SY761_MASK_GLOVE BIT(3) BIT 51 drivers/input/touchscreen/s6sy761.c #define S6SY761_MASK_STYLUS BIT(4) BIT 52 drivers/input/touchscreen/s6sy761.c #define S6SY761_MASK_PALM BIT(5) BIT 53 drivers/input/touchscreen/s6sy761.c #define S6SY761_MASK_WET BIT(6) BIT 54 drivers/input/touchscreen/s6sy761.c #define S6SY761_MASK_PROXIMITY BIT(7) BIT 60 drivers/input/touchscreen/sis_i2c.c #define SIS_PKT_HAS_AREA(x) ((x) & BIT(4)) BIT 61 drivers/input/touchscreen/sis_i2c.c #define SIS_PKT_HAS_PRESSURE(x) ((x) & BIT(5)) BIT 62 drivers/input/touchscreen/sis_i2c.c #define SIS_PKT_HAS_SCANTIME(x) ((x) & BIT(6)) BIT 95 drivers/input/touchscreen/sun4i-ts.c #define TEMP_DATA_PENDING BIT(18) BIT 96 drivers/input/touchscreen/sun4i-ts.c #define FIFO_OVERRUN_PENDING BIT(17) BIT 97 drivers/input/touchscreen/sun4i-ts.c #define FIFO_DATA_PENDING BIT(16) BIT 98 drivers/input/touchscreen/sun4i-ts.c #define TP_IDLE_FLG BIT(2) BIT 99 drivers/input/touchscreen/sun4i-ts.c #define TP_UP_PENDING BIT(1) BIT 100 drivers/input/touchscreen/sun4i-ts.c #define TP_DOWN_PENDING BIT(0) BIT 297 drivers/input/touchscreen/sun4i-ts.c ts->input->evbit[0] = BIT(EV_SYN) | BIT(EV_KEY) | BIT(EV_ABS); BIT 47 drivers/input/touchscreen/sx8654.c #define SX8650_STAT_CONVIRQ BIT(7) BIT 57 drivers/input/touchscreen/sx8654.c #define IRQ_PENTOUCH_TOUCHCONVDONE BIT(3) BIT 58 drivers/input/touchscreen/sx8654.c #define IRQ_PENRELEASE BIT(2) BIT 66 drivers/input/touchscreen/sx8654.c #define CONV_X BIT(7) BIT 67 drivers/input/touchscreen/sx8654.c #define CONV_Y BIT(6) BIT 142 drivers/input/touchscreen/ts4800-ts.c ts->bit = BIT(bit); BIT 19 drivers/input/touchscreen/tsc2007_iio.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 20 drivers/input/touchscreen/tsc2007_iio.c BIT(_chan_info), \ BIT 81 drivers/input/touchscreen/zet6223.c if (!(finger_bits & BIT(15 - i))) BIT 61 drivers/interconnect/qcom/sdm845.c #define QCOM_ICC_TAG_AMC BIT(QCOM_ICC_BUCKET_AMC) BIT 62 drivers/interconnect/qcom/sdm845.c #define QCOM_ICC_TAG_WAKE BIT(QCOM_ICC_BUCKET_WAKE) BIT 63 drivers/interconnect/qcom/sdm845.c #define QCOM_ICC_TAG_SLEEP BIT(QCOM_ICC_BUCKET_SLEEP) BIT 658 drivers/interconnect/qcom/sdm845.c if (tag & BIT(i)) { BIT 1445 drivers/iommu/amd_iommu_init.c if (value & BIT(2)) BIT 1476 drivers/iommu/amd_iommu_init.c if (value & BIT(0)) BIT 1480 drivers/iommu/amd_iommu_init.c iommu_write_l2(iommu, 0x47, value | BIT(0)); BIT 1542 drivers/iommu/amd_iommu_init.c if ((h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) && BIT 1543 drivers/iommu/amd_iommu_init.c (h->efr_reg & BIT(IOMMU_EFR_MSICAPMMIOSUP_SHIFT))) BIT 26 drivers/iommu/arm-smmu.h #define sCR0_VMID16EN BIT(31) BIT 28 drivers/iommu/arm-smmu.h #define sCR0_FB BIT(13) BIT 29 drivers/iommu/arm-smmu.h #define sCR0_PTM BIT(12) BIT 30 drivers/iommu/arm-smmu.h #define sCR0_VMIDPNE BIT(11) BIT 31 drivers/iommu/arm-smmu.h #define sCR0_USFCFG BIT(10) BIT 32 drivers/iommu/arm-smmu.h #define sCR0_GCFGFIE BIT(5) BIT 33 drivers/iommu/arm-smmu.h #define sCR0_GCFGFRE BIT(4) BIT 34 drivers/iommu/arm-smmu.h #define sCR0_EXIDENABLE BIT(3) BIT 35 drivers/iommu/arm-smmu.h #define sCR0_GFIE BIT(2) BIT 36 drivers/iommu/arm-smmu.h #define sCR0_GFRE BIT(1) BIT 37 drivers/iommu/arm-smmu.h #define sCR0_CLIENTPD BIT(0) BIT 44 drivers/iommu/arm-smmu.h #define ID0_S1TS BIT(30) BIT 45 drivers/iommu/arm-smmu.h #define ID0_S2TS BIT(29) BIT 46 drivers/iommu/arm-smmu.h #define ID0_NTS BIT(28) BIT 47 drivers/iommu/arm-smmu.h #define ID0_SMS BIT(27) BIT 48 drivers/iommu/arm-smmu.h #define ID0_ATOSNS BIT(26) BIT 49 drivers/iommu/arm-smmu.h #define ID0_PTFS_NO_AARCH32 BIT(25) BIT 50 drivers/iommu/arm-smmu.h #define ID0_PTFS_NO_AARCH32S BIT(24) BIT 52 drivers/iommu/arm-smmu.h #define ID0_CTTW BIT(14) BIT 54 drivers/iommu/arm-smmu.h #define ID0_EXIDS BIT(8) BIT 58 drivers/iommu/arm-smmu.h #define ID1_PAGESIZE BIT(31) BIT 64 drivers/iommu/arm-smmu.h #define ID2_VMID16 BIT(15) BIT 65 drivers/iommu/arm-smmu.h #define ID2_PTFS_64K BIT(14) BIT 66 drivers/iommu/arm-smmu.h #define ID2_PTFS_16K BIT(13) BIT 67 drivers/iommu/arm-smmu.h #define ID2_PTFS_4K BIT(12) BIT 93 drivers/iommu/arm-smmu.h #define sTLBGSTATUS_GSACTIVE BIT(0) BIT 97 drivers/iommu/arm-smmu.h #define SMR_VALID BIT(31) BIT 115 drivers/iommu/arm-smmu.h #define S2CR_EXIDVALID BIT(10) BIT 138 drivers/iommu/arm-smmu.h #define CBA2R_VA64 BIT(0) BIT 141 drivers/iommu/arm-smmu.h #define SCTLR_S1_ASIDPNE BIT(12) BIT 142 drivers/iommu/arm-smmu.h #define SCTLR_CFCFG BIT(7) BIT 143 drivers/iommu/arm-smmu.h #define SCTLR_CFIE BIT(6) BIT 144 drivers/iommu/arm-smmu.h #define SCTLR_CFRE BIT(5) BIT 145 drivers/iommu/arm-smmu.h #define SCTLR_E BIT(4) BIT 146 drivers/iommu/arm-smmu.h #define SCTLR_AFE BIT(2) BIT 147 drivers/iommu/arm-smmu.h #define SCTLR_TRE BIT(1) BIT 148 drivers/iommu/arm-smmu.h #define SCTLR_M BIT(0) BIT 153 drivers/iommu/arm-smmu.h #define RESUME_TERMINATE BIT(0) BIT 158 drivers/iommu/arm-smmu.h #define TCR2_AS BIT(4) BIT 170 drivers/iommu/arm-smmu.h #define CB_PAR_F BIT(0) BIT 173 drivers/iommu/arm-smmu.h #define FSR_MULTI BIT(31) BIT 174 drivers/iommu/arm-smmu.h #define FSR_SS BIT(30) BIT 175 drivers/iommu/arm-smmu.h #define FSR_UUT BIT(8) BIT 176 drivers/iommu/arm-smmu.h #define FSR_ASF BIT(7) BIT 177 drivers/iommu/arm-smmu.h #define FSR_TLBLKF BIT(6) BIT 178 drivers/iommu/arm-smmu.h #define FSR_TLBMCF BIT(5) BIT 179 drivers/iommu/arm-smmu.h #define FSR_EF BIT(4) BIT 180 drivers/iommu/arm-smmu.h #define FSR_PF BIT(3) BIT 181 drivers/iommu/arm-smmu.h #define FSR_AFF BIT(2) BIT 182 drivers/iommu/arm-smmu.h #define FSR_TF BIT(1) BIT 192 drivers/iommu/arm-smmu.h #define FSYNR0_WNR BIT(4) BIT 204 drivers/iommu/arm-smmu.h #define ATSR_ACTIVE BIT(0) BIT 300 drivers/iommu/intel-iommu.c #define DOMAIN_FLAG_STATIC_IDENTITY BIT(0) BIT 308 drivers/iommu/intel-iommu.c #define DOMAIN_FLAG_LOSE_CHILDREN BIT(1) BIT 21 drivers/iommu/intel-pasid.h #define PASID_TBL_ENTRIES BIT(PASID_PDE_SHIFT) BIT 38 drivers/iommu/intel-pasid.h #define PASID_FLAG_SUPERVISOR_MODE BIT(0) BIT 89 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl))) BIT 90 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_B BIT(2) BIT 91 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_C BIT(3) BIT 92 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_NS_TABLE BIT(3) BIT 93 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_NS_SECTION BIT(19) BIT 95 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_CONT_SECTION BIT(18) BIT 106 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_AP0 BIT(0) BIT 107 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_AP1 BIT(1) BIT 108 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_AP2 BIT(5) BIT 109 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_S BIT(6) BIT 110 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_NG BIT(7) BIT 116 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9) BIT 117 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4) BIT 137 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_PRRR_DS0 BIT(16) BIT 138 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_PRRR_DS1 BIT(17) BIT 139 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_PRRR_NS0 BIT(18) BIT 140 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_PRRR_NS1 BIT(19) BIT 141 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_PRRR_NOS(n) BIT((n) + 24) BIT 146 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_TTBR_S BIT(1) BIT 147 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_TTBR_NOS BIT(5) BIT 152 drivers/iommu/io-pgtable-arm-v7s.c #define ARM_V7S_TCR_PD1 BIT(5) BIT 387 drivers/iommu/io-pgtable-arm-v7s.c arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT); BIT 166 drivers/iommu/io-pgtable-arm.c #define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2) BIT 167 drivers/iommu/io-pgtable-arm.c #define ARM_MALI_LPAE_TTBR_SHARE_OUTER BIT(4) BIT 69 drivers/iommu/iommu.c #define IOMMU_CMD_LINE_DMA_API BIT(0) BIT 41 drivers/iommu/mtk_iommu.c #define F_INVLD_EN0 BIT(0) BIT 42 drivers/iommu/mtk_iommu.c #define F_INVLD_EN1 BIT(1) BIT 49 drivers/iommu/mtk_iommu.c #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) BIT 58 drivers/iommu/mtk_iommu.c #define F_L2_MULIT_HIT_EN BIT(0) BIT 59 drivers/iommu/mtk_iommu.c #define F_TABLE_WALK_FAULT_INT_EN BIT(1) BIT 60 drivers/iommu/mtk_iommu.c #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) BIT 61 drivers/iommu/mtk_iommu.c #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) BIT 62 drivers/iommu/mtk_iommu.c #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) BIT 63 drivers/iommu/mtk_iommu.c #define F_MISS_FIFO_ERR_INT_EN BIT(6) BIT 64 drivers/iommu/mtk_iommu.c #define F_INT_CLR_BIT BIT(12) BIT 68 drivers/iommu/mtk_iommu.c #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) BIT 69 drivers/iommu/mtk_iommu.c #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) BIT 70 drivers/iommu/mtk_iommu.c #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) BIT 71 drivers/iommu/mtk_iommu.c #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) BIT 72 drivers/iommu/mtk_iommu.c #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) BIT 73 drivers/iommu/mtk_iommu.c #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) BIT 74 drivers/iommu/mtk_iommu.c #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) BIT 83 drivers/iommu/mtk_iommu.c #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) BIT 84 drivers/iommu/mtk_iommu.c #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) BIT 41 drivers/iommu/mtk_iommu_v1.c #define F_INVLD_EN0 BIT(0) BIT 42 drivers/iommu/mtk_iommu_v1.c #define F_INVLD_EN1 BIT(1) BIT 48 drivers/iommu/mtk_iommu_v1.c #define F_MMU_CTRL_COHERENT_EN BIT(8) BIT 51 drivers/iommu/mtk_iommu_v1.c #define F_INT_TRANSLATION_FAULT BIT(0) BIT 52 drivers/iommu/mtk_iommu_v1.c #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) BIT 53 drivers/iommu/mtk_iommu_v1.c #define F_INT_INVALID_PA_FAULT BIT(2) BIT 54 drivers/iommu/mtk_iommu_v1.c #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) BIT 55 drivers/iommu/mtk_iommu_v1.c #define F_INT_TABLE_WALK_FAULT BIT(4) BIT 56 drivers/iommu/mtk_iommu_v1.c #define F_INT_TLB_MISS_FAULT BIT(5) BIT 57 drivers/iommu/mtk_iommu_v1.c #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6) BIT 58 drivers/iommu/mtk_iommu_v1.c #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7) BIT 61 drivers/iommu/mtk_iommu_v1.c #define F_INT_CLR_BIT BIT(12) BIT 75 drivers/iommu/mtk_iommu_v1.c #define F_MMU_DCM_ON BIT(1) BIT 78 drivers/iommu/mtk_iommu_v1.c #define F_DESC_NONSEC BIT(3) BIT 140 drivers/iommu/omap-iommu.h #define MMU_IRQ_MULTIHITFAULT BIT(4) BIT 141 drivers/iommu/omap-iommu.h #define MMU_IRQ_TABLEWALKFAULT BIT(3) BIT 142 drivers/iommu/omap-iommu.h #define MMU_IRQ_EMUMISS BIT(2) BIT 143 drivers/iommu/omap-iommu.h #define MMU_IRQ_TRANSLATIONFAULT BIT(1) BIT 144 drivers/iommu/omap-iommu.h #define MMU_IRQ_TLBMISS BIT(0) BIT 156 drivers/iommu/omap-iommu.h #define MMU_CNTL_EML_TLB BIT(3) BIT 157 drivers/iommu/omap-iommu.h #define MMU_CNTL_TWL_EN BIT(2) BIT 158 drivers/iommu/omap-iommu.h #define MMU_CNTL_MMU_EN BIT(1) BIT 164 drivers/iommu/omap-iommu.h #define MMU_CAM_P BIT(3) BIT 165 drivers/iommu/omap-iommu.h #define MMU_CAM_V BIT(2) BIT 178 drivers/iommu/omap-iommu.h #define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT) BIT 180 drivers/iommu/omap-iommu.h #define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT) BIT 189 drivers/iommu/omap-iommu.h #define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT) BIT 19 drivers/iommu/omap-iopgtable.h #define IOPGD_SIZE BIT(IOPGD_SHIFT) BIT 26 drivers/iommu/omap-iopgtable.h #define IOSECTION_SIZE BIT(IOSECTION_SHIFT) BIT 33 drivers/iommu/omap-iopgtable.h #define IOSUPER_SIZE BIT(IOSUPER_SHIFT) BIT 43 drivers/iommu/omap-iopgtable.h #define IOPTE_SIZE BIT(IOPTE_SHIFT) BIT 50 drivers/iommu/omap-iopgtable.h #define IOLARGE_SIZE BIT(IOLARGE_SHIFT) BIT 76 drivers/iommu/omap-iopgtable.h #define IOPGD_SUPER (BIT(18) | IOPGD_SECTION) BIT 50 drivers/iommu/rockchip-iommu.c #define RK_MMU_STATUS_PAGING_ENABLED BIT(0) BIT 51 drivers/iommu/rockchip-iommu.c #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) BIT 52 drivers/iommu/rockchip-iommu.c #define RK_MMU_STATUS_STALL_ACTIVE BIT(2) BIT 53 drivers/iommu/rockchip-iommu.c #define RK_MMU_STATUS_IDLE BIT(3) BIT 54 drivers/iommu/rockchip-iommu.c #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) BIT 55 drivers/iommu/rockchip-iommu.c #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) BIT 56 drivers/iommu/rockchip-iommu.c #define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31) BIT 175 drivers/iommu/rockchip-iommu.c #define RK_DTE_PT_VALID BIT(0) BIT 214 drivers/iommu/rockchip-iommu.c #define RK_PTE_PAGE_WRITABLE BIT(2) BIT 215 drivers/iommu/rockchip-iommu.c #define RK_PTE_PAGE_READABLE BIT(1) BIT 216 drivers/iommu/rockchip-iommu.c #define RK_PTE_PAGE_VALID BIT(0) BIT 27 drivers/iommu/tegra-gart.c #define GART_ENTRY_PHYS_ADDR_VALID BIT(31) BIT 361 drivers/iommu/tegra-smmu.c value |= BIT(client->smmu.bit); BIT 398 drivers/iommu/tegra-smmu.c value &= ~BIT(client->smmu.bit); BIT 965 drivers/iommu/tegra-smmu.c if (value & BIT(client->smmu.bit)) BIT 37 drivers/irqchip/alphascale_asm9260-icoll.h #define ASM9260_BM_LEVELn(nr) BIT(nr) BIT 44 drivers/irqchip/alphascale_asm9260-icoll.h #define ASM9260_BM_CTRL_SFTRST BIT(31) BIT 45 drivers/irqchip/alphascale_asm9260-icoll.h #define ASM9260_BM_CTRL_CLKGATE BIT(30) BIT 47 drivers/irqchip/alphascale_asm9260-icoll.h #define ASM9260_BM_CTRL_NO_NESTING BIT(19) BIT 58 drivers/irqchip/alphascale_asm9260-icoll.h #define ASM9260_BM_CTRL_ARM_RSE_MODE BIT(18) BIT 59 drivers/irqchip/alphascale_asm9260-icoll.h #define ASM9260_BM_CTRL_IRQ_ENABLE BIT(16) BIT 83 drivers/irqchip/alphascale_asm9260-icoll.h #define ASM9260_BM_INT_ENABLE BIT(2) BIT 84 drivers/irqchip/alphascale_asm9260-icoll.h #define ASM9260_BM_INT_SOFTIRQ BIT(3) BIT 101 drivers/irqchip/alphascale_asm9260-icoll.h #define ASM9260_BM_CLEAR_BIT(n) BIT(n & 0x1f) BIT 22 drivers/irqchip/irq-al-fic.c #define CONTROL_TRIGGER_RISING BIT(3) BIT 23 drivers/irqchip/irq-al-fic.c #define CONTROL_MASK_MSI_X BIT(5) BIT 135 drivers/irqchip/irq-al-fic.c writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE); BIT 29 drivers/irqchip/irq-alpine-msi.c #define ALPINE_MSIX_SPI_TARGET_CLUSTER0 BIT(16) BIT 124 drivers/irqchip/irq-armada-370-xp.c #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid) BIT 488 drivers/irqchip/irq-armada-370-xp.c if (!(msimask & BIT(msinr))) BIT 52 drivers/irqchip/irq-ath79-cpu.c pending &= ~BIT(irq); BIT 54 drivers/irqchip/irq-ath79-misc.c pending &= ~BIT(bit); BIT 67 drivers/irqchip/irq-ath79-misc.c __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); BIT 80 drivers/irqchip/irq-ath79-misc.c __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); BIT 93 drivers/irqchip/irq-ath79-misc.c __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); BIT 17 drivers/irqchip/irq-ativic32.c __nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2); BIT 23 drivers/irqchip/irq-ativic32.c __nds32__mtsr_dsb(int_mask2 & (~(BIT(data->hwirq))), NDS32_SR_INT_MASK2); BIT 29 drivers/irqchip/irq-ativic32.c __nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2); BIT 83 drivers/irqchip/irq-ativic32.c if (int_trigger_type & (BIT(hw))) { BIT 50 drivers/irqchip/irq-bcm2835.c #define HWIRQ_BIT(i) BIT(i & 0x1f) BIT 58 drivers/irqchip/irq-bcm2835.c #define BANK1_HWIRQ BIT(8) BIT 59 drivers/irqchip/irq-bcm2835.c #define BANK2_HWIRQ BIT(9) BIT 30 drivers/irqchip/irq-bcm2836.c writel(readl(reg) & ~BIT(bit), reg); BIT 39 drivers/irqchip/irq-bcm2836.c writel(readl(reg) | BIT(bit), reg); BIT 130 drivers/irqchip/irq-bcm2836.c if (stat & BIT(LOCAL_IRQ_MAILBOX0)) { BIT 156 drivers/irqchip/irq-bcm6345-l1.c u32 mask = BIT(d->hwirq % IRQS_PER_WORD); BIT 168 drivers/irqchip/irq-bcm6345-l1.c u32 mask = BIT(d->hwirq % IRQS_PER_WORD); BIT 202 drivers/irqchip/irq-bcm6345-l1.c u32 mask = BIT(d->hwirq % IRQS_PER_WORD); BIT 152 drivers/irqchip/irq-bcm7038-l1.c u32 mask = BIT(d->hwirq % IRQS_PER_WORD); BIT 163 drivers/irqchip/irq-bcm7038-l1.c u32 mask = BIT(d->hwirq % IRQS_PER_WORD); BIT 198 drivers/irqchip/irq-bcm7038-l1.c u32 mask = BIT(hw % IRQS_PER_WORD); BIT 244 drivers/irqchip/irq-csky-apb-intc.c writel(BIT(31), reg_base + CK_INTC_ICR); BIT 154 drivers/irqchip/irq-csky-mpintc.c cpu |= BIT(31); BIT 255 drivers/irqchip/irq-csky-mpintc.c writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR); BIT 266 drivers/irqchip/irq-csky-mpintc.c writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR); BIT 39 drivers/irqchip/irq-davinci-cp-intc.c #define DAVINCI_CP_INTC_GPIR_NONE BIT(31) BIT 60 drivers/irqchip/irq-ftintc010.c mask &= ~BIT(irqd_to_hwirq(d)); BIT 70 drivers/irqchip/irq-ftintc010.c mask |= BIT(irqd_to_hwirq(d)); BIT 78 drivers/irqchip/irq-ftintc010.c writel(BIT(irqd_to_hwirq(d)), FT010_IRQ_CLEAR(f->base)); BIT 92 drivers/irqchip/irq-ftintc010.c mode &= ~BIT(offset); BIT 93 drivers/irqchip/irq-ftintc010.c polarity |= BIT(offset); BIT 96 drivers/irqchip/irq-ftintc010.c mode &= ~BIT(offset); BIT 97 drivers/irqchip/irq-ftintc010.c polarity &= ~BIT(offset); BIT 100 drivers/irqchip/irq-ftintc010.c mode |= BIT(offset); BIT 101 drivers/irqchip/irq-ftintc010.c polarity |= BIT(offset); BIT 104 drivers/irqchip/irq-ftintc010.c mode |= BIT(offset); BIT 105 drivers/irqchip/irq-ftintc010.c polarity &= ~BIT(offset); BIT 17 drivers/irqchip/irq-gic-realview.c #define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24) BIT 19 drivers/irqchip/irq-gic-realview.c #define PLD_INTMODE_NEW_DCC BIT(22) BIT 20 drivers/irqchip/irq-gic-realview.c #define PLD_INTMODE_NEW_NO_DCC BIT(23) BIT 21 drivers/irqchip/irq-gic-realview.c #define PLD_INTMODE_FIQ_ENABLE BIT(24) BIT 56 drivers/irqchip/irq-gic-v3-its.c #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) BIT 57 drivers/irqchip/irq-gic-v3-its.c #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) BIT 704 drivers/irqchip/irq-gic-v3.c gic_write_pmr(BIT(8 - gic_get_pribits())); BIT 403 drivers/irqchip/irq-imgpdc.c gc->unused = ~(BIT(priv->nr_perips) - 1); BIT 417 drivers/irqchip/irq-imgpdc.c gc->unused = ~(BIT(priv->nr_syswakes) - 1); BIT 81 drivers/irqchip/irq-imx-gpcv2.c mask = BIT(d->hwirq % 32); BIT 104 drivers/irqchip/irq-imx-gpcv2.c val &= ~BIT(d->hwirq % 32); BIT 120 drivers/irqchip/irq-imx-gpcv2.c val |= BIT(d->hwirq % 32); BIT 54 drivers/irqchip/irq-imx-irqsteer.c val |= BIT(d->hwirq % 32); BIT 68 drivers/irqchip/irq-imx-irqsteer.c val &= ~BIT(d->hwirq % 32); BIT 199 drivers/irqchip/irq-imx-irqsteer.c writel_relaxed(BIT(data->channel), data->regs + CHANCTRL); BIT 264 drivers/irqchip/irq-imx-irqsteer.c writel_relaxed(BIT(data->channel), data->regs + CHANCTRL); BIT 80 drivers/irqchip/irq-ixp4xx.c val &= ~BIT(d->hwirq - 32); BIT 84 drivers/irqchip/irq-ixp4xx.c val &= ~BIT(d->hwirq); BIT 100 drivers/irqchip/irq-ixp4xx.c val |= BIT(d->hwirq - 32); BIT 104 drivers/irqchip/irq-ixp4xx.c val |= BIT(d->hwirq); BIT 70 drivers/irqchip/irq-keystone.c kirq->mask |= BIT(d->hwirq); BIT 78 drivers/irqchip/irq-keystone.c kirq->mask &= ~BIT(d->hwirq); BIT 106 drivers/irqchip/irq-keystone.c if (BIT(src) & pending) { BIT 48 drivers/irqchip/irq-lpc32xx.c u32 val, mask = BIT(d->hwirq); BIT 57 drivers/irqchip/irq-lpc32xx.c u32 val, mask = BIT(d->hwirq); BIT 66 drivers/irqchip/irq-lpc32xx.c u32 mask = BIT(d->hwirq); BIT 74 drivers/irqchip/irq-lpc32xx.c u32 val, mask = BIT(d->hwirq); BIT 128 drivers/irqchip/irq-lpc32xx.c hwirq &= ~BIT(irq); BIT 143 drivers/irqchip/irq-lpc32xx.c hwirq &= ~BIT(irq); BIT 54 drivers/irqchip/irq-ls1x.c pending &= ~BIT(bit); BIT 33 drivers/irqchip/irq-meson-gpio.c #define REG_EDGE_POL_EDGE(x) BIT(x) BIT 34 drivers/irqchip/irq-meson-gpio.c #define REG_EDGE_POL_LOW(x) BIT(16 + (x)) BIT 35 drivers/irqchip/irq-meson-gpio.c #define REG_BOTH_EDGE(x) BIT(8 + (x)) BIT 146 drivers/irqchip/irq-mips-cpu.c pending &= ~BIT(irq); BIT 271 drivers/irqchip/irq-mips-gic.c write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); BIT 331 drivers/irqchip/irq-mips-gic.c write_gic_vl_rmask(BIT(intr)); BIT 338 drivers/irqchip/irq-mips-gic.c write_gic_vl_smask(BIT(intr)); BIT 360 drivers/irqchip/irq-mips-gic.c write_gic_vo_rmask(BIT(intr)); BIT 378 drivers/irqchip/irq-mips-gic.c write_gic_vo_smask(BIT(intr)); BIT 393 drivers/irqchip/irq-mips-gic.c write_gic_vl_smask(BIT(intr)); BIT 426 drivers/irqchip/irq-mips-gic.c write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); BIT 685 drivers/irqchip/irq-mips-gic.c reserved |= BIT(cpu_vec); BIT 55 drivers/irqchip/irq-mscc-ocelot.c reg &= ~(BIT(hwirq)); BIT 35 drivers/irqchip/irq-mvebu-icu.c #define ICU_INT_ENABLE BIT(24) BIT 36 drivers/irqchip/irq-mvebu-icu.c #define ICU_IS_EDGE BIT(28) BIT 61 drivers/irqchip/irq-mvebu-sei.c writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), BIT 74 drivers/irqchip/irq-mvebu-sei.c reg |= BIT(SEI_IRQ_REG_BIT(d->hwirq)); BIT 88 drivers/irqchip/irq-mvebu-sei.c reg &= ~BIT(SEI_IRQ_REG_BIT(d->hwirq)); BIT 38 drivers/irqchip/irq-mxs.c #define BM_ICOLL_INTR_ENABLE BIT(2) BIT 65 drivers/irqchip/irq-pic32-evic.c writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON)); BIT 68 drivers/irqchip/irq-pic32-evic.c writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON)); BIT 32 drivers/irqchip/irq-rda-intc.c writel_relaxed(BIT(d->hwirq), rda_intc_base + RDA_INTC_MASK_CLR); BIT 37 drivers/irqchip/irq-rda-intc.c writel_relaxed(BIT(d->hwirq), rda_intc_base + RDA_INTC_MASK_SET); BIT 57 drivers/irqchip/irq-rda-intc.c stat &= ~BIT(hwirq); BIT 117 drivers/irqchip/irq-renesas-intc-irqpin.c return BIT((p->iomem[reg].width - 1) - hw_irq); BIT 205 drivers/irqchip/irq-renesas-intc-irqpin.c p->shared_irq_mask &= ~BIT(hw_irq); BIT 216 drivers/irqchip/irq-renesas-intc-irqpin.c p->shared_irq_mask |= BIT(hw_irq); BIT 309 drivers/irqchip/irq-renesas-intc-irqpin.c if (reg_source & BIT(7 - k)) { BIT 310 drivers/irqchip/irq-renesas-intc-irqpin.c if (BIT(k) & p->shared_irq_mask) BIT 111 drivers/irqchip/irq-renesas-irqc.c u32 bit = BIT(i->hw_irq); BIT 25 drivers/irqchip/irq-renesas-rza1.c #define ICR0_NMIL BIT(15) /* NMI Input Level (0=low, 1=high) */ BIT 26 drivers/irqchip/irq-renesas-rza1.c #define ICR0_NMIE BIT(8) /* Edge Select (0=falling, 1=rising) */ BIT 27 drivers/irqchip/irq-renesas-rza1.c #define ICR0_NMIF BIT(1) /* NMI Interrupt Request */ BIT 57 drivers/irqchip/irq-renesas-rza1.c u16 bit = BIT(irqd_to_hwirq(d)); BIT 39 drivers/irqchip/irq-sa11x0.c reg &= ~BIT(d->hwirq); BIT 48 drivers/irqchip/irq-sa11x0.c reg |= BIT(d->hwirq); BIT 44 drivers/irqchip/irq-sni-exiu.c writel(BIT(d->hwirq), data->base + EIREQCLR); BIT 53 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); BIT 63 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); BIT 74 drivers/irqchip/irq-sni-exiu.c writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); BIT 76 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); BIT 88 drivers/irqchip/irq-sni-exiu.c val |= BIT(d->hwirq); BIT 90 drivers/irqchip/irq-sni-exiu.c val &= ~BIT(d->hwirq); BIT 95 drivers/irqchip/irq-sni-exiu.c val &= ~BIT(d->hwirq); BIT 97 drivers/irqchip/irq-sni-exiu.c val |= BIT(d->hwirq); BIT 100 drivers/irqchip/irq-sni-exiu.c writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); BIT 26 drivers/irqchip/irq-st.c #define ST_A9_IRQ_EN_CTI_0 BIT(0) BIT 27 drivers/irqchip/irq-st.c #define ST_A9_IRQ_EN_CTI_1 BIT(1) BIT 28 drivers/irqchip/irq-st.c #define ST_A9_IRQ_EN_PMU_0 BIT(2) BIT 29 drivers/irqchip/irq-st.c #define ST_A9_IRQ_EN_PMU_1 BIT(3) BIT 30 drivers/irqchip/irq-st.c #define ST_A9_IRQ_EN_PL310_L2 BIT(4) BIT 31 drivers/irqchip/irq-st.c #define ST_A9_IRQ_EN_EXT_0 BIT(5) BIT 32 drivers/irqchip/irq-st.c #define ST_A9_IRQ_EN_EXT_1 BIT(6) BIT 33 drivers/irqchip/irq-st.c #define ST_A9_IRQ_EN_EXT_2 BIT(7) BIT 258 drivers/irqchip/irq-stm32-exti.c u32 mask = BIT(d->hwirq % IRQS_PER_BANK); BIT 441 drivers/irqchip/irq-stm32-exti.c val |= BIT(d->hwirq % IRQS_PER_BANK); BIT 454 drivers/irqchip/irq-stm32-exti.c val &= ~BIT(d->hwirq % IRQS_PER_BANK); BIT 538 drivers/irqchip/irq-stm32-exti.c u32 mask = BIT(d->hwirq % IRQS_PER_BANK); BIT 56 drivers/irqchip/irq-sun4i.c writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)); BIT 198 drivers/irqchip/irq-sun4i.c BIT(0))) BIT 28 drivers/irqchip/irq-sunxi-nmi.c #define SUNXI_NMI_IRQ_BIT BIT(0) BIT 66 drivers/irqchip/irq-tango.c status &= ~BIT(hwirq); BIT 87 drivers/irqchip/irq-tegra.c mask = BIT(d->hwirq % 32); BIT 122 drivers/irqchip/irq-tegra.c mask = BIT(irq % 32); BIT 369 drivers/irqchip/irq-ti-sci-inta.c writeq_relaxed(BIT(event_desc->vint_bit), BIT 52 drivers/irqchip/irq-uniphier-aidet.c mask = BIT(index % 32); BIT 135 drivers/irqchip/irq-versatile-fpga.c if (!(f->valid & BIT(hwirq))) BIT 178 drivers/irqchip/irq-versatile-fpga.c if (valid & BIT(i)) { BIT 37 drivers/irqchip/irq-vt8500.c #define ICPC_ROTATE BIT(6) BIT 50 drivers/irqchip/irq-vt8500.c #define VT8500_INT_ENABLE BIT(3) BIT 53 drivers/irqchip/irq-vt8500.c #define VT8500_TRIGGER_RISING BIT(5) BIT 54 drivers/irqchip/irq-vt8500.c #define VT8500_TRIGGER_FALLING BIT(6) BIT 182 drivers/irqchip/irq-vt8500.c if (!(stat & BIT(31))) BIT 20 drivers/leds/leds-an30259a.c #define AN30259A_LED_SRESET BIT(0) BIT 24 drivers/leds/leds-an30259a.c #define AN30259A_LED_EN(x) BIT((x) - 1) BIT 25 drivers/leds/leds-an30259a.c #define AN30259A_LED_SLOPE(x) BIT(((x) - 1) + 4) BIT 33 drivers/leds/leds-bcm6328.c #define BCM6328_SERIAL_LED_EN BIT(12) BIT 34 drivers/leds/leds-bcm6328.c #define BCM6328_SERIAL_LED_MUX BIT(13) BIT 35 drivers/leds/leds-bcm6328.c #define BCM6328_SERIAL_LED_CLK_NPOL BIT(14) BIT 36 drivers/leds/leds-bcm6328.c #define BCM6328_SERIAL_LED_DATA_PPOL BIT(15) BIT 37 drivers/leds/leds-bcm6328.c #define BCM6328_SERIAL_LED_SHIFT_DIR BIT(16) BIT 38 drivers/leds/leds-bcm6328.c #define BCM6328_LED_SHIFT_TEST BIT(30) BIT 39 drivers/leds/leds-bcm6328.c #define BCM6328_LED_TEST BIT(31) BIT 130 drivers/leds/leds-bcm6328.c *(led->blink_leds) &= ~BIT(led->pin); BIT 180 drivers/leds/leds-bcm6328.c *(led->blink_leds) == BIT(led->pin) || BIT 184 drivers/leds/leds-bcm6328.c *(led->blink_leds) |= BIT(led->pin); BIT 212 drivers/leds/leds-bcm6328.c val &= ~BIT(reg); BIT 241 drivers/leds/leds-bcm6328.c val |= (BIT(reg % 4) << (((sel % 4) * 4) + 16)); BIT 268 drivers/leds/leds-bcm6328.c val |= (BIT(reg % 4) << ((sel % 4) * 4)); BIT 24 drivers/leds/leds-bcm6358.c #define BCM6358_SLED_POLARITY BIT(2) BIT 25 drivers/leds/leds-bcm6358.c #define BCM6358_SLED_BUSY BIT(3) BIT 87 drivers/leds/leds-bcm6358.c val |= BIT(led->pin); BIT 89 drivers/leds/leds-bcm6358.c val &= ~(BIT(led->pin)); BIT 123 drivers/leds/leds-bcm6358.c val &= BIT(led->pin); BIT 69 drivers/leds/leds-cr0014114.c crc |= BIT(7); BIT 25 drivers/leds/leds-is31fl32xx.c #define IS31FL32XX_SHUTDOWN_SSD_DISABLE BIT(0) BIT 33 drivers/leds/leds-is31fl32xx.c #define IS31FL3216_CONFIG_SSD_ENABLE BIT(7) BIT 152 drivers/leds/leds-ktd2692.c ktd2692_expresswire_set_bit(led, value & BIT(i)); BIT 47 drivers/leds/leds-lm3532.c #define LM3532_CTRL_A_ENABLE BIT(0) BIT 48 drivers/leds/leds-lm3532.c #define LM3532_CTRL_B_ENABLE BIT(1) BIT 49 drivers/leds/leds-lm3532.c #define LM3532_CTRL_C_ENABLE BIT(2) BIT 53 drivers/leds/leds-lm3532.c #define LM3532_PWM_ZONE_0_EN BIT(2) BIT 54 drivers/leds/leds-lm3532.c #define LM3532_PWM_ZONE_1_EN BIT(3) BIT 55 drivers/leds/leds-lm3532.c #define LM3532_PWM_ZONE_2_EN BIT(4) BIT 56 drivers/leds/leds-lm3532.c #define LM3532_PWM_ZONE_3_EN BIT(5) BIT 57 drivers/leds/leds-lm3532.c #define LM3532_PWM_ZONE_4_EN BIT(6) BIT 60 drivers/leds/leds-lm3532.c #define LM3532_I2C_CTRL BIT(0) BIT 62 drivers/leds/leds-lm3532.c #define LM3532_LINEAR_MAP BIT(1) BIT 63 drivers/leds/leds-lm3532.c #define LM3532_ZONE_MASK (BIT(2) | BIT(3) | BIT(4)) BIT 65 drivers/leds/leds-lm3532.c #define LM3532_ZONE_1 BIT(2) BIT 66 drivers/leds/leds-lm3532.c #define LM3532_ZONE_2 BIT(3) BIT 67 drivers/leds/leds-lm3532.c #define LM3532_ZONE_3 (BIT(2) | BIT(3)) BIT 68 drivers/leds/leds-lm3532.c #define LM3532_ZONE_4 BIT(4) BIT 70 drivers/leds/leds-lm3532.c #define LM3532_ENABLE_ALS BIT(3) BIT 300 drivers/leds/leds-lm3532.c int ctrl_en_val = BIT(led_data->control_bank); BIT 325 drivers/leds/leds-lm3532.c int ctrl_en_val = BIT(led_data->control_bank); BIT 25 drivers/leds/leds-lm3601x.c #define LM3601X_SW_RESET BIT(7) BIT 29 drivers/leds/leds-lm3601x.c #define LM3601X_MODE_IR_DRV BIT(0) BIT 30 drivers/leds/leds-lm3601x.c #define LM3601X_MODE_TORCH BIT(1) BIT 31 drivers/leds/leds-lm3601x.c #define LM3601X_MODE_STROBE (BIT(0) | BIT(1)) BIT 32 drivers/leds/leds-lm3601x.c #define LM3601X_STRB_EN BIT(2) BIT 33 drivers/leds/leds-lm3601x.c #define LM3601X_STRB_EDGE_TRIG BIT(3) BIT 34 drivers/leds/leds-lm3601x.c #define LM3601X_IVFM_EN BIT(4) BIT 36 drivers/leds/leds-lm3601x.c #define LM36010_BOOST_LIMIT_28 BIT(5) BIT 37 drivers/leds/leds-lm3601x.c #define LM36010_BOOST_FREQ_4MHZ BIT(6) BIT 38 drivers/leds/leds-lm3601x.c #define LM36010_BOOST_MODE_PASS BIT(7) BIT 41 drivers/leds/leds-lm3601x.c #define LM3601X_FLASH_TIME_OUT BIT(0) BIT 42 drivers/leds/leds-lm3601x.c #define LM3601X_UVLO_FAULT BIT(1) BIT 43 drivers/leds/leds-lm3601x.c #define LM3601X_THERM_SHUTDOWN BIT(2) BIT 44 drivers/leds/leds-lm3601x.c #define LM3601X_THERM_CURR BIT(3) BIT 45 drivers/leds/leds-lm3601x.c #define LM36010_CURR_LIMIT BIT(4) BIT 46 drivers/leds/leds-lm3601x.c #define LM3601X_SHORT_FAULT BIT(5) BIT 47 drivers/leds/leds-lm3601x.c #define LM3601X_IVFM_TRIP BIT(6) BIT 48 drivers/leds/leds-lm3601x.c #define LM36010_OVP_FAULT BIT(7) BIT 20 drivers/leds/leds-lm36274.c #define LM36274_BL_EN BIT(4) BIT 34 drivers/leds/leds-lm3692x.c #define LM3692X_SW_RESET BIT(0) BIT 35 drivers/leds/leds-lm3692x.c #define LM3692X_DEVICE_EN BIT(0) BIT 36 drivers/leds/leds-lm3692x.c #define LM3692X_LED1_EN BIT(1) BIT 37 drivers/leds/leds-lm3692x.c #define LM3692X_LED2_EN BIT(2) BIT 38 drivers/leds/leds-lm3692x.c #define LM36923_LED3_EN BIT(3) BIT 43 drivers/leds/leds-lm3692x.c #define LM3692X_BL_ADJ_POL BIT(0) BIT 45 drivers/leds/leds-lm3692x.c #define LM3692X_RAMP_RATE_250us BIT(1) BIT 46 drivers/leds/leds-lm3692x.c #define LM3692X_RAMP_RATE_500us BIT(2) BIT 47 drivers/leds/leds-lm3692x.c #define LM3692X_RAMP_RATE_1ms (BIT(1) | BIT(2)) BIT 48 drivers/leds/leds-lm3692x.c #define LM3692X_RAMP_RATE_2ms BIT(3) BIT 49 drivers/leds/leds-lm3692x.c #define LM3692X_RAMP_RATE_4ms (BIT(3) | BIT(1)) BIT 50 drivers/leds/leds-lm3692x.c #define LM3692X_RAMP_RATE_8ms (BIT(2) | BIT(3)) BIT 51 drivers/leds/leds-lm3692x.c #define LM3692X_RAMP_RATE_16ms (BIT(1) | BIT(2) | BIT(3)) BIT 52 drivers/leds/leds-lm3692x.c #define LM3692X_RAMP_EN BIT(4) BIT 54 drivers/leds/leds-lm3692x.c #define LM3692X_BRHT_MODE_PWM BIT(5) BIT 55 drivers/leds/leds-lm3692x.c #define LM3692X_BRHT_MODE_MULTI_RAMP BIT(6) BIT 56 drivers/leds/leds-lm3692x.c #define LM3692X_BRHT_MODE_RAMP_MULTI (BIT(5) | BIT(6)) BIT 57 drivers/leds/leds-lm3692x.c #define LM3692X_MAP_MODE_EXP BIT(7) BIT 60 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_FILTER_100 BIT(0) BIT 61 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_FILTER_150 BIT(1) BIT 62 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_FILTER_200 (BIT(0) | BIT(1)) BIT 63 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_HYSTER_1LSB BIT(2) BIT 64 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_HYSTER_2LSB BIT(3) BIT 65 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_HYSTER_3LSB (BIT(3) | BIT(2)) BIT 66 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_HYSTER_4LSB BIT(4) BIT 67 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_HYSTER_5LSB (BIT(4) | BIT(2)) BIT 68 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_HYSTER_6LSB (BIT(4) | BIT(3)) BIT 69 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_POLARITY BIT(5) BIT 70 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_SAMP_4MHZ BIT(6) BIT 71 drivers/leds/leds-lm3692x.c #define LM3692X_PWM_SAMP_24MHZ BIT(7) BIT 74 drivers/leds/leds-lm3692x.c #define LM3692X_OCP_PROT_1A BIT(0) BIT 75 drivers/leds/leds-lm3692x.c #define LM3692X_OCP_PROT_1_25A BIT(1) BIT 76 drivers/leds/leds-lm3692x.c #define LM3692X_OCP_PROT_1_5A (BIT(0) | BIT(1)) BIT 77 drivers/leds/leds-lm3692x.c #define LM3692X_OVP_21V BIT(2) BIT 78 drivers/leds/leds-lm3692x.c #define LM3692X_OVP_25V BIT(3) BIT 79 drivers/leds/leds-lm3692x.c #define LM3692X_OVP_29V (BIT(2) | BIT(3)) BIT 80 drivers/leds/leds-lm3692x.c #define LM3692X_MIN_IND_22UH BIT(4) BIT 81 drivers/leds/leds-lm3692x.c #define LM3692X_BOOST_SW_1MHZ BIT(5) BIT 82 drivers/leds/leds-lm3692x.c #define LM3692X_BOOST_SW_NO_SHIFT BIT(6) BIT 85 drivers/leds/leds-lm3692x.c #define LM3692X_FAULT_CTRL_OVP BIT(0) BIT 86 drivers/leds/leds-lm3692x.c #define LM3692X_FAULT_CTRL_OCP BIT(1) BIT 87 drivers/leds/leds-lm3692x.c #define LM3692X_FAULT_CTRL_TSD BIT(2) BIT 88 drivers/leds/leds-lm3692x.c #define LM3692X_FAULT_CTRL_OPEN BIT(3) BIT 91 drivers/leds/leds-lm3692x.c #define LM3692X_FAULT_FLAG_OVP BIT(0) BIT 92 drivers/leds/leds-lm3692x.c #define LM3692X_FAULT_FLAG_OCP BIT(1) BIT 93 drivers/leds/leds-lm3692x.c #define LM3692X_FAULT_FLAG_TSD BIT(2) BIT 94 drivers/leds/leds-lm3692x.c #define LM3692X_FAULT_FLAG_SHRT BIT(3) BIT 95 drivers/leds/leds-lm3692x.c #define LM3692X_FAULT_FLAG_OPEN BIT(4) BIT 29 drivers/leds/leds-lm3697.c #define LM3697_SW_RESET BIT(0) BIT 31 drivers/leds/leds-lm3697.c #define LM3697_CTRL_A_EN BIT(0) BIT 32 drivers/leds/leds-lm3697.c #define LM3697_CTRL_B_EN BIT(1) BIT 28 drivers/leds/leds-lp8501.c #define LP8501_ENABLE BIT(6) BIT 53 drivers/leds/leds-lp8501.c #define LP8501_PWM_PSAVE BIT(7) BIT 54 drivers/leds/leds-lp8501.c #define LP8501_AUTO_INC BIT(6) BIT 55 drivers/leds/leds-lp8501.c #define LP8501_PWR_SAVE BIT(5) BIT 57 drivers/leds/leds-lp8501.c #define LP8501_INT_CLK BIT(0) BIT 26 drivers/leds/leds-max77650.c #define MAX77650_LED_TOP_DEFAULT BIT(0) BIT 19 drivers/leds/leds-menf21bmc.c #define BMC_BIT_LED_STATUS BIT(0) BIT 20 drivers/leds/leds-menf21bmc.c #define BMC_BIT_LED_HOTSWAP BIT(1) BIT 21 drivers/leds/leds-menf21bmc.c #define BMC_BIT_LED_USER1 BIT(2) BIT 22 drivers/leds/leds-menf21bmc.c #define BMC_BIT_LED_USER2 BIT(3) BIT 20 drivers/leds/leds-mt6323.c #define MT6323_RG_DRV_32K_CK_PDN BIT(11) BIT 21 drivers/leds/leds-mt6323.c #define MT6323_RG_DRV_32K_CK_PDN_MASK BIT(11) BIT 27 drivers/leds/leds-mt6323.c #define MT6323_RG_ISINK_CK_PDN(i) BIT(i) BIT 28 drivers/leds/leds-mt6323.c #define MT6323_RG_ISINK_CK_PDN_MASK(i) BIT(i) BIT 34 drivers/leds/leds-mt6323.c #define MT6323_RG_ISINK_CK_SEL_MASK(i) (BIT(10) << (i)) BIT 59 drivers/leds/leds-mt6323.c #define MT6323_ISINK_SFSTR0_EN_MASK BIT(0) BIT 60 drivers/leds/leds-mt6323.c #define MT6323_ISINK_SFSTR0_EN BIT(0) BIT 63 drivers/leds/leds-mt6323.c #define MT6323_ISINK_CH_EN_MASK(i) BIT(i) BIT 64 drivers/leds/leds-mt6323.c #define MT6323_ISINK_CH_EN(i) BIT(i) BIT 13 drivers/leds/leds-nic78bx.c #define NIC78BX_USER1_GREEN_LED BIT(0) BIT 14 drivers/leds/leds-nic78bx.c #define NIC78BX_USER1_YELLOW_LED BIT(1) BIT 17 drivers/leds/leds-nic78bx.c #define NIC78BX_USER2_GREEN_LED BIT(2) BIT 18 drivers/leds/leds-nic78bx.c #define NIC78BX_USER2_YELLOW_LED BIT(3) BIT 34 drivers/leds/leds-ot200.c .mask = BIT(0), BIT 39 drivers/leds/leds-ot200.c .mask = BIT(1), BIT 44 drivers/leds/leds-ot200.c .mask = BIT(2), BIT 49 drivers/leds/leds-ot200.c .mask = BIT(6), BIT 54 drivers/leds/leds-ot200.c .mask = BIT(5), BIT 59 drivers/leds/leds-ot200.c .mask = BIT(4), BIT 64 drivers/leds/leds-ot200.c .mask = BIT(3), BIT 69 drivers/leds/leds-ot200.c .mask = BIT(2), BIT 74 drivers/leds/leds-ot200.c .mask = BIT(1), BIT 79 drivers/leds/leds-ot200.c .mask = BIT(0), BIT 133 drivers/leds/leds-ot200.c leds_back = BIT(1); /* turn on init led */ BIT 194 drivers/leds/leds-pca963x.c PCA963X_MODE1, *leds_on ? 0 : BIT(4)); BIT 436 drivers/leds/leds-pca963x.c i2c_smbus_write_byte_data(client, PCA963X_MODE1, BIT(4)); BIT 15 drivers/leds/leds-sc27xx-bltc.c #define SC27XX_BLTC_EN BIT(9) BIT 16 drivers/leds/leds-sc27xx-bltc.c #define SC27XX_RTC_EN BIT(7) BIT 17 drivers/leds/leds-sc27xx-bltc.c #define SC27XX_RGB_PD BIT(0) BIT 27 drivers/leds/leds-sc27xx-bltc.c #define SC27XX_LED_RUN BIT(0) BIT 28 drivers/leds/leds-sc27xx-bltc.c #define SC27XX_LED_TYPE BIT(1) BIT 1393 drivers/macintosh/via-pmu.c ints &= ~BIT(idx); BIT 1401 drivers/macintosh/via-pmu.c switch (BIT(idx)) { BIT 32 drivers/mailbox/armada-37xx-rwtm-mailbox.c #define SP_CMD_COMPLETE BIT(0) BIT 33 drivers/mailbox/armada-37xx-rwtm-mailbox.c #define SP_CMD_QUEUE_FULL_ACCESS BIT(17) BIT 34 drivers/mailbox/armada-37xx-rwtm-mailbox.c #define SP_CMD_QUEUE_FULL BIT(18) BIT 151 drivers/mailbox/bcm-flexrm-mailbox.c #define DME_STATUS_MEM_COR_ERR BIT(0) BIT 152 drivers/mailbox/bcm-flexrm-mailbox.c #define DME_STATUS_MEM_UCOR_ERR BIT(1) BIT 153 drivers/mailbox/bcm-flexrm-mailbox.c #define DME_STATUS_FIFO_UNDERFLOW BIT(2) BIT 154 drivers/mailbox/bcm-flexrm-mailbox.c #define DME_STATUS_FIFO_OVERFLOW BIT(3) BIT 155 drivers/mailbox/bcm-flexrm-mailbox.c #define DME_STATUS_RRESP_ERR BIT(4) BIT 156 drivers/mailbox/bcm-flexrm-mailbox.c #define DME_STATUS_BRESP_ERR BIT(5) BIT 943 drivers/mailbox/bcm-flexrm-mailbox.c BIT(CONTROL_ACTIVE_SHIFT)) BIT 1340 drivers/mailbox/bcm-flexrm-mailbox.c val |= BIT(MSI_ENABLE_SHIFT); BIT 1345 drivers/mailbox/bcm-flexrm-mailbox.c val = BIT(CONTROL_ACTIVE_SHIFT); BIT 1381 drivers/mailbox/bcm-flexrm-mailbox.c writel_relaxed(BIT(CONTROL_FLUSH_SHIFT), BIT 63 drivers/mailbox/bcm-pdc-mailbox.c #define RING_ALIGN BIT(RING_ALIGN_ORDER) BIT 66 drivers/mailbox/bcm-pdc-mailbox.c #define RX_BUF_ALIGN BIT(RX_BUF_ALIGN_ORDER) BIT 93 drivers/mailbox/bcm-pdc-mailbox.c #define PDC_RCVINTEN_0 BIT(PDC_RCVINT_0) BIT 108 drivers/mailbox/bcm-pdc-mailbox.c #define PDC_CKSUM_CTRL BIT(27) BIT 142 drivers/mailbox/bcm-pdc-mailbox.c #define D64_CTRL1_EOT BIT(28) /* end of descriptor table */ BIT 143 drivers/mailbox/bcm-pdc-mailbox.c #define D64_CTRL1_IOC BIT(29) /* interrupt on complete */ BIT 144 drivers/mailbox/bcm-pdc-mailbox.c #define D64_CTRL1_EOF BIT(30) /* end of frame */ BIT 145 drivers/mailbox/bcm-pdc-mailbox.c #define D64_CTRL1_SOF BIT(31) /* start of frame */ BIT 49 drivers/mailbox/bcm2835-mailbox.c #define ARM_MS_FULL BIT(31) BIT 50 drivers/mailbox/bcm2835-mailbox.c #define ARM_MS_EMPTY BIT(30) BIT 53 drivers/mailbox/bcm2835-mailbox.c #define ARM_MC_IHAVEDATAIRQEN BIT(0) BIT 40 drivers/mailbox/hi3660-mailbox.c #define MBOX_STATE_IDLE BIT(4) BIT 41 drivers/mailbox/hi3660-mailbox.c #define MBOX_STATE_READY BIT(5) BIT 42 drivers/mailbox/hi3660-mailbox.c #define MBOX_STATE_ACK BIT(7) BIT 108 drivers/mailbox/hi3660-mailbox.c writel(BIT(mchan->ack_irq), base + MBOX_ICLR_REG); BIT 145 drivers/mailbox/hi3660-mailbox.c writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG); BIT 149 drivers/mailbox/hi3660-mailbox.c if (val & BIT(mchan->ack_irq)) BIT 190 drivers/mailbox/hi3660-mailbox.c writel_relaxed(~BIT(mchan->dst_irq), base + MBOX_IMASK_REG); BIT 193 drivers/mailbox/hi3660-mailbox.c writel_relaxed(BIT(mchan->dst_irq), base + MBOX_DST_REG); BIT 203 drivers/mailbox/hi3660-mailbox.c writel(BIT(mchan->ack_irq), base + MBOX_SEND_REG); BIT 144 drivers/mailbox/hi6220-mailbox.c writel(BIT(mchan->dst_irq), DST_INT_RAW_REG(mbox->ipc)); BIT 186 drivers/mailbox/hi6220-mailbox.c writel(BIT(mchan->ack_irq), ACK_INT_CLR_REG(mbox->ipc)); BIT 201 drivers/mailbox/hi6220-mailbox.c writel(BIT(mchan->ack_irq), ACK_INT_ENA_REG(mbox->ipc)); BIT 211 drivers/mailbox/hi6220-mailbox.c writel(BIT(mchan->ack_irq), ACK_INT_DIS_REG(mbox->ipc)); BIT 21 drivers/mailbox/imx-mailbox.c #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x))) BIT 22 drivers/mailbox/imx-mailbox.c #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x))) BIT 23 drivers/mailbox/imx-mailbox.c #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x))) BIT 24 drivers/mailbox/imx-mailbox.c #define IMX_MU_xSR_BRDIP BIT(9) BIT 29 drivers/mailbox/imx-mailbox.c #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x))) BIT 31 drivers/mailbox/imx-mailbox.c #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x))) BIT 33 drivers/mailbox/imx-mailbox.c #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x))) BIT 35 drivers/mailbox/imx-mailbox.c #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x))) BIT 93 drivers/mailbox/mailbox-sti.c return mdev->enabled[instance] & BIT(channel); BIT 129 drivers/mailbox/mailbox-sti.c mdev->enabled[instance] |= BIT(channel); BIT 130 drivers/mailbox/mailbox-sti.c writel_relaxed(BIT(channel), base + STI_ENA_SET_OFFSET); BIT 144 drivers/mailbox/mailbox-sti.c mdev->enabled[instance] &= ~BIT(channel); BIT 145 drivers/mailbox/mailbox-sti.c writel_relaxed(BIT(channel), base + STI_ENA_CLR_OFFSET); BIT 157 drivers/mailbox/mailbox-sti.c writel_relaxed(BIT(channel), base + STI_IRQ_CLR_OFFSET); BIT 259 drivers/mailbox/mailbox-sti.c if (!(readl_relaxed(base + STI_ENA_VAL_OFFSET) & BIT(channel))) { BIT 265 drivers/mailbox/mailbox-sti.c if (readl_relaxed(base + STI_IRQ_VAL_OFFSET) & BIT(channel)) { BIT 283 drivers/mailbox/mailbox-sti.c writel_relaxed(BIT(channel), base + STI_IRQ_SET_OFFSET); BIT 21 drivers/mailbox/mailbox-xgene-slimpro.c #define MBOX_STATUS_AVAIL_MASK BIT(16) BIT 22 drivers/mailbox/mailbox-xgene-slimpro.c #define MBOX_STATUS_ACK_MASK BIT(0) BIT 6 drivers/mailbox/mailbox.h #define TXDONE_BY_IRQ BIT(0) /* controller has remote RTR irq */ BIT 7 drivers/mailbox/mailbox.h #define TXDONE_BY_POLL BIT(1) /* controller can read status of last TX */ BIT 8 drivers/mailbox/mailbox.h #define TXDONE_BY_ACK BIT(2) /* S/W ACK recevied by Client ticks the TX */ BIT 44 drivers/mailbox/mtk-cmdq-mailbox.c #define CMDQ_THR_STATUS_SUSPENDED BIT(1) BIT 45 drivers/mailbox/mtk-cmdq-mailbox.c #define CMDQ_THR_DO_WARM_RESET BIT(0) BIT 49 drivers/mailbox/mtk-cmdq-mailbox.c #define CMDQ_THR_IS_WAITING BIT(31) BIT 41 drivers/mailbox/qcom-apcs-ipc-mailbox.c return regmap_write(apcs->regmap, apcs->offset, BIT(idx)); BIT 18 drivers/mailbox/stm32-ipcc.c #define XCR_RXOIE BIT(0) BIT 19 drivers/mailbox/stm32-ipcc.c #define XCR_TXOIE BIT(16) BIT 35 drivers/mailbox/stm32-ipcc.c #define RX_BIT_CHAN(chan) BIT(chan) BIT 38 drivers/mailbox/stm32-ipcc.c #define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan)) BIT 43 drivers/mailbox/tegra-hsp.c #define HSP_SM_SHRD_MBOX_FULL BIT(31) BIT 136 drivers/mailbox/tegra-hsp.c return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0; BIT 228 drivers/mailbox/tegra-hsp.c hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); BIT 331 drivers/mailbox/tegra-hsp.c value |= BIT(db->master); BIT 354 drivers/mailbox/tegra-hsp.c value &= ~BIT(db->master); BIT 385 drivers/mailbox/tegra-hsp.c hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index); BIT 438 drivers/mailbox/tegra-hsp.c hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); BIT 440 drivers/mailbox/tegra-hsp.c hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index); BIT 477 drivers/mailbox/tegra-hsp.c hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); BIT 479 drivers/mailbox/tegra-hsp.c hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index); BIT 467 drivers/md/md-bitmap.c sb->state = cpu_to_le32(bitmap->flags & ~BIT(BITMAP_WRITE_ERROR)); BIT 2572 drivers/md/md.c bit_clear_unless(&mddev->sb_flags, BIT(MD_SB_CHANGE_PENDING), BIT 2573 drivers/md/md.c BIT(MD_SB_CHANGE_DEVS) | BIT 2574 drivers/md/md.c BIT(MD_SB_CHANGE_CLEAN)); BIT 2721 drivers/md/md.c !bit_clear_unless(&mddev->sb_flags, BIT(MD_SB_CHANGE_PENDING), BIT 2722 drivers/md/md.c BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_CLEAN))) BIT 8786 drivers/md/md.c BIT(MD_SB_CHANGE_PENDING) | BIT(MD_SB_CHANGE_DEVS)); BIT 9251 drivers/md/md.c BIT(MD_SB_CHANGE_CLEAN) | BIT(MD_SB_CHANGE_PENDING)); BIT 1646 drivers/md/raid1.c BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_PENDING)); BIT 1332 drivers/md/raid10.c BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_PENDING)); BIT 1664 drivers/md/raid10.c BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_PENDING)); BIT 1339 drivers/md/raid5-cache.c BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_PENDING)); BIT 2699 drivers/md/raid5.c BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_PENDING)); BIT 28 drivers/media/dvb-frontends/lnbh29.c #define LNBH29_STATUS_OLF BIT(0) BIT 29 drivers/media/dvb-frontends/lnbh29.c #define LNBH29_STATUS_OTF BIT(1) BIT 30 drivers/media/dvb-frontends/lnbh29.c #define LNBH29_STATUS_VMON BIT(2) BIT 31 drivers/media/dvb-frontends/lnbh29.c #define LNBH29_STATUS_PNG BIT(3) BIT 32 drivers/media/dvb-frontends/lnbh29.c #define LNBH29_STATUS_PDO BIT(4) BIT 15 drivers/media/dvb-frontends/lnbh29.h #define LNBH29_DATA_COMP BIT(3) BIT 23 drivers/media/dvb-frontends/mn88443x.c #define CPMON1_S_FSYNC BIT(5) BIT 24 drivers/media/dvb-frontends/mn88443x.c #define CPMON1_S_ERRMON BIT(4) BIT 25 drivers/media/dvb-frontends/mn88443x.c #define CPMON1_S_SIGOFF BIT(3) BIT 26 drivers/media/dvb-frontends/mn88443x.c #define CPMON1_S_W2LOCK BIT(2) BIT 27 drivers/media/dvb-frontends/mn88443x.c #define CPMON1_S_W1LOCK BIT(1) BIT 28 drivers/media/dvb-frontends/mn88443x.c #define CPMON1_S_DW1LOCK BIT(0) BIT 31 drivers/media/dvb-frontends/mn88443x.c #define BERCNFLG_S_BERVRDY BIT(5) BIT 32 drivers/media/dvb-frontends/mn88443x.c #define BERCNFLG_S_BERVCHK BIT(4) BIT 33 drivers/media/dvb-frontends/mn88443x.c #define BERCNFLG_S_BERDRDY BIT(3) BIT 34 drivers/media/dvb-frontends/mn88443x.c #define BERCNFLG_S_BERDCHK BIT(2) BIT 89 drivers/media/dvb-frontends/mn88443x.c #define PWDSET_OFDMPD_DOWN BIT(3) BIT 91 drivers/media/dvb-frontends/mn88443x.c #define PWDSET_PSKPD_DOWN BIT(1) BIT 119 drivers/media/dvb-frontends/mn88443x.c #define AGCSET2_T_IFPOLINV_INC BIT(0) BIT 120 drivers/media/dvb-frontends/mn88443x.c #define AGCSET2_T_RFPOLINV_INC BIT(1) BIT 152 drivers/media/dvb-frontends/mn88443x.c #define BERFLG_T_BERDRDY BIT(7) BIT 153 drivers/media/dvb-frontends/mn88443x.c #define BERFLG_T_BERDCHK BIT(6) BIT 154 drivers/media/dvb-frontends/mn88443x.c #define BERFLG_T_BERVRDYA BIT(5) BIT 155 drivers/media/dvb-frontends/mn88443x.c #define BERFLG_T_BERVCHKA BIT(4) BIT 156 drivers/media/dvb-frontends/mn88443x.c #define BERFLG_T_BERVRDYB BIT(3) BIT 157 drivers/media/dvb-frontends/mn88443x.c #define BERFLG_T_BERVCHKB BIT(2) BIT 158 drivers/media/dvb-frontends/mn88443x.c #define BERFLG_T_BERVRDYC BIT(1) BIT 159 drivers/media/dvb-frontends/mn88443x.c #define BERFLG_T_BERVCHKC BIT(0) BIT 166 drivers/media/dvb-frontends/mn88443x.c #define ERRFLG_T_BERDOVF BIT(7) BIT 167 drivers/media/dvb-frontends/mn88443x.c #define ERRFLG_T_BERVOVFA BIT(6) BIT 168 drivers/media/dvb-frontends/mn88443x.c #define ERRFLG_T_BERVOVFB BIT(5) BIT 169 drivers/media/dvb-frontends/mn88443x.c #define ERRFLG_T_BERVOVFC BIT(4) BIT 170 drivers/media/dvb-frontends/mn88443x.c #define ERRFLG_T_NERRFA BIT(3) BIT 171 drivers/media/dvb-frontends/mn88443x.c #define ERRFLG_T_NERRFB BIT(2) BIT 172 drivers/media/dvb-frontends/mn88443x.c #define ERRFLG_T_NERRFC BIT(1) BIT 173 drivers/media/dvb-frontends/mn88443x.c #define ERRFLG_T_NERRF BIT(0) BIT 11 drivers/media/dvb-frontends/rtl2832.c #define REG_MASK(b) (BIT(b + 1) - 1) BIT 188 drivers/media/i2c/adv7180.c #define ADV7180_FLAG_RESET_POWERED BIT(0) BIT 189 drivers/media/i2c/adv7180.c #define ADV7180_FLAG_V2 BIT(1) BIT 190 drivers/media/i2c/adv7180.c #define ADV7180_FLAG_MIPI_CSI2 BIT(2) BIT 191 drivers/media/i2c/adv7180.c #define ADV7180_FLAG_I2P BIT(3) BIT 388 drivers/media/i2c/adv7180.c if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { BIT 1086 drivers/media/i2c/adv7180.c .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) | BIT 1087 drivers/media/i2c/adv7180.c BIT(ADV7180_INPUT_CVBS_AIN2) | BIT 1088 drivers/media/i2c/adv7180.c BIT(ADV7180_INPUT_CVBS_AIN3) | BIT 1089 drivers/media/i2c/adv7180.c BIT(ADV7180_INPUT_CVBS_AIN4) | BIT 1090 drivers/media/i2c/adv7180.c BIT(ADV7180_INPUT_CVBS_AIN5) | BIT 1091 drivers/media/i2c/adv7180.c BIT(ADV7180_INPUT_CVBS_AIN6) | BIT 1092 drivers/media/i2c/adv7180.c BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) | BIT 1093 drivers/media/i2c/adv7180.c BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) | BIT 1094 drivers/media/i2c/adv7180.c BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) | BIT 1095 drivers/media/i2c/adv7180.c BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) | BIT 1096 drivers/media/i2c/adv7180.c BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6), BIT 1103 drivers/media/i2c/adv7180.c .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | BIT 1104 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN2) | BIT 1105 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN3) | BIT 1106 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN4) | BIT 1107 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | BIT 1108 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | BIT 1109 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | BIT 1110 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | BIT 1111 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4), BIT 1119 drivers/media/i2c/adv7180.c .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | BIT 1120 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN2) | BIT 1121 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN3) | BIT 1122 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN4) | BIT 1123 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | BIT 1124 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | BIT 1125 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3), BIT 1133 drivers/media/i2c/adv7180.c .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | BIT 1134 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN2) | BIT 1135 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN3) | BIT 1136 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN4) | BIT 1137 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN5) | BIT 1138 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN6) | BIT 1139 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN7) | BIT 1140 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN8) | BIT 1141 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | BIT 1142 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | BIT 1143 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | BIT 1144 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | BIT 1145 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | BIT 1146 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6), BIT 1154 drivers/media/i2c/adv7180.c .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | BIT 1155 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN2) | BIT 1156 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN7) | BIT 1157 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN8) | BIT 1158 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | BIT 1159 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | BIT 1160 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | BIT 1161 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), BIT 1169 drivers/media/i2c/adv7180.c .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | BIT 1170 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN2) | BIT 1171 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN3) | BIT 1172 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN4) | BIT 1173 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN7) | BIT 1174 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN8) | BIT 1175 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | BIT 1176 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | BIT 1177 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | BIT 1178 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | BIT 1179 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | BIT 1180 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | BIT 1181 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), BIT 1189 drivers/media/i2c/adv7180.c .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | BIT 1190 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN2) | BIT 1191 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN3) | BIT 1192 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN4) | BIT 1193 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN5) | BIT 1194 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN6) | BIT 1195 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN7) | BIT 1196 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN8) | BIT 1197 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | BIT 1198 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | BIT 1199 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | BIT 1200 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | BIT 1201 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | BIT 1202 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) | BIT 1203 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | BIT 1204 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | BIT 1205 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) | BIT 1206 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), BIT 1214 drivers/media/i2c/adv7180.c .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | BIT 1215 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN2) | BIT 1216 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN7) | BIT 1217 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN8) | BIT 1218 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | BIT 1219 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | BIT 1220 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | BIT 1221 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), BIT 1229 drivers/media/i2c/adv7180.c .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | BIT 1230 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN2) | BIT 1231 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN3) | BIT 1232 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN4) | BIT 1233 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN7) | BIT 1234 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_CVBS_AIN8) | BIT 1235 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | BIT 1236 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | BIT 1237 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | BIT 1238 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | BIT 1239 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | BIT 1240 drivers/media/i2c/adv7180.c BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), BIT 317 drivers/media/i2c/adv748x/adv748x-hdmi.c bt->polarities = (polarity & BIT(4) ? V4L2_DV_VSYNC_POS_POL : 0) | BIT 318 drivers/media/i2c/adv748x/adv748x-hdmi.c (polarity & BIT(5) ? V4L2_DV_HSYNC_POS_POL : 0); BIT 211 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_IO_PD_RX_EN BIT(6) BIT 214 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_IO_REG_01_PWRDN_MASK (BIT(7) | BIT(6)) BIT 215 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_IO_REG_01_PWRDN2B BIT(7) /* CEC Wakeup Support */ BIT 216 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_IO_REG_01_PWRDNB BIT(6) /* CEC Wakeup Support */ BIT 219 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_IO_REG_04_FORCE_FR BIT(0) /* Force CP free-run */ BIT 228 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_IO_10_CSI4_EN BIT(7) BIT 229 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_IO_10_CSI1_EN BIT(6) BIT 230 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_IO_10_PIX_OUT_EN BIT(5) BIT 231 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_IO_10_CSI4_IN_SEL_AFE BIT(3) BIT 237 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_IO_REG_F2_READ_AUTO_INC BIT(0) BIT 251 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_HDMI_LW1_VERT_FILTER BIT(7) BIT 252 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_HDMI_LW1_DE_REGEN BIT(5) BIT 259 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_HDMI_F1H1_INTERLACED BIT(5) BIT 287 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_REPEATER_EDID_CTL_EN BIT(0) /* man_edid_a_enable */ BIT 316 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_SDP_DEF_VAL_EN BIT(0) /* Force free run mode */ BIT 317 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_SDP_DEF_VAL_AUTO_EN BIT(1) /* Free run when no signal */ BIT 335 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_SDP_RO_10_IN_LOCK BIT(0) BIT 339 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_CP_PAT_GEN_EN BIT(7) BIT 366 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_CP_VID_ADJ_ENABLE BIT(7) /* Enable colour controls */ BIT 369 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_CP_DE_POS_HIGH_SET BIT(6) BIT 374 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_CP_VID_ADJ_2_INTERLACED BIT(6) BIT 375 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_CP_VID_ADJ_2_INTERLACED_3D BIT(4) BIT 378 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_CP_CLMP_POS_DIS_AUTO BIT(0) /* dis_auto_param_buff */ BIT 385 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_CSI_FS_AS_LS_UNKNOWN BIT(6) /* Undocumented bit */ BIT 518 drivers/media/i2c/adv7604.c gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); BIT 615 drivers/media/i2c/adv7604.c if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) BIT 630 drivers/media/i2c/adv7604.c if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) BIT 3003 drivers/media/i2c/adv7604.c .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | BIT 3004 drivers/media/i2c/adv7604.c BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | BIT 3005 drivers/media/i2c/adv7604.c BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | BIT 3006 drivers/media/i2c/adv7604.c BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | BIT 3007 drivers/media/i2c/adv7604.c BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | BIT 3008 drivers/media/i2c/adv7604.c BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | BIT 3009 drivers/media/i2c/adv7604.c BIT(ADV7604_PAGE_VDP), BIT 3050 drivers/media/i2c/adv7604.c .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | BIT 3051 drivers/media/i2c/adv7604.c BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | BIT 3052 drivers/media/i2c/adv7604.c BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | BIT 3053 drivers/media/i2c/adv7604.c BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), BIT 3094 drivers/media/i2c/adv7604.c .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | BIT 3095 drivers/media/i2c/adv7604.c BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | BIT 3096 drivers/media/i2c/adv7604.c BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | BIT 3097 drivers/media/i2c/adv7604.c BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), BIT 3519 drivers/media/i2c/adv7604.c if (!(BIT(i) & state->info->page_mask)) BIT 199 drivers/media/i2c/cx25840/cx25840-core.c (BIT(V4L2_SUBDEV_IO_PIN_DISABLE) | BIT 200 drivers/media/i2c/cx25840/cx25840-core.c BIT(V4L2_SUBDEV_IO_PIN_INPUT))) { BIT 206 drivers/media/i2c/cx25840/cx25840-core.c BIT(V4L2_SUBDEV_IO_PIN_ACTIVE_LOW)) { BIT 222 drivers/media/i2c/cx25840/cx25840-core.c if (p[i].flags & BIT(V4L2_SUBDEV_IO_PIN_SET_VALUE)) { BIT 234 drivers/media/i2c/cx25840/cx25840-core.c if (p[i].flags & BIT(V4L2_SUBDEV_IO_PIN_DISABLE)) BIT 243 drivers/media/i2c/cx25840/cx25840-core.c if (p[i].flags & BIT(V4L2_SUBDEV_IO_PIN_SET_VALUE)) { BIT 261 drivers/media/i2c/cx25840/cx25840-core.c if (p[i].flags & BIT(V4L2_SUBDEV_IO_PIN_SET_VALUE)) { BIT 279 drivers/media/i2c/cx25840/cx25840-core.c if (p[i].flags & BIT(V4L2_SUBDEV_IO_PIN_SET_VALUE)) { BIT 297 drivers/media/i2c/cx25840/cx25840-core.c if (p[i].flags & BIT(V4L2_SUBDEV_IO_PIN_SET_VALUE)) { BIT 338 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 |= BIT(2); BIT 340 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 &= ~BIT(2); BIT 345 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 |= BIT(5); BIT 347 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 &= ~BIT(5); BIT 352 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 |= BIT(4); BIT 354 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 &= ~BIT(4); BIT 359 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 |= BIT(0); BIT 361 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 &= ~BIT(0); BIT 371 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 |= BIT(6); BIT 373 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 &= ~BIT(6); BIT 378 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 |= BIT(1); BIT 380 drivers/media/i2c/cx25840/cx25840-core.c *voutctrl4 &= ~BIT(1); BIT 416 drivers/media/i2c/cx25840/cx25840-core.c if (p[i].flags & BIT(V4L2_SUBDEV_IO_PIN_DISABLE)) BIT 417 drivers/media/i2c/cx25840/cx25840-core.c pinctrl[0] &= ~BIT(6); BIT 419 drivers/media/i2c/cx25840/cx25840-core.c pinctrl[0] |= BIT(6); BIT 429 drivers/media/i2c/cx25840/cx25840-core.c BIT(V4L2_SUBDEV_IO_PIN_ACTIVE_LOW)); BIT 445 drivers/media/i2c/cx25840/cx25840-core.c if (p[i].flags & BIT(V4L2_SUBDEV_IO_PIN_DISABLE)) BIT 446 drivers/media/i2c/cx25840/cx25840-core.c pinctrl[1] &= ~BIT(0); BIT 448 drivers/media/i2c/cx25840/cx25840-core.c pinctrl[1] |= BIT(0); BIT 458 drivers/media/i2c/cx25840/cx25840-core.c BIT(V4L2_SUBDEV_IO_PIN_ACTIVE_LOW)); BIT 474 drivers/media/i2c/cx25840/cx25840-core.c if (p[i].flags & BIT(V4L2_SUBDEV_IO_PIN_DISABLE)) BIT 475 drivers/media/i2c/cx25840/cx25840-core.c pinctrl[2] &= ~BIT(2); BIT 477 drivers/media/i2c/cx25840/cx25840-core.c pinctrl[2] |= BIT(2); BIT 613 drivers/media/i2c/cx25840/cx25840-core.c (voc)[idx] |= BIT(bit); \ BIT 615 drivers/media/i2c/cx25840/cx25840-core.c (voc)[idx] &= ~BIT(bit); \ BIT 864 drivers/media/i2c/et8ek8/et8ek8_driver.c val |= BIT(4); BIT 866 drivers/media/i2c/et8ek8/et8ek8_driver.c val &= ~BIT(4); BIT 132 drivers/media/i2c/mt9m111.c #define MT9M111_RM_PWR_MASK BIT(10) BIT 1304 drivers/media/i2c/mt9m111.c ~(BIT(V4L2_COLORFX_NONE) | BIT 1305 drivers/media/i2c/mt9m111.c BIT(V4L2_COLORFX_BW) | BIT 1306 drivers/media/i2c/mt9m111.c BIT(V4L2_COLORFX_SEPIA) | BIT 1307 drivers/media/i2c/mt9m111.c BIT(V4L2_COLORFX_NEGATIVE) | BIT 1308 drivers/media/i2c/mt9m111.c BIT(V4L2_COLORFX_SOLARIZATION)), BIT 60 drivers/media/i2c/mt9v111.c #define MT9V111_IFP_R06_OPMODE_CTRL_AWB_EN BIT(1) BIT 61 drivers/media/i2c/mt9v111.c #define MT9V111_IFP_R06_OPMODE_CTRL_AE_EN BIT(14) BIT 63 drivers/media/i2c/mt9v111.c #define MT9V111_IFP_R07_IFP_RESET_MASK BIT(0) BIT 65 drivers/media/i2c/mt9v111.c #define MT9V111_IFP_R08_OUTFMT_CTRL_FLICKER BIT(11) BIT 66 drivers/media/i2c/mt9v111.c #define MT9V111_IFP_R08_OUTFMT_CTRL_PCLK BIT(5) BIT 68 drivers/media/i2c/mt9v111.c #define MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_CBCR BIT(0) BIT 69 drivers/media/i2c/mt9v111.c #define MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_YC BIT(1) BIT 78 drivers/media/i2c/mt9v111.c #define MT9V111_IFP_DECIMATION_FREEZE BIT(15) BIT 93 drivers/media/i2c/mt9v111.c #define MT9V111_CORE_R07_OUT_CTRL_SAMPLE BIT(4) BIT 97 drivers/media/i2c/mt9v111.c #define MT9V111_CORE_R0D_CORE_RESET_MASK BIT(0) BIT 78 drivers/media/i2c/ov13858.c #define OV13858_TEST_PATTERN_ENABLE BIT(7) BIT 184 drivers/media/i2c/ov2659.c #define TEST_PATTERN_ENABLE BIT(7) BIT 339 drivers/media/i2c/ov2680.c hv_flip = (format2 & BIT(2) << 1) | (format1 & BIT(2)); BIT 350 drivers/media/i2c/ov2680.c ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT1, BIT(2), BIT(2)); BIT 361 drivers/media/i2c/ov2680.c ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT1, BIT(2), BIT(0)); BIT 372 drivers/media/i2c/ov2680.c ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT2, BIT(2), BIT(2)); BIT 383 drivers/media/i2c/ov2680.c ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT2, BIT(2), BIT(0)); BIT 395 drivers/media/i2c/ov2680.c return ov2680_mod_reg(sensor, OV2680_REG_ISP_CTRL00, BIT(7), 0); BIT 401 drivers/media/i2c/ov2680.c ret = ov2680_mod_reg(sensor, OV2680_REG_ISP_CTRL00, BIT(7), BIT(7)); BIT 414 drivers/media/i2c/ov2680.c ret = ov2680_mod_reg(sensor, OV2680_REG_R_MANUAL, BIT(1), BIT 415 drivers/media/i2c/ov2680.c auto_gain ? 0 : BIT(1)); BIT 447 drivers/media/i2c/ov2680.c ret = ov2680_mod_reg(sensor, OV2680_REG_R_MANUAL, BIT(0), BIT 448 drivers/media/i2c/ov2680.c auto_exp ? 0 : BIT(0)); BIT 29 drivers/media/i2c/ov2685.c #define SC_CTRL_MODE_STREAMING BIT(0) BIT 805 drivers/media/i2c/ov5640.c #define OV5640_PLL_CTRL3_PLL_ROOT_DIV_2 BIT(4) BIT 1129 drivers/media/i2c/ov5640.c BIT(0), on ? 0 : BIT(0)); BIT 1197 drivers/media/i2c/ov5640.c BIT(1), on ? 0 : BIT(1)); BIT 1549 drivers/media/i2c/ov5640.c return temp & BIT(0); BIT 1561 drivers/media/i2c/ov5640.c BIT(0), enable ? BIT(0) : 0); BIT 1570 drivers/media/i2c/ov5640.c BIT(0), enable ? BIT(0) : 0); BIT 2319 drivers/media/i2c/ov5640.c BIT(5), is_jpeg ? BIT(5) : 0); BIT 2330 drivers/media/i2c/ov5640.c BIT(4) | BIT(3) | BIT(2), BIT 2331 drivers/media/i2c/ov5640.c is_jpeg ? 0 : (BIT(4) | BIT(3) | BIT(2))); BIT 2341 drivers/media/i2c/ov5640.c BIT(5) | BIT(3), BIT 2342 drivers/media/i2c/ov5640.c is_jpeg ? (BIT(5) | BIT(3)) : 0); BIT 2355 drivers/media/i2c/ov5640.c BIT(0), BIT(0)); BIT 2360 drivers/media/i2c/ov5640.c ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(0), 0); BIT 2372 drivers/media/i2c/ov5640.c BIT(2), BIT(2)); BIT 2378 drivers/media/i2c/ov5640.c ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(2), 0); BIT 2390 drivers/media/i2c/ov5640.c BIT(1), BIT(1)); BIT 2400 drivers/media/i2c/ov5640.c ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(1), 0); BIT 2411 drivers/media/i2c/ov5640.c BIT(0), awb ? 0 : 1); BIT 2486 drivers/media/i2c/ov5640.c #define OV5640_TEST_ENABLE BIT(7) BIT 2487 drivers/media/i2c/ov5640.c #define OV5640_TEST_ROLLING BIT(6) /* rolling horizontal bar */ BIT 2488 drivers/media/i2c/ov5640.c #define OV5640_TEST_TRANSPARENT BIT(5) BIT 2489 drivers/media/i2c/ov5640.c #define OV5640_TEST_SQUARE_BW BIT(4) /* black & white squares */ BIT 2519 drivers/media/i2c/ov5640.c ret = ov5640_mod_reg(sensor, OV5640_REG_HZ5060_CTRL01, BIT(7), BIT 2521 drivers/media/i2c/ov5640.c 0 : BIT(7)); BIT 2525 drivers/media/i2c/ov5640.c return ov5640_mod_reg(sensor, OV5640_REG_HZ5060_CTRL00, BIT(2), BIT 2527 drivers/media/i2c/ov5640.c BIT(2) : 0); BIT 2547 drivers/media/i2c/ov5640.c BIT(2) | BIT(1), BIT 2549 drivers/media/i2c/ov5640.c (BIT(2) | BIT(1)) : 0); BIT 2562 drivers/media/i2c/ov5640.c BIT(2) | BIT(1), BIT 2564 drivers/media/i2c/ov5640.c (BIT(2) | BIT(1)) : 0); BIT 47 drivers/media/i2c/ov5645.c #define OV5645_AWB_MANUAL_ENABLE BIT(0) BIT 49 drivers/media/i2c/ov5645.c #define OV5645_AEC_MANUAL_ENABLE BIT(0) BIT 50 drivers/media/i2c/ov5645.c #define OV5645_AGC_MANUAL_ENABLE BIT(1) BIT 52 drivers/media/i2c/ov5645.c #define OV5645_SENSOR_VFLIP BIT(1) BIT 53 drivers/media/i2c/ov5645.c #define OV5645_ISP_VFLIP BIT(2) BIT 55 drivers/media/i2c/ov5645.c #define OV5645_SENSOR_MIRROR BIT(1) BIT 60 drivers/media/i2c/ov5645.c #define OV5645_TEST_PATTERN_ENABLE BIT(7) BIT 38 drivers/media/i2c/ov5647.c #define MIPI_CTRL00_CLOCK_LANE_GATE BIT(5) BIT 39 drivers/media/i2c/ov5647.c #define MIPI_CTRL00_BUS_IDLE BIT(2) BIT 40 drivers/media/i2c/ov5647.c #define MIPI_CTRL00_CLOCK_LANE_DISABLE BIT(0) BIT 59 drivers/media/i2c/ov5670.c #define OV5670_TEST_PATTERN_ENABLE BIT(3) BIT 63 drivers/media/i2c/ov5675.c #define OV5675_TEST_PATTERN_ENABLE BIT(7) BIT 35 drivers/media/i2c/ov5695.c #define OV5695_MODE_STREAMING BIT(0) BIT 120 drivers/media/i2c/ov6650.c #define HUE_EN BIT(5) BIT 135 drivers/media/i2c/ov6650.c #define COMA_RESET BIT(7) BIT 136 drivers/media/i2c/ov6650.c #define COMA_QCIF BIT(5) BIT 137 drivers/media/i2c/ov6650.c #define COMA_RAW_RGB BIT(4) BIT 138 drivers/media/i2c/ov6650.c #define COMA_RGB BIT(3) BIT 139 drivers/media/i2c/ov6650.c #define COMA_BW BIT(2) BIT 140 drivers/media/i2c/ov6650.c #define COMA_WORD_SWAP BIT(1) BIT 141 drivers/media/i2c/ov6650.c #define COMA_BYTE_SWAP BIT(0) BIT 144 drivers/media/i2c/ov6650.c #define COMB_FLIP_V BIT(7) BIT 145 drivers/media/i2c/ov6650.c #define COMB_FLIP_H BIT(5) BIT 146 drivers/media/i2c/ov6650.c #define COMB_BAND_FILTER BIT(4) BIT 147 drivers/media/i2c/ov6650.c #define COMB_AWB BIT(2) BIT 148 drivers/media/i2c/ov6650.c #define COMB_AGC BIT(1) BIT 149 drivers/media/i2c/ov6650.c #define COMB_AEC BIT(0) BIT 152 drivers/media/i2c/ov6650.c #define COML_ONE_CHANNEL BIT(7) BIT 159 drivers/media/i2c/ov6650.c #define COMF_HREF_LOW BIT(4) BIT 161 drivers/media/i2c/ov6650.c #define COMJ_PCLK_RISING BIT(4) BIT 162 drivers/media/i2c/ov6650.c #define COMJ_VSYNC_HIGH BIT(0) BIT 39 drivers/media/i2c/ov7251.c #define OV7251_TIMING_FORMAT1_VFLIP BIT(2) BIT 41 drivers/media/i2c/ov7251.c #define OV7251_TIMING_FORMAT2_MIRROR BIT(2) BIT 43 drivers/media/i2c/ov7251.c #define OV7251_PRE_ISP_00_TEST_PATTERN BIT(7) BIT 1555 drivers/media/i2c/ov7670.c value & BIT(0) ? TEST_PATTTERN_0 : 0); BIT 1560 drivers/media/i2c/ov7670.c value & BIT(1) ? TEST_PATTTERN_1 : 0); BIT 62 drivers/media/i2c/ov8856.c #define OV8856_TEST_PATTERN_ENABLE BIT(7) BIT 202 drivers/media/i2c/s5k5baf.c #define AALG_ALL_EN BIT(0) BIT 203 drivers/media/i2c/s5k5baf.c #define AALG_AE_EN BIT(1) BIT 204 drivers/media/i2c/s5k5baf.c #define AALG_DIVLEI_EN BIT(2) BIT 205 drivers/media/i2c/s5k5baf.c #define AALG_WB_EN BIT(3) BIT 206 drivers/media/i2c/s5k5baf.c #define AALG_USE_WB_FOR_ISP BIT(4) BIT 207 drivers/media/i2c/s5k5baf.c #define AALG_FLICKER_EN BIT(5) BIT 208 drivers/media/i2c/s5k5baf.c #define AALG_FIT_EN BIT(6) BIT 209 drivers/media/i2c/s5k5baf.c #define AALG_WRHW_EN BIT(7) BIT 867 drivers/media/i2c/smiapp/smiapp-core.c sensor->default_mbus_frame_fmts &= ~BIT(i); BIT 40 drivers/media/i2c/st-mipid02.c #define CLK_ENABLE BIT(0) BIT 42 drivers/media/i2c/st-mipid02.c #define CLK_MIPI_CSI BIT(1) BIT 44 drivers/media/i2c/st-mipid02.c #define DATA_ENABLE BIT(0) BIT 46 drivers/media/i2c/st-mipid02.c #define DATA_MIPI_CSI BIT(0) BIT 48 drivers/media/i2c/st-mipid02.c #define MODE_DATA_SWAP BIT(2) BIT 49 drivers/media/i2c/st-mipid02.c #define MODE_NO_BYPASS BIT(6) BIT 51 drivers/media/i2c/st-mipid02.c #define MODE_HSYNC_ACTIVE_HIGH BIT(1) BIT 52 drivers/media/i2c/st-mipid02.c #define MODE_VSYNC_ACTIVE_HIGH BIT(2) BIT 54 drivers/media/i2c/st-mipid02.c #define SELECTION_MANUAL_DATA BIT(2) BIT 55 drivers/media/i2c/st-mipid02.c #define SELECTION_MANUAL_WIDTH BIT(3) BIT 1543 drivers/media/i2c/tda1997x.c if (reg & BIT(AUDCFG_TYPE_DST)) BIT 1545 drivers/media/i2c/tda1997x.c if (reg & BIT(AUDCFG_TYPE_OBA)) BIT 1547 drivers/media/i2c/tda1997x.c if (reg & BIT(AUDCFG_TYPE_HBR)) BIT 1549 drivers/media/i2c/tda1997x.c if (reg & BIT(AUDCFG_TYPE_PCM)) BIT 125 drivers/media/i2c/tda1997x_regs.h #define DETECT_UTIL BIT(7) /* utility of HDMI level */ BIT 126 drivers/media/i2c/tda1997x_regs.h #define DETECT_HPD BIT(6) /* HPD of HDMI level */ BIT 127 drivers/media/i2c/tda1997x_regs.h #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */ BIT 128 drivers/media/i2c/tda1997x_regs.h #define DETECT_5V_B BIT(1) /* 5V present on input B */ BIT 129 drivers/media/i2c/tda1997x_regs.h #define DETECT_5V_A BIT(0) /* 5V present on input A */ BIT 132 drivers/media/i2c/tda1997x_regs.h #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */ BIT 133 drivers/media/i2c/tda1997x_regs.h #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */ BIT 134 drivers/media/i2c/tda1997x_regs.h #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */ BIT 135 drivers/media/i2c/tda1997x_regs.h #define INPUT_SEL_B BIT(0) /* 0=inputA 1=inputB */ BIT 148 drivers/media/i2c/tda1997x_regs.h #define SVC_MODE_RAMP BIT(3) /* 0=colorbar 1=ramp */ BIT 149 drivers/media/i2c/tda1997x_regs.h #define SVC_MODE_PAL BIT(2) /* 0=NTSC(480i/p) 1=PAL(576i/p) */ BIT 150 drivers/media/i2c/tda1997x_regs.h #define SVC_MODE_INT_PROG BIT(1) /* 0=interlaced 1=progressive */ BIT 151 drivers/media/i2c/tda1997x_regs.h #define SVC_MODE_SM_ON BIT(0) /* Enable color bars and tone gen */ BIT 154 drivers/media/i2c/tda1997x_regs.h #define HPD_MAN_CTRL_HPD_PULSE BIT(7) /* HPD Pulse low 110ms */ BIT 155 drivers/media/i2c/tda1997x_regs.h #define HPD_MAN_CTRL_5VEN BIT(2) /* Output 5V */ BIT 156 drivers/media/i2c/tda1997x_regs.h #define HPD_MAN_CTRL_HPD_B BIT(1) /* Assert HPD High for Input A */ BIT 157 drivers/media/i2c/tda1997x_regs.h #define HPD_MAN_CTRL_HPD_A BIT(0) /* Assert HPD High for Input A */ BIT 160 drivers/media/i2c/tda1997x_regs.h #define RT_MAN_CTRL_RT_AUTO BIT(7) BIT 161 drivers/media/i2c/tda1997x_regs.h #define RT_MAN_CTRL_RT BIT(6) BIT 162 drivers/media/i2c/tda1997x_regs.h #define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */ BIT 163 drivers/media/i2c/tda1997x_regs.h #define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */ BIT 166 drivers/media/i2c/tda1997x_regs.h #define VDP_CTRL_COMPDEL_BP BIT(5) /* bypass compdel */ BIT 167 drivers/media/i2c/tda1997x_regs.h #define VDP_CTRL_FORMATTER_BP BIT(4) /* bypass formatter */ BIT 168 drivers/media/i2c/tda1997x_regs.h #define VDP_CTRL_PREFILTER_BP BIT(1) /* bypass prefilter */ BIT 169 drivers/media/i2c/tda1997x_regs.h #define VDP_CTRL_MATRIX_BP BIT(0) /* bypass matrix conversion */ BIT 172 drivers/media/i2c/tda1997x_regs.h #define VHREF_INT_DET BIT(7) /* interlace detect: 1=alt 0=frame */ BIT 185 drivers/media/i2c/tda1997x_regs.h #define VHREF_VREF_SRC_STD BIT(2) /* 1=from standard 0=manual */ BIT 186 drivers/media/i2c/tda1997x_regs.h #define VHREF_HREF_SRC_STD BIT(1) /* 1=from standard 0=manual */ BIT 187 drivers/media/i2c/tda1997x_regs.h #define VHREF_HSYNC_SEL_HS BIT(0) /* 1=HS 0=VS */ BIT 190 drivers/media/i2c/tda1997x_regs.h #define AUDIO_OUT_ENABLE_ACLK BIT(5) BIT 191 drivers/media/i2c/tda1997x_regs.h #define AUDIO_OUT_ENABLE_WS BIT(4) BIT 192 drivers/media/i2c/tda1997x_regs.h #define AUDIO_OUT_ENABLE_AP3 BIT(3) BIT 193 drivers/media/i2c/tda1997x_regs.h #define AUDIO_OUT_ENABLE_AP2 BIT(2) BIT 194 drivers/media/i2c/tda1997x_regs.h #define AUDIO_OUT_ENABLE_AP1 BIT(1) BIT 195 drivers/media/i2c/tda1997x_regs.h #define AUDIO_OUT_ENABLE_AP0 BIT(0) BIT 235 drivers/media/i2c/tda1997x_regs.h #define HDMI_FLAGS_AUDIO BIT(7) /* Audio packet in last videoframe */ BIT 236 drivers/media/i2c/tda1997x_regs.h #define HDMI_FLAGS_HDMI BIT(6) /* HDMI detected */ BIT 237 drivers/media/i2c/tda1997x_regs.h #define HDMI_FLAGS_EESS BIT(5) /* EESS detected */ BIT 238 drivers/media/i2c/tda1997x_regs.h #define HDMI_FLAGS_HDCP BIT(4) /* HDCP detected */ BIT 239 drivers/media/i2c/tda1997x_regs.h #define HDMI_FLAGS_AVMUTE BIT(3) /* AVMUTE */ BIT 240 drivers/media/i2c/tda1997x_regs.h #define HDMI_FLAGS_AUD_LAYOUT BIT(2) /* Layout status Audio sample packet */ BIT 241 drivers/media/i2c/tda1997x_regs.h #define HDMI_FLAGS_AUD_FIFO_OF BIT(1) /* FIFO read/write pointers crossed */ BIT 242 drivers/media/i2c/tda1997x_regs.h #define HDMI_FLAGS_AUD_FIFO_LOW BIT(0) /* FIFO read ptr within 2 of write */ BIT 270 drivers/media/i2c/tda1997x_regs.h #define CLK_CFG_INV_OUT_CLK BIT(7) BIT 271 drivers/media/i2c/tda1997x_regs.h #define CLK_CFG_INV_BUS_CLK BIT(6) BIT 272 drivers/media/i2c/tda1997x_regs.h #define CLK_CFG_SEL_ACLK_EN BIT(1) BIT 273 drivers/media/i2c/tda1997x_regs.h #define CLK_CFG_SEL_ACLK BIT(0) BIT 299 drivers/media/i2c/tda1997x_regs.h #define HDCP_DE_REGEN_EN BIT(5) /* enable regen mode */ BIT 334 drivers/media/i2c/tda1997x_regs.h #define CGU_DBG_XO_FRO_SEL BIT(2) BIT 335 drivers/media/i2c/tda1997x_regs.h #define CGU_DBG_VDP_CLK_SEL BIT(1) BIT 336 drivers/media/i2c/tda1997x_regs.h #define CGU_DBG_PIX_CLK_SEL BIT(0) BIT 339 drivers/media/i2c/tda1997x_regs.h #define MAN_DIS_OUT_BUF BIT(7) BIT 340 drivers/media/i2c/tda1997x_regs.h #define MAN_DIS_ANA_PATH BIT(6) BIT 341 drivers/media/i2c/tda1997x_regs.h #define MAN_DIS_HDCP BIT(5) BIT 342 drivers/media/i2c/tda1997x_regs.h #define MAN_DIS_TMDS_ENC BIT(4) BIT 343 drivers/media/i2c/tda1997x_regs.h #define MAN_DIS_TMDS_FLOW BIT(3) BIT 344 drivers/media/i2c/tda1997x_regs.h #define MAN_RST_HDCP BIT(2) BIT 345 drivers/media/i2c/tda1997x_regs.h #define MAN_RST_TMDS_ENC BIT(1) BIT 346 drivers/media/i2c/tda1997x_regs.h #define MAN_RST_TMDS_FLOW BIT(0) BIT 356 drivers/media/i2c/tda1997x_regs.h #define AUDIO_CLOCK_PLL_PD BIT(7) /* powerdown PLL */ BIT 375 drivers/media/i2c/tda1997x_regs.h #define EDID_ENABLE_NACK_OFF BIT(7) BIT 376 drivers/media/i2c/tda1997x_regs.h #define EDID_ENABLE_EDID_ONLY BIT(6) BIT 377 drivers/media/i2c/tda1997x_regs.h #define EDID_ENABLE_B_EN BIT(1) BIT 378 drivers/media/i2c/tda1997x_regs.h #define EDID_ENABLE_A_EN BIT(0) BIT 385 drivers/media/i2c/tda1997x_regs.h #define HPD_POWER_EDID_ONLY BIT(1) BIT 388 drivers/media/i2c/tda1997x_regs.h #define HPD_AUTO_READ_EDID BIT(7) BIT 389 drivers/media/i2c/tda1997x_regs.h #define HPD_AUTO_HPD_F3TECH BIT(5) BIT 390 drivers/media/i2c/tda1997x_regs.h #define HPD_AUTO_HP_OTHER BIT(4) BIT 391 drivers/media/i2c/tda1997x_regs.h #define HPD_AUTO_HPD_UNSEL BIT(3) BIT 392 drivers/media/i2c/tda1997x_regs.h #define HPD_AUTO_HPD_ALL_CH BIT(2) BIT 393 drivers/media/i2c/tda1997x_regs.h #define HPD_AUTO_HPD_PRV_CH BIT(1) BIT 394 drivers/media/i2c/tda1997x_regs.h #define HPD_AUTO_HPD_NEW_CH BIT(0) BIT 433 drivers/media/i2c/tda1997x_regs.h #define INTERRUPT_AFE BIT(7) /* AFE module */ BIT 434 drivers/media/i2c/tda1997x_regs.h #define INTERRUPT_HDCP BIT(6) /* HDCP module */ BIT 435 drivers/media/i2c/tda1997x_regs.h #define INTERRUPT_AUDIO BIT(5) /* Audio module */ BIT 436 drivers/media/i2c/tda1997x_regs.h #define INTERRUPT_INFO BIT(4) /* Infoframe module */ BIT 437 drivers/media/i2c/tda1997x_regs.h #define INTERRUPT_MODE BIT(3) /* HDMI mode module */ BIT 438 drivers/media/i2c/tda1997x_regs.h #define INTERRUPT_RATE BIT(2) /* rate module */ BIT 439 drivers/media/i2c/tda1997x_regs.h #define INTERRUPT_DDC BIT(1) /* DDC module */ BIT 440 drivers/media/i2c/tda1997x_regs.h #define INTERRUPT_SUS BIT(0) /* SUS module */ BIT 443 drivers/media/i2c/tda1997x_regs.h #define MASK_HDCP_MTP BIT(7) /* HDCP MTP busy */ BIT 444 drivers/media/i2c/tda1997x_regs.h #define MASK_HDCP_DLMTP BIT(4) /* HDCP end download MTP to SRAM */ BIT 445 drivers/media/i2c/tda1997x_regs.h #define MASK_HDCP_DLRAM BIT(3) /* HDCP end download keys from SRAM */ BIT 446 drivers/media/i2c/tda1997x_regs.h #define MASK_HDCP_ENC BIT(2) /* HDCP ENC */ BIT 447 drivers/media/i2c/tda1997x_regs.h #define MASK_STATE_C5 BIT(1) /* HDCP State C5 reached */ BIT 448 drivers/media/i2c/tda1997x_regs.h #define MASK_AKSV BIT(0) /* AKSV received (start of auth) */ BIT 451 drivers/media/i2c/tda1997x_regs.h #define MASK_RATE_B_DRIFT BIT(7) /* Rate measurement drifted */ BIT 452 drivers/media/i2c/tda1997x_regs.h #define MASK_RATE_B_ST BIT(6) /* Rate measurement stability change */ BIT 453 drivers/media/i2c/tda1997x_regs.h #define MASK_RATE_B_ACT BIT(5) /* Rate measurement activity change */ BIT 454 drivers/media/i2c/tda1997x_regs.h #define MASK_RATE_B_PST BIT(4) /* Rate measreument presence change */ BIT 455 drivers/media/i2c/tda1997x_regs.h #define MASK_RATE_A_DRIFT BIT(3) /* Rate measurement drifted */ BIT 456 drivers/media/i2c/tda1997x_regs.h #define MASK_RATE_A_ST BIT(2) /* Rate measurement stability change */ BIT 457 drivers/media/i2c/tda1997x_regs.h #define MASK_RATE_A_ACT BIT(1) /* Rate measurement presence change */ BIT 458 drivers/media/i2c/tda1997x_regs.h #define MASK_RATE_A_PST BIT(0) /* Rate measreument presence change */ BIT 461 drivers/media/i2c/tda1997x_regs.h #define MASK_MPT BIT(7) /* Config MTP end of process */ BIT 462 drivers/media/i2c/tda1997x_regs.h #define MASK_FMT BIT(5) /* Video format changed */ BIT 463 drivers/media/i2c/tda1997x_regs.h #define MASK_RT_PULSE BIT(4) /* End of termination resistance pulse */ BIT 464 drivers/media/i2c/tda1997x_regs.h #define MASK_SUS_END BIT(3) /* SUS last state reached */ BIT 465 drivers/media/i2c/tda1997x_regs.h #define MASK_SUS_ACT BIT(2) /* Activity of selected input changed */ BIT 466 drivers/media/i2c/tda1997x_regs.h #define MASK_SUS_CH BIT(1) /* Selected input changed */ BIT 467 drivers/media/i2c/tda1997x_regs.h #define MASK_SUS_ST BIT(0) /* SUS state changed */ BIT 470 drivers/media/i2c/tda1997x_regs.h #define MASK_EDID_MTP BIT(7) /* EDID MTP end of process */ BIT 471 drivers/media/i2c/tda1997x_regs.h #define MASK_DDC_ERR BIT(6) /* master DDC error */ BIT 472 drivers/media/i2c/tda1997x_regs.h #define MASK_DDC_CMD_DONE BIT(5) /* master DDC cmd send correct */ BIT 473 drivers/media/i2c/tda1997x_regs.h #define MASK_READ_DONE BIT(4) /* End of down EDID read */ BIT 474 drivers/media/i2c/tda1997x_regs.h #define MASK_RX_DDC_SW BIT(3) /* Output DDC switching finished */ BIT 475 drivers/media/i2c/tda1997x_regs.h #define MASK_HDCP_DDC_SW BIT(2) /* HDCP DDC switching finished */ BIT 476 drivers/media/i2c/tda1997x_regs.h #define MASK_HDP_PULSE_END BIT(1) /* End of Hot Plug Detect pulse */ BIT 477 drivers/media/i2c/tda1997x_regs.h #define MASK_DET_5V BIT(0) /* Detection of +5V */ BIT 480 drivers/media/i2c/tda1997x_regs.h #define MASK_HDMI_FLG BIT(7) /* HDMI mode/avmute/encrypt/FIFO fail */ BIT 481 drivers/media/i2c/tda1997x_regs.h #define MASK_GAMUT BIT(6) /* Gamut packet */ BIT 482 drivers/media/i2c/tda1997x_regs.h #define MASK_ISRC2 BIT(5) /* ISRC2 packet */ BIT 483 drivers/media/i2c/tda1997x_regs.h #define MASK_ISRC1 BIT(4) /* ISRC1 packet */ BIT 484 drivers/media/i2c/tda1997x_regs.h #define MASK_ACP BIT(3) /* Audio Content Protection packet */ BIT 485 drivers/media/i2c/tda1997x_regs.h #define MASK_DC_NO_GCP BIT(2) /* GCP not received in 5 frames */ BIT 486 drivers/media/i2c/tda1997x_regs.h #define MASK_DC_PHASE BIT(1) /* deepcolor pixel phase needs update */ BIT 487 drivers/media/i2c/tda1997x_regs.h #define MASK_DC_MODE BIT(0) /* deepcolor color depth changed */ BIT 490 drivers/media/i2c/tda1997x_regs.h #define MASK_MPS_IF BIT(6) /* MPEG Source Product */ BIT 491 drivers/media/i2c/tda1997x_regs.h #define MASK_AUD_IF BIT(5) /* Audio */ BIT 492 drivers/media/i2c/tda1997x_regs.h #define MASK_SPD_IF BIT(4) /* Source Product Descriptor */ BIT 493 drivers/media/i2c/tda1997x_regs.h #define MASK_AVI_IF BIT(3) /* Auxiliary Video IF */ BIT 494 drivers/media/i2c/tda1997x_regs.h #define MASK_VS_IF_OTHER_BK2 BIT(2) /* Vendor Specific (bank2) */ BIT 495 drivers/media/i2c/tda1997x_regs.h #define MASK_VS_IF_OTHER_BK1 BIT(1) /* Vendor Specific (bank1) */ BIT 496 drivers/media/i2c/tda1997x_regs.h #define MASK_VS_IF_HDMI BIT(0) /* Vendor Specific (w/ HDMI LLC code) */ BIT 499 drivers/media/i2c/tda1997x_regs.h #define MASK_AUDIO_FREQ_FLG BIT(5) /* Audio freq change */ BIT 500 drivers/media/i2c/tda1997x_regs.h #define MASK_AUDIO_FLG BIT(4) /* DST, OBA, HBR, ASP change */ BIT 501 drivers/media/i2c/tda1997x_regs.h #define MASK_MUTE_FLG BIT(3) /* Audio Mute */ BIT 502 drivers/media/i2c/tda1997x_regs.h #define MASK_CH_STATE BIT(2) /* Channel status */ BIT 503 drivers/media/i2c/tda1997x_regs.h #define MASK_UNMUTE_FIFO BIT(1) /* Audio Unmute */ BIT 504 drivers/media/i2c/tda1997x_regs.h #define MASK_ERROR_FIFO_PT BIT(0) /* Audio FIFO pointer error */ BIT 507 drivers/media/i2c/tda1997x_regs.h #define MASK_AFE_WDL_UNLOCKED BIT(7) /* Wordlocker was unlocked */ BIT 508 drivers/media/i2c/tda1997x_regs.h #define MASK_AFE_GAIN_DONE BIT(6) /* Gain calibration done */ BIT 509 drivers/media/i2c/tda1997x_regs.h #define MASK_AFE_OFFSET_DONE BIT(5) /* Offset calibration done */ BIT 510 drivers/media/i2c/tda1997x_regs.h #define MASK_AFE_ACTIVITY_DET BIT(4) /* Activity detected on data */ BIT 511 drivers/media/i2c/tda1997x_regs.h #define MASK_AFE_PLL_LOCK BIT(3) /* TMDS PLL is locked */ BIT 512 drivers/media/i2c/tda1997x_regs.h #define MASK_AFE_TRMCAL_DONE BIT(2) /* Termination calibration done */ BIT 513 drivers/media/i2c/tda1997x_regs.h #define MASK_AFE_ASU_STATE BIT(1) /* ASU state is reached */ BIT 514 drivers/media/i2c/tda1997x_regs.h #define MASK_AFE_ASU_READY BIT(0) /* AFE calibration done: TMDS ready */ BIT 517 drivers/media/i2c/tda1997x_regs.h #define AUDCFG_CLK_INVERT BIT(7) /* invert A_CLK polarity */ BIT 518 drivers/media/i2c/tda1997x_regs.h #define AUDCFG_TEST_TONE BIT(6) /* enable test tone generator */ BIT 525 drivers/media/i2c/tda1997x_regs.h #define AUDCFG_AUTO_MUTE_EN BIT(3) /* Enable Automatic audio mute */ BIT 537 drivers/media/i2c/tda1997x_regs.h #define OF_VP_ENABLE BIT(7) /* VP[35:0]/HS/VS/DE/CLK */ BIT 538 drivers/media/i2c/tda1997x_regs.h #define OF_BLK BIT(4) /* blanking codes */ BIT 539 drivers/media/i2c/tda1997x_regs.h #define OF_TRC BIT(3) /* timing codes (SAV/EAV) */ BIT 581 drivers/media/i2c/tda1997x_regs.h #define RESET_DC BIT(7) /* Reset deep color module */ BIT 582 drivers/media/i2c/tda1997x_regs.h #define RESET_HDCP BIT(6) /* Reset HDCP module */ BIT 583 drivers/media/i2c/tda1997x_regs.h #define RESET_KSV BIT(5) /* Reset KSV-FIFO */ BIT 584 drivers/media/i2c/tda1997x_regs.h #define RESET_SCFG BIT(4) /* Reset HDCP and repeater function */ BIT 585 drivers/media/i2c/tda1997x_regs.h #define RESET_HCFG BIT(3) /* Reset HDCP DDC part */ BIT 586 drivers/media/i2c/tda1997x_regs.h #define RESET_PA BIT(2) /* Reset polarity adjust */ BIT 587 drivers/media/i2c/tda1997x_regs.h #define RESET_EP BIT(1) /* Reset Error protection */ BIT 588 drivers/media/i2c/tda1997x_regs.h #define RESET_TMDS BIT(0) /* Reset TMDS (calib, encoding, flow) */ BIT 591 drivers/media/i2c/tda1997x_regs.h #define NACK_HDCP BIT(7) /* No ACK on HDCP request */ BIT 592 drivers/media/i2c/tda1997x_regs.h #define RESET_FIFO BIT(4) /* Reset Audio FIFO control */ BIT 593 drivers/media/i2c/tda1997x_regs.h #define RESET_GAMUT BIT(3) /* Clear Gamut packet */ BIT 594 drivers/media/i2c/tda1997x_regs.h #define RESET_AI BIT(2) /* Clear ACP and ISRC packets */ BIT 595 drivers/media/i2c/tda1997x_regs.h #define RESET_IF BIT(1) /* Clear all Audio infoframe packets */ BIT 596 drivers/media/i2c/tda1997x_regs.h #define RESET_AUDIO BIT(0) /* Reset Audio FIFO control */ BIT 599 drivers/media/i2c/tda1997x_regs.h #define HDCP_HDMI BIT(7) /* HDCP supports HDMI (vs DVI only) */ BIT 600 drivers/media/i2c/tda1997x_regs.h #define HDCP_REPEATER BIT(6) /* HDCP supports repeater function */ BIT 601 drivers/media/i2c/tda1997x_regs.h #define HDCP_READY BIT(5) /* set by repeater function */ BIT 602 drivers/media/i2c/tda1997x_regs.h #define HDCP_FAST BIT(4) /* Up to 400kHz */ BIT 603 drivers/media/i2c/tda1997x_regs.h #define HDCP_11 BIT(1) /* HDCP 1.1 supported */ BIT 604 drivers/media/i2c/tda1997x_regs.h #define HDCP_FAST_REAUTH BIT(0) /* fast reauthentication supported */ BIT 607 drivers/media/i2c/tda1997x_regs.h #define AUDIO_LAYOUT_SP_FLAG BIT(2) /* sp flag used by FIFO */ BIT 608 drivers/media/i2c/tda1997x_regs.h #define AUDIO_LAYOUT_MANUAL BIT(1) /* manual layout (vs per pkt) */ BIT 609 drivers/media/i2c/tda1997x_regs.h #define AUDIO_LAYOUT_LAYOUT1 BIT(0) /* Layout1: AP0-3 vs Layout0:AP0 */ BIT 13 drivers/media/i2c/tvp5150_reg.h #define TVP5150_MISC_CTL_VBLK_GPCL BIT(7) BIT 14 drivers/media/i2c/tvp5150_reg.h #define TVP5150_MISC_CTL_GPCL BIT(6) BIT 15 drivers/media/i2c/tvp5150_reg.h #define TVP5150_MISC_CTL_INTREQ_OE BIT(5) BIT 16 drivers/media/i2c/tvp5150_reg.h #define TVP5150_MISC_CTL_HVLK BIT(4) BIT 17 drivers/media/i2c/tvp5150_reg.h #define TVP5150_MISC_CTL_YCBCR_OE BIT(3) BIT 18 drivers/media/i2c/tvp5150_reg.h #define TVP5150_MISC_CTL_SYNC_OE BIT(2) BIT 19 drivers/media/i2c/tvp5150_reg.h #define TVP5150_MISC_CTL_VBLANK BIT(1) BIT 20 drivers/media/i2c/tvp5150_reg.h #define TVP5150_MISC_CTL_CLOCK_OE BIT(0) BIT 128 drivers/media/i2c/tvp5150_reg.h #define TVP5150_INT_A_LOCK_STATUS BIT(7) BIT 129 drivers/media/i2c/tvp5150_reg.h #define TVP5150_INT_A_LOCK BIT(6) BIT 132 drivers/media/i2c/tvp5150_reg.h #define TVP5150_VDPOE BIT(2) BIT 150 drivers/media/i2c/video-i2c.c #define AMG88XX_FPSC_1FPS BIT(0) BIT 308 drivers/media/i2c/video-i2c.c if (tmp & BIT(11)) BIT 405 drivers/media/mc/mc-device.c #define MEDIA_IOC_FL_GRAPH_MUTEX BIT(0) BIT 65 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_DIP0_MSK BIT(0) BIT 66 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_DIP1_MSK BIT(1) BIT 67 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_HSMA_PRSNTN_MSK BIT(2) BIT 68 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK BIT(3) BIT 69 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI0_5V_MSK BIT(4) BIT 70 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI0_INT1_MSK BIT(5) BIT 71 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI0_INT2_MSK BIT(6) BIT 72 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI0_LOST_DATA_MSK BIT(7) BIT 73 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI1_5V_MSK BIT(8) BIT 74 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI1_INT1_MSK BIT(9) BIT 75 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI1_INT2_MSK BIT(10) BIT 76 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI1_LOST_DATA_MSK BIT(11) BIT 77 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI2_5V_MSK BIT(12) BIT 78 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI2_INT1_MSK BIT(13) BIT 79 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI2_INT2_MSK BIT(14) BIT 80 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI2_LOST_DATA_MSK BIT(15) BIT 81 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI3_5V_MSK BIT(16) BIT 82 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI3_INT1_MSK BIT(17) BIT 83 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI3_INT2_MSK BIT(18) BIT 84 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VI3_LOST_DATA_MSK BIT(19) BIT 85 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VIHSMA_5V_MSK BIT(20) BIT 86 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VIHSMA_INT1_MSK BIT(21) BIT 87 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VIHSMA_INT2_MSK BIT(22) BIT 88 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK BIT(23) BIT 89 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VOHSMA_INT1_MSK BIT(24) BIT 90 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK BIT(25) BIT 91 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK BIT(26) BIT 92 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK BIT(28) BIT 93 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK BIT(29) BIT 94 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK BIT(30) BIT 95 drivers/media/pci/cobalt/cobalt-driver.h #define COBALT_SYSSTAT_PCIE_SMBCLK_MSK BIT(31) BIT 81 drivers/media/pci/cx18/cx18-ioctl.c if (BIT(i) & set) BIT 1897 drivers/media/pci/cx23885/cx23885-cards.c .flags = BIT(V4L2_SUBDEV_IO_PIN_INPUT), BIT 1903 drivers/media/pci/cx23885/cx23885-cards.c .flags = BIT(V4L2_SUBDEV_IO_PIN_OUTPUT), BIT 1914 drivers/media/pci/cx23885/cx23885-cards.c .flags = BIT(V4L2_SUBDEV_IO_PIN_INPUT), BIT 723 drivers/media/pci/intel/ipu3/ipu3-cio2.c ie_status &= ~BIT(port * 8 + i); BIT 724 drivers/media/pci/intel/ipu3/ipu3-cio2.c port_status &= ~BIT(i); BIT 741 drivers/media/pci/intel/ipu3/ipu3-cio2.c csi2_status &= ~BIT(i); BIT 47 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CSIRX_IF_CONFIG_FLAG_ERROR BIT(2) BIT 64 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_REG_MIPIBE_FORCE_RAW8_ENABLE BIT(0) BIT 65 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_REG_MIPIBE_FORCE_RAW8_USE_TYPEID BIT(1) BIT 99 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_CSI2_TGE BIT(0) BIT 100 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_PRIM_TGE BIT(1) BIT 101 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_SIDE_TGE BIT(2) BIT 102 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_XOSC_TGE BIT(3) BIT 103 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_MPLL_SHUTDOWN_EN BIT(4) BIT 104 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_D3I3_TGE BIT(5) BIT 105 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_CSI2_INTERFRAME_TGE BIT(6) BIT 106 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_CSI2_PORT_DCGE BIT(8) BIT 107 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_CSI2_DCGE BIT(9) BIT 108 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_SIDE_DCGE BIT(10) BIT 109 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_PRIM_DCGE BIT(11) BIT 110 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_ROSC_DCGE BIT(12) BIT 111 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_XOSC_DCGE BIT(13) BIT 112 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CGC_FLIS_DCGE BIT(14) BIT 116 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_D0I3C_I3 BIT(2) /* Set D0I3 */ BIT 117 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_D0I3C_RR BIT(3) /* Restore? */ BIT 140 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_INT_IOIE BIT(22) BIT 141 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_INT_IOOE BIT(23) BIT 142 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_INT_IOIRQ BIT(24) BIT 149 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PBM_ARB_CTRL_LE_EN BIT(7) BIT 158 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PBM_WMCTRL1_TS_COUNT_DISABLE BIT(31) BIT 171 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PBM_WMCTRL2_DYNWMEN BIT(28) BIT 172 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PBM_WMCTRL2_OBFF_MEM_EN BIT(29) BIT 173 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PBM_WMCTRL2_OBFF_CPU_EN BIT(30) BIT 174 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PBM_WMCTRL2_DRAINNOW BIT(31) BIT 182 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_LTRCTRL_LTRDYNEN BIT(16) BIT 185 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_LTRCTRL_LTRSEL1S3 BIT(7) BIT 186 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_LTRCTRL_LTRSEL1S2 BIT(6) BIT 187 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_LTRCTRL_LTRSEL1S1 BIT(5) BIT 188 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_LTRCTRL_LTRSEL1S0 BIT(4) BIT 189 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_LTRCTRL_LTRSEL2S3 BIT(3) BIT 190 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_LTRCTRL_LTRSEL2S2 BIT(2) BIT 191 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_LTRCTRL_LTRSEL2S1 BIT(1) BIT 192 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_LTRCTRL_LTRSEL2S0 BIT(0) BIT 217 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CDMAC0_FBPT_NS BIT(25) BIT 218 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CDMAC0_DMA_INTR_ON_FS BIT(26) BIT 219 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CDMAC0_DMA_INTR_ON_FE BIT(27) BIT 220 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CDMAC0_FBPT_UPDATE_FIFO_FULL BIT(28) BIT 221 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CDMAC0_FBPT_FIFO_FULL_FIX_DIS BIT(29) BIT 222 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CDMAC0_DMA_EN BIT(30) BIT 223 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_CDMAC0_DMA_HALTED BIT(31) BIT 258 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PXM_FRF_CFG_FNSEL BIT(0) BIT 259 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PXM_FRF_CFG_FN_RST BIT(1) BIT 260 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PXM_FRF_CFG_ABORT BIT(2) BIT 262 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NR BIT(8) BIT 263 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PXM_FRF_CFG_MSK_ECC_RE BIT(9) BIT 264 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NE BIT(10) BIT 266 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PXM_FRF_CFG_MASK_CRC_THRES BIT(13) BIT 267 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PXM_FRF_CFG_MASK_CSI_ACCEPT BIT(14) BIT 268 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_PXM_FRF_CFG_CIOHC_FS_MODE BIT(15) BIT 395 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_FBPT_CTRL_VALID BIT(0) BIT 396 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_FBPT_CTRL_IOC BIT(1) BIT 397 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_FBPT_CTRL_IOS BIT(2) BIT 398 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_FBPT_CTRL_SUCCXFAIL BIT(3) BIT 913 drivers/media/pci/ivtv/ivtv-driver.c u32 device = BIT(i); BIT 76 drivers/media/pci/ivtv/ivtv-ioctl.c if (BIT(i) & set) BIT 77 drivers/media/pci/ivtv/ivtv-ioctl.c return BIT(i); BIT 13 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_ENC_START_CAP BIT(31) BIT 14 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_ENC_EOS BIT(30) BIT 15 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_ENC_VBI_CAP BIT(29) BIT 16 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_ENC_VIM_RST BIT(28) BIT 17 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_ENC_DMA_COMPLETE BIT(27) BIT 18 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_ENC_PIO_COMPLETE BIT(25) BIT 19 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_DEC_AUD_MODE_CHG BIT(24) BIT 20 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_DEC_DATA_REQ BIT(22) BIT 21 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_DEC_DMA_COMPLETE BIT(20) BIT 22 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_DEC_VBI_RE_INSERT BIT(19) BIT 23 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_DMA_ERR BIT(18) BIT 24 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_DMA_WRITE BIT(17) BIT 25 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_DMA_READ BIT(16) BIT 26 drivers/media/pci/ivtv/ivtv-irq.h #define IVTV_IRQ_DEC_VSYNC BIT(10) BIT 17 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_RISCEN BIT(27) BIT 18 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_I2CRACK BIT(26) BIT 22 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_PCMCIA7 BIT(19) BIT 23 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_PCMCIA6 BIT(18) BIT 24 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_PCMCIA5 BIT(17) BIT 25 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_PCMCIA4 BIT(16) BIT 26 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_PCMCIA3 BIT(15) BIT 27 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_PCMCIA2 BIT(14) BIT 28 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_PCMCIA1 BIT(13) BIT 29 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_PCMCIA0 BIT(12) BIT 30 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_IRQ1 BIT(11) BIT 31 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_IRQ0 BIT(10) BIT 32 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_OCERR BIT(8) BIT 33 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_PABORT BIT(7) BIT 34 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_RIPERR BIT(6) BIT 35 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_PPERR BIT(5) BIT 36 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_FTRGT BIT(3) BIT 37 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_RISCI BIT(1) BIT 38 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_INT_I2CDONE BIT(0) BIT 44 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_CPU_DO BIT(10) BIT 45 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_DRV_DO BIT(9) BIT 46 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_I2C_RD BIT(7) BIT 47 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_I2C_WR BIT(6) BIT 48 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_DCAP_MODE BIT(5) BIT 52 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_FIFO_EN BIT(2) BIT 53 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_DCAP_EN BIT(1) BIT 54 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_RISC_EN BIT(0) BIT 71 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_I2C_STOP BIT(5) BIT 72 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_I2C_PGMODE BIT(3) BIT 88 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_DET BIT(7) BIT 89 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_DAT_CF_EN BIT(6) BIT 91 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_VCCEN BIT(3) BIT 92 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_BYPASS BIT(2) BIT 93 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_MRST BIT(1) BIT 94 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_CRST_INT BIT(0) BIT 98 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_BYTEADDRSUB BIT(25) BIT 99 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_WAITPOL BIT(24) BIT 102 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_SLFTIMEDMODE BIT(15) BIT 105 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_BIGENDIAN BIT(3) BIT 107 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_HWORDDEV BIT(0) BIT 110 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_WSTOPERWREN3 BIT(31) BIT 111 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_PARBOOTN BIT(29) BIT 113 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_WSTOPERWREN2 BIT(23) BIT 115 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_WSTOPERWREN1 BIT(15) BIT 117 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_WSTOPERWREN0 BIT(7) BIT 121 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_CS2RWWREN3 BIT(31) BIT 123 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_CS2RWWREN2 BIT(23) BIT 125 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_CS2RWWREN1 BIT(15) BIT 127 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_CS2RWWREN0 BIT(7) BIT 131 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_IRQPOL BIT(8) BIT 132 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_MASK_WRACK BIT(7) BIT 133 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_MASK_BRRDY BIT(6) BIT 134 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_MASK_OVFLW BIT(5) BIT 135 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_MASK_OTHERR BIT(4) BIT 136 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_MASK_WSTO BIT(3) BIT 137 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_MASK_EXTIRQ BIT(2) BIT 138 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_MASK_PLUGIN BIT(1) BIT 139 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_MASK_PLUGOUT BIT(0) BIT 142 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_SBUF_KILLOP BIT(15) BIT 143 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_SBUF_OPDONE BIT(14) BIT 144 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_SBUF_EMPTY BIT(13) BIT 145 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_DETSTAT BIT(9) BIT 146 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_INTSTAT BIT(8) BIT 147 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_WRACK BIT(7) BIT 148 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_BRRDY BIT(6) BIT 149 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_SBUF_OVFLW BIT(5) BIT 150 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_OTHERR BIT(4) BIT 151 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_SBUF_WSTO BIT(3) BIT 152 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_EXTIRQ BIT(2) BIT 153 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_CARD_PLUGIN BIT(1) BIT 154 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_CARD_PLUGOUT BIT(0) BIT 157 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_PCMCIAREG BIT(27) BIT 158 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_PCMCIAIOM BIT(26) BIT 170 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_HIFRDWRN BIT(31) BIT 171 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_PCMCIAREG BIT(27) BIT 172 drivers/media/pci/mantis/mantis_reg.h #define MANTIS_GPIF_PCMCIAIOM BIT(26) BIT 37 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_DMA_CTRL_SDRAM_CLK_INVERT BIT(5) BIT 38 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_DMA_CTRL_STROBE_SELECT BIT(4) BIT 39 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_DMA_CTRL_READ_DATA_SELECT BIT(3) BIT 40 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_DMA_CTRL_READ_CLK_SELECT BIT(2) BIT 47 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VCLK_INVERT BIT(22) BIT 61 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_P2M(n) BIT((n) + 17) BIT 62 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_GPIO BIT(16) BIT 63 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_VIDEO_LOSS BIT(15) BIT 64 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_VIDEO_IN BIT(14) BIT 65 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_MOTION BIT(13) BIT 66 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_ATA_CMD BIT(12) BIT 67 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_ATA_DIR BIT(11) BIT 68 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_PCI_ERR BIT(10) BIT 69 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_PS2_1 BIT(9) BIT 70 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_PS2_0 BIT(8) BIT 71 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_SPI BIT(7) BIT 72 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_IIC BIT(6) BIT 73 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_UART(n) BIT((n) + 4) BIT 74 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_G723 BIT(3) BIT 75 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_DECODER BIT(1) BIT 76 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_ENCODER BIT(0) BIT 84 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_EEPROM_ACCESS_EN BIT(7) BIT 85 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_EEPROM_CS BIT(3) BIT 86 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_EEPROM_CLK BIT(2) BIT 87 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_EEPROM_DO BIT(1) BIT 88 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_EEPROM_DI BIT(0) BIT 107 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_CSC_BYTE_REORDER BIT(5) /* BGR -> RGB */ BIT 109 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_CSC_16BIT_565 BIT(4) BIT 110 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_UV_SWAP BIT(3) BIT 111 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_PCI_MASTER_MODE BIT(2) BIT 112 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_DESC_INTR_OPT BIT(1) /* 1:Empty, 0:Each */ BIT 113 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_DESC_MODE BIT(0) BIT 121 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_COMMAND_DONE BIT(8) BIT 134 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_CSC_16BIT BIT(6) /* 0:24bit, 1:16bit */ BIT 137 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_CSC_ON BIT(3) BIT 138 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_INTERRUPT_REQ BIT(2) BIT 139 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_WRITE BIT(1) BIT 140 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_P2M_TRANS_ON BIT(0) BIT 162 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_FMT_CHECK_VCOUNT BIT(31) BIT 163 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_FMT_CHECK_HCOUNT BIT(30) BIT 164 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_FMT_TEST_SIGNAL BIT(28) BIT 176 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_FI_INVERT BIT(31) BIT 189 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_PB_USER_MODE BIT(1) BIT 190 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_PB_PAL BIT(0) BIT 231 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_MOTION_INTR_START_STOP BIT(15) BIT 232 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_MOTION_FREEZE_DATA BIT(14) BIT 239 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_MOTION_Y_SET BIT(29) BIT 240 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_MOTION_Y_ADD BIT(28) BIT 241 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_MOTION_CB_SET BIT(27) BIT 242 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_MOTION_CB_ADD BIT(26) BIT 243 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_MOTION_CR_SET BIT(25) BIT 244 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_MOTION_CR_ADD BIT(24) BIT 250 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_SCAN_MODE_PROGRESSIVE BIT(31) BIT 251 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_FMT_TYPE_PAL BIT(30) BIT 253 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_USER_SET BIT(29) BIT 255 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_FI_CHANGE BIT(20) BIT 256 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_USER_COLOR_SET_VSYNC BIT(19) BIT 257 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_USER_COLOR_SET_HSYNC BIT(18) BIT 258 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_USER_COLOR_SET_NAH BIT(17) BIT 259 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_USER_COLOR_SET_NAV BIT(16) BIT 275 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_SYNC_INVERT BIT(24) BIT 276 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_HSYNC_INVERT BIT(23) BIT 277 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_VSYNC_INVERT BIT(22) BIT 282 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_DISP_ON BIT(31) BIT 284 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_DISP_DOUBLE_SCAN BIT(22) BIT 285 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_DISP_SINGLE_PAGE BIT(21) BIT 289 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_DISP_ERASE_ON BIT(0) BIT 292 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_ZOOM_VER_ON BIT(24) BIT 293 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_ZOOM_HOR_ON BIT(23) BIT 294 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_ZOOM_V_COMP BIT(22) BIT 299 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_FREEZE_ON BIT(1) BIT 300 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_FREEZE_INTERPOLATION BIT(0) BIT 339 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_OSG_ON BIT(31) BIT 340 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_OSG_COLOR_MUTE BIT(28) BIT 350 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_OSG_BLINK_ON BIT(1) BIT 351 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VO_OSG_BLINK_INTREVAL18 BIT(0) BIT 379 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VE_TWO_PAGE_MODE BIT(31) BIT 386 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VE_INSERT_INDEX BIT(18) BIT 391 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VE_INSERT_INDEX_JPEG BIT(19) /* 6110 Only */ BIT 399 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VE_LITTLE_ENDIAN BIT(31) BIT 400 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_COMP_ATTR_RN BIT(30) BIT 421 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VE_OSD_V_DOUBLE BIT(16) /* 6110 Only */ BIT 422 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VE_OSD_H_SHADOW BIT(15) BIT 423 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VE_OSD_V_SHADOW BIT(14) BIT 440 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_NO_WRITE_NO_WINDOW BIT(24) BIT 441 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_BUSY_WIAT_CODE BIT(23) BIT 442 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_BUSY_WIAT_REF BIT(22) BIT 443 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_BUSY_WIAT_RES BIT(21) BIT 444 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_BUSY_WIAT_MS BIT(20) BIT 445 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_SINGLE_MODE BIT(18) BIT 446 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_SCAL_MANUAL BIT(17) BIT 447 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_USER_PAGE_CTRL BIT(16) BIT 448 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_LITTLE_ENDIAN BIT(15) BIT 449 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_START_FI BIT(14) BIT 450 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_ERR_LOCK BIT(13) BIT 451 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_CFG_ERR_INT_ENA BIT(12) BIT 464 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_OPER_ON BIT(31) BIT 468 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_STATUS0_INTR_ACK BIT(22) BIT 469 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_STATUS0_INTR_EMPTY BIT(21) BIT 470 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_STATUS0_INTR_ERR BIT(20) BIT 475 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_IDX_INTERLACE BIT(30) BIT 482 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_IDX_DEINTERLACE BIT(16) BIT 487 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_IDX_REF_BASE_SIDE BIT(31) BIT 492 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_IDX_INTERLACE_WR BIT(27) BIT 493 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_IDX_INTERPOL BIT(26) BIT 494 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VD_IDX_HOR2X BIT(25) BIT 516 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_ENABLE BIT(8) BIT 520 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_AUTO_CLEAR BIT(20) BIT 521 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_STATE_RX_ACK BIT(19) BIT 522 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_STATE_BUSY BIT(18) BIT 523 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_STATE_SIG_ERR BIT(17) BIT 524 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_STATE_TRNS BIT(16) BIT 526 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_ACK_EN BIT(4) BIT 527 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_START BIT(3) BIT 528 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_STOP BIT(2) BIT 529 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_READ BIT(1) BIT 530 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IIC_WRITE BIT(0) BIT 540 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_MODEM_CTRL_EN BIT(20) BIT 541 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_PARITY_ERROR_DROP BIT(18) BIT 542 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_ERR_EN BIT(17) BIT 543 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_RX_EN BIT(16) BIT 544 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_IRQ_TX_EN BIT(15) BIT 545 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_RX_EN BIT(14) BIT 546 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_TX_EN BIT(13) BIT 547 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_UART_HALF_DUPLEX BIT(12) BIT 548 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_UART_LOOPBACK BIT(11) BIT 574 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_UART_CTS BIT(15) BIT 575 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_UART_RX_BUSY BIT(14) BIT 576 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_UART_OVERRUN BIT(13) BIT 577 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_UART_FRAME_ERR BIT(12) BIT 578 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_UART_PARITY_ERR BIT(11) BIT 579 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_UART_TX_BUSY BIT(5) BIT 587 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_UART_TX_DATA_PUSH BIT(8) BIT 589 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_UART_RX_DATA_POP BIT(8) BIT 597 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_AUDIO_ENABLE BIT(31) BIT 598 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_AUDIO_MASTER_MODE BIT(30) BIT 599 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_AUDIO_I2S_MODE BIT(29) BIT 600 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_AUDIO_I2S_LR_SWAP BIT(27) BIT 601 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_AUDIO_I2S_8BIT BIT(26) BIT 603 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_AUDIO_MIX_9TO0 BIT(23) BIT 605 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_AUDIO_MIX_19TO10 BIT(19) BIT 609 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_AUDIO_EE_MODE_ON BIT(30) BIT 18 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_EMU_EN_DDR BIT(0) BIT 20 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_EMU_EN_ME BIT(1) BIT 22 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_EMU_EN_SEN BIT(2) BIT 24 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_EMU_EN_BHOST BIT(3) BIT 26 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_EMU_EN_LPF BIT(4) BIT 28 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_EMU_EN_PLBK BIT(5) BIT 38 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DSP_FRAME_TYPE_D1 BIT(6) BIT 45 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_SLICE_END BIT(0) BIT 47 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MAS_SLICE_END BIT(4) BIT 49 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_START_NSLICE BIT(15) BIT 74 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DSP_CODEC_MODE BIT(0) BIT 84 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_CIF_MAP_MD BIT(6) BIT 89 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_HD1_MAP_MD BIT(7) BIT 91 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_VLD BIT(8) BIT 93 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MV_VECT_VLD BIT(9) BIT 95 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MV_FLAG_VLD BIT(10) BIT 148 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DDR_BRST_EN BIT(13) BIT 154 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DDR_AB_SEL BIT(14) BIT 160 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DDR_MODE BIT(15) BIT 199 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DSP_INTER_ST BIT(1) BIT 201 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DI_EN BIT(2) BIT 207 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DI_MD BIT(3) BIT 228 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DUAL_STR BIT(8) BIT 251 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_QPEL_EN BIT(0) BIT 253 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_HPEL_EN BIT(1) BIT 255 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_ME_EN BIT(2) BIT 257 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTRA_EN BIT(3) BIT 259 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SKIP_EN BIT(4) BIT 348 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PROG_A BIT(0) BIT 353 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PROG_B BIT(1) BIT 358 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_FRAME BIT(2) BIT 426 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_BYTE_SWP BIT(6) BIT 428 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_ADD03_EN BIT(7) BIT 437 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_INF_SEL BIT(13) BIT 439 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_OVFL_CNTL BIT(14) BIT 444 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_PCI_SEL BIT(15) BIT 449 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_A03_DISAB BIT(16) BIT 466 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_BK0_FULL BIT(0) BIT 468 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_BK1_FULL BIT(1) BIT 470 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_END_SLICE BIT(2) BIT 472 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DSP_RD_OF BIT(3) BIT 490 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_RD_MEM BIT(0) BIT 495 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_RD_BRST BIT(1) BIT 516 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_ADPCM_DEC BIT(0) BIT 518 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_ADPCM_IN_DATA BIT(1) BIT 520 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_ADPCM_ENC BIT(2) BIT 527 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SPK_ORG_EN BIT(16) BIT 532 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AD_BIT_MODE BIT(17) BIT 549 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_TEST_ADLOOP_EN BIT(30) BIT 554 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AUD_MODE BIT(31) BIT 561 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SPK_ADPCM_EN BIT(16) BIT 651 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_FLOW_EN BIT(16) BIT 656 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_AUD_FRM_EN BIT(17) BIT 669 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SYNC_CFG BIT(7) BIT 674 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SYNC_ADR_EDGE BIT(0) BIT 687 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_OUT_EDGE BIT(3) BIT 732 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SYSPLL_IREF BIT(4) BIT 784 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SYSPLL_LPF_5PF BIT(6) BIT 790 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SYSPLL_ED_SEL BIT(7) BIT 796 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SYSPLL_RST BIT(0) BIT 798 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SYSPLL_PD BIT(4) BIT 807 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SRST BIT(0) BIT 813 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SYSPLL_CFG BIT(2) BIT 819 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SPLL_CFG BIT(4) BIT 824 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_LOAD BIT(3) BIT 896 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_VLC_RAM BIT(0) BIT 897 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_BURST BIT(1) BIT 898 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_MV_DSP BIT(2) BIT 899 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_VIN_LOST BIT(3) BIT 902 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_JPEG BIT(12) BIT 903 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_VLC_DONE BIT(17) BIT 904 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_AD_VSYNC BIT(19) BIT 905 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_PV_EOF BIT(20) BIT 906 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_PV_OVERFLOW BIT(21) BIT 907 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_TIMER BIT(22) BIT 908 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_AUD_EOF BIT(24) BIT 909 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_I2C_DONE BIT(25) BIT 910 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INTR_AD BIT(26) BIT 1070 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MASTER_MODE BIT(0) BIT 1075 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SINGLE_PROC BIT(1) BIT 1080 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_WRITE_FLAG BIT(2) BIT 1121 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AUD_DATA_IN_ENB BIT(0) BIT 1123 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AUD_ENC_REQ_ENB BIT(1) BIT 1125 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AUD_DEC_REQ0_ENB BIT(2) BIT 1127 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AUD_DEC_REQ1_ENB BIT(3) BIT 1129 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_STRM_REQ_ENB BIT(4) BIT 1131 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DVM_MV_REQ_ENB BIT(5) BIT 1133 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MVD_REQ_ENB BIT(6) BIT 1135 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MVD_TMP_REQ_ENB BIT(7) BIT 1137 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_JPEG_REQ_ENB BIT(8) BIT 1139 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MV_FLAG_REQ_ENB BIT(9) BIT 1144 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_ARB12_ENB BIT(15) BIT 1171 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_BUSY BIT(31) BIT 1173 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_ENABLE BIT(25) BIT 1175 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_RW BIT(24) BIT 1210 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MV_BK0_FULL BIT(0) BIT 1212 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MV_BK1_FULL BIT(1) BIT 1214 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MV_EOF BIT(2) BIT 1216 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MV_DSP_INTR BIT(3) BIT 1218 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_DSP_WR_OF BIT(4) BIT 1223 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MPI_DDR_SEL BIT(13) BIT 1232 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_MPI_DDR_SEL2 BIT(15) BIT 1238 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_VLC_DONE_INTR BIT(1) BIT 1240 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AD_VSYNC_INTR BIT(3) BIT 1242 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PREV_EOF_INTR BIT(4) BIT 1244 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PREV_OVERFLOW_INTR BIT(5) BIT 1246 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_TIMER_INTR BIT(6) BIT 1248 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AUDIO_EOF_INTR BIT(8) BIT 1250 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_IIC_DONE_INTR BIT(24) BIT 1252 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AD_INTR_REG BIT(25) BIT 1257 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_MAST_ENB BIT(0) BIT 1261 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AD_MAST_ENB BIT(3) BIT 1263 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PREV_MAST_ENB BIT(4) BIT 1265 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PREV_OVERFLOW_ENB BIT(5) BIT 1267 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_TIMER_INTR_ENB BIT(6) BIT 1269 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_JPEG_MAST_ENB BIT(7) BIT 1274 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_IIC_INTR_ENB BIT(24) BIT 1276 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_AD_INTR_ENB BIT(25) BIT 1278 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_TAR_BURST_ENB BIT(26) BIT 1280 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_VLC_BURST_ENB BIT(27) BIT 1282 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_DDR_BURST_ENB BIT(28) BIT 1301 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_VLC_INTR_ENB BIT(1) BIT 1303 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_PREV_INTR_ENB BIT(4) BIT 1305 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_PREV_OF_INTR_ENB BIT(5) BIT 1307 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_JPEG_INTR_ENB BIT(7) BIT 1309 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_PCI_AUD_INTR_ENB BIT(8) BIT 1332 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_IIC_RW BIT(16) BIT 1341 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_IIC_DONE BIT(24) BIT 1346 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_APP_SOFT_RST BIT(0) BIT 1418 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_BRST_RW BIT(16) BIT 1420 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_NEW_BRST_CMD BIT(17) BIT 1422 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_BRST_END BIT(24) BIT 1424 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SING_ERR_INTR BIT(25) BIT 1426 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_BRST_ERR_INTR BIT(26) BIT 1428 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_BRST_END_INTR BIT(27) BIT 1430 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SINGLE_ERR BIT(28) BIT 1432 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_SINGLE_BUSY BIT(29) BIT 1434 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_BRST_ERR BIT(30) BIT 1436 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_BRST_BUSY BIT(31) BIT 1462 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_0_VDLOSS BIT(7) BIT 1467 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_0_HLOCK BIT(6) BIT 1472 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_0_SLOCK BIT(5) BIT 1477 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_0_FLD BIT(4) BIT 1482 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_0_VLOCK BIT(3) BIT 1487 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_0_MONO BIT(1) BIT 1494 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_0_DET50 BIT(0) BIT 1498 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_1_VCR BIT(7) BIT 1500 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_1_WKAIR BIT(6) BIT 1502 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_1_WKAIR1 BIT(5) BIT 1508 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_1_VSTD BIT(4) BIT 1514 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_1_NINTL BIT(3) BIT 1537 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_6_VDELAY_XY_HI BIT(4) BIT 1538 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_6_VACTIVE_XY_HI BIT(5) BIT 1574 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_8_SCURVE BIT(7) BIT 1628 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_D_CSBAD BIT(3) BIT 1630 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_D_MCVSN BIT(2) BIT 1632 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_D_CSTRIPE BIT(1) BIT 1639 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_D_CTYPE2 BIT(0) BIT 1649 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_E_DETSTUS BIT(7) BIT 1669 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_E_ATREG BIT(3) BIT 1690 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_F_ATSTART BIT(7) BIT 1692 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_F_PAL60EN BIT(6) BIT 1694 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_F_PALCNEN BIT(5) BIT 1696 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_F_PALMEN BIT(4) BIT 1698 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_F_NTSC44EN BIT(3) BIT 1700 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_F_SECAMEN BIT(2) BIT 1702 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_F_PALBEN BIT(1) BIT 1704 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VIN_F_NTSCEN BIT(0) BIT 1710 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VD_108_POL_VD12 BIT(0) BIT 1711 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_VD_108_POL_VD34 BIT(1) BIT 1759 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_MIX_DERATIO BIT(5) BIT 1777 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E3_EXT_ADATP BIT(7) BIT 1779 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E3_ACLKPPOLO BIT(6) BIT 1785 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E3_ACLKRPOL BIT(5) BIT 1791 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E3_ACLKPPOLI BIT(4) BIT 1798 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E3_AFAUTO BIT(3) BIT 1816 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E4_I2S8MODE BIT(7) BIT 1824 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E4_MASCKMD BIT(6) BIT 1826 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E4_PBINSWAP BIT(5) BIT 1832 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E4_ASYNRDLY BIT(4) BIT 1838 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E4_ASYNPDLY BIT(3) BIT 1845 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_AIN_0x0E4_ADATPDLY BIT(2) BIT 1936 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_DETECTION_CTL0_MD_DIS BIT(5) BIT 1942 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_DETECTION_CTL0_MD_STRB BIT(3) BIT 1948 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_DETECTION_CTL0_MD_STRB_EN BIT(2) BIT 1982 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_DETECTION_CTL2_MD_REFFLD BIT(7) BIT 2118 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_RESET_VD BIT(7) BIT 2119 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_RESET_DLL BIT(6) BIT 2120 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_RESET_MUX_CORE BIT(5) BIT 2123 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_PV_VD_CK_POL_PV(channel) BIT(channel) BIT 2124 drivers/media/pci/tw5864/tw5864-reg.h #define TW5864_INDIR_PV_VD_CK_POL_VD(channel) BIT(channel + 4) BIT 8 drivers/media/pci/tw5864/tw5864-util.c while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries) BIT 22 drivers/media/pci/tw5864/tw5864-util.c while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries) BIT 31 drivers/media/pci/tw5864/tw5864-util.c while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries) BIT 395 drivers/media/pci/tw5864/tw5864-video.c TW5864_ME_EN | BIT(5) /* SRCH_OPT default */); BIT 43 drivers/media/pci/tw686x/tw686x-audio.c pb = !!(pb_status & BIT(AUDIO_CHANNEL_OFFSET + ch)); BIT 382 drivers/media/pci/tw686x/tw686x-audio.c reg_write(dev, AUDIO_CONTROL1, BIT(0)); BIT 98 drivers/media/pci/tw686x/tw686x-core.c dma_en &= ~BIT(channel); BIT 99 drivers/media/pci/tw686x/tw686x-core.c dma_cmd &= ~BIT(channel); BIT 102 drivers/media/pci/tw686x/tw686x-core.c dev->pending_dma_en &= ~BIT(channel); BIT 103 drivers/media/pci/tw686x/tw686x-core.c dev->pending_dma_cmd &= ~BIT(channel); BIT 117 drivers/media/pci/tw686x/tw686x-core.c dev->pending_dma_en |= dma_en | BIT(channel); BIT 118 drivers/media/pci/tw686x/tw686x-core.c dev->pending_dma_cmd |= dma_cmd | DMA_CMD_ENABLE | BIT(channel); BIT 114 drivers/media/pci/tw686x/tw686x-regs.h #define DMA_CMD_ENABLE BIT(31) BIT 115 drivers/media/pci/tw686x/tw686x-regs.h #define INT_STATUS_DMA_TOUT BIT(17) BIT 116 drivers/media/pci/tw686x/tw686x-regs.h #define TW686X_VIDSTAT_HLOCK BIT(6) BIT 117 drivers/media/pci/tw686x/tw686x-regs.h #define TW686X_VIDSTAT_VDLOSS BIT(7) BIT 211 drivers/media/pci/tw686x/tw686x-video.c cpu_to_le32(BIT(30) | entry_len); BIT 701 drivers/media/pci/tw686x/tw686x-video.c val |= BIT(23); BIT 703 drivers/media/pci/tw686x/tw686x-video.c val &= ~BIT(23); BIT 706 drivers/media/pci/tw686x/tw686x-video.c val |= BIT(24); BIT 708 drivers/media/pci/tw686x/tw686x-video.c val &= ~BIT(24); BIT 855 drivers/media/pci/tw686x/tw686x-video.c if (!(detected_std & BIT(7))) BIT 862 drivers/media/pci/tw686x/tw686x-video.c if (detected_std & BIT(7)) BIT 1103 drivers/media/pci/tw686x/tw686x-video.c if (vc->no_signal && !(fifo_status & BIT(ch))) { BIT 1107 drivers/media/pci/tw686x/tw686x-video.c *reset_ch |= BIT(ch); BIT 1111 drivers/media/pci/tw686x/tw686x-video.c vc->no_signal = !!(fifo_status & BIT(ch)); BIT 1117 drivers/media/pci/tw686x/tw686x-video.c fifo_ov = (fifo_status >> 24) & BIT(ch); BIT 1118 drivers/media/pci/tw686x/tw686x-video.c fifo_bad = (fifo_status >> 16) & BIT(ch); BIT 1123 drivers/media/pci/tw686x/tw686x-video.c *reset_ch |= BIT(ch); BIT 1129 drivers/media/pci/tw686x/tw686x-video.c pb = !!(pb_status & BIT(ch)); BIT 1135 drivers/media/pci/tw686x/tw686x-video.c *reset_ch |= BIT(ch); BIT 69 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_WEN_ENABLE BIT(17) BIT 71 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_VDHDEN_ENABLE BIT(16) BIT 72 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_LPF_ENABLE BIT(14) BIT 73 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_ALAW_ENABLE BIT(3) BIT 75 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_BLK_CLAMP_ENABLE BIT(31) BIT 88 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_LATCH_ON_VSYNC_DISABLE BIT(15) BIT 89 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_DATA_PACK_ENABLE BIT(11) BIT 117 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_SYN_MODE_VD_POL_NEGATIVE BIT(2) BIT 119 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_CCDCFG_BW656_10BIT BIT(5) BIT 122 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_VDINT0 BIT(0) BIT 123 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_VDINT1 BIT(1) BIT 124 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_VDINT2 BIT(2) BIT 125 drivers/media/platform/am437x/am437x-vpfe_regs.h #define VPFE_DMA_CNTL_OVERFLOW BIT(31) BIT 60 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_TRIG_MODE_DET BIT(0) BIT 61 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_TRIG_CAPTURE BIT(1) BIT 62 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_FORCE_IDLE BIT(2) BIT 63 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_MULT_FRAME BIT(3) BIT 64 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_TRIG_COMP BIT(4) BIT 65 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_AUTO_COMP BIT(5) BIT 66 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_EN_WATCHDOG BIT(7) BIT 67 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_YUV420 BIT(10) BIT 69 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_HALT BIT(12) BIT 70 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_EN_WATCHDOG_COMP BIT(14) BIT 71 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_TRIG_JPG BIT(15) BIT 72 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_CAP_BUSY BIT(16) BIT 73 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_COMP_BUSY BIT(18) BIT 76 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_JPEG_MODE BIT(13) /* AST2500 */ BIT 78 drivers/media/platform/aspeed-video.c #define VE_SEQ_CTRL_JPEG_MODE BIT(8) /* AST2400 */ BIT 82 drivers/media/platform/aspeed-video.c #define VE_CTRL_HSYNC_POL BIT(0) BIT 83 drivers/media/platform/aspeed-video.c #define VE_CTRL_VSYNC_POL BIT(1) BIT 84 drivers/media/platform/aspeed-video.c #define VE_CTRL_SOURCE BIT(2) BIT 85 drivers/media/platform/aspeed-video.c #define VE_CTRL_INT_DE BIT(4) BIT 86 drivers/media/platform/aspeed-video.c #define VE_CTRL_DIRECT_FETCH BIT(5) BIT 87 drivers/media/platform/aspeed-video.c #define VE_CTRL_YUV BIT(6) BIT 88 drivers/media/platform/aspeed-video.c #define VE_CTRL_RGB BIT(7) BIT 90 drivers/media/platform/aspeed-video.c #define VE_CTRL_AUTO_OR_CURSOR BIT(8) BIT 91 drivers/media/platform/aspeed-video.c #define VE_CTRL_CLK_INVERSE BIT(11) BIT 93 drivers/media/platform/aspeed-video.c #define VE_CTRL_INTERLACE BIT(14) BIT 94 drivers/media/platform/aspeed-video.c #define VE_CTRL_HSYNC_POL_CTRL BIT(15) BIT 123 drivers/media/platform/aspeed-video.c #define VE_COMP_CTRL_VQ_DCT_ONLY BIT(0) BIT 124 drivers/media/platform/aspeed-video.c #define VE_COMP_CTRL_VQ_4COLOR BIT(1) BIT 125 drivers/media/platform/aspeed-video.c #define VE_COMP_CTRL_QUANTIZE BIT(2) BIT 126 drivers/media/platform/aspeed-video.c #define VE_COMP_CTRL_EN_BQ BIT(4) BIT 127 drivers/media/platform/aspeed-video.c #define VE_COMP_CTRL_EN_CRYPTO BIT(5) BIT 130 drivers/media/platform/aspeed-video.c #define VE_COMP_CTRL_EN_HQ BIT(16) BIT 131 drivers/media/platform/aspeed-video.c #define VE_COMP_CTRL_RSVD BIT(19) BIT 140 drivers/media/platform/aspeed-video.c #define VE_SRC_LR_EDGE_DET_NO_V BIT(12) BIT 141 drivers/media/platform/aspeed-video.c #define VE_SRC_LR_EDGE_DET_NO_H BIT(13) BIT 142 drivers/media/platform/aspeed-video.c #define VE_SRC_LR_EDGE_DET_NO_DISP BIT(14) BIT 143 drivers/media/platform/aspeed-video.c #define VE_SRC_LR_EDGE_DET_NO_CLK BIT(15) BIT 146 drivers/media/platform/aspeed-video.c #define VE_SRC_LR_EDGE_DET_INTERLACE BIT(31) BIT 157 drivers/media/platform/aspeed-video.c #define VE_MODE_DETECT_STATUS_VSYNC BIT(28) BIT 158 drivers/media/platform/aspeed-video.c #define VE_MODE_DETECT_STATUS_HSYNC BIT(29) BIT 167 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_MODE_DETECT_WD BIT(0) BIT 168 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_CAPTURE_COMPLETE BIT(1) BIT 169 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_COMP_READY BIT(2) BIT 170 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_COMP_COMPLETE BIT(3) BIT 171 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_MODE_DETECT BIT(4) BIT 172 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_FRAME_COMPLETE BIT(5) BIT 173 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_DECODE_ERR BIT(6) BIT 174 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_HALT_READY BIT(8) BIT 175 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_HANG_WD BIT(9) BIT 176 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_STREAM_DESC BIT(10) BIT 177 drivers/media/platform/aspeed-video.c #define VE_INTERRUPT_VSYNC_DESC BIT(11) BIT 1504 drivers/media/platform/aspeed-video.c const u64 mask = ~(BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_444) | BIT 1505 drivers/media/platform/aspeed-video.c BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_420)); BIT 643 drivers/media/platform/atmel/atmel-isc-base.c val = pipeline & BIT(i) ? 1 : 0; BIT 16 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CTRL_CAPTURE BIT(0) BIT 17 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CTRL_UPPRO BIT(1) BIT 18 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CTRL_HISREQ BIT(2) BIT 19 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CTRL_HISCLR BIT(3) BIT 24 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG0_HPOL_LOW BIT(0) BIT 25 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG0_VPOL_LOW BIT(1) BIT 26 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG0_PPOL_LOW BIT(2) BIT 27 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG0_CCIR656 BIT(9) BIT 28 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG0_CCIR_CRC BIT(10) BIT 40 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG0_COLEN BIT(12) BIT 41 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG0_ROWEN BIT(13) BIT 67 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CLKSR_SIP BIT(31) BIT 69 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CLK(n) BIT(n) BIT 90 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_INT_DDONE BIT(8) BIT 91 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_INT_HISDONE BIT(12) BIT 118 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CFA_CFG_EITPOL BIT(4) BIT 220 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_HIS_CTRL_EN BIT(0) BIT 236 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_HIS_CFG_RAR BIT(8) BIT 73 drivers/media/platform/atmel/atmel-isc.h #define WB_ENABLE BIT(0) BIT 74 drivers/media/platform/atmel/atmel-isc.h #define CFA_ENABLE BIT(1) BIT 75 drivers/media/platform/atmel/atmel-isc.h #define CC_ENABLE BIT(2) BIT 76 drivers/media/platform/atmel/atmel-isc.h #define GAM_ENABLE BIT(3) BIT 77 drivers/media/platform/atmel/atmel-isc.h #define GAM_BENABLE BIT(4) BIT 78 drivers/media/platform/atmel/atmel-isc.h #define GAM_GENABLE BIT(5) BIT 79 drivers/media/platform/atmel/atmel-isc.h #define GAM_RENABLE BIT(6) BIT 80 drivers/media/platform/atmel/atmel-isc.h #define CSC_ENABLE BIT(7) BIT 81 drivers/media/platform/atmel/atmel-isc.h #define CBC_ENABLE BIT(8) BIT 82 drivers/media/platform/atmel/atmel-isc.h #define SUB422_ENABLE BIT(9) BIT 83 drivers/media/platform/atmel/atmel-isc.h #define SUB420_ENABLE BIT(10) BIT 26 drivers/media/platform/cadence/cdns-csi2rx.c #define CSI2RX_SOFT_RESET_PROTOCOL BIT(1) BIT 27 drivers/media/platform/cadence/cdns-csi2rx.c #define CSI2RX_SOFT_RESET_FRONT BIT(0) BIT 36 drivers/media/platform/cadence/cdns-csi2rx.c #define CSI2RX_STREAM_CTRL_START BIT(0) BIT 39 drivers/media/platform/cadence/cdns-csi2rx.c #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) BIT 40 drivers/media/platform/cadence/cdns-csi2rx.c #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) BIT 337 drivers/media/platform/cadence/cdns-csi2rx.c csi2rx->has_internal_dphy = dev_cfg & BIT(3) ? true : false; BIT 25 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_DEVICE_CONFIG_HAS_DPHY BIT(3) BIT 29 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_CONFIG_CFG_REQ BIT(2) BIT 30 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_CONFIG_SRST_REQ BIT(1) BIT 33 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_DPHY_CFG_CLK_RESET BIT(16) BIT 34 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_DPHY_CFG_LANE_RESET(n) BIT((n) + 12) BIT 39 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_DPHY_CFG_CLK_ENABLE BIT(4) BIT 40 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_DPHY_CFG_LANE_ENABLE(n) BIT(n) BIT 57 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_V2_DPHY_CFG_RESET BIT(16) BIT 58 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_V2_DPHY_CFG_CLOCK_MODE BIT(10) BIT 63 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_V2_DPHY_CFG_CLK_ENABLE BIT(4) BIT 64 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_V2_DPHY_CFG_LANE_ENABLE(n) BIT(n) BIT 1230 drivers/media/platform/coda/coda-bit.c value |= BIT(31); /* disable autoskip */ BIT 11 drivers/media/platform/coda/coda-gdi.c #define XY2_INVERT BIT(7) BIT 12 drivers/media/platform/coda/coda-gdi.c #define XY2_ZERO BIT(6) BIT 13 drivers/media/platform/coda/coda-gdi.c #define XY2_TB_XOR BIT(5) BIT 14 drivers/media/platform/coda/coda-gdi.c #define XY2_XYSEL BIT(4) BIT 347 drivers/media/platform/coda/coda_regs.h #define CODA_PARAM_CHANGE_RC_GOP BIT(0) BIT 348 drivers/media/platform/coda/coda_regs.h #define CODA_PARAM_CHANGE_RC_INTRA_QP BIT(1) BIT 349 drivers/media/platform/coda/coda_regs.h #define CODA_PARAM_CHANGE_RC_BITRATE BIT(2) BIT 350 drivers/media/platform/coda/coda_regs.h #define CODA_PARAM_CHANGE_RC_FRAME_RATE BIT(3) BIT 351 drivers/media/platform/coda/coda_regs.h #define CODA_PARAM_CHANGE_INTRA_MB_NUM BIT(4) BIT 352 drivers/media/platform/coda/coda_regs.h #define CODA_PARAM_CHANGE_SLICE_MODE BIT(5) BIT 353 drivers/media/platform/coda/coda_regs.h #define CODA_PARAM_CHANGE_HEC_MODE BIT(6) BIT 385 drivers/media/platform/coda/coda_regs.h #define CODA_FORCE_IPICTURE BIT(1) BIT 386 drivers/media/platform/coda/coda_regs.h #define CODA_REPORT_MB_INFO BIT(3) BIT 387 drivers/media/platform/coda/coda_regs.h #define CODA_REPORT_MV_INFO BIT(4) BIT 388 drivers/media/platform/coda/coda_regs.h #define CODA_REPORT_SLICE_INFO BIT(5) BIT 472 drivers/media/platform/coda/coda_regs.h #define CODA9_XY2RBC_SEPARATE_MAP BIT(19) BIT 473 drivers/media/platform/coda/coda_regs.h #define CODA9_XY2RBC_TOP_BOT_SPLIT BIT(18) BIT 474 drivers/media/platform/coda/coda_regs.h #define CODA9_XY2RBC_TILED_MAP BIT(17) BIT 475 drivers/media/platform/coda/coda_regs.h #define CODA9_XY2RBC_CA_INC_HOR BIT(16) BIT 42 drivers/media/platform/coda/imx-vdoa.c #define VDOAC_ISEL BIT(6) BIT 43 drivers/media/platform/coda/imx-vdoa.c #define VDOAC_PFS BIT(5) BIT 44 drivers/media/platform/coda/imx-vdoa.c #define VDOAC_SO BIT(4) BIT 45 drivers/media/platform/coda/imx-vdoa.c #define VDOAC_SYNC BIT(3) BIT 46 drivers/media/platform/coda/imx-vdoa.c #define VDOAC_NF BIT(2) BIT 52 drivers/media/platform/coda/imx-vdoa.c #define VDOASRR_START BIT(1) BIT 53 drivers/media/platform/coda/imx-vdoa.c #define VDOASRR_SWRST BIT(0) BIT 55 drivers/media/platform/coda/imx-vdoa.c #define VDOAIE_EITERR BIT(1) BIT 56 drivers/media/platform/coda/imx-vdoa.c #define VDOAIE_EIEOT BIT(0) BIT 58 drivers/media/platform/coda/imx-vdoa.c #define VDOAIST_TERR BIT(1) BIT 59 drivers/media/platform/coda/imx-vdoa.c #define VDOAIST_EOT BIT(0) BIT 67 drivers/media/platform/coda/imx-vdoa.c #define VDOASR_ERRW BIT(4) BIT 68 drivers/media/platform/coda/imx-vdoa.c #define VDOASR_EOB BIT(3) BIT 70 drivers/media/platform/coda/imx-vdoa.c #define VDOASR_CURRENT_BUFFER BIT(1) BIT 69 drivers/media/platform/davinci/dm644x_ccdc_regs.h #define CCDC_WEN_ENABLE BIT(17) BIT 71 drivers/media/platform/davinci/dm644x_ccdc_regs.h #define CCDC_VDHDEN_ENABLE BIT(16) BIT 72 drivers/media/platform/davinci/dm644x_ccdc_regs.h #define CCDC_LPF_ENABLE BIT(14) BIT 73 drivers/media/platform/davinci/dm644x_ccdc_regs.h #define CCDC_ALAW_ENABLE BIT(3) BIT 75 drivers/media/platform/davinci/dm644x_ccdc_regs.h #define CCDC_BLK_CLAMP_ENABLE BIT(31) BIT 88 drivers/media/platform/davinci/dm644x_ccdc_regs.h #define CCDC_LATCH_ON_VSYNC_DISABLE BIT(15) BIT 89 drivers/media/platform/davinci/dm644x_ccdc_regs.h #define CCDC_FPC_ENABLE BIT(15) BIT 92 drivers/media/platform/davinci/dm644x_ccdc_regs.h #define CCDC_DATA_PACK_ENABLE BIT(11) BIT 135 drivers/media/platform/davinci/dm644x_ccdc_regs.h #define CCDC_SYN_MODE_VD_POL_NEGATIVE BIT(2) BIT 137 drivers/media/platform/davinci/dm644x_ccdc_regs.h #define CCDC_CCDCFG_BW656_10BIT BIT(5) BIT 455 drivers/media/platform/davinci/isif.c val &= ~BIT(ISIF_DFCMEMCTL_DFCMARST_SHIFT); BIT 594 drivers/media/platform/davinci/isif.c val = BIT(ISIF_DPCM_EN_SHIFT) | BIT 39 drivers/media/platform/davinci/vpss.c #define DM365_ISP5_PCCR_BL_CLK_ENABLE BIT(0) BIT 40 drivers/media/platform/davinci/vpss.c #define DM365_ISP5_PCCR_ISIF_CLK_ENABLE BIT(1) BIT 41 drivers/media/platform/davinci/vpss.c #define DM365_ISP5_PCCR_H3A_CLK_ENABLE BIT(2) BIT 42 drivers/media/platform/davinci/vpss.c #define DM365_ISP5_PCCR_RSZ_CLK_ENABLE BIT(3) BIT 43 drivers/media/platform/davinci/vpss.c #define DM365_ISP5_PCCR_IPIPE_CLK_ENABLE BIT(4) BIT 44 drivers/media/platform/davinci/vpss.c #define DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE BIT(5) BIT 45 drivers/media/platform/davinci/vpss.c #define DM365_ISP5_PCCR_RSV BIT(6) BIT 48 drivers/media/platform/davinci/vpss.c #define DM365_ISP5_BCR_ISIF_OUT_ENABLE BIT(1) BIT 58 drivers/media/platform/davinci/vpss.c #define VPSS_CLK_CTRL_VENCCLKEN BIT(3) BIT 59 drivers/media/platform/davinci/vpss.c #define VPSS_CLK_CTRL_DACCLKEN BIT(4) BIT 198 drivers/media/platform/exynos4-is/fimc-isp-video.c video->buf_mask |= BIT(ivb->index); BIT 250 drivers/media/platform/exynos4-is/fimc-isp-video.c video->buf_mask &= ~BIT(buf_index); BIT 280 drivers/media/platform/exynos4-is/fimc-lite-reg.c cfg |= BIT(index); BIT 292 drivers/media/platform/exynos4-is/fimc-lite-reg.c cfg &= ~BIT(index); BIT 32 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE BIT(21) BIT 33 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_ODMA_DISABLE BIT(20) BIT 34 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_SWRST_REQ BIT(19) BIT 35 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_SWRST_RDY BIT(18) BIT 36 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_SWRST BIT(17) BIT 37 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR BIT(15) BIT 38 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_INVPOLPCLK BIT(14) BIT 39 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_INVPOLVSYNC BIT(13) BIT 40 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_INVPOLHREF BIT(12) BIT 42 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_IRQ_LASTEN BIT(8) BIT 43 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_IRQ_ENDEN BIT(7) BIT 44 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_IRQ_STARTEN BIT(6) BIT 45 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_IRQ_OVFEN BIT(5) BIT 47 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGCTRL_SELCAM_MIPI BIT(3) BIT 51 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIIMGCPT_IMGCPTEN BIT(31) BIT 52 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIIMGCPT_CPT_FREN BIT(25) BIT 61 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIWDOFST_WINOFSEN BIT(31) BIT 62 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIWDOFST_CLROVIY BIT(31) BIT 63 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIWDOFST_CLROVFICB BIT(15) BIT 64 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIWDOFST_CLROVFICR BIT(14) BIT 72 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIODMAFMT_RAW_CON BIT(15) BIT 73 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIODMAFMT_PACK12 BIT(14) BIT 93 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_MIPI_VVALID BIT(22) BIT 94 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_MIPI_HVALID BIT(21) BIT 95 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_MIPI_DVALID BIT(20) BIT 96 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_ITU_VSYNC BIT(14) BIT 97 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_ITU_HREFF BIT(13) BIT 98 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_OVFIY BIT(10) BIT 99 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_OVFICB BIT(9) BIT 100 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_OVFICR BIT(8) BIT 101 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW BIT(7) BIT 102 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND BIT(6) BIT 103 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART BIT(5) BIT 104 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND BIT(4) BIT 105 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS_IRQ_CAM BIT(0) BIT 110 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS2_LASTCAPEND BIT(1) BIT 111 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CISTATUS2_FRMEND BIT(0) BIT 115 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CITHOLD_W_QOS_EN BIT(30) BIT 120 drivers/media/platform/exynos4-is/fimc-lite-reg.h #define FLITE_REG_CIGENERAL_CAM_B BIT(0) BIT 17 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31) BIT 18 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29) BIT 26 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIWDOFST_OFF_EN BIT(31) BIT 27 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30) BIT 28 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29) BIT 30 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15) BIT 31 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14) BIT 36 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_SWRST BIT(31) BIT 37 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_CAMRST_A BIT(30) BIT 38 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_SELCAM_ITU_A BIT(29) BIT 45 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_INVPOLPCLK BIT(26) BIT 46 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_INVPOLVSYNC BIT(25) BIT 47 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_INVPOLHREF BIT(24) BIT 48 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_IRQ_OVFEN BIT(22) BIT 49 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_HREF_MASK BIT(21) BIT 50 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_IRQ_LEVEL BIT(20) BIT 51 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_IRQ_CLR BIT(19) BIT 52 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_IRQ_ENABLE BIT(16) BIT 53 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_SHDW_DISABLE BIT(12) BIT 55 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_SELWB_A BIT(10) BIT 56 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_CAM_JPEG BIT(8) BIT 57 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_SELCAM_MIPI_A BIT(7) BIT 58 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_CAMIF_SELWB BIT(6) BIT 60 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_CSC_ITU601_709 BIT(5) BIT 61 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_INVPOLHSYNC BIT(4) BIT 62 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_SELCAM_MIPI BIT(3) BIT 63 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_INVPOLFIELD BIT(1) BIT 64 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIGCTRL_INTERLACE BIT(0) BIT 78 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CITRGFMT_INROT90 BIT(31) BIT 91 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CITRGFMT_OUTROT90 BIT(13) BIT 101 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIOCTRL_LASTIRQ_ENABLE BIT(2) BIT 121 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISCCTRL_SCALERBYPASS BIT(31) BIT 122 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISCCTRL_SCALEUP_H BIT(30) BIT 123 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISCCTRL_SCALEUP_V BIT(29) BIT 124 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISCCTRL_CSCR2Y_WIDE BIT(28) BIT 125 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISCCTRL_CSCY2R_WIDE BIT(27) BIT 126 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISCCTRL_LCDPATHEN_FIFO BIT(26) BIT 127 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISCCTRL_INTERLACE BIT(25) BIT 128 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISCCTRL_SCALERSTART BIT(15) BIT 137 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISCCTRL_RGB_EXT BIT(10) BIT 138 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISCCTRL_ONE2ONE BIT(9) BIT 152 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_OVFIY BIT(31) BIT 153 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_OVFICB BIT(30) BIT 154 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_OVFICR BIT(29) BIT 155 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_VSYNC BIT(28) BIT 158 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_WINOFF_EN BIT(25) BIT 159 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_IMGCPT_EN BIT(22) BIT 160 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_IMGCPT_SCEN BIT(21) BIT 161 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_VSYNC_A BIT(20) BIT 162 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_VSYNC_B BIT(19) BIT 163 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_OVRLB BIT(18) BIT 164 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_FRAME_END BIT(17) BIT 165 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_LASTCAPT_END BIT(16) BIT 166 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_VVALID_A BIT(15) BIT 167 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CISTATUS_VVALID_B BIT(14) BIT 174 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIIMGCPT_IMGCPTEN BIT(31) BIT 175 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIIMGCPT_IMGCPTEN_SC BIT(30) BIT 176 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE BIT(25) BIT 177 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT BIT(18) BIT 184 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIIMGEFF_IE_ENABLE BIT(30) BIT 203 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN BIT(31) BIT 204 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS BIT(30) BIT 220 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_MSCTRL_FIFO_CTRL_FULL BIT(12) BIT 228 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_MSCTRL_INPUT_MEMORY BIT(3) BIT 229 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_MSCTRL_INPUT_MASK BIT(3) BIT 235 drivers/media/platform/exynos4-is/fimc-reg.h #define FIMC_REG_MSCTRL_ENVID BIT(0) BIT 282 drivers/media/platform/exynos4-is/fimc-reg.h #define SYSREG_ISPBLK_FIFORST_CAM_BLK BIT(7) BIT 285 drivers/media/platform/exynos4-is/fimc-reg.h #define SYSREG_CAMBLK_FIFORST_ISP BIT(15) BIT 35 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CLK_CNTL_DUAL_EN BIT(28) BIT 36 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CLK_CNTL_OUTPUT_EN BIT(30) BIT 37 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CLK_CNTL_INPUT_EN BIT(31) BIT 43 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CLK_CNTL_BYPASS_EN BIT(24) BIT 63 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_GEN_CNTL_RESET BIT(0) BIT 68 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_GEN_CNTL_SYS_CLK_EN BIT(3) BIT 88 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_RW_WRITE_EN BIT(16) BIT 89 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_RW_BUS_BUSY BIT(23) BIT 105 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_INTR_DONE BIT(0) BIT 106 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_INTR_EOM BIT(1) BIT 107 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_INTR_NACK BIT(2) BIT 108 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_INTR_ARB_LOSS BIT(3) BIT 109 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_INTR_INITIATOR_ERR BIT(4) BIT 110 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_INTR_FOLLOWER_ERR BIT(5) BIT 111 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_INTR_WAKE_UP BIT(6) BIT 117 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CTRL_SEND BIT(0) BIT 167 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_LOCK_BUF_EN BIT(0) BIT 513 drivers/media/platform/meson/ao-cec-g12a.c BIT(logical_addr), BIT 514 drivers/media/platform/meson/ao-cec-g12a.c BIT(logical_addr)); BIT 517 drivers/media/platform/meson/ao-cec-g12a.c BIT(logical_addr - 8), BIT 518 drivers/media/platform/meson/ao-cec-g12a.c BIT(logical_addr - 8)); BIT 523 drivers/media/platform/meson/ao-cec-g12a.c BIT(CEC_LOG_ADDR_UNREGISTERED - 8), BIT 524 drivers/media/platform/meson/ao-cec-g12a.c BIT(CEC_LOG_ADDR_UNREGISTERED - 8)); BIT 37 drivers/media/platform/meson/ao-cec.c #define CEC_GEN_CNTL_RESET BIT(0) BIT 56 drivers/media/platform/meson/ao-cec.c #define CEC_RW_WRITE_EN BIT(16) BIT 57 drivers/media/platform/meson/ao-cec.c #define CEC_RW_BUS_BUSY BIT(23) BIT 68 drivers/media/platform/meson/ao-cec.c #define CEC_INTR_TX BIT(1) BIT 69 drivers/media/platform/meson/ao-cec.c #define CEC_INTR_RX BIT(2) BIT 213 drivers/media/platform/meson/ao-cec.c #define LOGICAL_ADDR_VALID BIT(4) BIT 18 drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h #define MTK_JPEG_FMT_FLAG_DEC_OUTPUT BIT(0) BIT 19 drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h #define MTK_JPEG_FMT_FLAG_DEC_CAPTURE BIT(1) BIT 27 drivers/media/platform/mtk-mdp/mtk_mdp_core.h #define MTK_MDP_FMT_FLAG_OUTPUT BIT(0) BIT 28 drivers/media/platform/mtk-mdp/mtk_mdp_core.h #define MTK_MDP_FMT_FLAG_CAPTURE BIT(1) BIT 30 drivers/media/platform/mtk-mdp/mtk_mdp_core.h #define MTK_MDP_VPU_INIT BIT(0) BIT 31 drivers/media/platform/mtk-mdp/mtk_mdp_core.h #define MTK_MDP_SRC_FMT BIT(1) BIT 32 drivers/media/platform/mtk-mdp/mtk_mdp_core.h #define MTK_MDP_DST_FMT BIT(2) BIT 33 drivers/media/platform/mtk-mdp/mtk_mdp_core.h #define MTK_MDP_CTX_ERROR BIT(5) BIT 62 drivers/media/platform/mtk-vpu/mtk_vpu.c #define VPU_IPC_INT BIT(8) BIT 230 drivers/media/platform/mtk-vpu/mtk_vpu.c return vpu_cfg_readl(vpu, VPU_RESET) & BIT(0); BIT 48 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1) BIT 58 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0) BIT 61 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11) BIT 62 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10) BIT 63 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9) BIT 64 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8) BIT 65 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7) BIT 66 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5) BIT 67 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ BIT(4) BIT 68 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ BIT(3) BIT 69 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ BIT(2) BIT 70 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ BIT(1) BIT 71 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ BIT(0) BIT 76 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ BIT(0) BIT 77 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ BIT(1) BIT 80 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_CTRL_IF_EN BIT(0) BIT 81 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_CTRL_PHY_SEL BIT(1) BIT 86 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_CTRL_IO_OUT_SEL BIT(2) BIT 89 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_CTRL_MODE BIT(4) BIT 90 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_CTRL_VP_CLK_FORCE_ON BIT(9) BIT 91 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_CTRL_INV BIT(10) BIT 94 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_CTRL_VP_ONLY_EN BIT(11) BIT 95 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_CTRL_VP_CLK_POL BIT(12) BIT 105 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LCx_CTRL_CHAN_EN BIT(0) BIT 106 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LCx_CTRL_CRC_EN BIT(19) BIT 110 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LCx_CTRL_REGION_EN BIT(1) BIT 130 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LCM_CTRL_CHAN_EN BIT(0) BIT 131 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LCM_CTRL_DST_PORT BIT(2) BIT 141 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED BIT(22) BIT 142 drivers/media/platform/omap3isp/ispreg.h #define ISPCCP2_LCM_CTRL_SRC_PACK BIT(23) BIT 204 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_H3A_AEAWB_WBL_OVF BIT(16) BIT 205 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_H3A_AF_WBL_OVF BIT(17) BIT 206 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_RSZ4_WBL_OVF BIT(18) BIT 207 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_RSZ3_WBL_OVF BIT(19) BIT 208 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_RSZ2_WBL_OVF BIT(20) BIT 209 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_RSZ1_WBL_OVF BIT(21) BIT 210 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_PRV_WBL_OVF BIT(22) BIT 211 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_CCDC_WBL_OVF BIT(23) BIT 212 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF BIT(24) BIT 213 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_CSIA_WBL_OVF BIT(25) BIT 214 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_PCR_CSIB_WBL_OVF BIT(26) BIT 216 drivers/media/platform/omap3isp/ispreg.h #define ISPSBL_CCDC_WR_0_DATA_READY BIT(21) BIT 369 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_BUSY BIT(1) BIT 370 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_SOURCE BIT(2) BIT 371 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_ONESHOT BIT(3) BIT 372 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_WIDTH BIT(4) BIT 373 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_INVALAW BIT(5) BIT 374 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_DRKFEN BIT(6) BIT 375 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_DRKFCAP BIT(7) BIT 376 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_HMEDEN BIT(8) BIT 377 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_NFEN BIT(9) BIT 378 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_CFAEN BIT(10) BIT 387 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_YNENHEN BIT(15) BIT 388 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_SUPEN BIT(16) BIT 394 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_RSZPORT BIT(19) BIT 395 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_SDRPORT BIT(20) BIT 396 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_SCOMP_EN BIT(21) BIT 399 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_GAMMA_BYPASS BIT(26) BIT 400 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_DCOREN BIT(27) BIT 401 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_DCCOUP BIT(28) BIT 402 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_PCR_DRK_FAIL BIT(31) BIT 426 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_HMED_EVENDIST BIT(8) BIT 427 drivers/media/platform/omap3isp/ispreg.h #define ISPPRV_HMED_ODDDIST BIT(9) BIT 520 drivers/media/platform/omap3isp/ispreg.h #define ISP_SYSCONFIG_AUTOIDLE BIT(0) BIT 521 drivers/media/platform/omap3isp/ispreg.h #define ISP_SYSCONFIG_SOFTRESET BIT(1) BIT 529 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CSIA_IRQ BIT(0) BIT 530 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CSIC_IRQ BIT(1) BIT 531 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCP2_LCM_IRQ BIT(3) BIT 532 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCP2_LC0_IRQ BIT(4) BIT 533 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCP2_LC1_IRQ BIT(5) BIT 534 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCP2_LC2_IRQ BIT(6) BIT 535 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCP2_LC3_IRQ BIT(7) BIT 542 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCDC_VD0_IRQ BIT(8) BIT 543 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCDC_VD1_IRQ BIT(9) BIT 544 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCDC_VD2_IRQ BIT(10) BIT 545 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCDC_ERR_IRQ BIT(11) BIT 546 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_H3A_AF_DONE_IRQ BIT(12) BIT 547 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_H3A_AWB_DONE_IRQ BIT(13) BIT 548 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_HIST_DONE_IRQ BIT(16) BIT 549 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCDC_LSC_DONE_IRQ BIT(17) BIT 550 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ BIT(18) BIT 551 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ BIT(19) BIT 552 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_PRV_DONE_IRQ BIT(20) BIT 553 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_RSZ_DONE_IRQ BIT(24) BIT 554 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_OVF_IRQ BIT(25) BIT 555 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_PING_IRQ BIT(26) BIT 556 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_PONG_IRQ BIT(27) BIT 557 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_MMU_ERR_IRQ BIT(28) BIT 558 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_OCP_ERR_IRQ BIT(29) BIT 559 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_SEC_ERR_IRQ BIT(30) BIT 560 drivers/media/platform/omap3isp/ispreg.h #define IRQ0ENABLE_HS_VS_IRQ BIT(31) BIT 562 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CSIA_IRQ BIT(0) BIT 563 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CSI2C_IRQ BIT(1) BIT 564 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CCP2_LCM_IRQ BIT(3) BIT 565 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CCP2_LC0_IRQ BIT(4) BIT 569 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CSIB_LC1_IRQ BIT(5) BIT 570 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CSIB_LC2_IRQ BIT(6) BIT 571 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CSIB_LC3_IRQ BIT(7) BIT 572 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CCDC_VD0_IRQ BIT(8) BIT 573 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CCDC_VD1_IRQ BIT(9) BIT 574 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CCDC_VD2_IRQ BIT(10) BIT 575 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CCDC_ERR_IRQ BIT(11) BIT 576 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_H3A_AF_DONE_IRQ BIT(12) BIT 577 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_H3A_AWB_DONE_IRQ BIT(13) BIT 578 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_HIST_DONE_IRQ BIT(16) BIT 579 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CCDC_LSC_DONE_IRQ BIT(17) BIT 580 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ BIT(18) BIT 581 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ BIT(19) BIT 582 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_PRV_DONE_IRQ BIT(20) BIT 583 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_RSZ_DONE_IRQ BIT(24) BIT 584 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_OVF_IRQ BIT(25) BIT 585 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_PING_IRQ BIT(26) BIT 586 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_PONG_IRQ BIT(27) BIT 587 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_MMU_ERR_IRQ BIT(28) BIT 588 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_OCP_ERR_IRQ BIT(29) BIT 589 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_SEC_ERR_IRQ BIT(30) BIT 590 drivers/media/platform/omap3isp/ispreg.h #define IRQ0STATUS_HS_VS_IRQ BIT(31) BIT 610 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_PAR_CLK_POL_INV BIT(4) BIT 611 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_PING_PONG_EN BIT(5) BIT 618 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_CCDC_CLK_EN BIT(8) BIT 619 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_SCMP_CLK_EN BIT(9) BIT 620 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_H3A_CLK_EN BIT(10) BIT 621 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_HIST_CLK_EN BIT(11) BIT 622 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_PREV_CLK_EN BIT(12) BIT 623 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_RSZ_CLK_EN BIT(13) BIT 631 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_CCDC_RAM_EN BIT(16) BIT 632 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_PREV_RAM_EN BIT(17) BIT 633 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_SBL_RD_RAM_EN BIT(18) BIT 634 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_SBL_WR1_RAM_EN BIT(19) BIT 635 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_SBL_WR0_RAM_EN BIT(20) BIT 636 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_SBL_AUTOIDLE BIT(21) BIT 637 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_SBL_SHARED_WPORTC BIT(26) BIT 638 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_SBL_SHARED_RPORTA BIT(27) BIT 639 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_SBL_SHARED_RPORTB BIT(28) BIT 640 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_JPEG_FLUSH BIT(30) BIT 641 drivers/media/platform/omap3isp/ispreg.h #define ISPCTRL_CCDC_FLUSH BIT(31) BIT 658 drivers/media/platform/omap3isp/ispreg.h #define ISPTCTRL_CTRL_SHUTEN BIT(21) BIT 659 drivers/media/platform/omap3isp/ispreg.h #define ISPTCTRL_CTRL_PSTRBEN BIT(22) BIT 660 drivers/media/platform/omap3isp/ispreg.h #define ISPTCTRL_CTRL_STRBEN BIT(23) BIT 661 drivers/media/platform/omap3isp/ispreg.h #define ISPTCTRL_CTRL_SHUTPOL BIT(24) BIT 662 drivers/media/platform/omap3isp/ispreg.h #define ISPTCTRL_CTRL_STRBPSTRBPOL BIT(26) BIT 669 drivers/media/platform/omap3isp/ispreg.h #define ISPTCTRL_CTRL_GRESETEn BIT(29) BIT 670 drivers/media/platform/omap3isp/ispreg.h #define ISPTCTRL_CTRL_GRESETPOL BIT(30) BIT 671 drivers/media/platform/omap3isp/ispreg.h #define ISPTCTRL_CTRL_GRESETDIR BIT(31) BIT 682 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_PCR_BUSY BIT(1) BIT 685 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_FLDOUT BIT(1) BIT 686 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_VDPOL BIT(2) BIT 687 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_HDPOL BIT(3) BIT 688 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_FLDPOL BIT(4) BIT 689 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_EXWEN BIT(5) BIT 690 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_DATAPOL BIT(6) BIT 691 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_FLDMODE BIT(7) BIT 698 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_PACK8 BIT(11) BIT 703 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_LPF BIT(14) BIT 704 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_FLDSTAT BIT(15) BIT 705 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_VDHDEN BIT(16) BIT 706 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_WEN BIT(17) BIT 707 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_VP2SDR BIT(18) BIT 708 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SYN_MODE_SDR2RSZ BIT(19) BIT 734 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_SDOFST_FIINV BIT(14) BIT 746 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_CLAMP_CLAMPEN BIT(31) BIT 775 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_FPC_FPCEN BIT(15) BIT 776 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_FPC_FPERR BIT(16) BIT 787 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_ALAW_CCDTBL BIT(3) BIT 790 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_REC656IF_ECCFVH BIT(1) BIT 792 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_CFG_BW656 BIT(5) BIT 794 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_CFG_WENLOG BIT(8) BIT 797 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_CFG_Y8POS BIT(11) BIT 798 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_CFG_BSWD BIT(12) BIT 799 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_CFG_MSBINVI BIT(13) BIT 800 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_CFG_VDLC BIT(15) BIT 803 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_FMTCFG_LNALT BIT(1) BIT 812 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_FMTCFG_VPEN BIT(15) BIT 842 drivers/media/platform/omap3isp/ispreg.h #define ISPRSZ_PCR_ENABLE BIT(0) BIT 843 drivers/media/platform/omap3isp/ispreg.h #define ISPRSZ_PCR_BUSY BIT(1) BIT 844 drivers/media/platform/omap3isp/ispreg.h #define ISPRSZ_PCR_ONESHOT BIT(2) BIT 856 drivers/media/platform/omap3isp/ispreg.h #define ISPRSZ_CNT_YCPOS BIT(26) BIT 857 drivers/media/platform/omap3isp/ispreg.h #define ISPRSZ_CNT_INPTYP BIT(27) BIT 858 drivers/media/platform/omap3isp/ispreg.h #define ISPRSZ_CNT_INPSRC BIT(28) BIT 859 drivers/media/platform/omap3isp/ispreg.h #define ISPRSZ_CNT_CBILIN BIT(29) BIT 1084 drivers/media/platform/omap3isp/ispreg.h #define ISPH3A_PCR_BUSYAF BIT(15) BIT 1085 drivers/media/platform/omap3isp/ispreg.h #define ISPH3A_PCR_BUSYAEAWB BIT(18) BIT 1169 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_LSC_ENABLE BIT(0) BIT 1170 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_LSC_BUSY BIT(7) BIT 1177 drivers/media/platform/omap3isp/ispreg.h #define ISPCCDC_LSC_AFTER_REFORMATTER_MASK BIT(6) BIT 1199 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_SYSCONFIG_SOFT_RESET BIT(1) BIT 1200 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_SYSCONFIG_AUTO_IDLE BIT(0) BIT 1203 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_SYSSTATUS_RESET_DONE BIT(0) BIT 1206 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ BIT(14) BIT 1207 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ BIT(13) BIT 1208 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ BIT(12) BIT 1209 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ BIT(11) BIT 1210 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ BIT(10) BIT 1211 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ BIT(9) BIT 1212 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ BIT(8) BIT 1213 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_IRQSTATUS_CONTEXT(n) BIT(n) BIT 1217 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTRL_VP_CLK_EN BIT(15) BIT 1218 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTRL_VP_ONLY_EN BIT(11) BIT 1222 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTRL_DBG_EN BIT(7) BIT 1226 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTRL_FRAME BIT(3) BIT 1227 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTRL_ECC_EN BIT(2) BIT 1228 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTRL_SECURE BIT(1) BIT 1229 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTRL_IF_EN BIT(0) BIT 1234 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_CFG_RESET_CTRL BIT(30) BIT 1235 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_CFG_RESET_DONE BIT(29) BIT 1254 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_CFG_PWR_AUTO BIT(24) BIT 1303 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT BIT(26) BIT 1304 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER BIT(25) BIT 1305 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 BIT(24) BIT 1306 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 BIT(23) BIT 1307 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 BIT(22) BIT 1308 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 BIT(21) BIT 1309 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 BIT(20) BIT 1310 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 BIT(19) BIT 1311 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 BIT(18) BIT 1312 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 BIT(17) BIT 1313 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 BIT(16) BIT 1314 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 BIT(15) BIT 1315 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRESC5 BIT(14) BIT 1316 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRESC4 BIT(13) BIT 1317 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRESC3 BIT(12) BIT 1318 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRESC2 BIT(11) BIT 1319 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRESC1 BIT(10) BIT 1320 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 BIT(9) BIT 1321 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 BIT(8) BIT 1322 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 BIT(7) BIT 1323 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 BIT(6) BIT 1324 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 BIT(5) BIT 1325 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 BIT(4) BIT 1326 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 BIT(3) BIT 1327 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 BIT(2) BIT 1328 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 BIT(1) BIT 1329 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 BIT(0) BIT 1333 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT BIT(26) BIT 1334 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER BIT(25) BIT 1335 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_STATEULPM5 BIT(24) BIT 1336 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_STATEULPM4 BIT(23) BIT 1337 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_STATEULPM3 BIT(22) BIT 1338 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_STATEULPM2 BIT(21) BIT 1339 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_STATEULPM1 BIT(20) BIT 1340 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 BIT(19) BIT 1341 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 BIT(18) BIT 1342 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 BIT(17) BIT 1343 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 BIT(16) BIT 1344 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 BIT(15) BIT 1345 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRESC5 BIT(14) BIT 1346 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRESC4 BIT(13) BIT 1347 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRESC3 BIT(12) BIT 1348 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRESC2 BIT(11) BIT 1349 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRESC1 BIT(10) BIT 1350 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 BIT(9) BIT 1351 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 BIT(8) BIT 1352 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 BIT(7) BIT 1353 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 BIT(6) BIT 1354 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 BIT(5) BIT 1355 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 BIT(4) BIT 1356 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 BIT(3) BIT 1357 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 BIT(2) BIT 1358 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 BIT(1) BIT 1359 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 BIT(0) BIT 1374 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_CTRL1_EOF_EN BIT(7) BIT 1375 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_CTRL1_EOL_EN BIT(6) BIT 1376 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_CTRL1_CS_EN BIT(5) BIT 1377 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK BIT(4) BIT 1378 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_CTRL1_PING_PONG BIT(3) BIT 1379 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_CTRL1_CTX_EN BIT(0) BIT 1388 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_CTRL2_DPCM_PRED BIT(10) BIT 1404 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ BIT(8) BIT 1405 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ BIT(7) BIT 1406 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ BIT(6) BIT 1407 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQENABLE_CS_IRQ BIT(5) BIT 1408 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQENABLE_LE_IRQ BIT(3) BIT 1409 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQENABLE_LS_IRQ BIT(2) BIT 1410 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQENABLE_FE_IRQ BIT(1) BIT 1411 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQENABLE_FS_IRQ BIT(0) BIT 1414 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ BIT(8) BIT 1415 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ BIT(7) BIT 1416 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ BIT(6) BIT 1417 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQSTATUS_CS_IRQ BIT(5) BIT 1418 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQSTATUS_LE_IRQ BIT(3) BIT 1419 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQSTATUS_LS_IRQ BIT(2) BIT 1420 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQSTATUS_FE_IRQ BIT(1) BIT 1421 drivers/media/platform/omap3isp/ispreg.h #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ BIT(0) BIT 1457 drivers/media/platform/omap3isp/ispreg.h #define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK BIT(29) BIT 1459 drivers/media/platform/omap3isp/ispreg.h #define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS BIT(25) BIT 1501 drivers/media/platform/omap3isp/ispreg.h #define OMAP343X_CONTROL_CSIRXFE_CSIB_INV BIT(7) BIT 1502 drivers/media/platform/omap3isp/ispreg.h #define OMAP343X_CONTROL_CSIRXFE_RESENABLE BIT(8) BIT 1503 drivers/media/platform/omap3isp/ispreg.h #define OMAP343X_CONTROL_CSIRXFE_SELFORM BIT(10) BIT 1504 drivers/media/platform/omap3isp/ispreg.h #define OMAP343X_CONTROL_CSIRXFE_PWRDNZ BIT(12) BIT 1505 drivers/media/platform/omap3isp/ispreg.h #define OMAP343X_CONTROL_CSIRXFE_RESET BIT(13) BIT 1516 drivers/media/platform/omap3isp/ispreg.h #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 BIT(4) BIT 1042 drivers/media/platform/omap3isp/ispstat.c subdev->grp_id = BIT(16); /* group ID for isp subdevs */ BIT 37 drivers/media/platform/qcom/camss/camss-csid.c #define CAMSS_CSID_CID_n_CFG_ISPIF_EN BIT(0) BIT 38 drivers/media/platform/qcom/camss/camss-csid.c #define CAMSS_CSID_CID_n_CFG_RDI_EN BIT(1) BIT 18 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) BIT 20 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3) BIT 30 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c #define CSIPHY_3PH_LNn_MISC1_IS_CLKLANE BIT(2) BIT 32 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c #define CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT BIT(0) BIT 36 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c #define CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP BIT(0) BIT 37 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c #define CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE BIT(1) BIT 44 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) BIT 45 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) BIT 148 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val = BIT(c->clk.pos); BIT 150 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c val |= BIT(c->data[i].pos * 2); BIT 551 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(BIT(1) | BIT(0)); BIT 556 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(BIT(5) | BIT(4)); BIT 561 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(BIT(9) | BIT(8)); BIT 566 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(BIT(13) | BIT(12)); BIT 571 drivers/media/platform/qcom/camss/camss-ispif.c val &= ~(BIT(21) | BIT(20)); BIT 20 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) BIT 21 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) BIT 22 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) BIT 23 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) BIT 24 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) BIT 25 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_GLOBAL_RESET_CMD_TIMER BIT(5) BIT 26 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_GLOBAL_RESET_CMD_PM BIT(6) BIT 27 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(7) BIT 28 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(8) BIT 31 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_MODULE_CFG_DEMUX BIT(2) BIT 32 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_MODULE_CFG_CHROMA_UPSAMPLE BIT(3) BIT 33 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_MODULE_CFG_SCALE_ENC BIT(23) BIT 34 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_MODULE_CFG_CROP_ENC BIT(27) BIT 43 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) BIT 46 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) BIT 47 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) BIT 48 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) BIT 50 drivers/media/platform/qcom/camss/camss-vfe-4-1.c ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) BIT 51 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) BIT 52 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) BIT 53 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) BIT 55 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) BIT 56 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) BIT 57 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) BIT 58 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) BIT 59 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) BIT 65 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) BIT 66 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) BIT 68 drivers/media/platform/qcom/camss/camss-vfe-4-1.c ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) BIT 69 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) BIT 70 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) BIT 71 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) BIT 73 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) BIT 74 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) BIT 75 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) BIT 81 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) BIT 86 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(1) BIT 134 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) BIT 136 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(r) BIT(16 + (r)) BIT 142 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) BIT 144 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) BIT 151 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_CAMIF_STATUS_HALT BIT(31) BIT 154 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) BIT 203 drivers/media/platform/qcom/camss/camss-vfe-4-1.c #define VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(x) BIT(x) BIT 20 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) BIT 21 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) BIT 22 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) BIT 23 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) BIT 24 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) BIT 25 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_GLOBAL_RESET_CMD_PM BIT(5) BIT 26 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(6) BIT 27 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(7) BIT 28 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_GLOBAL_RESET_CMD_DSP BIT(8) BIT 29 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_GLOBAL_RESET_CMD_IDLE_CGC BIT(9) BIT 32 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_MODULE_LENS_EN_DEMUX BIT(2) BIT 33 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_MODULE_LENS_EN_CHROMA_UPSAMPLE BIT(3) BIT 36 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_MODULE_ZOOM_EN_SCALE_ENC BIT(1) BIT 37 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_MODULE_ZOOM_EN_CROP_ENC BIT(2) BIT 38 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_MODULE_ZOOM_EN_REALIGN_BUF BIT(9) BIT 45 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN BIT(4) BIT 48 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) BIT 51 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) BIT 52 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) BIT 53 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) BIT 55 drivers/media/platform/qcom/camss/camss-vfe-4-7.c ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) BIT 56 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) BIT 57 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) BIT 58 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) BIT 60 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) BIT 61 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) BIT 62 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) BIT 63 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) BIT 64 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) BIT 70 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) BIT 71 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) BIT 73 drivers/media/platform/qcom/camss/camss-vfe-4-7.c ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) BIT 74 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) BIT 75 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) BIT 76 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) BIT 78 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) BIT 79 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) BIT 80 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) BIT 86 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) BIT 91 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(2) BIT 92 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN BIT(3) BIT 161 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) BIT 168 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) BIT 170 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) BIT 178 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_CAMIF_STATUS_HALT BIT(31) BIT 181 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) BIT 230 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL BIT(2) BIT 231 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL BIT(3) BIT 232 drivers/media/platform/qcom/camss/camss-vfe-4-7.c #define VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE BIT(4) BIT 286 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); BIT 1367 drivers/media/platform/qcom/venus/helpers.c ret = readl_poll_timeout(stat, val, val & BIT(1), 1, 100); BIT 1373 drivers/media/platform/qcom/venus/helpers.c ret = readl_poll_timeout(stat, val, !(val & BIT(1)), 1, 100); BIT 24 drivers/media/platform/qcom/venus/hfi_parser.c cap->codec = BIT(bit); BIT 31 drivers/media/platform/qcom/venus/hfi_parser.c cap->codec = BIT(bit); BIT 371 drivers/media/platform/qcom/venus/hfi_venus.c venus_writel(hdev, CPU_IC_SOFTINT, BIT(CPU_IC_SOFTINT_H2A_SHIFT)); BIT 446 drivers/media/platform/qcom/venus/hfi_venus.c venus_writel(hdev, VIDC_CTRL_INIT, BIT(VIDC_CTRL_INIT_CTRL_SHIFT)); BIT 14 drivers/media/platform/qcom/venus/hfi_venus_io.h #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0) BIT 15 drivers/media/platform/qcom/venus/hfi_venus_io.h #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0) BIT 38 drivers/media/platform/qcom/venus/hfi_venus_io.h #define CPU_CS_SCIACMDARG0_PC_READY BIT(8) BIT 39 drivers/media/platform/qcom/venus/hfi_venus_io.h #define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK BIT(30) BIT 98 drivers/media/platform/qcom/venus/hfi_venus_io.h #define WRAPPER_CPU_AXI_HALT_HALT BIT(16) BIT 100 drivers/media/platform/qcom/venus/hfi_venus_io.h #define WRAPPER_CPU_AXI_HALT_STATUS_IDLE BIT(24) BIT 104 drivers/media/platform/qcom/venus/hfi_venus_io.h #define WRAPPER_CPU_STATUS_WFI BIT(0) BIT 113 drivers/media/platform/qcom/venus/hfi_venus_io.h #define WRAPPER_A9SS_SW_RESET_BIT BIT(4) BIT 842 drivers/media/platform/rcar-vin/rcar-core.c vin_mask |= BIT(i); BIT 861 drivers/media/platform/rcar-vin/rcar-core.c if (!(vin_mask & BIT(i))) BIT 948 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, BIT 949 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, BIT 950 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, BIT 951 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, BIT 952 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, BIT 953 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, BIT 954 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, BIT 955 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) }, BIT 956 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, BIT 957 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, BIT 958 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, BIT 959 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, BIT 960 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, BIT 961 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) }, BIT 962 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, BIT 963 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, BIT 964 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, BIT 965 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, BIT 966 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 4, .mask = BIT(2) }, BIT 967 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, BIT 968 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, BIT 969 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) }, BIT 970 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, BIT 971 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) }, BIT 972 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) }, BIT 973 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, BIT 974 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) }, BIT 975 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, BIT 976 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) }, BIT 977 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) }, BIT 978 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) }, BIT 979 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, BIT 992 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, BIT 993 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, BIT 994 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 0, .mask = BIT(2) | BIT(5) }, BIT 995 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, BIT 996 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 1, .mask = BIT(1) }, BIT 997 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, BIT 998 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) }, BIT 999 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, BIT 1000 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 1, .vin = 1, .mask = BIT(5) }, BIT 1001 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 2, .mask = BIT(0) }, BIT 1002 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, BIT 1003 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, BIT 1004 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, BIT 1005 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, BIT 1006 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 2, .vin = 2, .mask = BIT(5) }, BIT 1007 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, BIT 1008 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) }, BIT 1009 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 1, .vin = 3, .mask = BIT(2) }, BIT 1010 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, BIT 1011 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, BIT 1012 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 3, .vin = 3, .mask = BIT(5) }, BIT 1013 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, BIT 1014 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, BIT 1015 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 4, .mask = BIT(2) | BIT(5) }, BIT 1016 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, BIT 1017 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 5, .mask = BIT(1) }, BIT 1018 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) }, BIT 1019 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(3) }, BIT 1020 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, BIT 1021 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 1, .vin = 5, .mask = BIT(5) }, BIT 1022 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 6, .mask = BIT(0) }, BIT 1023 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) }, BIT 1024 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, BIT 1025 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) }, BIT 1026 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, BIT 1027 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 2, .vin = 6, .mask = BIT(5) }, BIT 1028 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) }, BIT 1029 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) }, BIT 1030 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 1, .vin = 7, .mask = BIT(2) }, BIT 1031 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) }, BIT 1032 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, BIT 1033 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 3, .vin = 7, .mask = BIT(5) }, BIT 1046 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, BIT 1047 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, BIT 1048 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, BIT 1049 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, BIT 1050 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) }, BIT 1051 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, BIT 1052 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, BIT 1053 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, BIT 1054 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, BIT 1055 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, BIT 1056 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, BIT 1057 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) }, BIT 1058 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, BIT 1059 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, BIT 1060 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, BIT 1061 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, BIT 1062 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, BIT 1063 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 5, .mask = BIT(2) }, BIT 1064 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 5, .mask = BIT(3) }, BIT 1065 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, BIT 1066 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 6, .mask = BIT(1) }, BIT 1067 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, BIT 1068 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 6, .mask = BIT(3) }, BIT 1069 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, BIT 1070 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 7, .mask = BIT(0) }, BIT 1071 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) }, BIT 1072 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 7, .mask = BIT(3) }, BIT 1073 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, BIT 1086 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, BIT 1087 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, BIT 1088 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, BIT 1089 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, BIT 1090 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, BIT 1091 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, BIT 1092 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, BIT 1093 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) }, BIT 1094 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, BIT 1095 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, BIT 1096 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, BIT 1097 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, BIT 1098 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, BIT 1099 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) }, BIT 1100 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, BIT 1101 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, BIT 1102 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, BIT 1103 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, BIT 1104 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 4, .mask = BIT(2) }, BIT 1105 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, BIT 1106 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, BIT 1107 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 5, .mask = BIT(2) }, BIT 1108 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, BIT 1109 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) }, BIT 1110 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 6, .mask = BIT(1) }, BIT 1111 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, BIT 1112 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 6, .mask = BIT(3) }, BIT 1113 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, BIT 1114 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 7, .mask = BIT(0) }, BIT 1115 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) }, BIT 1116 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 7, .mask = BIT(3) }, BIT 1117 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, BIT 1130 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, BIT 1131 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, BIT 1132 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) }, BIT 1133 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, BIT 1134 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, BIT 1135 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, BIT 1136 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, BIT 1149 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, BIT 1150 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, BIT 1151 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, BIT 1152 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, BIT 1153 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, BIT 1154 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, BIT 1155 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, BIT 1156 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, BIT 1157 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, BIT 1158 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 4, .mask = BIT(2) }, BIT 1159 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) }, BIT 1160 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, BIT 1161 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) }, BIT 1162 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) }, BIT 1163 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) }, BIT 1164 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) }, BIT 1177 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, BIT 1178 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 5, .mask = BIT(2) }, BIT 1179 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 4, .mask = BIT(2) }, BIT 1180 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, BIT 32 drivers/media/platform/rcar-vin/rcar-csi2.c #define TREF_TREF BIT(0) BIT 36 drivers/media/platform/rcar-vin/rcar-csi2.c #define SRST_SRST BIT(0) BIT 40 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHYCNT_SHUTDOWNZ BIT(17) BIT 41 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHYCNT_RSTZ BIT(16) BIT 42 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHYCNT_ENABLECLK BIT(4) BIT 43 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHYCNT_ENABLE_3 BIT(3) BIT 44 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHYCNT_ENABLE_2 BIT(2) BIT 45 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHYCNT_ENABLE_1 BIT(1) BIT 46 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHYCNT_ENABLE_0 BIT(0) BIT 50 drivers/media/platform/rcar-vin/rcar-csi2.c #define CHKSUM_ECC_EN BIT(1) BIT 51 drivers/media/platform/rcar-vin/rcar-csi2.c #define CHKSUM_CRC_EN BIT(0) BIT 60 drivers/media/platform/rcar-vin/rcar-csi2.c #define VCDT_VCDTN_EN BIT(15) BIT 62 drivers/media/platform/rcar-vin/rcar-csi2.c #define VCDT_SEL_DTN_ON BIT(6) BIT 72 drivers/media/platform/rcar-vin/rcar-csi2.c #define FLD_FLD_EN4 BIT(3) BIT 73 drivers/media/platform/rcar-vin/rcar-csi2.c #define FLD_FLD_EN3 BIT(2) BIT 74 drivers/media/platform/rcar-vin/rcar-csi2.c #define FLD_FLD_EN2 BIT(1) BIT 75 drivers/media/platform/rcar-vin/rcar-csi2.c #define FLD_FLD_EN BIT(0) BIT 88 drivers/media/platform/rcar-vin/rcar-csi2.c #define INTEN_INT_AFIFO_OF BIT(27) BIT 89 drivers/media/platform/rcar-vin/rcar-csi2.c #define INTEN_INT_ERRSOTHS BIT(4) BIT 90 drivers/media/platform/rcar-vin/rcar-csi2.c #define INTEN_INT_ERRSOTSYNCHS BIT(3) BIT 97 drivers/media/platform/rcar-vin/rcar-csi2.c #define INTSTATE_INT_ULPS_START BIT(7) BIT 98 drivers/media/platform/rcar-vin/rcar-csi2.c #define INTSTATE_INT_ULPS_END BIT(6) BIT 111 drivers/media/platform/rcar-vin/rcar-csi2.c #define LINKCNT_MONITOR_EN BIT(31) BIT 112 drivers/media/platform/rcar-vin/rcar-csi2.c #define LINKCNT_REG_MONI_PACT_EN BIT(25) BIT 113 drivers/media/platform/rcar-vin/rcar-csi2.c #define LINKCNT_ICLK_NONSTOP BIT(24) BIT 124 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHTW_DWEN BIT(24) BIT 126 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHTW_CWEN BIT(8) BIT 197 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHTC_TESTCLR BIT(0) BIT 302 drivers/media/platform/rcar-vin/rcar-csi2.c #define PHCLM_STOPSTATECKL BIT(0) BIT 78 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_RFOVF BIT(3) /* Receive FIFO overflow */ BIT 79 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_RFUDF BIT(4) /* Receive FIFO underflow */ BIT 80 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_RFSERR BIT(5) /* Receive frame sync error */ BIT 81 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_REOF BIT(7) /* Frame reception end */ BIT 82 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_RDREQ BIT(12) /* Receive data xfer req */ BIT 83 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_RFFUL BIT(13) /* Receive FIFO full */ BIT 113 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_SITMDR1_PCON BIT(30) BIT 115 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_SICTR_RX_RISING_EDGE BIT(26) BIT 116 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_SICTR_RX_EN BIT(8) BIT 117 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_SICTR_RESET BIT(0) BIT 128 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_BUF_DONE BIT(0) /* DMA completed */ BIT 129 drivers/media/platform/rcar_drif.c #define RCAR_DRIF_BUF_OVERFLOW BIT(1) /* Overflow detected */ BIT 749 drivers/media/platform/rcar_drif.c enabled |= BIT(i); BIT 782 drivers/media/platform/rcar_drif.c enabled |= BIT(i); BIT 950 drivers/media/platform/rcar_drif.c sdr->cur_ch_mask = BIT(0); BIT 1290 drivers/media/platform/rcar_drif.c sdr->hw_ch_mask |= BIT(ch->num); BIT 1437 drivers/media/platform/rcar_drif.c sdr->hw_ch_mask = BIT(ch->num); BIT 50 drivers/media/platform/rcar_fdp1.c #define FDP1_CAPTURE BIT(0) BIT 51 drivers/media/platform/rcar_fdp1.c #define FDP1_OUTPUT BIT(1) BIT 67 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_CMD_STRCMD BIT(0) BIT 71 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_SGCMD_SGEN BIT(0) BIT 75 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_REGEND_REGEND BIT(0) BIT 79 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_CHACT_SMW BIT(9) BIT 80 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_CHACT_WR BIT(8) BIT 81 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_CHACT_SMR BIT(3) BIT 82 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_CHACT_RD2 BIT(2) BIT 83 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_CHACT_RD1 BIT(1) BIT 84 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_CHACT_RD0 BIT(0) BIT 88 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_OPMODE_PRG BIT(4) BIT 95 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_CLKCTRL_CSTP_N BIT(0) BIT 99 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_SRESET_SRST BIT(0) BIT 105 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_STATUS_SGREGSET BIT(10) BIT 106 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_STATUS_SGVERR BIT(9) BIT 107 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_STATUS_SGFREND BIT(8) BIT 108 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_STATUS_BSY BIT(0) BIT 120 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_IRQ_VERE BIT(16) BIT 121 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_IRQ_VINTE BIT(4) BIT 122 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_IRQ_FREE BIT(0) BIT 134 drivers/media/platform/rcar_fdp1.c #define FD1_RPF_FORMAT_CIPM BIT(16) BIT 135 drivers/media/platform/rcar_fdp1.c #define FD1_RPF_FORMAT_RSPYCS BIT(13) BIT 136 drivers/media/platform/rcar_fdp1.c #define FD1_RPF_FORMAT_RSPUVS BIT(12) BIT 137 drivers/media/platform/rcar_fdp1.c #define FD1_RPF_FORMAT_CF BIT(8) BIT 160 drivers/media/platform/rcar_fdp1.c #define FD1_WPF_FORMAT_FCNL BIT(20) BIT 161 drivers/media/platform/rcar_fdp1.c #define FD1_WPF_FORMAT_WSPYCS BIT(15) BIT 162 drivers/media/platform/rcar_fdp1.c #define FD1_WPF_FORMAT_WSPUVS BIT(14) BIT 166 drivers/media/platform/rcar_fdp1.c #define FD1_WPF_FORMAT_CSC BIT(8) BIT 169 drivers/media/platform/rcar_fdp1.c #define FD1_WPF_RNDCTL_CBRM BIT(28) BIT 187 drivers/media/platform/rcar_fdp1.c #define FD1_RWPF_SWAP_BYTE BIT(0) BIT 188 drivers/media/platform/rcar_fdp1.c #define FD1_RWPF_SWAP_WORD BIT(1) BIT 189 drivers/media/platform/rcar_fdp1.c #define FD1_RWPF_SWAP_LWRD BIT(2) BIT 190 drivers/media/platform/rcar_fdp1.c #define FD1_RWPF_SWAP_LLWD BIT(3) BIT 194 drivers/media/platform/rcar_fdp1.c #define FD1_IPC_MODE_DLI BIT(8) BIT 2111 drivers/media/platform/rcar_fdp1.c FDP1_NEXTFIELD, BIT(0), FDP1_FIXED3D, BIT 71 drivers/media/platform/renesas-ceu.c #define CEU_CAMCR_JPEG BIT(4) BIT 84 drivers/media/platform/renesas-ceu.c #define CEU_CAMCR_DTIF_16BITS BIT(12) BIT 87 drivers/media/platform/renesas-ceu.c #define CEU_CDOCR_NO_DOWSAMPLE BIT(4) BIT 93 drivers/media/platform/renesas-ceu.c #define CEU_CAPSR_CPKIL BIT(16) BIT 94 drivers/media/platform/renesas-ceu.c #define CEU_CAPSR_CE BIT(0) BIT 97 drivers/media/platform/renesas-ceu.c #define CEU_CAPCR_CTNCP BIT(16) BIT 98 drivers/media/platform/renesas-ceu.c #define CEU_CSTRST_CPTON BIT(0) BIT 105 drivers/media/platform/renesas-ceu.c #define CEU_CETCR_IGRW BIT(4) BIT 107 drivers/media/platform/renesas-ceu.c #define CEU_CEIER_CPE BIT(0) BIT 109 drivers/media/platform/renesas-ceu.c #define CEU_CEIER_VBP BIT(20) BIT 24 drivers/media/platform/s3c-camif/camif-regs.h #define CISRCFMT_ITU601_8BIT BIT(31) BIT 35 drivers/media/platform/s3c-camif/camif-regs.h #define CIWDOFST_WINOFSEN BIT(31) BIT 36 drivers/media/platform/s3c-camif/camif-regs.h #define CIWDOFST_CLROVCOFIY BIT(30) BIT 37 drivers/media/platform/s3c-camif/camif-regs.h #define CIWDOFST_CLROVRLB_PR BIT(28) BIT 39 drivers/media/platform/s3c-camif/camif-regs.h #define CIWDOFST_CLROVCOFICB BIT(15) BIT 40 drivers/media/platform/s3c-camif/camif-regs.h #define CIWDOFST_CLROVCOFICR BIT(14) BIT 41 drivers/media/platform/s3c-camif/camif-regs.h #define CIWDOFST_CLROVPRFICB BIT(13) BIT 42 drivers/media/platform/s3c-camif/camif-regs.h #define CIWDOFST_CLROVPRFICR BIT(12) BIT 51 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_SWRST BIT(31) BIT 52 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_CAMRST BIT(30) BIT 58 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_INVPOLPCLK BIT(26) BIT 59 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_INVPOLVSYNC BIT(25) BIT 60 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_INVPOLHREF BIT(24) BIT 61 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_IRQ_OVFEN BIT(22) BIT 62 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_HREF_MASK BIT(21) BIT 63 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_IRQ_LEVEL BIT(20) BIT 65 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id)) BIT 66 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_FIELDMODE BIT(2) BIT 67 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_INVPOLFIELD BIT(1) BIT 68 drivers/media/platform/s3c-camif/camif-regs.h #define CIGCTRL_CAM_INTERLACE BIT(0) BIT 79 drivers/media/platform/s3c-camif/camif-regs.h #define CITRGFMT_IN422 BIT(31) /* only for s3c24xx */ BIT 80 drivers/media/platform/s3c-camif/camif-regs.h #define CITRGFMT_OUT422 BIT(30) /* only for s3c24xx */ BIT 93 drivers/media/platform/s3c-camif/camif-regs.h #define CITRGFMT_ROT90_PR BIT(13) BIT 107 drivers/media/platform/s3c-camif/camif-regs.h #define CICTRL_LASTIRQ_ENABLE BIT(2) BIT 118 drivers/media/platform/s3c-camif/camif-regs.h #define CISCCTRL_SCALERBYPASS BIT(31) BIT 120 drivers/media/platform/s3c-camif/camif-regs.h #define CIPRSCCTRL_SAMPLE BIT(31) BIT 122 drivers/media/platform/s3c-camif/camif-regs.h #define CIPRSCCTRL_RGB_FORMAT_24BIT BIT(30) /* only for s3c244x */ BIT 123 drivers/media/platform/s3c-camif/camif-regs.h #define CIPRSCCTRL_SCALEUP_H BIT(29) /* only for s3c244x */ BIT 124 drivers/media/platform/s3c-camif/camif-regs.h #define CIPRSCCTRL_SCALEUP_V BIT(28) /* only for s3c244x */ BIT 126 drivers/media/platform/s3c-camif/camif-regs.h #define CISCCTRL_SCALEUP_H BIT(30) BIT 127 drivers/media/platform/s3c-camif/camif-regs.h #define CISCCTRL_SCALEUP_V BIT(29) BIT 129 drivers/media/platform/s3c-camif/camif-regs.h #define CISCCTRL_CSCR2Y_WIDE BIT(28) BIT 130 drivers/media/platform/s3c-camif/camif-regs.h #define CISCCTRL_CSCY2R_WIDE BIT(27) BIT 131 drivers/media/platform/s3c-camif/camif-regs.h #define CISCCTRL_LCDPATHEN_FIFO BIT(26) BIT 132 drivers/media/platform/s3c-camif/camif-regs.h #define CISCCTRL_INTERLACE BIT(25) BIT 133 drivers/media/platform/s3c-camif/camif-regs.h #define CISCCTRL_SCALERSTART BIT(15) BIT 142 drivers/media/platform/s3c-camif/camif-regs.h #define CISCCTRL_EXTRGB_EXTENSION BIT(10) BIT 143 drivers/media/platform/s3c-camif/camif-regs.h #define CISCCTRL_ONE2ONE BIT(9) BIT 152 drivers/media/platform/s3c-camif/camif-regs.h #define CISTATUS_OVFIY_STATUS BIT(31) BIT 153 drivers/media/platform/s3c-camif/camif-regs.h #define CISTATUS_OVFICB_STATUS BIT(30) BIT 154 drivers/media/platform/s3c-camif/camif-regs.h #define CISTATUS_OVFICR_STATUS BIT(29) BIT 157 drivers/media/platform/s3c-camif/camif-regs.h #define CISTATUS_VSYNC_STATUS BIT(28) BIT 160 drivers/media/platform/s3c-camif/camif-regs.h #define CISTATUS_WINOFSTEN_STATUS BIT(25) BIT 161 drivers/media/platform/s3c-camif/camif-regs.h #define CISTATUS_IMGCPTEN_STATUS BIT(22) BIT 162 drivers/media/platform/s3c-camif/camif-regs.h #define CISTATUS_IMGCPTENSC_STATUS BIT(21) BIT 163 drivers/media/platform/s3c-camif/camif-regs.h #define CISTATUS_VSYNC_A_STATUS BIT(20) BIT 164 drivers/media/platform/s3c-camif/camif-regs.h #define CISTATUS_FRAMEEND_STATUS BIT(19) /* 17 on s3c64xx */ BIT 168 drivers/media/platform/s3c-camif/camif-regs.h #define CIIMGCPT_IMGCPTEN BIT(31) BIT 169 drivers/media/platform/s3c-camif/camif-regs.h #define CIIMGCPT_IMGCPTEN_SC(id) BIT(30 - (id)) BIT 171 drivers/media/platform/s3c-camif/camif-regs.h #define CIIMGCPT_CPT_FREN_ENABLE(id) BIT(25 - (id)) BIT 173 drivers/media/platform/s3c-camif/camif-regs.h #define CIIMGCPT_CPT_FRMOD_CNT BIT(18) BIT 180 drivers/media/platform/s3c-camif/camif-regs.h #define CIIMGEFF_IE_ENABLE(id) BIT(30 + (id)) BIT 183 drivers/media/platform/s3c-camif/camif-regs.h #define CIIMGEFF_IE_AFTER_SC BIT(29) BIT 212 drivers/media/platform/s3c-camif/camif-regs.h #define AUTOLOAD_ENABLE BIT(31) BIT 213 drivers/media/platform/s3c-camif/camif-regs.h #define ADDR_CH_DIS BIT(30) BIT 224 drivers/media/platform/s3c-camif/camif-regs.h #define MSCTRL_SEL_DMA_CAM BIT(3) BIT 229 drivers/media/platform/s3c-camif/camif-regs.h #define MSCTRL_ENVID_M BIT(0) BIT 770 drivers/media/platform/s5p-mfc/s5p_mfc_common.h #define MFC_V5_BIT BIT(0) BIT 771 drivers/media/platform/s5p-mfc/s5p_mfc_common.h #define MFC_V6_BIT BIT(1) BIT 772 drivers/media/platform/s5p-mfc/s5p_mfc_common.h #define MFC_V7_BIT BIT(2) BIT 773 drivers/media/platform/s5p-mfc/s5p_mfc_common.h #define MFC_V8_BIT BIT(3) BIT 774 drivers/media/platform/s5p-mfc/s5p_mfc_common.h #define MFC_V10_BIT BIT(5) BIT 30 drivers/media/platform/seco-cec/seco-cec.h #define BRA_DONE_STATUS BIT(7) BIT 31 drivers/media/platform/seco-cec/seco-cec.h #define BRA_INUSE_STS BIT(6) BIT 32 drivers/media/platform/seco-cec/seco-cec.h #define BRA_FAILED_OP BIT(4) BIT 33 drivers/media/platform/seco-cec/seco-cec.h #define BRA_BUS_ERR BIT(3) BIT 34 drivers/media/platform/seco-cec/seco-cec.h #define BRA_DEV_ERR BIT(2) BIT 35 drivers/media/platform/seco-cec/seco-cec.h #define BRA_INTR BIT(1) BIT 36 drivers/media/platform/seco-cec/seco-cec.h #define BRA_HOST_BUSY BIT(0) BIT 39 drivers/media/platform/seco-cec/seco-cec.h #define BRA_PEC_EN BIT(7) BIT 40 drivers/media/platform/seco-cec/seco-cec.h #define BRA_START BIT(6) BIT 41 drivers/media/platform/seco-cec/seco-cec.h #define BRA_LAST__BYTE BIT(5) BIT 42 drivers/media/platform/seco-cec/seco-cec.h #define BRA_INTREN BIT(0) BIT 133 drivers/media/platform/seco-cec/seco-cec.h #define SECOCEC_STATUS_MSG_RECEIVED_MASK BIT(0) BIT 134 drivers/media/platform/seco-cec/seco-cec.h #define SECOCEC_STATUS_RX_ERROR_MASK BIT(1) BIT 135 drivers/media/platform/seco-cec/seco-cec.h #define SECOCEC_STATUS_MSG_SENT_MASK BIT(2) BIT 136 drivers/media/platform/seco-cec/seco-cec.h #define SECOCEC_STATUS_TX_ERROR_MASK BIT(3) BIT 138 drivers/media/platform/seco-cec/seco-cec.h #define SECOCEC_STATUS_TX_NACK_ERROR BIT(4) BIT 139 drivers/media/platform/seco-cec/seco-cec.h #define SECOCEC_STATUS_RX_OVERFLOW_MASK BIT(5) BIT 159 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_CTL_RESET BIT(31) /* Global soft reset */ BIT 161 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_ITS_AQ1_LNA BIT(12) /* AQ1 LNA reached */ BIT 163 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_STA1_IDLE BIT(0) /* BDISP idle */ BIT 167 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_S1_MASK (BIT(0) | BIT(1) | BIT(2)) BIT 173 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_S2_MASK (BIT(3) | BIT(4)) BIT 177 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_S3_MASK BIT(5) BIT 180 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_IVMX BIT(6) /* Input versatile matrix */ BIT 181 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_CLUT BIT(7) /* Color Look Up Table */ BIT 182 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_SCALE BIT(8) /* Scaling */ BIT 183 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_FLICK BIT(9) /* Flicker filter */ BIT 184 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_CLIP BIT(10) /* Clipping */ BIT 185 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_CKEY BIT(11) /* Color key */ BIT 186 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_OVMX BIT(12) /* Output versatile matrix */ BIT 187 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_DEI BIT(13) /* Deinterlace */ BIT 188 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_PMASK BIT(14) /* Plane mask */ BIT 189 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_VC1R BIT(17) /* VC1 Range mapping */ BIT 190 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_ROTATE BIT(18) /* Rotation */ BIT 191 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_GRAD BIT(19) /* Gradient fill */ BIT 192 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_AQLOCK BIT(29) /* AQ lock */ BIT 193 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_PACE BIT(30) /* Pace down */ BIT 194 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_INS_IRQ BIT(31) /* Raise IRQ when node done */ BIT 200 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_TTY_ALPHA_R BIT(21) /* Alpha range */ BIT 201 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_TTY_CR_NOT_CB BIT(22) /* CR not Cb */ BIT 202 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_TTY_MB BIT(23) /* MB frame / field*/ BIT 203 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_TTY_HSO BIT(24) /* H scan order */ BIT 204 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_TTY_VSO BIT(25) /* V scan order */ BIT 205 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_TTY_DITHER BIT(26) /* Dithering */ BIT 206 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_TTY_CHROMA BIT(27) /* Write chroma / luma */ BIT 207 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_TTY_BIG_END BIT(30) /* Big endianness */ BIT 209 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_S1TY_A1_SUBSET BIT(22) /* A1 subset */ BIT 210 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_S1TY_CHROMA_EXT BIT(26) /* Chroma Extended */ BIT 211 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BTL_S1TY_SUBBYTE BIT(28) /* Sub-byte fmt, pixel order */ BIT 212 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_S1TY_RGB_EXP BIT(29) /* RGB expansion mode */ BIT 214 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_S2TY_A1_SUBSET BIT(22) /* A1 subset */ BIT 215 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_S2TY_CHROMA_EXT BIT(26) /* Chroma Extended */ BIT 216 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BTL_S2TY_SUBBYTE BIT(28) /* Sub-byte fmt, pixel order */ BIT 217 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_S2TY_RGB_EXP BIT(29) /* RGB expansion mode */ BIT 219 drivers/media/platform/sti/bdisp/bdisp-reg.h #define BLT_S3TY_BLANK_ACC BIT(26) /* Blank access */ BIT 25 drivers/media/platform/sti/bdisp/bdisp-v4l2.c #define BDISP_PARAMS BIT(0) /* Config updated */ BIT 26 drivers/media/platform/sti/bdisp/bdisp-v4l2.c #define BDISP_SRC_FMT BIT(1) /* Source set */ BIT 27 drivers/media/platform/sti/bdisp/bdisp-v4l2.c #define BDISP_DST_FMT BIT(2) /* Destination set */ BIT 28 drivers/media/platform/sti/bdisp/bdisp-v4l2.c #define BDISP_CTX_STOP_REQ BIT(3) /* Stop request */ BIT 29 drivers/media/platform/sti/bdisp/bdisp-v4l2.c #define BDISP_CTX_ABORT BIT(4) /* Abort while device run */ BIT 552 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c tmp |= BIT(tsin->tsin_id); BIT 119 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define TSDMAENABLE BIT(1) BIT 120 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define MEMDMAENABLE BIT(0) BIT 136 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_IGNORE_ERR_AT_SOP BIT(7) BIT 137 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_IGNORE_ERR_IN_PKT BIT(6) BIT 138 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_IGNORE_ERR_IN_BYTE BIT(5) BIT 139 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_INVERT_TSCLK BIT(4) BIT 140 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_ALIGN_BYTE_SOP BIT(3) BIT 141 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_ASYNC_NOT_SYNC BIT(2) BIT 142 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_BYTE_ENDIANNESS_MSB BIT(1) BIT 143 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_SERIAL_NOT_PARALLEL BIT(0) BIT 149 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_SLDENDIANNESS BIT(16) BIT 154 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_TAG_ENABLE BIT(0) BIT 159 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_PID_ENABLE BIT(31) BIT 183 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_MASK_FIFO_OVERFLOW BIT(0) BIT 184 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_MASK_BUFFER_OVERFLOW BIT(1) BIT 185 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_MASK_OUTOFORDERRP(x) BIT(2) BIT 186 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_MASK_PID_OVERFLOW(x) BIT(3) BIT 187 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_MASK_PKT_OVERFLOW(x) BIT(4) BIT 192 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_SYS_RESET BIT(1) BIT 193 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define C8SECTPFE_SYS_ENABLE BIT(0) BIT 272 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h #define IDLEREQ BIT(31) BIT 46 drivers/media/platform/sti/cec/stih-cec.c #define CEC_LINE_INACTIVE_EN BIT(0) BIT 47 drivers/media/platform/sti/cec/stih-cec.c #define CEC_AUTO_BUS_ERR_EN BIT(1) BIT 48 drivers/media/platform/sti/cec/stih-cec.c #define CEC_STOP_ON_ARB_ERR_EN BIT(2) BIT 49 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_REQ_WAIT_EN BIT(3) BIT 52 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_ARRAY_EN BIT(0) BIT 53 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_ARRAY_EN BIT(1) BIT 54 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_ARRAY_RESET BIT(2) BIT 55 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_ARRAY_RESET BIT(3) BIT 56 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_N_OF_BYTES_IRQ_EN BIT(4) BIT 57 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_STOP_ON_NACK BIT(7) BIT 61 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_START BIT(5) BIT 62 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_AUTO_SOM_EN BIT(6) BIT 63 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_AUTO_EOM_EN BIT(7) BIT 66 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_DONE_IRQ_EN BIT(0) BIT 67 drivers/media/platform/sti/cec/stih-cec.c #define CEC_ERROR_IRQ_EN BIT(2) BIT 68 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_DONE_IRQ_EN BIT(3) BIT 69 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_SOM_IRQ_EN BIT(4) BIT 70 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_EOM_IRQ_EN BIT(5) BIT 71 drivers/media/platform/sti/cec/stih-cec.c #define CEC_FREE_TIME_IRQ_EN BIT(6) BIT 72 drivers/media/platform/sti/cec/stih-cec.c #define CEC_PIN_STS_IRQ_EN BIT(7) BIT 75 drivers/media/platform/sti/cec/stih-cec.c #define CEC_IN_FILTER_EN BIT(0) BIT 76 drivers/media/platform/sti/cec/stih-cec.c #define CEC_PWR_SAVE_EN BIT(1) BIT 77 drivers/media/platform/sti/cec/stih-cec.c #define CEC_EN BIT(4) BIT 78 drivers/media/platform/sti/cec/stih-cec.c #define CEC_ACK_CTRL BIT(5) BIT 79 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_RESET_EN BIT(6) BIT 80 drivers/media/platform/sti/cec/stih-cec.c #define CEC_IGNORE_RX_ERROR BIT(7) BIT 83 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_DONE_STS BIT(0) BIT 84 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_ACK_GET_STS BIT(1) BIT 85 drivers/media/platform/sti/cec/stih-cec.c #define CEC_ERROR_STS BIT(2) BIT 86 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_DONE_STS BIT(3) BIT 87 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_SOM_STS BIT(4) BIT 88 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_EOM_STS BIT(5) BIT 89 drivers/media/platform/sti/cec/stih-cec.c #define CEC_FREE_TIME_IRQ_STS BIT(6) BIT 90 drivers/media/platform/sti/cec/stih-cec.c #define CEC_PIN_STS BIT(7) BIT 91 drivers/media/platform/sti/cec/stih-cec.c #define CEC_SBIT_TOUT_STS BIT(8) BIT 92 drivers/media/platform/sti/cec/stih-cec.c #define CEC_DBIT_TOUT_STS BIT(9) BIT 93 drivers/media/platform/sti/cec/stih-cec.c #define CEC_LPULSE_ERROR_STS BIT(10) BIT 94 drivers/media/platform/sti/cec/stih-cec.c #define CEC_HPULSE_ERROR_STS BIT(11) BIT 95 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_ERROR BIT(12) BIT 96 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_ARB_ERROR BIT(13) BIT 97 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_ERROR_MIN BIT(14) BIT 98 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_ERROR_MAX BIT(15) BIT 106 drivers/media/platform/sti/cec/stih-cec.c #define CEC_SBIT_TOUT_47MS BIT(1) BIT 107 drivers/media/platform/sti/cec/stih-cec.c #define CEC_SBIT_TOUT_48MS (BIT(0) | BIT(1)) BIT 108 drivers/media/platform/sti/cec/stih-cec.c #define CEC_SBIT_TOUT_50MS BIT(2) BIT 109 drivers/media/platform/sti/cec/stih-cec.c #define CEC_DBIT_TOUT_27MS BIT(0) BIT 110 drivers/media/platform/sti/cec/stih-cec.c #define CEC_DBIT_TOUT_28MS BIT(1) BIT 111 drivers/media/platform/sti/cec/stih-cec.c #define CEC_DBIT_TOUT_29MS (BIT(0) | BIT(1)) BIT 114 drivers/media/platform/sti/cec/stih-cec.c #define CEC_BIT_LPULSE_03MS BIT(1) BIT 115 drivers/media/platform/sti/cec/stih-cec.c #define CEC_BIT_HPULSE_03MS BIT(3) BIT 119 drivers/media/platform/sti/cec/stih-cec.c #define CEC_TX_N_OF_BYTES_SENT BIT(5) BIT 120 drivers/media/platform/sti/cec/stih-cec.c #define CEC_RX_OVERRUN BIT(6) BIT 152 drivers/media/platform/sti/cec/stih-cec.c writel(BIT(5) | BIT(7), cec->regs + CEC_TX_CTRL); BIT 58 drivers/media/platform/sti/hva/hva-hw.c #define CLK_GATING_HVC BIT(0) BIT 59 drivers/media/platform/sti/hva/hva-hw.c #define CLK_GATING_HEC BIT(1) BIT 60 drivers/media/platform/sti/hva/hva-hw.c #define CLK_GATING_HJE BIT(2) BIT 29 drivers/media/platform/stm32/stm32-cec.c #define TXEOM BIT(2) BIT 30 drivers/media/platform/stm32/stm32-cec.c #define TXSOM BIT(1) BIT 31 drivers/media/platform/stm32/stm32-cec.c #define CECEN BIT(0) BIT 33 drivers/media/platform/stm32/stm32-cec.c #define LSTN BIT(31) BIT 35 drivers/media/platform/stm32/stm32-cec.c #define SFTOP BIT(8) BIT 36 drivers/media/platform/stm32/stm32-cec.c #define BRDNOGEN BIT(7) BIT 37 drivers/media/platform/stm32/stm32-cec.c #define LBPEGEN BIT(6) BIT 38 drivers/media/platform/stm32/stm32-cec.c #define BREGEN BIT(5) BIT 39 drivers/media/platform/stm32/stm32-cec.c #define BRESTP BIT(4) BIT 40 drivers/media/platform/stm32/stm32-cec.c #define RXTOL BIT(3) BIT 45 drivers/media/platform/stm32/stm32-cec.c #define TXACKE BIT(12) BIT 46 drivers/media/platform/stm32/stm32-cec.c #define TXERR BIT(11) BIT 47 drivers/media/platform/stm32/stm32-cec.c #define TXUDR BIT(10) BIT 48 drivers/media/platform/stm32/stm32-cec.c #define TXEND BIT(9) BIT 49 drivers/media/platform/stm32/stm32-cec.c #define TXBR BIT(8) BIT 50 drivers/media/platform/stm32/stm32-cec.c #define ARBLST BIT(7) BIT 51 drivers/media/platform/stm32/stm32-cec.c #define RXACKE BIT(6) BIT 52 drivers/media/platform/stm32/stm32-cec.c #define RXOVR BIT(2) BIT 53 drivers/media/platform/stm32/stm32-cec.c #define RXEND BIT(1) BIT 54 drivers/media/platform/stm32/stm32-cec.c #define RXBR BIT(0) BIT 58 drivers/media/platform/stm32/stm32-dcmi.c #define CR_CAPTURE BIT(0) BIT 59 drivers/media/platform/stm32/stm32-dcmi.c #define CR_CM BIT(1) BIT 60 drivers/media/platform/stm32/stm32-dcmi.c #define CR_CROP BIT(2) BIT 61 drivers/media/platform/stm32/stm32-dcmi.c #define CR_JPEG BIT(3) BIT 62 drivers/media/platform/stm32/stm32-dcmi.c #define CR_ESS BIT(4) BIT 63 drivers/media/platform/stm32/stm32-dcmi.c #define CR_PCKPOL BIT(5) BIT 64 drivers/media/platform/stm32/stm32-dcmi.c #define CR_HSPOL BIT(6) BIT 65 drivers/media/platform/stm32/stm32-dcmi.c #define CR_VSPOL BIT(7) BIT 66 drivers/media/platform/stm32/stm32-dcmi.c #define CR_FCRC_0 BIT(8) BIT 67 drivers/media/platform/stm32/stm32-dcmi.c #define CR_FCRC_1 BIT(9) BIT 68 drivers/media/platform/stm32/stm32-dcmi.c #define CR_EDM_0 BIT(10) BIT 69 drivers/media/platform/stm32/stm32-dcmi.c #define CR_EDM_1 BIT(11) BIT 70 drivers/media/platform/stm32/stm32-dcmi.c #define CR_ENABLE BIT(14) BIT 73 drivers/media/platform/stm32/stm32-dcmi.c #define SR_HSYNC BIT(0) BIT 74 drivers/media/platform/stm32/stm32-dcmi.c #define SR_VSYNC BIT(1) BIT 75 drivers/media/platform/stm32/stm32-dcmi.c #define SR_FNE BIT(2) BIT 81 drivers/media/platform/stm32/stm32-dcmi.c #define IT_FRAME BIT(0) BIT 82 drivers/media/platform/stm32/stm32-dcmi.c #define IT_OVR BIT(1) BIT 83 drivers/media/platform/stm32/stm32-dcmi.c #define IT_ERR BIT(2) BIT 84 drivers/media/platform/stm32/stm32-dcmi.c #define IT_VSYNC BIT(3) BIT 85 drivers/media/platform/stm32/stm32-dcmi.c #define IT_LINE BIT(4) BIT 30 drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h #define CSI_CPT_CTRL_VIDEO_START BIT(1) BIT 31 drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h #define CSI_CPT_CTRL_IMAGE_START BIT(0) BIT 36 drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h #define CSI_BUF_CTRL_DBN BIT(2) BIT 37 drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h #define CSI_BUF_CTRL_DBS BIT(1) BIT 38 drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h #define CSI_BUF_CTRL_DBE BIT(0) BIT 41 drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h #define CSI_INT_FRM_DONE BIT(1) BIT 42 drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h #define CSI_INT_CPT_DONE BIT(0) BIT 14 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_EN_VER_EN BIT(30) BIT 15 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_EN_CSI_EN BIT(0) BIT 18 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_IF_CFG_SRC_TYPE_MASK BIT(21) BIT 21 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_IF_CFG_FPS_DS_EN BIT(20) BIT 22 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_IF_CFG_FIELD_MASK BIT(19) BIT 25 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_IF_CFG_VREF_POL_MASK BIT(18) BIT 28 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_IF_CFG_HREF_POL_MASK BIT(17) BIT 31 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_IF_CFG_CLK_POL_MASK BIT(16) BIT 38 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_IF_CFG_MIPI_IF_MASK BIT(7) BIT 40 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_IF_CFG_MIPI_IF_MIPI BIT(7) BIT 50 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CAP_CH0_VCAP_ON BIT(1) BIT 51 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CAP_CH0_SCAP_ON BIT(0) BIT 65 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_CFG_VFLIP_EN BIT(13) BIT 66 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_CFG_HFLIP_EN BIT(12) BIT 75 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_SCALE_QUART_EN BIT(0) BIT 84 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_STA_FIELD_STA_MASK BIT(2) BIT 87 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_STA_VCAP_STA BIT(1) BIT 88 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_STA_SCAP_STA BIT(0) BIT 91 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_EN_VS_INT_EN BIT(7) BIT 92 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_EN_HB_OF_INT_EN BIT(6) BIT 93 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_EN_MUL_ERR_INT_EN BIT(5) BIT 94 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_EN_FIFO2_OF_INT_EN BIT(4) BIT 95 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_EN_FIFO1_OF_INT_EN BIT(3) BIT 96 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_EN_FIFO0_OF_INT_EN BIT(2) BIT 97 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_EN_FD_INT_EN BIT(1) BIT 98 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_EN_CD_INT_EN BIT(0) BIT 101 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_STA_VS_PD BIT(7) BIT 102 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_STA_HB_OF_PD BIT(6) BIT 103 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_STA_MUL_ERR_PD BIT(5) BIT 104 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_STA_FIFO2_OF_PD BIT(4) BIT 105 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_STA_FIFO1_OF_PD BIT(3) BIT 106 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_STA_FIFO0_OF_PD BIT(2) BIT 107 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_STA_FD_PD BIT(1) BIT 108 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_INT_STA_CD_PD BIT(0) BIT 37 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_HWCTRL_RX_SNOOP BIT(15) BIT 38 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_HWCTRL_RX_NAK_MODE BIT(16) BIT 39 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_HWCTRL_TX_NAK_MODE BIT(24) BIT 40 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE BIT(30) BIT 41 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_HWCTRL_TX_RX_MODE BIT(31) BIT 43 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INPUT_FILTER_MODE BIT(31) BIT 47 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_TX_REG_EOM BIT(8) BIT 48 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_TX_REG_BCAST BIT(12) BIT 49 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_TX_REG_START_BIT BIT(16) BIT 50 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_TX_REG_RETRY BIT(17) BIT 53 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_RX_REGISTER_EOM BIT(8) BIT 54 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_RX_REGISTER_ACK BIT(9) BIT 82 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY BIT(0) BIT 83 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN BIT(1) BIT 84 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD BIT(2) BIT 85 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED BIT(3) BIT 86 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED BIT(4) BIT 87 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED BIT(5) BIT 88 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL BIT(8) BIT 89 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN BIT(9) BIT 90 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED BIT(10) BIT 91 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED BIT(11) BIT 92 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED BIT(12) BIT 93 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L BIT(13) BIT 94 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H BIT(14) BIT 96 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY BIT(0) BIT 97 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN BIT(1) BIT 98 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD BIT(2) BIT 99 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED BIT(3) BIT 100 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED BIT(4) BIT 101 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED BIT(5) BIT 102 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL BIT(8) BIT 103 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN BIT(9) BIT 104 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED BIT(10) BIT 105 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED BIT(11) BIT 106 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED BIT(12) BIT 107 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L BIT(13) BIT 108 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H BIT(14) BIT 113 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT BIT(25) BIT 114 drivers/media/platform/tegra-cec/tegra_cec.h #define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER BIT(26) BIT 516 drivers/media/platform/ti-vpe/vpdma.c return read_reg(vpdma, VPDMA_LIST_STAT_SYNC) & BIT(list_num + 16); BIT 327 drivers/media/platform/ti-vpe/vpe.c #define Q_DATA_FRAME_1D BIT(0) BIT 328 drivers/media/platform/ti-vpe/vpe.c #define Q_DATA_MODE_TILED BIT(1) BIT 329 drivers/media/platform/ti-vpe/vpe.c #define Q_DATA_INTERLACED_ALTERNATE BIT(2) BIT 330 drivers/media/platform/ti-vpe/vpe.c #define Q_DATA_INTERLACED_SEQ_TB BIT(3) BIT 51 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST0_COMPLETE BIT(0) BIT 52 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST0_NOTIFY BIT(1) BIT 53 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST1_COMPLETE BIT(2) BIT 54 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST1_NOTIFY BIT(3) BIT 55 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST2_COMPLETE BIT(4) BIT 56 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST2_NOTIFY BIT(5) BIT 57 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST3_COMPLETE BIT(6) BIT 58 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST3_NOTIFY BIT(7) BIT 59 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST4_COMPLETE BIT(8) BIT 60 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST4_NOTIFY BIT(9) BIT 61 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST5_COMPLETE BIT(10) BIT 62 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST5_NOTIFY BIT(11) BIT 63 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST6_COMPLETE BIT(12) BIT 64 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST6_NOTIFY BIT(13) BIT 65 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST7_COMPLETE BIT(14) BIT 66 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_LIST7_NOTIFY BIT(15) BIT 67 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_DESCRIPTOR BIT(16) BIT 68 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_DEI_FMD_INT BIT(18) BIT 77 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_CHANNEL_GROUP0 BIT(0) BIT 78 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_CHANNEL_GROUP1 BIT(1) BIT 79 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_CHANNEL_GROUP2 BIT(2) BIT 80 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_CHANNEL_GROUP3 BIT(3) BIT 81 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_CHANNEL_GROUP4 BIT(4) BIT 82 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_CHANNEL_GROUP5 BIT(5) BIT 83 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_INT0_CLIENT BIT(7) BIT 84 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_DEI_ERROR_INT BIT(16) BIT 85 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_DS1_UV_ERROR_INT BIT(22) BIT 90 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_VPEDMA_CLK_ENABLE BIT(0) BIT 91 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_DATA_PATH_CLK_ENABLE BIT(1) BIT 104 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_RGB_OUT_SELECT BIT(8) BIT 107 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_DS_BYPASS BIT(16) BIT 108 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_COLOR_SEPARATE_422 BIT(18) BIT 118 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_RANGE_MAP_ON BIT(6) BIT 119 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_RANGE_REDUCTION_ON BIT(28) BIT 198 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_DEI_INTERLACE_BYPASS BIT(29) BIT 199 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_DEI_FIELD_FLUSH BIT(30) BIT 200 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_DEI_PROGRESSIVE BIT(31) BIT 203 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_MDT_TEMPMAX_BYPASS BIT(0) BIT 204 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_MDT_SPATMAX_BYPASS BIT(1) BIT 217 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_EDI_ENABLE_3D BIT(2) BIT 218 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_EDI_ENABLE_CHROMA_3D BIT(3) BIT 271 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_FMD_WINDOW_ENABLE BIT(31) BIT 280 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_FMD_ENABLE BIT(0) BIT 281 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_FMD_LOCK BIT(1) BIT 282 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_FMD_JAM_DIR BIT(2) BIT 283 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_FMD_BED_ENABLE BIT(3) BIT 296 drivers/media/platform/ti-vpe/vpe_regs.h #define VPE_FMD_RESET BIT(24) BIT 16 drivers/media/platform/vicodec/codec-fwht.c #define OVERFLOW_BIT BIT(14) BIT 23 drivers/media/platform/vicodec/codec-fwht.c #define PFRAME_BIT BIT(15) BIT 62 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_IS_INTERLACED BIT(0) BIT 64 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_IS_BOTTOM_FIRST BIT(1) BIT 66 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_IS_ALTERNATE BIT(2) BIT 71 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_IS_BOTTOM_FIELD BIT(3) BIT 73 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_LUMA_IS_UNCOMPRESSED BIT(4) BIT 74 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_CB_IS_UNCOMPRESSED BIT(5) BIT 75 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_CR_IS_UNCOMPRESSED BIT(6) BIT 76 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_CHROMA_FULL_HEIGHT BIT(7) BIT 77 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_CHROMA_FULL_WIDTH BIT(8) BIT 78 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_ALPHA_IS_UNCOMPRESSED BIT(9) BIT 79 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_I_FRAME BIT(10) BIT 131 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FRAME_PCODED BIT(0) BIT 132 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FRAME_UNENCODED BIT(1) BIT 133 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_LUMA_UNENCODED BIT(2) BIT 134 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_CB_UNENCODED BIT(3) BIT 135 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_CR_UNENCODED BIT(4) BIT 136 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_ALPHA_UNENCODED BIT(5) BIT 64 drivers/media/platform/vim2m.c #define MEM2MEM_CAPTURE BIT(0) BIT 65 drivers/media/platform/vim2m.c #define MEM2MEM_OUTPUT BIT(1) BIT 75 drivers/media/platform/vim2m.c #define MEM2MEM_HFLIP BIT(0) BIT 76 drivers/media/platform/vim2m.c #define MEM2MEM_VFLIP BIT(1) BIT 21 drivers/media/platform/vsp1/vsp1_dl.h #define VSP1_DL_FRAME_END_COMPLETED BIT(0) BIT 22 drivers/media/platform/vsp1/vsp1_dl.h #define VSP1_DL_FRAME_END_WRITEBACK BIT(1) BIT 23 drivers/media/platform/vsp1/vsp1_dl.h #define VSP1_DL_FRAME_END_INTERNAL BIT(2) BIT 18 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_CMD_UPDHDR BIT(4) BIT 19 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_CMD_STRCMD BIT(0) BIT 28 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_SRESET_SRTS(n) BIT(n) BIT 31 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_STATUS_FLD_STD(n) BIT((n) + 28) BIT 32 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8) BIT 35 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WFP_IRQ_ENB_DFEE BIT(1) BIT 36 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WFP_IRQ_ENB_FREE BIT(0) BIT 39 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WFP_IRQ_STA_DFE BIT(1) BIT 40 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WFP_IRQ_STA_FRE BIT(0) BIT 43 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DISP_IRQ_ENB_DSTE BIT(8) BIT 44 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DISP_IRQ_ENB_MAEE BIT(5) BIT 45 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DISP_IRQ_ENB_LNEE(n) BIT(n) BIT 48 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DISP_IRQ_STA_DST BIT(8) BIT 49 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DISP_IRQ_STA_MAE BIT(5) BIT 50 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DISP_IRQ_STA_LNE(n) BIT(n) BIT 62 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_CTRL_DC2 BIT(12) BIT 63 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_CTRL_DC1 BIT(8) BIT 64 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_CTRL_DC0 BIT(4) BIT 65 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_CTRL_CFM0 BIT(2) BIT 66 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_CTRL_NH0 BIT(1) BIT 67 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_CTRL_DLE BIT(0) BIT 72 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_SWAP_LWS BIT(2) BIT 73 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_SWAP_WDS BIT(1) BIT 74 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_SWAP_BTS BIT(0) BIT 77 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_EXT_CTRL_NWE BIT(16) BIT 80 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_EXT_CTRL_DLPRI BIT(5) BIT 81 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_EXT_CTRL_EXPRI BIT(4) BIT 82 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_EXT_CTRL_EXT BIT(0) BIT 84 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_EXT_AUTOFLD_INT BIT(0) BIT 87 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DL_BODY_SIZE_UPD BIT(24) BIT 110 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_INFMT_VIR BIT(28) BIT 111 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_INFMT_CIPM BIT(16) BIT 112 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_INFMT_SPYCS BIT(15) BIT 113 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_INFMT_SPUVS BIT(14) BIT 123 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_INFMT_CSC BIT(8) BIT 128 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_DSWAP_A_LLS BIT(11) BIT 129 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_DSWAP_A_LWS BIT(10) BIT 130 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_DSWAP_A_WDS BIT(9) BIT 131 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_DSWAP_A_BTS BIT(8) BIT 132 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_DSWAP_P_LLS BIT(3) BIT 133 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_DSWAP_P_LWS BIT(2) BIT 134 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_DSWAP_P_WDS BIT(1) BIT 135 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_DSWAP_P_BTS BIT(0) BIT 153 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_ALPH_SEL_BSEL BIT(23) BIT 174 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_MSK_CTRL_MSK_EN BIT(24) BIT 194 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_CKEY_CTRL_CV BIT(4) BIT 195 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_CKEY_CTRL_SAPE1 BIT(1) BIT 196 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_RPF_CKEY_CTRL_SAPE0 BIT(0) BIT 253 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_SZCLIP_EN BIT(28) BIT 262 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_OUTFMT_PXA BIT(23) BIT 263 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_OUTFMT_ROT BIT(18) BIT 264 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_OUTFMT_HFLP BIT(17) BIT 265 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_OUTFMT_FLP BIT(16) BIT 266 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_OUTFMT_SPYCS BIT(15) BIT 267 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_OUTFMT_SPUVS BIT(14) BIT 276 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_OUTFMT_CSC BIT(8) BIT 281 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_DSWAP_P_LLS BIT(3) BIT 282 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_DSWAP_P_LWS BIT(2) BIT 283 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_DSWAP_P_WDS BIT(1) BIT 284 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_DSWAP_P_BTS BIT(0) BIT 287 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_RNDCTRL_CBRM BIT(28) BIT 300 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_ROT_CTRL_LN16 BIT(17) BIT 311 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_WPF_WRBCK_CTRL_WBMD BIT(0) BIT 320 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UIF_DISCOM_DOCMCR_CMPRU BIT(16) BIT 321 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UIF_DISCOM_DOCMCR_CMPR BIT(0) BIT 324 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UIF_DISCOM_DOCMSTR_CMPPRE BIT(1) BIT 325 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UIF_DISCOM_DOCMSTR_CMPST BIT(0) BIT 328 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE BIT(1) BIT 329 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST BIT(0) BIT 332 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN BIT(1) BIT 333 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UIF_DISCOM_DOCMIENR_CMPIEN BIT(0) BIT 341 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UIF_DISCOM_DOCMPMR_CMPDAUF BIT(7) BIT 368 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_DPR_ROUTE_BRSSEL BIT(28) BIT 410 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_SRU_CTRL0_PARAM2 BIT(3) BIT 411 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_SRU_CTRL0_PARAM3 BIT(2) BIT 412 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_SRU_CTRL0_PARAM4 BIT(1) BIT 413 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_SRU_CTRL0_EN BIT(0) BIT 430 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_AMD BIT(30) BIT 431 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_FMD BIT(29) BIT 432 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_BLADV BIT(28) BIT 433 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_AON BIT(25) BIT 434 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_ATHON BIT(24) BIT 435 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_BC BIT(20) BIT 436 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_NE_A BIT(19) BIT 437 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_NE_RCR BIT(18) BIT 438 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_NE_GY BIT(17) BIT 439 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_NE_BCB BIT(16) BIT 440 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_AMDSLH BIT(2) BIT 441 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_CTRL_TDIPC BIT(1) BIT 480 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_IPC_FIELD BIT(27) BIT 485 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_UDS_HSZCLIP_HCEN BIT(28) BIT 510 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_LUT_CTRL_EN BIT(0) BIT 517 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_CLU_CTRL_AAI BIT(28) BIT 518 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_CLU_CTRL_MVS BIT(24) BIT 524 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_CLU_CTRL_M2D BIT(1) BIT 525 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_CLU_CTRL_EN BIT(0) BIT 532 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_HST_CTRL_EN BIT(0) BIT 539 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_HSI_CTRL_EN BIT(0) BIT 566 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_BRU_INCTRL_NRM BIT(28) BIT 600 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_BRU_CTRL_RBC BIT(31) BIT 613 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_BRU_BLD_CBES BIT(31) BIT 627 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_BRU_BLD_ABES BIT(23) BIT 665 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_HGO_MODE_STEP BIT(10) BIT 666 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_HGO_MODE_MAXRGB BIT(7) BIT 667 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_HGO_MODE_OFSB_R BIT(6) BIT 668 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_HGO_MODE_OFSB_G BIT(5) BIT 669 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_HGO_MODE_OFSB_B BIT(4) BIT 690 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_HGO_REGRST_RCLEA BIT(0) BIT 716 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_HGT_REGRST_RCLEA BIT(0) BIT 727 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_LIF_CTRL_CFMT BIT(4) BIT 728 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_LIF_CTRL_REQSEL BIT(1) BIT 729 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_LIF_CTRL_LIF_EN BIT(0) BIT 738 drivers/media/platform/vsp1/vsp1_regs.h #define VI6_LIF_LBA_LBA0 BIT(31) BIT 223 drivers/media/platform/vsp1/vsp1_rpf.c cmd->flags |= VI6_DL_EXT_AUTOFLD_INT | BIT(16 + rpf->entity.index); BIT 115 drivers/media/platform/vsp1/vsp1_wpf.c flip |= BIT(WPF_CTRL_VFLIP); BIT 118 drivers/media/platform/vsp1/vsp1_wpf.c flip |= BIT(WPF_CTRL_HFLIP); BIT 121 drivers/media/platform/vsp1/vsp1_wpf.c flip ^= BIT(WPF_CTRL_VFLIP) | BIT(WPF_CTRL_HFLIP); BIT 370 drivers/media/platform/vsp1/vsp1_wpf.c const unsigned int mask = BIT(WPF_CTRL_VFLIP) BIT 371 drivers/media/platform/vsp1/vsp1_wpf.c | BIT(WPF_CTRL_HFLIP); BIT 383 drivers/media/platform/vsp1/vsp1_wpf.c if (wpf->flip.active & BIT(WPF_CTRL_VFLIP)) BIT 385 drivers/media/platform/vsp1/vsp1_wpf.c if (wpf->flip.active & BIT(WPF_CTRL_HFLIP)) BIT 457 drivers/media/platform/vsp1/vsp1_wpf.c if (flip & BIT(WPF_CTRL_HFLIP) && !wpf->flip.rotate) BIT 459 drivers/media/platform/vsp1/vsp1_wpf.c else if (flip & BIT(WPF_CTRL_VFLIP) && wpf->flip.rotate) BIT 476 drivers/media/platform/vsp1/vsp1_wpf.c if (flip & BIT(WPF_CTRL_VFLIP)) { BIT 499 drivers/media/platform/vsp1/vsp1_wpf.c if (wpf->flip.rotate && !(flip & BIT(WPF_CTRL_HFLIP))) { BIT 39 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_CONTROL_SW_ENABLE BIT(0) BIT 40 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_CONTROL_REG_UPDATE BIT(1) BIT 41 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_CONTROL_BYPASS BIT(4) BIT 42 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_CONTROL_TEST_PATTERN BIT(5) BIT 43 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET BIT(30) BIT 44 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_CONTROL_SW_RESET BIT(31) BIT 46 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_STATUS_PROC_STARTED BIT(0) BIT 47 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_STATUS_EOF BIT(1) BIT 49 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY BIT(0) BIT 50 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_ERROR_SLAVE_EOL_LATE BIT(1) BIT 51 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY BIT(2) BIT 52 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_ERROR_SLAVE_SOF_LATE BIT(3) BIT 54 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED BIT(0) BIT 55 drivers/media/platform/xilinx/xilinx-vip.h #define XVIP_CTRL_IRQ_EOF BIT(1) BIT 23 drivers/media/radio/radio-wl1273.c #define WL1273_POWER_SET_FM BIT(0) BIT 24 drivers/media/radio/radio-wl1273.c #define WL1273_POWER_SET_RDS BIT(1) BIT 25 drivers/media/radio/radio-wl1273.c #define WL1273_POWER_SET_RETENTION BIT(4) BIT 162 drivers/media/radio/wl128x/fmdrv_common.h #define FM_FR_EVENT BIT(0) BIT 163 drivers/media/radio/wl128x/fmdrv_common.h #define FM_BL_EVENT BIT(1) BIT 164 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_EVENT BIT(2) BIT 165 drivers/media/radio/wl128x/fmdrv_common.h #define FM_BBLK_EVENT BIT(3) BIT 166 drivers/media/radio/wl128x/fmdrv_common.h #define FM_LSYNC_EVENT BIT(4) BIT 167 drivers/media/radio/wl128x/fmdrv_common.h #define FM_LEV_EVENT BIT(5) BIT 168 drivers/media/radio/wl128x/fmdrv_common.h #define FM_IFFR_EVENT BIT(6) BIT 169 drivers/media/radio/wl128x/fmdrv_common.h #define FM_PI_EVENT BIT(7) BIT 170 drivers/media/radio/wl128x/fmdrv_common.h #define FM_PD_EVENT BIT(8) BIT 171 drivers/media/radio/wl128x/fmdrv_common.h #define FM_STIC_EVENT BIT(9) BIT 172 drivers/media/radio/wl128x/fmdrv_common.h #define FM_MAL_EVENT BIT(10) BIT 173 drivers/media/radio/wl128x/fmdrv_common.h #define FM_POW_ENB_EVENT BIT(11) BIT 271 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_0A BIT(0) BIT 272 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_0B BIT(1) BIT 273 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_1A BIT(2) BIT 274 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_1B BIT(3) BIT 275 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_2A BIT(4) BIT 276 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_2B BIT(5) BIT 277 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_3A BIT(6) BIT 278 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_3B BIT(7) BIT 279 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_4A BIT(8) BIT 280 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_4B BIT(9) BIT 281 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_5A BIT(10) BIT 282 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_5B BIT(11) BIT 283 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_6A BIT(12) BIT 284 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_6B BIT(13) BIT 285 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_7A BIT(14) BIT 286 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_7B BIT(15) BIT 287 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_8A BIT(16) BIT 288 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_8B BIT(17) BIT 289 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_9A BIT(18) BIT 290 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_9B BIT(19) BIT 291 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_10A BIT(20) BIT 292 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_10B BIT(21) BIT 293 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_11A BIT(22) BIT 294 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_11B BIT(23) BIT 295 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_12A BIT(24) BIT 296 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_12B BIT(25) BIT 297 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_13A BIT(26) BIT 298 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_13B BIT(27) BIT 299 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_14A BIT(28) BIT 300 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_14B BIT(29) BIT 301 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_15A BIT(30) BIT 302 drivers/media/radio/wl128x/fmdrv_common.h #define FM_RDS_GROUP_TYPE_MASK_15B BIT(31) BIT 50 drivers/media/rc/img-ir/img-ir-hw.c #define IMG_IR_F_FILTER BIT(RC_FILTER_NORMAL) /* enable filtering */ BIT 51 drivers/media/rc/img-ir/img-ir-hw.c #define IMG_IR_F_WAKE BIT(RC_FILTER_WAKEUP) /* enable waking */ BIT 380 drivers/media/rc/img-ir/img-ir-hw.c if (hw->flags & BIT(type)) BIT 32 drivers/media/rc/ir-hix5hd2.c #define INTMS_SYMBRCV (BIT(24) | BIT(8)) BIT 33 drivers/media/rc/ir-hix5hd2.c #define INTMS_TIMEOUT (BIT(25) | BIT(9)) BIT 34 drivers/media/rc/ir-hix5hd2.c #define INTMS_OVERFLOW (BIT(26) | BIT(10)) BIT 35 drivers/media/rc/ir-hix5hd2.c #define INT_CLR_OVERFLOW BIT(18) BIT 36 drivers/media/rc/ir-hix5hd2.c #define INT_CLR_TIMEOUT BIT(17) BIT 37 drivers/media/rc/ir-hix5hd2.c #define INT_CLR_RCV BIT(16) BIT 38 drivers/media/rc/ir-hix5hd2.c #define INT_CLR_RCVTIMEOUT (BIT(16) | BIT(17)) BIT 41 drivers/media/rc/ir-hix5hd2.c #define IR_CLK_ENABLE BIT(4) BIT 42 drivers/media/rc/ir-hix5hd2.c #define IR_CLK_RESET BIT(5) BIT 51 drivers/media/rc/ir-hix5hd2.c #define IR_CFG_MODE_RAW BIT(7) BIT 13 drivers/media/rc/ir-imon-decoder.c #define IMON_CHKBITS (BIT(30) | BIT(25) | BIT(24) | BIT(22) | \ BIT 14 drivers/media/rc/ir-imon-decoder.c BIT(21) | BIT(20) | BIT(19) | BIT(18) | \ BIT 15 drivers/media/rc/ir-imon-decoder.c BIT(17) | BIT(16) | BIT(14) | BIT(13) | \ BIT 16 drivers/media/rc/ir-imon-decoder.c BIT(12) | BIT(11) | BIT(10) | BIT(9)) BIT 139 drivers/media/rc/ir-imon-decoder.c if (IMON_CHKBITS & BIT(data->count)) BIT 150 drivers/media/rc/ir-imon-decoder.c if (IMON_CHKBITS & BIT(data->count)) { BIT 203 drivers/media/rc/ir-imon-decoder.c if (BIT(i) & IMON_CHKBITS) BIT 204 drivers/media/rc/ir-imon-decoder.c pulse = !(scancode & (BIT(i) | BIT(i + 1))); BIT 216 drivers/media/rc/ir-imon-decoder.c pulse = !(scancode & BIT(i)); BIT 55 drivers/media/rc/meson-ir.c #define REG1_RESET BIT(0) BIT 56 drivers/media/rc/meson-ir.c #define REG1_ENABLE BIT(15) BIT 58 drivers/media/rc/meson-ir.c #define STATUS_IR_DEC_IN BIT(8) BIT 21 drivers/media/rc/mtk-cir.c #define MTK_PWM_EN BIT(13) BIT 30 drivers/media/rc/mtk-cir.c #define MTK_IR_EN BIT(0) BIT 33 drivers/media/rc/mtk-cir.c #define MTK_IRCLR BIT(0) BIT 44 drivers/media/rc/mtk-cir.c #define MTK_IRINT_EN BIT(0) BIT 47 drivers/media/rc/mtk-cir.c #define MTK_IRINT_CLR BIT(0) BIT 26 drivers/media/rc/sunxi-cir.c #define REG_CTL_GEN BIT(0) BIT 28 drivers/media/rc/sunxi-cir.c #define REG_CTL_RXEN BIT(1) BIT 30 drivers/media/rc/sunxi-cir.c #define REG_CTL_MD (BIT(4) | BIT(5)) BIT 35 drivers/media/rc/sunxi-cir.c #define REG_RXCTL_RPPI BIT(2) BIT 43 drivers/media/rc/sunxi-cir.c #define REG_RXINT_ROI_EN BIT(0) BIT 45 drivers/media/rc/sunxi-cir.c #define REG_RXINT_RPEI_EN BIT(1) BIT 47 drivers/media/rc/sunxi-cir.c #define REG_RXINT_RAI_EN BIT(4) BIT 40 drivers/media/rc/tango-ir.c #define DISABLE_NEC (BIT(4) | BIT(8)) BIT 41 drivers/media/rc/tango-ir.c #define ENABLE_RC5 (BIT(0) | BIT(9)) BIT 42 drivers/media/rc/tango-ir.c #define ENABLE_RC6 (BIT(0) | BIT(7)) BIT 43 drivers/media/rc/tango-ir.c #define ACK_IR_INT (BIT(0) | BIT(1)) BIT 44 drivers/media/rc/tango-ir.c #define ACK_RC6_INT (BIT(31)) BIT 75 drivers/media/rc/tango-ir.c if (data & BIT(31)) BIT 118 drivers/media/rc/tango-ir.c if (!(rc5_stat & 3) && !(rc6_stat & BIT(31))) BIT 121 drivers/media/rc/tango-ir.c if (rc5_stat & BIT(0)) BIT 124 drivers/media/rc/tango-ir.c if (rc5_stat & BIT(1)) BIT 127 drivers/media/rc/tango-ir.c if (rc6_stat & BIT(31)) BIT 20 drivers/media/rc/zx-irdec.c #define ZX_IREN BIT(0) BIT 30 drivers/media/rc/zx-irdec.c #define ZX_NECRPT BIT(16) BIT 317 drivers/media/usb/dvb-usb-v2/lmedm04.c signal_lock = ibuf[2] & BIT(5); BIT 326 drivers/media/usb/dvb-usb-v2/lmedm04.c signal_lock = ibuf[2] & BIT(4); BIT 344 drivers/media/usb/dvb-usb-v2/lmedm04.c signal_lock |= ibuf[2] & BIT(0); BIT 54 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_BT656_FIELD_MASK BIT(6) BIT 56 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_BT656_FIELD_2 BIT(6) BIT 58 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_BT656_VBI_MASK BIT(5) BIT 59 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_BT656_VBI_ON BIT(5) BIT 62 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_BT656_SEAV_MASK BIT(4) BIT 63 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_BT656_SEAV_EAV BIT(4) BIT 160 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_DBG_RC BIT(0) BIT 161 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_DBG_I2C BIT(1) BIT 162 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_DBG_MISC BIT(2) BIT 163 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_DBG_BT656 BIT(3) BIT 164 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_DBG_URB BIT(4) BIT 165 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_DBG_OPS BIT(5) BIT 166 drivers/media/usb/dvb-usb/cxusb.h #define CXUSB_DBG_AUXB BIT(6) BIT 7 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPIO_0 ((unsigned char)BIT(0)) BIT 8 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPIO_1 ((unsigned char)BIT(1)) BIT 9 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPIO_2 ((unsigned char)BIT(2)) BIT 10 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPIO_3 ((unsigned char)BIT(3)) BIT 11 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPIO_4 ((unsigned char)BIT(4)) BIT 12 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPIO_5 ((unsigned char)BIT(5)) BIT 13 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPIO_6 ((unsigned char)BIT(6)) BIT 14 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPIO_7 ((unsigned char)BIT(7)) BIT 16 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPO_0 ((unsigned char)BIT(0)) BIT 17 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPO_1 ((unsigned char)BIT(1)) BIT 18 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPO_2 ((unsigned char)BIT(2)) BIT 19 drivers/media/usb/em28xx/em28xx-reg.h #define EM_GPO_3 ((unsigned char)BIT(3)) BIT 258 drivers/media/usb/em28xx/em28xx-reg.h #define EM2874_TS1_CAPTURE_ENABLE ((unsigned char)BIT(0)) BIT 259 drivers/media/usb/em28xx/em28xx-reg.h #define EM2874_TS1_FILTER_ENABLE ((unsigned char)BIT(1)) BIT 260 drivers/media/usb/em28xx/em28xx-reg.h #define EM2874_TS1_NULL_DISCARD ((unsigned char)BIT(2)) BIT 261 drivers/media/usb/em28xx/em28xx-reg.h #define EM2874_TS2_CAPTURE_ENABLE ((unsigned char)BIT(4)) BIT 262 drivers/media/usb/em28xx/em28xx-reg.h #define EM2874_TS2_FILTER_ENABLE ((unsigned char)BIT(5)) BIT 263 drivers/media/usb/em28xx/em28xx-reg.h #define EM2874_TS2_NULL_DISCARD ((unsigned char)BIT(6)) BIT 388 drivers/media/usb/em28xx/em28xx.h EM28XX_AOUT_MASTER = BIT(0), BIT 389 drivers/media/usb/em28xx/em28xx.h EM28XX_AOUT_LINE = BIT(1), BIT 390 drivers/media/usb/em28xx/em28xx.h EM28XX_AOUT_MONO = BIT(2), BIT 391 drivers/media/usb/em28xx/em28xx.h EM28XX_AOUT_LFE = BIT(3), BIT 392 drivers/media/usb/em28xx/em28xx.h EM28XX_AOUT_SURR = BIT(4), BIT 395 drivers/media/usb/em28xx/em28xx.h EM28XX_AOUT_PCM_IN = BIT(7), BIT 502 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c err = stv06xx_write_sensor(sd, HDCS_REG_CONFIG(sd), BIT(3)); BIT 182 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.h {HDCS_STATUS, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)}, BIT 185 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.h {HDCS_PCTRL, BIT(6) | BIT(5) | BIT(1) | BIT(0)}, BIT 187 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.h {HDCS_ICTRL, BIT(5)}, BIT 188 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.h {HDCS_ITMG, BIT(4) | BIT(1)}, BIT 197 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c stv06xx_write_sensor(sd, PB_ROWSPEED, BIT(4)|BIT(3)|BIT(1)); BIT 199 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c stv06xx_write_sensor(sd, PB_ROWSPEED, BIT(5)|BIT(3)|BIT(1)); BIT 226 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = stv06xx_write_sensor(sd, PB_CONTROL, BIT(5)|BIT(3)|BIT(1)); BIT 243 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c err = stv06xx_write_sensor(sd, PB_CONTROL, BIT(5)|BIT(3)); BIT 264 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c stv06xx_write_sensor(sd, PB_CONTROL, BIT(5)|BIT(3)); BIT 267 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c stv06xx_write_sensor(sd, PB_PREADCTRL, BIT(12)|BIT(10)|BIT(6)); BIT 305 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c stv06xx_write_sensor(sd, PB_ROWSPEED, BIT(4)|BIT(3)|BIT(1)); BIT 399 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val = BIT(6)|BIT(4)|BIT(0); BIT 401 drivers/media/usb/gspca/stv06xx/stv06xx_pb0100.c val = BIT(4)|BIT(0); BIT 225 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.h {VV6410_SETUP1, BIT(6)}, BIT 227 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.h {VV6410_FGMODES, BIT(6) | BIT(4) | BIT(2) | BIT(0)}, BIT 230 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.h {VV6410_DATAFORMAT, BIT(7) | BIT(0)}, BIT 236 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.h {VV6410_AS0, BIT(6) | BIT(4) | BIT(3) | BIT(2) | BIT(1)}, BIT 239 drivers/media/usb/gspca/stv06xx/stv06xx_vv6410.h {VV6410_AT1, BIT(4) | BIT(0)}, BIT 46 drivers/media/usb/pwc/pwc.h #define PWC_DEBUG_LEVEL_MODULE BIT(0) BIT 47 drivers/media/usb/pwc/pwc.h #define PWC_DEBUG_LEVEL_PROBE BIT(1) BIT 48 drivers/media/usb/pwc/pwc.h #define PWC_DEBUG_LEVEL_OPEN BIT(2) BIT 49 drivers/media/usb/pwc/pwc.h #define PWC_DEBUG_LEVEL_READ BIT(3) BIT 50 drivers/media/usb/pwc/pwc.h #define PWC_DEBUG_LEVEL_MEMORY BIT(4) BIT 51 drivers/media/usb/pwc/pwc.h #define PWC_DEBUG_LEVEL_FLOW BIT(5) BIT 52 drivers/media/usb/pwc/pwc.h #define PWC_DEBUG_LEVEL_SIZE BIT(6) BIT 53 drivers/media/usb/pwc/pwc.h #define PWC_DEBUG_LEVEL_IOCTL BIT(7) BIT 54 drivers/media/usb/pwc/pwc.h #define PWC_DEBUG_LEVEL_TRACE BIT(8) BIT 24 drivers/media/usb/stk1160/stk1160-reg.h #define STK1160_POSV_L_ACDOUT BIT(3) BIT 25 drivers/media/usb/stk1160/stk1160-reg.h #define STK1160_POSV_L_ACSYNC BIT(2) BIT 62 drivers/media/usb/stk1160/stk1160-reg.h #define STK1160_H_DEC_EN BIT(0) BIT 63 drivers/media/usb/stk1160/stk1160-reg.h #define STK1160_H_DEC_MODE BIT(1) BIT 64 drivers/media/usb/stk1160/stk1160-reg.h #define STK1160_V_DEC_EN BIT(2) BIT 65 drivers/media/usb/stk1160/stk1160-reg.h #define STK1160_V_DEC_MODE BIT(3) BIT 66 drivers/media/usb/stk1160/stk1160-reg.h #define STK1160_DEC_UNIT_SIZE BIT(4) BIT 115 drivers/media/usb/stk1160/stk1160-reg.h #define STK1160_AC97CTL_0_CR BIT(1) BIT 116 drivers/media/usb/stk1160/stk1160-reg.h #define STK1160_AC97CTL_0_CW BIT(2) BIT 182 drivers/media/v4l2-core/v4l2-fwnode.c if (lanes_used & BIT(array[i])) { BIT 188 drivers/media/v4l2-core/v4l2-fwnode.c lanes_used |= BIT(array[i]); BIT 211 drivers/media/v4l2-core/v4l2-fwnode.c if (have_clk_lane && lanes_used & BIT(clock_lane) && BIT 318 drivers/memory/atmel-ebi.c !(ebi->caps->available_cs & BIT(cs))) { BIT 364 drivers/memory/atmel-ebi.c BIT(cs), 0); BIT 101 drivers/memory/brcmstb_dpfe.c #define DCPU_RET_ERROR_BIT BIT(31) BIT 103 drivers/memory/brcmstb_dpfe.c #define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0)) BIT 104 drivers/memory/brcmstb_dpfe.c #define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1)) BIT 105 drivers/memory/brcmstb_dpfe.c #define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2)) BIT 106 drivers/memory/brcmstb_dpfe.c #define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3)) BIT 108 drivers/memory/brcmstb_dpfe.c #define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4)) BIT 25 drivers/memory/jz4780-nemc.c #define NEMC_SMCR_SMT BIT(0) BIT 40 drivers/memory/jz4780-nemc.c #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1) BIT 41 drivers/memory/jz4780-nemc.c #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1) BIT 42 drivers/memory/jz4780-nemc.c #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1) BIT 75 drivers/memory/jz4780-nemc.c if (!(referenced & BIT(bank))) { BIT 76 drivers/memory/jz4780-nemc.c referenced |= BIT(bank); BIT 339 drivers/memory/jz4780-nemc.c referenced |= BIT(bank); BIT 36 drivers/memory/mtk-smi.c #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) BIT 42 drivers/memory/mtk-smi.c #define F_MMU_EN BIT(0) BIT 165 drivers/memory/mtk-smi.c if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) BIT 195 drivers/memory/mtk-smi.c if (*larb->mmu & BIT(i)) { BIT 239 drivers/memory/mtk-smi.c .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ BIT 245 drivers/memory/mtk-smi.c .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), BIT 37 drivers/memory/mvebu-devbus.c #define ORION_WR_HIGH_EXT_BIT BIT(27) BIT 39 drivers/memory/mvebu-devbus.c #define ORION_WR_LOW_EXT_BIT BIT(26) BIT 41 drivers/memory/mvebu-devbus.c #define ORION_ALE_WR_EXT_BIT BIT(25) BIT 43 drivers/memory/mvebu-devbus.c #define ORION_ACC_NEXT_EXT_BIT BIT(24) BIT 45 drivers/memory/mvebu-devbus.c #define ORION_ACC_FIRST_EXT_BIT BIT(23) BIT 47 drivers/memory/mvebu-devbus.c #define ORION_TURN_OFF_EXT_BIT BIT(22) BIT 79 drivers/memory/omap-gpmc.c #define GPMC_CONFIG_LIMITEDADDRESS BIT(1) BIT 81 drivers/memory/omap-gpmc.c #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0) BIT 83 drivers/memory/omap-gpmc.c #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) BIT 84 drivers/memory/omap-gpmc.c #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) BIT 85 drivers/memory/omap-gpmc.c #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) BIT 86 drivers/memory/omap-gpmc.c #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) BIT 87 drivers/memory/omap-gpmc.c #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) BIT 88 drivers/memory/omap-gpmc.c #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) BIT 170 drivers/memory/omap-gpmc.c #define GPMC_CONFIG7_CSVALID_MASK BIT(6) BIT 1270 drivers/memory/omap-gpmc.c regval |= BIT(hwirq); BIT 1272 drivers/memory/omap-gpmc.c regval &= ~BIT(hwirq); BIT 1311 drivers/memory/omap-gpmc.c regval &= ~BIT(hwirq); BIT 1313 drivers/memory/omap-gpmc.c regval |= BIT(hwirq); BIT 1327 drivers/memory/omap-gpmc.c gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq)); BIT 1387 drivers/memory/omap-gpmc.c if (regvalx & BIT(hwirq)) { BIT 2315 drivers/memory/omap-gpmc.c reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset); BIT 31 drivers/memory/pl172.c #define MPMC_STATIC_CFG_PM BIT(3) BIT 32 drivers/memory/pl172.c #define MPMC_STATIC_CFG_PC BIT(6) BIT 33 drivers/memory/pl172.c #define MPMC_STATIC_CFG_PB BIT(7) BIT 34 drivers/memory/pl172.c #define MPMC_STATIC_CFG_EW BIT(8) BIT 35 drivers/memory/pl172.c #define MPMC_STATIC_CFG_B BIT(19) BIT 36 drivers/memory/pl172.c #define MPMC_STATIC_CFG_P BIT(20) BIT 60 drivers/memory/pl353-smc.c #define PL353_SMC_ECC_STATUS_BUSY BIT(6) BIT 49 drivers/memory/tegra/mc.c #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) BIT 52 drivers/memory/tegra/mc.c #define MC_TIMING_UPDATE BIT(0) BIT 85 drivers/memory/tegra/mc.c value = mc_readl(mc, rst->control) | BIT(rst->bit); BIT 96 drivers/memory/tegra/mc.c return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; BIT 107 drivers/memory/tegra/mc.c value = mc_readl(mc, rst->control) & ~BIT(rst->bit); BIT 118 drivers/memory/tegra/mc.c return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; BIT 570 drivers/memory/tegra/mc.c switch (BIT(bit)) { BIT 578 drivers/memory/tegra/mc.c if (value & BIT(31)) BIT 589 drivers/memory/tegra/mc.c if (value & BIT(0)) BIT 598 drivers/memory/tegra/mc.c type = (value & BIT(30)) ? 4 : 3; BIT 602 drivers/memory/tegra/mc.c if (value & BIT(31)) BIT 30 drivers/memory/tegra/tegra124-emc.c #define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4) BIT 33 drivers/memory/tegra/tegra124-emc.c #define EMC_CFG_DRAM_CLKSTOP_PD BIT(31) BIT 34 drivers/memory/tegra/tegra124-emc.c #define EMC_CFG_DRAM_CLKSTOP_SR BIT(30) BIT 35 drivers/memory/tegra/tegra124-emc.c #define EMC_CFG_DRAM_ACPD BIT(29) BIT 36 drivers/memory/tegra/tegra124-emc.c #define EMC_CFG_DYN_SREF BIT(28) BIT 37 drivers/memory/tegra/tegra124-emc.c #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18)) BIT 38 drivers/memory/tegra/tegra124-emc.c #define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18) BIT 42 drivers/memory/tegra/tegra124-emc.c #define EMC_REFCTRL_ENABLE BIT(31) BIT 93 drivers/memory/tegra/tegra124-emc.c #define EMC_MODE_SET_DLL_RESET BIT(8) BIT 94 drivers/memory/tegra/tegra124-emc.c #define EMC_MODE_SET_LONG_CNT BIT(26) BIT 100 drivers/memory/tegra/tegra124-emc.c #define EMC_SELF_REF_CMD_ENABLED BIT(0) BIT 123 drivers/memory/tegra/tegra124-emc.c #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31) BIT 126 drivers/memory/tegra/tegra124-emc.c #define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31) BIT 128 drivers/memory/tegra/tegra124-emc.c #define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23) BIT 132 drivers/memory/tegra/tegra124-emc.c #define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6) BIT 144 drivers/memory/tegra/tegra124-emc.c #define EMC_ZQ_CAL_CMD BIT(0) BIT 145 drivers/memory/tegra/tegra124-emc.c #define EMC_ZQ_CAL_LONG BIT(4) BIT 154 drivers/memory/tegra/tegra124-emc.c #define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0) BIT 155 drivers/memory/tegra/tegra124-emc.c #define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5) BIT 194 drivers/memory/tegra/tegra124-emc.c #define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8) BIT 195 drivers/memory/tegra/tegra124-emc.c #define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5) BIT 196 drivers/memory/tegra/tegra124-emc.c #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4) BIT 197 drivers/memory/tegra/tegra124-emc.c #define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3) BIT 198 drivers/memory/tegra/tegra124-emc.c #define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2) BIT 200 drivers/memory/tegra/tegra124-emc.c ((0xf << 2) | BIT(8)) BIT 202 drivers/memory/tegra/tegra124-emc.c ((0x3 << 2) | BIT(5) | BIT(8)) BIT 262 drivers/memory/tegra/tegra124-emc.c #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3) BIT 263 drivers/memory/tegra/tegra124-emc.c #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2) BIT 264 drivers/memory/tegra/tegra124-emc.c #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1) BIT 73 drivers/memory/tegra/tegra20-emc.c #define EMC_CLKCHANGE_REQ_ENABLE BIT(0) BIT 74 drivers/memory/tegra/tegra20-emc.c #define EMC_CLKCHANGE_PD_ENABLE BIT(1) BIT 75 drivers/memory/tegra/tegra20-emc.c #define EMC_CLKCHANGE_SR_ENABLE BIT(2) BIT 77 drivers/memory/tegra/tegra20-emc.c #define EMC_TIMING_UPDATE BIT(0) BIT 79 drivers/memory/tegra/tegra20-emc.c #define EMC_REFRESH_OVERFLOW_INT BIT(3) BIT 80 drivers/memory/tegra/tegra20-emc.c #define EMC_CLKCHANGE_COMPLETE_INT BIT(4) BIT 207 drivers/memory/tegra/tegra20.c mc_writel(mc, value & ~BIT(rst->bit), rst->reset); BIT 223 drivers/memory/tegra/tegra20.c mc_writel(mc, value | BIT(rst->bit), rst->reset); BIT 238 drivers/memory/tegra/tegra20.c value = mc_readl(mc, rst->control) & ~BIT(rst->bit); BIT 255 drivers/memory/tegra/tegra20.c return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0; BIT 266 drivers/memory/tegra/tegra20.c value = mc_readl(mc, rst->control) | BIT(rst->bit); BIT 69 drivers/memory/ti-aemif.c #define ACR_EW_MASK BIT(30) BIT 70 drivers/memory/ti-aemif.c #define ACR_SS_MASK BIT(31) BIT 133 drivers/mfd/ab8500-core.c #define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT BIT(2) BIT 30 drivers/mfd/axp20x.c #define AXP20X_OFF BIT(7) BIT 33 drivers/mfd/axp20x.c #define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4) BIT 284 drivers/mfd/axp20x.c [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) } BIT 65 drivers/mfd/bcm590xx.c i2c_pri->addr | BIT(2)); BIT 200 drivers/mfd/db8500-prcmu.c #define HOTMON_CONFIG_LOW BIT(0) BIT 201 drivers/mfd/db8500-prcmu.c #define HOTMON_CONFIG_HIGH BIT(1) BIT 206 drivers/mfd/db8500-prcmu.c #define A9WDOG_AUTO_OFF_EN BIT(7) BIT 215 drivers/mfd/db8500-prcmu.c #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6)) BIT 216 drivers/mfd/db8500-prcmu.c #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6)) BIT 217 drivers/mfd/db8500-prcmu.c #define PRCMU_I2C_STOP_EN BIT(3) BIT 226 drivers/mfd/db8500-prcmu.c #define MBOX_BIT BIT BIT 233 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_RTC BIT(0) BIT 234 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_RTT0 BIT(1) BIT 235 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_RTT1 BIT(2) BIT 236 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_HSI0 BIT(3) BIT 237 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_HSI1 BIT(4) BIT 238 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_CA_WAKE BIT(5) BIT 239 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_USB BIT(6) BIT 240 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_ABB BIT(7) BIT 241 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_ABB_FIFO BIT(8) BIT 242 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_SYSCLK_OK BIT(9) BIT 243 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_CA_SLEEP BIT(10) BIT 244 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) BIT 245 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) BIT 246 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_ANC_OK BIT(13) BIT 247 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_SW_ERROR BIT(14) BIT 248 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) BIT 249 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_ARM BIT(17) BIT 250 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_HOTMON_LOW BIT(18) BIT 251 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_HOTMON_HIGH BIT(19) BIT 252 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) BIT 253 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_GPIO0 BIT(23) BIT 254 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_GPIO1 BIT(24) BIT 255 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_GPIO2 BIT(25) BIT 256 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_GPIO3 BIT(26) BIT 257 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_GPIO4 BIT(27) BIT 258 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_GPIO5 BIT(28) BIT 259 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_GPIO6 BIT(29) BIT 260 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_GPIO7 BIT(30) BIT 261 drivers/mfd/db8500-prcmu.c #define WAKEUP_BIT_GPIO8 BIT(31) BIT 332 drivers/mfd/db8500-prcmu.c #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) BIT 852 drivers/mfd/db8500-prcmu.c if (wakeups & BIT(i)) BIT 1083 drivers/mfd/db8500-prcmu.c ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) BIT 1113 drivers/mfd/db8500-prcmu.c ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) BIT 15 drivers/mfd/dbx500-prcmu-regs.h #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) BIT 59 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0) BIT 60 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16) BIT 73 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0) BIT 74 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1) BIT 83 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16) BIT 91 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0) BIT 92 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1) BIT 93 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2) BIT 111 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11) BIT 112 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22) BIT 125 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLL_FREQ_SELDIV2 BIT(24) BIT 126 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLL_FREQ_DIV2EN BIT(25) BIT 137 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0) BIT 139 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 BIT(0) BIT 140 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3 BIT(1) BIT 158 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN BIT(24) BIT 159 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN BIT(25) BIT 160 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN BIT(26) BIT 162 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14) BIT 185 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_SEM_PRCM_SEM BIT(0) BIT 189 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_TCR_STOP_TIMERS BIT(16) BIT 190 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_TCR_DOZE_MODE BIT(17) BIT 200 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_CLKOCR_CLK1TYPE BIT(28) BIT 203 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_CLK_MGT_CLKPLLSW_SOC0 BIT(5) BIT 204 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_CLK_MGT_CLKPLLSW_SOC1 BIT(6) BIT 205 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_CLK_MGT_CLKPLLSW_DDR BIT(7) BIT 207 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_CLK_MGT_CLKEN BIT(8) BIT 208 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_CLK_MGT_CLK38 BIT(9) BIT 209 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_CLK_MGT_CLK38DIV BIT(11) BIT 210 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN BIT(12) BIT 213 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_GPIOCR_SPI2_SELECT BIT(23) BIT 217 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_CGATING_BYPASS_ICN2 BIT(6) BIT 120 drivers/mfd/dm355evm_msp.c #define MSP_GPIO_MASK(offset) BIT(msp_gpios[(offset)] & 0x07) BIT 29 drivers/mfd/exynos-lpass.c #define LPASS_SB_SW_RESET BIT(11) BIT 30 drivers/mfd/exynos-lpass.c #define LPASS_UART_SW_RESET BIT(10) BIT 31 drivers/mfd/exynos-lpass.c #define LPASS_PCM_SW_RESET BIT(9) BIT 32 drivers/mfd/exynos-lpass.c #define LPASS_I2S_SW_RESET BIT(8) BIT 33 drivers/mfd/exynos-lpass.c #define LPASS_WDT1_SW_RESET BIT(4) BIT 34 drivers/mfd/exynos-lpass.c #define LPASS_WDT0_SW_RESET BIT(3) BIT 35 drivers/mfd/exynos-lpass.c #define LPASS_TIMER_SW_RESET BIT(2) BIT 36 drivers/mfd/exynos-lpass.c #define LPASS_MEM_SW_RESET BIT(1) BIT 37 drivers/mfd/exynos-lpass.c #define LPASS_DMA_SW_RESET BIT(0) BIT 41 drivers/mfd/exynos-lpass.c #define LPASS_INTR_APM BIT(9) BIT 42 drivers/mfd/exynos-lpass.c #define LPASS_INTR_MIF BIT(8) BIT 43 drivers/mfd/exynos-lpass.c #define LPASS_INTR_TIMER BIT(7) BIT 44 drivers/mfd/exynos-lpass.c #define LPASS_INTR_DMA BIT(6) BIT 45 drivers/mfd/exynos-lpass.c #define LPASS_INTR_GPIO BIT(5) BIT 46 drivers/mfd/exynos-lpass.c #define LPASS_INTR_I2S BIT(4) BIT 47 drivers/mfd/exynos-lpass.c #define LPASS_INTR_PCM BIT(3) BIT 48 drivers/mfd/exynos-lpass.c #define LPASS_INTR_SLIMBUS BIT(2) BIT 49 drivers/mfd/exynos-lpass.c #define LPASS_INTR_UART BIT(1) BIT 50 drivers/mfd/exynos-lpass.c #define LPASS_INTR_SFR BIT(0) BIT 43 drivers/mfd/intel-lpss.c #define LPSS_PRIV_RESETS_IDMA BIT(2) BIT 49 drivers/mfd/intel-lpss.c #define LPSS_PRIV_LTR_REQ BIT(15) BIT 56 drivers/mfd/intel-lpss.c #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0) BIT 61 drivers/mfd/intel-lpss.c #define LPSS_PRIV_CAPS_NO_IDMA BIT(8) BIT 43 drivers/mfd/intel_soc_pmic_bxtwc.c #define BXTWC_MIRQLVL1_MCHGR BIT(5) BIT 100 drivers/mfd/intel_soc_pmic_bxtwc.c REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)), BIT 101 drivers/mfd/intel_soc_pmic_bxtwc.c REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)), BIT 102 drivers/mfd/intel_soc_pmic_bxtwc.c REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)), BIT 103 drivers/mfd/intel_soc_pmic_bxtwc.c REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)), BIT 104 drivers/mfd/intel_soc_pmic_bxtwc.c REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)), BIT 105 drivers/mfd/intel_soc_pmic_bxtwc.c REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)), BIT 106 drivers/mfd/intel_soc_pmic_bxtwc.c REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)), BIT 107 drivers/mfd/intel_soc_pmic_bxtwc.c REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)), BIT 89 drivers/mfd/intel_soc_pmic_chtdc_ti.c REGMAP_IRQ_REG(CHTDC_TI_PWRBTN, 0, BIT(CHTDC_TI_PWRBTN)), BIT 90 drivers/mfd/intel_soc_pmic_chtdc_ti.c REGMAP_IRQ_REG(CHTDC_TI_DIETMPWARN, 0, BIT(CHTDC_TI_DIETMPWARN)), BIT 91 drivers/mfd/intel_soc_pmic_chtdc_ti.c REGMAP_IRQ_REG(CHTDC_TI_ADCCMPL, 0, BIT(CHTDC_TI_ADCCMPL)), BIT 92 drivers/mfd/intel_soc_pmic_chtdc_ti.c REGMAP_IRQ_REG(CHTDC_TI_VBATLOW, 0, BIT(CHTDC_TI_VBATLOW)), BIT 93 drivers/mfd/intel_soc_pmic_chtdc_ti.c REGMAP_IRQ_REG(CHTDC_TI_VBUSDET, 0, BIT(CHTDC_TI_VBUSDET)), BIT 94 drivers/mfd/intel_soc_pmic_chtdc_ti.c REGMAP_IRQ_REG(CHTDC_TI_CCEOCAL, 0, BIT(CHTDC_TI_CCEOCAL)), BIT 119 drivers/mfd/intel_soc_pmic_chtwc.c REGMAP_IRQ_REG(CHT_WC_PWRSRC_IRQ, 0, BIT(CHT_WC_PWRSRC_IRQ)), BIT 120 drivers/mfd/intel_soc_pmic_chtwc.c REGMAP_IRQ_REG(CHT_WC_THRM_IRQ, 0, BIT(CHT_WC_THRM_IRQ)), BIT 121 drivers/mfd/intel_soc_pmic_chtwc.c REGMAP_IRQ_REG(CHT_WC_BCU_IRQ, 0, BIT(CHT_WC_BCU_IRQ)), BIT 122 drivers/mfd/intel_soc_pmic_chtwc.c REGMAP_IRQ_REG(CHT_WC_ADC_IRQ, 0, BIT(CHT_WC_ADC_IRQ)), BIT 123 drivers/mfd/intel_soc_pmic_chtwc.c REGMAP_IRQ_REG(CHT_WC_EXT_CHGR_IRQ, 0, BIT(CHT_WC_EXT_CHGR_IRQ)), BIT 124 drivers/mfd/intel_soc_pmic_chtwc.c REGMAP_IRQ_REG(CHT_WC_GPIO_IRQ, 0, BIT(CHT_WC_GPIO_IRQ)), BIT 125 drivers/mfd/intel_soc_pmic_chtwc.c REGMAP_IRQ_REG(CHT_WC_CRIT_IRQ, 0, BIT(CHT_WC_CRIT_IRQ)), BIT 105 drivers/mfd/intel_soc_pmic_crc.c REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)), BIT 106 drivers/mfd/intel_soc_pmic_crc.c REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)), BIT 107 drivers/mfd/intel_soc_pmic_crc.c REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)), BIT 108 drivers/mfd/intel_soc_pmic_crc.c REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)), BIT 109 drivers/mfd/intel_soc_pmic_crc.c REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)), BIT 110 drivers/mfd/intel_soc_pmic_crc.c REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)), BIT 111 drivers/mfd/intel_soc_pmic_crc.c REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)), BIT 65 drivers/mfd/lpc_ich.c #define SPIBASE_BYT_EN BIT(1) BIT 70 drivers/mfd/lpc_ich.c #define BCR_WPD BIT(0) BIT 18 drivers/mfd/max77650.c #define MAX77650_INT_GPI_F_MSK BIT(0) BIT 19 drivers/mfd/max77650.c #define MAX77650_INT_GPI_R_MSK BIT(1) BIT 22 drivers/mfd/max77650.c #define MAX77650_INT_nEN_F_MSK BIT(2) BIT 23 drivers/mfd/max77650.c #define MAX77650_INT_nEN_R_MSK BIT(3) BIT 24 drivers/mfd/max77650.c #define MAX77650_INT_TJAL1_R_MSK BIT(4) BIT 25 drivers/mfd/max77650.c #define MAX77650_INT_TJAL2_R_MSK BIT(5) BIT 26 drivers/mfd/max77650.c #define MAX77650_INT_DOD_R_MSK BIT(6) BIT 28 drivers/mfd/max77650.c #define MAX77650_INT_THM_MSK BIT(0) BIT 29 drivers/mfd/max77650.c #define MAX77650_INT_CHG_MSK BIT(1) BIT 30 drivers/mfd/max77650.c #define MAX77650_INT_CHGIN_MSK BIT(2) BIT 31 drivers/mfd/max77650.c #define MAX77650_INT_TJ_REG_MSK BIT(3) BIT 32 drivers/mfd/max77650.c #define MAX77650_INT_CHGIN_CTRL_MSK BIT(4) BIT 33 drivers/mfd/max77650.c #define MAX77650_INT_SYS_CTRL_MSK BIT(5) BIT 34 drivers/mfd/max77650.c #define MAX77650_INT_SYS_CNFG_MSK BIT(6) BIT 39 drivers/mfd/max77650.c #define MAX77650_SBIA_LPM_MASK BIT(5) BIT 84 drivers/mfd/mc13xxx-core.c if (val >= BIT(24)) BIT 442 drivers/mfd/mc13xxx-core.c mc13xxx->irqs[i].mask = BIT(i % MC13XXX_IRQ_PER_REG); BIT 38 drivers/mfd/motorola-cpcap.c int mask = BIT(irq % CPCAP_REGISTER_BITS); BIT 42 drivers/mfd/mt6397-irq.c mt6397->irq_masks_cur[reg] &= ~BIT(shift); BIT 51 drivers/mfd/mt6397-irq.c mt6397->irq_masks_cur[reg] |= BIT(shift); BIT 62 drivers/mfd/mt6397-irq.c mt6397->wake_mask[reg] |= BIT(shift); BIT 64 drivers/mfd/mt6397-irq.c mt6397->wake_mask[reg] &= ~BIT(shift); BIT 94 drivers/mfd/mt6397-irq.c if (status & BIT(i)) { BIT 353 drivers/mfd/palmas.c reg_add, BIT(bit_pos), BIT(bit_pos)); BIT 356 drivers/mfd/palmas.c reg_add, BIT(bit_pos), 0); BIT 365 drivers/mfd/palmas.c PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0); BIT 217 drivers/mfd/qcom-pm8xxx.c if (bits & BIT(i)) { BIT 231 drivers/mfd/qcom-pm8xxx.c if (master_val & BIT(block)) BIT 255 drivers/mfd/qcom-pm8xxx.c if (!(master & BIT(0))) BIT 355 drivers/mfd/qcom-pm8xxx.c *state = !!(bits & BIT(irq_bit)); BIT 419 drivers/mfd/qcom-pm8xxx.c BIT(irq_bit), BIT(irq_bit)); BIT 427 drivers/mfd/qcom-pm8xxx.c BIT(irq_bit), BIT(irq_bit)); BIT 446 drivers/mfd/qcom-pm8xxx.c BIT(irq_bit), ~BIT(irq_bit)); BIT 473 drivers/mfd/qcom-pm8xxx.c *state = !!(bits & BIT(irq_bit)); BIT 66 drivers/mfd/qcom_rpm.c #define RPM_NOTIFICATION BIT(30) BIT 67 drivers/mfd/qcom_rpm.c #define RPM_REJECTED BIT(31) BIT 475 drivers/mfd/qcom_rpm.c writel_relaxed(BIT(state), RPM_CTRL_REG(rpm, rpm->data->req_ctx_off)); BIT 478 drivers/mfd/qcom_rpm.c regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit)); BIT 518 drivers/mfd/qcom_rpm.c regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit)); BIT 278 drivers/mfd/rc5t583-irq.c rtc_int_sts |= BIT(6); BIT 280 drivers/mfd/rc5t583-irq.c rtc_int_sts |= BIT(7); BIT 282 drivers/mfd/rc5t583-irq.c rtc_int_sts |= BIT(0); BIT 284 drivers/mfd/rc5t583-irq.c rtc_int_sts |= BIT(5); BIT 94 drivers/mfd/rc5t583.c sleepseq_val |= BIT(en_bit); BIT 96 drivers/mfd/rc5t583.c ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1)); BIT 129 drivers/mfd/rc5t583.c ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(2)); BIT 234 drivers/mfd/rk808.c { RK818_H5V_EN_REG, BIT(1), RK818_REF_RDY_CTRL }, BIT 236 drivers/mfd/rk808.c { RK818_H5V_EN_REG, BIT(0), RK818_H5V_EN }, BIT 203 drivers/mfd/sprd-sc27xx-spi.c ddata->irqs[i].mask = BIT(i % pdata->num_irqs); BIT 186 drivers/mfd/stmfx.c stmfx->irq_src &= ~BIT(data->hwirq % 8); BIT 193 drivers/mfd/stmfx.c stmfx->irq_src |= BIT(data->hwirq % 8); BIT 219 drivers/mfd/stmfx.c ack = pending & ~BIT(STMFX_REG_IRQ_SRC_EN_GPIO); BIT 61 drivers/mfd/t7l66xb.c #define SCR_DEV_CTL_USB BIT(0) /* USB enable */ BIT 62 drivers/mfd/t7l66xb.c #define SCR_DEV_CTL_MMC BIT(1) /* MMC enable */ BIT 54 drivers/mfd/tc6393xb.c #define SCR_CCR_CK32K BIT(0) BIT 55 drivers/mfd/tc6393xb.c #define SCR_CCR_USBCK BIT(1) BIT 56 drivers/mfd/tc6393xb.c #define SCR_CCR_UNK1 BIT(4) BIT 66 drivers/mfd/tc6393xb.c #define SCR_FER_USBEN BIT(0) /* USB host enable */ BIT 67 drivers/mfd/tc6393xb.c #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */ BIT 68 drivers/mfd/tc6393xb.c #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */ BIT 74 drivers/mfd/tc6393xb.c #define SCR_MCR_RDY_UNK BIT(2) BIT 75 drivers/mfd/tc6393xb.c #define SCR_MCR_RDY_EN BIT(3) BIT 80 drivers/mfd/tc6393xb.c #define SCR_MCR_INT_UNK BIT(6) BIT 81 drivers/mfd/tc6393xb.c #define SCR_MCR_INT_EN BIT(7) BIT 670 drivers/mfd/tc6393xb.c BIT(15), tc6393xb->scr + SCR_MCR); BIT 806 drivers/mfd/tc6393xb.c BIT(15), tc6393xb->scr + SCR_MCR); BIT 68 drivers/mfd/tps65217.c u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT; BIT 76 drivers/mfd/tps65217.c u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT; BIT 128 drivers/mfd/tps65217.c if (status & BIT(i)) { BIT 32 drivers/mfd/tps6586x.c #define EXITSLREQ_BIT BIT(1) BIT 33 drivers/mfd/tps6586x.c #define SLEEP_MODE_BIT BIT(3) BIT 86 drivers/mfd/tps80031.c .mask = BIT(_mask), \ BIT 133 drivers/mfd/tps80031.c [TPS80031_PREQ1] = PUPD_DATA(1, BIT(0), BIT(1)), BIT 134 drivers/mfd/tps80031.c [TPS80031_PREQ2A] = PUPD_DATA(1, BIT(2), BIT(3)), BIT 135 drivers/mfd/tps80031.c [TPS80031_PREQ2B] = PUPD_DATA(1, BIT(4), BIT(5)), BIT 136 drivers/mfd/tps80031.c [TPS80031_PREQ2C] = PUPD_DATA(1, BIT(6), BIT(7)), BIT 137 drivers/mfd/tps80031.c [TPS80031_PREQ3] = PUPD_DATA(2, BIT(0), BIT(1)), BIT 138 drivers/mfd/tps80031.c [TPS80031_NRES_WARM] = PUPD_DATA(2, 0, BIT(2)), BIT 139 drivers/mfd/tps80031.c [TPS80031_PWM_FORCE] = PUPD_DATA(2, BIT(5), 0), BIT 140 drivers/mfd/tps80031.c [TPS80031_CHRG_EXT_CHRG_STATZ] = PUPD_DATA(2, 0, BIT(6)), BIT 141 drivers/mfd/tps80031.c [TPS80031_SIM] = PUPD_DATA(3, BIT(0), BIT(1)), BIT 142 drivers/mfd/tps80031.c [TPS80031_MMC] = PUPD_DATA(3, BIT(2), BIT(3)), BIT 143 drivers/mfd/tps80031.c [TPS80031_GPADC_START] = PUPD_DATA(3, BIT(4), 0), BIT 144 drivers/mfd/tps80031.c [TPS80031_DVSI2C_SCL] = PUPD_DATA(4, 0, BIT(0)), BIT 145 drivers/mfd/tps80031.c [TPS80031_DVSI2C_SDA] = PUPD_DATA(4, 0, BIT(1)), BIT 146 drivers/mfd/tps80031.c [TPS80031_CTLI2C_SCL] = PUPD_DATA(4, 0, BIT(2)), BIT 147 drivers/mfd/tps80031.c [TPS80031_CTLI2C_SDA] = PUPD_DATA(4, 0, BIT(3)), BIT 175 drivers/mfd/tps80031.c BIT(preq_bit & 0x7)); BIT 184 drivers/mfd/tps80031.c TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit)); BIT 90 drivers/mfd/twl-core.c #define SMARTREFLEX_ENABLE BIT(3) BIT 295 drivers/mfd/twl4030-irq.c pih_isr &= ~BIT(pending); BIT 440 drivers/mfd/twl4030-irq.c agent->imr |= BIT(data->irq - agent->irq_base); BIT 448 drivers/mfd/twl4030-irq.c agent->imr &= ~BIT(data->irq - agent->irq_base); BIT 460 drivers/mfd/twl4030-irq.c agent->edge_change |= BIT(data->irq - agent->irq_base); BIT 529 drivers/mfd/twl4030-irq.c bytes[byte] |= BIT(off + 1); BIT 531 drivers/mfd/twl4030-irq.c bytes[byte] |= BIT(off + 0); BIT 533 drivers/mfd/twl4030-irq.c edge_change &= ~BIT(i); BIT 599 drivers/mfd/twl4030-irq.c isr &= ~BIT(irq); BIT 38 drivers/mfd/twl4030-power.c #define PWR_STOPON_PRWON BIT(6) BIT 39 drivers/mfd/twl4030-power.c #define PWR_STOPON_SYSEN BIT(5) BIT 40 drivers/mfd/twl4030-power.c #define PWR_ENABLE_WARMRESET BIT(4) BIT 41 drivers/mfd/twl4030-power.c #define PWR_LVL_WAKEUP BIT(3) BIT 42 drivers/mfd/twl4030-power.c #define PWR_DEVACT BIT(2) BIT 43 drivers/mfd/twl4030-power.c #define PWR_DEVSLP BIT(1) BIT 44 drivers/mfd/twl4030-power.c #define PWR_DEVOFF BIT(0) BIT 47 drivers/mfd/twl4030-power.c #define STARTON_SWBUG BIT(7) /* Start on watchdog */ BIT 48 drivers/mfd/twl4030-power.c #define STARTON_VBUS BIT(5) /* Start on VBUS */ BIT 49 drivers/mfd/twl4030-power.c #define STARTON_VBAT BIT(4) /* Start on battery insert */ BIT 50 drivers/mfd/twl4030-power.c #define STARTON_RTC BIT(3) /* Start on RTC */ BIT 51 drivers/mfd/twl4030-power.c #define STARTON_USB BIT(2) /* Start on USB host */ BIT 52 drivers/mfd/twl4030-power.c #define STARTON_CHG BIT(1) /* Start on charger */ BIT 53 drivers/mfd/twl4030-power.c #define STARTON_PWON BIT(0) /* Start on PWRON button */ BIT 28 drivers/misc/eeprom/at24.c #define AT24_FLAG_ADDR16 BIT(7) BIT 30 drivers/misc/eeprom/at24.c #define AT24_FLAG_READONLY BIT(6) BIT 32 drivers/misc/eeprom/at24.c #define AT24_FLAG_IRUGO BIT(5) BIT 34 drivers/misc/eeprom/at24.c #define AT24_FLAG_TAKE8ADDR BIT(4) BIT 36 drivers/misc/eeprom/at24.c #define AT24_FLAG_SERIAL BIT(3) BIT 38 drivers/misc/eeprom/at24.c #define AT24_FLAG_MAC BIT(2) BIT 40 drivers/misc/eeprom/at24.c #define AT24_FLAG_NO_RDROL BIT(1) BIT 278 drivers/misc/eeprom/at24.c remainder = BIT(bits) - offset; BIT 215 drivers/misc/habanalabs/goya/goya_coresight.c up ? val & BIT(position) : !(val & BIT(position)), BIT 51 drivers/misc/mei/hw-txe-regs.h # define SEC_IPC_INPUT_STATUS_RDY BIT(0) BIT 55 drivers/misc/mei/hw-txe-regs.h #define SEC_IPC_HOST_INT_STATUS_OUT_DB BIT(0) BIT 56 drivers/misc/mei/hw-txe-regs.h #define SEC_IPC_HOST_INT_STATUS_IN_RDY BIT(1) BIT 57 drivers/misc/mei/hw-txe-regs.h #define SEC_IPC_HOST_INT_STATUS_HDCP_M0_RCVD BIT(5) BIT 58 drivers/misc/mei/hw-txe-regs.h #define SEC_IPC_HOST_INT_STATUS_ILL_MEM_ACCESS BIT(17) BIT 59 drivers/misc/mei/hw-txe-regs.h #define SEC_IPC_HOST_INT_STATUS_AES_HKEY_ERR BIT(18) BIT 60 drivers/misc/mei/hw-txe-regs.h #define SEC_IPC_HOST_INT_STATUS_DES_HKEY_ERR BIT(19) BIT 61 drivers/misc/mei/hw-txe-regs.h #define SEC_IPC_HOST_INT_STATUS_TMRMTB_OVERFLOW BIT(21) BIT 71 drivers/misc/mei/hw-txe-regs.h # define SEC_IPC_HOST_INT_MASK_OUT_DB BIT(0) /* Output Doorbell Int Mask */ BIT 72 drivers/misc/mei/hw-txe-regs.h # define SEC_IPC_HOST_INT_MASK_IN_RDY BIT(1) /* Input Ready Int Mask */ BIT 84 drivers/misc/mei/hw-txe-regs.h # define SATT2_CTRL_VALID_MSK BIT(0) BIT 86 drivers/misc/mei/hw-txe-regs.h # define SATT2_CTRL_BRIDGE_HOST_EN_MSK BIT(12) BIT 105 drivers/misc/mei/hw-txe-regs.h #define IPC_HHIER_SEC BIT(0) BIT 106 drivers/misc/mei/hw-txe-regs.h #define IPC_HHIER_BRIDGE BIT(1) BIT 115 drivers/misc/mei/hw-txe-regs.h #define IPC_HHIMR_SEC BIT(0) BIT 116 drivers/misc/mei/hw-txe-regs.h #define IPC_HHIMR_BRIDGE BIT(1) BIT 129 drivers/misc/mei/hw-txe-regs.h #define HICR_SEC_IPC_READINESS_HOST_RDY BIT(0) BIT 130 drivers/misc/mei/hw-txe-regs.h #define HICR_SEC_IPC_READINESS_SEC_RDY BIT(1) BIT 134 drivers/misc/mei/hw-txe-regs.h #define HICR_SEC_IPC_READINESS_RDY_CLR BIT(2) BIT 142 drivers/misc/mei/hw-txe-regs.h #define HICR_HOST_ALIVENESS_RESP_ACK BIT(0) BIT 161 drivers/misc/mei/hw-txe-regs.h #define HISR_INT_0_STS BIT(0) BIT 162 drivers/misc/mei/hw-txe-regs.h #define HISR_INT_1_STS BIT(1) BIT 163 drivers/misc/mei/hw-txe-regs.h #define HISR_INT_2_STS BIT(2) BIT 164 drivers/misc/mei/hw-txe-regs.h #define HISR_INT_3_STS BIT(3) BIT 165 drivers/misc/mei/hw-txe-regs.h #define HISR_INT_4_STS BIT(4) BIT 166 drivers/misc/mei/hw-txe-regs.h #define HISR_INT_5_STS BIT(5) BIT 167 drivers/misc/mei/hw-txe-regs.h #define HISR_INT_6_STS BIT(6) BIT 168 drivers/misc/mei/hw-txe-regs.h #define HISR_INT_7_STS BIT(7) BIT 174 drivers/misc/mei/hw-txe-regs.h #define HIER_INT_0_EN BIT(0) BIT 175 drivers/misc/mei/hw-txe-regs.h #define HIER_INT_1_EN BIT(1) BIT 176 drivers/misc/mei/hw-txe-regs.h #define HIER_INT_2_EN BIT(2) BIT 177 drivers/misc/mei/hw-txe-regs.h #define HIER_INT_3_EN BIT(3) BIT 178 drivers/misc/mei/hw-txe-regs.h #define HIER_INT_4_EN BIT(4) BIT 179 drivers/misc/mei/hw-txe-regs.h #define HIER_INT_5_EN BIT(5) BIT 180 drivers/misc/mei/hw-txe-regs.h #define HIER_INT_6_EN BIT(6) BIT 181 drivers/misc/mei/hw-txe-regs.h #define HIER_INT_7_EN BIT(7) BIT 199 drivers/misc/mei/hw-txe-regs.h #define SICR_HOST_ALIVENESS_REQ_REQUESTED BIT(0) BIT 212 drivers/misc/mei/hw-txe-regs.h #define SICR_HOST_IPC_READINESS_HOST_RDY BIT(0) BIT 213 drivers/misc/mei/hw-txe-regs.h #define SICR_HOST_IPC_READINESS_SEC_RDY BIT(1) BIT 217 drivers/misc/mei/hw-txe-regs.h #define SICR_HOST_IPC_READINESS_RDY_CLR BIT(2) BIT 227 drivers/misc/mei/hw-txe-regs.h # define SEC_IPC_OUTPUT_STATUS_RDY BIT(0) BIT 25 drivers/misc/mei/hw-txe.h #define TXE_INTR_IN_READY BIT(8) BIT 276 drivers/misc/mei/hw.h MEI_HBM_ENUM_F_ALLOW_ADD = BIT(0), BIT 277 drivers/misc/mei/hw.h MEI_HBM_ENUM_F_IMMEDIATE_ENUM = BIT(1), BIT 101 drivers/misc/mei/mei_dev.h MEI_CL_IO_TX_BLOCKING = BIT(0), BIT 102 drivers/misc/mei/mei_dev.h MEI_CL_IO_TX_INTERNAL = BIT(1), BIT 104 drivers/misc/mei/mei_dev.h MEI_CL_IO_RX_NONBLOCK = BIT(2), BIT 179 drivers/misc/mei/pci-me.c err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); BIT 57 drivers/misc/mei/pci-txe.c const int mask = BIT(SEC_BAR) | BIT(BRIDGE_BAR); BIT 92 drivers/misc/mic/host/mic_debugfs.c BIT(j)) ? 1 : 0); BIT 58 drivers/misc/mic/host/mic_intr.c if (mask & BIT(i)) { BIT 459 drivers/misc/mic/host/mic_intr.c mdev->irq_info.mic_msi_map[entry] |= BIT(offset); BIT 521 drivers/misc/mic/host/mic_intr.c mdev->irq_info.mic_msi_map[entry] &= ~(BIT(offset)); BIT 534 drivers/misc/mic/host/mic_intr.c mdev->irq_info.mic_msi_map[entry] &= ~(BIT(src_id)); BIT 628 drivers/misc/mic/host/mic_intr.c if (mdev->irq_info.mic_msi_map[entry] & BIT(offset)) BIT 464 drivers/misc/mic/scif/scif_dma.c #define SCIF_DMA_POLL BIT(0) BIT 465 drivers/misc/mic/scif/scif_dma.c #define SCIF_DMA_INTR BIT(1) BIT 113 drivers/misc/mic/vop/vop_main.c if (ioread8(&in_features[i / 8]) & (BIT(i % 8))) BIT 8 drivers/misc/ocxl/config.c #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit))) BIT 825 drivers/misc/ocxl/config.c val |= BIT(20); BIT 37 drivers/misc/pci_endpoint_test.c #define COMMAND_RAISE_LEGACY_IRQ BIT(0) BIT 38 drivers/misc/pci_endpoint_test.c #define COMMAND_RAISE_MSI_IRQ BIT(1) BIT 39 drivers/misc/pci_endpoint_test.c #define COMMAND_RAISE_MSIX_IRQ BIT(2) BIT 40 drivers/misc/pci_endpoint_test.c #define COMMAND_READ BIT(3) BIT 41 drivers/misc/pci_endpoint_test.c #define COMMAND_WRITE BIT(4) BIT 42 drivers/misc/pci_endpoint_test.c #define COMMAND_COPY BIT(5) BIT 45 drivers/misc/pci_endpoint_test.c #define STATUS_READ_SUCCESS BIT(0) BIT 46 drivers/misc/pci_endpoint_test.c #define STATUS_READ_FAIL BIT(1) BIT 47 drivers/misc/pci_endpoint_test.c #define STATUS_WRITE_SUCCESS BIT(2) BIT 48 drivers/misc/pci_endpoint_test.c #define STATUS_WRITE_FAIL BIT(3) BIT 49 drivers/misc/pci_endpoint_test.c #define STATUS_COPY_SUCCESS BIT(4) BIT 50 drivers/misc/pci_endpoint_test.c #define STATUS_COPY_FAIL BIT(5) BIT 51 drivers/misc/pci_endpoint_test.c #define STATUS_IRQ_RAISED BIT(6) BIT 52 drivers/misc/pci_endpoint_test.c #define STATUS_SRC_ADDR_INVALID BIT(7) BIT 53 drivers/misc/pci_endpoint_test.c #define STATUS_DST_ADDR_INVALID BIT(8) BIT 139 drivers/misc/phantom.c if (rs.mask & BIT(i)) BIT 170 drivers/misc/phantom.c if (rs.mask & BIT(i)) BIT 303 drivers/misc/phantom.c if (r->mask & BIT(i)) BIT 24 drivers/misc/qcom-coincell.c #define QCOM_COINCELL_ENABLE BIT(7) BIT 117 drivers/mmc/core/block.c #define MMC_BLK_READ BIT(0) BIT 118 drivers/mmc/core/block.c #define MMC_BLK_WRITE BIT(1) BIT 119 drivers/mmc/core/block.c #define MMC_BLK_DISCARD BIT(2) BIT 120 drivers/mmc/core/block.c #define MMC_BLK_SECDISCARD BIT(3) BIT 121 drivers/mmc/core/block.c #define MMC_BLK_CQE_RECOVERY BIT(4) BIT 577 drivers/mmc/core/block.c sbc.arg = data.blocks | (idata->ic.write_flag & BIT(31)); BIT 1678 drivers/mmc/core/mmc.c if (rocr & BIT(30)) BIT 204 drivers/mmc/core/mmc_ops.c cmd.arg = cmd.resp[0] | BIT(30); BIT 83 drivers/mmc/core/queue.h #define MMC_CQE_DCMD_BUSY BIT(0) BIT 84 drivers/mmc/core/queue.h #define MMC_CQE_QUEUE_FULL BIT(1) BIT 50 drivers/mmc/host/atmel-mci.c #define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */ BIT 51 drivers/mmc/host/atmel-mci.c #define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */ BIT 52 drivers/mmc/host/atmel-mci.c #define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */ BIT 53 drivers/mmc/host/atmel-mci.c #define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */ BIT 54 drivers/mmc/host/atmel-mci.c #define ATMCI_CR_SWRST BIT(7) /* Software Reset */ BIT 58 drivers/mmc/host/atmel-mci.c #define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */ BIT 59 drivers/mmc/host/atmel-mci.c #define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */ BIT 60 drivers/mmc/host/atmel-mci.c #define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */ BIT 61 drivers/mmc/host/atmel-mci.c #define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */ BIT 62 drivers/mmc/host/atmel-mci.c #define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */ BIT 115 drivers/mmc/host/atmel-mci.c #define ATMCI_CMDRDY BIT(0) /* Command Ready */ BIT 116 drivers/mmc/host/atmel-mci.c #define ATMCI_RXRDY BIT(1) /* Receiver Ready */ BIT 117 drivers/mmc/host/atmel-mci.c #define ATMCI_TXRDY BIT(2) /* Transmitter Ready */ BIT 118 drivers/mmc/host/atmel-mci.c #define ATMCI_BLKE BIT(3) /* Data Block Ended */ BIT 119 drivers/mmc/host/atmel-mci.c #define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */ BIT 120 drivers/mmc/host/atmel-mci.c #define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */ BIT 121 drivers/mmc/host/atmel-mci.c #define ATMCI_ENDRX BIT(6) /* End of RX Buffer */ BIT 122 drivers/mmc/host/atmel-mci.c #define ATMCI_ENDTX BIT(7) /* End of TX Buffer */ BIT 123 drivers/mmc/host/atmel-mci.c #define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */ BIT 124 drivers/mmc/host/atmel-mci.c #define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */ BIT 125 drivers/mmc/host/atmel-mci.c #define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */ BIT 126 drivers/mmc/host/atmel-mci.c #define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */ BIT 127 drivers/mmc/host/atmel-mci.c #define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */ BIT 128 drivers/mmc/host/atmel-mci.c #define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */ BIT 129 drivers/mmc/host/atmel-mci.c #define ATMCI_RINDE BIT(16) /* Response Index Error */ BIT 130 drivers/mmc/host/atmel-mci.c #define ATMCI_RDIRE BIT(17) /* Response Direction Error */ BIT 131 drivers/mmc/host/atmel-mci.c #define ATMCI_RCRCE BIT(18) /* Response CRC Error */ BIT 132 drivers/mmc/host/atmel-mci.c #define ATMCI_RENDE BIT(19) /* Response End Bit Error */ BIT 133 drivers/mmc/host/atmel-mci.c #define ATMCI_RTOE BIT(20) /* Response Time-Out Error */ BIT 134 drivers/mmc/host/atmel-mci.c #define ATMCI_DCRCE BIT(21) /* Data CRC Error */ BIT 135 drivers/mmc/host/atmel-mci.c #define ATMCI_DTOE BIT(22) /* Data Time-Out Error */ BIT 136 drivers/mmc/host/atmel-mci.c #define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */ BIT 137 drivers/mmc/host/atmel-mci.c #define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */ BIT 138 drivers/mmc/host/atmel-mci.c #define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */ BIT 139 drivers/mmc/host/atmel-mci.c #define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */ BIT 140 drivers/mmc/host/atmel-mci.c #define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */ BIT 141 drivers/mmc/host/atmel-mci.c #define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */ BIT 142 drivers/mmc/host/atmel-mci.c #define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */ BIT 143 drivers/mmc/host/atmel-mci.c #define ATMCI_OVRE BIT(30) /* RX Overrun Error */ BIT 144 drivers/mmc/host/atmel-mci.c #define ATMCI_UNRE BIT(31) /* TX Underrun Error */ BIT 148 drivers/mmc/host/atmel-mci.c #define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */ BIT 150 drivers/mmc/host/atmel-mci.c #define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */ BIT 151 drivers/mmc/host/atmel-mci.c #define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */ BIT 152 drivers/mmc/host/atmel-mci.c #define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */ BIT 153 drivers/mmc/host/atmel-mci.c #define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */ BIT 155 drivers/mmc/host/atmel-mci.c #define ATMCI_WP_EN BIT(0) /* WP Enable */ BIT 99 drivers/mmc/host/bcm2835.c #define SDHCFG_BUSY_IRPT_EN BIT(10) BIT 100 drivers/mmc/host/bcm2835.c #define SDHCFG_BLOCK_IRPT_EN BIT(8) BIT 101 drivers/mmc/host/bcm2835.c #define SDHCFG_SDIO_IRPT_EN BIT(5) BIT 102 drivers/mmc/host/bcm2835.c #define SDHCFG_DATA_IRPT_EN BIT(4) BIT 103 drivers/mmc/host/bcm2835.c #define SDHCFG_SLOW_CARD BIT(3) BIT 104 drivers/mmc/host/bcm2835.c #define SDHCFG_WIDE_EXT_BUS BIT(2) BIT 105 drivers/mmc/host/bcm2835.c #define SDHCFG_WIDE_INT_BUS BIT(1) BIT 106 drivers/mmc/host/bcm2835.c #define SDHCFG_REL_CMD_LINE BIT(0) BIT 111 drivers/mmc/host/bcm2835.c #define SDEDM_FORCE_DATA_MODE BIT(19) BIT 112 drivers/mmc/host/bcm2835.c #define SDEDM_CLOCK_PULSE BIT(20) BIT 113 drivers/mmc/host/bcm2835.c #define SDEDM_BYPASS BIT(21) BIT 28 drivers/mmc/host/cqhci.c #define CQHCI_EXTERNAL_TIMEOUT BIT(0) BIT 29 drivers/mmc/host/cqhci.c #define CQHCI_COMPLETED BIT(1) BIT 30 drivers/mmc/host/cqhci.c #define CQHCI_HOST_CRC BIT(2) BIT 31 drivers/mmc/host/cqhci.c #define CQHCI_HOST_TIMEOUT BIT(3) BIT 32 drivers/mmc/host/cqhci.c #define CQHCI_HOST_OTHER BIT(4) BIT 38 drivers/mmc/host/cqhci.h #define CQHCI_IS_HAC BIT(0) BIT 39 drivers/mmc/host/cqhci.h #define CQHCI_IS_TCC BIT(1) BIT 40 drivers/mmc/host/cqhci.h #define CQHCI_IS_RED BIT(2) BIT 41 drivers/mmc/host/cqhci.h #define CQHCI_IS_TCL BIT(3) BIT 53 drivers/mmc/host/cqhci.h #define CQHCI_IC_ENABLE BIT(31) BIT 54 drivers/mmc/host/cqhci.h #define CQHCI_IC_RESET BIT(16) BIT 55 drivers/mmc/host/cqhci.h #define CQHCI_IC_ICCTHWEN BIT(15) BIT 57 drivers/mmc/host/cqhci.h #define CQHCI_IC_ICTOVALWEN BIT(7) BIT 99 drivers/mmc/host/cqhci.h #define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15)) BIT 102 drivers/mmc/host/cqhci.h #define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31)) BIT 83 drivers/mmc/host/davinci_mmc.c #define MMCST0_DATDNE BIT(0) /* data done */ BIT 84 drivers/mmc/host/davinci_mmc.c #define MMCST0_BSYDNE BIT(1) /* busy done */ BIT 85 drivers/mmc/host/davinci_mmc.c #define MMCST0_RSPDNE BIT(2) /* command done */ BIT 86 drivers/mmc/host/davinci_mmc.c #define MMCST0_TOUTRD BIT(3) /* data read timeout */ BIT 87 drivers/mmc/host/davinci_mmc.c #define MMCST0_TOUTRS BIT(4) /* command response timeout */ BIT 88 drivers/mmc/host/davinci_mmc.c #define MMCST0_CRCWR BIT(5) /* data write CRC error */ BIT 89 drivers/mmc/host/davinci_mmc.c #define MMCST0_CRCRD BIT(6) /* data read CRC error */ BIT 90 drivers/mmc/host/davinci_mmc.c #define MMCST0_CRCRS BIT(7) /* command response CRC error */ BIT 91 drivers/mmc/host/davinci_mmc.c #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ BIT 92 drivers/mmc/host/davinci_mmc.c #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ BIT 93 drivers/mmc/host/davinci_mmc.c #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ BIT 94 drivers/mmc/host/davinci_mmc.c #define MMCST0_TRNDNE BIT(12) /* transfer done */ BIT 126 drivers/mmc/host/davinci_mmc.c #define SDIOST0_DAT1_HI BIT(0) BIT 129 drivers/mmc/host/davinci_mmc.c #define SDIOIEN_IOINTEN BIT(0) BIT 132 drivers/mmc/host/davinci_mmc.c #define SDIOIST_IOINT BIT(0) BIT 31 drivers/mmc/host/dw_mmc-exynos.h #define SDMMC_CLKSEL_WAKEUP_INT BIT(11) BIT 34 drivers/mmc/host/dw_mmc-exynos.h #define DATA_STROBE_EN BIT(0) BIT 35 drivers/mmc/host/dw_mmc-exynos.h #define AXI_NON_BLOCKING_WR BIT(7) BIT 49 drivers/mmc/host/dw_mmc-exynos.h #define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7) BIT 50 drivers/mmc/host/dw_mmc-exynos.h #define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6) BIT 51 drivers/mmc/host/dw_mmc-exynos.h #define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5) BIT 52 drivers/mmc/host/dw_mmc-exynos.h #define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) BIT 53 drivers/mmc/host/dw_mmc-exynos.h #define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3) BIT 54 drivers/mmc/host/dw_mmc-exynos.h #define SDMMC_MPSCTRL_ECB_MODE BIT(2) BIT 55 drivers/mmc/host/dw_mmc-exynos.h #define SDMMC_MPSCTRL_ENCRYPTION BIT(1) BIT 56 drivers/mmc/host/dw_mmc-exynos.h #define SDMMC_MPSCTRL_VALID BIT(0) BIT 26 drivers/mmc/host/dw_mmc-k3.c #define AO_SCTRL_SEL18 BIT(10) BIT 32 drivers/mmc/host/dw_mmc-k3.c #define SDCARD_IO_SEL18 BIT(2) BIT 38 drivers/mmc/host/dw_mmc-k3.c #define GPIO_CLK_ENABLE BIT(16) BIT 13 drivers/mmc/host/dw_mmc-zx.h #define DLL_REG_SET BIT(8) BIT 18 drivers/mmc/host/dw_mmc-zx.h #define PARA_DLL_BYPASS_MODE BIT(23) BIT 19 drivers/mmc/host/dw_mmc-zx.h #define PARA_HALF_CLK_MODE BIT(24) BIT 24 drivers/mmc/host/dw_mmc-zx.h #define READ_DQS_BYPASS_MODE BIT(7) BIT 27 drivers/mmc/host/dw_mmc-zx.h #define CLK_SAMP_BYPASS_MODE BIT(15) BIT 30 drivers/mmc/host/dw_mmc-zx.h #define ZX_DLL_LOCKED BIT(2) BIT 86 drivers/mmc/host/dw_mmc.c #define IDMAC_DES0_DIC BIT(1) BIT 87 drivers/mmc/host/dw_mmc.c #define IDMAC_DES0_LD BIT(2) BIT 88 drivers/mmc/host/dw_mmc.c #define IDMAC_DES0_FD BIT(3) BIT 89 drivers/mmc/host/dw_mmc.c #define IDMAC_DES0_CH BIT(4) BIT 90 drivers/mmc/host/dw_mmc.c #define IDMAC_DES0_ER BIT(5) BIT 91 drivers/mmc/host/dw_mmc.c #define IDMAC_DES0_CES BIT(30) BIT 92 drivers/mmc/host/dw_mmc.c #define IDMAC_DES0_OWN BIT(31) BIT 339 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_USE_IDMAC BIT(25) BIT 340 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_CEATA_INT_EN BIT(11) BIT 341 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) BIT 342 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_SEND_CCSD BIT(9) BIT 343 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) BIT 344 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) BIT 345 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_READ_WAIT BIT(6) BIT 346 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_DMA_ENABLE BIT(5) BIT 347 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_INT_ENABLE BIT(4) BIT 348 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_DMA_RESET BIT(2) BIT 349 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_FIFO_RESET BIT(1) BIT 350 drivers/mmc/host/dw_mmc.h #define SDMMC_CTRL_RESET BIT(0) BIT 352 drivers/mmc/host/dw_mmc.h #define SDMMC_CLKEN_LOW_PWR BIT(16) BIT 353 drivers/mmc/host/dw_mmc.h #define SDMMC_CLKEN_ENABLE BIT(0) BIT 360 drivers/mmc/host/dw_mmc.h #define SDMMC_CTYPE_8BIT BIT(16) BIT 361 drivers/mmc/host/dw_mmc.h #define SDMMC_CTYPE_4BIT BIT(0) BIT 364 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_SDIO(n) BIT(16 + (n)) BIT 365 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_EBE BIT(15) BIT 366 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_ACD BIT(14) BIT 367 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_SBE BIT(13) BIT 368 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_HLE BIT(12) BIT 369 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_FRUN BIT(11) BIT 370 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_HTO BIT(10) BIT 371 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ BIT 372 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_DRTO BIT(9) BIT 373 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_RTO BIT(8) BIT 374 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_DCRC BIT(7) BIT 375 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_RCRC BIT(6) BIT 376 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_RXDR BIT(5) BIT 377 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_TXDR BIT(4) BIT 378 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_DATA_OVER BIT(3) BIT 379 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_CMD_DONE BIT(2) BIT 380 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_RESP_ERR BIT(1) BIT 381 drivers/mmc/host/dw_mmc.h #define SDMMC_INT_CD BIT(0) BIT 384 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_START BIT(31) BIT 385 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_USE_HOLD_REG BIT(29) BIT 386 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_VOLT_SWITCH BIT(28) BIT 387 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_CCS_EXP BIT(23) BIT 388 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_CEATA_RD BIT(22) BIT 389 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_UPD_CLK BIT(21) BIT 390 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_INIT BIT(15) BIT 391 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_STOP BIT(14) BIT 392 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) BIT 393 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_SEND_STOP BIT(12) BIT 394 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_STRM_MODE BIT(11) BIT 395 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_DAT_WR BIT(10) BIT 396 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_DAT_EXP BIT(9) BIT 397 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_RESP_CRC BIT(8) BIT 398 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_RESP_LONG BIT(7) BIT 399 drivers/mmc/host/dw_mmc.h #define SDMMC_CMD_RESP_EXP BIT(6) BIT 403 drivers/mmc/host/dw_mmc.h #define SDMMC_STATUS_DMA_REQ BIT(31) BIT 404 drivers/mmc/host/dw_mmc.h #define SDMMC_STATUS_BUSY BIT(9) BIT 419 drivers/mmc/host/dw_mmc.h #define SDMMC_IDMAC_INT_AI BIT(9) BIT 420 drivers/mmc/host/dw_mmc.h #define SDMMC_IDMAC_INT_NI BIT(8) BIT 421 drivers/mmc/host/dw_mmc.h #define SDMMC_IDMAC_INT_CES BIT(5) BIT 422 drivers/mmc/host/dw_mmc.h #define SDMMC_IDMAC_INT_DU BIT(4) BIT 423 drivers/mmc/host/dw_mmc.h #define SDMMC_IDMAC_INT_FBE BIT(2) BIT 424 drivers/mmc/host/dw_mmc.h #define SDMMC_IDMAC_INT_RI BIT(1) BIT 425 drivers/mmc/host/dw_mmc.h #define SDMMC_IDMAC_INT_TI BIT(0) BIT 427 drivers/mmc/host/dw_mmc.h #define SDMMC_IDMAC_ENABLE BIT(7) BIT 428 drivers/mmc/host/dw_mmc.h #define SDMMC_IDMAC_FB BIT(1) BIT 429 drivers/mmc/host/dw_mmc.h #define SDMMC_IDMAC_SWRESET BIT(0) BIT 436 drivers/mmc/host/dw_mmc.h #define SDMMC_CARD_WR_THR_EN BIT(2) BIT 437 drivers/mmc/host/dw_mmc.h #define SDMMC_CARD_RD_THR_EN BIT(0) BIT 439 drivers/mmc/host/dw_mmc.h #define SDMMC_UHS_DDR BIT(16) BIT 440 drivers/mmc/host/dw_mmc.h #define SDMMC_UHS_18V BIT(0) BIT 442 drivers/mmc/host/dw_mmc.h #define SDMMC_DDR_HS400 BIT(31) BIT 444 drivers/mmc/host/dw_mmc.h #define SDMMC_ENABLE_PHASE BIT(0) BIT 46 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) BIT 47 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) BIT 48 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STRPCL_START_READWAIT BIT(5) BIT 49 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) BIT 50 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STRPCL_RESET BIT(3) BIT 51 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STRPCL_START_OP BIT(2) BIT 52 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) BIT 53 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) BIT 54 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STRPCL_CLOCK_START BIT(1) BIT 57 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_IS_RESETTING BIT(15) BIT 58 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) BIT 59 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_PRG_DONE BIT(13) BIT 60 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) BIT 61 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_END_CMD_RES BIT(11) BIT 62 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) BIT 63 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_IS_READWAIT BIT(9) BIT 64 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_CLK_EN BIT(8) BIT 65 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) BIT 66 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) BIT 67 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) BIT 68 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) BIT 69 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) BIT 70 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) BIT 71 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) BIT 72 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) BIT 74 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) BIT 75 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) BIT 78 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_CMDAT_IO_ABORT BIT(11) BIT 79 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) BIT 80 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_CMDAT_DMA_EN BIT(8) BIT 81 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_CMDAT_INIT BIT(7) BIT 82 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_CMDAT_BUSY BIT(6) BIT 83 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_CMDAT_STREAM BIT(5) BIT 84 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_CMDAT_WRITE BIT(4) BIT 85 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_CMDAT_DATA_EN BIT(3) BIT 86 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) BIT 91 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_IRQ_SDIO BIT(7) BIT 92 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) BIT 93 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) BIT 94 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_IRQ_END_CMD_RES BIT(2) BIT 95 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_IRQ_PRG_DONE BIT(1) BIT 96 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) BIT 98 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_DMAC_DMA_SEL BIT(1) BIT 99 drivers/mmc/host/jz4740_mmc.c #define JZ_MMC_DMAC_DMA_EN BIT(0) BIT 43 drivers/mmc/host/meson-gx-mmc.c #define CLK_V2_ALWAYS_ON BIT(24) BIT 47 drivers/mmc/host/meson-gx-mmc.c #define CLK_V3_ALWAYS_ON BIT(28) BIT 56 drivers/mmc/host/meson-gx-mmc.c #define ADJUST_DS_EN BIT(15) BIT 57 drivers/mmc/host/meson-gx-mmc.c #define ADJUST_ADJ_EN BIT(13) BIT 65 drivers/mmc/host/meson-gx-mmc.c #define START_DESC_INIT BIT(0) BIT 66 drivers/mmc/host/meson-gx-mmc.c #define START_DESC_BUSY BIT(1) BIT 74 drivers/mmc/host/meson-gx-mmc.c #define CFG_DDR BIT(2) BIT 78 drivers/mmc/host/meson-gx-mmc.c #define CFG_STOP_CLOCK BIT(22) BIT 79 drivers/mmc/host/meson-gx-mmc.c #define CFG_CLK_ALWAYS_ON BIT(18) BIT 80 drivers/mmc/host/meson-gx-mmc.c #define CFG_CHK_DS BIT(20) BIT 81 drivers/mmc/host/meson-gx-mmc.c #define CFG_AUTO_CLK BIT(23) BIT 82 drivers/mmc/host/meson-gx-mmc.c #define CFG_ERR_ABORT BIT(27) BIT 85 drivers/mmc/host/meson-gx-mmc.c #define STATUS_BUSY BIT(31) BIT 86 drivers/mmc/host/meson-gx-mmc.c #define STATUS_DESC_BUSY BIT(30) BIT 91 drivers/mmc/host/meson-gx-mmc.c #define IRQ_TXD_ERR BIT(8) BIT 92 drivers/mmc/host/meson-gx-mmc.c #define IRQ_DESC_ERR BIT(9) BIT 93 drivers/mmc/host/meson-gx-mmc.c #define IRQ_RESP_ERR BIT(10) BIT 96 drivers/mmc/host/meson-gx-mmc.c #define IRQ_RESP_TIMEOUT BIT(11) BIT 97 drivers/mmc/host/meson-gx-mmc.c #define IRQ_DESC_TIMEOUT BIT(12) BIT 100 drivers/mmc/host/meson-gx-mmc.c #define IRQ_END_OF_CHAIN BIT(13) BIT 101 drivers/mmc/host/meson-gx-mmc.c #define IRQ_RESP_STATUS BIT(14) BIT 102 drivers/mmc/host/meson-gx-mmc.c #define IRQ_SDIO BIT(15) BIT 129 drivers/mmc/host/meson-gx-mmc.c #define SD_EMMC_PRE_REQ_DONE BIT(0) BIT 130 drivers/mmc/host/meson-gx-mmc.c #define SD_EMMC_DESC_CHAIN_MODE BIT(1) BIT 179 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_BLOCK_MODE BIT(9) BIT 180 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_R1B BIT(10) BIT 181 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_END_OF_CHAIN BIT(11) BIT 183 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_NO_RESP BIT(16) BIT 184 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_NO_CMD BIT(17) BIT 185 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_DATA_IO BIT(18) BIT 186 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_DATA_WR BIT(19) BIT 187 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_RESP_NOCRC BIT(20) BIT 188 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_RESP_128 BIT(21) BIT 189 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_RESP_NUM BIT(22) BIT 190 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_DATA_NUM BIT(23) BIT 192 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_ERROR BIT(30) BIT 193 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_OWNER BIT(31) BIT 196 drivers/mmc/host/meson-gx-mmc.c #define CMD_DATA_BIG_ENDIAN BIT(1) BIT 197 drivers/mmc/host/meson-gx-mmc.c #define CMD_DATA_SRAM BIT(0) BIT 199 drivers/mmc/host/meson-gx-mmc.c #define CMD_RESP_SRAM BIT(0) BIT 35 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16) BIT 36 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17) BIT 37 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18) BIT 38 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19) BIT 39 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_SEND_DATA BIT(20) BIT 40 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21) BIT 46 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10) BIT 47 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11) BIT 49 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18) BIT 50 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19) BIT 51 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20) BIT 58 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4) BIT 59 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5) BIT 60 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6) BIT 61 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7) BIT 62 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQS_IF_INT BIT(8) BIT 63 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQS_CMD_INT BIT(9) BIT 65 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16) BIT 66 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17) BIT 67 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18) BIT 71 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3) BIT 72 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4) BIT 74 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8) BIT 75 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9) BIT 77 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15) BIT 78 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30) BIT 79 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31) BIT 83 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2) BIT 84 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3) BIT 85 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4) BIT 86 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5) BIT 87 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8) BIT 88 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10) BIT 89 drivers/mmc/host/meson-mx-sdio.c #define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11) BIT 221 drivers/mmc/host/meson-mx-sdio.c mult |= BIT(31); BIT 28 drivers/mmc/host/mmci.h #define MCI_STM32_VSWITCH BIT(2) BIT 29 drivers/mmc/host/mmci.h #define MCI_STM32_VSWITCHEN BIT(3) BIT 30 drivers/mmc/host/mmci.h #define MCI_STM32_DIRPOL BIT(4) BIT 50 drivers/mmc/host/mmci.h #define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11)) BIT 51 drivers/mmc/host/mmci.h #define MCI_QCOM_CLK_FLOWENA BIT(12) BIT 52 drivers/mmc/host/mmci.h #define MCI_QCOM_CLK_INVERTOUT BIT(13) BIT 55 drivers/mmc/host/mmci.h #define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15) BIT 56 drivers/mmc/host/mmci.h #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15)) BIT 60 drivers/mmc/host/mmci.h #define MCI_STM32_CLK_WIDEBUS_4 BIT(14) BIT 61 drivers/mmc/host/mmci.h #define MCI_STM32_CLK_WIDEBUS_8 BIT(15) BIT 62 drivers/mmc/host/mmci.h #define MCI_STM32_CLK_NEGEDGE BIT(16) BIT 63 drivers/mmc/host/mmci.h #define MCI_STM32_CLK_HWFCEN BIT(17) BIT 64 drivers/mmc/host/mmci.h #define MCI_STM32_CLK_DDR BIT(18) BIT 65 drivers/mmc/host/mmci.h #define MCI_STM32_CLK_BUSSPEED BIT(19) BIT 75 drivers/mmc/host/mmci.h #define MCI_CPSM_RESPONSE BIT(6) BIT 76 drivers/mmc/host/mmci.h #define MCI_CPSM_LONGRSP BIT(7) BIT 77 drivers/mmc/host/mmci.h #define MCI_CPSM_INTERRUPT BIT(8) BIT 78 drivers/mmc/host/mmci.h #define MCI_CPSM_PENDING BIT(9) BIT 79 drivers/mmc/host/mmci.h #define MCI_CPSM_ENABLE BIT(10) BIT 81 drivers/mmc/host/mmci.h #define MCI_CPSM_ST_SDIO_SUSP BIT(11) BIT 82 drivers/mmc/host/mmci.h #define MCI_CPSM_ST_ENCMD_COMPL BIT(12) BIT 83 drivers/mmc/host/mmci.h #define MCI_CPSM_ST_NIEN BIT(13) BIT 84 drivers/mmc/host/mmci.h #define MCI_CPSM_ST_CE_ATACMD BIT(14) BIT 86 drivers/mmc/host/mmci.h #define MCI_CPSM_QCOM_PROGENA BIT(11) BIT 87 drivers/mmc/host/mmci.h #define MCI_CPSM_QCOM_DATCMD BIT(12) BIT 88 drivers/mmc/host/mmci.h #define MCI_CPSM_QCOM_MCIABORT BIT(13) BIT 89 drivers/mmc/host/mmci.h #define MCI_CPSM_QCOM_CCSENABLE BIT(14) BIT 90 drivers/mmc/host/mmci.h #define MCI_CPSM_QCOM_CCSDISABLE BIT(15) BIT 91 drivers/mmc/host/mmci.h #define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16) BIT 92 drivers/mmc/host/mmci.h #define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21) BIT 94 drivers/mmc/host/mmci.h #define MCI_CPSM_STM32_CMDTRANS BIT(6) BIT 95 drivers/mmc/host/mmci.h #define MCI_CPSM_STM32_CMDSTOP BIT(7) BIT 101 drivers/mmc/host/mmci.h #define MCI_CPSM_STM32_ENABLE BIT(12) BIT 113 drivers/mmc/host/mmci.h #define MCI_DPSM_ENABLE BIT(0) BIT 114 drivers/mmc/host/mmci.h #define MCI_DPSM_DIRECTION BIT(1) BIT 115 drivers/mmc/host/mmci.h #define MCI_DPSM_MODE BIT(2) BIT 116 drivers/mmc/host/mmci.h #define MCI_DPSM_DMAENABLE BIT(3) BIT 117 drivers/mmc/host/mmci.h #define MCI_DPSM_BLOCKSIZE BIT(4) BIT 119 drivers/mmc/host/mmci.h #define MCI_DPSM_ST_RWSTART BIT(8) BIT 120 drivers/mmc/host/mmci.h #define MCI_DPSM_ST_RWSTOP BIT(9) BIT 121 drivers/mmc/host/mmci.h #define MCI_DPSM_ST_RWMOD BIT(10) BIT 122 drivers/mmc/host/mmci.h #define MCI_DPSM_ST_SDIOEN BIT(11) BIT 124 drivers/mmc/host/mmci.h #define MCI_DPSM_ST_DMAREQCTL BIT(12) BIT 125 drivers/mmc/host/mmci.h #define MCI_DPSM_ST_DBOOTMODEEN BIT(13) BIT 126 drivers/mmc/host/mmci.h #define MCI_DPSM_ST_BUSYMODE BIT(14) BIT 127 drivers/mmc/host/mmci.h #define MCI_DPSM_ST_DDRMODE BIT(15) BIT 129 drivers/mmc/host/mmci.h #define MCI_DPSM_QCOM_DATA_PEND BIT(17) BIT 130 drivers/mmc/host/mmci.h #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) BIT 166 drivers/mmc/host/mmci.h #define MCI_STM32_BUSYD0 BIT(20) BIT 213 drivers/mmc/host/mmci.h #define MCI_STM32_BUSYD0ENDMASK BIT(21) BIT 221 drivers/mmc/host/mmci.h #define MMCI_STM32_IDMAEN BIT(0) BIT 222 drivers/mmc/host/mmci.h #define MMCI_STM32_IDMALLIEN BIT(1) BIT 232 drivers/mmc/host/mmci.h #define MMCI_STM32_ABR BIT(29) BIT 233 drivers/mmc/host/mmci.h #define MMCI_STM32_ULS BIT(30) BIT 234 drivers/mmc/host/mmci.h #define MMCI_STM32_ULA BIT(31) BIT 17 drivers/mmc/host/mmci_qcom_dml.c #define PRODUCER_CRCI_X_SEL BIT(0) BIT 18 drivers/mmc/host/mmci_qcom_dml.c #define PRODUCER_CRCI_Y_SEL BIT(1) BIT 21 drivers/mmc/host/mmci_qcom_dml.c #define CONSUMER_CRCI_X_SEL BIT(2) BIT 22 drivers/mmc/host/mmci_qcom_dml.c #define CONSUMER_CRCI_Y_SEL BIT(3) BIT 23 drivers/mmc/host/mmci_qcom_dml.c #define PRODUCER_TRANS_END_EN BIT(4) BIT 24 drivers/mmc/host/mmci_qcom_dml.c #define BYPASS BIT(16) BIT 25 drivers/mmc/host/mmci_qcom_dml.c #define DIRECT_MODE BIT(17) BIT 26 drivers/mmc/host/mmci_qcom_dml.c #define INFINITE_CONS_TRANS BIT(18) BIT 15 drivers/mmc/host/mmci_stm32_sdmmc.c #define SDMMC_IDMA_BURST BIT(MMCI_STM32_IDMABNDT_SHIFT) BIT 57 drivers/mmc/host/moxart-mmc.c #define CMD_SDC_RESET BIT(10) BIT 58 drivers/mmc/host/moxart-mmc.c #define CMD_EN BIT(9) BIT 59 drivers/mmc/host/moxart-mmc.c #define CMD_APP_CMD BIT(8) BIT 60 drivers/mmc/host/moxart-mmc.c #define CMD_LONG_RSP BIT(7) BIT 61 drivers/mmc/host/moxart-mmc.c #define CMD_NEED_RSP BIT(6) BIT 65 drivers/mmc/host/moxart-mmc.c #define RSP_CMD_APP BIT(6) BIT 69 drivers/mmc/host/moxart-mmc.c #define DCR_DATA_FIFO_RESET BIT(8) BIT 70 drivers/mmc/host/moxart-mmc.c #define DCR_DATA_THRES BIT(7) BIT 71 drivers/mmc/host/moxart-mmc.c #define DCR_DATA_EN BIT(6) BIT 72 drivers/mmc/host/moxart-mmc.c #define DCR_DMA_EN BIT(5) BIT 73 drivers/mmc/host/moxart-mmc.c #define DCR_DATA_WRITE BIT(4) BIT 80 drivers/mmc/host/moxart-mmc.c #define WRITE_PROT BIT(12) BIT 81 drivers/mmc/host/moxart-mmc.c #define CARD_DETECT BIT(11) BIT 83 drivers/mmc/host/moxart-mmc.c #define CARD_CHANGE BIT(10) BIT 84 drivers/mmc/host/moxart-mmc.c #define FIFO_ORUN BIT(9) BIT 85 drivers/mmc/host/moxart-mmc.c #define FIFO_URUN BIT(8) BIT 86 drivers/mmc/host/moxart-mmc.c #define DATA_END BIT(7) BIT 87 drivers/mmc/host/moxart-mmc.c #define CMD_SENT BIT(6) BIT 88 drivers/mmc/host/moxart-mmc.c #define DATA_CRC_OK BIT(5) BIT 89 drivers/mmc/host/moxart-mmc.c #define RSP_CRC_OK BIT(4) BIT 90 drivers/mmc/host/moxart-mmc.c #define DATA_TIMEOUT BIT(3) BIT 91 drivers/mmc/host/moxart-mmc.c #define RSP_TIMEOUT BIT(2) BIT 92 drivers/mmc/host/moxart-mmc.c #define DATA_CRC_FAIL BIT(1) BIT 93 drivers/mmc/host/moxart-mmc.c #define RSP_CRC_FAIL BIT(0) BIT 104 drivers/mmc/host/moxart-mmc.c #define SD_POWER_ON BIT(4) BIT 108 drivers/mmc/host/moxart-mmc.c #define CLK_HISPD BIT(9) BIT 109 drivers/mmc/host/moxart-mmc.c #define CLK_OFF BIT(8) BIT 110 drivers/mmc/host/moxart-mmc.c #define CLK_SD BIT(7) BIT 114 drivers/mmc/host/moxart-mmc.c #define BUS_WIDTH_8 BIT(2) BIT 115 drivers/mmc/host/moxart-mmc.c #define BUS_WIDTH_4 BIT(1) BIT 116 drivers/mmc/host/moxart-mmc.c #define BUS_WIDTH_1 BIT(0) BIT 1363 drivers/mmc/host/mtk-sd.c return !(status & BIT(16)); BIT 1884 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); BIT 261 drivers/mmc/host/renesas_sdhi_core.c #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) BIT 266 drivers/mmc/host/renesas_sdhi_core.c #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) BIT 268 drivers/mmc/host/renesas_sdhi_core.c #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) BIT 270 drivers/mmc/host/renesas_sdhi_core.c #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) BIT 272 drivers/mmc/host/renesas_sdhi_core.c #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) BIT 273 drivers/mmc/host/renesas_sdhi_core.c #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) BIT 36 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ BIT 37 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) BIT 38 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ BIT 41 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define DTRAN_CTRL_DM_START BIT(0) BIT 44 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define RST_DTRANRST1 BIT(9) BIT 45 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define RST_DTRANRST0 BIT(8) BIT 51 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define INFO1_DTRANEND1 BIT(17) BIT 52 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define INFO1_DTRANEND0 BIT(16) BIT 56 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define INFO2_DTRANERR1 BIT(17) BIT 57 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define INFO2_DTRANERR0 BIT(16) BIT 304 drivers/mmc/host/renesas_sdhi_internal_dmac.c .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) }, BIT 306 drivers/mmc/host/renesas_sdhi_internal_dmac.c .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, BIT 308 drivers/mmc/host/renesas_sdhi_internal_dmac.c .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, BIT 41 drivers/mmc/host/sdhci-acpi.c SDHCI_ACPI_SD_CD = BIT(0), BIT 42 drivers/mmc/host/sdhci-acpi.c SDHCI_ACPI_RUNTIME_PM = BIT(1), BIT 43 drivers/mmc/host/sdhci-acpi.c SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2), BIT 88 drivers/mmc/host/sdhci-acpi.c #define INTEL_DSM_HS_CAPS_SDR25 BIT(0) BIT 89 drivers/mmc/host/sdhci-acpi.c #define INTEL_DSM_HS_CAPS_DDR50 BIT(1) BIT 90 drivers/mmc/host/sdhci-acpi.c #define INTEL_DSM_HS_CAPS_SDR50 BIT(2) BIT 91 drivers/mmc/host/sdhci-acpi.c #define INTEL_DSM_HS_CAPS_SDR104 BIT(3) BIT 20 drivers/mmc/host/sdhci-cadence.c #define SDHCI_CDNS_HRS04_ACK BIT(26) BIT 21 drivers/mmc/host/sdhci-cadence.c #define SDHCI_CDNS_HRS04_RD BIT(25) BIT 22 drivers/mmc/host/sdhci-cadence.c #define SDHCI_CDNS_HRS04_WR BIT(24) BIT 28 drivers/mmc/host/sdhci-cadence.c #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) BIT 127 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) BIT 132 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_USDHC BIT(3) BIT 134 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_MAN_TUNING BIT(4) BIT 136 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_STD_TUNING BIT(5) BIT 138 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_HAVE_CAP1 BIT(6) BIT 146 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_ERR004536 BIT(7) BIT 148 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_HS200 BIT(8) BIT 150 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_HS400 BIT(9) BIT 156 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_ERR010450 BIT(10) BIT 158 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_HS400_ES BIT(11) BIT 160 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_CQHCI BIT(12) BIT 162 drivers/mmc/host/sdhci-esdhc-imx.c #define ESDHC_FLAG_PMQOS BIT(13) BIT 766 drivers/mmc/host/sdhci-esdhc-imx.c writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); BIT 769 drivers/mmc/host/sdhci-esdhc-imx.c if (temp & BIT(10)) BIT 1195 drivers/mmc/host/sdhci-esdhc-imx.c writel(readl(host->ioaddr + 0x6c) & ~BIT(7), BIT 25 drivers/mmc/host/sdhci-msm.c #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29) BIT 29 drivers/mmc/host/sdhci-msm.c #define CORE_SW_RST BIT(7) BIT 30 drivers/mmc/host/sdhci-msm.c #define FF_CLK_SW_RST_DIS BIT(13) BIT 32 drivers/mmc/host/sdhci-msm.c #define CORE_PWRCTL_BUS_OFF BIT(0) BIT 33 drivers/mmc/host/sdhci-msm.c #define CORE_PWRCTL_BUS_ON BIT(1) BIT 34 drivers/mmc/host/sdhci-msm.c #define CORE_PWRCTL_IO_LOW BIT(2) BIT 35 drivers/mmc/host/sdhci-msm.c #define CORE_PWRCTL_IO_HIGH BIT(3) BIT 36 drivers/mmc/host/sdhci-msm.c #define CORE_PWRCTL_BUS_SUCCESS BIT(0) BIT 37 drivers/mmc/host/sdhci-msm.c #define CORE_PWRCTL_IO_SUCCESS BIT(2) BIT 38 drivers/mmc/host/sdhci-msm.c #define REQ_BUS_OFF BIT(0) BIT 39 drivers/mmc/host/sdhci-msm.c #define REQ_BUS_ON BIT(1) BIT 40 drivers/mmc/host/sdhci-msm.c #define REQ_IO_LOW BIT(2) BIT 41 drivers/mmc/host/sdhci-msm.c #define REQ_IO_HIGH BIT(3) BIT 44 drivers/mmc/host/sdhci-msm.c #define CORE_DLL_LOCK BIT(7) BIT 45 drivers/mmc/host/sdhci-msm.c #define CORE_DDR_DLL_LOCK BIT(11) BIT 46 drivers/mmc/host/sdhci-msm.c #define CORE_DLL_EN BIT(16) BIT 47 drivers/mmc/host/sdhci-msm.c #define CORE_CDR_EN BIT(17) BIT 48 drivers/mmc/host/sdhci-msm.c #define CORE_CK_OUT_EN BIT(18) BIT 49 drivers/mmc/host/sdhci-msm.c #define CORE_CDR_EXT_EN BIT(19) BIT 50 drivers/mmc/host/sdhci-msm.c #define CORE_DLL_PDN BIT(29) BIT 51 drivers/mmc/host/sdhci-msm.c #define CORE_DLL_RST BIT(30) BIT 52 drivers/mmc/host/sdhci-msm.c #define CORE_CMD_DAT_TRACK_SEL BIT(0) BIT 54 drivers/mmc/host/sdhci-msm.c #define CORE_DDR_CAL_EN BIT(0) BIT 55 drivers/mmc/host/sdhci-msm.c #define CORE_FLL_CYCLE_CNT BIT(18) BIT 56 drivers/mmc/host/sdhci-msm.c #define CORE_DLL_CLOCK_DISABLE BIT(21) BIT 59 drivers/mmc/host/sdhci-msm.c #define CORE_CLK_PWRSAVE BIT(1) BIT 65 drivers/mmc/host/sdhci-msm.c #define CORE_HC_SELECT_IN_EN BIT(18) BIT 74 drivers/mmc/host/sdhci-msm.c #define CORE_SW_TRIG_FULL_CALIB BIT(16) BIT 75 drivers/mmc/host/sdhci-msm.c #define CORE_HW_AUTOCAL_ENA BIT(17) BIT 79 drivers/mmc/host/sdhci-msm.c #define CORE_TIMER_ENA BIT(16) BIT 88 drivers/mmc/host/sdhci-msm.c #define CORE_CALIBRATION_DONE BIT(0) BIT 93 drivers/mmc/host/sdhci-msm.c #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0) BIT 94 drivers/mmc/host/sdhci-msm.c #define CORE_CDC_SWITCH_RC_EN BIT(1) BIT 96 drivers/mmc/host/sdhci-msm.c #define CORE_CDC_T4_DLY_SEL BIT(0) BIT 97 drivers/mmc/host/sdhci-msm.c #define CORE_CMDIN_RCLK_EN BIT(1) BIT 98 drivers/mmc/host/sdhci-msm.c #define CORE_START_CDC_TRAFFIC BIT(6) BIT 100 drivers/mmc/host/sdhci-msm.c #define CORE_PWRSAVE_DLL BIT(3) BIT 31 drivers/mmc/host/sdhci-of-arasan.c #define VENDOR_ENHANCED_STROBE BIT(0) BIT 100 drivers/mmc/host/sdhci-of-arasan.c #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) BIT 103 drivers/mmc/host/sdhci-of-arasan.c #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) BIT 20 drivers/mmc/host/sdhci-of-aspeed.c #define ASPEED_SDC_S1MMC8 BIT(25) BIT 21 drivers/mmc/host/sdhci-of-aspeed.c #define ASPEED_SDC_S0MMC8 BIT(24) BIT 25 drivers/mmc/host/sdhci-of-at91.c #define SDMMC_MC1R_DDR BIT(3) BIT 26 drivers/mmc/host/sdhci-of-at91.c #define SDMMC_MC1R_FCD BIT(7) BIT 28 drivers/mmc/host/sdhci-of-at91.c #define SDMMC_CACR_CAPWREN BIT(0) BIT 24 drivers/mmc/host/sdhci-omap.c #define CON_DW8 BIT(5) BIT 25 drivers/mmc/host/sdhci-omap.c #define CON_DMA_MASTER BIT(20) BIT 26 drivers/mmc/host/sdhci-omap.c #define CON_DDR BIT(19) BIT 27 drivers/mmc/host/sdhci-omap.c #define CON_CLKEXTFREE BIT(16) BIT 28 drivers/mmc/host/sdhci-omap.c #define CON_PADEN BIT(15) BIT 29 drivers/mmc/host/sdhci-omap.c #define CON_CTPL BIT(11) BIT 30 drivers/mmc/host/sdhci-omap.c #define CON_INIT BIT(1) BIT 31 drivers/mmc/host/sdhci-omap.c #define CON_OD BIT(0) BIT 34 drivers/mmc/host/sdhci-omap.c #define DLL_SWT BIT(20) BIT 37 drivers/mmc/host/sdhci-omap.c #define DLL_FORCE_VALUE BIT(12) BIT 38 drivers/mmc/host/sdhci-omap.c #define DLL_CALIB BIT(1) BIT 43 drivers/mmc/host/sdhci-omap.c #define PSTATE_DLEV_DAT0 BIT(20) BIT 44 drivers/mmc/host/sdhci-omap.c #define PSTATE_DATI BIT(1) BIT 47 drivers/mmc/host/sdhci-omap.c #define HCTL_SDBP BIT(8) BIT 55 drivers/mmc/host/sdhci-omap.c #define SYSCTL_CEN BIT(2) BIT 62 drivers/mmc/host/sdhci-omap.c #define INT_CC_EN BIT(0) BIT 65 drivers/mmc/host/sdhci-omap.c #define AC12_V1V8_SIGEN BIT(19) BIT 66 drivers/mmc/host/sdhci-omap.c #define AC12_SCLK_SEL BIT(23) BIT 69 drivers/mmc/host/sdhci-omap.c #define CAPA_VS33 BIT(24) BIT 70 drivers/mmc/host/sdhci-omap.c #define CAPA_VS30 BIT(25) BIT 71 drivers/mmc/host/sdhci-omap.c #define CAPA_VS18 BIT(26) BIT 74 drivers/mmc/host/sdhci-omap.c #define CAPA2_TSDR50 BIT(13) BIT 87 drivers/mmc/host/sdhci-omap.c #define SDHCI_OMAP_REQUIRE_IODELAY BIT(0) BIT 21 drivers/mmc/host/sdhci-pci-arasan.c #define PHY_WRITE BIT(8) BIT 22 drivers/mmc/host/sdhci-pci-arasan.c #define PHY_BUSY BIT(9) BIT 46 drivers/mmc/host/sdhci-pci-arasan.c #define DLL_ENBL BIT(3) BIT 47 drivers/mmc/host/sdhci-pci-arasan.c #define RTRIM_EN BIT(1) BIT 48 drivers/mmc/host/sdhci-pci-arasan.c #define PDB_ENBL BIT(1) BIT 49 drivers/mmc/host/sdhci-pci-arasan.c #define RETB_ENBL BIT(6) BIT 50 drivers/mmc/host/sdhci-pci-arasan.c #define ODEN_CMD BIT(1) BIT 52 drivers/mmc/host/sdhci-pci-arasan.c #define REN_STRB BIT(0) BIT 53 drivers/mmc/host/sdhci-pci-arasan.c #define REN_CMND BIT(1) BIT 55 drivers/mmc/host/sdhci-pci-arasan.c #define PU_CMD BIT(1) BIT 57 drivers/mmc/host/sdhci-pci-arasan.c #define ITAPDLY_EN BIT(0) BIT 58 drivers/mmc/host/sdhci-pci-arasan.c #define OTAPDLY_EN BIT(0) BIT 59 drivers/mmc/host/sdhci-pci-arasan.c #define OD_REL_CMD BIT(1) BIT 62 drivers/mmc/host/sdhci-pci-arasan.c #define PDB_CMND BIT(0) BIT 64 drivers/mmc/host/sdhci-pci-arasan.c #define PDB_STRB BIT(0) BIT 65 drivers/mmc/host/sdhci-pci-arasan.c #define PDB_CLOCK BIT(0) BIT 71 drivers/mmc/host/sdhci-pci-arasan.c #define ENHSTRB_MODE BIT(0) BIT 72 drivers/mmc/host/sdhci-pci-arasan.c #define HS400_MODE BIT(1) BIT 73 drivers/mmc/host/sdhci-pci-arasan.c #define LEGACY_MODE BIT(2) BIT 74 drivers/mmc/host/sdhci-pci-arasan.c #define DDR50_MODE BIT(3) BIT 80 drivers/mmc/host/sdhci-pci-arasan.c #define HS200_MODE BIT(4) BIT 81 drivers/mmc/host/sdhci-pci-arasan.c #define HISPD_MODE BIT(5) BIT 661 drivers/mmc/host/sdhci-pci-core.c #define INTEL_HS400_ES_BIT BIT(0) BIT 1960 drivers/mmc/host/sdhci-pci-core.c ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); BIT 20 drivers/mmc/host/sdhci-pci-gli.c #define SDHCI_GLI_9750_WT_EN BIT(0) BIT 29 drivers/mmc/host/sdhci-pci-gli.c #define SDHCI_GLI_9750_SEL_1 BIT(29) BIT 30 drivers/mmc/host/sdhci-pci-gli.c #define SDHCI_GLI_9750_SEL_2 BIT(31) BIT 31 drivers/mmc/host/sdhci-pci-gli.c #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) BIT 34 drivers/mmc/host/sdhci-pci-gli.c #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) BIT 44 drivers/mmc/host/sdhci-pci-gli.c #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) BIT 45 drivers/mmc/host/sdhci-pci-gli.c #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) BIT 54 drivers/mmc/host/sdhci-pci-gli.c #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) BIT 57 drivers/mmc/host/sdhci-pci-gli.c #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) BIT 47 drivers/mmc/host/sdhci-pci-o2micro.c #define O2_SD_LED_ENABLE BIT(6) BIT 48 drivers/mmc/host/sdhci-pci-o2micro.c #define O2_SD_FREG0_LEDOFF BIT(13) BIT 49 drivers/mmc/host/sdhci-pci-o2micro.c #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) BIT 53 drivers/mmc/host/sdhci-pci-o2micro.c #define O2_SD_HW_TUNING_DISABLE BIT(4) BIT 56 drivers/mmc/host/sdhci-pci-o2micro.c #define O2_PLL_FORCE_ACTIVE BIT(18) BIT 57 drivers/mmc/host/sdhci-pci-o2micro.c #define O2_PLL_LOCK_STATUS BIT(14) BIT 58 drivers/mmc/host/sdhci-pci-o2micro.c #define O2_PLL_SOFT_RESET BIT(12) BIT 59 drivers/mmc/host/sdhci-pci-o2micro.c #define O2_DLL_LOCK_STATUS BIT(11) BIT 69 drivers/mmc/host/sdhci-pxav3.c #define SDIO3_CONF_CLK_INV BIT(0) BIT 70 drivers/mmc/host/sdhci-pxav3.c #define SDIO3_CONF_SD_FB_CLK BIT(2) BIT 37 drivers/mmc/host/sdhci-s3c.c #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31) BIT 38 drivers/mmc/host/sdhci-s3c.c #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30) BIT 39 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29) BIT 40 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28) BIT 50 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15) BIT 51 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14) BIT 52 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_SDCDSEL BIT(13) BIT 53 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_SDSIGPC BIT(12) BIT 54 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11) BIT 63 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8) BIT 64 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_RWAITMODE BIT(7) BIT 65 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_DISBUFRD BIT(6) BIT 69 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_PWRSYNC BIT(3) BIT 70 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1) BIT 71 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL2_HWINITFIN BIT(0) BIT 73 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL3_FCSEL3 BIT(31) BIT 74 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL3_FCSEL2 BIT(23) BIT 75 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL3_FCSEL1 BIT(15) BIT 76 drivers/mmc/host/sdhci-s3c.c #define S3C_SDHCI_CTRL3_FCSEL0 BIT(7) BIT 17 drivers/mmc/host/sdhci-sirf.c #define SDHCI_SIRF_8BITBUS BIT(3) BIT 27 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) BIT 28 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_DLL_EN BIT(21) BIT 29 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) BIT 36 drivers/mmc/host/sdhci-sprd.c #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) BIT 37 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) BIT 38 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) BIT 39 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) BIT 42 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) BIT 43 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) BIT 46 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) BIT 47 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) BIT 63 drivers/mmc/host/sdhci-sprd.c #define SDHCI_HW_RESET_CARD BIT(3) BIT 29 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT BIT(24) BIT 30 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ BIT(12) BIT 31 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT BIT(8) BIT 32 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_ASYNC_WAKEUP BIT(0) BIT 39 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_HIGH_SPEED BIT(28) BIT 40 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_ADMA2 BIT(24) BIT 41 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_8BIT BIT(20) BIT 54 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_EMMC_SLOT_TYPE BIT(28) BIT 55 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_64BIT BIT(24) BIT 56 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT BIT(20) BIT 57 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_1P8_VOLT BIT(16) BIT 58 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_3P0_VOLT BIT(12) BIT 59 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_3P3_VOLT BIT(8) BIT 60 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_SUSP_RES_SUPPORT BIT(4) BIT 61 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_SDMA BIT(0) BIT 69 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_D_DRIVER BIT(20) BIT 70 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_C_DRIVER BIT(16) BIT 71 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_A_DRIVER BIT(12) BIT 72 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_DDR50 BIT(8) BIT 73 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_SDR104 BIT(4) BIT 74 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_SDR50 BIT(0) BIT 78 drivers/mmc/host/sdhci-st.c #define ST_MMC_CCONFIG_TUNING_FOR_SDR50 BIT(8) BIT 84 drivers/mmc/host/sdhci-st.c #define ST_MMC_GP_OUTPUT_CD BIT(12) BIT 95 drivers/mmc/host/sdhci-st.c #define ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_CMD BIT(0) BIT 96 drivers/mmc/host/sdhci-st.c #define ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_PH_SEL BIT(1) BIT 97 drivers/mmc/host/sdhci-st.c #define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE BIT(8) BIT 98 drivers/mmc/host/sdhci-st.c #define ST_TOP_MMC_DLY_CTRL_RX_DLL_ENABLE BIT(9) BIT 99 drivers/mmc/host/sdhci-st.c #define ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY BIT(10) BIT 100 drivers/mmc/host/sdhci-st.c #define ST_TOP_MMC_START_DLL_LOCK BIT(11) BIT 36 drivers/mmc/host/sdhci-tegra.c #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) BIT 37 drivers/mmc/host/sdhci-tegra.c #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) BIT 38 drivers/mmc/host/sdhci-tegra.c #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) BIT 41 drivers/mmc/host/sdhci-tegra.c #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) BIT 54 drivers/mmc/host/sdhci-tegra.c #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) BIT 57 drivers/mmc/host/sdhci-tegra.c #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) BIT 79 drivers/mmc/host/sdhci-tegra.c #define SDHCI_AUTO_CAL_START BIT(31) BIT 80 drivers/mmc/host/sdhci-tegra.c #define SDHCI_AUTO_CAL_ENABLE BIT(29) BIT 86 drivers/mmc/host/sdhci-tegra.c #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) BIT 90 drivers/mmc/host/sdhci-tegra.c #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) BIT 92 drivers/mmc/host/sdhci-tegra.c #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) BIT 93 drivers/mmc/host/sdhci-tegra.c #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) BIT 94 drivers/mmc/host/sdhci-tegra.c #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) BIT 95 drivers/mmc/host/sdhci-tegra.c #define NVQUIRK_ENABLE_SDR50 BIT(3) BIT 96 drivers/mmc/host/sdhci-tegra.c #define NVQUIRK_ENABLE_SDR104 BIT(4) BIT 97 drivers/mmc/host/sdhci-tegra.c #define NVQUIRK_ENABLE_DDR50 BIT(5) BIT 98 drivers/mmc/host/sdhci-tegra.c #define NVQUIRK_HAS_PADCALIB BIT(6) BIT 99 drivers/mmc/host/sdhci-tegra.c #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) BIT 100 drivers/mmc/host/sdhci-tegra.c #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) BIT 101 drivers/mmc/host/sdhci-tegra.c #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9) BIT 26 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_TIMING_ADJUST_SLOW_MODE BIT(29) BIT 27 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_TIMING_ADJUST_SDIO_MODE BIT(28) BIT 28 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18) BIT 30 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_PHY_INITIALIZAION BIT(31) BIT 43 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_ASYNC_DDRMODE_MASK BIT(23) BIT 45 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_CMD_DDR_MODE BIT(16) BIT 48 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_DQ_ASYNC_MODE BIT(4) BIT 55 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_FC_DQ_RECEN BIT(24) BIT 56 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_FC_CMD_RECEN BIT(25) BIT 57 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_FC_QSP_RECEN BIT(26) BIT 58 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_FC_QSN_RECEN BIT(27) BIT 59 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_OEN_QSN BIT(28) BIT 60 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_AUTO_RECEN_CTRL BIT(30) BIT 63 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_EMMC5_FC_QSP_PD BIT(18) BIT 64 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_EMMC5_FC_QSP_PU BIT(22) BIT 65 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_EMMC5_FC_CMD_PD BIT(17) BIT 66 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_EMMC5_FC_CMD_PU BIT(21) BIT 67 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_EMMC5_FC_DQ_PD BIT(16) BIT 68 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_EMMC5_FC_DQ_PU BIT(20) BIT 71 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_EMMC5_1_FC_QSP_PD BIT(9) BIT 72 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_EMMC5_1_FC_QSP_PU BIT(25) BIT 73 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_EMMC5_1_FC_CMD_PD BIT(8) BIT 74 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_EMMC5_1_FC_CMD_PU BIT(24) BIT 94 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_DLL_ENABLE BIT(31) BIT 95 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_DLL_UPDATE_STROBE_5_0 BIT(30) BIT 96 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_DLL_REFCLK_SEL BIT(30) BIT 97 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_DLL_UPDATE BIT(23) BIT 102 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_DLL_FAST_LOCK BIT(5) BIT 103 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_DLL_GAIN2X BIT(3) BIT 104 drivers/mmc/host/sdhci-xenon-phy.c #define XENON_DLL_BYPASS_EN BIT(0) BIT 88 drivers/mmc/host/sdhci-xenon.c reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT); BIT 106 drivers/mmc/host/sdhci-xenon.c reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT); BIT 117 drivers/mmc/host/sdhci-xenon.c reg |= BIT(sdhc_id); BIT 17 drivers/mmc/host/sdhci-xenon.h #define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20) BIT 22 drivers/mmc/host/sdhci-xenon.h #define XENON_MASK_CMD_CONFLICT_ERR BIT(8) BIT 30 drivers/mmc/host/sdhci-xenon.h #define XENON_TUNING_STEP_DIVIDER BIT(6) BIT 33 drivers/mmc/host/sdhci-xenon.h #define XENON_ENABLE_RESP_STROBE BIT(25) BIT 34 drivers/mmc/host/sdhci-xenon.h #define XENON_ENABLE_DATA_STROBE BIT(24) BIT 21 drivers/mmc/host/sdhci_am654.c #define SLOTTYPE_EMBEDDED BIT(30) BIT 34 drivers/mmc/host/sdhci_am654.c #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) BIT 36 drivers/mmc/host/sdhci_am654.c #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) BIT 43 drivers/mmc/host/sdhci_am654.c #define SEL50_MASK BIT(SEL50_SHIFT) BIT 45 drivers/mmc/host/sdhci_am654.c #define SEL100_MASK BIT(SEL100_SHIFT) BIT 53 drivers/mmc/host/sdhci_am654.c #define ENDLL_MASK BIT(ENDLL_SHIFT) BIT 55 drivers/mmc/host/sdhci_am654.c #define DLLRDY_MASK BIT(DLLRDY_SHIFT) BIT 57 drivers/mmc/host/sdhci_am654.c #define PDB_MASK BIT(PDB_SHIFT) BIT 59 drivers/mmc/host/sdhci_am654.c #define CALDONE_MASK BIT(CALDONE_SHIFT) BIT 61 drivers/mmc/host/sdhci_am654.c #define RETRIM_MASK BIT(RETRIM_SHIFT) BIT 82 drivers/mmc/host/sunxi-mmc.c #define SDXC_SOFT_RESET BIT(0) BIT 83 drivers/mmc/host/sunxi-mmc.c #define SDXC_FIFO_RESET BIT(1) BIT 84 drivers/mmc/host/sunxi-mmc.c #define SDXC_DMA_RESET BIT(2) BIT 85 drivers/mmc/host/sunxi-mmc.c #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) BIT 86 drivers/mmc/host/sunxi-mmc.c #define SDXC_DMA_ENABLE_BIT BIT(5) BIT 87 drivers/mmc/host/sunxi-mmc.c #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) BIT 88 drivers/mmc/host/sunxi-mmc.c #define SDXC_POSEDGE_LATCH_DATA BIT(9) BIT 89 drivers/mmc/host/sunxi-mmc.c #define SDXC_DDR_MODE BIT(10) BIT 90 drivers/mmc/host/sunxi-mmc.c #define SDXC_MEMORY_ACCESS_DONE BIT(29) BIT 91 drivers/mmc/host/sunxi-mmc.c #define SDXC_ACCESS_DONE_DIRECT BIT(30) BIT 92 drivers/mmc/host/sunxi-mmc.c #define SDXC_ACCESS_BY_AHB BIT(31) BIT 98 drivers/mmc/host/sunxi-mmc.c #define SDXC_MASK_DATA0 BIT(31) BIT 99 drivers/mmc/host/sunxi-mmc.c #define SDXC_CARD_CLOCK_ON BIT(16) BIT 100 drivers/mmc/host/sunxi-mmc.c #define SDXC_LOW_POWER_ON BIT(17) BIT 108 drivers/mmc/host/sunxi-mmc.c #define SDXC_RESP_EXPIRE BIT(6) BIT 109 drivers/mmc/host/sunxi-mmc.c #define SDXC_LONG_RESPONSE BIT(7) BIT 110 drivers/mmc/host/sunxi-mmc.c #define SDXC_CHECK_RESPONSE_CRC BIT(8) BIT 111 drivers/mmc/host/sunxi-mmc.c #define SDXC_DATA_EXPIRE BIT(9) BIT 112 drivers/mmc/host/sunxi-mmc.c #define SDXC_WRITE BIT(10) BIT 113 drivers/mmc/host/sunxi-mmc.c #define SDXC_SEQUENCE_MODE BIT(11) BIT 114 drivers/mmc/host/sunxi-mmc.c #define SDXC_SEND_AUTO_STOP BIT(12) BIT 115 drivers/mmc/host/sunxi-mmc.c #define SDXC_WAIT_PRE_OVER BIT(13) BIT 116 drivers/mmc/host/sunxi-mmc.c #define SDXC_STOP_ABORT_CMD BIT(14) BIT 117 drivers/mmc/host/sunxi-mmc.c #define SDXC_SEND_INIT_SEQUENCE BIT(15) BIT 118 drivers/mmc/host/sunxi-mmc.c #define SDXC_UPCLK_ONLY BIT(21) BIT 119 drivers/mmc/host/sunxi-mmc.c #define SDXC_READ_CEATA_DEV BIT(22) BIT 120 drivers/mmc/host/sunxi-mmc.c #define SDXC_CCS_EXPIRE BIT(23) BIT 121 drivers/mmc/host/sunxi-mmc.c #define SDXC_ENABLE_BIT_BOOT BIT(24) BIT 122 drivers/mmc/host/sunxi-mmc.c #define SDXC_ALT_BOOT_OPTIONS BIT(25) BIT 123 drivers/mmc/host/sunxi-mmc.c #define SDXC_BOOT_ACK_EXPIRE BIT(26) BIT 124 drivers/mmc/host/sunxi-mmc.c #define SDXC_BOOT_ABORT BIT(27) BIT 125 drivers/mmc/host/sunxi-mmc.c #define SDXC_VOLTAGE_SWITCH BIT(28) BIT 126 drivers/mmc/host/sunxi-mmc.c #define SDXC_USE_HOLD_REGISTER BIT(29) BIT 127 drivers/mmc/host/sunxi-mmc.c #define SDXC_START BIT(31) BIT 130 drivers/mmc/host/sunxi-mmc.c #define SDXC_RESP_ERROR BIT(1) BIT 131 drivers/mmc/host/sunxi-mmc.c #define SDXC_COMMAND_DONE BIT(2) BIT 132 drivers/mmc/host/sunxi-mmc.c #define SDXC_DATA_OVER BIT(3) BIT 133 drivers/mmc/host/sunxi-mmc.c #define SDXC_TX_DATA_REQUEST BIT(4) BIT 134 drivers/mmc/host/sunxi-mmc.c #define SDXC_RX_DATA_REQUEST BIT(5) BIT 135 drivers/mmc/host/sunxi-mmc.c #define SDXC_RESP_CRC_ERROR BIT(6) BIT 136 drivers/mmc/host/sunxi-mmc.c #define SDXC_DATA_CRC_ERROR BIT(7) BIT 137 drivers/mmc/host/sunxi-mmc.c #define SDXC_RESP_TIMEOUT BIT(8) BIT 138 drivers/mmc/host/sunxi-mmc.c #define SDXC_DATA_TIMEOUT BIT(9) BIT 139 drivers/mmc/host/sunxi-mmc.c #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) BIT 140 drivers/mmc/host/sunxi-mmc.c #define SDXC_FIFO_RUN_ERROR BIT(11) BIT 141 drivers/mmc/host/sunxi-mmc.c #define SDXC_HARD_WARE_LOCKED BIT(12) BIT 142 drivers/mmc/host/sunxi-mmc.c #define SDXC_START_BIT_ERROR BIT(13) BIT 143 drivers/mmc/host/sunxi-mmc.c #define SDXC_AUTO_COMMAND_DONE BIT(14) BIT 144 drivers/mmc/host/sunxi-mmc.c #define SDXC_END_BIT_ERROR BIT(15) BIT 145 drivers/mmc/host/sunxi-mmc.c #define SDXC_SDIO_INTERRUPT BIT(16) BIT 146 drivers/mmc/host/sunxi-mmc.c #define SDXC_CARD_INSERT BIT(30) BIT 147 drivers/mmc/host/sunxi-mmc.c #define SDXC_CARD_REMOVE BIT(31) BIT 157 drivers/mmc/host/sunxi-mmc.c #define SDXC_RXWL_FLAG BIT(0) BIT 158 drivers/mmc/host/sunxi-mmc.c #define SDXC_TXWL_FLAG BIT(1) BIT 159 drivers/mmc/host/sunxi-mmc.c #define SDXC_FIFO_EMPTY BIT(2) BIT 160 drivers/mmc/host/sunxi-mmc.c #define SDXC_FIFO_FULL BIT(3) BIT 161 drivers/mmc/host/sunxi-mmc.c #define SDXC_CARD_PRESENT BIT(8) BIT 162 drivers/mmc/host/sunxi-mmc.c #define SDXC_CARD_DATA_BUSY BIT(9) BIT 163 drivers/mmc/host/sunxi-mmc.c #define SDXC_DATA_FSM_BUSY BIT(10) BIT 164 drivers/mmc/host/sunxi-mmc.c #define SDXC_DMA_REQUEST BIT(31) BIT 169 drivers/mmc/host/sunxi-mmc.c #define SDXC_SEND_IRQ_RESPONSE BIT(0) BIT 170 drivers/mmc/host/sunxi-mmc.c #define SDXC_SDIO_READ_WAIT BIT(1) BIT 171 drivers/mmc/host/sunxi-mmc.c #define SDXC_ABORT_READ_DATA BIT(2) BIT 172 drivers/mmc/host/sunxi-mmc.c #define SDXC_SEND_CCSD BIT(8) BIT 173 drivers/mmc/host/sunxi-mmc.c #define SDXC_SEND_AUTO_STOPCCSD BIT(9) BIT 174 drivers/mmc/host/sunxi-mmc.c #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) BIT 177 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_SOFT_RESET BIT(0) BIT 178 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_FIX_BURST BIT(1) BIT 179 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_IDMA_ON BIT(7) BIT 180 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_REFETCH_DES BIT(31) BIT 183 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) BIT 184 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) BIT 185 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) BIT 186 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) BIT 187 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) BIT 188 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) BIT 189 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) BIT 190 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) BIT 208 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ BIT 209 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ BIT 210 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ BIT 211 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ BIT 212 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ BIT 213 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ BIT 214 drivers/mmc/host/sunxi-mmc.c #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ BIT 222 drivers/mmc/host/sunxi-mmc.c #define SDXC_2X_TIMING_MODE BIT(31) BIT 224 drivers/mmc/host/sunxi-mmc.c #define SDXC_CAL_START BIT(15) BIT 225 drivers/mmc/host/sunxi-mmc.c #define SDXC_CAL_DONE BIT(14) BIT 227 drivers/mmc/host/sunxi-mmc.c #define SDXC_CAL_DL_SW_EN BIT(7) BIT 48 drivers/mmc/host/tmio_mmc.h #define TMIO_STOP_STP BIT(0) BIT 49 drivers/mmc/host/tmio_mmc.h #define TMIO_STOP_SEC BIT(8) BIT 52 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_CMDRESPEND BIT(0) BIT 53 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_DATAEND BIT(2) BIT 54 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_CARD_REMOVE BIT(3) BIT 55 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_CARD_INSERT BIT(4) BIT 56 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_SIGSTATE BIT(5) BIT 57 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_WRPROTECT BIT(7) BIT 58 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_CARD_REMOVE_A BIT(8) BIT 59 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_CARD_INSERT_A BIT(9) BIT 60 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_SIGSTATE_A BIT(10) BIT 63 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_CMD_IDX_ERR BIT(16) BIT 64 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_CRCFAIL BIT(17) BIT 65 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_STOPBIT_ERR BIT(18) BIT 66 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_DATATIMEOUT BIT(19) BIT 67 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_RXOVERFLOW BIT(20) BIT 68 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_TXUNDERRUN BIT(21) BIT 69 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_CMDTIMEOUT BIT(22) BIT 70 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */ BIT 71 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_RXRDY BIT(24) BIT 72 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_TXRQ BIT(25) BIT 73 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_ALWAYS_SET_27 BIT(27) /* only known on R-Car 2+ so far */ BIT 74 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */ BIT 75 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */ BIT 76 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_CMD_BUSY BIT(30) BIT 77 drivers/mmc/host/tmio_mmc.h #define TMIO_STAT_ILL_ACCESS BIT(31) BIT 81 drivers/mmc/host/tmio_mmc.h #define CLK_CTL_SCLKEN BIT(8) BIT 84 drivers/mmc/host/tmio_mmc.h #define CARD_OPT_WIDTH8 BIT(13) BIT 85 drivers/mmc/host/tmio_mmc.h #define CARD_OPT_WIDTH BIT(15) BIT 96 drivers/mmc/host/tmio_mmc.h #define DMA_ENABLE_DMASDRW BIT(1) BIT 28 drivers/mmc/host/toshsd.h #define SD_PCICFG_CLKMODE_DIV_DISABLE BIT(0) BIT 74 drivers/mmc/host/toshsd.h #define SD_TRANSCTL_SET BIT(8) BIT 76 drivers/mmc/host/toshsd.h #define SD_CARDCLK_DIV_DISABLE BIT(15) BIT 77 drivers/mmc/host/toshsd.h #define SD_CARDCLK_ENABLE_CLOCK BIT(8) BIT 78 drivers/mmc/host/toshsd.h #define SD_CARDCLK_CLK_DIV_512 BIT(7) BIT 79 drivers/mmc/host/toshsd.h #define SD_CARDCLK_CLK_DIV_256 BIT(6) BIT 80 drivers/mmc/host/toshsd.h #define SD_CARDCLK_CLK_DIV_128 BIT(5) BIT 81 drivers/mmc/host/toshsd.h #define SD_CARDCLK_CLK_DIV_64 BIT(4) BIT 82 drivers/mmc/host/toshsd.h #define SD_CARDCLK_CLK_DIV_32 BIT(3) BIT 83 drivers/mmc/host/toshsd.h #define SD_CARDCLK_CLK_DIV_16 BIT(2) BIT 84 drivers/mmc/host/toshsd.h #define SD_CARDCLK_CLK_DIV_8 BIT(1) BIT 85 drivers/mmc/host/toshsd.h #define SD_CARDCLK_CLK_DIV_4 BIT(0) BIT 90 drivers/mmc/host/toshsd.h #define SD_CARDOPT_C2_MODULE_ABSENT BIT(14) BIT 104 drivers/mmc/host/toshsd.h #define SD_CMD_DATA_PRESENT BIT(11) BIT 105 drivers/mmc/host/toshsd.h #define SD_CMD_TRANSFER_READ BIT(12) BIT 106 drivers/mmc/host/toshsd.h #define SD_CMD_MULTI_BLOCK BIT(13) BIT 107 drivers/mmc/host/toshsd.h #define SD_CMD_SECURITY_CMD BIT(14) BIT 109 drivers/mmc/host/toshsd.h #define SD_STOPINT_ISSUE_CMD12 BIT(0) BIT 110 drivers/mmc/host/toshsd.h #define SD_STOPINT_AUTO_ISSUE_CMD12 BIT(8) BIT 112 drivers/mmc/host/toshsd.h #define SD_CARD_RESP_END BIT(0) BIT 113 drivers/mmc/host/toshsd.h #define SD_CARD_RW_END BIT(2) BIT 114 drivers/mmc/host/toshsd.h #define SD_CARD_CARD_REMOVED_0 BIT(3) BIT 115 drivers/mmc/host/toshsd.h #define SD_CARD_CARD_INSERTED_0 BIT(4) BIT 116 drivers/mmc/host/toshsd.h #define SD_CARD_PRESENT_0 BIT(5) BIT 117 drivers/mmc/host/toshsd.h #define SD_CARD_UNK6 BIT(6) BIT 118 drivers/mmc/host/toshsd.h #define SD_CARD_WRITE_PROTECT BIT(7) BIT 119 drivers/mmc/host/toshsd.h #define SD_CARD_CARD_REMOVED_3 BIT(8) BIT 120 drivers/mmc/host/toshsd.h #define SD_CARD_CARD_INSERTED_3 BIT(9) BIT 121 drivers/mmc/host/toshsd.h #define SD_CARD_PRESENT_3 BIT(10) BIT 123 drivers/mmc/host/toshsd.h #define SD_BUF_CMD_INDEX_ERR BIT(16) BIT 124 drivers/mmc/host/toshsd.h #define SD_BUF_CRC_ERR BIT(17) BIT 125 drivers/mmc/host/toshsd.h #define SD_BUF_STOP_BIT_END_ERR BIT(18) BIT 126 drivers/mmc/host/toshsd.h #define SD_BUF_DATA_TIMEOUT BIT(19) BIT 127 drivers/mmc/host/toshsd.h #define SD_BUF_OVERFLOW BIT(20) BIT 128 drivers/mmc/host/toshsd.h #define SD_BUF_UNDERFLOW BIT(21) BIT 129 drivers/mmc/host/toshsd.h #define SD_BUF_CMD_TIMEOUT BIT(22) BIT 130 drivers/mmc/host/toshsd.h #define SD_BUF_UNK7 BIT(23) BIT 131 drivers/mmc/host/toshsd.h #define SD_BUF_READ_ENABLE BIT(24) BIT 132 drivers/mmc/host/toshsd.h #define SD_BUF_WRITE_ENABLE BIT(25) BIT 133 drivers/mmc/host/toshsd.h #define SD_BUF_ILLEGAL_FUNCTION BIT(29) BIT 134 drivers/mmc/host/toshsd.h #define SD_BUF_CMD_BUSY BIT(30) BIT 135 drivers/mmc/host/toshsd.h #define SD_BUF_ILLEGAL_ACCESS BIT(31) BIT 137 drivers/mmc/host/toshsd.h #define SD_ERR0_RESP_CMD_ERR BIT(0) BIT 138 drivers/mmc/host/toshsd.h #define SD_ERR0_RESP_NON_CMD12_END_BIT_ERR BIT(2) BIT 139 drivers/mmc/host/toshsd.h #define SD_ERR0_RESP_CMD12_END_BIT_ERR BIT(3) BIT 140 drivers/mmc/host/toshsd.h #define SD_ERR0_READ_DATA_END_BIT_ERR BIT(4) BIT 141 drivers/mmc/host/toshsd.h #define SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR BIT(5) BIT 142 drivers/mmc/host/toshsd.h #define SD_ERR0_RESP_NON_CMD12_CRC_ERR BIT(8) BIT 143 drivers/mmc/host/toshsd.h #define SD_ERR0_RESP_CMD12_CRC_ERR BIT(9) BIT 144 drivers/mmc/host/toshsd.h #define SD_ERR0_READ_DATA_CRC_ERR BIT(10) BIT 145 drivers/mmc/host/toshsd.h #define SD_ERR0_WRITE_CMD_CRC_ERR BIT(11) BIT 147 drivers/mmc/host/toshsd.h #define SD_ERR1_NO_CMD_RESP BIT(16) BIT 148 drivers/mmc/host/toshsd.h #define SD_ERR1_TIMEOUT_READ_DATA BIT(20) BIT 149 drivers/mmc/host/toshsd.h #define SD_ERR1_TIMEOUT_CRS_STATUS BIT(21) BIT 150 drivers/mmc/host/toshsd.h #define SD_ERR1_TIMEOUT_CRC_BUSY BIT(22) BIT 22 drivers/mmc/host/uniphier-sd.c #define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16) BIT 23 drivers/mmc/host/uniphier-sd.c #define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10) BIT 24 drivers/mmc/host/uniphier-sd.c #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop BIT 26 drivers/mmc/host/uniphier-sd.c #define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1) BIT 42 drivers/mmc/host/uniphier-sd.c #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed BIT 44 drivers/mmc/host/uniphier-sd.c #define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared) BIT 46 drivers/mmc/host/uniphier-sd.c #define UNIPHIER_SD_DMA_RST_CH1 BIT(9) BIT 47 drivers/mmc/host/uniphier-sd.c #define UNIPHIER_SD_DMA_RST_CH0 BIT(8) BIT 55 drivers/mmc/host/uniphier-sd.c #define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0) BIT 57 drivers/mmc/host/uniphier-sd.c #define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1) BIT 70 drivers/mmc/host/usdhi6rol0.c #define USDHI6_CC_EXT_MODE_SDRW BIT(1) BIT 72 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO1_RSP_END BIT(0) BIT 73 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO1_ACCESS_END BIT(2) BIT 74 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO1_CARD_OUT BIT(3) BIT 75 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO1_CARD_IN BIT(4) BIT 76 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO1_CD BIT(5) BIT 77 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO1_WP BIT(7) BIT 78 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO1_D3_CARD_OUT BIT(8) BIT 79 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO1_D3_CARD_IN BIT(9) BIT 81 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_CMD_ERR BIT(0) BIT 82 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_CRC_ERR BIT(1) BIT 83 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_END_ERR BIT(2) BIT 84 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_TOUT BIT(3) BIT 85 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_IWA_ERR BIT(4) BIT 86 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_IRA_ERR BIT(5) BIT 87 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_RSP_TOUT BIT(6) BIT 88 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_SDDAT0 BIT(7) BIT 89 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_BRE BIT(8) BIT 90 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_BWE BIT(9) BIT 91 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_SCLKDIVEN BIT(13) BIT 92 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_CBSY BIT(14) BIT 93 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_INFO2_ILA BIT(15) BIT 112 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_CLK_CTRL_SCLKEN BIT(8) BIT 114 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_STOP_STP BIT(0) BIT 115 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_STOP_SEC BIT(8) BIT 117 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SDIO_INFO1_IOIRQ BIT(0) BIT 118 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SDIO_INFO1_EXPUB52 BIT(14) BIT 119 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SDIO_INFO1_EXWT BIT(15) BIT 121 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_ERR_STS1_CRC_NO_ERROR BIT(13) BIT 123 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SOFT_RST_RESERVED (BIT(1) | BIT(2)) BIT 124 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SOFT_RST_RESET BIT(0) BIT 128 drivers/mmc/host/usdhi6rol0.c #define USDHI6_SD_OPTION_WIDTH_1 BIT(15) BIT 56 drivers/mtd/chips/cfi_cmdset_0002.c #define CFI_SR_DRB BIT(7) BIT 57 drivers/mtd/chips/cfi_cmdset_0002.c #define CFI_SR_ESB BIT(5) BIT 58 drivers/mtd/chips/cfi_cmdset_0002.c #define CFI_SR_PSB BIT(4) BIT 59 drivers/mtd/chips/cfi_cmdset_0002.c #define CFI_SR_WBASB BIT(3) BIT 60 drivers/mtd/chips/cfi_cmdset_0002.c #define CFI_SR_SLSB BIT(1) BIT 37 drivers/mtd/devices/mchp23k256.c #define MCHP23K256_MODE_SEQ BIT(6) BIT 130 drivers/mtd/maps/physmap-core.c if ((BIT(i) & ofs) == (BIT(i) & info->gpio_values)) BIT 133 drivers/mtd/maps/physmap-core.c gpiod_set_value(info->gpios->desc[i], !!(BIT(i) & ofs)); BIT 139 drivers/mtd/maps/physmap-core.c #define win_mask(order) (BIT(order) - 1) BIT 170 drivers/mtd/maps/physmap-core.c BIT(info->win_order) - winofs); BIT 207 drivers/mtd/maps/physmap-core.c BIT(info->win_order) - winofs); BIT 509 drivers/mtd/maps/physmap-core.c info->maps[i].size = BIT(info->win_order + BIT 69 drivers/mtd/maps/physmap-versatile.c #define INTEGRATOR_SC_CTRL_FLVPPEN BIT(1) BIT 70 drivers/mtd/maps/physmap-versatile.c #define INTEGRATOR_SC_CTRL_FLWP BIT(2) BIT 74 drivers/mtd/maps/physmap-versatile.c #define INTEGRATOR_EBI_WRITE_ENABLE BIT(3) BIT 145 drivers/mtd/maps/physmap-versatile.c #define CINTEGRATOR_FLVPPEN BIT(0) BIT 146 drivers/mtd/maps/physmap-versatile.c #define CINTEGRATOR_FLWREN BIT(1) BIT 147 drivers/mtd/maps/physmap-versatile.c #define CINTEGRATOR_FLMASK BIT(0)|BIT(1) BIT 74 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13) BIT 75 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12) BIT 76 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9) BIT 77 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8) BIT 82 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_CTRL_EN BIT(0) BIT 83 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_CTRL_DIS BIT(1) BIT 89 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_ENABLED BIT(1) BIT 90 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4) BIT 91 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5) BIT 92 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_BUSY BIT(8) BIT 93 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_WR BIT(11) BIT 95 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16) BIT 96 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17) BIT 97 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_DTOE BIT(20) BIT 98 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_UNDEF BIT(21) BIT 99 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_AWB BIT(22) BIT 100 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_NFCASE BIT(23) BIT 105 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24) BIT 115 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_NFC_VCMD2 BIT(18) BIT 118 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_NFC_DATAEN BIT(25) BIT 119 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_NFC_NFCWR BIT(26) BIT 123 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_NAND_ALE_OFFSET BIT(21) BIT 124 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_NAND_CLE_OFFSET BIT(22) BIT 1521 drivers/mtd/nand/raw/atmel/nand-controller.c BIT(nand->cs[i].id), BIT(nand->cs[i].id)); BIT 2326 drivers/mtd/nand/raw/atmel/nand-controller.c .ale_offs = BIT(21), BIT 2327 drivers/mtd/nand/raw/atmel/nand-controller.c .cle_offs = BIT(22), BIT 2334 drivers/mtd/nand/raw/atmel/nand-controller.c .ale_offs = BIT(21), BIT 2335 drivers/mtd/nand/raw/atmel/nand-controller.c .cle_offs = BIT(22), BIT 2391 drivers/mtd/nand/raw/atmel/nand-controller.c .ale_offs = BIT(21), BIT 2392 drivers/mtd/nand/raw/atmel/nand-controller.c .cle_offs = BIT(22), BIT 2406 drivers/mtd/nand/raw/atmel/nand-controller.c .ale_offs = BIT(21), BIT 2407 drivers/mtd/nand/raw/atmel/nand-controller.c .cle_offs = BIT(22), BIT 2413 drivers/mtd/nand/raw/atmel/nand-controller.c .ale_offs = BIT(22), BIT 2414 drivers/mtd/nand/raw/atmel/nand-controller.c .cle_offs = BIT(21), BIT 2421 drivers/mtd/nand/raw/atmel/nand-controller.c .ale_offs = BIT(21), BIT 2422 drivers/mtd/nand/raw/atmel/nand-controller.c .cle_offs = BIT(22), BIT 2429 drivers/mtd/nand/raw/atmel/nand-controller.c .ale_offs = BIT(21), BIT 2430 drivers/mtd/nand/raw/atmel/nand-controller.c .cle_offs = BIT(22), BIT 2437 drivers/mtd/nand/raw/atmel/nand-controller.c .ale_offs = BIT(21), BIT 2438 drivers/mtd/nand/raw/atmel/nand-controller.c .cle_offs = BIT(22), BIT 2444 drivers/mtd/nand/raw/atmel/nand-controller.c .ale_offs = BIT(22), BIT 2445 drivers/mtd/nand/raw/atmel/nand-controller.c .cle_offs = BIT(21), BIT 2452 drivers/mtd/nand/raw/atmel/nand-controller.c .ale_offs = BIT(21), BIT 2453 drivers/mtd/nand/raw/atmel/nand-controller.c .cle_offs = BIT(22), BIT 78 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_CFG_SPARE_ENABLE BIT(16) BIT 79 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_CFG_AUTO_ENABLE BIT(20) BIT 89 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_CTRL_RST BIT(0) BIT 90 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_CTRL_DATA BIT(1) BIT 91 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_CTRL_USER BIT(2) BIT 92 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_CTRL_ENABLE BIT(4) BIT 93 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_CTRL_DISABLE BIT(5) BIT 96 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_SR_BUSY BIT(0) BIT 97 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_SR_ENABLE BIT(4) BIT 103 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_ERROR_INT BIT(0) BIT 120 drivers/mtd/nand/raw/atmel/pmecc.c #define PMERRLOC_DISABLE BIT(0) BIT 123 drivers/mtd/nand/raw/atmel/pmecc.c #define PMERRLOC_ELSR_BUSY BIT(0) BIT 130 drivers/mtd/nand/raw/atmel/pmecc.c #define PMERRLOC_CALC_DONE BIT(0) BIT 196 drivers/mtd/nand/raw/atmel/pmecc.c const unsigned int k = BIT(deg(poly)); BIT 197 drivers/mtd/nand/raw/atmel/pmecc.c unsigned int nn = BIT(mm) - 1; BIT 449 drivers/mtd/nand/raw/atmel/pmecc.c int cw_len = BIT(degree) - 1; BIT 469 drivers/mtd/nand/raw/atmel/pmecc.c if (partial_syn[i] & BIT(j)) BIT 495 drivers/mtd/nand/raw/atmel/pmecc.c int cw_len = BIT(degree) - 1; BIT 698 drivers/mtd/nand/raw/atmel/pmecc.c if (!(user->isr & BIT(sector))) BIT 737 drivers/mtd/nand/raw/atmel/pmecc.c area, byte, *ptr, (unsigned int)(*ptr ^ BIT(bit))); BIT 739 drivers/mtd/nand/raw/atmel/pmecc.c *ptr ^= BIT(bit); BIT 26 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c BCM63138_CTLRDY = BIT(4), BIT 40 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c BCM6368_NP_READ = BIT(0), BIT 41 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c BCM6368_BLOCK_ERASE = BIT(1), BIT 42 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c BCM6368_COPY_BACK = BIT(2), BIT 43 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c BCM6368_PAGE_PGM = BIT(3), BIT 44 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c BCM6368_CTRL_READY = BIT(4), BIT 45 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c BCM6368_DEV_RBPIN = BIT(5), BIT 46 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c BCM6368_ECC_ERR_UNC = BIT(6), BIT 47 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c BCM6368_ECC_ERR_CORR = BIT(7), BIT 88 drivers/mtd/nand/raw/brcmnand/brcmnand.c #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */ BIT 89 drivers/mtd/nand/raw/brcmnand/brcmnand.c #define FLASH_DMA_MODE_MODE BIT(0) /* link list */ BIT 152 drivers/mtd/nand/raw/brcmnand/brcmnand.c BRCMNAND_HAS_1K_SECTORS = BIT(0), BIT 153 drivers/mtd/nand/raw/brcmnand/brcmnand.c BRCMNAND_HAS_PREFETCH = BIT(1), BIT 154 drivers/mtd/nand/raw/brcmnand/brcmnand.c BRCMNAND_HAS_CACHE_MODE = BIT(2), BIT 155 drivers/mtd/nand/raw/brcmnand/brcmnand.c BRCMNAND_HAS_WP = BIT(3), BIT 467 drivers/mtd/nand/raw/brcmnand/brcmnand.c CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT), BIT 483 drivers/mtd/nand/raw/brcmnand/brcmnand.c INTFC_ERASED = BIT(27), BIT 484 drivers/mtd/nand/raw/brcmnand/brcmnand.c INTFC_OOB_VALID = BIT(28), BIT 485 drivers/mtd/nand/raw/brcmnand/brcmnand.c INTFC_CACHE_VALID = BIT(29), BIT 486 drivers/mtd/nand/raw/brcmnand/brcmnand.c INTFC_FLASH_READY = BIT(30), BIT 487 drivers/mtd/nand/raw/brcmnand/brcmnand.c INTFC_CTLR_READY = BIT(31), BIT 764 drivers/mtd/nand/raw/brcmnand/brcmnand.c ACC_CONTROL_CACHE_MODE = BIT(22), BIT 767 drivers/mtd/nand/raw/brcmnand/brcmnand.c ACC_CONTROL_PREFETCH = BIT(23), BIT 769 drivers/mtd/nand/raw/brcmnand/brcmnand.c ACC_CONTROL_PAGE_HIT = BIT(24), BIT 770 drivers/mtd/nand/raw/brcmnand/brcmnand.c ACC_CONTROL_WR_PREEMPT = BIT(25), BIT 771 drivers/mtd/nand/raw/brcmnand/brcmnand.c ACC_CONTROL_PARTIAL_PAGE = BIT(26), BIT 772 drivers/mtd/nand/raw/brcmnand/brcmnand.c ACC_CONTROL_RD_ERASED = BIT(27), BIT 773 drivers/mtd/nand/raw/brcmnand/brcmnand.c ACC_CONTROL_FAST_PGM_RDIN = BIT(28), BIT 774 drivers/mtd/nand/raw/brcmnand/brcmnand.c ACC_CONTROL_WR_ECC = BIT(30), BIT 775 drivers/mtd/nand/raw/brcmnand/brcmnand.c ACC_CONTROL_RD_ECC = BIT(31), BIT 870 drivers/mtd/nand/raw/brcmnand/brcmnand.c CS_SELECT_NAND_WP = BIT(29), BIT 871 drivers/mtd/nand/raw/brcmnand/brcmnand.c CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30), BIT 1401 drivers/mtd/nand/raw/brcmnand/brcmnand.c LLOP_RE = BIT(16), BIT 1402 drivers/mtd/nand/raw/brcmnand/brcmnand.c LLOP_WE = BIT(17), BIT 1403 drivers/mtd/nand/raw/brcmnand/brcmnand.c LLOP_ALE = BIT(18), BIT 1404 drivers/mtd/nand/raw/brcmnand/brcmnand.c LLOP_CLE = BIT(19), BIT 1405 drivers/mtd/nand/raw/brcmnand/brcmnand.c LLOP_RETURN_IDLE = BIT(31), BIT 26 drivers/mtd/nand/raw/brcmnand/iproc_nand.c #define IPROC_NAND_CTLR_READY BIT(0) BIT 29 drivers/mtd/nand/raw/brcmnand/iproc_nand.c #define IPROC_NAND_APB_LE_MODE BIT(24) BIT 30 drivers/mtd/nand/raw/brcmnand/iproc_nand.c #define IPROC_NAND_INT_CTRL_READ_ENABLE BIT(6) BIT 617 drivers/mtd/nand/raw/cafe_nand.c cafe->ctl2 = BIT(27); /* Reed-Solomon ECC */ BIT 619 drivers/mtd/nand/raw/cafe_nand.c cafe->ctl2 |= BIT(29); /* 2KiB page size */ BIT 150 drivers/mtd/nand/raw/davinci_nand.c nandcfr |= BIT(8 + info->core_chipsel); BIT 187 drivers/mtd/nand/raw/davinci_nand.c dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7); BIT 233 drivers/mtd/nand/raw/davinci_nand.c val |= (info->core_chipsel << 4) | BIT(12); BIT 342 drivers/mtd/nand/raw/davinci_nand.c davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); BIT 454 drivers/mtd/nand/raw/davinci_nand.c return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0); BIT 785 drivers/mtd/nand/raw/davinci_nand.c val |= BIT(info->core_chipsel); BIT 419 drivers/mtd/nand/raw/denali.c if (!(uncor_ecc_flags & BIT(i))) BIT 510 drivers/mtd/nand/raw/denali.c *uncor_ecc_flags |= BIT(err_sector); BIT 564 drivers/mtd/nand/raw/denali.c (write ? BIT(8) : 0) | page_count); BIT 585 drivers/mtd/nand/raw/denali.c 0x2000 | (write ? BIT(8) : 0) | page_count); BIT 18 drivers/mtd/nand/raw/denali.h #define DEVICE_RESET__BANK(bank) BIT(bank) BIT 21 drivers/mtd/nand/raw/denali.h #define TRANSFER_SPARE_REG__FLAG BIT(0) BIT 36 drivers/mtd/nand/raw/denali.h #define RB_PIN_ENABLED__BANK(bank) BIT(bank) BIT 39 drivers/mtd/nand/raw/denali.h #define MULTIPLANE_OPERATION__FLAG BIT(0) BIT 42 drivers/mtd/nand/raw/denali.h #define MULTIPLANE_READ_ENABLE__FLAG BIT(0) BIT 45 drivers/mtd/nand/raw/denali.h #define COPYBACK_DISABLE__FLAG BIT(0) BIT 48 drivers/mtd/nand/raw/denali.h #define CACHE_WRITE_ENABLE__FLAG BIT(0) BIT 51 drivers/mtd/nand/raw/denali.h #define CACHE_READ_ENABLE__FLAG BIT(0) BIT 54 drivers/mtd/nand/raw/denali.h #define PREFETCH_MODE__PREFETCH_EN BIT(0) BIT 58 drivers/mtd/nand/raw/denali.h #define CHIP_EN_DONT_CARE__FLAG BIT(0) BIT 61 drivers/mtd/nand/raw/denali.h #define ECC_ENABLE__FLAG BIT(0) BIT 64 drivers/mtd/nand/raw/denali.h #define GLOBAL_INT_EN_FLAG BIT(0) BIT 97 drivers/mtd/nand/raw/denali.h #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0) BIT 100 drivers/mtd/nand/raw/denali.h #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0) BIT 144 drivers/mtd/nand/raw/denali.h #define WRITE_PROTECT__FLAG BIT(0) BIT 187 drivers/mtd/nand/raw/denali.h #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8) BIT 198 drivers/mtd/nand/raw/denali.h #define FEATURES__DMA BIT(6) BIT 199 drivers/mtd/nand/raw/denali.h #define FEATURES__CMD_DMA BIT(7) BIT 200 drivers/mtd/nand/raw/denali.h #define FEATURES__PARTITION BIT(8) BIT 201 drivers/mtd/nand/raw/denali.h #define FEATURES__XDMA_SIDEBAND BIT(9) BIT 202 drivers/mtd/nand/raw/denali.h #define FEATURES__GPREG BIT(10) BIT 203 drivers/mtd/nand/raw/denali.h #define FEATURES__INDEX_ADDR BIT(11) BIT 211 drivers/mtd/nand/raw/denali.h #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */ BIT 212 drivers/mtd/nand/raw/denali.h #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */ BIT 213 drivers/mtd/nand/raw/denali.h #define INTR__ECC_ERR BIT(1) /* old IP */ BIT 214 drivers/mtd/nand/raw/denali.h #define INTR__DMA_CMD_COMP BIT(2) BIT 215 drivers/mtd/nand/raw/denali.h #define INTR__TIME_OUT BIT(3) BIT 216 drivers/mtd/nand/raw/denali.h #define INTR__PROGRAM_FAIL BIT(4) BIT 217 drivers/mtd/nand/raw/denali.h #define INTR__ERASE_FAIL BIT(5) BIT 218 drivers/mtd/nand/raw/denali.h #define INTR__LOAD_COMP BIT(6) BIT 219 drivers/mtd/nand/raw/denali.h #define INTR__PROGRAM_COMP BIT(7) BIT 220 drivers/mtd/nand/raw/denali.h #define INTR__ERASE_COMP BIT(8) BIT 221 drivers/mtd/nand/raw/denali.h #define INTR__PIPE_CPYBCK_CMD_COMP BIT(9) BIT 222 drivers/mtd/nand/raw/denali.h #define INTR__LOCKED_BLK BIT(10) BIT 223 drivers/mtd/nand/raw/denali.h #define INTR__UNSUP_CMD BIT(11) BIT 224 drivers/mtd/nand/raw/denali.h #define INTR__INT_ACT BIT(12) BIT 225 drivers/mtd/nand/raw/denali.h #define INTR__RST_COMP BIT(13) BIT 226 drivers/mtd/nand/raw/denali.h #define INTR__PIPE_CMD_ERR BIT(14) BIT 227 drivers/mtd/nand/raw/denali.h #define INTR__PAGE_XFER_INC BIT(15) BIT 228 drivers/mtd/nand/raw/denali.h #define INTR__ERASED_PAGE BIT(16) BIT 251 drivers/mtd/nand/raw/denali.h #define ERR_CORRECTION_INFO__UNCOR BIT(14) BIT 252 drivers/mtd/nand/raw/denali.h #define ERR_CORRECTION_INFO__LAST_ERR BIT(15) BIT 257 drivers/mtd/nand/raw/denali.h #define ECC_COR_INFO__UNCOR_ERR BIT(7) BIT 268 drivers/mtd/nand/raw/denali.h #define DMA_ENABLE__FLAG BIT(0) BIT 271 drivers/mtd/nand/raw/denali.h #define IGNORE_ECC_DONE__FLAG BIT(0) BIT 275 drivers/mtd/nand/raw/denali.h #define DMA_INTR__TARGET_ERROR BIT(0) BIT 276 drivers/mtd/nand/raw/denali.h #define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1) BIT 277 drivers/mtd/nand/raw/denali.h #define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2) BIT 278 drivers/mtd/nand/raw/denali.h #define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3) BIT 279 drivers/mtd/nand/raw/denali.h #define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4) BIT 280 drivers/mtd/nand/raw/denali.h #define DMA_INTR__MEMCOPY_DESC_COMP BIT(5) BIT 289 drivers/mtd/nand/raw/denali.h #define CHNL_ACTIVE__CHANNEL0 BIT(0) BIT 290 drivers/mtd/nand/raw/denali.h #define CHNL_ACTIVE__CHANNEL1 BIT(1) BIT 291 drivers/mtd/nand/raw/denali.h #define CHNL_ACTIVE__CHANNEL2 BIT(2) BIT 292 drivers/mtd/nand/raw/denali.h #define CHNL_ACTIVE__CHANNEL3 BIT(3) BIT 389 drivers/mtd/nand/raw/denali.h #define DENALI_CAP_HW_ECC_FIXUP BIT(0) BIT 390 drivers/mtd/nand/raw/denali.h #define DENALI_CAP_DMA_64BIT BIT(1) BIT 41 drivers/mtd/nand/raw/fsmc_nand.c #define BANK_ENABLE BIT(0) BIT 42 drivers/mtd/nand/raw/fsmc_nand.c #define MUXED BIT(1) BIT 44 drivers/mtd/nand/raw/fsmc_nand.c #define WIDTH_16 BIT(4) BIT 45 drivers/mtd/nand/raw/fsmc_nand.c #define RSTPWRDWN BIT(6) BIT 46 drivers/mtd/nand/raw/fsmc_nand.c #define WPROT BIT(7) BIT 47 drivers/mtd/nand/raw/fsmc_nand.c #define WRT_ENABLE BIT(12) BIT 48 drivers/mtd/nand/raw/fsmc_nand.c #define WAIT_ENB BIT(13) BIT 63 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_RESET BIT(0) BIT 64 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_WAITON BIT(1) BIT 65 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_ENABLE BIT(2) BIT 66 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_DEVTYPE_NAND BIT(3) BIT 67 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_DEVWID_16 BIT(4) BIT 68 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_ECCEN BIT(6) BIT 69 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_ECCPLEN_256 BIT(7) BIT 76 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_CODE_RDY BIT(15) BIT 41 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_CON_OP_MODE_NORMAL BIT(0) BIT 44 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_CON_BUS_WIDTH BIT(4) BIT 45 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_CON_READY_BUSY_SEL BIT(8) BIT 59 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_OP_READ_DATA_EN BIT(1) BIT 60 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_OP_WAIT_READY_EN BIT(2) BIT 61 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_OP_CMD2_EN BIT(3) BIT 62 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_OP_WRITE_DATA_EN BIT(4) BIT 63 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_OP_ADDR_EN BIT(5) BIT 64 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_OP_CMD1_EN BIT(6) BIT 71 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_READY BIT(0) BIT 74 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_INTEN_DMA BIT(9) BIT 75 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_INTEN_UE BIT(6) BIT 76 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_INTEN_CE BIT(5) BIT 79 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_INTS_DMA BIT(9) BIT 80 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_INTS_UE BIT(6) BIT 81 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_INTS_CE BIT(5) BIT 84 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_INTCLR_DMA BIT(9) BIT 85 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_INTCLR_UE BIT(6) BIT 86 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_INTCLR_CE BIT(5) BIT 92 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_CTRL_DMA_START BIT(0) BIT 93 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_CTRL_WE BIT(1) BIT 94 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_CTRL_DATA_AREA_EN BIT(2) BIT 95 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_CTRL_OOB_AREA_EN BIT(3) BIT 96 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_CTRL_BURST4_EN BIT(4) BIT 97 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_CTRL_BURST8_EN BIT(5) BIT 98 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_CTRL_BURST16_EN BIT(6) BIT 112 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_PARA_DATA_RW_EN BIT(0) BIT 113 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_PARA_OOB_RW_EN BIT(1) BIT 114 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_PARA_DATA_EDC_EN BIT(2) BIT 115 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_PARA_OOB_EDC_EN BIT(3) BIT 116 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_PARA_DATA_ECC_EN BIT(4) BIT 117 drivers/mtd/nand/raw/hisi504_nand.c #define HINFC504_DMA_PARA_OOB_ECC_EN BIT(5) BIT 33 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c #define BCH_BHCR_ENCE BIT(3) BIT 34 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c #define BCH_BHCR_BSEL BIT(2) BIT 35 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c #define BCH_BHCR_INIT BIT(1) BIT 36 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c #define BCH_BHCR_BCHE BIT(0) BIT 52 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c #define BCH_BHINT_ALL_0 BIT(5) BIT 53 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c #define BCH_BHINT_ALL_F BIT(4) BIT 54 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c #define BCH_BHINT_DECF BIT(3) BIT 55 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c #define BCH_BHINT_ENCF BIT(2) BIT 56 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c #define BCH_BHINT_UNCOR BIT(1) BIT 57 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c #define BCH_BHINT_ERR BIT(0) BIT 262 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c buf[(bit >> 3)] ^= BIT(bit & 0x7); BIT 28 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_ECC_CTRL_PAR_READY BIT(4) BIT 29 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_ECC_CTRL_ENCODING BIT(3) BIT 30 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_ECC_CTRL_RS BIT(2) BIT 31 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_ECC_CTRL_RESET BIT(1) BIT 32 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_ECC_CTRL_ENABLE BIT(0) BIT 34 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29)) BIT 35 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_STATUS_PAD_FINISH BIT(4) BIT 36 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_STATUS_DEC_FINISH BIT(3) BIT 37 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_STATUS_ENC_FINISH BIT(2) BIT 38 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_STATUS_UNCOR_ERROR BIT(1) BIT 39 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c #define JZ_NAND_STATUS_ERROR BIT(0) BIT 34 drivers/mtd/nand/raw/ingenic/jz4780_bch.c #define BCH_BHCR_ENCE BIT(2) BIT 35 drivers/mtd/nand/raw/ingenic/jz4780_bch.c #define BCH_BHCR_INIT BIT(1) BIT 36 drivers/mtd/nand/raw/ingenic/jz4780_bch.c #define BCH_BHCR_BCHE BIT(0) BIT 52 drivers/mtd/nand/raw/ingenic/jz4780_bch.c #define BCH_BHINT_DECF BIT(3) BIT 53 drivers/mtd/nand/raw/ingenic/jz4780_bch.c #define BCH_BHINT_ENCF BIT(2) BIT 54 drivers/mtd/nand/raw/ingenic/jz4780_bch.c #define BCH_BHINT_UNCOR BIT(1) BIT 55 drivers/mtd/nand/raw/ingenic/jz4780_bch.c #define BCH_BHINT_ERR BIT(0) BIT 113 drivers/mtd/nand/raw/marvell_nand.c #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0) BIT 114 drivers/mtd/nand/raw/marvell_nand.c #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20) BIT 115 drivers/mtd/nand/raw/marvell_nand.c #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21) BIT 116 drivers/mtd/nand/raw/marvell_nand.c #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25) BIT 118 drivers/mtd/nand/raw/marvell_nand.c #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2) BIT 120 drivers/mtd/nand/raw/marvell_nand.c #define GENCONF_ND_CLK_CTRL_EN BIT(0) BIT 125 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_CS1_CMDDM BIT(7) BIT 126 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_CS0_CMDDM BIT(8) BIT 127 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_RDYM BIT(11) BIT 128 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_ND_ARB_EN BIT(12) BIT 129 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_RA_START BIT(15) BIT 131 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0) BIT 132 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_DWIDTH_M BIT(26) BIT 133 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_DWIDTH_C BIT(27) BIT 134 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_ND_RUN BIT(28) BIT 135 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_DMA_EN BIT(29) BIT 136 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_ECC_EN BIT(30) BIT 137 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_SPARE_EN BIT(31) BIT 146 drivers/mtd/nand/raw/marvell_nand.c #define NDTR0_SEL_NRE_EDGE BIT(7) BIT 152 drivers/mtd/nand/raw/marvell_nand.c #define NDTR0_SELCNTR BIT(26) BIT 160 drivers/mtd/nand/raw/marvell_nand.c #define NDTR1_PRESCALE BIT(14) BIT 161 drivers/mtd/nand/raw/marvell_nand.c #define NDTR1_WAIT_MODE BIT(15) BIT 166 drivers/mtd/nand/raw/marvell_nand.c #define NDSR_WRCMDREQ BIT(0) BIT 167 drivers/mtd/nand/raw/marvell_nand.c #define NDSR_RDDREQ BIT(1) BIT 168 drivers/mtd/nand/raw/marvell_nand.c #define NDSR_WRDREQ BIT(2) BIT 169 drivers/mtd/nand/raw/marvell_nand.c #define NDSR_CORERR BIT(3) BIT 170 drivers/mtd/nand/raw/marvell_nand.c #define NDSR_UNCERR BIT(4) BIT 171 drivers/mtd/nand/raw/marvell_nand.c #define NDSR_CMDD(cs) BIT(8 - cs) BIT 172 drivers/mtd/nand/raw/marvell_nand.c #define NDSR_RDY(rb) BIT(11 + rb) BIT 177 drivers/mtd/nand/raw/marvell_nand.c #define NDECCCTRL_BCH_EN BIT(0) BIT 188 drivers/mtd/nand/raw/marvell_nand.c #define NDCB0_DBC BIT(19) BIT 190 drivers/mtd/nand/raw/marvell_nand.c #define NDCB0_CSEL BIT(24) BIT 191 drivers/mtd/nand/raw/marvell_nand.c #define NDCB0_RDY_BYP BIT(27) BIT 192 drivers/mtd/nand/raw/marvell_nand.c #define NDCB0_LEN_OVRD BIT(28) BIT 1341 drivers/mtd/nand/raw/marvell_nand.c failure_mask |= BIT(chunk); BIT 1378 drivers/mtd/nand/raw/marvell_nand.c if (!(failure_mask & BIT(chunk))) BIT 35 drivers/mtd/nand/raw/meson_nand.c #define NFC_CMD_RB BIT(20) BIT 36 drivers/mtd/nand/raw/meson_nand.c #define NFC_CMD_SCRAMBLER_ENABLE BIT(19) BIT 39 drivers/mtd/nand/raw/meson_nand.c #define NFC_CMD_RB_INT BIT(14) BIT 57 drivers/mtd/nand/raw/meson_nand.c #define NFC_RB_IRQ_EN BIT(21) BIT 87 drivers/mtd/nand/raw/meson_nand.c #define CLK_SELECT_NAND BIT(31) BIT 100 drivers/mtd/nand/raw/meson_nand.c #define ECC_COMPLETE BIT(31) BIT 21 drivers/mtd/nand/raw/mtk_ecc.c #define ECC_IDLE_MASK BIT(0) BIT 22 drivers/mtd/nand/raw/mtk_ecc.c #define ECC_IRQ_EN BIT(0) BIT 23 drivers/mtd/nand/raw/mtk_ecc.c #define ECC_PG_IRQ_SEL BIT(1) BIT 34 drivers/mtd/nand/raw/mtk_ecc.c #define DEC_EMPTY_EN BIT(31) BIT 24 drivers/mtd/nand/raw/mtk_nand.c #define CNFG_AHB BIT(0) BIT 25 drivers/mtd/nand/raw/mtk_nand.c #define CNFG_READ_EN BIT(1) BIT 26 drivers/mtd/nand/raw/mtk_nand.c #define CNFG_DMA_BURST_EN BIT(2) BIT 27 drivers/mtd/nand/raw/mtk_nand.c #define CNFG_BYTE_RW BIT(6) BIT 28 drivers/mtd/nand/raw/mtk_nand.c #define CNFG_HW_ECC_EN BIT(8) BIT 29 drivers/mtd/nand/raw/mtk_nand.c #define CNFG_AUTO_FMT_EN BIT(9) BIT 34 drivers/mtd/nand/raw/mtk_nand.c #define PAGEFMT_SEC_SEL_512 BIT(2) BIT 41 drivers/mtd/nand/raw/mtk_nand.c #define CON_FIFO_FLUSH BIT(0) BIT 42 drivers/mtd/nand/raw/mtk_nand.c #define CON_NFI_RST BIT(1) BIT 43 drivers/mtd/nand/raw/mtk_nand.c #define CON_BRD BIT(8) /* burst read */ BIT 44 drivers/mtd/nand/raw/mtk_nand.c #define CON_BWR BIT(9) /* burst write */ BIT 49 drivers/mtd/nand/raw/mtk_nand.c #define INTR_AHB_DONE_EN BIT(6) BIT 64 drivers/mtd/nand/raw/mtk_nand.c #define STA_CMD BIT(0) BIT 65 drivers/mtd/nand/raw/mtk_nand.c #define STA_ADDR BIT(1) BIT 66 drivers/mtd/nand/raw/mtk_nand.c #define STA_BUSY BIT(8) BIT 67 drivers/mtd/nand/raw/mtk_nand.c #define STA_EMP_PAGE BIT(12) BIT 23 drivers/mtd/nand/raw/mxic_nand.c #define HC_CFG_DUAL_SLAVE BIT(31) BIT 24 drivers/mtd/nand/raw/mxic_nand.c #define HC_CFG_INDIVIDUAL BIT(30) BIT 32 drivers/mtd/nand/raw/mxic_nand.c #define HC_CFG_CLK_PH_EN BIT(20) BIT 33 drivers/mtd/nand/raw/mxic_nand.c #define HC_CFG_CLK_POL_INV BIT(19) BIT 34 drivers/mtd/nand/raw/mxic_nand.c #define HC_CFG_BIG_ENDIAN BIT(18) BIT 35 drivers/mtd/nand/raw/mxic_nand.c #define HC_CFG_DATA_PASS BIT(17) BIT 37 drivers/mtd/nand/raw/mxic_nand.c #define HC_CFG_MAN_START_EN BIT(3) BIT 38 drivers/mtd/nand/raw/mxic_nand.c #define HC_CFG_MAN_START BIT(2) BIT 39 drivers/mtd/nand/raw/mxic_nand.c #define HC_CFG_MAN_CS_EN BIT(1) BIT 40 drivers/mtd/nand/raw/mxic_nand.c #define HC_CFG_MAN_CS_ASSERT BIT(0) BIT 46 drivers/mtd/nand/raw/mxic_nand.c #define INT_RDY_PIN BIT(26) BIT 47 drivers/mtd/nand/raw/mxic_nand.c #define INT_RDY_SR BIT(25) BIT 48 drivers/mtd/nand/raw/mxic_nand.c #define INT_LNR_SUSP BIT(24) BIT 49 drivers/mtd/nand/raw/mxic_nand.c #define INT_ECC_ERR BIT(17) BIT 50 drivers/mtd/nand/raw/mxic_nand.c #define INT_CRC_ERR BIT(16) BIT 51 drivers/mtd/nand/raw/mxic_nand.c #define INT_LWR_DIS BIT(12) BIT 52 drivers/mtd/nand/raw/mxic_nand.c #define INT_LRD_DIS BIT(11) BIT 53 drivers/mtd/nand/raw/mxic_nand.c #define INT_SDMA_INT BIT(10) BIT 54 drivers/mtd/nand/raw/mxic_nand.c #define INT_DMA_FINISH BIT(9) BIT 55 drivers/mtd/nand/raw/mxic_nand.c #define INT_RX_NOT_FULL BIT(3) BIT 56 drivers/mtd/nand/raw/mxic_nand.c #define INT_RX_NOT_EMPTY BIT(2) BIT 57 drivers/mtd/nand/raw/mxic_nand.c #define INT_TX_NOT_FULL BIT(1) BIT 58 drivers/mtd/nand/raw/mxic_nand.c #define INT_TX_EMPTY BIT(0) BIT 61 drivers/mtd/nand/raw/mxic_nand.c #define HC_EN_BIT BIT(0) BIT 70 drivers/mtd/nand/raw/mxic_nand.c #define OP_READ BIT(23) BIT 74 drivers/mtd/nand/raw/mxic_nand.c #define OP_OCTA_CRC_EN BIT(12) BIT 75 drivers/mtd/nand/raw/mxic_nand.c #define OP_DQS_EN BIT(11) BIT 76 drivers/mtd/nand/raw/mxic_nand.c #define OP_ENHC_EN BIT(10) BIT 77 drivers/mtd/nand/raw/mxic_nand.c #define OP_PREAMBLE_EN BIT(9) BIT 78 drivers/mtd/nand/raw/mxic_nand.c #define OP_DATA_DDR BIT(8) BIT 80 drivers/mtd/nand/raw/mxic_nand.c #define OP_ADDR_DDR BIT(5) BIT 82 drivers/mtd/nand/raw/mxic_nand.c #define OP_CMD_DDR BIT(2) BIT 90 drivers/mtd/nand/raw/mxic_nand.c #define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16)) BIT 92 drivers/mtd/nand/raw/mxic_nand.c #define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16)) BIT 99 drivers/mtd/nand/raw/mxic_nand.c #define LMODE_EN BIT(31) BIT 113 drivers/mtd/nand/raw/mxic_nand.c #define DMAC_CFG_PERIPH_EN BIT(31) BIT 114 drivers/mtd/nand/raw/mxic_nand.c #define DMAC_CFG_ALLFLUSH_EN BIT(30) BIT 115 drivers/mtd/nand/raw/mxic_nand.c #define DMAC_CFG_LASTFLUSH_EN BIT(29) BIT 119 drivers/mtd/nand/raw/mxic_nand.c #define DMAC_CFG_DIR_READ BIT(1) BIT 120 drivers/mtd/nand/raw/mxic_nand.c #define DMAC_CFG_START BIT(0) BIT 128 drivers/mtd/nand/raw/mxic_nand.c #define DMAM_CFG_START BIT(31) BIT 129 drivers/mtd/nand/raw/mxic_nand.c #define DMAM_CFG_CONT BIT(30) BIT 131 drivers/mtd/nand/raw/mxic_nand.c #define DMAM_CFG_DIR_READ BIT(1) BIT 132 drivers/mtd/nand/raw/mxic_nand.c #define DMAM_CFG_EN BIT(0) BIT 142 drivers/mtd/nand/raw/mxic_nand.c #define RDM_CFG1_RDM_EN BIT(31) BIT 146 drivers/mtd/nand/raw/mxic_nand.c #define LWR_SUSP_CTRL_EN BIT(31) BIT 149 drivers/mtd/nand/raw/mxic_nand.c #define DMAS_CTRL_EN BIT(31) BIT 150 drivers/mtd/nand/raw/mxic_nand.c #define DMAS_CTRL_DIR_READ BIT(30) BIT 153 drivers/mtd/nand/raw/mxic_nand.c #define DATA_STROB_EDO_EN BIT(2) BIT 154 drivers/mtd/nand/raw/mxic_nand.c #define DATA_STROB_INV_POL BIT(1) BIT 155 drivers/mtd/nand/raw/mxic_nand.c #define DATA_STROB_DELAY_2CYC BIT(0) BIT 161 drivers/mtd/nand/raw/mxic_nand.c #define GPIO_PT(x) BIT(3 + ((x) * 16)) BIT 162 drivers/mtd/nand/raw/mxic_nand.c #define GPIO_RESET(x) BIT(2 + ((x) * 16)) BIT 163 drivers/mtd/nand/raw/mxic_nand.c #define GPIO_HOLDB(x) BIT(1 + ((x) * 16)) BIT 164 drivers/mtd/nand/raw/mxic_nand.c #define GPIO_WPB(x) BIT((x) * 16) BIT 11 drivers/mtd/nand/raw/nand_macronix.c #define MACRONIX_READ_RETRY_BIT BIT(0) BIT 17 drivers/mtd/nand/raw/nand_micron.c #define NAND_ECC_STATUS_WRITE_RECOMMENDED BIT(3) BIT 33 drivers/mtd/nand/raw/nand_micron.c #define NAND_ECC_STATUS_MASK (BIT(4) | BIT(3) | BIT(0)) BIT 34 drivers/mtd/nand/raw/nand_micron.c #define NAND_ECC_STATUS_UNCORRECTABLE BIT(0) BIT 35 drivers/mtd/nand/raw/nand_micron.c #define NAND_ECC_STATUS_4_6_CORRECTED BIT(3) BIT 36 drivers/mtd/nand/raw/nand_micron.c #define NAND_ECC_STATUS_1_3_CORRECTED BIT(4) BIT 37 drivers/mtd/nand/raw/nand_micron.c #define NAND_ECC_STATUS_7_8_CORRECTED (BIT(4) | BIT(3)) BIT 359 drivers/mtd/nand/raw/nand_micron.c #define MICRON_ID_ECC_ENABLED BIT(7) BIT 125 drivers/mtd/nand/raw/nand_onfi.c if (srcbuf[i] & BIT(j)) BIT 130 drivers/mtd/nand/raw/nand_onfi.c val |= BIT(j); BIT 12 drivers/mtd/nand/raw/nand_toshiba.c #define TOSHIBA_NAND_ID4_IS_BENAND BIT(7) BIT 15 drivers/mtd/nand/raw/nand_toshiba.c #define TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED BIT(3) BIT 35 drivers/mtd/nand/raw/omap_elm.c #define INTR_STATUS_PAGE_VALID BIT(8) BIT 38 drivers/mtd/nand/raw/omap_elm.c #define INTR_EN_PAGE_MASK BIT(8) BIT 44 drivers/mtd/nand/raw/omap_elm.c #define ELM_SYNDROME_VALID BIT(16) BIT 47 drivers/mtd/nand/raw/omap_elm.c #define ECC_CORRECTABLE_MASK BIT(8) BIT 146 drivers/mtd/nand/raw/omap_elm.c reg_val |= BIT(index); /* enable page mode */ BIT 148 drivers/mtd/nand/raw/omap_elm.c reg_val &= ~BIT(index); /* disable page mode */ BIT 319 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, ELM_IRQSTATUS, BIT(i)); BIT 25 drivers/mtd/nand/raw/oxnas_nand.c #define OXNAS_NAND_CMD_ALE BIT(18) BIT 26 drivers/mtd/nand/raw/oxnas_nand.c #define OXNAS_NAND_CMD_CLE BIT(19) BIT 57 drivers/mtd/nand/raw/qcom_nandc.c #define PAGE_ACC BIT(4) BIT 58 drivers/mtd/nand/raw/qcom_nandc.c #define LAST_PAGE BIT(5) BIT 62 drivers/mtd/nand/raw/qcom_nandc.c #define DM_EN BIT(2) BIT 65 drivers/mtd/nand/raw/qcom_nandc.c #define FS_OP_ERR BIT(4) BIT 66 drivers/mtd/nand/raw/qcom_nandc.c #define FS_READY_BSY_N BIT(5) BIT 67 drivers/mtd/nand/raw/qcom_nandc.c #define FS_MPU_ERR BIT(8) BIT 68 drivers/mtd/nand/raw/qcom_nandc.c #define FS_DEVICE_STS_ERR BIT(16) BIT 69 drivers/mtd/nand/raw/qcom_nandc.c #define FS_DEVICE_WP BIT(23) BIT 72 drivers/mtd/nand/raw/qcom_nandc.c #define BS_UNCORRECTABLE_BIT BIT(8) BIT 107 drivers/mtd/nand/raw/qcom_nandc.c #define READ_START_VLD BIT(0) BIT 108 drivers/mtd/nand/raw/qcom_nandc.c #define READ_STOP_VLD BIT(1) BIT 109 drivers/mtd/nand/raw/qcom_nandc.c #define WRITE_START_VLD BIT(2) BIT 110 drivers/mtd/nand/raw/qcom_nandc.c #define ERASE_START_VLD BIT(3) BIT 111 drivers/mtd/nand/raw/qcom_nandc.c #define SEQ_READ_START_VLD BIT(4) BIT 126 drivers/mtd/nand/raw/qcom_nandc.c #define PAGE_ALL_ERASED BIT(7) BIT 127 drivers/mtd/nand/raw/qcom_nandc.c #define CODEWORD_ALL_ERASED BIT(6) BIT 128 drivers/mtd/nand/raw/qcom_nandc.c #define PAGE_ERASED BIT(5) BIT 129 drivers/mtd/nand/raw/qcom_nandc.c #define CODEWORD_ERASED BIT(4) BIT 160 drivers/mtd/nand/raw/qcom_nandc.c #define BAM_MODE_EN BIT(0) BIT 178 drivers/mtd/nand/raw/qcom_nandc.c #define ECC_NONE BIT(0) BIT 179 drivers/mtd/nand/raw/qcom_nandc.c #define ECC_RS_4BIT BIT(1) BIT 180 drivers/mtd/nand/raw/qcom_nandc.c #define ECC_BCH_4BIT BIT(2) BIT 181 drivers/mtd/nand/raw/qcom_nandc.c #define ECC_BCH_8BIT BIT(3) BIT 214 drivers/mtd/nand/raw/qcom_nandc.c #define NAND_BAM_NO_EOT BIT(0) BIT 216 drivers/mtd/nand/raw/qcom_nandc.c #define NAND_BAM_NWD BIT(1) BIT 218 drivers/mtd/nand/raw/qcom_nandc.c #define NAND_BAM_NEXT_SGL BIT(2) BIT 223 drivers/mtd/nand/raw/qcom_nandc.c #define NAND_ERASED_CW_SET BIT(4) BIT 1786 drivers/mtd/nand/raw/qcom_nandc.c uncorrectable_cws |= BIT(i); BIT 83 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCR1_FMC2EN BIT(31) BIT 86 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_PCR_PWAITEN BIT(1) BIT 87 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_PCR_PBKEN BIT(2) BIT 92 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_PCR_ECCEN BIT(6) BIT 93 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_PCR_ECCALG BIT(8) BIT 104 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_PCR_BCHECC BIT(24) BIT 105 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_PCR_WEN BIT(25) BIT 108 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_SR_NWRF BIT(6) BIT 125 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_ISR_IHLF BIT(1) BIT 128 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_ICR_CIHLF BIT(1) BIT 131 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCR_CSQSTART BIT(0) BIT 134 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR1_CMD2EN BIT(1) BIT 135 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR1_DMADEN BIT(2) BIT 139 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR1_CMD1T BIT(24) BIT 140 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR1_CMD2T BIT(25) BIT 143 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR2_SQSDTEN BIT(0) BIT 144 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR2_RCMD2EN BIT(1) BIT 145 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR2_DMASEN BIT(2) BIT 148 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR2_RCMD1T BIT(24) BIT 149 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR2_RCMD2T BIT(25) BIT 153 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR3_AC1T BIT(16) BIT 154 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR3_AC2T BIT(17) BIT 155 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR3_AC3T BIT(18) BIT 156 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR3_AC4T BIT(19) BIT 157 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR3_AC5T BIT(20) BIT 158 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR3_SDT BIT(21) BIT 159 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR3_RAC1T BIT(22) BIT 160 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQCFGR3_RAC2T BIT(23) BIT 174 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQIER_TCIE BIT(0) BIT 183 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHIER_DERIE BIT(1) BIT 184 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHIER_EPBRIE BIT(4) BIT 190 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR0_DUE BIT(0) BIT 191 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR0_DEF BIT(1) BIT 1106 drivers/mtd/nand/raw/stm32_fmc2_nand.c if (sta_map & BIT(s)) { BIT 1121 drivers/mtd/nand/raw/stm32_fmc2_nand.c if (sta_map & BIT(s)) BIT 1819 drivers/mtd/nand/raw/stm32_fmc2_nand.c if (fmc2->cs_assigned & BIT(cs)) { BIT 1824 drivers/mtd/nand/raw/stm32_fmc2_nand.c fmc2->cs_assigned |= BIT(cs); BIT 1893 drivers/mtd/nand/raw/stm32_fmc2_nand.c if (!(fmc2->cs_assigned & BIT(chip_cs))) BIT 2052 drivers/mtd/nand/raw/stm32_fmc2_nand.c if (!(fmc2->cs_assigned & BIT(chip_cs))) BIT 59 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_EN BIT(0) BIT 60 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RESET BIT(1) BIT 61 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_BUS_WIDTH_MSK BIT(2) BIT 64 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RB_SEL_MSK BIT(3) BIT 68 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_CE_CTL BIT(6) BIT 71 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_SAM BIT(12) BIT 72 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RAM_METHOD BIT(14) BIT 73 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_DMA_TYPE_NORMAL BIT(15) BIT 74 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_DEBUG_CTL BIT(31) BIT 77 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RB_B2R BIT(0) BIT 78 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_CMD_INT_FLAG BIT(1) BIT 79 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_DMA_INT_FLAG BIT(2) BIT 80 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_CMD_FIFO_STATUS BIT(3) BIT 81 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_STA BIT(4) BIT 82 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_NATCH_INT_FLAG BIT(5) BIT 83 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RB_STATE(x) BIT(x + 8) BIT 86 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_B2R_INT_ENABLE BIT(0) BIT 87 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_CMD_INT_ENABLE BIT(1) BIT 88 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_DMA_INT_ENABLE BIT(2) BIT 94 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_TIMING_CTL_EDO BIT(8) BIT 108 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_SEND_ADR BIT(19) BIT 109 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ACCESS_DIR BIT(20) BIT 110 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_DATA_TRANS BIT(21) BIT 111 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_SEND_CMD1 BIT(22) BIT 112 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_WAIT_FLAG BIT(23) BIT 113 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_SEND_CMD2 BIT(24) BIT 114 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_SEQ BIT(25) BIT 115 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_DATA_SWAP_METHOD BIT(26) BIT 116 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ROW_AUTO_INC BIT(27) BIT 117 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_SEND_CMD3 BIT(28) BIT 118 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_SEND_CMD4 BIT(29) BIT 136 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ECC_EN BIT(0) BIT 137 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ECC_PIPELINE BIT(3) BIT 138 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ECC_EXCEPTION BIT(4) BIT 139 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ECC_BLOCK_SIZE_MSK BIT(5) BIT 140 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ECC_BLOCK_512 BIT(5) BIT 141 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RANDOM_EN BIT(9) BIT 142 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RANDOM_DIRECTION BIT(10) BIT 149 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ECC_ERR(x) BIT(x) BIT 151 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ECC_PAT_FOUND(x) BIT(x + 16) BIT 36 drivers/mtd/nand/raw/tango_nand.c #define CMD_READY BIT(31) BIT 43 drivers/mtd/nand/raw/tango_nand.c #define PAGE_IS_EMPTY BIT(16) BIT 57 drivers/mtd/nand/raw/tango_nand.c #define DECODE_FAIL_PKT_0(v) (((v) & BIT(7)) == 0) BIT 58 drivers/mtd/nand/raw/tango_nand.c #define DECODE_FAIL_PKT_N(v) (((v) & BIT(15)) == 0) BIT 65 drivers/mtd/nand/raw/tango_nand.c #define PBUS_IORDY BIT(31) BIT 74 drivers/mtd/nand/raw/tango_nand.c #define MODE_NFC BIT(31) BIT 23 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_GO BIT(31) BIT 24 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_CLE BIT(30) BIT 25 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_ALE BIT(29) BIT 26 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_PIO BIT(28) BIT 27 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_TX BIT(27) BIT 28 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_RX BIT(26) BIT 29 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_SEC_CMD BIT(25) BIT 30 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_AFT_DAT BIT(24) BIT 32 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_A_VALID BIT(19) BIT 33 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_B_VALID BIT(18) BIT 34 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_RD_STATUS_CHK BIT(17) BIT 35 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_RBSY_CHK BIT(16) BIT 36 drivers/mtd/nand/raw/tegra_nand.c #define COMMAND_CE(x) BIT(8 + ((x) & 0x7)) BIT 43 drivers/mtd/nand/raw/tegra_nand.c #define ISR_CORRFAIL_ERR BIT(24) BIT 44 drivers/mtd/nand/raw/tegra_nand.c #define ISR_UND BIT(7) BIT 45 drivers/mtd/nand/raw/tegra_nand.c #define ISR_OVR BIT(6) BIT 46 drivers/mtd/nand/raw/tegra_nand.c #define ISR_CMD_DONE BIT(5) BIT 47 drivers/mtd/nand/raw/tegra_nand.c #define ISR_ECC_ERR BIT(4) BIT 51 drivers/mtd/nand/raw/tegra_nand.c #define IER_UND BIT(7) BIT 52 drivers/mtd/nand/raw/tegra_nand.c #define IER_OVR BIT(6) BIT 53 drivers/mtd/nand/raw/tegra_nand.c #define IER_CMD_DONE BIT(5) BIT 54 drivers/mtd/nand/raw/tegra_nand.c #define IER_ECC_ERR BIT(4) BIT 55 drivers/mtd/nand/raw/tegra_nand.c #define IER_GIE BIT(0) BIT 58 drivers/mtd/nand/raw/tegra_nand.c #define CONFIG_HW_ECC BIT(31) BIT 59 drivers/mtd/nand/raw/tegra_nand.c #define CONFIG_ECC_SEL BIT(30) BIT 60 drivers/mtd/nand/raw/tegra_nand.c #define CONFIG_ERR_COR BIT(29) BIT 61 drivers/mtd/nand/raw/tegra_nand.c #define CONFIG_PIPE_EN BIT(28) BIT 65 drivers/mtd/nand/raw/tegra_nand.c #define CONFIG_SKIP_SPARE BIT(23) BIT 66 drivers/mtd/nand/raw/tegra_nand.c #define CONFIG_BUS_WIDTH_16 BIT(21) BIT 67 drivers/mtd/nand/raw/tegra_nand.c #define CONFIG_COM_BSY BIT(20) BIT 101 drivers/mtd/nand/raw/tegra_nand.c #define DMA_MST_CTRL_GO BIT(31) BIT 103 drivers/mtd/nand/raw/tegra_nand.c #define DMA_MST_CTRL_OUT BIT(30) BIT 104 drivers/mtd/nand/raw/tegra_nand.c #define DMA_MST_CTRL_PERF_EN BIT(29) BIT 105 drivers/mtd/nand/raw/tegra_nand.c #define DMA_MST_CTRL_IE_DONE BIT(28) BIT 106 drivers/mtd/nand/raw/tegra_nand.c #define DMA_MST_CTRL_REUSE BIT(27) BIT 111 drivers/mtd/nand/raw/tegra_nand.c #define DMA_MST_CTRL_IS_DONE BIT(20) BIT 112 drivers/mtd/nand/raw/tegra_nand.c #define DMA_MST_CTRL_EN_A BIT(2) BIT 113 drivers/mtd/nand/raw/tegra_nand.c #define DMA_MST_CTRL_EN_B BIT(1) BIT 119 drivers/mtd/nand/raw/tegra_nand.c #define FIFO_CTRL_CLR_ALL BIT(3) BIT 126 drivers/mtd/nand/raw/tegra_nand.c #define DEC_STATUS_A_ECC_FAIL BIT(1) BIT 138 drivers/mtd/nand/raw/tegra_nand.c #define BCH_ENABLE BIT(0) BIT 60 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_CMD_BYTE1 BIT(14) BIT 61 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_CAR_BYTE1 BIT(13) BIT 62 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_CAR_BYTE2 BIT(12) BIT 63 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_RAR_BYTE1 BIT(11) BIT 64 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_RAR_BYTE2 BIT(10) BIT 65 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_RAR_BYTE3 BIT(9) BIT 67 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_WRITE_DATA BIT(8) BIT 68 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_CMD_BYTE2 BIT(7) BIT 69 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_RB_HANDSHAKE BIT(6) BIT 70 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_READ_DATA BIT(5) BIT 71 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_CMD_BYTE3 BIT(4) BIT 72 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_READ_STATUS BIT(3) BIT 73 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_READ_ID BIT(2) BIT 93 drivers/mtd/nand/raw/vf610_nfc.c #define START_BIT BIT(0) BIT 116 drivers/mtd/nand/raw/vf610_nfc.c #define CONFIG_ECC_SRAM_REQ_BIT BIT(21) BIT 117 drivers/mtd/nand/raw/vf610_nfc.c #define CONFIG_DMA_REQ_BIT BIT(20) BIT 120 drivers/mtd/nand/raw/vf610_nfc.c #define CONFIG_FAST_FLASH_BIT BIT(16) BIT 121 drivers/mtd/nand/raw/vf610_nfc.c #define CONFIG_16BIT BIT(7) BIT 122 drivers/mtd/nand/raw/vf610_nfc.c #define CONFIG_BOOT_MODE_BIT BIT(6) BIT 123 drivers/mtd/nand/raw/vf610_nfc.c #define CONFIG_ADDR_AUTO_INCR_BIT BIT(5) BIT 124 drivers/mtd/nand/raw/vf610_nfc.c #define CONFIG_BUFNO_AUTO_INCR_BIT BIT(4) BIT 129 drivers/mtd/nand/raw/vf610_nfc.c #define IDLE_IRQ_BIT BIT(29) BIT 130 drivers/mtd/nand/raw/vf610_nfc.c #define IDLE_EN_BIT BIT(20) BIT 131 drivers/mtd/nand/raw/vf610_nfc.c #define CMD_DONE_CLEAR_BIT BIT(18) BIT 132 drivers/mtd/nand/raw/vf610_nfc.c #define IDLE_CLEAR_BIT BIT(17) BIT 496 drivers/mtd/nand/raw/vf610_nfc.c tmp |= BIT(cs) << ROW_ADDR_CHIP_SEL_SHIFT; BIT 18 drivers/mtd/nand/raw/xway_nand.c #define NAND_WAIT_RD BIT(0) /* NAND flash status output */ BIT 19 drivers/mtd/nand/raw/xway_nand.c #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */ BIT 31 drivers/mtd/nand/raw/xway_nand.c #define NAND_CMD_ALE BIT(2) /* address latch enable */ BIT 32 drivers/mtd/nand/raw/xway_nand.c #define NAND_CMD_CLE BIT(3) /* command latch enable */ BIT 33 drivers/mtd/nand/raw/xway_nand.c #define NAND_CMD_CS BIT(4) /* chip select */ BIT 34 drivers/mtd/nand/raw/xway_nand.c #define NAND_CMD_SE BIT(5) /* spare area access latch */ BIT 35 drivers/mtd/nand/raw/xway_nand.c #define NAND_CMD_WP BIT(6) /* write protect */ BIT 16 drivers/mtd/nand/spi/winbond.c #define WINBOND_CFG_BUF_READ BIT(3) BIT 89 drivers/mtd/parsers/sharpslpart.c freebytes |= BIT(i - 8); BIT 123 drivers/mtd/spi-nor/aspeed-smc.c #define CONFIG_DISABLE_LEGACY BIT(31) /* 1 */ BIT 125 drivers/mtd/spi-nor/aspeed-smc.c #define CONFIG_CE2_WRITE BIT(18) BIT 126 drivers/mtd/spi-nor/aspeed-smc.c #define CONFIG_CE1_WRITE BIT(17) BIT 127 drivers/mtd/spi-nor/aspeed-smc.c #define CONFIG_CE0_WRITE BIT(16) BIT 129 drivers/mtd/spi-nor/aspeed-smc.c #define CONFIG_CE2_TYPE BIT(4) /* AST2500 FMC only */ BIT 130 drivers/mtd/spi-nor/aspeed-smc.c #define CONFIG_CE1_TYPE BIT(2) /* AST2500 FMC only */ BIT 131 drivers/mtd/spi-nor/aspeed-smc.c #define CONFIG_CE0_TYPE BIT(0) /* AST2500 FMC only */ BIT 141 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_AAF_MODE BIT(31) BIT 143 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_IO_DUAL_DATA BIT(29) BIT 144 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) BIT 145 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_IO_QUAD_DATA BIT(30) BIT 146 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28)) BIT 152 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_DUMMY_COMMAND_OUT BIT(15) BIT 153 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_IO_DUMMY_HI BIT(14) BIT 155 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_CLK_DIV4 BIT(13) /* others */ BIT 156 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI */ BIT 157 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_RW_MERGE BIT(12) BIT 170 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_LSB_FIRST BIT(5) BIT 171 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_CLOCK_MODE_3 BIT(4) BIT 172 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_IN_DUAL_DATA BIT(3) BIT 173 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_CE_STOP_ACTIVE_CONTROL BIT(2) BIT 258 drivers/mtd/spi-nor/aspeed-smc.c return BIT(chip->controller->info->we0 + chip->cs); BIT 36 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_NEEDS_WR_DELAY BIT(0) BIT 116 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) BIT 117 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) BIT 118 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) BIT 120 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) BIT 188 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) BIT 189 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) BIT 190 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) BIT 197 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) BIT 198 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) BIT 211 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) BIT 212 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) BIT 213 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) BIT 226 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_IRQ_MODE_ERR BIT(0) BIT 227 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) BIT 228 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_IRQ_IND_COMP BIT(2) BIT 229 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) BIT 230 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) BIT 231 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) BIT 232 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_IRQ_WATERMARK BIT(6) BIT 233 drivers/mtd/spi-nor/cadence-quadspi.c #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) BIT 31 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_GLOBAL_CFG_WP_ENABLE BIT(6) BIT 40 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_INT_OP_DONE BIT(0) BIT 53 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_OP_DUMMY_EN BIT(8) BIT 54 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_OP_CMD1_EN BIT(7) BIT 55 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_OP_ADDR_EN BIT(6) BIT 56 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_OP_WRITE_DATA_EN BIT(5) BIT 57 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_OP_READ_DATA_EN BIT(2) BIT 58 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_OP_READ_STATUS_EN BIT(1) BIT 59 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_OP_REG_OP_START BIT(0) BIT 69 drivers/mtd/spi-nor/hisi-sfc.c #define OP_CTRL_DMA_OP_READY BIT(0) BIT 17 drivers/mtd/spi-nor/intel-spi-pci.c #define BCR_WPD BIT(0) BIT 26 drivers/mtd/spi-nor/intel-spi.c #define HSFSTS_CTL_FSMIE BIT(31) BIT 41 drivers/mtd/spi-nor/intel-spi.c #define HSFSTS_CTL_FGO BIT(16) BIT 42 drivers/mtd/spi-nor/intel-spi.c #define HSFSTS_CTL_FLOCKDN BIT(15) BIT 43 drivers/mtd/spi-nor/intel-spi.c #define HSFSTS_CTL_FDV BIT(14) BIT 44 drivers/mtd/spi-nor/intel-spi.c #define HSFSTS_CTL_SCIP BIT(5) BIT 45 drivers/mtd/spi-nor/intel-spi.c #define HSFSTS_CTL_AEL BIT(2) BIT 46 drivers/mtd/spi-nor/intel-spi.c #define HSFSTS_CTL_FCERR BIT(1) BIT 47 drivers/mtd/spi-nor/intel-spi.c #define HSFSTS_CTL_FDONE BIT(0) BIT 62 drivers/mtd/spi-nor/intel-spi.c #define PR_WPE BIT(31) BIT 65 drivers/mtd/spi-nor/intel-spi.c #define PR_RPE BIT(15) BIT 70 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_FSMIE BIT(23) BIT 71 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_DS BIT(22) BIT 73 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_SPOP BIT(11) BIT 74 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_ACS BIT(10) BIT 75 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_SCGO BIT(9) BIT 77 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_FRS BIT(7) BIT 78 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_DOFRS BIT(6) BIT 79 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_AEL BIT(4) BIT 80 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_FCERR BIT(3) BIT 81 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_FDONE BIT(2) BIT 82 drivers/mtd/spi-nor/intel-spi.c #define SSFSTS_CTL_SCIP BIT(0) BIT 97 drivers/mtd/spi-nor/intel-spi.c #define BYT_BCR_WPD BIT(0) BIT 99 drivers/mtd/spi-nor/mtk-quadspi.c #define MTK_NOR_4B_ADDR_EN BIT(4) BIT 28 drivers/mtd/spi-nor/nxp-spifi.c #define SPIFI_CTRL_MODE3 BIT(23) BIT 29 drivers/mtd/spi-nor/nxp-spifi.c #define SPIFI_CTRL_DUAL BIT(28) BIT 30 drivers/mtd/spi-nor/nxp-spifi.c #define SPIFI_CTRL_FBCLK BIT(30) BIT 33 drivers/mtd/spi-nor/nxp-spifi.c #define SPIFI_CMD_DOUT BIT(15) BIT 47 drivers/mtd/spi-nor/nxp-spifi.c #define SPIFI_STAT_MCINIT BIT(0) BIT 48 drivers/mtd/spi-nor/nxp-spifi.c #define SPIFI_STAT_CMD BIT(1) BIT 49 drivers/mtd/spi-nor/nxp-spifi.c #define SPIFI_STAT_RESET BIT(4) BIT 92 drivers/mtd/spi-nor/spi-nor.c #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) BIT 97 drivers/mtd/spi-nor/spi-nor.c #define BFPT_DWORD1_DTR BIT(19) BIT 98 drivers/mtd/spi-nor/spi-nor.c #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) BIT 99 drivers/mtd/spi-nor/spi-nor.c #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) BIT 100 drivers/mtd/spi-nor/spi-nor.c #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) BIT 103 drivers/mtd/spi-nor/spi-nor.c #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) BIT 104 drivers/mtd/spi-nor/spi-nor.c #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) BIT 200 drivers/mtd/spi-nor/spi-nor.c #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ BIT 201 drivers/mtd/spi-nor/spi-nor.c #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ BIT 202 drivers/mtd/spi-nor/spi-nor.c #define SST_WRITE BIT(2) /* use SST byte programming */ BIT 203 drivers/mtd/spi-nor/spi-nor.c #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ BIT 204 drivers/mtd/spi-nor/spi-nor.c #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ BIT 205 drivers/mtd/spi-nor/spi-nor.c #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ BIT 206 drivers/mtd/spi-nor/spi-nor.c #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ BIT 207 drivers/mtd/spi-nor/spi-nor.c #define USE_FSR BIT(7) /* use flag status register */ BIT 208 drivers/mtd/spi-nor/spi-nor.c #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ BIT 209 drivers/mtd/spi-nor/spi-nor.c #define SPI_NOR_HAS_TB BIT(9) /* BIT 214 drivers/mtd/spi-nor/spi-nor.c #define SPI_NOR_XSR_RDY BIT(10) /* BIT 222 drivers/mtd/spi-nor/spi-nor.c #define SPI_S3AN BIT(10) /* BIT 228 drivers/mtd/spi-nor/spi-nor.c #define SPI_NOR_4B_OPCODES BIT(11) /* BIT 232 drivers/mtd/spi-nor/spi-nor.c #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ BIT 233 drivers/mtd/spi-nor/spi-nor.c #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ BIT 234 drivers/mtd/spi-nor/spi-nor.c #define USE_CLSR BIT(14) /* use CLSR command */ BIT 235 drivers/mtd/spi-nor/spi-nor.c #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ BIT 1009 drivers/mtd/spi-nor/spi-nor.c if (!(erase_mask & BIT(i))) BIT 3023 drivers/mtd/spi-nor/spi-nor.c if (!(*hwcaps & BIT(cap))) BIT 3026 drivers/mtd/spi-nor/spi-nor.c rdidx = spi_nor_hwcaps_read2cmd(BIT(cap)); BIT 3029 drivers/mtd/spi-nor/spi-nor.c *hwcaps &= ~BIT(cap); BIT 3031 drivers/mtd/spi-nor/spi-nor.c ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap)); BIT 3037 drivers/mtd/spi-nor/spi-nor.c *hwcaps &= ~BIT(cap); BIT 3111 drivers/mtd/spi-nor/spi-nor.c BFPT_DWORD(1), BIT(16), /* Supported bit */ BIT 3119 drivers/mtd/spi-nor/spi-nor.c BFPT_DWORD(1), BIT(20), /* Supported bit */ BIT 3127 drivers/mtd/spi-nor/spi-nor.c BFPT_DWORD(5), BIT(0), /* Supported bit */ BIT 3135 drivers/mtd/spi-nor/spi-nor.c BFPT_DWORD(1), BIT(22), /* Supported bit */ BIT 3143 drivers/mtd/spi-nor/spi-nor.c BFPT_DWORD(1), BIT(21), /* Supported bit */ BIT 3151 drivers/mtd/spi-nor/spi-nor.c BFPT_DWORD(5), BIT(4), /* Supported bit */ BIT 3257 drivers/mtd/spi-nor/spi-nor.c if (erase_type[i].size && erase_mask & BIT(erase_type[i].idx)) BIT 3258 drivers/mtd/spi-nor/spi-nor.c sorted_erase_mask |= BIT(i); BIT 3401 drivers/mtd/spi-nor/spi-nor.c if (params->size & BIT(31)) { BIT 3402 drivers/mtd/spi-nor/spi-nor.c params->size &= ~BIT(31); BIT 3455 drivers/mtd/spi-nor/spi-nor.c erase_mask |= BIT(i); BIT 3559 drivers/mtd/spi-nor/spi-nor.c #define SMPT_DESC_TYPE_MAP BIT(1) BIT 3560 drivers/mtd/spi-nor/spi-nor.c #define SMPT_DESC_END BIT(0) BIT 3703 drivers/mtd/spi-nor/spi-nor.c if (!(erase_type & BIT(i))) BIT 3793 drivers/mtd/spi-nor/spi-nor.c if (!(regions_erase_type & BIT(erase[i].idx))) BIT 3883 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_READ, BIT(0) }, BIT 3884 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_READ_FAST, BIT(1) }, BIT 3885 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_READ_1_1_2, BIT(2) }, BIT 3886 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_READ_1_2_2, BIT(3) }, BIT 3887 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_READ_1_1_4, BIT(4) }, BIT 3888 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_READ_1_4_4, BIT(5) }, BIT 3889 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_READ_1_1_1_DTR, BIT(13) }, BIT 3890 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_READ_1_2_2_DTR, BIT(14) }, BIT 3891 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_READ_1_4_4_DTR, BIT(15) }, BIT 3894 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_PP, BIT(6) }, BIT 3895 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_PP_1_1_4, BIT(7) }, BIT 3896 drivers/mtd/spi-nor/spi-nor.c { SNOR_HWCAPS_PP_1_4_4, BIT(8) }, BIT 3899 drivers/mtd/spi-nor/spi-nor.c { 0u /* not used */, BIT(9) }, BIT 3900 drivers/mtd/spi-nor/spi-nor.c { 0u /* not used */, BIT(10) }, BIT 3901 drivers/mtd/spi-nor/spi-nor.c { 0u /* not used */, BIT(11) }, BIT 3902 drivers/mtd/spi-nor/spi-nor.c { 0u /* not used */, BIT(12) }, BIT 3976 drivers/mtd/spi-nor/spi-nor.c erase_mask |= BIT(i); BIT 4018 drivers/mtd/spi-nor/spi-nor.c if (erase_mask & BIT(i)) BIT 4173 drivers/mtd/spi-nor/spi-nor.c cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); BIT 4204 drivers/mtd/spi-nor/spi-nor.c cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); BIT 4235 drivers/mtd/spi-nor/spi-nor.c if (!(uniform_erase_type & BIT(i))) BIT 4263 drivers/mtd/spi-nor/spi-nor.c map->uniform_erase_type |= BIT(erase - map->erase_type); BIT 4530 drivers/mtd/spi-nor/spi-nor.c erase_mask |= BIT(i); BIT 4535 drivers/mtd/spi-nor/spi-nor.c erase_mask |= BIT(i); BIT 4540 drivers/mtd/spi-nor/spi-nor.c erase_mask |= BIT(i); BIT 81 drivers/mtd/ubi/attach.c #define AV_FIND BIT(0) BIT 82 drivers/mtd/ubi/attach.c #define AV_ADD BIT(1) BIT 16 drivers/mux/adg792a.c #define ADG792A_LDSW BIT(0) BIT 17 drivers/mux/adg792a.c #define ADG792A_RESETB BIT(1) BIT 220 drivers/net/bonding/bond_options.c .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_ROUNDROBIN)), BIT 235 drivers/net/bonding/bond_options.c .unsuppmodes = BIT(BOND_MODE_8023AD) | BIT(BOND_MODE_TLB) | BIT 236 drivers/net/bonding/bond_options.c BIT(BOND_MODE_ALB), BIT 259 drivers/net/bonding/bond_options.c .unsuppmodes = BIT(BOND_MODE_8023AD) | BIT(BOND_MODE_TLB) | BIT 260 drivers/net/bonding/bond_options.c BIT(BOND_MODE_ALB), BIT 290 drivers/net/bonding/bond_options.c .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_8023AD)), BIT 328 drivers/net/bonding/bond_options.c .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_ACTIVEBACKUP) | BIT 329 drivers/net/bonding/bond_options.c BIT(BOND_MODE_TLB) | BIT 330 drivers/net/bonding/bond_options.c BIT(BOND_MODE_ALB)), BIT 352 drivers/net/bonding/bond_options.c .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_ACTIVEBACKUP) | BIT 353 drivers/net/bonding/bond_options.c BIT(BOND_MODE_TLB) | BIT 354 drivers/net/bonding/bond_options.c BIT(BOND_MODE_ALB)), BIT 396 drivers/net/bonding/bond_options.c .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_TLB) | BIT(BOND_MODE_ALB)), BIT 404 drivers/net/bonding/bond_options.c .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_8023AD)), BIT 411 drivers/net/bonding/bond_options.c .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_8023AD)), BIT 418 drivers/net/bonding/bond_options.c .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_8023AD)), BIT 56 drivers/net/can/at91_can.c #define AT91_MR_CANEN BIT(0) BIT 57 drivers/net/can/at91_can.c #define AT91_MR_LPM BIT(1) BIT 58 drivers/net/can/at91_can.c #define AT91_MR_ABM BIT(2) BIT 59 drivers/net/can/at91_can.c #define AT91_MR_OVL BIT(3) BIT 60 drivers/net/can/at91_can.c #define AT91_MR_TEOF BIT(4) BIT 61 drivers/net/can/at91_can.c #define AT91_MR_TTM BIT(5) BIT 62 drivers/net/can/at91_can.c #define AT91_MR_TIMFRZ BIT(6) BIT 63 drivers/net/can/at91_can.c #define AT91_MR_DRPT BIT(7) BIT 65 drivers/net/can/at91_can.c #define AT91_SR_RBSY BIT(29) BIT 69 drivers/net/can/at91_can.c #define AT91_MID_MIDE BIT(29) BIT 71 drivers/net/can/at91_can.c #define AT91_MSR_MRTR BIT(20) BIT 72 drivers/net/can/at91_can.c #define AT91_MSR_MABT BIT(22) BIT 73 drivers/net/can/at91_can.c #define AT91_MSR_MRDY BIT(23) BIT 74 drivers/net/can/at91_can.c #define AT91_MSR_MMI BIT(24) BIT 76 drivers/net/can/at91_can.c #define AT91_MCR_MRTR BIT(20) BIT 77 drivers/net/can/at91_can.c #define AT91_MCR_MTCR BIT(23) BIT 52 drivers/net/can/c_can/c_can.c #define CONTROL_EX_PDR BIT(8) BIT 55 drivers/net/can/c_can/c_can.c #define CONTROL_SWR BIT(15) BIT 56 drivers/net/can/c_can/c_can.c #define CONTROL_TEST BIT(7) BIT 57 drivers/net/can/c_can/c_can.c #define CONTROL_CCE BIT(6) BIT 58 drivers/net/can/c_can/c_can.c #define CONTROL_DISABLE_AR BIT(5) BIT 60 drivers/net/can/c_can/c_can.c #define CONTROL_EIE BIT(3) BIT 61 drivers/net/can/c_can/c_can.c #define CONTROL_SIE BIT(2) BIT 62 drivers/net/can/c_can/c_can.c #define CONTROL_IE BIT(1) BIT 63 drivers/net/can/c_can/c_can.c #define CONTROL_INIT BIT(0) BIT 68 drivers/net/can/c_can/c_can.c #define TEST_RX BIT(7) BIT 69 drivers/net/can/c_can/c_can.c #define TEST_TX1 BIT(6) BIT 70 drivers/net/can/c_can/c_can.c #define TEST_TX2 BIT(5) BIT 71 drivers/net/can/c_can/c_can.c #define TEST_LBACK BIT(4) BIT 72 drivers/net/can/c_can/c_can.c #define TEST_SILENT BIT(3) BIT 73 drivers/net/can/c_can/c_can.c #define TEST_BASIC BIT(2) BIT 76 drivers/net/can/c_can/c_can.c #define STATUS_PDA BIT(10) BIT 77 drivers/net/can/c_can/c_can.c #define STATUS_BOFF BIT(7) BIT 78 drivers/net/can/c_can/c_can.c #define STATUS_EWARN BIT(6) BIT 79 drivers/net/can/c_can/c_can.c #define STATUS_EPASS BIT(5) BIT 80 drivers/net/can/c_can/c_can.c #define STATUS_RXOK BIT(4) BIT 81 drivers/net/can/c_can/c_can.c #define STATUS_TXOK BIT(3) BIT 109 drivers/net/can/c_can/c_can.c #define IF_COMR_BUSY BIT(15) BIT 112 drivers/net/can/c_can/c_can.c #define IF_COMM_WR BIT(7) BIT 113 drivers/net/can/c_can/c_can.c #define IF_COMM_MASK BIT(6) BIT 114 drivers/net/can/c_can/c_can.c #define IF_COMM_ARB BIT(5) BIT 115 drivers/net/can/c_can/c_can.c #define IF_COMM_CONTROL BIT(4) BIT 116 drivers/net/can/c_can/c_can.c #define IF_COMM_CLR_INT_PND BIT(3) BIT 117 drivers/net/can/c_can/c_can.c #define IF_COMM_TXRQST BIT(2) BIT 119 drivers/net/can/c_can/c_can.c #define IF_COMM_DATAA BIT(1) BIT 120 drivers/net/can/c_can/c_can.c #define IF_COMM_DATAB BIT(0) BIT 143 drivers/net/can/c_can/c_can.c #define IF_ARB_MSGVAL BIT(31) BIT 144 drivers/net/can/c_can/c_can.c #define IF_ARB_MSGXTD BIT(30) BIT 145 drivers/net/can/c_can/c_can.c #define IF_ARB_TRANSMIT BIT(29) BIT 148 drivers/net/can/c_can/c_can.c #define IF_MCONT_NEWDAT BIT(15) BIT 149 drivers/net/can/c_can/c_can.c #define IF_MCONT_MSGLST BIT(14) BIT 150 drivers/net/can/c_can/c_can.c #define IF_MCONT_INTPND BIT(13) BIT 151 drivers/net/can/c_can/c_can.c #define IF_MCONT_UMASK BIT(12) BIT 152 drivers/net/can/c_can/c_can.c #define IF_MCONT_TXIE BIT(11) BIT 153 drivers/net/can/c_can/c_can.c #define IF_MCONT_RXIE BIT(10) BIT 154 drivers/net/can/c_can/c_can.c #define IF_MCONT_RMTEN BIT(9) BIT 155 drivers/net/can/c_can/c_can.c #define IF_MCONT_TXRQST BIT(8) BIT 156 drivers/net/can/c_can/c_can.c #define IF_MCONT_EOB BIT(7) BIT 452 drivers/net/can/c_can/c_can.c mask |= BIT(29); BIT 814 drivers/net/can/c_can/c_can.c pend &= ~BIT(obj - 1); BIT 37 drivers/net/can/flexcan.c #define FLEXCAN_MCR_MDIS BIT(31) BIT 38 drivers/net/can/flexcan.c #define FLEXCAN_MCR_FRZ BIT(30) BIT 39 drivers/net/can/flexcan.c #define FLEXCAN_MCR_FEN BIT(29) BIT 40 drivers/net/can/flexcan.c #define FLEXCAN_MCR_HALT BIT(28) BIT 41 drivers/net/can/flexcan.c #define FLEXCAN_MCR_NOT_RDY BIT(27) BIT 42 drivers/net/can/flexcan.c #define FLEXCAN_MCR_WAK_MSK BIT(26) BIT 43 drivers/net/can/flexcan.c #define FLEXCAN_MCR_SOFTRST BIT(25) BIT 44 drivers/net/can/flexcan.c #define FLEXCAN_MCR_FRZ_ACK BIT(24) BIT 45 drivers/net/can/flexcan.c #define FLEXCAN_MCR_SUPV BIT(23) BIT 46 drivers/net/can/flexcan.c #define FLEXCAN_MCR_SLF_WAK BIT(22) BIT 47 drivers/net/can/flexcan.c #define FLEXCAN_MCR_WRN_EN BIT(21) BIT 48 drivers/net/can/flexcan.c #define FLEXCAN_MCR_LPM_ACK BIT(20) BIT 49 drivers/net/can/flexcan.c #define FLEXCAN_MCR_WAK_SRC BIT(19) BIT 50 drivers/net/can/flexcan.c #define FLEXCAN_MCR_DOZE BIT(18) BIT 51 drivers/net/can/flexcan.c #define FLEXCAN_MCR_SRX_DIS BIT(17) BIT 52 drivers/net/can/flexcan.c #define FLEXCAN_MCR_IRMQ BIT(16) BIT 53 drivers/net/can/flexcan.c #define FLEXCAN_MCR_LPRIO_EN BIT(13) BIT 54 drivers/net/can/flexcan.c #define FLEXCAN_MCR_AEN BIT(12) BIT 67 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_BOFF_MSK BIT(15) BIT 68 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_ERR_MSK BIT(14) BIT 69 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_CLK_SRC BIT(13) BIT 70 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_LPB BIT(12) BIT 71 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_TWRN_MSK BIT(11) BIT 72 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_RWRN_MSK BIT(10) BIT 73 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_SMP BIT(7) BIT 74 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_BOFF_REC BIT(6) BIT 75 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_TSYN BIT(5) BIT 76 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_LBUF BIT(4) BIT 77 drivers/net/can/flexcan.c #define FLEXCAN_CTRL_LOM BIT(3) BIT 87 drivers/net/can/flexcan.c #define FLEXCAN_CTRL2_ECRWRE BIT(29) BIT 88 drivers/net/can/flexcan.c #define FLEXCAN_CTRL2_WRMFRZ BIT(28) BIT 91 drivers/net/can/flexcan.c #define FLEXCAN_CTRL2_MRP BIT(18) BIT 92 drivers/net/can/flexcan.c #define FLEXCAN_CTRL2_RRS BIT(17) BIT 93 drivers/net/can/flexcan.c #define FLEXCAN_CTRL2_EACEN BIT(16) BIT 96 drivers/net/can/flexcan.c #define FLEXCAN_MECR_ECRWRDIS BIT(31) BIT 97 drivers/net/can/flexcan.c #define FLEXCAN_MECR_HANCEI_MSK BIT(19) BIT 98 drivers/net/can/flexcan.c #define FLEXCAN_MECR_FANCEI_MSK BIT(18) BIT 99 drivers/net/can/flexcan.c #define FLEXCAN_MECR_CEI_MSK BIT(16) BIT 100 drivers/net/can/flexcan.c #define FLEXCAN_MECR_HAERRIE BIT(15) BIT 101 drivers/net/can/flexcan.c #define FLEXCAN_MECR_FAERRIE BIT(14) BIT 102 drivers/net/can/flexcan.c #define FLEXCAN_MECR_EXTERRIE BIT(13) BIT 103 drivers/net/can/flexcan.c #define FLEXCAN_MECR_RERRDIS BIT(9) BIT 104 drivers/net/can/flexcan.c #define FLEXCAN_MECR_ECCDIS BIT(8) BIT 105 drivers/net/can/flexcan.c #define FLEXCAN_MECR_NCEFAFRZ BIT(7) BIT 108 drivers/net/can/flexcan.c #define FLEXCAN_ESR_TWRN_INT BIT(17) BIT 109 drivers/net/can/flexcan.c #define FLEXCAN_ESR_RWRN_INT BIT(16) BIT 110 drivers/net/can/flexcan.c #define FLEXCAN_ESR_BIT1_ERR BIT(15) BIT 111 drivers/net/can/flexcan.c #define FLEXCAN_ESR_BIT0_ERR BIT(14) BIT 112 drivers/net/can/flexcan.c #define FLEXCAN_ESR_ACK_ERR BIT(13) BIT 113 drivers/net/can/flexcan.c #define FLEXCAN_ESR_CRC_ERR BIT(12) BIT 114 drivers/net/can/flexcan.c #define FLEXCAN_ESR_FRM_ERR BIT(11) BIT 115 drivers/net/can/flexcan.c #define FLEXCAN_ESR_STF_ERR BIT(10) BIT 116 drivers/net/can/flexcan.c #define FLEXCAN_ESR_TX_WRN BIT(9) BIT 117 drivers/net/can/flexcan.c #define FLEXCAN_ESR_RX_WRN BIT(8) BIT 118 drivers/net/can/flexcan.c #define FLEXCAN_ESR_IDLE BIT(7) BIT 119 drivers/net/can/flexcan.c #define FLEXCAN_ESR_TXRX BIT(6) BIT 124 drivers/net/can/flexcan.c #define FLEXCAN_ESR_BOFF_INT BIT(2) BIT 125 drivers/net/can/flexcan.c #define FLEXCAN_ESR_ERR_INT BIT(1) BIT 126 drivers/net/can/flexcan.c #define FLEXCAN_ESR_WAK_INT BIT(0) BIT 145 drivers/net/can/flexcan.c #define FLEXCAN_IFLAG_MB(x) BIT((x) & 0x1f) BIT 146 drivers/net/can/flexcan.c #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) BIT 147 drivers/net/can/flexcan.c #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) BIT 148 drivers/net/can/flexcan.c #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) BIT 164 drivers/net/can/flexcan.c #define FLEXCAN_MB_CNT_SRR BIT(22) BIT 165 drivers/net/can/flexcan.c #define FLEXCAN_MB_CNT_IDE BIT(21) BIT 166 drivers/net/can/flexcan.c #define FLEXCAN_MB_CNT_RTR BIT(20) BIT 187 drivers/net/can/flexcan.c #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */ BIT 188 drivers/net/can/flexcan.c #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */ BIT 189 drivers/net/can/flexcan.c #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */ BIT 190 drivers/net/can/flexcan.c #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */ BIT 191 drivers/net/can/flexcan.c #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */ BIT 192 drivers/net/can/flexcan.c #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */ BIT 193 drivers/net/can/flexcan.c #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7) /* default to BE register access */ BIT 194 drivers/net/can/flexcan.c #define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8) /* Setup stop mode to support wakeup */ BIT 847 drivers/net/can/flexcan.c priv->write(BIT(n), ®s->iflag1); BIT 849 drivers/net/can/flexcan.c priv->write(BIT(n - 32), ®s->iflag2); BIT 29 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_ENABLE BIT(0) BIT 30 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_ERROR_ACTIVE BIT(2) BIT 31 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_ERROR_PASSIVE BIT(3) BIT 32 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_BUSOFF BIT(4) BIT 33 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_ERROR_WARNING BIT(5) BIT 34 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_BUSMONITOR BIT(16) BIT 35 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_LOOPBACK BIT(18) BIT 36 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_DISABLE_CANFD BIT(24) BIT 37 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_ENABLE_ISO BIT(25) BIT 38 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_ENABLE_7_9_8_8_TIMING BIT(26) BIT 39 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_STCMD_NORMAL_MODE ((u32)BIT(31)) BIT 42 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_RXSTCMD_REMOVE_MSG BIT(0) BIT 43 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_RXSTCMD_RESET BIT(7) BIT 44 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_RXSTCMD_EMPTY BIT(8) BIT 45 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_RXSTCMD_OVERFLOW BIT(13) BIT 48 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TXSTCMD_ADD_MSG BIT(0) BIT 49 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TXSTCMD_HIGH_PRIO BIT(1) BIT 50 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TXSTCMD_RESET BIT(7) BIT 51 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TXSTCMD_EMPTY BIT(8) BIT 52 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TXSTCMD_FULL BIT(12) BIT 53 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TXSTCMD_OVERFLOW BIT(13) BIT 56 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_INTERRUPT_ERROR_BUSOFF BIT(0) BIT 57 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_INTERRUPT_ERROR_WARNING BIT(1) BIT 58 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_INTERRUPT_ERROR_STATE_CHG BIT(2) BIT 59 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_INTERRUPT_ERROR_REC_TEC_INC BIT(3) BIT 60 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_INTERRUPT_ERROR_COUNTER BIT(10) BIT 61 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_INTERRUPT_TXFIFO_EMPTY BIT(16) BIT 62 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_INTERRUPT_TXFIFO_REMOVE BIT(22) BIT 63 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_INTERRUPT_RXFIFO_NEMPTY BIT(24) BIT 64 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_INTERRUPT_RXFIFO_NEMPTY_PER BIT(25) BIT 65 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_INTERRUPT_SET_IRQ ((u32)BIT(31)) BIT 68 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_IRQMASK_ERROR_BUSOFF BIT(0) BIT 69 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_IRQMASK_ERROR_WARNING BIT(1) BIT 70 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_IRQMASK_ERROR_STATE_CHG BIT(2) BIT 71 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_IRQMASK_ERROR_REC_TEC_INC BIT(3) BIT 72 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_IRQMASK_SET_ERR BIT(7) BIT 73 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_IRQMASK_SET_TS BIT(15) BIT 74 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_IRQMASK_TXFIFO_EMPTY BIT(16) BIT 75 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_IRQMASK_SET_TX BIT(23) BIT 76 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_IRQMASK_RXFIFO_NEMPTY BIT(24) BIT 77 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_IRQMASK_SET_RX ((u32)BIT(31)) BIT 86 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TIME_SET_SJW_4_12_6_6 BIT(6) BIT 87 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TIME_SET_TIMEB_4_12_6_6 BIT(7) BIT 88 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TIME_SET_PRESC_4_12_6_6 BIT(14) BIT 89 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TIME_SET_TIMEA_4_12_6_6 BIT(15) BIT 94 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TDELAY_ABS BIT(14) BIT 95 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TDELAY_EN BIT(15) BIT 121 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_OVERLOAD_FIRST BIT(0) BIT 122 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_ACK_ERROR_FIRST BIT(1) BIT 123 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_BIT0_ERROR_FIRST BIT(2) BIT 124 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_BIT1_ERROR_FIRST BIT(3) BIT 125 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_STUFF_ERROR_FIRST BIT(4) BIT 126 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_CRC_ERROR_FIRST BIT(5) BIT 127 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_FORM_ERROR_FIRST BIT(6) BIT 128 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_OVERLOAD_ALL BIT(8) BIT 129 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_ACK_ERROR_ALL BIT(9) BIT 130 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_BIT0_ERROR_ALL BIT(10) BIT 131 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_BIT1_ERROR_ALL BIT(11) BIT 132 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_STUFF_ERROR_ALL BIT(12) BIT 133 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_CRC_ERROR_ALL BIT(13) BIT 134 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_FORM_ERROR_ALL BIT(14) BIT 137 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_ER_RESET BIT(30) BIT 138 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_ERROR_CTR_ER_ENABLE ((u32)BIT(31)) BIT 162 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_RXFIFO_DLC_RTR BIT(4) BIT 163 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_RXFIFO_DLC_EDL BIT(5) BIT 164 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_RXFIFO_DLC_BRS BIT(6) BIT 165 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_RXFIFO_DLC_ESI BIT(7) BIT 179 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_RXFIFO_ID_IDE BIT(29) BIT 190 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TXFIFO_DLC_RTR BIT(4) BIT 191 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TXFIFO_DLC_EDL BIT(5) BIT 192 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TXFIFO_DLC_BRS BIT(6) BIT 204 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_TXFIFO_ID_IDE BIT(29) BIT 209 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_FILTER_MASK_EXT BIT(29) BIT 210 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_FILTER_MASK_EDL BIT(30) BIT 211 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_FILTER_MASK_VALID ((u32)BIT(31)) BIT 214 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_FILTER_IDENT_IDE BIT(29) BIT 215 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_FILTER_IDENT_CANFD BIT(30) BIT 216 drivers/net/can/ifi_canfd/ifi_canfd.c #define IFI_CANFD_FILTER_IDENT_VALID ((u32)BIT(31)) BIT 33 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0) BIT 86 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_IRQ_SRB BIT(4) BIT 93 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4) BIT 94 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5) BIT 95 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_CMD_FOR BIT(0) BIT 98 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8) BIT 99 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9) BIT 101 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10) BIT 102 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11) BIT 104 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12) BIT 105 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13) BIT 108 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_STAT_DI BIT(15) BIT 110 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_STAT_DMA BIT(24) BIT 113 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0) BIT 123 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SPI_TMT BIT(5) BIT 124 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SPI_TRDY BIT(6) BIT 125 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SPI_RRDY BIT(7) BIT 138 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0) BIT 140 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_CMD_AT BIT(1) BIT 143 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0) BIT 145 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1) BIT 147 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2) BIT 149 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3) BIT 151 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5) BIT 153 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13) BIT 155 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14) BIT 157 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15) BIT 159 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16) BIT 161 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17) BIT 167 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_STAT_AR BIT(7) BIT 169 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10) BIT 171 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11) BIT 173 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14) BIT 175 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15) BIT 177 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16) BIT 179 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_STAT_FD BIT(19) BIT 185 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_MODE_RM BIT(8) BIT 187 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9) BIT 189 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12) BIT 191 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15) BIT 193 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_MODE_APT BIT(20) BIT 195 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23) BIT 197 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31) BIT 222 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_RPACKET_IDE BIT(30) BIT 223 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_RPACKET_RTR BIT(29) BIT 225 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_RPACKET_ESI BIT(13) BIT 226 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_RPACKET_BRS BIT(14) BIT 227 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_RPACKET_FDF BIT(15) BIT 230 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_TPACKET_SMS BIT(16) BIT 231 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_TPACKET_AREQ BIT(31) BIT 234 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_APACKET_FLU BIT(8) BIT 235 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_APACKET_CT BIT(9) BIT 236 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_APACKET_ABL BIT(10) BIT 237 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_APACKET_NACK BIT(11) BIT 241 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SPACK_BOFF BIT(16) BIT 242 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SPACK_IDET BIT(20) BIT 243 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SPACK_IRM BIT(21) BIT 244 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SPACK_RMCD BIT(22) BIT 246 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SPACK_AUTO BIT(21) BIT 247 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SPACK_EWLR BIT(23) BIT 248 drivers/net/can/kvaser_pciefd.c #define KVASER_PCIEFD_SPACK_EPLR BIT(24) BIT 340 drivers/net/can/kvaser_pciefd.c iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG); BIT 341 drivers/net/can/kvaser_pciefd.c iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG); BIT 94 drivers/net/can/m_can/m_can.c #define DBTP_TDC BIT(23) BIT 111 drivers/net/can/m_can/m_can.c #define TEST_LBCK BIT(4) BIT 124 drivers/net/can/m_can/m_can.c #define CCCR_TXP BIT(14) BIT 125 drivers/net/can/m_can/m_can.c #define CCCR_TEST BIT(7) BIT 126 drivers/net/can/m_can/m_can.c #define CCCR_MON BIT(5) BIT 127 drivers/net/can/m_can/m_can.c #define CCCR_CSR BIT(4) BIT 128 drivers/net/can/m_can/m_can.c #define CCCR_CSA BIT(3) BIT 129 drivers/net/can/m_can/m_can.c #define CCCR_ASM BIT(2) BIT 130 drivers/net/can/m_can/m_can.c #define CCCR_CCE BIT(1) BIT 131 drivers/net/can/m_can/m_can.c #define CCCR_INIT BIT(0) BIT 134 drivers/net/can/m_can/m_can.c #define CCCR_EFBI BIT(13) BIT 135 drivers/net/can/m_can/m_can.c #define CCCR_PXHD BIT(12) BIT 136 drivers/net/can/m_can/m_can.c #define CCCR_BRSE BIT(9) BIT 137 drivers/net/can/m_can/m_can.c #define CCCR_FDOE BIT(8) BIT 139 drivers/net/can/m_can/m_can.c #define CCCR_NISO BIT(15) BIT 152 drivers/net/can/m_can/m_can.c #define ECR_RP BIT(15) BIT 159 drivers/net/can/m_can/m_can.c #define PSR_BO BIT(7) BIT 160 drivers/net/can/m_can/m_can.c #define PSR_EW BIT(6) BIT 161 drivers/net/can/m_can/m_can.c #define PSR_EP BIT(5) BIT 168 drivers/net/can/m_can/m_can.c #define IR_ARA BIT(29) BIT 169 drivers/net/can/m_can/m_can.c #define IR_PED BIT(28) BIT 170 drivers/net/can/m_can/m_can.c #define IR_PEA BIT(27) BIT 173 drivers/net/can/m_can/m_can.c #define IR_STE BIT(31) BIT 174 drivers/net/can/m_can/m_can.c #define IR_FOE BIT(30) BIT 175 drivers/net/can/m_can/m_can.c #define IR_ACKE BIT(29) BIT 176 drivers/net/can/m_can/m_can.c #define IR_BE BIT(28) BIT 177 drivers/net/can/m_can/m_can.c #define IR_CRCE BIT(27) BIT 178 drivers/net/can/m_can/m_can.c #define IR_WDI BIT(26) BIT 179 drivers/net/can/m_can/m_can.c #define IR_BO BIT(25) BIT 180 drivers/net/can/m_can/m_can.c #define IR_EW BIT(24) BIT 181 drivers/net/can/m_can/m_can.c #define IR_EP BIT(23) BIT 182 drivers/net/can/m_can/m_can.c #define IR_ELO BIT(22) BIT 183 drivers/net/can/m_can/m_can.c #define IR_BEU BIT(21) BIT 184 drivers/net/can/m_can/m_can.c #define IR_BEC BIT(20) BIT 185 drivers/net/can/m_can/m_can.c #define IR_DRX BIT(19) BIT 186 drivers/net/can/m_can/m_can.c #define IR_TOO BIT(18) BIT 187 drivers/net/can/m_can/m_can.c #define IR_MRAF BIT(17) BIT 188 drivers/net/can/m_can/m_can.c #define IR_TSW BIT(16) BIT 189 drivers/net/can/m_can/m_can.c #define IR_TEFL BIT(15) BIT 190 drivers/net/can/m_can/m_can.c #define IR_TEFF BIT(14) BIT 191 drivers/net/can/m_can/m_can.c #define IR_TEFW BIT(13) BIT 192 drivers/net/can/m_can/m_can.c #define IR_TEFN BIT(12) BIT 193 drivers/net/can/m_can/m_can.c #define IR_TFE BIT(11) BIT 194 drivers/net/can/m_can/m_can.c #define IR_TCF BIT(10) BIT 195 drivers/net/can/m_can/m_can.c #define IR_TC BIT(9) BIT 196 drivers/net/can/m_can/m_can.c #define IR_HPM BIT(8) BIT 197 drivers/net/can/m_can/m_can.c #define IR_RF1L BIT(7) BIT 198 drivers/net/can/m_can/m_can.c #define IR_RF1F BIT(6) BIT 199 drivers/net/can/m_can/m_can.c #define IR_RF1W BIT(5) BIT 200 drivers/net/can/m_can/m_can.c #define IR_RF1N BIT(4) BIT 201 drivers/net/can/m_can/m_can.c #define IR_RF0L BIT(3) BIT 202 drivers/net/can/m_can/m_can.c #define IR_RF0F BIT(2) BIT 203 drivers/net/can/m_can/m_can.c #define IR_RF0W BIT(1) BIT 204 drivers/net/can/m_can/m_can.c #define IR_RF0N BIT(0) BIT 225 drivers/net/can/m_can/m_can.c #define ILE_EINT1 BIT(1) BIT 226 drivers/net/can/m_can/m_can.c #define ILE_EINT0 BIT(0) BIT 235 drivers/net/can/m_can/m_can.c #define RXFS_RFL BIT(25) BIT 236 drivers/net/can/m_can/m_can.c #define RXFS_FF BIT(24) BIT 254 drivers/net/can/m_can/m_can.c #define TXFQS_TFQF BIT(21) BIT 271 drivers/net/can/m_can/m_can.c #define TXEFS_TEFL BIT(25) BIT 272 drivers/net/can/m_can/m_can.c #define TXEFS_EFF BIT(24) BIT 298 drivers/net/can/m_can/m_can.c #define RX_BUF_ESI BIT(31) BIT 299 drivers/net/can/m_can/m_can.c #define RX_BUF_XTD BIT(30) BIT 300 drivers/net/can/m_can/m_can.c #define RX_BUF_RTR BIT(29) BIT 302 drivers/net/can/m_can/m_can.c #define RX_BUF_ANMF BIT(31) BIT 303 drivers/net/can/m_can/m_can.c #define RX_BUF_FDF BIT(21) BIT 304 drivers/net/can/m_can/m_can.c #define RX_BUF_BRS BIT(20) BIT 308 drivers/net/can/m_can/m_can.c #define TX_BUF_ESI BIT(31) BIT 309 drivers/net/can/m_can/m_can.c #define TX_BUF_XTD BIT(30) BIT 310 drivers/net/can/m_can/m_can.c #define TX_BUF_RTR BIT(29) BIT 312 drivers/net/can/m_can/m_can.c #define TX_BUF_EFC BIT(23) BIT 313 drivers/net/can/m_can/m_can.c #define TX_BUF_FDF BIT(21) BIT 314 drivers/net/can/m_can/m_can.c #define TX_BUF_BRS BIT(20) BIT 31 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30) BIT 32 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANHCANL_INT_EN BIT(29) BIT 33 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANHBAT_INT_EN BIT(28) BIT 34 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANLGND_INT_EN BIT(27) BIT 35 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26) BIT 36 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANBUSGND_INT_EN BIT(25) BIT 37 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANBUSBAT_INT_EN BIT(24) BIT 38 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_UVSUP_INT_EN BIT(22) BIT 39 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_UVIO_INT_EN BIT(21) BIT 40 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_TSD_INT_EN BIT(19) BIT 41 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_ECCERR_INT_EN BIT(16) BIT 42 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANINT_INT_EN BIT(15) BIT 43 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_LWU_INT_EN BIT(14) BIT 44 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANSLNT_INT_EN BIT(10) BIT 45 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANDOM_INT_EN BIT(8) BIT 46 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5) BIT 47 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_BUS_FAULT BIT(4) BIT 48 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_INT BIT(1) BIT 54 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_ARA BIT(29) BIT 55 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_PED BIT(28) BIT 56 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_PEA BIT(27) BIT 57 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_WD BIT(26) BIT 58 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_BO BIT(25) BIT 59 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_EW BIT(24) BIT 60 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_EP BIT(23) BIT 61 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_ELO BIT(22) BIT 62 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_BEU BIT(21) BIT 63 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_BEC BIT(20) BIT 64 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_DRX BIT(19) BIT 65 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_TOO BIT(18) BIT 66 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_MRAF BIT(17) BIT 67 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_TSW BIT(16) BIT 68 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_TEFL BIT(15) BIT 69 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_TEFF BIT(14) BIT 70 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_TEFW BIT(13) BIT 71 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_TEFN BIT(12) BIT 72 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_TFE BIT(11) BIT 73 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_TCF BIT(10) BIT 74 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_TC BIT(9) BIT 75 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_HPM BIT(8) BIT 76 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_RF1L BIT(7) BIT 77 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_RF1F BIT(6) BIT 78 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_RF1W BIT(5) BIT 79 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_RF1N BIT(4) BIT 80 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_RF0L BIT(3) BIT 81 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_RF0F BIT(2) BIT 82 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_RF0W BIT(1) BIT 83 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_IR_RF0N BIT(0) BIT 99 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6)) BIT 101 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MODE_STANDBY BIT(6) BIT 102 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MODE_NORMAL BIT(7) BIT 104 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_SW_RESET BIT(2) BIT 106 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_MCAN_CONFIGURED BIT(5) BIT 107 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_WATCHDOG_EN BIT(3) BIT 109 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_WD_600_MS_TIMER BIT(28) BIT 110 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_WD_3_S_TIMER BIT(29) BIT 111 drivers/net/can/m_can/tcan4x5x.c #define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29)) BIT 22 drivers/net/can/pch_can.c #define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ BIT 23 drivers/net/can/pch_can.c #define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ BIT 24 drivers/net/can/pch_can.c #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) BIT 25 drivers/net/can/pch_can.c #define PCH_CTRL_CCE BIT(6) BIT 26 drivers/net/can/pch_can.c #define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ BIT 27 drivers/net/can/pch_can.c #define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ BIT 28 drivers/net/can/pch_can.c #define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ BIT 33 drivers/net/can/pch_can.c #define PCH_CMASK_NEWDAT BIT(2) BIT 34 drivers/net/can/pch_can.c #define PCH_CMASK_CLRINTPND BIT(3) BIT 35 drivers/net/can/pch_can.c #define PCH_CMASK_CTRL BIT(4) BIT 36 drivers/net/can/pch_can.c #define PCH_CMASK_ARB BIT(5) BIT 37 drivers/net/can/pch_can.c #define PCH_CMASK_MASK BIT(6) BIT 38 drivers/net/can/pch_can.c #define PCH_CMASK_RDWR BIT(7) BIT 39 drivers/net/can/pch_can.c #define PCH_IF_MCONT_NEWDAT BIT(15) BIT 40 drivers/net/can/pch_can.c #define PCH_IF_MCONT_MSGLOST BIT(14) BIT 41 drivers/net/can/pch_can.c #define PCH_IF_MCONT_INTPND BIT(13) BIT 42 drivers/net/can/pch_can.c #define PCH_IF_MCONT_UMASK BIT(12) BIT 43 drivers/net/can/pch_can.c #define PCH_IF_MCONT_TXIE BIT(11) BIT 44 drivers/net/can/pch_can.c #define PCH_IF_MCONT_RXIE BIT(10) BIT 45 drivers/net/can/pch_can.c #define PCH_IF_MCONT_RMTEN BIT(9) BIT 46 drivers/net/can/pch_can.c #define PCH_IF_MCONT_TXRQXT BIT(8) BIT 47 drivers/net/can/pch_can.c #define PCH_IF_MCONT_EOB BIT(7) BIT 48 drivers/net/can/pch_can.c #define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) BIT 49 drivers/net/can/pch_can.c #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) BIT 50 drivers/net/can/pch_can.c #define PCH_ID2_DIR BIT(13) BIT 51 drivers/net/can/pch_can.c #define PCH_ID2_XTD BIT(14) BIT 52 drivers/net/can/pch_can.c #define PCH_ID_MSGVAL BIT(15) BIT 53 drivers/net/can/pch_can.c #define PCH_IF_CREQ_BUSY BIT(15) BIT 60 drivers/net/can/pch_can.c #define PCH_TX_OK BIT(3) BIT 61 drivers/net/can/pch_can.c #define PCH_RX_OK BIT(4) BIT 62 drivers/net/can/pch_can.c #define PCH_EPASSIV BIT(5) BIT 63 drivers/net/can/pch_can.c #define PCH_EWARN BIT(6) BIT 64 drivers/net/can/pch_can.c #define PCH_BUS_OFF BIT(7) BIT 29 drivers/net/can/rcar/rcar_can.c #define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ BIT 30 drivers/net/can/rcar/rcar_can.c BIT(CLKR_CLKEXT)) BIT 786 drivers/net/can/rcar/rcar_can.c if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) { BIT 46 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GRMCFG_RCMC BIT(0) BIT 49 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCFG_EEFE BIT(6) BIT 50 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCFG_CMPOC BIT(5) /* CAN FD only */ BIT 51 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCFG_DCS BIT(4) BIT 52 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCFG_DCE BIT(1) BIT 53 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCFG_TPRI BIT(0) BIT 56 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCTR_TSRST BIT(16) BIT 57 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCTR_CFMPOFIE BIT(11) /* CAN FD only */ BIT 58 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCTR_THLEIE BIT(10) BIT 59 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCTR_MEIE BIT(9) BIT 60 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCTR_DEIE BIT(8) BIT 61 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GCTR_GSLPR BIT(2) BIT 68 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GSTS_GRAMINIT BIT(3) BIT 69 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GSTS_GSLPSTS BIT(2) BIT 70 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GSTS_GHLTSTS BIT(1) BIT 71 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GSTS_GRSTSTS BIT(0) BIT 73 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GSTS_GNOPM (BIT(0) | BIT(1) | BIT(2) | BIT(3)) BIT 76 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GERFL_EEF1 BIT(17) BIT 77 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GERFL_EEF0 BIT(16) BIT 78 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GERFL_CMPOF BIT(3) /* CAN FD only */ BIT 79 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GERFL_THLES BIT(2) BIT 80 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GERFL_MES BIT(1) BIT 81 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GERFL_DEF BIT(0) BIT 95 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GAFLECTR_AFLDAE BIT(8) BIT 99 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_GAFLID_GAFLLB BIT(29) BIT 119 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_CTME BIT(24) BIT 120 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_ERRD BIT(23) BIT 125 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_TDCVFIE BIT(19) BIT 126 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_SOCOIE BIT(18) BIT 127 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_EOCOIE BIT(17) BIT 128 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_TAIE BIT(16) BIT 129 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_ALIE BIT(15) BIT 130 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_BLIE BIT(14) BIT 131 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_OLIE BIT(13) BIT 132 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_BORIE BIT(12) BIT 133 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_BOEIE BIT(11) BIT 134 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_EPIE BIT(10) BIT 135 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_EWIE BIT(9) BIT 136 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_BEIE BIT(8) BIT 137 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CCTR_CSLPR BIT(2) BIT 144 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CSTS_COMSTS BIT(7) BIT 145 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CSTS_RECSTS BIT(6) BIT 146 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CSTS_TRMSTS BIT(5) BIT 147 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CSTS_BOSTS BIT(4) BIT 148 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CSTS_EPSTS BIT(3) BIT 149 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CSTS_SLPSTS BIT(2) BIT 150 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CSTS_HLTSTS BIT(1) BIT 151 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CSTS_CRSTSTS BIT(0) BIT 157 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_ADERR BIT(14) BIT 158 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_B0ERR BIT(13) BIT 159 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_B1ERR BIT(12) BIT 160 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_CERR BIT(11) BIT 161 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_AERR BIT(10) BIT 162 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_FERR BIT(9) BIT 163 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_SERR BIT(8) BIT 164 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_ALF BIT(7) BIT 165 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_BLF BIT(6) BIT 166 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_OVLF BIT(5) BIT 167 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_BORF BIT(4) BIT 168 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_BOEF BIT(3) BIT 169 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_EPF BIT(2) BIT 170 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_EWF BIT(1) BIT 171 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CERFL_BEF BIT(0) BIT 182 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_FDCFG_TDCE BIT(9) BIT 183 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_FDCFG_TDCOC BIT(8) BIT 187 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFCC_RFIM BIT(12) BIT 190 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFCC_RFIE BIT(1) BIT 191 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFCC_RFE BIT(0) BIT 194 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFSTS_RFIF BIT(3) BIT 195 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFSTS_RFMLT BIT(2) BIT 196 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFSTS_RFFLL BIT(1) BIT 197 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFSTS_RFEMP BIT(0) BIT 200 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFID_RFIDE BIT(31) BIT 201 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFID_RFRTR BIT(30) BIT 209 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFFDSTS_RFFDF BIT(2) BIT 210 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFFDSTS_RFBRS BIT(1) BIT 211 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_RFFDSTS_RFESI BIT(0) BIT 218 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFCC_CFIM BIT(12) BIT 221 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFCC_CFTXIE BIT(2) BIT 222 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFCC_CFE BIT(0) BIT 226 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFSTS_CFTXIF BIT(4) BIT 227 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFSTS_CFMLT BIT(2) BIT 228 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFSTS_CFFLL BIT(1) BIT 229 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFSTS_CFEMP BIT(0) BIT 232 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFID_CFIDE BIT(31) BIT 233 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFID_CFRTR BIT(30) BIT 242 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFFDCSTS_CFFDF BIT(2) BIT 243 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFFDCSTS_CFBRS BIT(1) BIT 244 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CFFDCSTS_CFESI BIT(0) BIT 468 drivers/net/can/rcar/rcar_canfd.c #define RCANFD_CHANNELS_MASK BIT((RCANFD_NUM_CHANNELS) - 1) BIT 1647 drivers/net/can/rcar/rcar_canfd.c channels_mask |= BIT(0); /* Channel 0 */ BIT 1651 drivers/net/can/rcar/rcar_canfd.c channels_mask |= BIT(1); /* Channel 1 */ BIT 23 drivers/net/can/sja1000/f81601.c #define F81601_IO_MODE BIT(7) BIT 24 drivers/net/can/sja1000/f81601.c #define F81601_MEM_MODE BIT(6) BIT 25 drivers/net/can/sja1000/f81601.c #define F81601_CFG_MODE BIT(5) BIT 26 drivers/net/can/sja1000/f81601.c #define F81601_CAN2_INTERNAL_CLK BIT(3) BIT 27 drivers/net/can/sja1000/f81601.c #define F81601_CAN1_INTERNAL_CLK BIT(2) BIT 28 drivers/net/can/sja1000/f81601.c #define F81601_CAN2_EN BIT(1) BIT 29 drivers/net/can/sja1000/f81601.c #define F81601_CAN1_EN BIT(0) BIT 32 drivers/net/can/sja1000/f81601.c #define F81601_CAN2_HAS_EN BIT(4) BIT 64 drivers/net/can/spi/hi311x.c #define HI3110_CTRL1_TXEN BIT(7) BIT 66 drivers/net/can/spi/hi311x.c #define HI3110_INT_RXTMP BIT(7) BIT 67 drivers/net/can/spi/hi311x.c #define HI3110_INT_RXFIFO BIT(6) BIT 68 drivers/net/can/spi/hi311x.c #define HI3110_INT_TXCPLT BIT(5) BIT 69 drivers/net/can/spi/hi311x.c #define HI3110_INT_BUSERR BIT(4) BIT 70 drivers/net/can/spi/hi311x.c #define HI3110_INT_MCHG BIT(3) BIT 71 drivers/net/can/spi/hi311x.c #define HI3110_INT_WAKEUP BIT(2) BIT 72 drivers/net/can/spi/hi311x.c #define HI3110_INT_F1MESS BIT(1) BIT 73 drivers/net/can/spi/hi311x.c #define HI3110_INT_F0MESS BIT(0) BIT 75 drivers/net/can/spi/hi311x.c #define HI3110_ERR_BUSOFF BIT(7) BIT 76 drivers/net/can/spi/hi311x.c #define HI3110_ERR_TXERRP BIT(6) BIT 77 drivers/net/can/spi/hi311x.c #define HI3110_ERR_RXERRP BIT(5) BIT 78 drivers/net/can/spi/hi311x.c #define HI3110_ERR_BITERR BIT(4) BIT 79 drivers/net/can/spi/hi311x.c #define HI3110_ERR_FRMERR BIT(3) BIT 80 drivers/net/can/spi/hi311x.c #define HI3110_ERR_CRCERR BIT(2) BIT 81 drivers/net/can/spi/hi311x.c #define HI3110_ERR_ACKERR BIT(1) BIT 82 drivers/net/can/spi/hi311x.c #define HI3110_ERR_STUFERR BIT(0) BIT 86 drivers/net/can/spi/hi311x.c #define HI3110_STAT_RXFMTY BIT(1) BIT 87 drivers/net/can/spi/hi311x.c #define HI3110_STAT_BUSOFF BIT(2) BIT 88 drivers/net/can/spi/hi311x.c #define HI3110_STAT_ERRP BIT(3) BIT 89 drivers/net/can/spi/hi311x.c #define HI3110_STAT_ERRW BIT(4) BIT 90 drivers/net/can/spi/hi311x.c #define HI3110_STAT_TXMTY BIT(7) BIT 105 drivers/net/can/spi/hi311x.c #define HI3110_FIFO_WOTIME_TAG_IDE BIT(7) BIT 106 drivers/net/can/spi/hi311x.c #define HI3110_FIFO_WOTIME_ID_RTR BIT(0) BIT 105 drivers/net/can/sun4i_can.c #define SUN4I_MSEL_LOOPBACK_MODE BIT(2) BIT 106 drivers/net/can/sun4i_can.c #define SUN4I_MSEL_LISTEN_ONLY_MODE BIT(1) BIT 107 drivers/net/can/sun4i_can.c #define SUN4I_MSEL_RESET_MODE BIT(0) BIT 112 drivers/net/can/sun4i_can.c #define SUN4I_CMD_BUS_OFF_REQ BIT(5) BIT 113 drivers/net/can/sun4i_can.c #define SUN4I_CMD_SELF_RCV_REQ BIT(4) BIT 114 drivers/net/can/sun4i_can.c #define SUN4I_CMD_CLEAR_OR_FLAG BIT(3) BIT 115 drivers/net/can/sun4i_can.c #define SUN4I_CMD_RELEASE_RBUF BIT(2) BIT 116 drivers/net/can/sun4i_can.c #define SUN4I_CMD_ABORT_REQ BIT(1) BIT 117 drivers/net/can/sun4i_can.c #define SUN4I_CMD_TRANS_REQ BIT(0) BIT 127 drivers/net/can/sun4i_can.c #define SUN4I_STA_ERR_DIR BIT(21) BIT 153 drivers/net/can/sun4i_can.c #define SUN4I_STA_BUS_OFF BIT(7) BIT 154 drivers/net/can/sun4i_can.c #define SUN4I_STA_ERR_STA BIT(6) BIT 155 drivers/net/can/sun4i_can.c #define SUN4I_STA_TRANS_BUSY BIT(5) BIT 156 drivers/net/can/sun4i_can.c #define SUN4I_STA_RCV_BUSY BIT(4) BIT 157 drivers/net/can/sun4i_can.c #define SUN4I_STA_TRANS_OVER BIT(3) BIT 158 drivers/net/can/sun4i_can.c #define SUN4I_STA_TBUF_RDY BIT(2) BIT 159 drivers/net/can/sun4i_can.c #define SUN4I_STA_DATA_ORUN BIT(1) BIT 160 drivers/net/can/sun4i_can.c #define SUN4I_STA_RBUF_RDY BIT(0) BIT 165 drivers/net/can/sun4i_can.c #define SUN4I_INT_BUS_ERR BIT(7) BIT 166 drivers/net/can/sun4i_can.c #define SUN4I_INT_ARB_LOST BIT(6) BIT 167 drivers/net/can/sun4i_can.c #define SUN4I_INT_ERR_PASSIVE BIT(5) BIT 168 drivers/net/can/sun4i_can.c #define SUN4I_INT_WAKEUP BIT(4) BIT 169 drivers/net/can/sun4i_can.c #define SUN4I_INT_DATA_OR BIT(3) BIT 170 drivers/net/can/sun4i_can.c #define SUN4I_INT_ERR_WRN BIT(2) BIT 171 drivers/net/can/sun4i_can.c #define SUN4I_INT_TBUF_VLD BIT(1) BIT 172 drivers/net/can/sun4i_can.c #define SUN4I_INT_RBUF_VLD BIT(0) BIT 177 drivers/net/can/sun4i_can.c #define SUN4I_INTEN_BERR BIT(7) BIT 178 drivers/net/can/sun4i_can.c #define SUN4I_INTEN_ARB_LOST BIT(6) BIT 179 drivers/net/can/sun4i_can.c #define SUN4I_INTEN_ERR_PASSIVE BIT(5) BIT 180 drivers/net/can/sun4i_can.c #define SUN4I_INTEN_WAKEUP BIT(4) BIT 181 drivers/net/can/sun4i_can.c #define SUN4I_INTEN_OR BIT(3) BIT 182 drivers/net/can/sun4i_can.c #define SUN4I_INTEN_ERR_WRN BIT(2) BIT 183 drivers/net/can/sun4i_can.c #define SUN4I_INTEN_TX BIT(1) BIT 184 drivers/net/can/sun4i_can.c #define SUN4I_INTEN_RX BIT(0) BIT 196 drivers/net/can/sun4i_can.c #define SUN4I_MSG_EFF_FLAG BIT(7) BIT 197 drivers/net/can/sun4i_can.c #define SUN4I_MSG_RTR_FLAG BIT(6) BIT 61 drivers/net/can/ti_hecc.c #define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT) BIT 121 drivers/net/can/ti_hecc.c #define HECC_CANMC_SCM BIT(13) /* SCC compat mode */ BIT 122 drivers/net/can/ti_hecc.c #define HECC_CANMC_CCR BIT(12) /* Change config request */ BIT 123 drivers/net/can/ti_hecc.c #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */ BIT 124 drivers/net/can/ti_hecc.c #define HECC_CANMC_ABO BIT(7) /* Auto Bus On */ BIT 125 drivers/net/can/ti_hecc.c #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */ BIT 126 drivers/net/can/ti_hecc.c #define HECC_CANMC_SRES BIT(5) /* Software reset */ BIT 128 drivers/net/can/ti_hecc.c #define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */ BIT 129 drivers/net/can/ti_hecc.c #define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */ BIT 131 drivers/net/can/ti_hecc.c #define HECC_CANMID_IDE BIT(31) /* Extended frame format */ BIT 132 drivers/net/can/ti_hecc.c #define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */ BIT 133 drivers/net/can/ti_hecc.c #define HECC_CANMID_AAM BIT(29) /* Auto answer mode */ BIT 135 drivers/net/can/ti_hecc.c #define HECC_CANES_FE BIT(24) /* form error */ BIT 136 drivers/net/can/ti_hecc.c #define HECC_CANES_BE BIT(23) /* bit error */ BIT 137 drivers/net/can/ti_hecc.c #define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */ BIT 138 drivers/net/can/ti_hecc.c #define HECC_CANES_CRCE BIT(21) /* CRC error */ BIT 139 drivers/net/can/ti_hecc.c #define HECC_CANES_SE BIT(20) /* stuff bit error */ BIT 140 drivers/net/can/ti_hecc.c #define HECC_CANES_ACKE BIT(19) /* ack error */ BIT 141 drivers/net/can/ti_hecc.c #define HECC_CANES_BO BIT(18) /* Bus off status */ BIT 142 drivers/net/can/ti_hecc.c #define HECC_CANES_EP BIT(17) /* Error passive status */ BIT 143 drivers/net/can/ti_hecc.c #define HECC_CANES_EW BIT(16) /* Error warning status */ BIT 144 drivers/net/can/ti_hecc.c #define HECC_CANES_SMA BIT(5) /* suspend mode ack */ BIT 145 drivers/net/can/ti_hecc.c #define HECC_CANES_CCE BIT(4) /* Change config enabled */ BIT 146 drivers/net/can/ti_hecc.c #define HECC_CANES_PDA BIT(3) /* Power down mode ack */ BIT 148 drivers/net/can/ti_hecc.c #define HECC_CANBTC_SAM BIT(7) /* sample points */ BIT 156 drivers/net/can/ti_hecc.c #define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */ BIT 158 drivers/net/can/ti_hecc.c #define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */ BIT 159 drivers/net/can/ti_hecc.c #define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */ BIT 160 drivers/net/can/ti_hecc.c #define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */ BIT 161 drivers/net/can/ti_hecc.c #define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */ BIT 162 drivers/net/can/ti_hecc.c #define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */ BIT 163 drivers/net/can/ti_hecc.c #define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */ BIT 164 drivers/net/can/ti_hecc.c #define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */ BIT 165 drivers/net/can/ti_hecc.c #define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */ BIT 166 drivers/net/can/ti_hecc.c #define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */ BIT 167 drivers/net/can/ti_hecc.c #define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */ BIT 169 drivers/net/can/ti_hecc.c #define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */ BIT 170 drivers/net/can/ti_hecc.c #define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */ BIT 172 drivers/net/can/ti_hecc.c #define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */ BIT 379 drivers/net/can/ti_hecc.c mbx_mask = BIT(mbxno); BIT 389 drivers/net/can/ti_hecc.c hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1); BIT 396 drivers/net/can/ti_hecc.c mbx_mask = ~BIT(HECC_RX_LAST_MBOX); BIT 486 drivers/net/can/ti_hecc.c mbx_mask = BIT(mbxno); BIT 520 drivers/net/can/ti_hecc.c if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) || BIT 546 drivers/net/can/ti_hecc.c mbx_mask = BIT(mbxno); BIT 736 drivers/net/can/ti_hecc.c mbx_mask = BIT(mbxno); BIT 84 drivers/net/can/usb/gs_usb.c #define GS_CAN_MODE_LISTEN_ONLY BIT(0) BIT 85 drivers/net/can/usb/gs_usb.c #define GS_CAN_MODE_LOOP_BACK BIT(1) BIT 86 drivers/net/can/usb/gs_usb.c #define GS_CAN_MODE_TRIPLE_SAMPLE BIT(2) BIT 87 drivers/net/can/usb/gs_usb.c #define GS_CAN_MODE_ONE_SHOT BIT(3) BIT 112 drivers/net/can/usb/gs_usb.c #define GS_CAN_FEATURE_LISTEN_ONLY BIT(0) BIT 113 drivers/net/can/usb/gs_usb.c #define GS_CAN_FEATURE_LOOP_BACK BIT(1) BIT 114 drivers/net/can/usb/gs_usb.c #define GS_CAN_FEATURE_TRIPLE_SAMPLE BIT(2) BIT 115 drivers/net/can/usb/gs_usb.c #define GS_CAN_FEATURE_ONE_SHOT BIT(3) BIT 116 drivers/net/can/usb/gs_usb.c #define GS_CAN_FEATURE_HW_TIMESTAMP BIT(4) BIT 117 drivers/net/can/usb/gs_usb.c #define GS_CAN_FEATURE_IDENTIFY BIT(5) BIT 39 drivers/net/can/usb/kvaser_usb/kvaser_usb.h #define KVASER_USB_HAS_SILENT_MODE BIT(0) BIT 40 drivers/net/can/usb/kvaser_usb/kvaser_usb.h #define KVASER_USB_HAS_TXRX_ERRORS BIT(1) BIT 131 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_SW_FLAG_FW_BETA BIT(2) BIT 132 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_SW_FLAG_FW_BAD BIT(4) BIT 133 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_SW_FLAG_FREQ_80M BIT(5) BIT 134 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_SW_FLAG_EXT_CMD BIT(9) BIT 135 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_SW_FLAG_CANFD BIT(10) BIT 136 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_SW_FLAG_NONISO BIT(11) BIT 137 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_SW_FLAG_EXT_CAP BIT(12) BIT 181 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_BUS_ERR_PASS BIT(5) BIT 182 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_BUS_BUS_OFF BIT(6) BIT 243 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_EXTENDED_FRAME_ID BIT(31) BIT 292 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_CF_FLAG_ERROR_FRAME BIT(0) BIT 293 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_CF_FLAG_OVERRUN BIT(1) BIT 294 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_CF_FLAG_REMOTE_FRAME BIT(4) BIT 295 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_CF_FLAG_EXTENDED_ID BIT(5) BIT 297 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_CF_FLAG_OSM_NACK BIT(12) BIT 298 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_CF_FLAG_ABL BIT(13) BIT 299 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_CF_FLAG_FDF BIT(16) BIT 300 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_CF_FLAG_BRS BIT(17) BIT 301 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_CF_FLAG_ESI BIT(18) BIT 311 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_KCAN_DATA_BRS BIT(14) BIT 312 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_KCAN_DATA_FDF BIT(15) BIT 313 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_KCAN_DATA_OSM BIT(16) BIT 314 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_KCAN_DATA_AREQ BIT(31) BIT 315 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_KCAN_DATA_SRR BIT(31) BIT 316 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_KCAN_DATA_RTR BIT(29) BIT 317 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_KCAN_DATA_IDE BIT(30) BIT 749 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c if (BIT(i) & (value & mask)) { BIT 41 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define MSG_FLAG_ERROR_FRAME BIT(0) BIT 42 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define MSG_FLAG_OVERRUN BIT(1) BIT 43 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define MSG_FLAG_NERR BIT(2) BIT 44 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define MSG_FLAG_WAKEUP BIT(3) BIT 45 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define MSG_FLAG_REMOTE_FRAME BIT(4) BIT 46 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define MSG_FLAG_RESERVED BIT(5) BIT 47 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define MSG_FLAG_TX_ACK BIT(6) BIT 48 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define MSG_FLAG_TX_REQUEST BIT(7) BIT 51 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_STATE_BUS_RESET BIT(0) BIT 52 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_STATE_BUS_ERROR BIT(4) BIT 53 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_STATE_BUS_PASSIVE BIT(5) BIT 54 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_STATE_BUS_OFF BIT(6) BIT 84 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_EF_ACKE BIT(0) BIT 85 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_EF_CRCE BIT(1) BIT 86 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_EF_FORME BIT(2) BIT 87 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_EF_STFE BIT(3) BIT 88 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_EF_BITE0 BIT(4) BIT 89 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_EF_BITE1 BIT(5) BIT 90 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_EF_RCVE BIT(6) BIT 91 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define M16C_EF_TRE BIT(7) BIT 97 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define USBCAN_ERROR_STATE_TX_ERROR BIT(0) BIT 98 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define USBCAN_ERROR_STATE_RX_ERROR BIT(1) BIT 99 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define USBCAN_ERROR_STATE_BUSERROR BIT(2) BIT 118 drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c #define KVASER_EXTENDED_FRAME BIT(31) BIT 104 drivers/net/can/usb/ucan.c UCAN_MODE_LOOPBACK = BIT(0), BIT 105 drivers/net/can/usb/ucan.c UCAN_MODE_SILENT = BIT(1), BIT 106 drivers/net/can/usb/ucan.c UCAN_MODE_3_SAMPLES = BIT(2), BIT 107 drivers/net/can/usb/ucan.c UCAN_MODE_ONE_SHOT = BIT(3), BIT 108 drivers/net/can/usb/ucan.c UCAN_MODE_BERR_REPORT = BIT(4), BIT 192 drivers/net/can/usb/ucan.c UCAN_TX_COMPLETE_SUCCESS = BIT(0), BIT 672 drivers/net/can/xilinx_can.c BIT(XCAN_TX_MAILBOX_IDX))) BIT 685 drivers/net/can/xilinx_can.c priv->write_reg(priv, XCAN_TRR_OFFSET, BIT(XCAN_TX_MAILBOX_IDX)); BIT 511 drivers/net/dsa/b53/b53_common.c pvlan |= BIT(cpu_port); BIT 545 drivers/net/dsa/b53/b53_common.c pvlan |= BIT(port); BIT 615 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); BIT 617 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); BIT 625 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); BIT 627 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); BIT 1162 drivers/net/dsa/b53/b53_common.c link = !!(sts & BIT(port)); BIT 1359 drivers/net/dsa/b53/b53_common.c vl->members |= BIT(port); BIT 1361 drivers/net/dsa/b53/b53_common.c vl->untag |= BIT(port); BIT 1363 drivers/net/dsa/b53/b53_common.c vl->untag &= ~BIT(port); BIT 1393 drivers/net/dsa/b53/b53_common.c vl->members &= ~BIT(port); BIT 1399 drivers/net/dsa/b53/b53_common.c vl->untag &= ~(BIT(port)); BIT 1676 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); BIT 1677 drivers/net/dsa/b53/b53_common.c if ((reg & BIT(cpu_port)) == BIT(cpu_port)) BIT 1678 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(cpu_port); BIT 1692 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); BIT 1696 drivers/net/dsa/b53/b53_common.c pvlan |= BIT(i); BIT 1725 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); BIT 1731 drivers/net/dsa/b53/b53_common.c pvlan &= ~BIT(i); BIT 1742 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); BIT 1743 drivers/net/dsa/b53/b53_common.c if (!(reg & BIT(cpu_port))) BIT 1744 drivers/net/dsa/b53/b53_common.c reg |= BIT(cpu_port); BIT 1748 drivers/net/dsa/b53/b53_common.c vl->members |= BIT(port) | BIT(cpu_port); BIT 1749 drivers/net/dsa/b53/b53_common.c vl->untag |= BIT(port) | BIT(cpu_port); BIT 1806 drivers/net/dsa/b53/b53_common.c uc |= BIT(port); BIT 1808 drivers/net/dsa/b53/b53_common.c uc &= ~BIT(port); BIT 1813 drivers/net/dsa/b53/b53_common.c mc |= BIT(port); BIT 1815 drivers/net/dsa/b53/b53_common.c mc &= ~BIT(port); BIT 1820 drivers/net/dsa/b53/b53_common.c mc |= BIT(port); BIT 1822 drivers/net/dsa/b53/b53_common.c mc &= ~BIT(port); BIT 1890 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); BIT 1917 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); BIT 1949 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); BIT 1951 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); BIT 1984 drivers/net/dsa/b53/b53_common.c e->eee_active = !!(reg & BIT(port)); BIT 2323 drivers/net/dsa/b53/b53_common.c dev->enabled_ports &= ~BIT(4); BIT 2345 drivers/net/dsa/b53/b53_common.c dev->enabled_ports |= BIT(dev->cpu_port); BIT 2350 drivers/net/dsa/b53/b53_common.c if (!(dev->ds->phys_mii_mask & BIT(i)) && BIT 2352 drivers/net/dsa/b53/b53_common.c dev->ds->phys_mii_mask |= BIT(i); BIT 37 drivers/net/dsa/b53/b53_mdio.c #define REG_MII_PAGE_ENABLE BIT(0) BIT 38 drivers/net/dsa/b53/b53_mdio.c #define REG_MII_ADDR_WRITE BIT(0) BIT 39 drivers/net/dsa/b53/b53_mdio.c #define REG_MII_ADDR_READ BIT(1) BIT 148 drivers/net/dsa/b53/b53_priv.h if (dev->enabled_ports & BIT(i)) BIT 65 drivers/net/dsa/b53/b53_regs.h #define PORT_CTRL_RX_DISABLE BIT(0) BIT 66 drivers/net/dsa/b53/b53_regs.h #define PORT_CTRL_TX_DISABLE BIT(1) BIT 67 drivers/net/dsa/b53/b53_regs.h #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */ BIT 68 drivers/net/dsa/b53/b53_regs.h #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */ BIT 69 drivers/net/dsa/b53/b53_regs.h #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */ BIT 84 drivers/net/dsa/b53/b53_regs.h #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */ BIT 85 drivers/net/dsa/b53/b53_regs.h #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */ BIT 89 drivers/net/dsa/b53/b53_regs.h #define PORT_OVERRIDE_LINK BIT(0) BIT 90 drivers/net/dsa/b53/b53_regs.h #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ BIT 95 drivers/net/dsa/b53/b53_regs.h #define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */ BIT 96 drivers/net/dsa/b53/b53_regs.h #define PORT_OVERRIDE_RX_FLOW BIT(4) BIT 97 drivers/net/dsa/b53/b53_regs.h #define PORT_OVERRIDE_TX_FLOW BIT(5) BIT 98 drivers/net/dsa/b53/b53_regs.h #define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */ BIT 99 drivers/net/dsa/b53/b53_regs.h #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */ BIT 106 drivers/net/dsa/b53/b53_regs.h #define B53_IPMC_FWD_EN BIT(1) BIT 107 drivers/net/dsa/b53/b53_regs.h #define B53_UC_FWD_EN BIT(6) BIT 108 drivers/net/dsa/b53/b53_regs.h #define B53_MC_FWD_EN BIT(7) BIT 112 drivers/net/dsa/b53/b53_regs.h #define B53_MII_DUMB_FWDG_EN BIT(6) BIT 127 drivers/net/dsa/b53/b53_regs.h #define GMII_PO_LINK BIT(0) BIT 128 drivers/net/dsa/b53/b53_regs.h #define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ BIT 133 drivers/net/dsa/b53/b53_regs.h #define GMII_PO_RX_FLOW BIT(4) BIT 134 drivers/net/dsa/b53/b53_regs.h #define GMII_PO_TX_FLOW BIT(5) BIT 135 drivers/net/dsa/b53/b53_regs.h #define GMII_PO_EN BIT(6) /* Use the register contents */ BIT 136 drivers/net/dsa/b53/b53_regs.h #define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */ BIT 139 drivers/net/dsa/b53/b53_regs.h #define RGMII_CTRL_ENABLE_GMII BIT(7) BIT 140 drivers/net/dsa/b53/b53_regs.h #define RGMII_CTRL_TIMING_SEL BIT(2) BIT 141 drivers/net/dsa/b53/b53_regs.h #define RGMII_CTRL_DLL_RXC BIT(1) BIT 142 drivers/net/dsa/b53/b53_regs.h #define RGMII_CTRL_DLL_TXC BIT(0) BIT 148 drivers/net/dsa/b53/b53_regs.h #define SW_RST BIT(7) BIT 149 drivers/net/dsa/b53/b53_regs.h #define EN_CH_RST BIT(6) BIT 150 drivers/net/dsa/b53/b53_regs.h #define EN_SW_RST BIT(4) BIT 154 drivers/net/dsa/b53/b53_regs.h #define FAST_AGE_STATIC BIT(0) BIT 155 drivers/net/dsa/b53/b53_regs.h #define FAST_AGE_DYNAMIC BIT(1) BIT 156 drivers/net/dsa/b53/b53_regs.h #define FAST_AGE_PORT BIT(2) BIT 157 drivers/net/dsa/b53/b53_regs.h #define FAST_AGE_VLAN BIT(3) BIT 158 drivers/net/dsa/b53/b53_regs.h #define FAST_AGE_STP BIT(4) BIT 159 drivers/net/dsa/b53/b53_regs.h #define FAST_AGE_MC BIT(5) BIT 160 drivers/net/dsa/b53/b53_regs.h #define FAST_AGE_DONE BIT(7) BIT 196 drivers/net/dsa/b53/b53_regs.h #define SV_GMII_CTRL_115 BIT(27) BIT 214 drivers/net/dsa/b53/b53_regs.h #define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */ BIT 215 drivers/net/dsa/b53/b53_regs.h #define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */ BIT 216 drivers/net/dsa/b53/b53_regs.h #define BRCM_HDR_P7_EN BIT(2) /* Enable tagging on port 7 */ BIT 221 drivers/net/dsa/b53/b53_regs.h #define BLK_NOT_MIR BIT(14) BIT 222 drivers/net/dsa/b53/b53_regs.h #define MIRROR_EN BIT(15) BIT 227 drivers/net/dsa/b53/b53_regs.h #define DIV_EN BIT(13) BIT 273 drivers/net/dsa/b53/b53_regs.h #define VTA_START_CMD BIT(7) BIT 294 drivers/net/dsa/b53/b53_regs.h #define ARLTBL_RW BIT(0) BIT 295 drivers/net/dsa/b53/b53_regs.h #define ARLTBL_IVL_SVL_SELECT BIT(6) BIT 296 drivers/net/dsa/b53/b53_regs.h #define ARLTBL_START_DONE BIT(7) BIT 315 drivers/net/dsa/b53/b53_regs.h #define ARLTBL_AGE_25 BIT(61) BIT 316 drivers/net/dsa/b53/b53_regs.h #define ARLTBL_STATIC_25 BIT(62) BIT 317 drivers/net/dsa/b53/b53_regs.h #define ARLTBL_VALID_25 BIT(63) BIT 323 drivers/net/dsa/b53/b53_regs.h #define ARLTBL_AGE BIT(14) BIT 324 drivers/net/dsa/b53/b53_regs.h #define ARLTBL_STATIC BIT(15) BIT 325 drivers/net/dsa/b53/b53_regs.h #define ARLTBL_VALID BIT(16) BIT 333 drivers/net/dsa/b53/b53_regs.h #define ARL_SRCH_VLID BIT(0) BIT 334 drivers/net/dsa/b53/b53_regs.h #define ARL_SRCH_STDN BIT(7) BIT 391 drivers/net/dsa/b53/b53_regs.h #define VC0_RESERVED_1 BIT(1) BIT 392 drivers/net/dsa/b53/b53_regs.h #define VC0_DROP_VID_MISS BIT(4) BIT 393 drivers/net/dsa/b53/b53_regs.h #define VC0_VID_HASH_VID BIT(5) BIT 394 drivers/net/dsa/b53/b53_regs.h #define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */ BIT 395 drivers/net/dsa/b53/b53_regs.h #define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */ BIT 399 drivers/net/dsa/b53/b53_regs.h #define VC1_RX_MCST_TAG_EN BIT(1) BIT 400 drivers/net/dsa/b53/b53_regs.h #define VC1_RX_MCST_FWD_EN BIT(2) BIT 401 drivers/net/dsa/b53/b53_regs.h #define VC1_RX_MCST_UNTAG_EN BIT(3) BIT 409 drivers/net/dsa/b53/b53_regs.h #define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */ BIT 410 drivers/net/dsa/b53/b53_regs.h #define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */ BIT 427 drivers/net/dsa/b53/b53_regs.h #define VC5_VID_FFF_EN BIT(2) BIT 428 drivers/net/dsa/b53/b53_regs.h #define VC5_DROP_VTABLE_MISS BIT(3) BIT 443 drivers/net/dsa/b53/b53_regs.h #define VTA_RW_STATE BIT(12) BIT 445 drivers/net/dsa/b53/b53_regs.h #define VTA_RW_STATE_WR BIT(12) BIT 446 drivers/net/dsa/b53/b53_regs.h #define VTA_RW_OP_EN BIT(13) BIT 459 drivers/net/dsa/b53/b53_regs.h #define VA_VALID_25 BIT(20) BIT 460 drivers/net/dsa/b53/b53_regs.h #define VA_VALID_25_R4 BIT(24) BIT 461 drivers/net/dsa/b53/b53_regs.h #define VA_VALID_65 BIT(14) BIT 473 drivers/net/dsa/b53/b53_regs.h #define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */ BIT 27 drivers/net/dsa/b53/b53_serdes.h #define FIBER_MODE_1000X BIT(0) BIT 28 drivers/net/dsa/b53/b53_serdes.h #define TBI_INTERFACE BIT(1) BIT 29 drivers/net/dsa/b53/b53_serdes.h #define SIGNAL_DETECT_EN BIT(2) BIT 30 drivers/net/dsa/b53/b53_serdes.h #define INVERT_SIGNAL_DETECT BIT(3) BIT 31 drivers/net/dsa/b53/b53_serdes.h #define AUTODET_EN BIT(4) BIT 32 drivers/net/dsa/b53/b53_serdes.h #define SGMII_MASTER_MODE BIT(5) BIT 33 drivers/net/dsa/b53/b53_serdes.h #define DISABLE_DLL_PWRDOWN BIT(6) BIT 34 drivers/net/dsa/b53/b53_serdes.h #define CRC_CHECKER_DIS BIT(7) BIT 35 drivers/net/dsa/b53/b53_serdes.h #define COMMA_DET_EN BIT(8) BIT 36 drivers/net/dsa/b53/b53_serdes.h #define ZERO_COMMA_DET_EN BIT(9) BIT 37 drivers/net/dsa/b53/b53_serdes.h #define REMOTE_LOOPBACK BIT(10) BIT 38 drivers/net/dsa/b53/b53_serdes.h #define SEL_RX_PKTS_FOR_CNTR BIT(11) BIT 39 drivers/net/dsa/b53/b53_serdes.h #define MASTER_MDIO_PHY_SEL BIT(13) BIT 40 drivers/net/dsa/b53/b53_serdes.h #define DISABLE_SIGNAL_DETECT_FLT BIT(14) BIT 43 drivers/net/dsa/b53/b53_serdes.h #define EN_PARALLEL_DET BIT(0) BIT 44 drivers/net/dsa/b53/b53_serdes.h #define DIS_FALSE_LINK BIT(1) BIT 45 drivers/net/dsa/b53/b53_serdes.h #define FLT_FORCE_LINK BIT(2) BIT 46 drivers/net/dsa/b53/b53_serdes.h #define EN_AUTONEG_ERR_TIMER BIT(3) BIT 47 drivers/net/dsa/b53/b53_serdes.h #define DIS_REMOTE_FAULT_SENSING BIT(4) BIT 48 drivers/net/dsa/b53/b53_serdes.h #define FORCE_XMIT_DATA BIT(5) BIT 49 drivers/net/dsa/b53/b53_serdes.h #define AUTONEG_FAST_TIMERS BIT(6) BIT 50 drivers/net/dsa/b53/b53_serdes.h #define DIS_CARRIER_EXTEND BIT(7) BIT 51 drivers/net/dsa/b53/b53_serdes.h #define DIS_TRRR_GENERATION BIT(8) BIT 52 drivers/net/dsa/b53/b53_serdes.h #define BYPASS_PCS_RX BIT(9) BIT 53 drivers/net/dsa/b53/b53_serdes.h #define BYPASS_PCS_TX BIT(10) BIT 54 drivers/net/dsa/b53/b53_serdes.h #define TEST_CNTR_EN BIT(11) BIT 55 drivers/net/dsa/b53/b53_serdes.h #define TX_PACKET_SEQ_TEST BIT(12) BIT 56 drivers/net/dsa/b53/b53_serdes.h #define TX_IDLE_JAM_SEQ_TEST BIT(13) BIT 57 drivers/net/dsa/b53/b53_serdes.h #define CLR_BER_CNTR BIT(14) BIT 60 drivers/net/dsa/b53/b53_serdes.h #define TX_FIFO_RST BIT(0) BIT 66 drivers/net/dsa/b53/b53_serdes.h #define BLOCK_TXEN_MODE BIT(9) BIT 67 drivers/net/dsa/b53/b53_serdes.h #define JAM_FALSE_CARRIER_MODE BIT(10) BIT 68 drivers/net/dsa/b53/b53_serdes.h #define EXT_PHY_CRS_MODE BIT(11) BIT 69 drivers/net/dsa/b53/b53_serdes.h #define INVERT_EXT_PHY_CRS BIT(12) BIT 70 drivers/net/dsa/b53/b53_serdes.h #define DISABLE_TX_CRS BIT(13) BIT 73 drivers/net/dsa/b53/b53_serdes.h #define SGMII_MODE BIT(0) BIT 74 drivers/net/dsa/b53/b53_serdes.h #define LINK_STATUS BIT(1) BIT 75 drivers/net/dsa/b53/b53_serdes.h #define DUPLEX_STATUS BIT(2) BIT 82 drivers/net/dsa/b53/b53_serdes.h #define PAUSE_RESOLUTION_TX_SIDE BIT(5) BIT 83 drivers/net/dsa/b53/b53_serdes.h #define PAUSE_RESOLUTION_RX_SIDE BIT(6) BIT 84 drivers/net/dsa/b53/b53_serdes.h #define LINK_STATUS_CHANGE BIT(7) BIT 85 drivers/net/dsa/b53/b53_serdes.h #define EARLY_END_EXT_DET BIT(8) BIT 86 drivers/net/dsa/b53/b53_serdes.h #define CARRIER_EXT_ERR_DET BIT(9) BIT 87 drivers/net/dsa/b53/b53_serdes.h #define RX_ERR_DET BIT(10) BIT 88 drivers/net/dsa/b53/b53_serdes.h #define TX_ERR_DET BIT(11) BIT 89 drivers/net/dsa/b53/b53_serdes.h #define CRC_ERR_DET BIT(12) BIT 90 drivers/net/dsa/b53/b53_serdes.h #define FALSE_CARRIER_ERR_DET BIT(13) BIT 91 drivers/net/dsa/b53/b53_serdes.h #define RXFIFO_ERR_DET BIT(14) BIT 92 drivers/net/dsa/b53/b53_serdes.h #define TXFIFO_ERR_DET BIT(15) BIT 32 drivers/net/dsa/b53/b53_spi.c #define B53_SPI_CMD_SPIF BIT(7) BIT 33 drivers/net/dsa/b53/b53_spi.c #define B53_SPI_CMD_RACK BIT(5) BIT 32 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_CMDSTAT_RST BIT(2) BIT 33 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_CMDSTAT_WRITE BIT(1) BIT 34 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_CMDSTAT_GORDYN BIT(0) BIT 52 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_CTRLS_HOST_INTR BIT(1) BIT 53 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_CTRLS_RCAREQ BIT(3) BIT 54 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_CTRLS_RCAGNT BIT(4) BIT 55 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_CTRLS_SW_INIT_DONE BIT(6) BIT 59 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_INTR_P(x) BIT(x) BIT 60 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_SWITCH_PHY BIT(8) BIT 61 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_1588_SYNC BIT(9) BIT 62 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_IMP1_SLEEP_TIMER BIT(10) BIT 63 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_P7_SLEEP_TIMER BIT(11) BIT 64 drivers/net/dsa/b53/b53_srab.c #define B53_SRAB_IMP0_SLEEP_TIMER BIT(12) BIT 389 drivers/net/dsa/b53/b53_srab.c writel(BIT(port->num), priv->regs + B53_SRAB_INTR); BIT 177 drivers/net/dsa/bcm_sf2.c reg &= ~BIT(port); BIT 181 drivers/net/dsa/bcm_sf2.c if (priv->brcm_tag_mask & BIT(port)) BIT 238 drivers/net/dsa/bcm_sf2.c reg |= BIT(port); BIT 296 drivers/net/dsa/bcm_sf2.c if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) BIT 310 drivers/net/dsa/bcm_sf2.c if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) BIT 225 drivers/net/dsa/bcm_sf2_cfp.c BIT(port_num + DST_MAP_IB_SHIFT) | BIT 396 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, BIT(port), CORE_CFP_DATA_PORT(7)); BIT 454 drivers/net/dsa/bcm_sf2_cfp.c reg |= BIT(port); BIT 678 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, BIT(port), CORE_CFP_DATA_PORT(7)); BIT 801 drivers/net/dsa/bcm_sf2_cfp.c reg |= BIT(port); BIT 215 drivers/net/dsa/dsa_loop.c vl->members |= BIT(port); BIT 217 drivers/net/dsa/dsa_loop.c vl->untagged |= BIT(port); BIT 219 drivers/net/dsa/dsa_loop.c vl->untagged &= ~BIT(port); BIT 244 drivers/net/dsa/dsa_loop.c vl->members &= ~BIT(port); BIT 246 drivers/net/dsa/dsa_loop.c vl->untagged &= ~BIT(port); BIT 25 drivers/net/dsa/lan9303-core.c # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8) BIT 26 drivers/net/dsa/lan9303-core.c # define LAN9303_IRQ_CFG_IRQ_POL BIT(4) BIT 27 drivers/net/dsa/lan9303-core.c # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0) BIT 29 drivers/net/dsa/lan9303-core.c # define LAN9303_INT_STS_PHY_INT2 BIT(27) BIT 30 drivers/net/dsa/lan9303-core.c # define LAN9303_INT_STS_PHY_INT1 BIT(26) BIT 32 drivers/net/dsa/lan9303-core.c # define LAN9303_INT_EN_PHY_INT2_EN BIT(27) BIT 33 drivers/net/dsa/lan9303-core.c # define LAN9303_INT_EN_PHY_INT1_EN BIT(26) BIT 35 drivers/net/dsa/lan9303-core.c # define LAN9303_HW_CFG_READY BIT(27) BIT 36 drivers/net/dsa/lan9303-core.c # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26) BIT 37 drivers/net/dsa/lan9303-core.c # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25) BIT 42 drivers/net/dsa/lan9303-core.c # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0) BIT 43 drivers/net/dsa/lan9303-core.c # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1) BIT 49 drivers/net/dsa/lan9303-core.c #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31) BIT 50 drivers/net/dsa/lan9303-core.c #define LAN9303_SWITCH_CSR_CMD_RW BIT(30) BIT 51 drivers/net/dsa/lan9303-core.c #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16)) BIT 54 drivers/net/dsa/lan9303-core.c #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/ BIT 61 drivers/net/dsa/lan9303-core.c #define LAN9303_SW_RESET_RESET BIT(0) BIT 66 drivers/net/dsa/lan9303-core.c # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1) BIT 67 drivers/net/dsa/lan9303-core.c # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0) BIT 91 drivers/net/dsa/lan9303-core.c # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1) BIT 92 drivers/net/dsa/lan9303-core.c # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0) BIT 119 drivers/net/dsa/lan9303-core.c # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2) BIT 120 drivers/net/dsa/lan9303-core.c # define LAN9303_ALR_CMD_GET_FIRST BIT(1) BIT 121 drivers/net/dsa/lan9303-core.c # define LAN9303_ALR_CMD_GET_NEXT BIT(0) BIT 124 drivers/net/dsa/lan9303-core.c # define LAN9303_ALR_DAT1_VALID BIT(26) BIT 125 drivers/net/dsa/lan9303-core.c # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25) BIT 126 drivers/net/dsa/lan9303-core.c # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25) BIT 127 drivers/net/dsa/lan9303-core.c # define LAN9303_ALR_DAT1_STATIC BIT(24) BIT 133 drivers/net/dsa/lan9303-core.c # define ALR_STS_MAKE_PEND BIT(0) BIT 135 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_VLAN_CMD_RNW BIT(5) BIT 136 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4) BIT 139 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17) BIT 140 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16) BIT 141 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15) BIT 142 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14) BIT 143 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13) BIT 144 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12) BIT 147 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7) BIT 148 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p) BIT 151 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5) BIT 152 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4) BIT 154 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3) BIT 155 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2) BIT 157 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1) BIT 158 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0) BIT 161 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8) BIT 162 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7) BIT 163 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6) BIT 164 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5) BIT 165 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4) BIT 166 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3) BIT 167 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2) BIT 168 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1) BIT 169 drivers/net/dsa/lan9303-core.c # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0) BIT 175 drivers/net/dsa/lan9303-core.c # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16)) BIT 176 drivers/net/dsa/lan9303-core.c # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8)) BIT 177 drivers/net/dsa/lan9303-core.c # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0)) BIT 615 drivers/net/dsa/lan9303-core.c if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC)) BIT 636 drivers/net/dsa/lan9303-core.c if ((BIT(dump_ctx->port) & portmap) == 0) BIT 690 drivers/net/dsa/lan9303-core.c entr->port_map |= BIT(port); BIT 708 drivers/net/dsa/lan9303-core.c entr->port_map &= ~BIT(port); BIT 51 drivers/net/dsa/lantiq_gswip.c #define GSWIP_MDIO_GLOB_ENABLE BIT(15) BIT 53 drivers/net/dsa/lantiq_gswip.c #define GSWIP_MDIO_CTRL_BUSY BIT(12) BIT 54 drivers/net/dsa/lantiq_gswip.c #define GSWIP_MDIO_CTRL_RD BIT(11) BIT 55 drivers/net/dsa/lantiq_gswip.c #define GSWIP_MDIO_CTRL_WR BIT(10) BIT 97 drivers/net/dsa/lantiq_gswip.c #define GSWIP_MII_CFG_EN BIT(14) BIT 98 drivers/net/dsa/lantiq_gswip.c #define GSWIP_MII_CFG_LDCLKDIS BIT(12) BIT 119 drivers/net/dsa/lantiq_gswip.c #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ BIT 120 drivers/net/dsa/lantiq_gswip.c #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ BIT 134 drivers/net/dsa/lantiq_gswip.c #define GSWIP_BM_RAM_CTRL_BAS BIT(15) BIT 135 drivers/net/dsa/lantiq_gswip.c #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) BIT 138 drivers/net/dsa/lantiq_gswip.c #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) BIT 141 drivers/net/dsa/lantiq_gswip.c #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ BIT 142 drivers/net/dsa/lantiq_gswip.c #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ BIT 145 drivers/net/dsa/lantiq_gswip.c #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ BIT 146 drivers/net/dsa/lantiq_gswip.c #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ BIT 154 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) BIT 155 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) BIT 156 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) BIT 157 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) BIT 169 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ BIT 170 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) BIT 171 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ BIT 173 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ BIT 174 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ BIT 176 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ BIT 177 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ BIT 178 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ BIT 186 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ BIT 187 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ BIT 188 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ BIT 189 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ BIT 190 drivers/net/dsa/lantiq_gswip.c #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ BIT 195 drivers/net/dsa/lantiq_gswip.c #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ BIT 199 drivers/net/dsa/lantiq_gswip.c #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ BIT 200 drivers/net/dsa/lantiq_gswip.c #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ BIT 210 drivers/net/dsa/lantiq_gswip.c #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ BIT 211 drivers/net/dsa/lantiq_gswip.c #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ BIT 212 drivers/net/dsa/lantiq_gswip.c #define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */ BIT 628 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); BIT 674 drivers/net/dsa/lantiq_gswip.c gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0); BIT 692 drivers/net/dsa/lantiq_gswip.c gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0); BIT 745 drivers/net/dsa/lantiq_gswip.c if (!!(priv->port_vlan_filter & BIT(port)) != vlan_filtering && bridge) BIT 798 drivers/net/dsa/lantiq_gswip.c gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); BIT 799 drivers/net/dsa/lantiq_gswip.c gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); BIT 800 drivers/net/dsa/lantiq_gswip.c gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); BIT 953 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] |= BIT(cpu_port); BIT 954 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] |= BIT(port); BIT 1022 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] |= BIT(cpu_port); BIT 1023 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[2] |= BIT(cpu_port); BIT 1024 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] |= BIT(port); BIT 1026 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[2] &= ~BIT(port); BIT 1028 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[2] |= BIT(port); BIT 1077 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[1] &= ~BIT(port); BIT 1078 drivers/net/dsa/lantiq_gswip.c vlan_mapping.val[2] &= ~BIT(port); BIT 1086 drivers/net/dsa/lantiq_gswip.c if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { BIT 1115 drivers/net/dsa/lantiq_gswip.c priv->port_vlan_filter &= ~BIT(port); BIT 1117 drivers/net/dsa/lantiq_gswip.c priv->port_vlan_filter |= BIT(port); BIT 1331 drivers/net/dsa/lantiq_gswip.c mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ BIT 1384 drivers/net/dsa/lantiq_gswip.c if (mac_bridge.val[0] & BIT(port)) BIT 202 drivers/net/dsa/microchip/ksz8795.c ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); BIT 207 drivers/net/dsa/microchip/ksz8795.c ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); BIT 215 drivers/net/dsa/microchip/ksz8795.c ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); BIT 217 drivers/net/dsa/microchip/ksz8795.c ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); BIT 713 drivers/net/dsa/microchip/ksz8795.c if (dev->br_member & BIT(port)) { BIT 714 drivers/net/dsa/microchip/ksz8795.c dev->member |= BIT(port); BIT 734 drivers/net/dsa/microchip/ksz8795.c dev->rx_ports |= BIT(port); BIT 736 drivers/net/dsa/microchip/ksz8795.c dev->rx_ports &= ~BIT(port); BIT 738 drivers/net/dsa/microchip/ksz8795.c dev->tx_ports |= BIT(port); BIT 740 drivers/net/dsa/microchip/ksz8795.c dev->tx_ports &= ~BIT(port); BIT 748 drivers/net/dsa/microchip/ksz8795.c if (dev->br_member & BIT(port)) BIT 749 drivers/net/dsa/microchip/ksz8795.c dev->member &= ~BIT(port); BIT 822 drivers/net/dsa/microchip/ksz8795.c member |= BIT(port); BIT 857 drivers/net/dsa/microchip/ksz8795.c member &= ~BIT(port); BIT 886 drivers/net/dsa/microchip/ksz8795.c dev->mirror_rx |= BIT(port); BIT 889 drivers/net/dsa/microchip/ksz8795.c dev->mirror_tx |= BIT(port); BIT 910 drivers/net/dsa/microchip/ksz8795.c dev->mirror_rx &= ~BIT(port); BIT 913 drivers/net/dsa/microchip/ksz8795.c dev->mirror_tx &= ~BIT(port); BIT 982 drivers/net/dsa/microchip/ksz8795.c dev->on_ports |= BIT(port); BIT 986 drivers/net/dsa/microchip/ksz8795.c dev->live_ports |= BIT(port); BIT 1017 drivers/net/dsa/microchip/ksz8795.c p->vid_member = BIT(i); BIT 1178 drivers/net/dsa/microchip/ksz8795.c dev->host_mask = BIT(dev->cpu_port); BIT 1248 drivers/net/dsa/microchip/ksz8795.c dev->port_mask = BIT(dev->port_cnt) - 1; BIT 34 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_NEW_BACKOFF BIT(7) BIT 35 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_GLOBAL_RESET BIT(6) BIT 36 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_FLUSH_DYN_MAC_TABLE BIT(5) BIT 37 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_FLUSH_STA_MAC_TABLE BIT(4) BIT 38 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_LINK_AUTO_AGING BIT(0) BIT 42 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_HUGE_PACKET BIT(6) BIT 43 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_TX_FLOW_CTRL_DISABLE BIT(5) BIT 44 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_RX_FLOW_CTRL_DISABLE BIT(4) BIT 45 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_CHECK_LENGTH BIT(3) BIT 46 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_AGING_ENABLE BIT(2) BIT 47 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_FAST_AGING BIT(1) BIT 48 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_AGGR_BACKOFF BIT(0) BIT 52 drivers/net/dsa/microchip/ksz8795_reg.h #define UNICAST_VLAN_BOUNDARY BIT(7) BIT 53 drivers/net/dsa/microchip/ksz8795_reg.h #define MULTICAST_STORM_DISABLE BIT(6) BIT 54 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_BACK_PRESSURE BIT(5) BIT 55 drivers/net/dsa/microchip/ksz8795_reg.h #define FAIR_FLOW_CTRL BIT(4) BIT 56 drivers/net/dsa/microchip/ksz8795_reg.h #define NO_EXC_COLLISION_DROP BIT(3) BIT 57 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_LEGAL_PACKET_DISABLE BIT(1) BIT 60 drivers/net/dsa/microchip/ksz8795_reg.h #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3) BIT 62 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_VLAN_ENABLE BIT(7) BIT 63 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_IGMP_SNOOP BIT(6) BIT 64 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_MIRROR_RX_TX BIT(0) BIT 68 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_HALF_DUPLEX_FLOW_CTRL BIT(7) BIT 69 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_HALF_DUPLEX BIT(6) BIT 70 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_FLOW_CTRL BIT(5) BIT 71 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_10_MBIT BIT(4) BIT 72 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_REPLACE_VID BIT(3) BIT 82 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_MIB_COUNTER_FLUSH BIT(7) BIT 83 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_MIB_COUNTER_FREEZE BIT(6) BIT 101 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_TAIL_TAG_ENABLE BIT(1) BIT 102 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_PASS_PAUSE BIT(0) BIT 108 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_PLL_POWER_DOWN BIT(5) BIT 123 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_BROADCAST_STORM BIT(7) BIT 124 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_DIFFSERV_ENABLE BIT(6) BIT 125 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_802_1P_ENABLE BIT(5) BIT 132 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_INSERT_TAG BIT(2) BIT 133 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_REMOVE_TAG BIT(1) BIT 134 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_QUEUE_SPLIT_L BIT(0) BIT 142 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_MIRROR_SNIFFER BIT(7) BIT 143 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_MIRROR_RX BIT(6) BIT 144 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_MIRROR_TX BIT(5) BIT 153 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_802_1P_REMAPPING BIT(7) BIT 154 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_INGRESS_FILTER BIT(6) BIT 155 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_DISCARD_NON_VID BIT(5) BIT 156 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_FORCE_FLOW_CTRL BIT(4) BIT 157 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_BACK_PRESSURE BIT(3) BIT 158 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_TX_ENABLE BIT(2) BIT 159 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_RX_ENABLE BIT(1) BIT 160 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_LEARN_DISABLE BIT(0) BIT 181 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_ACL_ENABLE BIT(2) BIT 189 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_MII_INTERNAL_CLOCK BIT(7) BIT 190 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_GMII_1GPS_MODE BIT(6) BIT 191 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_RGMII_ID_IN_ENABLE BIT(4) BIT 192 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_RGMII_ID_OUT_ENABLE BIT(3) BIT 193 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_GMII_MAC_MODE BIT(2) BIT 205 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_AUTO_NEG_ASYM_PAUSE BIT(5) BIT 206 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_AUTO_NEG_SYM_PAUSE BIT(4) BIT 207 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_AUTO_NEG_100BTX_FD BIT(3) BIT 208 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_AUTO_NEG_100BTX BIT(2) BIT 209 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_AUTO_NEG_10BT_FD BIT(1) BIT 210 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_AUTO_NEG_10BT BIT(0) BIT 218 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_FIBER_MODE BIT(7) BIT 220 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_REMOTE_ASYM_PAUSE BIT(5) BIT 221 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_REMOTE_SYM_PAUSE BIT(4) BIT 222 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_REMOTE_100BTX_FD BIT(3) BIT 223 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_REMOTE_100BTX BIT(2) BIT 224 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_REMOTE_10BT_FD BIT(1) BIT 225 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_REMOTE_10BT BIT(0) BIT 232 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_HP_MDIX BIT(7) BIT 233 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_REVERSED_POLARITY BIT(5) BIT 234 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_TX_FLOW_CTRL BIT(4) BIT 235 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_RX_FLOW_CTRL BIT(3) BIT 236 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_STAT_SPEED_100MBIT BIT(2) BIT 237 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_STAT_FULL_DUPLEX BIT(1) BIT 239 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_REMOTE_FAULT BIT(0) BIT 246 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_CABLE_10M_SHORT BIT(7) BIT 253 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_START_CABLE_DIAG BIT(4) BIT 254 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_FORCE_LINK BIT(3) BIT 255 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_POWER_SAVING BIT(2) BIT 256 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_PHY_REMOTE_LOOPBACK BIT(1) BIT 272 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_AUTO_NEG_DISABLE BIT(7) BIT 273 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_FORCE_100_MBIT BIT(6) BIT 274 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_FORCE_FULL_DUPLEX BIT(5) BIT 281 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_LED_OFF BIT(7) BIT 282 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_TX_DISABLE BIT(6) BIT 283 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_AUTO_NEG_RESTART BIT(5) BIT 284 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_POWER_DOWN BIT(3) BIT 285 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_AUTO_MDIX_DISABLE BIT(2) BIT 286 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_FORCE_MDIX BIT(1) BIT 287 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_MAC_LOOPBACK BIT(0) BIT 294 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_MDIX_STATUS BIT(7) BIT 295 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_AUTO_NEG_COMPLETE BIT(6) BIT 296 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_STAT_LINK_GOOD BIT(5) BIT 303 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_PHY_LOOPBACK BIT(7) BIT 304 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_PHY_ISOLATE BIT(5) BIT 305 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_PHY_SOFT_RESET BIT(4) BIT 306 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_PHY_FORCE_LINK BIT(3) BIT 370 drivers/net/dsa/microchip/ksz8795_reg.h #define TABLE_READ BIT(4) BIT 406 drivers/net/dsa/microchip/ksz8795_reg.h #define INT_PME BIT(4) BIT 411 drivers/net/dsa/microchip/ksz8795_reg.h #define INT_PORT_5 BIT(4) BIT 412 drivers/net/dsa/microchip/ksz8795_reg.h #define INT_PORT_4 BIT(3) BIT 413 drivers/net/dsa/microchip/ksz8795_reg.h #define INT_PORT_3 BIT(2) BIT 414 drivers/net/dsa/microchip/ksz8795_reg.h #define INT_PORT_2 BIT(1) BIT 415 drivers/net/dsa/microchip/ksz8795_reg.h #define INT_PORT_1 BIT(0) BIT 443 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_SELF_ADDR_FILTER_ENABLE BIT(6) BIT 450 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_UNK_FWD_ENABLE BIT(5) BIT 460 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3) BIT 461 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_INS_TAG_ENABLE BIT(2) BIT 499 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_IPV6_MLD_OPTION BIT(3) BIT 500 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_IPV6_MLD_SNOOP BIT(2) BIT 508 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_PASS_ALL BIT(6) BIT 510 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_INS_TAG_FOR_PORT_5 BIT(3) BIT 511 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_INS_TAG_FOR_PORT_4 BIT(2) BIT 512 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_INS_TAG_FOR_PORT_3 BIT(1) BIT 513 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_INS_TAG_FOR_PORT_2 BIT(0) BIT 521 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_QUEUE_SPLIT_H BIT(1) BIT 525 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_DROP_TAG BIT(0) BIT 569 drivers/net/dsa/microchip/ksz8795_reg.h #define RATE_CTRL_ENABLE BIT(7) BIT 570 drivers/net/dsa/microchip/ksz8795_reg.h #define RATE_RATIO_M (BIT(7) - 1) BIT 572 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_OUT_RATE_ENABLE BIT(7) BIT 587 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S) BIT 588 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S) BIT 589 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S) BIT 594 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S) BIT 595 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S) BIT 618 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_IN_RATE_ENABLE BIT(7) BIT 619 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_RATE_LIMIT_M (BIT(7) - 1) BIT 644 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_PME_OUTPUT_ENABLE BIT(1) BIT 645 drivers/net/dsa/microchip/ksz8795_reg.h #define SW_PME_ACTIVE_HIGH BIT(0) BIT 647 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_MAGIC_PACKET_DETECT BIT(2) BIT 648 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_LINK_UP_DETECT BIT(1) BIT 649 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_ENERGY_DETECT BIT(0) BIT 673 drivers/net/dsa/microchip/ksz8795_reg.h #define ACL_SRC BIT(1) BIT 674 drivers/net/dsa/microchip/ksz8795_reg.h #define ACL_EQUAL BIT(0) BIT 690 drivers/net/dsa/microchip/ksz8795_reg.h #define ACL_TCP_FLAG_ENABLE BIT(0) BIT 706 drivers/net/dsa/microchip/ksz8795_reg.h #define ACL_VLAN_PRIO_REPLACE BIT(2) BIT 720 drivers/net/dsa/microchip/ksz8795_reg.h #define ACL_CNT_M (BIT(11) - 1) BIT 722 drivers/net/dsa/microchip/ksz8795_reg.h #define ACL_MSEC_UNIT BIT(4) BIT 723 drivers/net/dsa/microchip/ksz8795_reg.h #define ACL_INTR_MODE BIT(3) BIT 746 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_ACL_WRITE_DONE BIT(6) BIT 747 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_ACL_READ_DONE BIT(5) BIT 748 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_ACL_WRITE BIT(4) BIT 753 drivers/net/dsa/microchip/ksz8795_reg.h #define PORT_ACL_FORCE_DLR_MISS BIT(0) BIT 758 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_RESET BIT(15) BIT 759 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_LOOPBACK BIT(14) BIT 760 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_SPEED_100MBIT BIT(13) BIT 761 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_ENABLE BIT(12) BIT 762 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_POWER_DOWN BIT(11) BIT 763 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_MII_DISABLE BIT(10) BIT 764 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_RESTART BIT(9) BIT 765 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_FULL_DUPLEX BIT(8) BIT 766 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_COLLISION_TEST_NOT BIT(7) BIT 767 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_HP_MDIX BIT(5) BIT 768 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_FORCE_MDIX BIT(4) BIT 769 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_MDIX_DISABLE BIT(3) BIT 770 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_FAULT_DISABLE BIT(2) BIT 771 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_TRANSMIT_DISABLE BIT(1) BIT 772 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_LED_DISABLE BIT(0) BIT 776 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_100BT4_CAPABLE BIT(15) BIT 777 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_100BTX_FD_CAPABLE BIT(14) BIT 778 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_100BTX_CAPABLE BIT(13) BIT 779 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_10BT_FD_CAPABLE BIT(12) BIT 780 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_10BT_CAPABLE BIT(11) BIT 781 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_MII_SUPPRESS_CAPABLE_NOT BIT(6) BIT 782 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_ACKNOWLEDGE BIT(5) BIT 783 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_FAULT BIT(4) BIT 784 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_CAPABLE BIT(3) BIT 785 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_LINK_STATUS BIT(2) BIT 786 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_JABBER_DETECT_NOT BIT(1) BIT 787 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_EXTENDED_CAPABILITY BIT(0) BIT 794 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_NEXT_PAGE_NOT BIT(15) BIT 795 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_REMOTE_FAULT_NOT BIT(13) BIT 796 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_SYM_PAUSE BIT(10) BIT 797 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_100BT4 BIT(9) BIT 798 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_100BTX_FD BIT(8) BIT 799 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_100BTX BIT(7) BIT 800 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_10BT_FD BIT(6) BIT 801 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_AUTO_NEG_10BT BIT(5) BIT 807 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_NEXT_PAGE_NOT BIT(15) BIT 808 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_ACKNOWLEDGE_NOT BIT(14) BIT 809 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_REMOTE_FAULT_NOT BIT(13) BIT 810 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_SYM_PAUSE BIT(10) BIT 811 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_100BTX_FD BIT(8) BIT 812 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_100BTX BIT(7) BIT 813 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_10BT_FD BIT(6) BIT 814 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_10BT BIT(5) BIT 824 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_START_CABLE_DIAG BIT(15) BIT 830 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_CABLE_10M_SHORT BIT(12) BIT 837 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_STAT_REVERSED_POLARITY BIT(5) BIT 838 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_STAT_MDIX BIT(4) BIT 839 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_FORCE_LINK BIT(3) BIT 840 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_POWER_SAVING_ENABLE BIT(2) BIT 841 drivers/net/dsa/microchip/ksz8795_reg.h #define PHY_REMOTE_LOOPBACK BIT(1) BIT 968 drivers/net/dsa/microchip/ksz8795_reg.h #define MIB_COUNTER_OVERFLOW BIT(6) BIT 969 drivers/net/dsa/microchip/ksz8795_reg.h #define MIB_COUNTER_VALID BIT(5) BIT 998 drivers/net/dsa/microchip/ksz8795_reg.h #define TAIL_TAG_OVERRIDE BIT(6) BIT 999 drivers/net/dsa/microchip/ksz8795_reg.h #define TAIL_TAG_LOOKUP BIT(7) BIT 21 drivers/net/dsa/microchip/ksz9477.c #define GBIT_SUPPORT BIT(0) BIT 22 drivers/net/dsa/microchip/ksz9477.c #define NEW_XMII BIT(1) BIT 23 drivers/net/dsa/microchip/ksz9477.c #define IS_9893 BIT(2) BIT 537 drivers/net/dsa/microchip/ksz9477.c vlan_table[1] |= BIT(port); BIT 539 drivers/net/dsa/microchip/ksz9477.c vlan_table[1] &= ~BIT(port); BIT 540 drivers/net/dsa/microchip/ksz9477.c vlan_table[1] &= ~(BIT(dev->cpu_port)); BIT 542 drivers/net/dsa/microchip/ksz9477.c vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); BIT 573 drivers/net/dsa/microchip/ksz9477.c vlan_table[2] &= ~BIT(port); BIT 579 drivers/net/dsa/microchip/ksz9477.c vlan_table[1] &= ~BIT(port); BIT 626 drivers/net/dsa/microchip/ksz9477.c alu_table[1] |= BIT(port); BIT 685 drivers/net/dsa/microchip/ksz9477.c alu_table[2] &= ~BIT(port); BIT 774 drivers/net/dsa/microchip/ksz9477.c if (alu.port_forward & BIT(port)) { BIT 841 drivers/net/dsa/microchip/ksz9477.c static_table[1] |= BIT(port); BIT 910 drivers/net/dsa/microchip/ksz9477.c static_table[1] &= ~BIT(port); BIT 44 drivers/net/dsa/microchip/ksz9477_reg.h #define PME_ENABLE BIT(1) BIT 45 drivers/net/dsa/microchip/ksz9477_reg.h #define PME_POLARITY BIT(0) BIT 49 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_GIGABIT_ABLE BIT(6) BIT 50 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_REDUNDANCY_ABLE BIT(5) BIT 51 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_AVB_ABLE BIT(4) BIT 69 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_QW_ABLE BIT(5) BIT 75 drivers/net/dsa/microchip/ksz9477_reg.h #define LUE_INT BIT(31) BIT 76 drivers/net/dsa/microchip/ksz9477_reg.h #define TRIG_TS_INT BIT(30) BIT 77 drivers/net/dsa/microchip/ksz9477_reg.h #define APB_TIMEOUT_INT BIT(29) BIT 88 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_SPARE_REG_2 BIT(7) BIT 89 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_SPARE_REG_1 BIT(6) BIT 90 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_SPARE_REG_0 BIT(5) BIT 91 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_BIG_ENDIAN BIT(4) BIT 92 drivers/net/dsa/microchip/ksz9477_reg.h #define SPI_AUTO_EDGE_DETECTION BIT(1) BIT 93 drivers/net/dsa/microchip/ksz9477_reg.h #define SPI_CLOCK_OUT_RISING_EDGE BIT(0) BIT 96 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_ENABLE_REFCLKO BIT(1) BIT 97 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_REFCLKO_IS_125MHZ BIT(0) BIT 101 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_ENABLE BIT(31) BIT 102 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_DA_MATCH BIT(30) BIT 103 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_INIT BIT(29) BIT 112 drivers/net/dsa/microchip/ksz9477_reg.h #define APB_TIMEOUT_ACKNOWLEDGE BIT(31) BIT 131 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_REQ BIT(31) BIT 132 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_RESP BIT(30) BIT 133 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_DA_MISMATCH BIT(14) BIT 134 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_FMT_MISMATCH BIT(13) BIT 135 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_CODE_ERROR BIT(12) BIT 136 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_CMD_ERROR BIT(11) BIT 137 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_CMD_LOC_M (BIT(6) - 1) BIT 153 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IBA_RETRY_CNT_M (BIT(5) - 1) BIT 158 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_PLL_POWER_DOWN BIT(5) BIT 167 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_DOUBLE_TAG BIT(7) BIT 168 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_RESET BIT(1) BIT 169 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_START BIT(0) BIT 186 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_SHAPING_CREDIT_ACCT BIT(1) BIT 187 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_POLICING_CREDIT_ACCT BIT(0) BIT 191 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_VLAN_ENABLE BIT(7) BIT 192 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_DROP_INVALID_VID BIT(6) BIT 195 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_RESV_MCAST_ENABLE BIT(2) BIT 203 drivers/net/dsa/microchip/ksz9477_reg.h #define UNICAST_LEARN_DISABLE BIT(7) BIT 204 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_SRC_ADDR_FILTER BIT(6) BIT 205 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_FLUSH_STP_TABLE BIT(5) BIT 206 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_FLUSH_MSTP_TABLE BIT(4) BIT 207 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_FWD_MCAST_SRC_ADDR BIT(3) BIT 208 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_AGING_ENABLE BIT(2) BIT 209 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_FAST_AGING BIT(1) BIT 210 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_LINK_AUTO_AGING BIT(0) BIT 214 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_TRAP_DOUBLE_TAG BIT(6) BIT 215 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_EGRESS_VLAN_FILTER_DYN BIT(5) BIT 216 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_EGRESS_VLAN_FILTER_STA BIT(4) BIT 233 drivers/net/dsa/microchip/ksz9477_reg.h #define LEARN_FAIL_INT BIT(2) BIT 234 drivers/net/dsa/microchip/ksz9477_reg.h #define ALMOST_FULL_INT BIT(1) BIT 235 drivers/net/dsa/microchip/ksz9477_reg.h #define WRITE_FAIL_INT BIT(0) BIT 249 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_UNK_UCAST_ENABLE BIT(31) BIT 253 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_UNK_MCAST_ENABLE BIT(31) BIT 257 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_UNK_VID_ENABLE BIT(31) BIT 261 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_NEW_BACKOFF BIT(7) BIT 262 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_CHECK_LENGTH BIT(3) BIT 263 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_PAUSE_UNH_MODE BIT(1) BIT 264 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_AGGR_BACKOFF BIT(0) BIT 268 drivers/net/dsa/microchip/ksz9477_reg.h #define MULTICAST_STORM_DISABLE BIT(6) BIT 269 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_BACK_PRESSURE BIT(5) BIT 270 drivers/net/dsa/microchip/ksz9477_reg.h #define FAIR_FLOW_CTRL BIT(4) BIT 271 drivers/net/dsa/microchip/ksz9477_reg.h #define NO_EXC_COLLISION_DROP BIT(3) BIT 272 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_JUMBO_PACKET BIT(2) BIT 273 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_LEGAL_PACKET_DISABLE BIT(1) BIT 274 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_PASS_SHORT_FRAME BIT(0) BIT 278 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_REPLACE_VID BIT(3) BIT 288 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_PASS_PAUSE BIT(3) BIT 292 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3) BIT 296 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_MIB_COUNTER_FLUSH BIT(7) BIT 297 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_MIB_COUNTER_FREEZE BIT(6) BIT 311 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_TOS_DSCP_REMARK BIT(1) BIT 312 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_TOS_DSCP_REMAP BIT(0) BIT 349 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IGMP_SNOOP BIT(6) BIT 350 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IPV6_MLD_OPTION BIT(3) BIT 351 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_IPV6_MLD_SNOOP BIT(2) BIT 352 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_MIRROR_RX_TX BIT(0) BIT 356 drivers/net/dsa/microchip/ksz9477_reg.h #define SW_CLASS_D_IP_ENABLE BIT(31) BIT 373 drivers/net/dsa/microchip/ksz9477_reg.h #define UNICAST_VLAN_BOUNDARY BIT(1) BIT 382 drivers/net/dsa/microchip/ksz9477_reg.h #define VLAN_VALID BIT(31) BIT 383 drivers/net/dsa/microchip/ksz9477_reg.h #define VLAN_FORWARD_OPTION BIT(27) BIT 399 drivers/net/dsa/microchip/ksz9477_reg.h #define VLAN_START BIT(7) BIT 412 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_DIRECT_INDEX_M (BIT(12) - 1) BIT 416 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_VALID_CNT_M (BIT(14) - 1) BIT 418 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_START BIT(7) BIT 419 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_VALID BIT(6) BIT 420 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_DIRECT BIT(2) BIT 428 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_STAT_INDEX_M (BIT(4) - 1) BIT 430 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1) BIT 431 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_STAT_START BIT(7) BIT 432 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_RESV_MCAST_ADDR BIT(1) BIT 433 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_STAT_READ BIT(0) BIT 437 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_V_STATIC_VALID BIT(31) BIT 438 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_V_SRC_FILTER BIT(30) BIT 439 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_V_DST_FILTER BIT(29) BIT 440 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1) BIT 446 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_V_OVERRIDE BIT(31) BIT 447 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_V_USE_FID BIT(30) BIT 448 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_V_PORT_MAP (BIT(24) - 1) BIT 452 drivers/net/dsa/microchip/ksz9477_reg.h #define ALU_V_FID_M (BIT(16) - 1) BIT 467 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_INDEX_MAX BIT(9) BIT 472 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_PATH_INDEX_M (BIT(4) - 1) BIT 476 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_VALID_CNT_M (BIT(14) - 1) BIT 478 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_START BIT(7) BIT 479 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_VALID BIT(6) BIT 480 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_SEARCH_END BIT(5) BIT 481 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_DIRECT BIT(2) BIT 489 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_V_STATIC_VALID BIT(31) BIT 490 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_V_AGE_CNT_M (BIT(3) - 1) BIT 492 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_V_PATH_ID_M (BIT(4) - 1) BIT 518 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_V_SEQ_M (BIT(16) - 1) BIT 523 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_STEP_ADJ BIT(6) BIT 524 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_STEP_DIR BIT(5) BIT 525 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_READ_TIME BIT(4) BIT 526 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_LOAD_TIME BIT(3) BIT 527 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_CLK_ADJ_ENABLE BIT(2) BIT 528 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_CLK_ENABLE BIT(1) BIT 529 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_CLK_RESET BIT(0) BIT 546 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_RATE_DIR BIT(31) BIT 547 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_TMP_RATE_ENABLE BIT(30) BIT 557 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_802_1AS BIT(7) BIT 558 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_ENABLE BIT(6) BIT 559 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_ETH_ENABLE BIT(5) BIT 560 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_IPV4_UDP_ENABLE BIT(4) BIT 561 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_IPV6_UDP_ENABLE BIT(3) BIT 562 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_TC_P2P BIT(2) BIT 563 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_MASTER BIT(1) BIT 564 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_1STEP BIT(0) BIT 568 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_UNICAST_ENABLE BIT(12) BIT 569 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_ALTERNATE_MASTER BIT(11) BIT 570 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_ALL_HIGH_PRIO BIT(10) BIT 571 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_SYNC_CHECK BIT(9) BIT 572 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_DELAY_CHECK BIT(8) BIT 573 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_PDELAY_CHECK BIT(7) BIT 574 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_DROP_SYNC_DELAY_REQ BIT(5) BIT 575 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_DOMAIN_CHECK BIT(4) BIT 576 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_UDP_CHECKSUM BIT(2) BIT 605 drivers/net/dsa/microchip/ksz9477_reg.h #define GPIO_IN BIT(7) BIT 606 drivers/net/dsa/microchip/ksz9477_reg.h #define GPIO_OUT BIT(6) BIT 607 drivers/net/dsa/microchip/ksz9477_reg.h #define TS_INT_ENABLE BIT(5) BIT 608 drivers/net/dsa/microchip/ksz9477_reg.h #define TRIG_ACTIVE BIT(4) BIT 609 drivers/net/dsa/microchip/ksz9477_reg.h #define TRIG_ENABLE BIT(3) BIT 610 drivers/net/dsa/microchip/ksz9477_reg.h #define TRIG_RESET BIT(2) BIT 611 drivers/net/dsa/microchip/ksz9477_reg.h #define TS_ENABLE BIT(1) BIT 612 drivers/net/dsa/microchip/ksz9477_reg.h #define TS_RESET BIT(0) BIT 627 drivers/net/dsa/microchip/ksz9477_reg.h #define TRIG_CASCADE_ENABLE BIT(31) BIT 628 drivers/net/dsa/microchip/ksz9477_reg.h #define TRIG_CASCADE_TAIL BIT(30) BIT 631 drivers/net/dsa/microchip/ksz9477_reg.h #define TRIG_NOW BIT(25) BIT 632 drivers/net/dsa/microchip/ksz9477_reg.h #define TRIG_NOTIFY BIT(24) BIT 633 drivers/net/dsa/microchip/ksz9477_reg.h #define TRIG_EDGE BIT(23) BIT 665 drivers/net/dsa/microchip/ksz9477_reg.h #define TS_EVENT_OVERFLOW BIT(16) BIT 668 drivers/net/dsa/microchip/ksz9477_reg.h #define TS_DETECT_RISE BIT(7) BIT 669 drivers/net/dsa/microchip/ksz9477_reg.h #define TS_DETECT_FALL BIT(6) BIT 671 drivers/net/dsa/microchip/ksz9477_reg.h #define TS_CASCADE_TAIL BIT(5) BIT 674 drivers/net/dsa/microchip/ksz9477_reg.h #define TS_CASCADE_ENABLE BIT(0) BIT 713 drivers/net/dsa/microchip/ksz9477_reg.h #define TS_EVENT_NANOSEC_M (BIT(30) - 1) BIT 727 drivers/net/dsa/microchip/ksz9477_reg.h #define DLR_SRC_PORT_UNICAST BIT(31) BIT 736 drivers/net/dsa/microchip/ksz9477_reg.h #define DLR_RESET_SEQ_ID BIT(3) BIT 737 drivers/net/dsa/microchip/ksz9477_reg.h #define DLR_BACKUP_AUTO_ON BIT(2) BIT 738 drivers/net/dsa/microchip/ksz9477_reg.h #define DLR_BEACON_TX_ENABLE BIT(1) BIT 739 drivers/net/dsa/microchip/ksz9477_reg.h #define DLR_ASSIST_ENABLE BIT(0) BIT 759 drivers/net/dsa/microchip/ksz9477_reg.h #define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1) BIT 763 drivers/net/dsa/microchip/ksz9477_reg.h #define DLR_VLAN_ID_M (BIT(12) - 1) BIT 783 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_DUPLICATE_DISCARD BIT(7) BIT 784 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_NODE_UNICAST BIT(6) BIT 787 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_LEARN_MCAST_DISABLE BIT(2) BIT 796 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_LEARN_UCAST_DISABLE BIT(7) BIT 797 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_FLUSH_TABLE BIT(5) BIT 798 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_PROC_MCAST_SRC BIT(3) BIT 799 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_AGING_ENABLE BIT(2) BIT 808 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_WINDOW_OVERFLOW_INT BIT(3) BIT 809 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_LEARN_FAIL_INT BIT(2) BIT 810 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_ALMOST_FULL_INT BIT(1) BIT 811 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_WRITE_FAIL_INT BIT(0) BIT 815 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_ENTRY_INDEX_M (BIT(10) - 1) BIT 816 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_FAIL_INDEX_M (BIT(8) - 1) BIT 820 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1) BIT 824 drivers/net/dsa/microchip/ksz9477_reg.h #define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1) BIT 839 drivers/net/dsa/microchip/ksz9477_reg.h #define PME_WOL_MAGICPKT BIT(2) BIT 840 drivers/net/dsa/microchip/ksz9477_reg.h #define PME_WOL_LINKUP BIT(1) BIT 841 drivers/net/dsa/microchip/ksz9477_reg.h #define PME_WOL_ENERGY BIT(0) BIT 846 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_SGMII_INT BIT(3) BIT 847 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_PTP_INT BIT(2) BIT 848 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_PHY_INT BIT(1) BIT 849 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_ACL_INT BIT(0) BIT 856 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MAC_LOOPBACK BIT(7) BIT 857 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_FORCE_TX_FLOW_CTRL BIT(4) BIT 858 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_FORCE_RX_FLOW_CTRL BIT(3) BIT 859 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_TAIL_TAG_ENABLE BIT(2) BIT 870 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_INTF_FULL_DUPLEX BIT(2) BIT 871 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_TX_FLOW_CTRL BIT(1) BIT 872 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_RX_FLOW_CTRL BIT(0) BIT 879 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_PHY_RESET BIT(15) BIT 880 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_PHY_LOOPBACK BIT(14) BIT 881 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_SPEED_100MBIT BIT(13) BIT 882 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_ENABLE BIT(12) BIT 883 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_POWER_DOWN BIT(11) BIT 884 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_ISOLATE BIT(10) BIT 885 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_RESTART BIT(9) BIT 886 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_FULL_DUPLEX BIT(8) BIT 887 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_COLLISION_TEST BIT(7) BIT 888 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_SPEED_1000MBIT BIT(6) BIT 892 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_100BT4_CAPABLE BIT(15) BIT 893 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_100BTX_FD_CAPABLE BIT(14) BIT 894 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_100BTX_CAPABLE BIT(13) BIT 895 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_10BT_FD_CAPABLE BIT(12) BIT 896 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_10BT_CAPABLE BIT(11) BIT 897 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_EXTENDED_STATUS BIT(8) BIT 898 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MII_SUPPRESS_CAPABLE BIT(6) BIT 899 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5) BIT 900 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_FAULT BIT(4) BIT 901 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_CAPABLE BIT(3) BIT 902 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_LINK_STATUS BIT(2) BIT 903 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_JABBER_DETECT BIT(1) BIT 904 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_EXTENDED_CAPABILITY BIT(0) BIT 914 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_NEXT_PAGE BIT(15) BIT 915 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_REMOTE_FAULT BIT(13) BIT 916 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_ASYM_PAUSE BIT(11) BIT 917 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_SYM_PAUSE BIT(10) BIT 918 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_100BT4 BIT(9) BIT 919 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_100BTX_FD BIT(8) BIT 920 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_100BTX BIT(7) BIT 921 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_10BT_FD BIT(6) BIT 922 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_10BT BIT(5) BIT 931 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_NEXT_PAGE BIT(15) BIT 932 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_ACKNOWLEDGE BIT(14) BIT 933 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_REMOTE_FAULT BIT(13) BIT 934 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_ASYM_PAUSE BIT(11) BIT 935 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_SYM_PAUSE BIT(10) BIT 936 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_100BTX_FD BIT(8) BIT 937 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_100BTX BIT(7) BIT 938 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_10BT_FD BIT(6) BIT 939 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_10BT BIT(5) BIT 943 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_MANUAL BIT(12) BIT 944 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_MASTER BIT(11) BIT 945 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10) BIT 946 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_1000BT_FD BIT(9) BIT 947 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_AUTO_NEG_1000BT BIT(8) BIT 951 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MASTER_FAULT BIT(15) BIT 952 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_LOCAL_MASTER BIT(14) BIT 953 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_LOCAL_RX_OK BIT(13) BIT 954 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_RX_OK BIT(12) BIT 955 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_1000BT_FD BIT(11) BIT 956 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_1000BT BIT(10) BIT 987 drivers/net/dsa/microchip/ksz9477_reg.h #define DSP_SQI_ERR_DETECTED BIT(15) BIT 995 drivers/net/dsa/microchip/ksz9477_reg.h #define EEE_ADV_100MBIT BIT(1) BIT 996 drivers/net/dsa/microchip/ksz9477_reg.h #define EEE_ADV_1GBIT BIT(2) BIT 1005 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_100BTX_FD_ABLE BIT(15) BIT 1006 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_100BTX_ABLE BIT(14) BIT 1007 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_10BT_FD_ABLE BIT(13) BIT 1008 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_10BT_ABLE BIT(12) BIT 1011 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_SGMII_AUTO_INCR BIT(23) BIT 1014 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_SGMII_ADDR_M (BIT(21) - 1) BIT 1017 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_SGMII_DATA_M (BIT(16) - 1) BIT 1031 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_RESET BIT(15) BIT 1032 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_LOOPBACK BIT(14) BIT 1033 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_SPEED_100MBIT BIT(13) BIT 1034 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_AUTO_NEG_ENABLE BIT(12) BIT 1035 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_POWER_DOWN BIT(11) BIT 1036 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_AUTO_NEG_RESTART BIT(9) BIT 1037 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_FULL_DUPLEX BIT(8) BIT 1038 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_SPEED_1000MBIT BIT(6) BIT 1045 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15) BIT 1058 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6) BIT 1059 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5) BIT 1069 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_8_BIT BIT(8) BIT 1070 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_SGMII_LINK_UP BIT(4) BIT 1071 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_TX_CFG_PHY_MASTER BIT(3) BIT 1075 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0) BIT 1079 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_STAT_LINK_UP BIT(4) BIT 1085 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_STAT_FULL_DUPLEX BIT(1) BIT 1091 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_PHY_WRITE BIT(1) BIT 1092 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_PHY_START_BUSY BIT(0) BIT 1096 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_PHY_ADDR_M (BIT(16) - 1) BIT 1100 drivers/net/dsa/microchip/ksz9477_reg.h #define SR_MII_PHY_DATA_M (BIT(16) - 1) BIT 1107 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REMOTE_LOOPBACK BIT(8) BIT 1110 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_LED_CTRL_TEST BIT(3) BIT 1111 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_10BT_PREAMBLE BIT(2) BIT 1112 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_LINK_MD_10BT_ENABLE BIT(1) BIT 1113 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_LINK_MD_PASS BIT(0) BIT 1117 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_START_CABLE_DIAG BIT(15) BIT 1118 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_TX_DISABLE BIT(14) BIT 1133 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_1000_LINK_GOOD BIT(1) BIT 1134 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_100_LINK_GOOD BIT(0) BIT 1138 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_LINK_DETECT BIT(14) BIT 1139 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_SIGNAL_DETECT BIT(13) BIT 1140 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_PHY_STAT_MDI BIT(12) BIT 1141 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_PHY_STAT_MASTER BIT(11) BIT 1148 drivers/net/dsa/microchip/ksz9477_reg.h #define JABBER_INT BIT(7) BIT 1149 drivers/net/dsa/microchip/ksz9477_reg.h #define RX_ERR_INT BIT(6) BIT 1150 drivers/net/dsa/microchip/ksz9477_reg.h #define PAGE_RX_INT BIT(5) BIT 1151 drivers/net/dsa/microchip/ksz9477_reg.h #define PARALLEL_DETECT_FAULT_INT BIT(4) BIT 1152 drivers/net/dsa/microchip/ksz9477_reg.h #define LINK_PARTNER_ACK_INT BIT(3) BIT 1153 drivers/net/dsa/microchip/ksz9477_reg.h #define LINK_DOWN_INT BIT(2) BIT 1154 drivers/net/dsa/microchip/ksz9477_reg.h #define REMOTE_FAULT_INT BIT(1) BIT 1155 drivers/net/dsa/microchip/ksz9477_reg.h #define LINK_UP_INT BIT(0) BIT 1159 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_REG_CLK_SPEED_25_MHZ BIT(14) BIT 1160 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_PHY_FORCE_MDI BIT(7) BIT 1161 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_PHY_AUTO_MDIX_DISABLE BIT(6) BIT 1164 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_PHY_PCS_LOOPBACK BIT(0) BIT 1170 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_100BT_FIXED_LATENCY BIT(15) BIT 1174 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_INT_PIN_HIGH BIT(14) BIT 1175 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_ENABLE_JABBER BIT(9) BIT 1176 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_STAT_SPEED_1000MBIT BIT(6) BIT 1177 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_STAT_SPEED_100MBIT BIT(5) BIT 1178 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_STAT_SPEED_10MBIT BIT(4) BIT 1179 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_STAT_FULL_DUPLEX BIT(3) BIT 1182 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_STAT_MASTER BIT(2) BIT 1183 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_RESET BIT(1) BIT 1184 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_LINK_STATUS_FAIL BIT(0) BIT 1189 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_SGMII_SEL BIT(7) BIT 1190 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MII_FULL_DUPLEX BIT(6) BIT 1191 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MII_100MBIT BIT(4) BIT 1192 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_GRXC_ENABLE BIT(0) BIT 1196 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_RMII_CLK_SEL BIT(7) BIT 1198 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MII_1000MBIT_S1 BIT(6) BIT 1200 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MII_NOT_1GBIT BIT(6) BIT 1201 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MII_SEL_EDGE BIT(5) BIT 1202 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_RGMII_ID_IG_ENABLE BIT(4) BIT 1203 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_RGMII_ID_EG_ENABLE BIT(3) BIT 1204 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MII_MAC_MODE BIT(2) BIT 1220 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_BROADCAST_STORM BIT(1) BIT 1221 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_JUMBO_FRAME BIT(0) BIT 1225 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_BACK_PRESSURE BIT(3) BIT 1226 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_PASS_ALL BIT(0) BIT 1230 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_100BT_EEE_DISABLE BIT(7) BIT 1231 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_1000BT_EEE_DISABLE BIT(6) BIT 1240 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_IN_PORT_BASED BIT(6) BIT 1241 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_IN_PACKET_BASED BIT(5) BIT 1242 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_IN_FLOW_CTRL BIT(4) BIT 1249 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_COUNT_IFG BIT(1) BIT 1250 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_COUNT_PREAMBLE BIT(0) BIT 1266 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_RATE_LIMIT_M (BIT(7) - 1) BIT 1271 drivers/net/dsa/microchip/ksz9477_reg.h #define MIB_COUNTER_OVERFLOW BIT(31) BIT 1272 drivers/net/dsa/microchip/ksz9477_reg.h #define MIB_COUNTER_VALID BIT(30) BIT 1273 drivers/net/dsa/microchip/ksz9477_reg.h #define MIB_COUNTER_READ BIT(25) BIT 1274 drivers/net/dsa/microchip/ksz9477_reg.h #define MIB_COUNTER_FLUSH_FREEZE BIT(24) BIT 1275 drivers/net/dsa/microchip/ksz9477_reg.h #define MIB_COUNTER_INDEX_M (BIT(8) - 1) BIT 1306 drivers/net/dsa/microchip/ksz9477_reg.h #define ACL_SRC BIT(1) BIT 1307 drivers/net/dsa/microchip/ksz9477_reg.h #define ACL_EQUAL BIT(0) BIT 1333 drivers/net/dsa/microchip/ksz9477_reg.h #define ACL_TCP_FLAG_ENABLE BIT(0) BIT 1355 drivers/net/dsa/microchip/ksz9477_reg.h #define ACL_VLAN_PRIO_REPLACE BIT(2) BIT 1370 drivers/net/dsa/microchip/ksz9477_reg.h #define ACL_CNT_M (BIT(11) - 1) BIT 1376 drivers/net/dsa/microchip/ksz9477_reg.h #define ACL_MSEC_UNIT BIT(6) BIT 1377 drivers/net/dsa/microchip/ksz9477_reg.h #define ACL_INTR_MODE BIT(5) BIT 1400 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_ACL_WRITE_DONE BIT(6) BIT 1401 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_ACL_READ_DONE BIT(5) BIT 1402 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_ACL_WRITE BIT(4) BIT 1410 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MIRROR_RX BIT(6) BIT 1411 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MIRROR_TX BIT(5) BIT 1412 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MIRROR_SNIFFER BIT(1) BIT 1416 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_HIGHEST_PRIO BIT(7) BIT 1417 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_OR_PRIO BIT(6) BIT 1418 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MAC_PRIO_ENABLE BIT(4) BIT 1419 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_VLAN_PRIO_ENABLE BIT(3) BIT 1420 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_802_1P_PRIO_ENABLE BIT(2) BIT 1421 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_DIFFSERV_PRIO_ENABLE BIT(1) BIT 1422 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_ACL_PRIO_ENABLE BIT(0) BIT 1426 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_USER_PRIO_CEILING BIT(7) BIT 1427 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_DROP_NON_VLAN BIT(4) BIT 1428 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_DROP_TAG BIT(3) BIT 1434 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_ACL_ENABLE BIT(2) BIT 1454 drivers/net/dsa/microchip/ksz9477_reg.h #define POLICE_DROP_ALL BIT(10) BIT 1461 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_BASED_POLICING BIT(7) BIT 1464 drivers/net/dsa/microchip/ksz9477_reg.h #define COLOR_MARK_ENABLE BIT(4) BIT 1465 drivers/net/dsa/microchip/ksz9477_reg.h #define COLOR_REMAP_ENABLE BIT(3) BIT 1466 drivers/net/dsa/microchip/ksz9477_reg.h #define POLICE_DROP_SRP BIT(2) BIT 1467 drivers/net/dsa/microchip/ksz9477_reg.h #define POLICE_COLOR_NOT_AWARE BIT(1) BIT 1468 drivers/net/dsa/microchip/ksz9477_reg.h #define POLICE_ENABLE BIT(0) BIT 1476 drivers/net/dsa/microchip/ksz9477_reg.h #define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1) BIT 1491 drivers/net/dsa/microchip/ksz9477_reg.h #define WRED_PM_CTRL_M (BIT(11) - 1) BIT 1506 drivers/net/dsa/microchip/ksz9477_reg.h #define WRED_RANDOM_DROP_ENABLE BIT(31) BIT 1507 drivers/net/dsa/microchip/ksz9477_reg.h #define WRED_PMON_FLUSH BIT(30) BIT 1508 drivers/net/dsa/microchip/ksz9477_reg.h #define WRED_DROP_GYR_DISABLE BIT(29) BIT 1509 drivers/net/dsa/microchip/ksz9477_reg.h #define WRED_DROP_YR_DISABLE BIT(28) BIT 1510 drivers/net/dsa/microchip/ksz9477_reg.h #define WRED_DROP_R_DISABLE BIT(27) BIT 1511 drivers/net/dsa/microchip/ksz9477_reg.h #define WRED_DROP_ALL BIT(26) BIT 1512 drivers/net/dsa/microchip/ksz9477_reg.h #define WRED_PMON_M (BIT(24) - 1) BIT 1520 drivers/net/dsa/microchip/ksz9477_reg.h #define MTI_PVID_REPLACE BIT(0) BIT 1536 drivers/net/dsa/microchip/ksz9477_reg.h #define MTI_TX_RATIO_M (BIT(7) - 1) BIT 1557 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1) BIT 1563 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_QM_WATER_MARK_M (BIT(11) - 1) BIT 1568 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_QM_TX_CNT_M (BIT(11) - 1) BIT 1578 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_VLAN_LOOKUP_VID_0 BIT(7) BIT 1579 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_INGRESS_FILTER BIT(6) BIT 1580 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_DISCARD_NON_VID BIT(5) BIT 1581 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_MAC_BASED_802_1X BIT(4) BIT 1582 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_SRC_ADDR_FILTER BIT(3) BIT 1588 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_TX_ENABLE BIT(2) BIT 1589 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_RX_ENABLE BIT(1) BIT 1590 drivers/net/dsa/microchip/ksz9477_reg.h #define PORT_LEARN_DISABLE BIT(0) BIT 1613 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_PORT_SYNC_INT BIT(15) BIT 1614 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_PORT_XDELAY_REQ_INT BIT(14) BIT 1615 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_PORT_PDELAY_RESP_INT BIT(13) BIT 1656 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1) BIT 1657 drivers/net/dsa/microchip/ksz9477_reg.h #define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1) BIT 263 drivers/net/dsa/microchip/ksz_common.c if (!ret && (member & BIT(port))) { BIT 317 drivers/net/dsa/microchip/ksz_common.c alu.port_forward |= BIT(port); BIT 350 drivers/net/dsa/microchip/ksz_common.c alu.port_forward &= ~BIT(port); BIT 321 drivers/net/dsa/microchip/ksz_common.h .max_register = BIT(regbits) - 1, \ BIT 643 drivers/net/dsa/mt7530.c mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port))); BIT 673 drivers/net/dsa/mt7530.c priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); BIT 738 drivers/net/dsa/mt7530.c u32 port_bitmap = BIT(MT7530_CPU_PORT); BIT 753 drivers/net/dsa/mt7530.c PCR_MATRIX(BIT(port))); BIT 754 drivers/net/dsa/mt7530.c priv->ports[i].pm |= PCR_MATRIX(BIT(port)); BIT 756 drivers/net/dsa/mt7530.c port_bitmap |= BIT(i); BIT 861 drivers/net/dsa/mt7530.c PCR_MATRIX(BIT(port))); BIT 862 drivers/net/dsa/mt7530.c priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); BIT 871 drivers/net/dsa/mt7530.c PCR_MATRIX(BIT(MT7530_CPU_PORT))); BIT 872 drivers/net/dsa/mt7530.c priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); BIT 883 drivers/net/dsa/mt7530.c u8 port_mask = BIT(port); BIT 899 drivers/net/dsa/mt7530.c u8 port_mask = BIT(port); BIT 928 drivers/net/dsa/mt7530.c if (_fdb.port_mask & BIT(port)) { BIT 1006 drivers/net/dsa/mt7530.c new_members = entry->old_members | BIT(entry->port) | BIT 1007 drivers/net/dsa/mt7530.c BIT(MT7530_CPU_PORT); BIT 1042 drivers/net/dsa/mt7530.c new_members = entry->old_members & ~BIT(entry->port); BIT 1055 drivers/net/dsa/mt7530.c if (new_members && new_members != BIT(MT7530_CPU_PORT)) { BIT 25 drivers/net/dsa/mt7530.h #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) BIT 28 drivers/net/dsa/mt7530.h #define RESET_MCM BIT(2) BIT 37 drivers/net/dsa/mt7530.h #define CPU_EN BIT(7) BIT 53 drivers/net/dsa/mt7530.h #define ATC_BUSY BIT(15) BIT 54 drivers/net/dsa/mt7530.h #define ATC_SRCH_END BIT(14) BIT 55 drivers/net/dsa/mt7530.h #define ATC_SRCH_HIT BIT(13) BIT 56 drivers/net/dsa/mt7530.h #define ATC_INVALID BIT(12) BIT 92 drivers/net/dsa/mt7530.h #define VTCR_BUSY BIT(31) BIT 93 drivers/net/dsa/mt7530.h #define VTCR_INVALID BIT(16) BIT 107 drivers/net/dsa/mt7530.h #define PORT_STAG BIT(31) BIT 109 drivers/net/dsa/mt7530.h #define IVL_MAC BIT(30) BIT 111 drivers/net/dsa/mt7530.h #define VTAG_EN BIT(28) BIT 115 drivers/net/dsa/mt7530.h #define VLAN_VALID BIT(0) BIT 172 drivers/net/dsa/mt7530.h #define SA_DIS BIT(4) BIT 176 drivers/net/dsa/mt7530.h #define PORT_SPEC_TAG BIT(5) BIT 203 drivers/net/dsa/mt7530.h #define PMCR_EXT_PHY BIT(17) BIT 204 drivers/net/dsa/mt7530.h #define PMCR_MAC_MODE BIT(16) BIT 205 drivers/net/dsa/mt7530.h #define PMCR_FORCE_MODE BIT(15) BIT 206 drivers/net/dsa/mt7530.h #define PMCR_TX_EN BIT(14) BIT 207 drivers/net/dsa/mt7530.h #define PMCR_RX_EN BIT(13) BIT 208 drivers/net/dsa/mt7530.h #define PMCR_BACKOFF_EN BIT(9) BIT 209 drivers/net/dsa/mt7530.h #define PMCR_BACKPR_EN BIT(8) BIT 210 drivers/net/dsa/mt7530.h #define PMCR_TX_FC_EN BIT(5) BIT 211 drivers/net/dsa/mt7530.h #define PMCR_RX_FC_EN BIT(4) BIT 212 drivers/net/dsa/mt7530.h #define PMCR_FORCE_SPEED_1000 BIT(3) BIT 213 drivers/net/dsa/mt7530.h #define PMCR_FORCE_SPEED_100 BIT(2) BIT 214 drivers/net/dsa/mt7530.h #define PMCR_FORCE_FDX BIT(1) BIT 215 drivers/net/dsa/mt7530.h #define PMCR_FORCE_LNK BIT(0) BIT 220 drivers/net/dsa/mt7530.h #define PMSR_EEE1G BIT(7) BIT 221 drivers/net/dsa/mt7530.h #define PMSR_EEE100M BIT(6) BIT 222 drivers/net/dsa/mt7530.h #define PMSR_RX_FC BIT(5) BIT 223 drivers/net/dsa/mt7530.h #define PMSR_TX_FC BIT(4) BIT 224 drivers/net/dsa/mt7530.h #define PMSR_SPEED_1000 BIT(3) BIT 225 drivers/net/dsa/mt7530.h #define PMSR_SPEED_100 BIT(2) BIT 228 drivers/net/dsa/mt7530.h #define PMSR_DPX BIT(1) BIT 229 drivers/net/dsa/mt7530.h #define PMSR_LINK BIT(0) BIT 234 drivers/net/dsa/mt7530.h #define CCR_MIB_ENABLE BIT(31) BIT 235 drivers/net/dsa/mt7530.h #define CCR_RX_OCT_CNT_GOOD BIT(7) BIT 236 drivers/net/dsa/mt7530.h #define CCR_RX_OCT_CNT_BAD BIT(6) BIT 237 drivers/net/dsa/mt7530.h #define CCR_TX_OCT_CNT_GOOD BIT(5) BIT 238 drivers/net/dsa/mt7530.h #define CCR_TX_OCT_CNT_BAD BIT(4) BIT 250 drivers/net/dsa/mt7530.h #define SYS_CTRL_PHY_RST BIT(2) BIT 251 drivers/net/dsa/mt7530.h #define SYS_CTRL_SW_RST BIT(1) BIT 252 drivers/net/dsa/mt7530.h #define SYS_CTRL_REG_RST BIT(0) BIT 256 drivers/net/dsa/mt7530.h #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) BIT 257 drivers/net/dsa/mt7530.h #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) BIT 258 drivers/net/dsa/mt7530.h #define HWTRAP_XTAL_40MHZ (BIT(10)) BIT 259 drivers/net/dsa/mt7530.h #define HWTRAP_XTAL_20MHZ (BIT(9)) BIT 263 drivers/net/dsa/mt7530.h #define MHWTRAP_PHY0_SEL BIT(20) BIT 264 drivers/net/dsa/mt7530.h #define MHWTRAP_MANUAL BIT(16) BIT 265 drivers/net/dsa/mt7530.h #define MHWTRAP_P5_MAC_SEL BIT(13) BIT 266 drivers/net/dsa/mt7530.h #define MHWTRAP_P6_DIS BIT(8) BIT 267 drivers/net/dsa/mt7530.h #define MHWTRAP_P5_RGMII_MODE BIT(7) BIT 268 drivers/net/dsa/mt7530.h #define MHWTRAP_P5_DIS BIT(6) BIT 269 drivers/net/dsa/mt7530.h #define MHWTRAP_PHY_ACCESS BIT(5) BIT 273 drivers/net/dsa/mt7530.h #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) BIT 285 drivers/net/dsa/mt7530.h #define RX_RST BIT(31) BIT 286 drivers/net/dsa/mt7530.h #define RXC_DQSISEL BIT(30) BIT 293 drivers/net/dsa/mt7530.h #define DQS1_GATE BIT(31) BIT 294 drivers/net/dsa/mt7530.h #define DQS0_GATE BIT(30) BIT 297 drivers/net/dsa/mt7530.h #define BSLIP_EN BIT(31) BIT 298 drivers/net/dsa/mt7530.h #define EDGE_CHK BIT(30) BIT 303 drivers/net/dsa/mt7530.h #define TRAIN_TXEN BIT(31) BIT 304 drivers/net/dsa/mt7530.h #define TXC_INV BIT(30) BIT 305 drivers/net/dsa/mt7530.h #define TX_RST BIT(28) BIT 315 drivers/net/dsa/mt7530.h #define CSR_RGMII_EDGE_ALIGN BIT(8) BIT 327 drivers/net/dsa/mt7530.h #define RG_SYSPLL_EN_NORMAL BIT(15) BIT 328 drivers/net/dsa/mt7530.h #define RG_SYSPLL_VODEN BIT(14) BIT 329 drivers/net/dsa/mt7530.h #define RG_SYSPLL_LF BIT(13) BIT 331 drivers/net/dsa/mt7530.h #define RG_SYSPLL_LVROD_EN BIT(10) BIT 334 drivers/net/dsa/mt7530.h #define RG_SYSPLL_FBKSEL BIT(4) BIT 335 drivers/net/dsa/mt7530.h #define RT_SYSPLL_EN_AFE_OLT BIT(0) BIT 338 drivers/net/dsa/mt7530.h #define RG_SYSPLL_DDSFBK_EN BIT(12) BIT 339 drivers/net/dsa/mt7530.h #define RG_SYSPLL_BIAS_EN BIT(11) BIT 340 drivers/net/dsa/mt7530.h #define RG_SYSPLL_BIAS_LPF_EN BIT(10) BIT 349 drivers/net/dsa/mt7530.h #define RG_LCDDS_PWDB BIT(15) BIT 350 drivers/net/dsa/mt7530.h #define RG_LCDDS_ISO_EN BIT(13) BIT 352 drivers/net/dsa/mt7530.h #define RG_LCDDS_PCW_NCPO_CHG BIT(3) BIT 363 drivers/net/dsa/mt7530.h #define RG_GSWPLL_EN_PRE BIT(11) BIT 364 drivers/net/dsa/mt7530.h #define RG_GSWPLL_FBKSEL BIT(10) BIT 365 drivers/net/dsa/mt7530.h #define RG_GSWPLL_BP BIT(9) BIT 366 drivers/net/dsa/mt7530.h #define RG_GSWPLL_BR BIT(8) BIT 374 drivers/net/dsa/mt7530.h #define REG_GSWCK_EN BIT(0) BIT 375 drivers/net/dsa/mt7530.h #define REG_TRGMIICK_EN BIT(1) BIT 143 drivers/net/dsa/mv88e6060.c BIT(dsa_to_port(priv->ds, p)->cpu_dp->index))); BIT 152 drivers/net/dsa/mv88e6060.c return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p)); BIT 17 drivers/net/dsa/mv88e6060.h #define PORT_STATUS_PAUSE_EN BIT(15) BIT 18 drivers/net/dsa/mv88e6060.h #define PORT_STATUS_MY_PAUSE BIT(14) BIT 20 drivers/net/dsa/mv88e6060.h #define PORT_STATUS_RESOLVED BIT(13) BIT 21 drivers/net/dsa/mv88e6060.h #define PORT_STATUS_LINK BIT(12) BIT 22 drivers/net/dsa/mv88e6060.h #define PORT_STATUS_PORTMODE BIT(11) BIT 23 drivers/net/dsa/mv88e6060.h #define PORT_STATUS_PHYMODE BIT(10) BIT 24 drivers/net/dsa/mv88e6060.h #define PORT_STATUS_DUPLEX BIT(9) BIT 25 drivers/net/dsa/mv88e6060.h #define PORT_STATUS_SPEED BIT(8) BIT 32 drivers/net/dsa/mv88e6060.h #define PORT_CONTROL_FORCE_FLOW_CTRL BIT(15) BIT 33 drivers/net/dsa/mv88e6060.h #define PORT_CONTROL_TRAILER BIT(14) BIT 34 drivers/net/dsa/mv88e6060.h #define PORT_CONTROL_HEADER BIT(11) BIT 35 drivers/net/dsa/mv88e6060.h #define PORT_CONTROL_INGRESS_MODE BIT(8) BIT 36 drivers/net/dsa/mv88e6060.h #define PORT_CONTROL_VLAN_TUNNEL BIT(7) BIT 46 drivers/net/dsa/mv88e6060.h #define PORT_ASSOC_VECTOR_MONITOR BIT(15) BIT 58 drivers/net/dsa/mv88e6060.h #define GLOBAL_STATUS_INIT_READY BIT(11) BIT 59 drivers/net/dsa/mv88e6060.h #define GLOBAL_STATUS_ATU_FULL BIT(3) BIT 60 drivers/net/dsa/mv88e6060.h #define GLOBAL_STATUS_ATU_DONE BIT(2) BIT 61 drivers/net/dsa/mv88e6060.h #define GLOBAL_STATUS_PHY_INT BIT(1) BIT 62 drivers/net/dsa/mv88e6060.h #define GLOBAL_STATUS_EEINT BIT(0) BIT 64 drivers/net/dsa/mv88e6060.h #define GLOBAL_MAC_01_DIFF_ADDR BIT(8) BIT 68 drivers/net/dsa/mv88e6060.h #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) BIT 69 drivers/net/dsa/mv88e6060.h #define GLOBAL_CONTROL_MAX_FRAME_1536 BIT(10) BIT 70 drivers/net/dsa/mv88e6060.h #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) BIT 71 drivers/net/dsa/mv88e6060.h #define GLOBAL_CONTROL_CTRMODE BIT(8) BIT 72 drivers/net/dsa/mv88e6060.h #define GLOBAL_CONTROL_ATU_FULL_EN BIT(3) BIT 73 drivers/net/dsa/mv88e6060.h #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) BIT 74 drivers/net/dsa/mv88e6060.h #define GLOBAL_CONTROL_PHYINT_EN BIT(1) BIT 75 drivers/net/dsa/mv88e6060.h #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) BIT 77 drivers/net/dsa/mv88e6060.h #define GLOBAL_ATU_CONTROL_SWRESET BIT(15) BIT 78 drivers/net/dsa/mv88e6060.h #define GLOBAL_ATU_CONTROL_LEARNDIS BIT(14) BIT 86 drivers/net/dsa/mv88e6060.h #define GLOBAL_ATU_OP_BUSY BIT(15) BIT 110 drivers/net/dsa/mv88e6xxx/chip.c return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), BIT 111 drivers/net/dsa/mv88e6xxx/chip.c val ? BIT(bit) : 0x0000); BIT 1088 drivers/net/dsa/mv88e6xxx/chip.c pvlan |= BIT(i); BIT 1098 drivers/net/dsa/mv88e6xxx/chip.c output_ports &= ~BIT(port); BIT 1516 drivers/net/dsa/mv88e6xxx/chip.c entry.portvec &= ~BIT(port); BIT 1520 drivers/net/dsa/mv88e6xxx/chip.c entry.portvec |= BIT(port); BIT 1969 drivers/net/dsa/mv88e6xxx/chip.c if (addr.trunk || (addr.portvec & BIT(port)) == 0) BIT 4540 drivers/net/dsa/mv88e6xxx/chip.c .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), BIT 591 drivers/net/dsa/mv88e6xxx/chip.h #define STATS_TYPE_PORT BIT(0) BIT 592 drivers/net/dsa/mv88e6xxx/chip.h #define STATS_TYPE_BANK0 BIT(1) BIT 593 drivers/net/dsa/mv88e6xxx/chip.h #define STATS_TYPE_BANK1 BIT(2) BIT 629 drivers/net/dsa/mv88e6xxx/chip.h return (chip->info->invalid_port_mask & BIT(port)) != 0; BIT 82 drivers/net/dsa/mv88e6xxx/global1.h #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6) BIT 83 drivers/net/dsa/mv88e6xxx/global1.h #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5) BIT 125 drivers/net/dsa/mv88e6xxx/global1.h #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION BIT(7) BIT 126 drivers/net/dsa/mv88e6xxx/global1.h #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION BIT(6) BIT 127 drivers/net/dsa/mv88e6xxx/global1.h #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION BIT(5) BIT 128 drivers/net/dsa/mv88e6xxx/global1.h #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4) BIT 146 drivers/net/dsa/mv88e6xxx/global2.c const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; BIT 155 drivers/net/dsa/mv88e6xxx/global2.c const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; BIT 281 drivers/net/dsa/mv88e6xxx/global2.h #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2) BIT 122 drivers/net/dsa/mv88e6xxx/hwtstamp.c if (!(BIT(config->rx_filter) & ptp_ops->rx_filters)) { BIT 36 drivers/net/dsa/mv88e6xxx/hwtstamp.h #define MV88E6165_PTP_CFG_DISABLE_TS_OVERWRITE BIT(1) BIT 37 drivers/net/dsa/mv88e6xxx/hwtstamp.h #define MV88E6165_PTP_CFG_DISABLE_PTP BIT(0) BIT 98 drivers/net/dsa/mv88e6xxx/ptp.h #define MV88E6XXX_PTP_GC_CONFIG_DIS_OVERWRITE BIT(1) BIT 99 drivers/net/dsa/mv88e6xxx/ptp.h #define MV88E6XXX_PTP_GC_CONFIG_DIS_TS BIT(0) BIT 19 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14) BIT 20 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13) BIT 21 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6352_SERDES_INT_PAGE_RX BIT(12) BIT 22 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11) BIT 23 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10) BIT 24 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9) BIT 25 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8) BIT 26 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7) BIT 27 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4) BIT 44 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_PCS_CONTROL_1_RESET BIT(15) BIT 45 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_PCS_CONTROL_1_LOOPBACK BIT(14) BIT 46 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_PCS_CONTROL_1_SPEED BIT(13) BIT 47 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_PCS_CONTROL_1_PDOWN BIT(11) BIT 51 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_CONTROL_RESET BIT(15) BIT 52 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_CONTROL_LOOPBACK BIT(14) BIT 53 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_CONTROL_PDOWN BIT(11) BIT 55 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_STATUS_AN_DONE BIT(5) BIT 56 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_STATUS_REMOTE_FAULT BIT(4) BIT 57 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_STATUS_LINK BIT(2) BIT 59 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14) BIT 60 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13) BIT 61 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_INT_PAGE_RX BIT(12) BIT 62 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_INT_AN_COMPLETE BIT(11) BIT 63 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_INT_LINK_DOWN BIT(10) BIT 64 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_INT_LINK_UP BIT(9) BIT 65 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_INT_SYMBOL_ERROR BIT(8) BIT 66 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_INT_FALSE_CARRIER BIT(7) BIT 73 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL BIT(13) BIT 74 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11) BIT 75 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10) BIT 67 drivers/net/dsa/mv88e6xxx/smi.c if (!!(data & BIT(bit)) == !!val) BIT 596 drivers/net/dsa/qca8k.c external_mdio_mask |= BIT(reg); BIT 598 drivers/net/dsa/qca8k.c internal_mdio_mask |= BIT(reg); BIT 702 drivers/net/dsa/qca8k.c BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | BIT 703 drivers/net/dsa/qca8k.c BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | BIT 704 drivers/net/dsa/qca8k.c BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | BIT 705 drivers/net/dsa/qca8k.c BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); BIT 721 drivers/net/dsa/qca8k.c BIT(QCA8K_CPU_PORT)); BIT 887 drivers/net/dsa/qca8k.c int port_mask = BIT(QCA8K_CPU_PORT); BIT 898 drivers/net/dsa/qca8k.c BIT(port)); BIT 900 drivers/net/dsa/qca8k.c port_mask |= BIT(i); BIT 923 drivers/net/dsa/qca8k.c BIT(port)); BIT 930 drivers/net/dsa/qca8k.c QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT)); BIT 976 drivers/net/dsa/qca8k.c u16 port_mask = BIT(port); BIT 986 drivers/net/dsa/qca8k.c u16 port_mask = BIT(port); BIT 31 drivers/net/dsa/qca8k.h #define QCA8K_PORT_PAD_RGMII_EN BIT(26) BIT 37 drivers/net/dsa/qca8k.h #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) BIT 38 drivers/net/dsa/qca8k.h #define QCA8K_PORT_PAD_SGMII_EN BIT(7) BIT 40 drivers/net/dsa/qca8k.h #define QCA8K_MODULE_EN_MIB BIT(0) BIT 42 drivers/net/dsa/qca8k.h #define QCA8K_MIB_FLUSH BIT(24) BIT 43 drivers/net/dsa/qca8k.h #define QCA8K_MIB_CPU_KEEP BIT(20) BIT 44 drivers/net/dsa/qca8k.h #define QCA8K_MIB_BUSY BIT(17) BIT 46 drivers/net/dsa/qca8k.h #define QCA8K_MDIO_MASTER_BUSY BIT(31) BIT 47 drivers/net/dsa/qca8k.h #define QCA8K_MDIO_MASTER_EN BIT(30) BIT 48 drivers/net/dsa/qca8k.h #define QCA8K_MDIO_MASTER_READ BIT(27) BIT 50 drivers/net/dsa/qca8k.h #define QCA8K_MDIO_MASTER_SUP_PRE BIT(26) BIT 64 drivers/net/dsa/qca8k.h #define QCA8K_PORT_STATUS_TXMAC BIT(2) BIT 65 drivers/net/dsa/qca8k.h #define QCA8K_PORT_STATUS_RXMAC BIT(3) BIT 66 drivers/net/dsa/qca8k.h #define QCA8K_PORT_STATUS_TXFLOW BIT(4) BIT 67 drivers/net/dsa/qca8k.h #define QCA8K_PORT_STATUS_RXFLOW BIT(5) BIT 68 drivers/net/dsa/qca8k.h #define QCA8K_PORT_STATUS_DUPLEX BIT(6) BIT 69 drivers/net/dsa/qca8k.h #define QCA8K_PORT_STATUS_LINK_UP BIT(8) BIT 70 drivers/net/dsa/qca8k.h #define QCA8K_PORT_STATUS_LINK_AUTO BIT(9) BIT 71 drivers/net/dsa/qca8k.h #define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10) BIT 108 drivers/net/dsa/qca8k.h #define QCA8K_ATU_FUNC_BUSY BIT(31) BIT 109 drivers/net/dsa/qca8k.h #define QCA8K_ATU_FUNC_PORT_EN BIT(14) BIT 110 drivers/net/dsa/qca8k.h #define QCA8K_ATU_FUNC_MULTI_EN BIT(13) BIT 111 drivers/net/dsa/qca8k.h #define QCA8K_ATU_FUNC_FULL BIT(12) BIT 115 drivers/net/dsa/qca8k.h #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10) BIT 130 drivers/net/dsa/qca8k.h #define QCA8K_PORT_LOOKUP_LEARN BIT(20) BIT 280 drivers/net/dsa/rtl8366.c mask = BIT(port) | BIT(smi->cpu_port); BIT 391 drivers/net/dsa/rtl8366.c member |= BIT(port); BIT 394 drivers/net/dsa/rtl8366.c untag |= BIT(port); BIT 32 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0) BIT 39 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_SGCR_EN_VLAN BIT(13) BIT 40 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14) BIT 49 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0) BIT 53 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMC0_SPI BIT(0) BIT 54 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1) BIT 55 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMC0_PROBE BIT(2) BIT 56 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMC0_DIS_BISR BIT(3) BIT 57 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMC0_ADCTEST BIT(4) BIT 58 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMC0_SRAM_DIAG BIT(5) BIT 59 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMC0_EN_SCAN BIT(6) BIT 74 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMCR_MIRROR_RX BIT(8) BIT 75 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMCR_MIRROR_TX BIT(9) BIT 76 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMCR_MIRROR_SPC BIT(10) BIT 77 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMCR_MIRROR_ISO BIT(11) BIT 88 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PAACR_FULL_DUPLEX BIT(2) BIT 89 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PAACR_LINK_UP BIT(4) BIT 90 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PAACR_TX_PAUSE BIT(5) BIT 91 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PAACR_RX_PAUSE BIT(6) BIT 92 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PAACR_AN BIT(7) BIT 113 drivers/net/dsa/rtl8366rb.c #define RTL8368RB_CPU_INSTAG BIT(15) BIT 120 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0) BIT 121 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1) BIT 130 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PHY_CTRL_READ BIT(0) BIT 133 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PHY_INT_BUSY BIT(0) BIT 134 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PHY_EXT_BUSY BIT(4) BIT 186 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0) BIT 187 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1) BIT 188 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p)) BIT 189 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11) BIT 220 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */ BIT 221 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */ BIT 222 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */ BIT 223 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */ BIT 224 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */ BIT 226 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PORT_CPU BIT(5) /* CPU port */ BIT 267 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_IB_PREIFG BIT(14) BIT 274 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_EB_PREIFG BIT(9) BIT 281 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_QOS BIT(15) BIT 287 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_INTERRUPT_POLARITY BIT(0) BIT 288 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_P4_RGMII_LED BIT(2) BIT 291 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8) BIT 292 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9) BIT 293 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_INTERRUPT_P4_FIBER BIT(12) BIT 294 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_INTERRUPT_P4_UTP BIT(13) BIT 311 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_GREEN_FEATURE_TX BIT(0) BIT 312 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_GREEN_FEATURE_RX BIT(2) BIT 401 drivers/net/dsa/rtl8366rb.c val = BIT(line) | BIT(line + 6); BIT 403 drivers/net/dsa/rtl8366rb.c val = BIT(line); BIT 450 drivers/net/dsa/rtl8366rb.c stat &= ~BIT(line); BIT 856 drivers/net/dsa/rtl8366rb.c RTL8368RB_CPU_INSTAG | BIT(smi->cpu_port)); BIT 862 drivers/net/dsa/rtl8366rb.c BIT(smi->cpu_port), BIT 999 drivers/net/dsa/rtl8366rb.c BIT(port), BIT(port)); BIT 1010 drivers/net/dsa/rtl8366rb.c ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), BIT 1070 drivers/net/dsa/rtl8366rb.c ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), BIT 1086 drivers/net/dsa/rtl8366rb.c ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), BIT 1087 drivers/net/dsa/rtl8366rb.c BIT(port)); BIT 484 drivers/net/dsa/sja1105/sja1105_dynamic_config.c #define OP_READ BIT(0) BIT 485 drivers/net/dsa/sja1105/sja1105_dynamic_config.c #define OP_WRITE BIT(1) BIT 486 drivers/net/dsa/sja1105/sja1105_dynamic_config.c #define OP_DEL BIT(2) BIT 487 drivers/net/dsa/sja1105/sja1105_dynamic_config.c #define OP_SEARCH BIT(3) BIT 43 drivers/net/dsa/sja1105/sja1105_main.c l2_fwd[from].bc_domain |= BIT(to); BIT 44 drivers/net/dsa/sja1105/sja1105_main.c l2_fwd[from].reach_port |= BIT(to); BIT 45 drivers/net/dsa/sja1105/sja1105_main.c l2_fwd[from].fl_domain |= BIT(to); BIT 47 drivers/net/dsa/sja1105/sja1105_main.c l2_fwd[from].bc_domain &= ~BIT(to); BIT 48 drivers/net/dsa/sja1105/sja1105_main.c l2_fwd[from].reach_port &= ~BIT(to); BIT 49 drivers/net/dsa/sja1105/sja1105_main.c l2_fwd[from].fl_domain &= ~BIT(to); BIT 297 drivers/net/dsa/sja1105/sja1105_main.c pvid.vmemb_port |= BIT(i); BIT 298 drivers/net/dsa/sja1105/sja1105_main.c pvid.vlan_bc |= BIT(i); BIT 299 drivers/net/dsa/sja1105/sja1105_main.c pvid.tag_port &= ~BIT(i); BIT 827 drivers/net/dsa/sja1105/sja1105_main.c sja1105_inhibit_tx(ds->priv, BIT(port), true); BIT 835 drivers/net/dsa/sja1105/sja1105_main.c sja1105_inhibit_tx(ds->priv, BIT(port), false); BIT 891 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup[i].destports & BIT(port)) BIT 1009 drivers/net/dsa/sja1105/sja1105_main.c if (l2_lookup.destports & BIT(port)) BIT 1011 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.destports |= BIT(port); BIT 1019 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.destports = BIT(port); BIT 1071 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.destports &= ~BIT(port); BIT 1100 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.mask_iotag = BIT(0); BIT 1105 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.destports = BIT(port); BIT 1113 drivers/net/dsa/sja1105/sja1105_main.c if (l2_lookup.destports & BIT(port)) BIT 1118 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.destports |= BIT(port); BIT 1163 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.mask_iotag = BIT(0); BIT 1168 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.destports = BIT(port); BIT 1175 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.destports &= ~BIT(port); BIT 1252 drivers/net/dsa/sja1105/sja1105_main.c if (!(l2_lookup.destports & BIT(port))) BIT 1482 drivers/net/dsa/sja1105/sja1105_main.c vlan[match].vlan_bc |= BIT(port); BIT 1483 drivers/net/dsa/sja1105/sja1105_main.c vlan[match].vmemb_port |= BIT(port); BIT 1485 drivers/net/dsa/sja1105/sja1105_main.c vlan[match].vlan_bc &= ~BIT(port); BIT 1486 drivers/net/dsa/sja1105/sja1105_main.c vlan[match].vmemb_port &= ~BIT(port); BIT 1492 drivers/net/dsa/sja1105/sja1105_main.c vlan[match].tag_port &= ~BIT(port); BIT 1494 drivers/net/dsa/sja1105/sja1105_main.c vlan[match].tag_port |= BIT(port); BIT 1769 drivers/net/dsa/sja1105/sja1105_main.c mgmt_route.destports = BIT(port); BIT 10 drivers/net/dsa/sja1105/sja1105_tas.c #define SJA1105_TAS_MAX_DELTA BIT(19) BIT 223 drivers/net/dsa/sja1105/sja1105_tas.c schedule[k].destports = BIT(port); BIT 68 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31) BIT 69 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_PORT_RST BIT(29) BIT 70 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_TX_EN BIT(28) BIT 71 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27) BIT 74 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_FDX BIT(18) BIT 75 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17) BIT 76 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_RX_EN BIT(16) BIT 77 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15) BIT 78 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14) BIT 79 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */ BIT 84 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5) BIT 85 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4) BIT 111 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17) BIT 112 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16) BIT 116 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ADVPORTM_IFG_PPM BIT(7) BIT 117 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6) BIT 118 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ADVPORTM_EXT_PORT BIT(5) BIT 119 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ADVPORTM_INV_GTX BIT(4) BIT 120 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ADVPORTM_ENA_GTX BIT(3) BIT 121 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ADVPORTM_DDR_MODE BIT(2) BIT 122 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1) BIT 123 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0) BIT 126 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6) BIT 127 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4) BIT 128 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3) BIT 129 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2) BIT 130 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1) BIT 131 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0) BIT 133 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31) BIT 136 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0) BIT 167 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MACACCESS_CPU_COPY BIT(14) BIT 168 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MACACCESS_FWD_KILL BIT(13) BIT 169 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12) BIT 170 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MACACCESS_AGED_FLAG BIT(11) BIT 171 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MACACCESS_VALID BIT(10) BIT 172 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MACACCESS_LOCKED BIT(9) BIT 184 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30) BIT 185 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29) BIT 186 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28) BIT 230 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31) BIT 232 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7) BIT 233 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6) BIT 234 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3) BIT 235 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2) BIT 236 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1) BIT 237 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ICPU_CTRL_SRST BIT(0) BIT 248 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_GLORESET_STROBE BIT(4) BIT 249 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_GLORESET_ICPU_LOCK BIT(3) BIT 250 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_GLORESET_MEM_LOCK BIT(2) BIT 251 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_GLORESET_PHY_RESET BIT(1) BIT 252 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_GLORESET_MASTER_RESET BIT(0) BIT 495 drivers/net/dsa/vitesse-vsc73xx-core.c cmd = BIT(26) | (phy << 21) | (regnum << 16); BIT 503 drivers/net/dsa/vitesse-vsc73xx-core.c if (val & BIT(16)) { BIT 529 drivers/net/dsa/vitesse-vsc73xx-core.c if (regnum == 0 && (val & BIT(15))) { BIT 756 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_SBACKWDROP, BIT(port), 0); BIT 804 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_ARBDISC, BIT(port), BIT(port)); BIT 809 drivers/net/dsa/vitesse-vsc73xx-core.c while (!(val & BIT(port))) { BIT 827 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_ARBDISC, BIT(port), 0); BIT 831 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_SBACKWDROP, BIT(port), BIT(port)); BIT 835 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_RECVMASK, BIT(port), 0); BIT 884 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_RECVMASK, BIT(port), BIT(port)); BIT 1056 drivers/net/dsa/vitesse-vsc73xx-core.c return !!(val & BIT(offset)); BIT 1063 drivers/net/dsa/vitesse-vsc73xx-core.c u32 tmp = val ? BIT(offset) : 0; BIT 1066 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_GPIO, BIT(offset), tmp); BIT 1073 drivers/net/dsa/vitesse-vsc73xx-core.c u32 tmp = val ? BIT(offset) : 0; BIT 1076 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_GPIO, BIT(offset + 4) | BIT(offset), BIT 1077 drivers/net/dsa/vitesse-vsc73xx-core.c BIT(offset + 4) | tmp); BIT 1086 drivers/net/dsa/vitesse-vsc73xx-core.c VSC73XX_GPIO, BIT(offset + 4), BIT 1102 drivers/net/dsa/vitesse-vsc73xx-core.c return !(val & BIT(offset + 4)); BIT 75 drivers/net/ethernet/8390/ax88796.c #define AX_GPOC_PPDSET BIT(6) BIT 320 drivers/net/ethernet/8390/ax88796.c #define AX_MEMR_MDC BIT(0) BIT 321 drivers/net/ethernet/8390/ax88796.c #define AX_MEMR_MDIR BIT(1) BIT 322 drivers/net/ethernet/8390/ax88796.c #define AX_MEMR_MDI BIT(2) BIT 323 drivers/net/ethernet/8390/ax88796.c #define AX_MEMR_MDO BIT(3) BIT 324 drivers/net/ethernet/8390/ax88796.c #define AX_MEMR_EECS BIT(4) BIT 325 drivers/net/ethernet/8390/ax88796.c #define AX_MEMR_EEI BIT(5) BIT 326 drivers/net/ethernet/8390/ax88796.c #define AX_MEMR_EEO BIT(6) BIT 327 drivers/net/ethernet/8390/ax88796.c #define AX_MEMR_EECLK BIT(7) BIT 32 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_DESC_CTL_GEN_SOP BIT(8) BIT 33 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_DESC_CTL_GEN_EOP BIT(9) BIT 34 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_DESC_CTL_PARK_READS BIT(10) BIT 35 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_DESC_CTL_PARK_WRITES BIT(11) BIT 36 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_DESC_CTL_END_ON_EOP BIT(12) BIT 37 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_DESC_CTL_END_ON_LEN BIT(13) BIT 38 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14) BIT 39 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15) BIT 41 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_DESC_CTL_EARLY_DONE BIT(24) BIT 45 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_DESC_CTL_GO BIT(31) BIT 92 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_STAT_BUSY BIT(0) BIT 93 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY BIT(1) BIT 94 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_STAT_DESC_BUF_FULL BIT(2) BIT 95 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY BIT(3) BIT 96 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_STAT_RESP_BUF_FULL BIT(4) BIT 97 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_STAT_STOPPED BIT(5) BIT 98 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_STAT_RESETTING BIT(6) BIT 99 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_STAT_STOPPED_ON_ERR BIT(7) BIT 100 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY BIT(8) BIT 101 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_STAT_IRQ BIT(9) BIT 118 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_CTL_STOP BIT(0) BIT 119 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_CTL_RESET BIT(1) BIT 120 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_CTL_STOP_ON_ERR BIT(2) BIT 121 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_CTL_STOP_ON_EARLY BIT(3) BIT 122 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_CTL_GLOBAL_INTR BIT(4) BIT 123 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_CSR_CTL_STOP_DESCS BIT(5) BIT 144 drivers/net/ethernet/altera/altera_msgdmahw.h #define MSGDMA_RESP_EARLY_TERM BIT(8) BIT 44 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STATUS_ERR BIT(0) BIT 45 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STATUS_LENGTH_ERR BIT(1) BIT 46 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STATUS_CRC_ERR BIT(2) BIT 47 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STATUS_TRUNC_ERR BIT(3) BIT 48 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STATUS_PHY_ERR BIT(4) BIT 49 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STATUS_COLL_ERR BIT(5) BIT 50 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STATUS_EOP BIT(7) BIT 52 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CONTROL_EOP BIT(0) BIT 53 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CONTROL_RD_FIXED BIT(1) BIT 54 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CONTROL_WR_FIXED BIT(2) BIT 58 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CONTROL_HW_OWNED BIT(7) BIT 97 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STSREG_ERR BIT(0) /* Error */ BIT 98 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STSREG_EOP BIT(1) /* EOP */ BIT 99 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STSREG_DESCRIP BIT(2) /* Descriptor completed */ BIT 100 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STSREG_CHAIN BIT(3) /* Chain completed */ BIT 101 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_STSREG_BUSY BIT(4) /* Controller busy */ BIT 103 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_IOE BIT(0) /* Interrupt on error */ BIT 104 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_IOEOP BIT(1) /* Interrupt on EOP */ BIT 105 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_IDESCRIP BIT(2) /* Interrupt after every descriptor */ BIT 106 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_ILASTD BIT(3) /* Interrupt after last descriptor */ BIT 107 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_INTEN BIT(4) /* Global Interrupt enable */ BIT 108 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_START BIT(5) /* starts descriptor processing */ BIT 109 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_STOPERR BIT(6) /* stop on dma error */ BIT 110 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_INTMAX BIT(7) /* Interrupt on max descriptors */ BIT 111 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_RESET BIT(16)/* Software reset */ BIT 112 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_COBHW BIT(17)/* Clears owned by hardware */ BIT 113 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_POLL BIT(18)/* enables descriptor polling mode */ BIT 114 drivers/net/ethernet/altera/altera_sgdmahw.h #define SGDMA_CTRLREG_CLRINT BIT(31)/* Clears interrupt */ BIT 56 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_TX_ENA BIT(0) BIT 57 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_RX_ENA BIT(1) BIT 58 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_XON_GEN BIT(2) BIT 59 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_ETH_SPEED BIT(3) BIT 60 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_PROMIS_EN BIT(4) BIT 61 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_PAD_EN BIT(5) BIT 62 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_CRC_FWD BIT(6) BIT 63 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_PAUSE_FWD BIT(7) BIT 64 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_PAUSE_IGNORE BIT(8) BIT 65 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_TX_ADDR_INS BIT(9) BIT 66 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_HD_ENA BIT(10) BIT 67 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_EXCESS_COL BIT(11) BIT 68 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_LATE_COL BIT(12) BIT 69 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_SW_RESET BIT(13) BIT 70 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_MHASH_SEL BIT(14) BIT 71 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_LOOP_ENA BIT(15) BIT 73 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_MAGIC_ENA BIT(19) BIT 74 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_SLEEP BIT(20) BIT 75 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_WAKEUP BIT(21) BIT 76 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_XOFF_GEN BIT(22) BIT 77 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_CNTL_FRM_ENA BIT(23) BIT 78 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_NO_LGTH_CHECK BIT(24) BIT 79 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_ENA_10 BIT(25) BIT 80 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_RX_ERR_DISC BIT(26) BIT 81 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27) BIT 82 drivers/net/ethernet/altera/altera_tse.h #define MAC_CMDCFG_CNT_RESET BIT(31) BIT 364 drivers/net/ethernet/altera/altera_tse.h #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17) BIT 365 drivers/net/ethernet/altera/altera_tse.h #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18) BIT 366 drivers/net/ethernet/altera/altera_tse.h #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25) BIT 713 drivers/net/ethernet/amazon/ena/ena_admin_defs.h ENA_ADMIN_RSS_L2_DA = BIT(0), BIT 715 drivers/net/ethernet/amazon/ena/ena_admin_defs.h ENA_ADMIN_RSS_L2_SA = BIT(1), BIT 717 drivers/net/ethernet/amazon/ena/ena_admin_defs.h ENA_ADMIN_RSS_L3_DA = BIT(2), BIT 719 drivers/net/ethernet/amazon/ena/ena_admin_defs.h ENA_ADMIN_RSS_L3_SA = BIT(3), BIT 721 drivers/net/ethernet/amazon/ena/ena_admin_defs.h ENA_ADMIN_RSS_L4_DP = BIT(4), BIT 723 drivers/net/ethernet/amazon/ena/ena_admin_defs.h ENA_ADMIN_RSS_L4_SP = BIT(5), BIT 1033 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) BIT 1035 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) BIT 1037 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) BIT 1045 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) BIT 1053 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) BIT 1057 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) BIT 1064 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) BIT 1066 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) BIT 1069 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) BIT 1071 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) BIT 1073 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) BIT 1075 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) BIT 1077 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) BIT 1079 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) BIT 1081 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) BIT 1083 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) BIT 1084 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) BIT 1086 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) BIT 1088 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) BIT 1090 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) BIT 1098 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) BIT 1100 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) BIT 1102 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) BIT 1104 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) BIT 1120 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) BIT 1123 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) BIT 1126 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) BIT 1920 drivers/net/ethernet/amazon/ena/ena_com.c if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { BIT 2246 drivers/net/ethernet/amazon/ena/ena_com.c if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) { BIT 307 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23) BIT 309 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) BIT 311 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) BIT 313 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) BIT 315 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) BIT 318 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) BIT 320 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) BIT 324 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13) BIT 326 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14) BIT 328 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) BIT 330 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) BIT 340 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14) BIT 344 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) BIT 346 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21) BIT 348 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23) BIT 350 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24) BIT 352 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26) BIT 354 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27) BIT 356 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28) BIT 367 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) BIT 370 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) BIT 372 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) BIT 374 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) BIT 376 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4) BIT 385 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13) BIT 387 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14) BIT 389 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) BIT 391 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16) BIT 393 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) BIT 395 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25) BIT 397 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26) BIT 399 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27) BIT 401 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30) BIT 408 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30) BIT 413 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31) BIT 2662 drivers/net/ethernet/amazon/ena/ena_netdev.c aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | BIT 2663 drivers/net/ethernet/amazon/ena/ena_netdev.c BIT(ENA_ADMIN_FATAL_ERROR) | BIT 2664 drivers/net/ethernet/amazon/ena/ena_netdev.c BIT(ENA_ADMIN_WARNING) | BIT 2665 drivers/net/ethernet/amazon/ena/ena_netdev.c BIT(ENA_ADMIN_NOTIFICATION) | BIT 2666 drivers/net/ethernet/amazon/ena/ena_netdev.c BIT(ENA_ADMIN_KEEP_ALIVE); BIT 2676 drivers/net/ethernet/amazon/ena/ena_netdev.c *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); BIT 3150 drivers/net/ethernet/amazon/ena/ena_netdev.c if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { BIT 3201 drivers/net/ethernet/amazon/ena/ena_netdev.c has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR); BIT 3365 drivers/net/ethernet/amazon/ena/ena_netdev.c if (ctx->ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { BIT 80 drivers/net/ethernet/amazon/ena/ena_netdev.h #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR)) BIT 143 drivers/net/ethernet/amazon/ena/ena_netdev.h #define ENA_MMIO_DISABLE_REG_READ BIT(0) BIT 487 drivers/net/ethernet/amd/pcnet32.c unsigned int entries = BIT(size); BIT 549 drivers/net/ethernet/amd/pcnet32.c unsigned int entries = BIT(size); BIT 1331 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12) BIT 1335 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define MDIO_VEND2_CTRL1_AN_RESTART BIT(9) BIT 1339 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define MDIO_VEND2_CTRL1_SS6 BIT(6) BIT 1343 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define MDIO_VEND2_CTRL1_SS13 BIT(13) BIT 1347 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGBE_AN_CL73_INT_CMPLT BIT(0) BIT 1348 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGBE_AN_CL73_INC_LINK BIT(1) BIT 1349 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGBE_AN_CL73_PG_RCV BIT(2) BIT 1353 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGBE_XNP_ACK_PROCESSED BIT(12) BIT 1354 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGBE_XNP_MP_FORMATTED BIT(13) BIT 1355 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGBE_XNP_NP_EXCHANGE BIT(15) BIT 1357 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGBE_KR_TRAINING_START BIT(0) BIT 1358 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGBE_KR_TRAINING_ENABLE BIT(1) BIT 1360 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGBE_PCS_CL37_BP BIT(12) BIT 1362 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGBE_AN_CL37_INT_CMPLT BIT(0) BIT 132 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c #define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX) BIT 133 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c #define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX) BIT 134 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c #define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX) BIT 135 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c #define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX) BIT 141 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c #define XGBE_I2C_READ BIT(8) BIT 142 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c #define XGBE_I2C_STOP BIT(9) BIT 127 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_PHY_PORT_SPEED_100 BIT(0) BIT 128 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_PHY_PORT_SPEED_1000 BIT(1) BIT 129 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_PHY_PORT_SPEED_2500 BIT(2) BIT 130 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_PHY_PORT_SPEED_10000 BIT(3) BIT 143 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_GPIO_NO_TX_FAULT BIT(0) BIT 144 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_GPIO_NO_RATE_SELECT BIT(1) BIT 145 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) BIT 146 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_GPIO_NO_RX_LOS BIT(3) BIT 221 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) BIT 222 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) BIT 223 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) BIT 224 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) BIT 227 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) BIT 228 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) BIT 229 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) BIT 230 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) BIT 233 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) BIT 234 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) BIT 258 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) BIT 259 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) BIT 262 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) BIT 294 drivers/net/ethernet/amd/xgbe/xgbe.h #define XGBE_SGMII_AN_LINK_STATUS BIT(1) BIT 295 drivers/net/ethernet/amd/xgbe/xgbe.h #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) BIT 298 drivers/net/ethernet/amd/xgbe/xgbe.h #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) BIT 20 drivers/net/ethernet/apm/xgene-v2/enet.h #define DEVM_ARAUX_COH BIT(19) BIT 21 drivers/net/ethernet/apm/xgene-v2/enet.h #define DEVM_AWAUX_COH BIT(3) BIT 32 drivers/net/ethernet/apm/xgene-v2/mac.h #define SOFT_RESET BIT(31) BIT 33 drivers/net/ethernet/apm/xgene-v2/mac.h #define TX_EN BIT(0) BIT 34 drivers/net/ethernet/apm/xgene-v2/mac.h #define RX_EN BIT(2) BIT 35 drivers/net/ethernet/apm/xgene-v2/mac.h #define PAD_CRC BIT(2) BIT 36 drivers/net/ethernet/apm/xgene-v2/mac.h #define CRC_EN BIT(1) BIT 37 drivers/net/ethernet/apm/xgene-v2/mac.h #define FULL_DUPLEX BIT(0) BIT 56 drivers/net/ethernet/apm/xgene-v2/mac.h #define MII_MGMT_BUSY BIT(0) BIT 57 drivers/net/ethernet/apm/xgene-v2/mac.h #define MII_READ_CYCLE BIT(0) BIT 58 drivers/net/ethernet/apm/xgene-v2/mac.h #define CFG_WAITASYNCRD_EN BIT(16) BIT 49 drivers/net/ethernet/apm/xgene-v2/ring.h #define TX_PKT_SENT BIT(0) BIT 50 drivers/net/ethernet/apm/xgene-v2/ring.h #define TX_BUS_ERROR BIT(3) BIT 51 drivers/net/ethernet/apm/xgene-v2/ring.h #define RX_PKT_RCVD BIT(4) BIT 52 drivers/net/ethernet/apm/xgene-v2/ring.h #define RX_BUS_ERROR BIT(7) BIT 53 drivers/net/ethernet/apm/xgene-v2/ring.h #define RXSTATUS_RXPKTRCVD BIT(0) BIT 155 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c data |= BIT(31 - xgene_enet_ring_bufnum(ring->id)); BIT 171 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id)); BIT 739 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c data = BIT(xgene_enet_get_fpsel(ring->id)); BIT 742 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c data = BIT(xgene_enet_ring_bufnum(ring->id)); BIT 41 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define OVERWRITE BIT(31) BIT 42 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define IS_BUFFER_POOL BIT(20) BIT 43 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define PREFETCH_BUF_EN BIT(21) BIT 92 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define ACCEPTLERR BIT(19) BIT 93 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define QCOHERENT BIT(4) BIT 94 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define RECOMBBUF BIT(27) BIT 137 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define BUSY_MASK BIT(0) BIT 138 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define READ_CYCLE_MASK BIT(0) BIT 150 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31) BIT 151 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define RESUME_TX BIT(0) BIT 152 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_SPEED_1250 BIT(24) BIT 153 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define TX_PORT0 BIT(0) BIT 154 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_BYPASS_UNISEC_TX BIT(2) BIT 155 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_BYPASS_UNISEC_RX BIT(1) BIT 156 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_BYPASS_EN0 BIT(31) BIT 178 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define PAUSE_XON_EN BIT(30) BIT 179 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define MULTI_DPF_AUTOCTRL BIT(28) BIT 188 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define TX_DV_GATE_EN0 BIT(2) BIT 189 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define RX_DV_GATE_EN0 BIT(1) BIT 190 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define RESUME_RX0 BIT(0) BIT 209 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define SOFT_RESET1 BIT(31) BIT 210 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define TX_EN BIT(0) BIT 211 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define RX_EN BIT(2) BIT 212 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define TX_FLOW_EN BIT(4) BIT 213 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define RX_FLOW_EN BIT(5) BIT 214 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define ENET_LHD_MODE BIT(25) BIT 215 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define ENET_GHD_MODE BIT(26) BIT 216 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define FULL_DUPLEX2 BIT(0) BIT 217 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define PAD_CRC BIT(2) BIT 218 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define LENGTH_CHK BIT(4) BIT 46 drivers/net/ethernet/apm/xgene/xgene_enet_main.c } else if (!(hw_len & BIT(14))) { BIT 62 drivers/net/ethernet/apm/xgene/xgene_enet_main.c hw_len = (size == SIZE_4K) ? BIT(14) : 0; BIT 1570 drivers/net/ethernet/apm/xgene/xgene_enet_main.c pdata->port_id = id & BIT(0); BIT 17 drivers/net/ethernet/apm/xgene/xgene_enet_ring2.h #define INTR_CLEAR BIT(23) BIT 515 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c data = BIT(xgene_enet_get_fpsel(ring->id)); BIT 518 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c data = BIT(xgene_enet_ring_bufnum(ring->id)); BIT 21 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h #define AUTO_NEG_COMPLETE BIT(5) BIT 22 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h #define LINK_STATUS BIT(2) BIT 23 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h #define LINK_UP BIT(15) BIT 24 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h #define MPA_IDLE_WITH_QMI_EMPTY BIT(12) BIT 324 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c data |= BIT(12); BIT 451 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c data = BIT(xgene_enet_get_fpsel(ring->id)); BIT 454 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c data = BIT(xgene_enet_ring_bufnum(ring->id)); BIT 22 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define CSR_CLK BIT(0) BIT 23 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define XGENET_CLK BIT(1) BIT 24 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define PCS_CLK BIT(3) BIT 25 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define AN_REF_CLK BIT(4) BIT 26 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define AN_CLK BIT(5) BIT 27 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define AD_CLK BIT(6) BIT 29 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define CSR_RST BIT(0) BIT 30 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define XGENET_RST BIT(1) BIT 31 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define PCS_RST BIT(3) BIT 32 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define AN_REF_RST BIT(4) BIT 33 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define AN_RST BIT(5) BIT 34 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define AD_RST BIT(6) BIT 38 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define HSTMACRST BIT(31) BIT 39 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define HSTTCTLEN BIT(31) BIT 40 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define HSTTFEN BIT(30) BIT 41 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define HSTRCTLEN BIT(29) BIT 42 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define HSTRFEN BIT(28) BIT 43 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define HSTPPEN BIT(7) BIT 44 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define HSTDRPLT64 BIT(5) BIT 45 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define HSTLENCHK BIT(3) BIT 84 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h #define PCS_CTRL_PCS_RST BIT(15) BIT 47 drivers/net/ethernet/aquantia/atlantic/aq_common.h #define AQ_NIC_RATE_10G BIT(0) BIT 48 drivers/net/ethernet/aquantia/atlantic/aq_common.h #define AQ_NIC_RATE_5G BIT(1) BIT 49 drivers/net/ethernet/aquantia/atlantic/aq_common.h #define AQ_NIC_RATE_5GSR BIT(2) BIT 50 drivers/net/ethernet/aquantia/atlantic/aq_common.h #define AQ_NIC_RATE_2GS BIT(3) BIT 51 drivers/net/ethernet/aquantia/atlantic/aq_common.h #define AQ_NIC_RATE_1G BIT(4) BIT 52 drivers/net/ethernet/aquantia/atlantic/aq_common.h #define AQ_NIC_RATE_100M BIT(5) BIT 54 drivers/net/ethernet/aquantia/atlantic/aq_common.h #define AQ_NIC_RATE_EEE_10G BIT(6) BIT 55 drivers/net/ethernet/aquantia/atlantic/aq_common.h #define AQ_NIC_RATE_EEE_5G BIT(7) BIT 56 drivers/net/ethernet/aquantia/atlantic/aq_common.h #define AQ_NIC_RATE_EEE_2GS BIT(8) BIT 57 drivers/net/ethernet/aquantia/atlantic/aq_common.h #define AQ_NIC_RATE_EEE_1G BIT(9) BIT 475 drivers/net/ethernet/aquantia/atlantic/aq_filters.c rx_fltrs->fl3l4.active_ipv4 &= ~BIT(data->location); BIT 478 drivers/net/ethernet/aquantia/atlantic/aq_filters.c ~BIT((data->location) / 4); BIT 509 drivers/net/ethernet/aquantia/atlantic/aq_filters.c rx_fltrs->fl3l4.active_ipv4 |= BIT(data->location); BIT 513 drivers/net/ethernet/aquantia/atlantic/aq_filters.c rx_fltrs->fl3l4.active_ipv6 |= BIT((data->location) / 4); BIT 185 drivers/net/ethernet/aquantia/atlantic/aq_nic.c BIT(self->aq_nic_cfg.link_irq_vec)); BIT 60 drivers/net/ethernet/aquantia/atlantic/aq_nic.h #define AQ_NIC_WOL_ENABLED BIT(0) BIT 45 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h #define HW_ATL_A0_TXD_CTL_CMD_VLAN BIT(22) BIT 46 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h #define HW_ATL_A0_TXD_CTL_CMD_FCS BIT(23) BIT 47 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h #define HW_ATL_A0_TXD_CTL_CMD_IPCSO BIT(24) BIT 48 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h #define HW_ATL_A0_TXD_CTL_CMD_TUCSO BIT(25) BIT 49 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h #define HW_ATL_A0_TXD_CTL_CMD_LSO BIT(26) BIT 50 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h #define HW_ATL_A0_TXD_CTL_CMD_WB BIT(27) BIT 51 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h #define HW_ATL_A0_TXD_CTL_CMD_VXLAN BIT(28) BIT 53 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h #define HW_ATL_A0_TXD_CTL_CMD_IPV6 BIT(21) BIT 54 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h #define HW_ATL_A0_TXD_CTL_CMD_TCP BIT(22) BIT 449 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c hw_atl_reg_gen_irq_map_set(self, BIT(7) | BIT 713 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c if (is_rx_check_sum_enabled & BIT(0) && BIT 715 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c buff->is_ip_cso = (rx_stat & BIT(1)) ? 0U : 1U; BIT 717 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c if (is_rx_check_sum_enabled & BIT(1)) { BIT 719 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c buff->is_udp_cso = (rx_stat & BIT(2)) ? 0U : BIT 720 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c !!(rx_stat & BIT(3)); BIT 722 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c buff->is_tcp_cso = (rx_stat & BIT(2)) ? 0U : BIT 723 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c !!(rx_stat & BIT(3)); BIT 739 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c if ((rx_stat & BIT(0)) || rxd_wb->type & 0x1000U) { BIT 50 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22) BIT 51 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23) BIT 52 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24) BIT 53 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25) BIT 54 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26) BIT 55 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27) BIT 56 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28) BIT 58 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21) BIT 59 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22) BIT 119 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN BIT(5) BIT 120 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h #define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN_DOUBLE BIT(6) BIT 147 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c BIT(HW_ATL_MAC_PHY_MPI_RESET_BIT), BIT 189 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c BIT(HW_ATL_MAC_PHY_MPI_RESET_BIT), BIT 278 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h HW_ATL_RX_ENABLE_MNGMNT_QUEUE_L3L4 = BIT(22), BIT 279 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h HW_ATL_RX_ENABLE_QUEUE_L3L4 = BIT(23), BIT 280 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h HW_ATL_RX_ENABLE_ARP_FLTR_L3 = BIT(24), BIT 281 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h HW_ATL_RX_ENABLE_CMP_PROT_L4 = BIT(25), BIT 282 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4 = BIT(26), BIT 283 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4 = BIT(27), BIT 284 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3 = BIT(28), BIT 285 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3 = BIT(29), BIT 286 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h HW_ATL_RX_ENABLE_L3_IPV6 = BIT(30), BIT 287 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h HW_ATL_RX_ENABLE_FLTR_L3L4 = BIT(31) BIT 316 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h #define HAL_ATLANTIC_RATE_10G BIT(0) BIT 317 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h #define HAL_ATLANTIC_RATE_5G BIT(1) BIT 318 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h #define HAL_ATLANTIC_RATE_5GSR BIT(2) BIT 319 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h #define HAL_ATLANTIC_RATE_2GS BIT(3) BIT 320 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h #define HAL_ATLANTIC_RATE_1G BIT(4) BIT 321 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h #define HAL_ATLANTIC_RATE_100M BIT(5) BIT 322 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h #define HAL_ATLANTIC_RATE_INVALID BIT(6) BIT 29 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CAP_PAUSE BIT(CAPS_HI_PAUSE) BIT 30 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CAP_ASYM_PAUSE BIT(CAPS_HI_ASYMMETRIC_PAUSE) BIT 31 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY) BIT 32 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL) BIT 34 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CTRL_SLEEP_PROXY BIT(CTRL_SLEEP_PROXY) BIT 35 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CTRL_WOL BIT(CTRL_WOL) BIT 36 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CTRL_LINK_DROP BIT(CTRL_LINK_DROP) BIT 37 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CTRL_PAUSE BIT(CTRL_PAUSE) BIT 38 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CTRL_TEMPERATURE BIT(CTRL_TEMPERATURE) BIT 39 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE BIT(CTRL_ASYMMETRIC_PAUSE) BIT 40 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CTRL_FORCE_RECONNECT BIT(CTRL_FORCE_RECONNECT) BIT 42 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE) BIT 43 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE) BIT 44 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE) BIT 45 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c #define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE) BIT 173 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c *mpi_state |= BIT(CAPS_HI_PAUSE); BIT 175 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c *mpi_state &= ~BIT(CAPS_HI_PAUSE); BIT 178 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE); BIT 180 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE); BIT 202 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c mpi_state &= ~BIT(CAPS_HI_LINK_DROP); BIT 207 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c mpi_state |= BIT(CAPS_HI_LINK_DROP); BIT 292 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS); BIT 296 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS); BIT 303 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c BIT(CAPS_HI_STATISTICS)), BIT 485 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c mpi_opts |= BIT(CTRL_FORCE_RECONNECT); BIT 68 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG1_TXE BIT(0) /* Tx Enable */ BIT 69 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ BIT 70 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG1_RXE BIT(2) /* Rx Enable */ BIT 71 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ BIT 72 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ BIT 73 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ BIT 74 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG1_SR BIT(31) /* Soft Reset */ BIT 79 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG2_FDX BIT(0) BIT 80 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG2_PAD_CRC_EN BIT(2) BIT 81 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG2_LEN_CHECK BIT(4) BIT 82 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG2_IF_1000 BIT(9) BIT 83 drivers/net/ethernet/atheros/ag71xx.c #define MAC_CFG2_IF_10_100 BIT(8) BIT 103 drivers/net/ethernet/atheros/ag71xx.c #define MII_CFG_RESET BIT(31) BIT 106 drivers/net/ethernet/atheros/ag71xx.c #define MII_CMD_READ BIT(0) BIT 114 drivers/net/ethernet/atheros/ag71xx.c #define MII_IND_BUSY BIT(0) BIT 115 drivers/net/ethernet/atheros/ag71xx.c #define MII_IND_INVALID BIT(2) BIT 118 drivers/net/ethernet/atheros/ag71xx.c #define MAC_IFCTL_SPEED BIT(16) BIT 123 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ BIT 124 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ BIT 125 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ BIT 126 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ BIT 127 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ BIT 138 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_DE BIT(0) /* Drop Event */ BIT 139 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ BIT 140 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_FC BIT(2) /* False Carrier */ BIT 141 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_CE BIT(3) /* Code Error */ BIT 142 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_CR BIT(4) /* CRC error */ BIT 143 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ BIT 144 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_LO BIT(6) /* Length out of range */ BIT 145 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_OK BIT(7) /* Packet is OK */ BIT 146 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ BIT 147 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ BIT 148 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_DR BIT(10) /* Dribble */ BIT 149 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_LE BIT(11) /* Long Event */ BIT 150 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_CF BIT(12) /* Control Frame */ BIT 151 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_PF BIT(13) /* Pause Frame */ BIT 152 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ BIT 153 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ BIT 154 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ BIT 155 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ BIT 164 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_DE BIT(0) /* Drop Event */ BIT 165 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ BIT 166 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_FC BIT(2) /* False Carrier */ BIT 167 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_CE BIT(3) /* Code Error */ BIT 168 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ BIT 169 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ BIT 170 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_OK BIT(6) /* Packet is OK */ BIT 171 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ BIT 172 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ BIT 173 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_DR BIT(9) /* Dribble */ BIT 174 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_CF BIT(10) /* Control Frame */ BIT 175 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_PF BIT(11) /* Pause Frame */ BIT 176 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ BIT 177 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ BIT 178 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_LE BIT(14) /* Long Event */ BIT 179 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ BIT 180 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_16 BIT(16) /* unknown */ BIT 181 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_17 BIT(17) /* unknown */ BIT 182 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_SF BIT(18) /* Short Frame */ BIT 183 drivers/net/ethernet/atheros/ag71xx.c #define FIFO_CFG5_BM BIT(19) /* Byte Mode */ BIT 192 drivers/net/ethernet/atheros/ag71xx.c #define TX_CTRL_TXE BIT(0) /* Tx Enable */ BIT 196 drivers/net/ethernet/atheros/ag71xx.c #define TX_STATUS_PS BIT(0) /* Packet Sent */ BIT 197 drivers/net/ethernet/atheros/ag71xx.c #define TX_STATUS_UR BIT(1) /* Tx Underrun */ BIT 198 drivers/net/ethernet/atheros/ag71xx.c #define TX_STATUS_BE BIT(3) /* Bus Error */ BIT 201 drivers/net/ethernet/atheros/ag71xx.c #define RX_CTRL_RXE BIT(0) /* Rx Enable */ BIT 208 drivers/net/ethernet/atheros/ag71xx.c #define RX_STATUS_PR BIT(0) /* Packet Received */ BIT 209 drivers/net/ethernet/atheros/ag71xx.c #define RX_STATUS_OF BIT(2) /* Rx Overflow */ BIT 210 drivers/net/ethernet/atheros/ag71xx.c #define RX_STATUS_BE BIT(3) /* Bus Error */ BIT 214 drivers/net/ethernet/atheros/ag71xx.c #define AG71XX_INT_TX_PS BIT(0) BIT 215 drivers/net/ethernet/atheros/ag71xx.c #define AG71XX_INT_TX_UR BIT(1) BIT 216 drivers/net/ethernet/atheros/ag71xx.c #define AG71XX_INT_TX_BE BIT(3) BIT 217 drivers/net/ethernet/atheros/ag71xx.c #define AG71XX_INT_RX_PR BIT(4) BIT 218 drivers/net/ethernet/atheros/ag71xx.c #define AG71XX_INT_RX_OF BIT(6) BIT 219 drivers/net/ethernet/atheros/ag71xx.c #define AG71XX_INT_RX_BE BIT(7) BIT 237 drivers/net/ethernet/atheros/ag71xx.c #define DESC_EMPTY BIT(31) BIT 238 drivers/net/ethernet/atheros/ag71xx.c #define DESC_MORE BIT(24) BIT 637 drivers/net/ethernet/atheros/ag71xx.c ring_mask = BIT(ring->order) - 1; BIT 638 drivers/net/ethernet/atheros/ag71xx.c ring_size = BIT(ring->order); BIT 958 drivers/net/ethernet/atheros/ag71xx.c int ring_mask = BIT(ring->order) - 1; BIT 990 drivers/net/ethernet/atheros/ag71xx.c int ring_size = BIT(ring->order); BIT 1015 drivers/net/ethernet/atheros/ag71xx.c int ring_size = BIT(ring->order); BIT 1061 drivers/net/ethernet/atheros/ag71xx.c int ring_mask = BIT(ring->order) - 1; BIT 1062 drivers/net/ethernet/atheros/ag71xx.c int ring_size = BIT(ring->order); BIT 1101 drivers/net/ethernet/atheros/ag71xx.c int ring_mask = BIT(ring->order) - 1; BIT 1137 drivers/net/ethernet/atheros/ag71xx.c ring_size = BIT(tx->order) + BIT(rx->order); BIT 1138 drivers/net/ethernet/atheros/ag71xx.c tx_size = BIT(tx->order); BIT 1167 drivers/net/ethernet/atheros/ag71xx.c ring_size = BIT(tx->order) + BIT(rx->order); BIT 1283 drivers/net/ethernet/atheros/ag71xx.c ring_mask = BIT(ring->order) - 1; BIT 1337 drivers/net/ethernet/atheros/ag71xx.c ring_mask = BIT(ring->order) - 1; BIT 1338 drivers/net/ethernet/atheros/ag71xx.c ring_size = BIT(ring->order); BIT 1447 drivers/net/ethernet/atheros/ag71xx.c ring_mask = BIT(ring->order) - 1; BIT 1448 drivers/net/ethernet/atheros/ag71xx.c ring_size = BIT(ring->order); BIT 1521 drivers/net/ethernet/atheros/ag71xx.c int rx_ring_size = BIT(rx_ring->order); BIT 90 drivers/net/ethernet/atheros/alx/alx.h ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG = BIT(0), BIT 566 drivers/net/ethernet/atheros/alx/main.c mc_hash[reg] |= BIT(bit); BIT 63 drivers/net/ethernet/atheros/alx/reg.h #define ALX_UE_SVRT_FCPROTERR BIT(13) BIT 64 drivers/net/ethernet/atheros/alx/reg.h #define ALX_UE_SVRT_DLPROTERR BIT(4) BIT 68 drivers/net/ethernet/atheros/alx/reg.h #define ALX_EFLD_F_EXIST BIT(10) BIT 69 drivers/net/ethernet/atheros/alx/reg.h #define ALX_EFLD_E_EXIST BIT(9) BIT 70 drivers/net/ethernet/atheros/alx/reg.h #define ALX_EFLD_STAT BIT(5) BIT 71 drivers/net/ethernet/atheros/alx/reg.h #define ALX_EFLD_START BIT(0) BIT 75 drivers/net/ethernet/atheros/alx/reg.h #define ALX_SLD_STAT BIT(12) BIT 76 drivers/net/ethernet/atheros/alx/reg.h #define ALX_SLD_START BIT(11) BIT 80 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PDLL_TRNS1_D3PLLOFF_EN BIT(11) BIT 83 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_HOTRST_WTEN BIT(31) BIT 85 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_ASPM_FCEN BIT(30) BIT 86 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_SADLY_EN BIT(29) BIT 94 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_TXL1_AFTER_L0S BIT(19) BIT 98 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_RCVR_WT_1US BIT(15) BIT 100 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_L1_CLKSW_EN BIT(13) BIT 101 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_L0S_EN BIT(12) BIT 102 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_RXL1_AFTER_L0S BIT(11) BIT 103 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_L1_BUFSRX_EN BIT(7) BIT 105 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_L1_SRDSRX_PWD BIT(6) BIT 106 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_L1_SRDSPLL_EN BIT(5) BIT 107 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_L1_SRDS_EN BIT(4) BIT 108 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PMCTRL_L1_EN BIT(3) BIT 116 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MASTER_PCLKSEL_SRDS BIT(12) BIT 118 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MASTER_IRQMOD2_EN BIT(11) BIT 120 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MASTER_IRQMOD1_EN BIT(10) BIT 121 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MASTER_SYSALVTIMER_EN BIT(7) BIT 122 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MASTER_OOB_DIS BIT(6) BIT 124 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MASTER_WAKEN_25M BIT(5) BIT 126 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MASTER_DMA_MAC_RST BIT(0) BIT 134 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PHY_CTRL_100AB_EN BIT(17) BIT 136 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PHY_CTRL_POWER_DOWN BIT(14) BIT 138 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PHY_CTRL_PLL_ON BIT(13) BIT 139 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PHY_CTRL_RST_ANALOG BIT(12) BIT 140 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PHY_CTRL_HIB_PULSE BIT(11) BIT 141 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PHY_CTRL_HIB_EN BIT(10) BIT 142 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PHY_CTRL_IDDQ BIT(7) BIT 143 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PHY_CTRL_GATE_25M BIT(5) BIT 144 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PHY_CTRL_LED_MODE BIT(2) BIT 146 drivers/net/ethernet/atheros/alx/reg.h #define ALX_PHY_CTRL_DSPRST_OUT BIT(0) BIT 153 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_STS_TXQ_BUSY BIT(3) BIT 154 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_STS_RXQ_BUSY BIT(2) BIT 155 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_STS_TXMAC_BUSY BIT(1) BIT 156 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_STS_RXMAC_BUSY BIT(0) BIT 163 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MDIO_MODE_EXT BIT(30) BIT 164 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MDIO_BUSY BIT(27) BIT 169 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MDIO_START BIT(23) BIT 170 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MDIO_SPRES_PRMBL BIT(22) BIT 172 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MDIO_OP_READ BIT(21) BIT 186 drivers/net/ethernet/atheros/alx/reg.h #define ALX_SERDES_PHYCLK_SLWDWN BIT(18) BIT 187 drivers/net/ethernet/atheros/alx/reg.h #define ALX_SERDES_MACCLK_SLWDWN BIT(17) BIT 190 drivers/net/ethernet/atheros/alx/reg.h #define ALX_LPI_CTRL_EN BIT(0) BIT 196 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_SWOI_STARTUP_PKT_EN BIT(23) BIT 197 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_IOAC_2_FRAGMENTED BIT(22) BIT 198 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_IOAC_1_FRAGMENTED BIT(21) BIT 199 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_IOAC_1_KEEPALIVE_EN BIT(20) BIT 200 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_IOAC_1_HAS_VLAN BIT(19) BIT 201 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_8023 BIT(18) BIT 202 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_IPV6 BIT(17) BIT 203 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_IOAC_2_KEEPALIVE_EN BIT(16) BIT 204 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_IOAC_2_HAS_VLAN BIT(15) BIT 205 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_8023 BIT(14) BIT 206 drivers/net/ethernet/atheros/alx/reg.h #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_IPV6 BIT(13) BIT 207 drivers/net/ethernet/atheros/alx/reg.h #define ALX_HRTBT_EXT_CTRL_NS_EN BIT(12) BIT 210 drivers/net/ethernet/atheros/alx/reg.h #define ALX_HRTBT_EXT_CTRL_IS_8023 BIT(3) BIT 211 drivers/net/ethernet/atheros/alx/reg.h #define ALX_HRTBT_EXT_CTRL_IS_IPV6 BIT(2) BIT 212 drivers/net/ethernet/atheros/alx/reg.h #define ALX_HRTBT_EXT_CTRL_WAKEUP_EN BIT(1) BIT 213 drivers/net/ethernet/atheros/alx/reg.h #define ALX_HRTBT_EXT_CTRL_ARP_EN BIT(0) BIT 224 drivers/net/ethernet/atheros/alx/reg.h #define ALX_SWOI_ORIG_ACK_NAK_EN BIT(20) BIT 252 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_FAST_PAUSE BIT(31) BIT 253 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_WOLSPED_SWEN BIT(30) BIT 255 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_MHASH_ALG_HI5B BIT(29) BIT 256 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_BRD_EN BIT(26) BIT 257 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_MULTIALL_EN BIT(25) BIT 262 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_PROMISC_EN BIT(15) BIT 263 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_VLANSTRIP BIT(14) BIT 266 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_PCRCE BIT(7) BIT 267 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_CRCE BIT(6) BIT 268 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_FULLD BIT(5) BIT 269 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_RXFC_EN BIT(3) BIT 270 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_TXFC_EN BIT(2) BIT 271 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_RX_EN BIT(1) BIT 272 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MAC_CTRL_TX_EN BIT(0) BIT 290 drivers/net/ethernet/atheros/alx/reg.h #define ALX_SRAM_LOAD_PTR BIT(0) BIT 327 drivers/net/ethernet/atheros/alx/reg.h #define ALX_TXQ0_LSO_8023_EN BIT(7) BIT 328 drivers/net/ethernet/atheros/alx/reg.h #define ALX_TXQ0_MODE_ENHANCE BIT(6) BIT 329 drivers/net/ethernet/atheros/alx/reg.h #define ALX_TXQ0_EN BIT(5) BIT 330 drivers/net/ethernet/atheros/alx/reg.h #define ALX_TXQ0_SUPT_IPOPT BIT(4) BIT 337 drivers/net/ethernet/atheros/alx/reg.h #define ALX_TXQ1_ERRLGPKT_DROP_EN BIT(11) BIT 341 drivers/net/ethernet/atheros/alx/reg.h #define ALX_RXQ0_EN BIT(31) BIT 342 drivers/net/ethernet/atheros/alx/reg.h #define ALX_RXQ0_RSS_HASH_EN BIT(29) BIT 354 drivers/net/ethernet/atheros/alx/reg.h #define ALX_RXQ0_IPV6_PARSE_EN BIT(7) BIT 357 drivers/net/ethernet/atheros/alx/reg.h #define ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN BIT(5) BIT 358 drivers/net/ethernet/atheros/alx/reg.h #define ALX_RXQ0_RSS_HSTYP_IPV6_EN BIT(4) BIT 359 drivers/net/ethernet/atheros/alx/reg.h #define ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN BIT(3) BIT 360 drivers/net/ethernet/atheros/alx/reg.h #define ALX_RXQ0_RSS_HSTYP_IPV4_EN BIT(2) BIT 390 drivers/net/ethernet/atheros/alx/reg.h #define ALX_DMA_RREQ_PRI_DATA BIT(10) BIT 398 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL0_PME_LINK BIT(5) BIT 399 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL0_LINK_EN BIT(4) BIT 400 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL0_PME_MAGIC_EN BIT(3) BIT 401 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL0_MAGIC_EN BIT(2) BIT 464 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_DIS BIT(31) BIT 465 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_RX_Q7 BIT(30) BIT 466 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_RX_Q6 BIT(29) BIT 467 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_RX_Q5 BIT(28) BIT 468 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_RX_Q4 BIT(27) BIT 469 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_PCIE_LNKDOWN BIT(26) BIT 470 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_RX_Q3 BIT(19) BIT 471 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_RX_Q2 BIT(18) BIT 472 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_RX_Q1 BIT(17) BIT 473 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_RX_Q0 BIT(16) BIT 474 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_TX_Q0 BIT(15) BIT 475 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_PHY BIT(12) BIT 476 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_DMAW BIT(10) BIT 477 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_DMAR BIT(9) BIT 478 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_TXF_UR BIT(8) BIT 479 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_TX_Q3 BIT(7) BIT 480 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_TX_Q2 BIT(6) BIT 481 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_TX_Q1 BIT(5) BIT 482 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_RFD_UR BIT(4) BIT 483 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_RXF_OV BIT(3) BIT 484 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_MANU BIT(2) BIT 485 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_TIMER BIT(1) BIT 486 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ISR_SMB BIT(0) BIT 502 drivers/net/ethernet/atheros/alx/reg.h #define ALX_CLK_GATE_RXMAC BIT(5) BIT 503 drivers/net/ethernet/atheros/alx/reg.h #define ALX_CLK_GATE_TXMAC BIT(4) BIT 504 drivers/net/ethernet/atheros/alx/reg.h #define ALX_CLK_GATE_RXQ BIT(3) BIT 505 drivers/net/ethernet/atheros/alx/reg.h #define ALX_CLK_GATE_TXQ BIT(2) BIT 506 drivers/net/ethernet/atheros/alx/reg.h #define ALX_CLK_GATE_DMAR BIT(1) BIT 507 drivers/net/ethernet/atheros/alx/reg.h #define ALX_CLK_GATE_DMAW BIT(0) BIT 517 drivers/net/ethernet/atheros/alx/reg.h #define ALX_DRV_PHY_AUTO BIT(28) BIT 518 drivers/net/ethernet/atheros/alx/reg.h #define ALX_DRV_PHY_1000 BIT(27) BIT 519 drivers/net/ethernet/atheros/alx/reg.h #define ALX_DRV_PHY_100 BIT(26) BIT 520 drivers/net/ethernet/atheros/alx/reg.h #define ALX_DRV_PHY_10 BIT(25) BIT 521 drivers/net/ethernet/atheros/alx/reg.h #define ALX_DRV_PHY_DUPLEX BIT(24) BIT 523 drivers/net/ethernet/atheros/alx/reg.h #define ALX_DRV_PHY_PAUSE BIT(23) BIT 534 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL2_DATA_STORE BIT(3) BIT 535 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL2_PTRN_EVT BIT(2) BIT 536 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL2_PME_PTRN_EN BIT(1) BIT 537 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL2_PTRN_EN BIT(0) BIT 544 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT15_MATCH BIT(31) BIT 545 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT14_MATCH BIT(30) BIT 546 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT13_MATCH BIT(29) BIT 547 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT12_MATCH BIT(28) BIT 548 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT11_MATCH BIT(27) BIT 549 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT10_MATCH BIT(26) BIT 550 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT9_MATCH BIT(25) BIT 551 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT8_MATCH BIT(24) BIT 552 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT7_MATCH BIT(23) BIT 553 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT6_MATCH BIT(22) BIT 554 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT5_MATCH BIT(21) BIT 555 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT4_MATCH BIT(20) BIT 556 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT3_MATCH BIT(19) BIT 557 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT2_MATCH BIT(18) BIT 558 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT1_MATCH BIT(17) BIT 559 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT0_MATCH BIT(16) BIT 560 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT15_EN BIT(15) BIT 561 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT14_EN BIT(14) BIT 562 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT13_EN BIT(13) BIT 563 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT12_EN BIT(12) BIT 564 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT11_EN BIT(11) BIT 565 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT10_EN BIT(10) BIT 566 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT9_EN BIT(9) BIT 567 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT8_EN BIT(8) BIT 568 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT7_EN BIT(7) BIT 569 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT6_EN BIT(6) BIT 570 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT5_EN BIT(5) BIT 571 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT4_EN BIT(4) BIT 572 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT3_EN BIT(3) BIT 573 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT2_EN BIT(2) BIT 574 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT1_EN BIT(1) BIT 575 drivers/net/ethernet/atheros/alx/reg.h #define ALX_WOL_CTRL4_PT0_EN BIT(0) BIT 642 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ACER_MAGIC_EN BIT(31) BIT 643 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ACER_MAGIC_PME_EN BIT(30) BIT 644 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ACER_MAGIC_MATCH BIT(29) BIT 645 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ACER_MAGIC_FF_CHECK BIT(10) BIT 652 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ACER_TIMER_EN BIT(31) BIT 653 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ACER_TIMER_PME_EN BIT(30) BIT 654 drivers/net/ethernet/atheros/alx/reg.h #define ALX_ACER_TIMER_MATCH BIT(29) BIT 693 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MSI_MASK_SEL_LINE BIT(16) BIT 714 drivers/net/ethernet/atheros/alx/reg.h #define ALX_HQTPD_BURST_EN BIT(31) BIT 726 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MISC_ISO_EN BIT(12) BIT 727 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MISC_INTNLOSC_OPEN BIT(3) BIT 730 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MSIC2_CALB_START BIT(0) BIT 734 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MISC3_25M_BY_SW BIT(1) BIT 736 drivers/net/ethernet/atheros/alx/reg.h #define ALX_MISC3_25M_NOTO_INTNL BIT(0) BIT 95 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define TWSI_CTRL_LD_EXIST BIT(23) BIT 96 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define TWSI_CTRL_HW_LDSTAT BIT(12) /* 0:finish,1:in progress */ BIT 97 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define TWSI_CTRL_SW_LDSTART BIT(11) BIT 109 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PCIE_PHYMISC_FORCE_RCV_DET BIT(2) BIT 122 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define TWSI_DEBUG_DEV_EXIST BIT(29) BIT 125 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define DMA_DBG_VENDOR_MSG BIT(0) BIT 138 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define OTP_CTRL_CLK_EN BIT(1) BIT 141 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_HOTRST BIT(31) BIT 142 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on BIT 144 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_SA_DLY_EN BIT(29) BIT 145 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_L0S_BUFSRX_EN BIT(28) BIT 153 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */ BIT 168 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_RCVR_WT_TIMER BIT(15) /* 1:1us, 0:2ms */ BIT 169 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_CLK_PWM_VER1_1 BIT(14) /* 0:1.0a,1:1.1 */ BIT 170 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */ BIT 171 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_ASPM_L0S_EN BIT(12) BIT 172 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_RXL1_AFTER_L0S BIT(11) /* l1dv2.0+ */ BIT 177 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_SERDES_BUFS_RX_L1_EN BIT(7) BIT 178 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_SERDES_PD_EX_L1 BIT(6) /* power down serdes rx */ BIT 179 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_SERDES_PLL_L1_EN BIT(5) BIT 180 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_SERDES_L1_EN BIT(4) BIT 181 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_ASPM_L1_EN BIT(3) BIT 182 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_CLK_REQ_EN BIT(2) BIT 183 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_RBER_EN BIT(1) BIT 184 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define PM_CTRL_SPRSDWER_EN BIT(0) BIT 192 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_OTP_SEL BIT(31) BIT 197 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_INT_RDCLR BIT(14) BIT 198 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_CLK_SEL_DIS BIT(12) /* 1:alwys sel pclk from BIT 200 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_RX_ITIMER_EN BIT(11) /* IRQ MODURATION FOR RX */ BIT 201 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_TX_ITIMER_EN BIT(10) /* MODURATION FOR TX/RX */ BIT 202 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_MANU_INT BIT(9) /* SOFT MANUAL INT */ BIT 203 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_MANUTIMER_EN BIT(8) BIT 204 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_SA_TIMER_EN BIT(7) /* SYS ALIVE TIMER EN */ BIT 205 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_OOB_DIS BIT(6) /* OUT OF BOX DIS */ BIT 206 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */ BIT 207 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_BERT_START BIT(4) BIT 210 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_PCIE_RST BIT(1) BIT 211 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MASTER_CTRL_SOFT_RST BIT(0) /* RST MAC & DMA */ BIT 226 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_BP_VLTGSW BIT(18) BIT 227 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_100AB_EN BIT(17) BIT 228 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_10AB_EN BIT(16) BIT 229 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_PHY_PLL_BYPASS BIT(15) BIT 230 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_PWDOWN_HW BIT(14) /* affect MAC&PHY, to low pw */ BIT 231 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_PHY_PLL_ON BIT(13) /* 1:pll always on, 0:can sw */ BIT 232 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_SEL_ANA_RST BIT(12) BIT 233 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_HIB_PULSE BIT(11) BIT 234 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_HIB_EN BIT(10) BIT 235 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_GIGA_DIS BIT(9) BIT 236 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_PHY_IDDQ_DIS BIT(8) /* pw on RST */ BIT 237 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_PHY_IDDQ BIT(7) /* bit8 affect bit7 while rb */ BIT 238 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_LPW_EXIT BIT(6) BIT 239 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_GATE_25M_EN BIT(5) BIT 240 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_REV_ANEG BIT(4) BIT 241 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_ANEG_NOW BIT(3) BIT 242 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_LED_MODE BIT(2) BIT 243 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_RTL_MODE BIT(1) BIT 244 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define GPHY_CTRL_EXT_RESET BIT(0) /* 1:out of DSP RST status */ BIT 255 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define IDLE_STATUS_CALIB_DONE BIT(13) BIT 260 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define IDLE_STATUS_TXQ_BUSY BIT(3) BIT 261 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define IDLE_STATUS_RXQ_BUSY BIT(2) BIT 262 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define IDLE_STATUS_TXMAC_BUSY BIT(1) BIT 263 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define IDLE_STATUS_RXMAC_BUSY BIT(0) BIT 272 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MDIO_CTRL_MODE_EXT BIT(30) BIT 273 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MDIO_CTRL_POST_READ BIT(29) BIT 274 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MDIO_CTRL_AP_EN BIT(28) BIT 275 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MDIO_CTRL_BUSY BIT(27) BIT 285 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MDIO_CTRL_START BIT(23) BIT 286 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MDIO_CTRL_SPRES_PRMBL BIT(22) BIT 287 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MDIO_CTRL_OP_READ BIT(21) /* 1:read, 0:write */ BIT 321 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_PHY_CLK_SLOWDOWN BIT(18) BIT 322 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_MAC_CLK_SLOWDOWN BIT(17) BIT 325 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */ BIT 326 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */ BIT 327 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_BUFS_RX_EN BIT(11) BIT 328 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_PD_RX BIT(10) BIT 329 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_PLL_EN BIT(9) BIT 330 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_EN BIT(8) BIT 331 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */ BIT 338 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_VCO_SLOW BIT(3) BIT 339 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_VCO_FAST BIT(2) BIT 340 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_LOCK_DETECT_EN BIT(1) BIT 341 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define SERDES_LOCK_DETECT BIT(0) BIT 347 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define LPI_CTRL_CHK_DA BIT(31) BIT 352 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define LPI_CTRL_ENH_EN BIT(5) BIT 353 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define LPI_CTRL_CHK_RX BIT(4) BIT 354 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define LPI_CTRL_CHK_STATE BIT(3) BIT 355 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define LPI_CTRL_GMII BIT(2) BIT 356 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define LPI_CTRL_TO_PHY BIT(1) BIT 357 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define LPI_CTRL_EN BIT(0) BIT 365 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_SPEED_MODE_SW BIT(30) /* 0:phy,1:sw */ BIT 366 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_HASH_ALG_CRC32 BIT(29) /* 1:legacy,0:lw_5b */ BIT 367 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_SINGLE_PAUSE_EN BIT(28) BIT 368 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_DBG BIT(27) BIT 369 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_BC_EN BIT(26) BIT 370 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_MC_ALL_EN BIT(25) BIT 371 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_RX_CHKSUM_EN BIT(24) BIT 372 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_TX_HUGE BIT(23) BIT 373 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_DBG_TX_BKPRESURE BIT(22) BIT 378 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_TX_SIMURST BIT(19) BIT 379 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_SCNT BIT(17) BIT 380 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_TX_PAUSE BIT(16) BIT 381 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_PROMIS_EN BIT(15) BIT 382 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_RMV_VLAN BIT(14) BIT 385 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_HUGE_EN BIT(9) BIT 386 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_LENCHK BIT(8) BIT 387 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_PAD BIT(7) BIT 388 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_ADD_CRC BIT(6) BIT 389 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_DUPLX BIT(5) BIT 390 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_LOOPBACK BIT(4) BIT 391 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_RX_FLOW BIT(3) BIT 392 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_TX_FLOW BIT(2) BIT 393 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_RX_EN BIT(1) BIT 394 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define MAC_CTRL_TX_EN BIT(0) BIT 438 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT7_MATCH BIT(31) BIT 439 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT6_MATCH BIT(30) BIT 440 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT5_MATCH BIT(29) BIT 441 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT4_MATCH BIT(28) BIT 442 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT3_MATCH BIT(27) BIT 443 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT2_MATCH BIT(26) BIT 444 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT1_MATCH BIT(25) BIT 445 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT0_MATCH BIT(24) BIT 446 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT7_EN BIT(23) BIT 447 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT6_EN BIT(22) BIT 448 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT5_EN BIT(21) BIT 449 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT4_EN BIT(20) BIT 450 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT3_EN BIT(19) BIT 451 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT2_EN BIT(18) BIT 452 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT1_EN BIT(17) BIT 453 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PT0_EN BIT(16) BIT 454 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_LNKCHG_ST BIT(10) BIT 455 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_MAGIC_ST BIT(9) BIT 456 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PATTERN_ST BIT(8) BIT 457 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_OOB_EN BIT(6) BIT 458 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_LINK_CHG_PME_EN BIT(5) BIT 459 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_LINK_CHG_EN BIT(4) BIT 460 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_MAGIC_PME_EN BIT(3) BIT 461 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_MAGIC_EN BIT(2) BIT 462 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PATTERN_PME_EN BIT(1) BIT 463 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define WOL_PATTERN_EN BIT(0) BIT 548 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define TXQ_CTRL_PEDING_CLR BIT(8) BIT 549 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define TXQ_CTRL_LS_8023_EN BIT(7) BIT 550 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define TXQ_CTRL_ENH_MODE BIT(6) BIT 551 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define TXQ_CTRL_EN BIT(5) BIT 552 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define TXQ_CTRL_IP_OPTION_EN BIT(4) BIT 593 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define IPV6_CHKSUM_CTRL_EN BIT(7) BIT 603 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define RSS_NIP_QUEUE_SEL BIT(28) /* 0:q0, 1:table */ BIT 604 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define RRS_HASH_CTRL_EN BIT(29) BIT 605 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define RX_CUT_THRU_EN BIT(30) BIT 606 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define RXQ_CTRL_EN BIT(31) BIT 628 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define DMA_CTRL_SMB_NOW BIT(31) BIT 629 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define DMA_CTRL_WPEND_CLR BIT(30) BIT 630 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define DMA_CTRL_RPEND_CLR BIT(29) BIT 637 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define DMA_CTRL_RREQ_PRI_DATA BIT(10) /* 0:tpd, 1:data */ BIT 642 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define L1C_CTRL_DMA_RCB_LEN128 BIT(3) /* 0:64bytes,1:128bytes */ BIT 25 drivers/net/ethernet/aurora/nb8800.h #define TX_TPD BIT(5) BIT 26 drivers/net/ethernet/aurora/nb8800.h #define TX_APPEND_FCS BIT(4) BIT 27 drivers/net/ethernet/aurora/nb8800.h #define TX_PAD_EN BIT(3) BIT 28 drivers/net/ethernet/aurora/nb8800.h #define TX_RETRY_EN BIT(2) BIT 29 drivers/net/ethernet/aurora/nb8800.h #define TX_EN BIT(0) BIT 34 drivers/net/ethernet/aurora/nb8800.h #define RX_BC_DISABLE BIT(7) BIT 35 drivers/net/ethernet/aurora/nb8800.h #define RX_RUNT BIT(6) BIT 36 drivers/net/ethernet/aurora/nb8800.h #define RX_AF_EN BIT(5) BIT 37 drivers/net/ethernet/aurora/nb8800.h #define RX_PAUSE_EN BIT(3) BIT 38 drivers/net/ethernet/aurora/nb8800.h #define RX_SEND_CRC BIT(2) BIT 39 drivers/net/ethernet/aurora/nb8800.h #define RX_PAD_STRIP BIT(1) BIT 40 drivers/net/ethernet/aurora/nb8800.h #define RX_EN BIT(0) BIT 49 drivers/net/ethernet/aurora/nb8800.h #define MDIO_CMD_GO BIT(31) BIT 50 drivers/net/ethernet/aurora/nb8800.h #define MDIO_CMD_WR BIT(26) BIT 56 drivers/net/ethernet/aurora/nb8800.h #define MDIO_STS_ERR BIT(31) BIT 63 drivers/net/ethernet/aurora/nb8800.h #define RGMII_MODE BIT(7) BIT 64 drivers/net/ethernet/aurora/nb8800.h #define HALF_DUPLEX BIT(4) BIT 65 drivers/net/ethernet/aurora/nb8800.h #define BURST_EN BIT(3) BIT 66 drivers/net/ethernet/aurora/nb8800.h #define LOOPBACK_EN BIT(2) BIT 67 drivers/net/ethernet/aurora/nb8800.h #define GMAC_MODE BIT(0) BIT 82 drivers/net/ethernet/aurora/nb8800.h #define SLEEP_MODE BIT(0) BIT 85 drivers/net/ethernet/aurora/nb8800.h #define WAKEUP BIT(0) BIT 89 drivers/net/ethernet/aurora/nb8800.h #define TCR_LK BIT(12) BIT 90 drivers/net/ethernet/aurora/nb8800.h #define TCR_DS BIT(11) BIT 92 drivers/net/ethernet/aurora/nb8800.h #define TCR_DIE BIT(7) BIT 94 drivers/net/ethernet/aurora/nb8800.h #define TCR_LE BIT(3) BIT 95 drivers/net/ethernet/aurora/nb8800.h #define TCR_RS BIT(2) BIT 96 drivers/net/ethernet/aurora/nb8800.h #define TCR_DM BIT(1) BIT 97 drivers/net/ethernet/aurora/nb8800.h #define TCR_EN BIT(0) BIT 100 drivers/net/ethernet/aurora/nb8800.h #define TSR_DE BIT(3) BIT 101 drivers/net/ethernet/aurora/nb8800.h #define TSR_DI BIT(2) BIT 102 drivers/net/ethernet/aurora/nb8800.h #define TSR_TO BIT(1) BIT 103 drivers/net/ethernet/aurora/nb8800.h #define TSR_TI BIT(0) BIT 110 drivers/net/ethernet/aurora/nb8800.h #define TX_FIRST_DEFERRAL BIT(7) BIT 112 drivers/net/ethernet/aurora/nb8800.h #define TX_LATE_COLLISION BIT(2) BIT 113 drivers/net/ethernet/aurora/nb8800.h #define TX_PACKET_DROPPED BIT(1) BIT 114 drivers/net/ethernet/aurora/nb8800.h #define TX_FIFO_UNDERRUN BIT(0) BIT 121 drivers/net/ethernet/aurora/nb8800.h #define RCR_FL BIT(13) BIT 122 drivers/net/ethernet/aurora/nb8800.h #define RCR_LK BIT(12) BIT 123 drivers/net/ethernet/aurora/nb8800.h #define RCR_DS BIT(11) BIT 125 drivers/net/ethernet/aurora/nb8800.h #define RCR_DIE BIT(7) BIT 127 drivers/net/ethernet/aurora/nb8800.h #define RCR_LE BIT(3) BIT 128 drivers/net/ethernet/aurora/nb8800.h #define RCR_RS BIT(2) BIT 129 drivers/net/ethernet/aurora/nb8800.h #define RCR_DM BIT(1) BIT 130 drivers/net/ethernet/aurora/nb8800.h #define RCR_EN BIT(0) BIT 133 drivers/net/ethernet/aurora/nb8800.h #define RSR_DE BIT(3) BIT 134 drivers/net/ethernet/aurora/nb8800.h #define RSR_DI BIT(2) BIT 135 drivers/net/ethernet/aurora/nb8800.h #define RSR_RO BIT(1) BIT 136 drivers/net/ethernet/aurora/nb8800.h #define RSR_RI BIT(0) BIT 143 drivers/net/ethernet/aurora/nb8800.h #define RX_MULTICAST_PKT BIT(9) BIT 144 drivers/net/ethernet/aurora/nb8800.h #define RX_BROADCAST_PKT BIT(8) BIT 145 drivers/net/ethernet/aurora/nb8800.h #define RX_LENGTH_ERR BIT(7) BIT 146 drivers/net/ethernet/aurora/nb8800.h #define RX_FCS_ERR BIT(6) BIT 147 drivers/net/ethernet/aurora/nb8800.h #define RX_RUNT_PKT BIT(5) BIT 148 drivers/net/ethernet/aurora/nb8800.h #define RX_FIFO_OVERRUN BIT(4) BIT 149 drivers/net/ethernet/aurora/nb8800.h #define RX_LATE_COLLISION BIT(3) BIT 150 drivers/net/ethernet/aurora/nb8800.h #define RX_ALIGNMENT_ERROR BIT(2) BIT 162 drivers/net/ethernet/aurora/nb8800.h #define PAD_MODE_GTX_CLK_INV BIT(3) BIT 163 drivers/net/ethernet/aurora/nb8800.h #define PAD_MODE_GTX_CLK_DELAY BIT(4) BIT 176 drivers/net/ethernet/aurora/nb8800.h #define DESC_ID BIT(23) BIT 177 drivers/net/ethernet/aurora/nb8800.h #define DESC_EOC BIT(22) BIT 178 drivers/net/ethernet/aurora/nb8800.h #define DESC_EOF BIT(21) BIT 179 drivers/net/ethernet/aurora/nb8800.h #define DESC_LK BIT(20) BIT 180 drivers/net/ethernet/aurora/nb8800.h #define DESC_DS BIT(19) BIT 1523 drivers/net/ethernet/broadcom/b44.c pmask[len >> 3] |= BIT(len & 7); BIT 1537 drivers/net/ethernet/broadcom/b44.c pmask[len >> 3] |= BIT(len & 7); BIT 72 drivers/net/ethernet/broadcom/bcmsysport.c return BIT(bit); BIT 75 drivers/net/ethernet/broadcom/bcmsysport.c return BIT(bit + 1); BIT 77 drivers/net/ethernet/broadcom/bcmsysport.c return BIT(bit); BIT 888 drivers/net/ethernet/broadcom/bcmsysport.c intrl2_1_writel(ring->priv, BIT(ring->index), INTRL2_CPU_CLEAR); BIT 890 drivers/net/ethernet/broadcom/bcmsysport.c intrl2_0_writel(ring->priv, BIT(ring->index + BIT 972 drivers/net/ethernet/broadcom/bcmsysport.c intrl2_1_mask_clear(ring->priv, BIT(ring->index)); BIT 974 drivers/net/ethernet/broadcom/bcmsysport.c intrl2_0_mask_clear(ring->priv, BIT(ring->index + BIT 1138 drivers/net/ethernet/broadcom/bcmsysport.c ring_bit = BIT(ring + INTRL2_0_TDMA_MBDONE_SHIFT); BIT 1171 drivers/net/ethernet/broadcom/bcmsysport.c if (!(priv->irq1_stat & BIT(ring))) BIT 1177 drivers/net/ethernet/broadcom/bcmsysport.c intrl2_1_mask_set(priv, BIT(ring)); BIT 1520 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~BIT(TSB_SWAP1); BIT 2627 drivers/net/ethernet/broadcom/bcmsysport.c reg |= BIT(RXCHK_BRCM_TAG_MATCH_SHIFT + i); BIT 220 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_CLK_EN BIT(0) BIT 221 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_RESERVED_0 BIT(1) BIT 222 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_SOURCE_SYNC_MODE_EN BIT(2) BIT 223 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_DEST_SYNC_MODE_EN BIT(3) BIT 224 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_TX_CLK_OUT_INVERT_EN BIT(4) BIT 225 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_DIRECT_GMII_MODE BIT(5) BIT 226 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_CLK_250_SEL BIT(6) BIT 232 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_RESERVED BIT(31) BIT 409 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_TX_MASK_SETUP BIT(0) BIT 410 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_RX_MASK_SETUP BIT(1) BIT 411 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_IOST_ATTACHED BIT(2) BIT 412 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_NO_RESET BIT(3) BIT 413 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_MISC_PLL_REQ BIT(4) BIT 414 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_SW_TYPE_PHY BIT(5) BIT 415 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_SW_TYPE_EPHYRMII BIT(6) BIT 416 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_SW_TYPE_RGMII BIT(7) BIT 417 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_CMN_PHY_CTL BIT(8) BIT 418 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_FLW_CTRL1 BIT(9) BIT 419 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_FLW_CTRL2 BIT(10) BIT 420 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_SET_RXQ_CLK BIT(11) BIT 421 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_CLKCTLST BIT(12) BIT 422 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_NO_CLR_MIB BIT(13) BIT 423 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_FORCE_SPEED_2500 BIT(14) BIT 424 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_CMDCFG_SR_REV4 BIT(15) BIT 425 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_IRQ_ID_OOB_6 BIT(16) BIT 426 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_CC4_IF_SW_TYPE BIT(17) BIT 427 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII BIT(18) BIT 428 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_CC7_IF_TYPE_RGMII BIT(19) BIT 429 drivers/net/ethernet/broadcom/bgmac.h #define BGMAC_FEAT_IDM_MASK BIT(20) BIT 111 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h #define BNX2X_VF_FILTER_MAC BIT(0) BIT 112 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h #define BNX2X_VF_FILTER_VLAN BIT(1) BIT 409 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c BIT(DEVLINK_PARAM_CMODE_PERMANENT), BIT 413 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c BIT(DEVLINK_PARAM_CMODE_PERMANENT), BIT 417 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c BIT(DEVLINK_PARAM_CMODE_PERMANENT), BIT 421 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c BIT(DEVLINK_PARAM_CMODE_PERMANENT), BIT 426 drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c BIT(DEVLINK_PARAM_CMODE_PERMANENT), BIT 180 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c if ((dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_CONTROL)) == 0 || BIT 181 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c (dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_BASIC)) == 0) { BIT 67 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_ACTION_FLAG_FWD BIT(0) BIT 68 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_ACTION_FLAG_FWD_VXLAN BIT(1) BIT 69 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_ACTION_FLAG_PUSH_VLAN BIT(3) BIT 70 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_ACTION_FLAG_POP_VLAN BIT(4) BIT 71 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_ACTION_FLAG_DROP BIT(5) BIT 72 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_ACTION_FLAG_TUNNEL_ENCAP BIT(6) BIT 73 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_ACTION_FLAG_TUNNEL_DECAP BIT(7) BIT 86 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_FLOW_FLAGS_ETH_ADDRS BIT(1) BIT 87 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_FLOW_FLAGS_IPV4_ADDRS BIT(2) BIT 88 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_FLOW_FLAGS_IPV6_ADDRS BIT(3) BIT 89 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_FLOW_FLAGS_PORTS BIT(4) BIT 90 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_FLOW_FLAGS_ICMP BIT(5) BIT 91 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_FLOW_FLAGS_TUNL_ETH_ADDRS BIT(6) BIT 92 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_FLOW_FLAGS_TUNL_IPV4_ADDRS BIT(7) BIT 93 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_FLOW_FLAGS_TUNL_IPV6_ADDRS BIT(8) BIT 94 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_FLOW_FLAGS_TUNL_PORTS BIT(9) BIT 95 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.h #define BNXT_TC_FLOW_FLAGS_TUNL_ID BIT(10) BIT 2064 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= BIT(priv->hw_params->bp_in_en_shift); BIT 2649 drivers/net/ethernet/broadcom/genet/bcmgenet.c if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) BIT 2663 drivers/net/ethernet/broadcom/genet/bcmgenet.c if (!(status & BIT(index))) BIT 2765 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= BIT(1); BIT 2769 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~BIT(1); BIT 343 drivers/net/ethernet/broadcom/genet/bcmgenet.h #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4)) BIT 274 drivers/net/ethernet/broadcom/genet/bcmmii.c id_mode_dis = BIT(16); BIT 70 drivers/net/ethernet/brocade/bna/bfa_defs_mfg_comm.h CB_GPIO_PROTO = BIT(7) /*!< 8G 2port FC prototypes */ BIT 18 drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c #define bfa_ioc_ct_sync_pos(__ioc) BIT(bfa_ioc_pcifn(__ioc)) BIT 63 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_TXQ_WI_CF_FCOE_CRC BIT(8) BIT 64 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_TXQ_WI_CF_IPID_MODE BIT(5) BIT 65 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_TXQ_WI_CF_INS_PRIO BIT(4) BIT 66 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_TXQ_WI_CF_INS_VLAN BIT(3) BIT 67 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_TXQ_WI_CF_UDP_CKSUM BIT(2) BIT 68 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_TXQ_WI_CF_TCP_CKSUM BIT(1) BIT 69 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_TXQ_WI_CF_IP_CKSUM BIT(0) BIT 117 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_MAC_ERROR BIT(0) BIT 118 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_FCS_ERROR BIT(1) BIT 119 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_TOO_LONG BIT(2) BIT 120 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_FC_CRC_OK BIT(3) BIT 122 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_RSVD1 BIT(4) BIT 123 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_L4_CKSUM_OK BIT(5) BIT 124 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_L3_CKSUM_OK BIT(6) BIT 125 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_HDS_HEADER BIT(7) BIT 127 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_UDP BIT(8) BIT 128 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_TCP BIT(9) BIT 129 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_IP_OPTIONS BIT(10) BIT 130 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_IPV6 BIT(11) BIT 132 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_IPV4 BIT(12) BIT 133 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_VLAN BIT(13) BIT 134 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_RSS BIT(14) BIT 135 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_RSVD2 BIT(15) BIT 137 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_MCAST_MATCH BIT(16) BIT 138 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_MCAST BIT(17) BIT 139 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_BCAST BIT(18) BIT 140 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_REMOTE BIT(19) BIT 142 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_CQ_EF_LOCAL BIT(20) BIT 667 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_STATS_MAC BIT(0) /* !< MAC Statistics */ BIT 668 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_STATS_BPC BIT(1) /* !< Pause Stats from BPC */ BIT 669 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_STATS_RAD BIT(2) /* !< Rx Admission Statistics */ BIT 670 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_STATS_RX_FC BIT(3) /* !< Rx FC Stats from RxA */ BIT 671 drivers/net/ethernet/brocade/bna/bfi_enet.h #define BFI_ENET_STATS_TX_FC BIT(4) /* !< Tx FC Stats from TxA */ BIT 202 drivers/net/ethernet/brocade/bna/bna_enet.c if (rx_enet_mask & BIT(i)) { BIT 217 drivers/net/ethernet/brocade/bna/bna_enet.c if (tx_enet_mask & BIT(i)) { BIT 208 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_IB_MAX_ACK_EVENTS BIT(15) BIT 277 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_TXQ_WI_CF_FCOE_CRC BIT(8) BIT 278 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_TXQ_WI_CF_IPID_MODE BIT(5) BIT 279 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_TXQ_WI_CF_INS_PRIO BIT(4) BIT 280 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_TXQ_WI_CF_INS_VLAN BIT(3) BIT 281 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_TXQ_WI_CF_UDP_CKSUM BIT(2) BIT 282 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_TXQ_WI_CF_TCP_CKSUM BIT(1) BIT 283 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_TXQ_WI_CF_IP_CKSUM BIT(0) BIT 292 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_MAC_ERROR BIT(0) BIT 293 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_FCS_ERROR BIT(1) BIT 294 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_TOO_LONG BIT(2) BIT 295 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_FC_CRC_OK BIT(3) BIT 297 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_RSVD1 BIT(4) BIT 298 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_L4_CKSUM_OK BIT(5) BIT 299 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_L3_CKSUM_OK BIT(6) BIT 300 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_HDS_HEADER BIT(7) BIT 302 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_UDP BIT(8) BIT 303 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_TCP BIT(9) BIT 304 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_IP_OPTIONS BIT(10) BIT 305 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_IPV6 BIT(11) BIT 307 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_IPV4 BIT(12) BIT 308 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_VLAN BIT(13) BIT 309 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_RSS BIT(14) BIT 310 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_RSVD2 BIT(15) BIT 312 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_MCAST_MATCH BIT(16) BIT 313 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_MCAST BIT(17) BIT 314 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_BCAST BIT(18) BIT 315 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_REMOTE BIT(19) BIT 317 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_LOCAL BIT(20) BIT 321 drivers/net/ethernet/brocade/bna/bna_hw_defs.h #define BNA_CQ_EF_EOP BIT(31) BIT 458 drivers/net/ethernet/brocade/bna/bna_tx_rx.c rxf->vlan_pending_bitmask &= ~BIT(block_idx); BIT 928 drivers/net/ethernet/brocade/bna/bna_tx_rx.c int bit = BIT(vlan_id & BFI_VLAN_WORD_MASK); BIT 933 drivers/net/ethernet/brocade/bna/bna_tx_rx.c rxf->vlan_pending_bitmask |= BIT(group_id); BIT 943 drivers/net/ethernet/brocade/bna/bna_tx_rx.c int bit = BIT(vlan_id & BFI_VLAN_WORD_MASK); BIT 948 drivers/net/ethernet/brocade/bna/bna_tx_rx.c rxf->vlan_pending_bitmask |= BIT(group_id); BIT 2370 drivers/net/ethernet/brocade/bna/bna_tx_rx.c rxp->cq.ib.intr_vector = BIT(rxp->vector); BIT 2477 drivers/net/ethernet/brocade/bna/bna_tx_rx.c rx_mod->rid_mask |= BIT(rx->rid); BIT 2528 drivers/net/ethernet/brocade/bna/bna_tx_rx.c rx_mod->rid_mask &= ~BIT(rx->rid); BIT 3459 drivers/net/ethernet/brocade/bna/bna_tx_rx.c txq->ib.intr_vector = BIT(txq->ib.intr_vector); BIT 3501 drivers/net/ethernet/brocade/bna/bna_tx_rx.c tx_mod->rid_mask |= BIT(tx->rid); BIT 3519 drivers/net/ethernet/brocade/bna/bna_tx_rx.c tx->bna->tx_mod.rid_mask &= ~BIT(tx->rid); BIT 22 drivers/net/ethernet/cavium/common/cavium_ptp.c #define PTP_CLOCK_CFG_PTP_EN BIT(0) BIT 187 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29) BIT 192 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24) BIT 193 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_INPUT_CTL_RST BIT(23) BIT 194 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28) BIT 195 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22) BIT 196 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_INPUT_CTL_DATA_NS BIT(8) BIT 197 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6) BIT 198 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_INPUT_CTL_DATA_RO BIT(5) BIT 199 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4) BIT 200 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_INPUT_CTL_GATHER_NS BIT(3) BIT 314 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_TENB BIT(13) BIT 315 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_CENB BIT(12) BIT 316 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11) BIT 317 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_ES BIT(9) BIT 318 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_NSR BIT(8) BIT 319 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_ROR BIT(7) BIT 320 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6) BIT 321 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5) BIT 322 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3) BIT 323 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2) BIT 324 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1) BIT 325 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0) BIT 431 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_INTR_MBOX_ENB BIT(0) BIT 435 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_INTR_MIO_INT BIT(1) BIT 439 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_INTR_PKT_COUNT BIT(4) BIT 440 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_INTR_PKT_TIME BIT(5) BIT 444 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_INTR_M0UPB0_ERR BIT(8) BIT 445 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_INTR_M0UPWI_ERR BIT(9) BIT 446 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_INTR_M0UNB0_ERR BIT(10) BIT 447 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_INTR_M0UNWI_ERR BIT(11) BIT 580 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_DPI_DMA_O_ADD1 BIT(19) BIT 582 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_DPI_DMA_O_ES BIT(15) BIT 583 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h #define CN23XX_DPI_DMA_O_MODE BIT(14) BIT 87 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29) BIT 92 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24) BIT 93 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_INPUT_CTL_RST BIT(23) BIT 94 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28) BIT 95 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22) BIT 96 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_INPUT_CTL_DATA_NS BIT(8) BIT 97 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6) BIT 98 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_INPUT_CTL_DATA_RO BIT(5) BIT 99 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4) BIT 100 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_INPUT_CTL_GATHER_NS BIT(3) BIT 194 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_TENB BIT(13) BIT 195 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_CENB BIT(12) BIT 196 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11) BIT 197 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_ES BIT(9) BIT 198 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_NSR BIT(8) BIT 199 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_ROR BIT(7) BIT 200 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6) BIT 201 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5) BIT 202 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3) BIT 203 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2) BIT 204 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1) BIT 205 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0) BIT 237 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h #define CN23XX_INTR_MBOX_ENB BIT(0) BIT 162 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INPUT_CTL_ROUND_ROBIN_ARB BIT(22) BIT 163 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INPUT_CTL_DATA_NS BIT(8) BIT 164 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP BIT(6) BIT 165 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INPUT_CTL_DATA_RO BIT(5) BIT 166 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INPUT_CTL_USE_CSR BIT(4) BIT 167 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INPUT_CTL_GATHER_NS BIT(3) BIT 168 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INPUT_CTL_GATHER_ES_64B_SWAP BIT(2) BIT 169 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INPUT_CTL_GATHER_RO BIT(1) BIT 349 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_RML_TIMEOUT_ERR BIT(1) BIT 350 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_BAR0_RW_TIMEOUT_ERR BIT(2) BIT 351 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_IO2BIG_ERR BIT(3) BIT 352 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_PKT_COUNT BIT(4) BIT 353 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_PKT_TIME BIT(5) BIT 354 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_M0UPB0_ERR BIT(8) BIT 355 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_M0UPWI_ERR BIT(9) BIT 356 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_M0UNB0_ERR BIT(10) BIT 357 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_M0UNWI_ERR BIT(11) BIT 358 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_M1UPB0_ERR BIT(12) BIT 359 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_M1UPWI_ERR BIT(13) BIT 360 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_M1UNB0_ERR BIT(14) BIT 361 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_M1UNWI_ERR BIT(15) BIT 362 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_MIO_INT0 BIT(16) BIT 363 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_MIO_INT1 BIT(17) BIT 364 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_MAC_INT0 BIT(18) BIT 365 drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h #define CN6XXX_INTR_MAC_INT1 BIT(19) BIT 455 drivers/net/ethernet/cavium/liquidio/octeon_config.h #define DISPATCH_LIST_SIZE BIT(OPCODE_MASK_BITS) BIT 43 drivers/net/ethernet/cavium/thunder/nic.h #define NIC_SRIOV_ENABLED BIT(0) BIT 75 drivers/net/ethernet/cavium/thunder/nic.h #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) BIT 76 drivers/net/ethernet/cavium/thunder/nic.h #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) BIT 77 drivers/net/ethernet/cavium/thunder/nic.h #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) BIT 78 drivers/net/ethernet/cavium/thunder/nic.h #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) BIT 133 drivers/net/ethernet/cavium/thunder/nic.h #define RSS_L2_EXTENDED_HASH_ENA BIT(0) BIT 134 drivers/net/ethernet/cavium/thunder/nic.h #define RSS_IP_HASH_ENA BIT(1) BIT 135 drivers/net/ethernet/cavium/thunder/nic.h #define RSS_TCP_HASH_ENA BIT(2) BIT 136 drivers/net/ethernet/cavium/thunder/nic.h #define RSS_TCP_SYN_DIS BIT(3) BIT 137 drivers/net/ethernet/cavium/thunder/nic.h #define RSS_UDP_HASH_ENA BIT(4) BIT 138 drivers/net/ethernet/cavium/thunder/nic.h #define RSS_L4_EXTENDED_HASH_ENA BIT(5) BIT 139 drivers/net/ethernet/cavium/thunder/nic.h #define RSS_ROCE_ENA BIT(6) BIT 140 drivers/net/ethernet/cavium/thunder/nic.h #define RSS_L3_BI_DIRECTION_ENA BIT(7) BIT 141 drivers/net/ethernet/cavium/thunder/nic.h #define RSS_L4_BI_DIRECTION_ENA BIT(8) BIT 792 drivers/net/ethernet/cavium/thunder/nic_main.c if (cfg->rx_stat_mask & BIT(i)) { BIT 801 drivers/net/ethernet/cavium/thunder/nic_main.c if (cfg->tx_stat_mask & BIT(i)) { BIT 814 drivers/net/ethernet/cavium/thunder/nic_main.c if (cfg->rq_stat_mask & BIT(i)) { BIT 818 drivers/net/ethernet/cavium/thunder/nic_main.c if (cfg->sq_stat_mask & BIT(i)) { BIT 805 drivers/net/ethernet/cavium/thunder/nicvf_queues.c (BIT(24) | BIT(23) | BIT(21) | BIT(20))); BIT 313 drivers/net/ethernet/cavium/thunder/nicvf_queues.h #define CQ_WR_FULL BIT(26) BIT 314 drivers/net/ethernet/cavium/thunder/nicvf_queues.h #define CQ_WR_DISABLE BIT(25) BIT 315 drivers/net/ethernet/cavium/thunder/nicvf_queues.h #define CQ_WR_FAULT BIT(24) BIT 32 drivers/net/ethernet/cavium/thunder/thunder_bgx.c #define BCAST_ACCEPT BIT(0) BIT 33 drivers/net/ethernet/cavium/thunder/thunder_bgx.c #define CAM_ACCEPT BIT(3) BIT 212 drivers/net/ethernet/cavium/thunder/thunder_bgx.h #define LMAC_INTR_LINK_UP BIT(0) BIT 213 drivers/net/ethernet/cavium/thunder/thunder_bgx.h #define LMAC_INTR_LINK_DOWN BIT(1) BIT 215 drivers/net/ethernet/cavium/thunder/thunder_bgx.h #define BGX_XCAST_BCAST_ACCEPT BIT(0) BIT 216 drivers/net/ethernet/cavium/thunder/thunder_bgx.h #define BGX_XCAST_MCAST_ACCEPT BIT(1) BIT 217 drivers/net/ethernet/cavium/thunder/thunder_bgx.h #define BGX_XCAST_MCAST_FILTER BIT(2) BIT 556 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) BIT 634 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c field_desc_show(seq, p[1], (p[0] & BIT(17)) ? tp_la2 : tp_la1); BIT 235 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | BIT 236 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c BIT(FLOW_DISSECTOR_KEY_BASIC) | BIT 237 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | BIT 238 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | BIT 239 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c BIT(FLOW_DISSECTOR_KEY_PORTS) | BIT 240 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) | BIT 241 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c BIT(FLOW_DISSECTOR_KEY_VLAN) | BIT 242 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c BIT(FLOW_DISSECTOR_KEY_IP))) { BIT 1418 drivers/net/ethernet/cisco/enic/enic_main.c (rss_hash & BIT(0))) { BIT 1420 drivers/net/ethernet/cisco/enic/enic_main.c outer_csum_ok = (rss_hash & BIT(1)) && BIT 1421 drivers/net/ethernet/cisco/enic/enic_main.c (rss_hash & BIT(2)); BIT 719 drivers/net/ethernet/cisco/enic/vnic_devcmd.h #define ENIC_VXLAN_INNER_IPV6 BIT(0) BIT 720 drivers/net/ethernet/cisco/enic/vnic_devcmd.h #define ENIC_VXLAN_OUTER_IPV6 BIT(1) BIT 721 drivers/net/ethernet/cisco/enic/vnic_devcmd.h #define ENIC_VXLAN_MULTI_WQ BIT(2) BIT 63 drivers/net/ethernet/cortina/gemini.c #define HPROT_DATA_CACHE BIT(0) BIT 64 drivers/net/ethernet/cortina/gemini.c #define HPROT_PRIVILIGED BIT(1) BIT 65 drivers/net/ethernet/cortina/gemini.c #define HPROT_BUFFERABLE BIT(2) BIT 66 drivers/net/ethernet/cortina/gemini.c #define HPROT_CACHABLE BIT(3) BIT 200 drivers/net/ethernet/cortina/gemini.h #define GMAC1_TXDERR_INT_BIT BIT(31) BIT 201 drivers/net/ethernet/cortina/gemini.h #define GMAC1_TXPERR_INT_BIT BIT(30) BIT 202 drivers/net/ethernet/cortina/gemini.h #define GMAC0_TXDERR_INT_BIT BIT(29) BIT 203 drivers/net/ethernet/cortina/gemini.h #define GMAC0_TXPERR_INT_BIT BIT(28) BIT 204 drivers/net/ethernet/cortina/gemini.h #define GMAC1_RXDERR_INT_BIT BIT(27) BIT 205 drivers/net/ethernet/cortina/gemini.h #define GMAC1_RXPERR_INT_BIT BIT(26) BIT 206 drivers/net/ethernet/cortina/gemini.h #define GMAC0_RXDERR_INT_BIT BIT(25) BIT 207 drivers/net/ethernet/cortina/gemini.h #define GMAC0_RXPERR_INT_BIT BIT(24) BIT 208 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ15_FIN_INT_BIT BIT(23) BIT 209 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ14_FIN_INT_BIT BIT(22) BIT 210 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ13_FIN_INT_BIT BIT(21) BIT 211 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ12_FIN_INT_BIT BIT(20) BIT 212 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ11_FIN_INT_BIT BIT(19) BIT 213 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ10_FIN_INT_BIT BIT(18) BIT 214 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ05_FIN_INT_BIT BIT(17) BIT 215 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ04_FIN_INT_BIT BIT(16) BIT 216 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ03_FIN_INT_BIT BIT(15) BIT 217 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ02_FIN_INT_BIT BIT(14) BIT 218 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ01_FIN_INT_BIT BIT(13) BIT 219 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ00_FIN_INT_BIT BIT(12) BIT 220 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ15_EOF_INT_BIT BIT(11) BIT 221 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ14_EOF_INT_BIT BIT(10) BIT 222 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ13_EOF_INT_BIT BIT(9) BIT 223 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ12_EOF_INT_BIT BIT(8) BIT 224 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ11_EOF_INT_BIT BIT(7) BIT 225 drivers/net/ethernet/cortina/gemini.h #define GMAC1_SWTQ10_EOF_INT_BIT BIT(6) BIT 226 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ05_EOF_INT_BIT BIT(5) BIT 227 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ04_EOF_INT_BIT BIT(4) BIT 228 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ03_EOF_INT_BIT BIT(3) BIT 229 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ02_EOF_INT_BIT BIT(2) BIT 230 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ01_EOF_INT_BIT BIT(1) BIT 231 drivers/net/ethernet/cortina/gemini.h #define GMAC0_SWTQ00_EOF_INT_BIT BIT(0) BIT 237 drivers/net/ethernet/cortina/gemini.h #define TOE_IQ3_FULL_INT_BIT BIT(31) BIT 238 drivers/net/ethernet/cortina/gemini.h #define TOE_IQ2_FULL_INT_BIT BIT(30) BIT 239 drivers/net/ethernet/cortina/gemini.h #define TOE_IQ1_FULL_INT_BIT BIT(29) BIT 240 drivers/net/ethernet/cortina/gemini.h #define TOE_IQ0_FULL_INT_BIT BIT(28) BIT 241 drivers/net/ethernet/cortina/gemini.h #define TOE_IQ3_INT_BIT BIT(27) BIT 242 drivers/net/ethernet/cortina/gemini.h #define TOE_IQ2_INT_BIT BIT(26) BIT 243 drivers/net/ethernet/cortina/gemini.h #define TOE_IQ1_INT_BIT BIT(25) BIT 244 drivers/net/ethernet/cortina/gemini.h #define TOE_IQ0_INT_BIT BIT(24) BIT 245 drivers/net/ethernet/cortina/gemini.h #define GMAC1_HWTQ13_EOF_INT_BIT BIT(23) BIT 246 drivers/net/ethernet/cortina/gemini.h #define GMAC1_HWTQ12_EOF_INT_BIT BIT(22) BIT 247 drivers/net/ethernet/cortina/gemini.h #define GMAC1_HWTQ11_EOF_INT_BIT BIT(21) BIT 248 drivers/net/ethernet/cortina/gemini.h #define GMAC1_HWTQ10_EOF_INT_BIT BIT(20) BIT 249 drivers/net/ethernet/cortina/gemini.h #define GMAC0_HWTQ03_EOF_INT_BIT BIT(19) BIT 250 drivers/net/ethernet/cortina/gemini.h #define GMAC0_HWTQ02_EOF_INT_BIT BIT(18) BIT 251 drivers/net/ethernet/cortina/gemini.h #define GMAC0_HWTQ01_EOF_INT_BIT BIT(17) BIT 252 drivers/net/ethernet/cortina/gemini.h #define GMAC0_HWTQ00_EOF_INT_BIT BIT(16) BIT 253 drivers/net/ethernet/cortina/gemini.h #define CLASS_RX_INT_BIT(x) BIT((x + 2)) BIT 254 drivers/net/ethernet/cortina/gemini.h #define DEFAULT_Q1_INT_BIT BIT(1) BIT 255 drivers/net/ethernet/cortina/gemini.h #define DEFAULT_Q0_INT_BIT BIT(0) BIT 268 drivers/net/ethernet/cortina/gemini.h #define TOE_QL_FULL_INT_BIT(x) BIT(x) BIT 274 drivers/net/ethernet/cortina/gemini.h #define TOE_QH_FULL_INT_BIT(x) BIT(x - 32) BIT 280 drivers/net/ethernet/cortina/gemini.h #define GMAC1_RESERVED_INT_BIT BIT(31) BIT 281 drivers/net/ethernet/cortina/gemini.h #define GMAC1_MIB_INT_BIT BIT(30) BIT 282 drivers/net/ethernet/cortina/gemini.h #define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29) BIT 283 drivers/net/ethernet/cortina/gemini.h #define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28) BIT 284 drivers/net/ethernet/cortina/gemini.h #define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27) BIT 285 drivers/net/ethernet/cortina/gemini.h #define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26) BIT 286 drivers/net/ethernet/cortina/gemini.h #define GMAC1_RX_OVERRUN_INT_BIT BIT(25) BIT 287 drivers/net/ethernet/cortina/gemini.h #define GMAC1_STATUS_CHANGE_INT_BIT BIT(24) BIT 288 drivers/net/ethernet/cortina/gemini.h #define GMAC0_RESERVED_INT_BIT BIT(23) BIT 289 drivers/net/ethernet/cortina/gemini.h #define GMAC0_MIB_INT_BIT BIT(22) BIT 290 drivers/net/ethernet/cortina/gemini.h #define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21) BIT 291 drivers/net/ethernet/cortina/gemini.h #define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20) BIT 292 drivers/net/ethernet/cortina/gemini.h #define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19) BIT 293 drivers/net/ethernet/cortina/gemini.h #define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18) BIT 294 drivers/net/ethernet/cortina/gemini.h #define GMAC0_RX_OVERRUN_INT_BIT BIT(17) BIT 295 drivers/net/ethernet/cortina/gemini.h #define GMAC0_STATUS_CHANGE_INT_BIT BIT(16) BIT 296 drivers/net/ethernet/cortina/gemini.h #define CLASS_RX_FULL_INT_BIT(x) BIT(x + 2) BIT 297 drivers/net/ethernet/cortina/gemini.h #define HWFQ_EMPTY_INT_BIT BIT(1) BIT 298 drivers/net/ethernet/cortina/gemini.h #define SWFQ_EMPTY_INT_BIT BIT(0) BIT 462 drivers/net/ethernet/cortina/gemini.h #define TSS_IP_FIXED_LEN_BIT BIT(22) BIT 463 drivers/net/ethernet/cortina/gemini.h #define TSS_BYPASS_BIT BIT(21) BIT 464 drivers/net/ethernet/cortina/gemini.h #define TSS_UDP_CHKSUM_BIT BIT(20) BIT 465 drivers/net/ethernet/cortina/gemini.h #define TSS_TCP_CHKSUM_BIT BIT(19) BIT 466 drivers/net/ethernet/cortina/gemini.h #define TSS_IPV6_ENABLE_BIT BIT(18) BIT 467 drivers/net/ethernet/cortina/gemini.h #define TSS_IP_CHKSUM_BIT BIT(17) BIT 468 drivers/net/ethernet/cortina/gemini.h #define TSS_MTU_ENABLE_BIT BIT(16) BIT 504 drivers/net/ethernet/cortina/gemini.h #define EOFIE_BIT BIT(29) BIT 539 drivers/net/ethernet/cortina/gemini.h #define GMAC_RXDESC_0_T_derr BIT(30) BIT 540 drivers/net/ethernet/cortina/gemini.h #define GMAC_RXDESC_0_T_perr BIT(29) BIT 541 drivers/net/ethernet/cortina/gemini.h #define GMAC_RXDESC_0_T_chksum_status(x) BIT(x + 26) BIT 542 drivers/net/ethernet/cortina/gemini.h #define GMAC_RXDESC_0_T_status(x) BIT(x + 22) BIT 543 drivers/net/ethernet/cortina/gemini.h #define GMAC_RXDESC_0_T_desc_count(x) BIT(x + 16) BIT 651 drivers/net/ethernet/cortina/gemini.h #define MR_L2_BIT BIT(31) BIT 652 drivers/net/ethernet/cortina/gemini.h #define MR_L3_BIT BIT(30) BIT 653 drivers/net/ethernet/cortina/gemini.h #define MR_L4_BIT BIT(29) BIT 654 drivers/net/ethernet/cortina/gemini.h #define MR_L7_BIT BIT(28) BIT 655 drivers/net/ethernet/cortina/gemini.h #define MR_PORT_BIT BIT(27) BIT 656 drivers/net/ethernet/cortina/gemini.h #define MR_PRIORITY_BIT BIT(26) BIT 657 drivers/net/ethernet/cortina/gemini.h #define MR_DA_BIT BIT(23) BIT 658 drivers/net/ethernet/cortina/gemini.h #define MR_SA_BIT BIT(22) BIT 659 drivers/net/ethernet/cortina/gemini.h #define MR_ETHER_TYPE_BIT BIT(21) BIT 660 drivers/net/ethernet/cortina/gemini.h #define MR_VLAN_BIT BIT(20) BIT 661 drivers/net/ethernet/cortina/gemini.h #define MR_PPPOE_BIT BIT(19) BIT 662 drivers/net/ethernet/cortina/gemini.h #define MR_IP_VER_BIT BIT(15) BIT 663 drivers/net/ethernet/cortina/gemini.h #define MR_IP_HDR_LEN_BIT BIT(14) BIT 664 drivers/net/ethernet/cortina/gemini.h #define MR_FLOW_LABLE_BIT BIT(13) BIT 665 drivers/net/ethernet/cortina/gemini.h #define MR_TOS_TRAFFIC_BIT BIT(12) BIT 666 drivers/net/ethernet/cortina/gemini.h #define MR_SPR_BIT(x) BIT(x) BIT 778 drivers/net/ethernet/cortina/gemini.h #define CONFIG0_TX_RX_DISABLE (BIT(1) | BIT(0)) BIT 779 drivers/net/ethernet/cortina/gemini.h #define CONFIG0_RX_CHKSUM (BIT(18) | BIT(17)) BIT 780 drivers/net/ethernet/cortina/gemini.h #define CONFIG0_FLOW_RX BIT(14) BIT 781 drivers/net/ethernet/cortina/gemini.h #define CONFIG0_FLOW_TX BIT(15) BIT 782 drivers/net/ethernet/cortina/gemini.h #define CONFIG0_FLOW_TX_RX (BIT(14) | BIT(15)) BIT 783 drivers/net/ethernet/cortina/gemini.h #define CONFIG0_FLOW_CTL (BIT(14) | BIT(15)) BIT 211 drivers/net/ethernet/dlink/dl2k.h #define IPG_AC_LED_MODE BIT(14) BIT 212 drivers/net/ethernet/dlink/dl2k.h #define IPG_AC_LED_SPEED BIT(27) BIT 213 drivers/net/ethernet/dlink/dl2k.h #define IPG_AC_LED_MODE_BIT_1 BIT(29) BIT 362 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_LINK_STATUS_INIT BIT(1) BIT 363 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_SRIOV_ENABLED BIT(2) BIT 364 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_WORKER_SCHEDULED BIT(3) BIT 365 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_NAPI_ENABLED BIT(6) BIT 366 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) BIT 367 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_VXLAN_OFFLOADS BIT(8) BIT 368 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_SETUP_DONE BIT(9) BIT 369 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_PHY_MISCONFIGURED BIT(10) BIT 370 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11) BIT 371 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_OS2BMC BIT(12) BIT 372 drivers/net/ethernet/emulex/benet/be.h #define BE_FLAGS_TRY_RECOVERY BIT(13) BIT 938 drivers/net/ethernet/emulex/benet/be.h #define BE_ERROR_UE BIT(1) BIT 939 drivers/net/ethernet/emulex/benet/be.h #define BE_ERROR_FW BIT(2) BIT 940 drivers/net/ethernet/emulex/benet/be.h #define BE_ERROR_TX BIT(3) BIT 1277 drivers/net/ethernet/emulex/benet/be_cmds.c cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) | BIT 1278 drivers/net/ethernet/emulex/benet/be_cmds.c BIT(ASYNC_EVENT_CODE_GRP_5) | BIT 1279 drivers/net/ethernet/emulex/benet/be_cmds.c BIT(ASYNC_EVENT_CODE_QNQ) | BIT 1280 drivers/net/ethernet/emulex/benet/be_cmds.c BIT(ASYNC_EVENT_CODE_SLIPORT)); BIT 4263 drivers/net/ethernet/emulex/benet/be_cmds.c (!get_vft || nic->flags & BIT(VFT_SHIFT))) BIT 4641 drivers/net/ethernet/emulex/benet/be_cmds.c desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT); BIT 4650 drivers/net/ethernet/emulex/benet/be_cmds.c desc.nic_vft.flags = vft_res->flags | BIT(VFT_SHIFT) | BIT 4651 drivers/net/ethernet/emulex/benet/be_cmds.c BIT(IMM_SHIFT) | BIT(NOSV_SHIFT); BIT 43 drivers/net/ethernet/emulex/benet/be_cmds.h #define CQE_FLAGS_VALID_MASK BIT(31) BIT 44 drivers/net/ethernet/emulex/benet/be_cmds.h #define CQE_FLAGS_ASYNC_MASK BIT(30) BIT 45 drivers/net/ethernet/emulex/benet/be_cmds.h #define CQE_FLAGS_COMPLETED_MASK BIT(28) BIT 46 drivers/net/ethernet/emulex/benet/be_cmds.h #define CQE_FLAGS_CONSUMED_MASK BIT(27) BIT 228 drivers/net/ethernet/emulex/benet/be_cmds.h #define BMC_FILT_BROADCAST_ARP BIT(0) BIT 229 drivers/net/ethernet/emulex/benet/be_cmds.h #define BMC_FILT_BROADCAST_DHCP_CLIENT BIT(1) BIT 230 drivers/net/ethernet/emulex/benet/be_cmds.h #define BMC_FILT_BROADCAST_DHCP_SERVER BIT(2) BIT 231 drivers/net/ethernet/emulex/benet/be_cmds.h #define BMC_FILT_BROADCAST_NET_BIOS BIT(3) BIT 232 drivers/net/ethernet/emulex/benet/be_cmds.h #define BMC_FILT_BROADCAST BIT(7) BIT 233 drivers/net/ethernet/emulex/benet/be_cmds.h #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER BIT(8) BIT 234 drivers/net/ethernet/emulex/benet/be_cmds.h #define BMC_FILT_MULTICAST_IPV6_RA BIT(9) BIT 235 drivers/net/ethernet/emulex/benet/be_cmds.h #define BMC_FILT_MULTICAST_IPV6_RAS BIT(10) BIT 236 drivers/net/ethernet/emulex/benet/be_cmds.h #define BMC_FILT_MULTICAST BIT(15) BIT 2255 drivers/net/ethernet/emulex/benet/be_cmds.h #define QUERY_MODIFIABLE_FIELDS_TYPE BIT(3) BIT 2356 drivers/net/ethernet/emulex/benet/be_cmds.h #define PLINK_ENABLE BIT(0) BIT 2357 drivers/net/ethernet/emulex/benet/be_cmds.h #define PLINK_TRACK BIT(8) BIT 82 drivers/net/ethernet/emulex/benet/be_hw.h #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK BIT(29) /* bit 29 */ BIT 243 drivers/net/ethernet/emulex/benet/be_hw.h #define TX_HDR_WRB_EVT BIT(1) /* word 2 */ BIT 4060 drivers/net/ethernet/emulex/benet/be_main.c vft_res->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT); BIT 4074 drivers/net/ethernet/emulex/benet/be_main.c vft_res->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT); BIT 1807 drivers/net/ethernet/faraday/ftgmac100.c priv->rxdes0_edorr_mask = BIT(30); BIT 1808 drivers/net/ethernet/faraday/ftgmac100.c priv->txdes0_edotr_mask = BIT(30); BIT 1811 drivers/net/ethernet/faraday/ftgmac100.c priv->rxdes0_edorr_mask = BIT(15); BIT 1812 drivers/net/ethernet/faraday/ftgmac100.c priv->txdes0_edotr_mask = BIT(15); BIT 140 drivers/net/ethernet/faraday/ftgmac100.h #define FTGMAC100_REVR_NEW_MDIO_INTERFACE BIT(31) BIT 470 drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h #define DPAA2_ETH_DIST_ETHDST BIT(0) BIT 471 drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h #define DPAA2_ETH_DIST_ETHSRC BIT(1) BIT 472 drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h #define DPAA2_ETH_DIST_ETHTYPE BIT(2) BIT 473 drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h #define DPAA2_ETH_DIST_VLAN BIT(3) BIT 474 drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h #define DPAA2_ETH_DIST_IPSRC BIT(4) BIT 475 drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h #define DPAA2_ETH_DIST_IPDST BIT(5) BIT 476 drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h #define DPAA2_ETH_DIST_IPPROTO BIT(6) BIT 477 drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h #define DPAA2_ETH_DIST_L4SRC BIT(7) BIT 478 drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h #define DPAA2_ETH_DIST_L4DST BIT(8) BIT 63 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ETH_DA BIT(0) BIT 64 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ETH_SA BIT(1) BIT 65 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ETH_LENGTH BIT(2) BIT 66 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ETH_TYPE BIT(3) BIT 67 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ETH_FINAL_CKSUM BIT(4) BIT 68 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ETH_PADDING BIT(5) BIT 69 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ETH_ALL_FIELDS (BIT(6) - 1) BIT 72 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_VLAN_VPRI BIT(0) BIT 73 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_VLAN_CFI BIT(1) BIT 74 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_VLAN_VID BIT(2) BIT 75 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_VLAN_LENGTH BIT(3) BIT 76 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_VLAN_TYPE BIT(4) BIT 77 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_VLAN_ALL_FIELDS (BIT(5) - 1) BIT 84 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IP_VER BIT(0) BIT 85 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IP_DSCP BIT(2) BIT 86 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IP_ECN BIT(3) BIT 87 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IP_PROTO BIT(4) BIT 88 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IP_SRC BIT(5) BIT 89 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IP_DST BIT(6) BIT 90 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IP_TOS_TC BIT(7) BIT 91 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IP_ID BIT(8) BIT 92 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IP_ALL_FIELDS (BIT(9) - 1) BIT 95 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_VER BIT(0) BIT 96 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_HDR_LEN BIT(1) BIT 97 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_TOS BIT(2) BIT 98 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_TOTAL_LEN BIT(3) BIT 99 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_ID BIT(4) BIT 100 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_FLAG_D BIT(5) BIT 101 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_FLAG_M BIT(6) BIT 102 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_OFFSET BIT(7) BIT 103 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_TTL BIT(8) BIT 104 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_PROTO BIT(9) BIT 105 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_CKSUM BIT(10) BIT 106 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_SRC_IP BIT(11) BIT 107 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_DST_IP BIT(12) BIT 108 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_OPTS BIT(13) BIT 109 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_OPTS_COUNT BIT(14) BIT 110 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV4_ALL_FIELDS (BIT(15) - 1) BIT 113 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV6_VER BIT(0) BIT 114 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV6_TC BIT(1) BIT 115 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV6_SRC_IP BIT(2) BIT 116 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV6_DST_IP BIT(3) BIT 117 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV6_NEXT_HDR BIT(4) BIT 118 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV6_FL BIT(5) BIT 119 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV6_HOP_LIMIT BIT(6) BIT 120 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV6_ID BIT(7) BIT 121 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPV6_ALL_FIELDS (BIT(8) - 1) BIT 124 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ICMP_TYPE BIT(0) BIT 125 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ICMP_CODE BIT(1) BIT 126 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ICMP_CKSUM BIT(2) BIT 127 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ICMP_ID BIT(3) BIT 128 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ICMP_SQ_NUM BIT(4) BIT 129 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ICMP_ALL_FIELDS (BIT(5) - 1) BIT 132 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IGMP_VERSION BIT(0) BIT 133 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IGMP_TYPE BIT(1) BIT 134 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IGMP_CKSUM BIT(2) BIT 135 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IGMP_DATA BIT(3) BIT 136 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IGMP_ALL_FIELDS (BIT(4) - 1) BIT 139 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_PORT_SRC BIT(0) BIT 140 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_PORT_DST BIT(1) BIT 141 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_SEQ BIT(2) BIT 142 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_ACK BIT(3) BIT 143 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_OFFSET BIT(4) BIT 144 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_FLAGS BIT(5) BIT 145 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_WINDOW BIT(6) BIT 146 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_CKSUM BIT(7) BIT 147 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_URGPTR BIT(8) BIT 148 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_OPTS BIT(9) BIT 149 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_OPTS_COUNT BIT(10) BIT 150 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_TCP_ALL_FIELDS (BIT(11) - 1) BIT 153 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_PORT_SRC BIT(0) BIT 154 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_PORT_DST BIT(1) BIT 155 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_LEN BIT(2) BIT 156 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_CKSUM BIT(3) BIT 157 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_ALL_FIELDS (BIT(4) - 1) BIT 160 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_LITE_PORT_SRC BIT(0) BIT 161 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_LITE_PORT_DST BIT(1) BIT 162 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_LITE_ALL_FIELDS (BIT(2) - 1) BIT 165 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_ENC_ESP_PORT_SRC BIT(0) BIT 166 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_ENC_ESP_PORT_DST BIT(1) BIT 167 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_ENC_ESP_LEN BIT(2) BIT 168 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_ENC_ESP_CKSUM BIT(3) BIT 169 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_ENC_ESP_SPI BIT(4) BIT 170 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_ENC_ESP_SEQUENCE_NUM BIT(5) BIT 171 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_UDP_ENC_ESP_ALL_FIELDS (BIT(6) - 1) BIT 174 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_PORT_SRC BIT(0) BIT 175 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_PORT_DST BIT(1) BIT 176 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_VER_TAG BIT(2) BIT 177 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CKSUM BIT(3) BIT 178 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_ALL_FIELDS (BIT(4) - 1) BIT 181 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_DCCP_PORT_SRC BIT(0) BIT 182 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_DCCP_PORT_DST BIT(1) BIT 183 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_DCCP_ALL_FIELDS (BIT(2) - 1) BIT 186 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPHC_CID BIT(0) BIT 187 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPHC_CID_TYPE BIT(1) BIT 188 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPHC_HCINDEX BIT(2) BIT 189 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPHC_GEN BIT(3) BIT 190 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPHC_D_BIT BIT(4) BIT 191 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPHC_ALL_FIELDS (BIT(5) - 1) BIT 194 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_TYPE BIT(0) BIT 195 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_FLAGS BIT(1) BIT 196 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_LENGTH BIT(2) BIT 197 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_TSN BIT(3) BIT 198 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_STREAM_ID BIT(4) BIT 199 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_STREAM_SQN BIT(5) BIT 200 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_PAYLOAD_PID BIT(6) BIT 201 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_UNORDERED BIT(7) BIT 202 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_BEGGINING BIT(8) BIT 203 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_END BIT(9) BIT 204 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SCTP_CHUNK_DATA_ALL_FIELDS (BIT(10) - 1) BIT 207 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_TYPE_BIT BIT(0) BIT 208 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_LENGTH_BIT BIT(1) BIT 209 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_SEQUENCE_BIT BIT(2) BIT 210 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_OFFSET_BIT BIT(3) BIT 211 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_PRIORITY_BIT BIT(4) BIT 212 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_VERSION BIT(5) BIT 213 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_LEN BIT(6) BIT 214 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_TUNNEL_ID BIT(7) BIT 215 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_SESSION_ID BIT(8) BIT 216 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_NS BIT(9) BIT 217 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_NR BIT(10) BIT 218 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_OFFSET_SIZE BIT(11) BIT 219 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_FIRST_BYTE BIT(12) BIT 220 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV2_ALL_FIELDS (BIT(13) - 1) BIT 223 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_CTRL_TYPE_BIT BIT(0) BIT 224 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_CTRL_LENGTH_BIT BIT(1) BIT 225 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_CTRL_SEQUENCE_BIT BIT(2) BIT 226 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_CTRL_VERSION BIT(3) BIT 227 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_CTRL_LENGTH BIT(4) BIT 228 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_CTRL_CONTROL BIT(5) BIT 229 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_CTRL_SENT BIT(6) BIT 230 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_CTRL_RECV BIT(7) BIT 231 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_CTRL_FIRST_BYTE BIT(8) BIT 232 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_CTRL_ALL_FIELDS (BIT(9) - 1) BIT 234 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_SESS_TYPE_BIT BIT(0) BIT 235 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_SESS_VERSION BIT(1) BIT 236 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_SESS_ID BIT(2) BIT 237 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_SESS_COOKIE BIT(3) BIT 238 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_L2TPV3_SESS_ALL_FIELDS (BIT(4) - 1) BIT 241 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPP_PID BIT(0) BIT 242 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPP_COMPRESSED BIT(1) BIT 243 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPP_ALL_FIELDS (BIT(2) - 1) BIT 246 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPOE_VER BIT(0) BIT 247 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPOE_TYPE BIT(1) BIT 248 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPOE_CODE BIT(2) BIT 249 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPOE_SID BIT(3) BIT 250 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPOE_LEN BIT(4) BIT 251 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPOE_SESSION BIT(5) BIT 252 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPOE_PID BIT(6) BIT 253 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPOE_ALL_FIELDS (BIT(7) - 1) BIT 256 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPMUX_PID BIT(0) BIT 257 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPMUX_CKSUM BIT(1) BIT 258 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPMUX_COMPRESSED BIT(2) BIT 259 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPMUX_ALL_FIELDS (BIT(3) - 1) BIT 262 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPMUX_SUBFRM_PFF BIT(0) BIT 263 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPMUX_SUBFRM_LXT BIT(1) BIT 264 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPMUX_SUBFRM_LEN BIT(2) BIT 265 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPMUX_SUBFRM_PID BIT(3) BIT 266 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPMUX_SUBFRM_USE_PID BIT(4) BIT 267 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PPPMUX_SUBFRM_ALL_FIELDS (BIT(5) - 1) BIT 270 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_LLC_DSAP BIT(0) BIT 271 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_LLC_SSAP BIT(1) BIT 272 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_LLC_CTRL BIT(2) BIT 273 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_LLC_ALL_FIELDS (BIT(3) - 1) BIT 276 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_NLPID_NLPID BIT(0) BIT 277 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_NLPID_ALL_FIELDS (BIT(1) - 1) BIT 280 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SNAP_OUI BIT(0) BIT 281 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SNAP_PID BIT(1) BIT 282 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_SNAP_ALL_FIELDS (BIT(2) - 1) BIT 285 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_LLC_SNAP_TYPE BIT(0) BIT 286 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_LLC_SNAP_ALL_FIELDS (BIT(1) - 1) BIT 289 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ARP_HTYPE BIT(0) BIT 290 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ARP_PTYPE BIT(1) BIT 291 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ARP_HLEN BIT(2) BIT 292 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ARP_PLEN BIT(3) BIT 293 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ARP_OPER BIT(4) BIT 294 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ARP_SHA BIT(5) BIT 295 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ARP_SPA BIT(6) BIT 296 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ARP_THA BIT(7) BIT 297 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ARP_TPA BIT(8) BIT 298 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_ARP_ALL_FIELDS (BIT(9) - 1) BIT 301 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_RFC2684_LLC BIT(0) BIT 302 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_RFC2684_NLPID BIT(1) BIT 303 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_RFC2684_OUI BIT(2) BIT 304 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_RFC2684_PID BIT(3) BIT 305 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_RFC2684_VPN_OUI BIT(4) BIT 306 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_RFC2684_VPN_IDX BIT(5) BIT 307 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_RFC2684_ALL_FIELDS (BIT(6) - 1) BIT 310 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_USER_DEFINED_SRCPORT BIT(0) BIT 311 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_USER_DEFINED_PCDID BIT(1) BIT 312 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_USER_DEFINED_ALL_FIELDS (BIT(2) - 1) BIT 315 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PAYLOAD_BUFFER BIT(0) BIT 316 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PAYLOAD_SIZE BIT(1) BIT 317 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_MAX_FRM_SIZE BIT(2) BIT 318 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_MIN_FRM_SIZE BIT(3) BIT 319 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PAYLOAD_TYPE BIT(4) BIT 320 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_FRAME_SIZE BIT(5) BIT 321 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_PAYLOAD_ALL_FIELDS (BIT(6) - 1) BIT 324 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_GRE_TYPE BIT(0) BIT 325 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_GRE_ALL_FIELDS (BIT(1) - 1) BIT 328 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_MINENCAP_SRC_IP BIT(0) BIT 329 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_MINENCAP_DST_IP BIT(1) BIT 330 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_MINENCAP_TYPE BIT(2) BIT 331 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_MINENCAP_ALL_FIELDS (BIT(3) - 1) BIT 334 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPSEC_AH_SPI BIT(0) BIT 335 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPSEC_AH_NH BIT(1) BIT 336 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPSEC_AH_ALL_FIELDS (BIT(2) - 1) BIT 339 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPSEC_ESP_SPI BIT(0) BIT 340 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPSEC_ESP_SEQUENCE_NUM BIT(1) BIT 341 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_IPSEC_ESP_ALL_FIELDS (BIT(2) - 1) BIT 344 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_MPLS_LABEL_STACK BIT(0) BIT 345 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_MPLS_LABEL_STACK_ALL_FIELDS (BIT(1) - 1) BIT 348 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_MACSEC_SECTAG BIT(0) BIT 349 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_MACSEC_ALL_FIELDS (BIT(1) - 1) BIT 352 drivers/net/ethernet/freescale/dpaa2/dpkg.h #define NH_FLD_GTP_TEID BIT(0) BIT 389 drivers/net/ethernet/freescale/enetc/enetc.c enetc_wr_reg(tx_ring->idr, BIT(tx_ring->index) | BIT 390 drivers/net/ethernet/freescale/enetc/enetc.c BIT(16 + tx_ring->index)); BIT 651 drivers/net/ethernet/freescale/enetc/enetc.c enetc_wr_reg(rx_ring->idr, BIT(rx_ring->index)); BIT 988 drivers/net/ethernet/freescale/enetc/enetc.c enetc_wr(hw, ENETC_SICBDRMR, BIT(31)); BIT 116 drivers/net/ethernet/freescale/enetc/enetc.h ENETC_ERR_TXCSUM = BIT(0), BIT 117 drivers/net/ethernet/freescale/enetc/enetc.h ENETC_ERR_VLAN_ISOL = BIT(1), BIT 118 drivers/net/ethernet/freescale/enetc/enetc.h ENETC_ERR_UCMCSWP = BIT(2), BIT 174 drivers/net/ethernet/freescale/enetc/enetc.h ENETC_F_RX_TSTAMP = BIT(0), BIT 175 drivers/net/ethernet/freescale/enetc/enetc.h ENETC_F_TX_TSTAMP = BIT(1), BIT 102 drivers/net/ethernet/freescale/enetc/enetc_cbdr.c cbd.opt[0] = cpu_to_le32(BIT(31)); BIT 16 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_SIMR_EN BIT(31) BIT 17 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_SIMR_RSSE BIT(0) BIT 21 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_SIPCAPR0_RSS BIT(8) BIT 50 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */ BIT 55 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_VSIMSGSR_MB BIT(0) BIT 56 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_VSIMSGSR_MS BIT(1) BIT 101 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32) BIT 109 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_RBMR_BDS BIT(2) BIT 110 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_RBMR_VTE BIT(5) BIT 111 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_RBMR_EN BIT(31) BIT 120 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_RBIER_RXTIE BIT(0) BIT 123 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_RBICIR0_ICEN BIT(31) BIT 127 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TBSR_BUSY BIT(0) BIT 128 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TBMR_VIH BIT(9) BIT 131 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TBMR_EN BIT(31) BIT 140 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TBIER_TXTIE BIT(0) BIT 143 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TBICIR0_ICEN BIT(31) BIT 153 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */ BIT 154 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16) BIT 162 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_VLAN_TYPE_C BIT(0) BIT 163 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_VLAN_TYPE_S BIT(1) BIT 166 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSIVLAN_EN BIT(31) BIT 176 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSICFGR0_VTE BIT(12) BIT 177 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSICFGR0_SIVIE BIT(14) BIT 178 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSICFGR0_ASE BIT(15) BIT 186 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSIVLANFMR_VS BIT(0) BIT 188 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PRFSMR_RFSE BIT(31) BIT 193 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PFPMR_PMACE BIT(1) BIT 194 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PFPMR_MWLM BIT(0) BIT 202 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_MMCSR_ME BIT(16) BIT 207 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PM0_TX_EN BIT(0) BIT 208 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PM0_RX_EN BIT(1) BIT 209 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PM0_PROMISC BIT(4) BIT 210 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PM0_CMD_XGLP BIT(10) BIT 211 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PM0_CMD_TXP BIT(11) BIT 212 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PM0_CMD_PHY_TX_EN BIT(15) BIT 213 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PM0_CMD_SFD BIT(21) BIT 218 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PMO_IFM_RG BIT(2) BIT 219 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) BIT 220 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1)) BIT 221 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PM0_IFM_XGMII BIT(12) BIT 372 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_FLAGS_L4CS BIT(0) BIT 373 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_FLAGS_W BIT(2) BIT 374 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_FLAGS_CSUM BIT(3) BIT 375 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_FLAGS_EX BIT(6) BIT 376 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_FLAGS_F BIT(7) BIT 384 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_L3_IPCS BIT(7) BIT 385 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_L3_IPV6 BIT(15) BIT 391 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0) BIT 392 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2) BIT 401 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_L4_UDP BIT(5) BIT 402 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_L4_TCP BIT(6) BIT 432 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_RXBD_LSTATUS_R BIT(30) BIT 433 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_RXBD_LSTATUS_F BIT(31) BIT 436 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_RXBD_FLAG_VLAN BIT(9) BIT 437 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_RXBD_FLAG_TSTMP BIT(10) BIT 459 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */ BIT 488 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_RFSE_EN BIT(15) BIT 26 drivers/net/ethernet/freescale/enetc/enetc_mdio.c #define MDIO_CFG_BSY BIT(0) BIT 27 drivers/net/ethernet/freescale/enetc/enetc_mdio.c #define MDIO_CFG_RD_ER BIT(1) BIT 28 drivers/net/ethernet/freescale/enetc/enetc_mdio.c #define MDIO_CFG_ENC45 BIT(6) BIT 30 drivers/net/ethernet/freescale/enetc/enetc_mdio.c #define MDIO_CFG_NEG BIT(23) BIT 34 drivers/net/ethernet/freescale/enetc/enetc_mdio.c #define MDIO_CTL_READ BIT(15) BIT 61 drivers/net/ethernet/freescale/enetc/enetc_pf.c return pf->vlan_promisc_simap & BIT(si_idx); BIT 76 drivers/net/ethernet/freescale/enetc/enetc_pf.c pf->vlan_promisc_simap |= BIT(si_idx); BIT 82 drivers/net/ethernet/freescale/enetc/enetc_pf.c pf->vlan_promisc_simap &= ~BIT(si_idx); BIT 192 drivers/net/ethernet/freescale/enetc/enetc_pf.c BIT(0)); BIT 287 drivers/net/ethernet/freescale/enetc/enetc_pf.c res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i; BIT 23 drivers/net/ethernet/freescale/enetc/enetc_pf.h ENETC_VF_FLAG_PF_SET_MAC = BIT(0), BIT 228 drivers/net/ethernet/freescale/fec_main.c #define FEC_RACC_SHIFT16 BIT(7) BIT 232 drivers/net/ethernet/freescale/fec_main.c #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) BIT 1141 drivers/net/ethernet/freescale/fec_main.c BIT(stop_gpr->bit), BIT 1142 drivers/net/ethernet/freescale/fec_main.c BIT(stop_gpr->bit)); BIT 1145 drivers/net/ethernet/freescale/fec_main.c BIT(stop_gpr->bit), 0); BIT 35 drivers/net/ethernet/freescale/xgmac_mdio.c #define MDIO_STAT_ENC BIT(6) BIT 37 drivers/net/ethernet/freescale/xgmac_mdio.c #define MDIO_STAT_BSY BIT(0) BIT 38 drivers/net/ethernet/freescale/xgmac_mdio.c #define MDIO_STAT_RD_ER BIT(1) BIT 41 drivers/net/ethernet/freescale/xgmac_mdio.c #define MDIO_CTL_PRE_DIS BIT(10) BIT 42 drivers/net/ethernet/freescale/xgmac_mdio.c #define MDIO_CTL_SCAN_EN BIT(11) BIT 43 drivers/net/ethernet/freescale/xgmac_mdio.c #define MDIO_CTL_POST_INC BIT(14) BIT 44 drivers/net/ethernet/freescale/xgmac_mdio.c #define MDIO_CTL_READ BIT(15) BIT 47 drivers/net/ethernet/freescale/xgmac_mdio.c #define MDIO_DATA_BSY BIT(31) BIT 213 drivers/net/ethernet/google/gve/gve.h GVE_PRIV_FLAGS_DO_RESET = BIT(1), BIT 214 drivers/net/ethernet/google/gve/gve.h GVE_PRIV_FLAGS_RESET_IN_PROGRESS = BIT(2), BIT 215 drivers/net/ethernet/google/gve/gve.h GVE_PRIV_FLAGS_PROBE_IN_PROGRESS = BIT(3), BIT 219 drivers/net/ethernet/google/gve/gve.h GVE_PRIV_FLAGS_ADMIN_QUEUE_OK = BIT(1), BIT 220 drivers/net/ethernet/google/gve/gve.h GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK = BIT(2), BIT 221 drivers/net/ethernet/google/gve/gve.h GVE_PRIV_FLAGS_DEVICE_RINGS_OK = BIT(3), BIT 222 drivers/net/ethernet/google/gve/gve.h GVE_PRIV_FLAGS_NAPI_ENABLED = BIT(4), BIT 49 drivers/net/ethernet/google/gve/gve_desc.h #define GVE_TXF_L4CSUM BIT(0) /* Need csum offload */ BIT 50 drivers/net/ethernet/google/gve/gve_desc.h #define GVE_TXF_TSTAMP BIT(2) /* Timestamp required */ BIT 53 drivers/net/ethernet/google/gve/gve_desc.h #define GVE_TXSF_IPV6 BIT(1) /* IPv6 TSO */ BIT 96 drivers/net/ethernet/google/gve/gve_desc.h #define GVE_IRQ_ACK BIT(31) BIT 97 drivers/net/ethernet/google/gve/gve_desc.h #define GVE_IRQ_MASK BIT(30) BIT 98 drivers/net/ethernet/google/gve/gve_desc.h #define GVE_IRQ_EVENT BIT(29) BIT 24 drivers/net/ethernet/google/gve/gve_register.h GVE_DEVICE_STATUS_RESET_MASK = BIT(1), BIT 25 drivers/net/ethernet/google/gve/gve_register.h GVE_DEVICE_STATUS_LINK_STATUS_MASK = BIT(2), BIT 69 drivers/net/ethernet/hisilicon/hip04_eth.c #define RCV_INT BIT(10) BIT 70 drivers/net/ethernet/hisilicon/hip04_eth.c #define RCV_NOBUF BIT(8) BIT 71 drivers/net/ethernet/hisilicon/hip04_eth.c #define RCV_DROP BIT(7) BIT 72 drivers/net/ethernet/hisilicon/hip04_eth.c #define TX_DROP BIT(6) BIT 77 drivers/net/ethernet/hisilicon/hip04_eth.c #define TX_FREE_MEM BIT(0) BIT 78 drivers/net/ethernet/hisilicon/hip04_eth.c #define TX_READ_ALLOC_L3 BIT(1) BIT 80 drivers/net/ethernet/hisilicon/hip04_eth.c #define TX_CLEAR_WB BIT(7) BIT 81 drivers/net/ethernet/hisilicon/hip04_eth.c #define TX_RELEASE_TO_PPE BIT(4) BIT 82 drivers/net/ethernet/hisilicon/hip04_eth.c #define TX_FINISH_CACHE_INV BIT(6) BIT 85 drivers/net/ethernet/hisilicon/hip04_eth.c #define TX_CLEAR_WB BIT(4) BIT 86 drivers/net/ethernet/hisilicon/hip04_eth.c #define TX_FINISH_CACHE_INV BIT(2) BIT 88 drivers/net/ethernet/hisilicon/hip04_eth.c #define TX_L3_CHECKSUM BIT(5) BIT 89 drivers/net/ethernet/hisilicon/hip04_eth.c #define TX_LOOP_BACK BIT(11) BIT 92 drivers/net/ethernet/hisilicon/hip04_eth.c #define RX_PKT_DROP BIT(0) BIT 93 drivers/net/ethernet/hisilicon/hip04_eth.c #define RX_L2_ERR BIT(1) BIT 102 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_DUPLEX_FULL BIT(0) BIT 104 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_MODE_CHANGE_EN BIT(0) BIT 106 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_TX_AUTO_NEG BIT(5) BIT 107 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_TX_ADD_CRC BIT(6) BIT 108 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_TX_SHORT_PAD_THROUGH BIT(7) BIT 110 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_RX_STRIP_CRC BIT(0) BIT 111 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_RX_STRIP_PAD BIT(3) BIT 112 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_RX_PAD_EN BIT(4) BIT 114 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_AUTO_NEG_CTL BIT(0) BIT 116 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_RX_INT_THRESHOLD BIT(6) BIT 119 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_RX_PORT_EN BIT(1) BIT 120 drivers/net/ethernet/hisilicon/hip04_eth.c #define GE_TX_PORT_EN BIT(2) BIT 122 drivers/net/ethernet/hisilicon/hip04_eth.c #define PPE_CFG_RX_PKT_ALIGN BIT(18) BIT 127 drivers/net/ethernet/hisilicon/hip04_eth.c #define PPE_CFG_STS_RX_PKT_CNT_RC BIT(0) BIT 128 drivers/net/ethernet/hisilicon/hip04_eth.c #define PPE_CFG_QOS_VMID_MODE BIT(15) BIT 129 drivers/net/ethernet/hisilicon/hip04_eth.c #define PPE_CFG_BUS_LOCAL_REL (BIT(9) | BIT(15) | BIT(19) | BIT(23)) BIT 133 drivers/net/ethernet/hisilicon/hip04_eth.c #define PPE_TX_BUF_HOLD BIT(31) BIT 138 drivers/net/ethernet/hisilicon/hip04_eth.c #define PPE_CFG_STS_RX_PKT_CNT_RC BIT(12) BIT 139 drivers/net/ethernet/hisilicon/hip04_eth.c #define PPE_CFG_QOS_VMID_MODE BIT(14) BIT 140 drivers/net/ethernet/hisilicon/hip04_eth.c #define PPE_CFG_BUS_LOCAL_REL BIT(14) BIT 147 drivers/net/ethernet/hisilicon/hip04_eth.c #define PPE_CFG_RX_FIFO_FSFU BIT(11) BIT 151 drivers/net/ethernet/hisilicon/hip04_eth.c #define PPE_CFG_BUS_BIG_ENDIEN BIT(0) BIT 320 drivers/net/ethernet/hisilicon/hip04_eth.c val = BIT(priv->group); BIT 20 drivers/net/ethernet/hisilicon/hisi_femac.c #define MAC_PORTSEL_STAT_CPU BIT(0) BIT 21 drivers/net/ethernet/hisilicon/hisi_femac.c #define MAC_PORTSEL_RMII BIT(1) BIT 23 drivers/net/ethernet/hisilicon/hisi_femac.c #define MAC_PORTSET_DUPLEX_FULL BIT(0) BIT 24 drivers/net/ethernet/hisilicon/hisi_femac.c #define MAC_PORTSET_LINKED BIT(1) BIT 25 drivers/net/ethernet/hisilicon/hisi_femac.c #define MAC_PORTSET_SPEED_100M BIT(2) BIT 29 drivers/net/ethernet/hisilicon/hisi_femac.c #define BIT_PAUSE_EN BIT(18) BIT 46 drivers/net/ethernet/hisilicon/hisi_femac.c #define BIT_TX_READY BIT(24) BIT 47 drivers/net/ethernet/hisilicon/hisi_femac.c #define BIT_RX_READY BIT(25) BIT 52 drivers/net/ethernet/hisilicon/hisi_femac.c #define SOFT_RESET_ALL BIT(0) BIT 54 drivers/net/ethernet/hisilicon/hisi_femac.c #define FWCTRL_VLAN_ENABLE BIT(0) BIT 55 drivers/net/ethernet/hisilicon/hisi_femac.c #define FWCTRL_FW2CPU_ENA BIT(5) BIT 56 drivers/net/ethernet/hisilicon/hisi_femac.c #define FWCTRL_FWALL2CPU BIT(7) BIT 58 drivers/net/ethernet/hisilicon/hisi_femac.c #define MACTCTRL_UNI2CPU BIT(1) BIT 59 drivers/net/ethernet/hisilicon/hisi_femac.c #define MACTCTRL_MULTI2CPU BIT(3) BIT 60 drivers/net/ethernet/hisilicon/hisi_femac.c #define MACTCTRL_BROAD2CPU BIT(5) BIT 61 drivers/net/ethernet/hisilicon/hisi_femac.c #define MACTCTRL_MACT_ENA BIT(7) BIT 65 drivers/net/ethernet/hisilicon/hisi_femac.c #define IRQ_ENA_PORT0 BIT(18) BIT 66 drivers/net/ethernet/hisilicon/hisi_femac.c #define IRQ_ENA_ALL BIT(19) BIT 68 drivers/net/ethernet/hisilicon/hisi_femac.c #define IRQ_INT_RX_RDY BIT(0) BIT 69 drivers/net/ethernet/hisilicon/hisi_femac.c #define IRQ_INT_TX_PER_PACKET BIT(1) BIT 70 drivers/net/ethernet/hisilicon/hisi_femac.c #define IRQ_INT_TX_FIFO_EMPTY BIT(6) BIT 71 drivers/net/ethernet/hisilicon/hisi_femac.c #define IRQ_INT_MULTI_RXRDY BIT(7) BIT 78 drivers/net/ethernet/hisilicon/hisi_femac.c #define BIT_MACFLT_ENA BIT(17) BIT 79 drivers/net/ethernet/hisilicon/hisi_femac.c #define BIT_MACFLT_FW2CPU BIT(21) BIT 23 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_EN BIT(2) BIT 24 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_EN BIT(1) BIT 26 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BIT_CRC_ERR_PASS BIT(5) BIT 27 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BIT_PAUSE_FRM_PASS BIT(4) BIT 28 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BIT_VLAN_DROP_EN BIT(3) BIT 29 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BIT_BC_DROP_EN BIT(2) BIT 30 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BIT_MC_MATCH_EN BIT(1) BIT 31 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BIT_UC_MATCH_EN BIT(0) BIT 36 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BIT_MODE_CHANGE_EN BIT(0) BIT 39 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BIT_STRIP_PAD_EN BIT(3) BIT 40 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BIT_RUNT_PKT_EN BIT(4) BIT 47 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define MDIO_START BIT(20) BIT 48 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define MDIO_R_VALID BIT(0) BIT 49 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define MDIO_READ (BIT(17) | MDIO_START) BIT 50 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define MDIO_WRITE (BIT(16) | MDIO_START) BIT 59 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_FQ_START_ADDR_EN BIT(2) BIT 60 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_FQ_DEPTH_EN BIT(1) BIT 61 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_FQ_RD_ADDR_EN BIT(0) BIT 70 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_BQ_START_ADDR_EN BIT(2) BIT 71 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_BQ_DEPTH_EN BIT(1) BIT 72 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_BQ_WR_ADDR_EN BIT(0) BIT 81 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_BQ_START_ADDR_EN BIT(2) BIT 82 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_BQ_DEPTH_EN BIT(1) BIT 83 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_BQ_RD_ADDR_EN BIT(0) BIT 92 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_RQ_START_ADDR_EN BIT(2) BIT 93 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_RQ_DEPTH_EN BIT(1) BIT 94 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_RQ_WR_ADDR_EN BIT(0) BIT 99 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define MAC_FIFO_ERR_IN BIT(30) BIT 100 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_RQ_IN_TIMEOUT_INT BIT(29) BIT 101 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_BQ_IN_TIMEOUT_INT BIT(28) BIT 102 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TXOUTCFF_FULL_INT BIT(27) BIT 103 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TXOUTCFF_EMPTY_INT BIT(26) BIT 104 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TXCFF_FULL_INT BIT(25) BIT 105 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TXCFF_EMPTY_INT BIT(24) BIT 106 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RXOUTCFF_FULL_INT BIT(23) BIT 107 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RXOUTCFF_EMPTY_INT BIT(22) BIT 108 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RXCFF_FULL_INT BIT(21) BIT 109 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RXCFF_EMPTY_INT BIT(20) BIT 110 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_RQ_IN_INT BIT(19) BIT 111 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_BQ_OUT_INT BIT(18) BIT 112 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_BQ_IN_INT BIT(17) BIT 113 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_FQ_OUT_INT BIT(16) BIT 114 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_RQ_EMPTY_INT BIT(15) BIT 115 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_RQ_FULL_INT BIT(14) BIT 116 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_RQ_ALEMPTY_INT BIT(13) BIT 117 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_RQ_ALFULL_INT BIT(12) BIT 118 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_BQ_EMPTY_INT BIT(11) BIT 119 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_BQ_FULL_INT BIT(10) BIT 120 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_BQ_ALEMPTY_INT BIT(9) BIT 121 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define TX_BQ_ALFULL_INT BIT(8) BIT 122 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_BQ_EMPTY_INT BIT(7) BIT 123 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_BQ_FULL_INT BIT(6) BIT 124 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_BQ_ALEMPTY_INT BIT(5) BIT 125 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_BQ_ALFULL_INT BIT(4) BIT 126 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_FQ_EMPTY_INT BIT(3) BIT 127 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_FQ_FULL_INT BIT(2) BIT 128 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_FQ_ALEMPTY_INT BIT(1) BIT 129 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define RX_FQ_ALFULL_INT BIT(0) BIT 141 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_STOP BIT(1) BIT 142 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_STOP BIT(0) BIT 144 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_FLUSH_CMD BIT(5) BIT 145 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_FLUSH_CMD BIT(4) BIT 146 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_FLUSH_FLAG_DOWN BIT(3) BIT 147 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_TX_FLUSH_FLAG_UP BIT(2) BIT 148 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_FLUSH_FLAG_DOWN BIT(1) BIT 149 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define BITS_RX_FLUSH_FLAG_UP BIT(0) BIT 163 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define GMAC_FULL_DUPLEX BIT(4) BIT 184 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define DESC_SG BIT(30) BIT 192 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c #define HW_CAP_TSO BIT(0) BIT 96 drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h #define HCLGE_MBX_NEED_RESP_BIT BIT(0) BIT 59 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\ BIT 60 drivers/net/ethernet/hisilicon/hns3/hnae3.h BIT(HNAE3_DEV_SUPPORT_ROCE_B)) BIT 613 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) BIT 614 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) BIT 615 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) BIT 616 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_SUPPORT_VF BIT(3) BIT 617 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) BIT 619 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ BIT 620 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ BIT 621 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_BPE BIT(2) /* broadcast promisc enable */ BIT 622 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ BIT 623 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ BIT 624 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_VLAN_FLTR BIT(5) /* enable vlan filter */ BIT 319 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c rcb_reg |= BIT(HNS3_RING_EN_B); BIT 328 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c rcb_reg &= ~BIT(HNS3_RING_EN_B); BIT 2510 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) BIT 2534 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) BIT 2537 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | BIT 2538 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c BIT(HNS3_RXD_OL3E_B) | BIT 2539 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c BIT(HNS3_RXD_OL4E_B)))) { BIT 2706 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { BIT 2712 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) BIT 2825 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | BIT 2826 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c BIT(HNS3_RXD_L2E_B))))) { BIT 2828 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c if (l234info & BIT(HNS3_RXD_L2E_B)) BIT 2889 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) BIT 1322 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c if (loc_fec & BIT(HNAE3_FEC_AUTO)) BIT 1324 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c if (loc_fec & BIT(HNAE3_FEC_RS)) BIT 1326 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c if (loc_fec & BIT(HNAE3_FEC_BASER)) BIT 1345 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c loc_fec |= BIT(HNAE3_FEC_AUTO); BIT 1347 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c loc_fec |= BIT(HNAE3_FEC_RS); BIT 1349 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c loc_fec |= BIT(HNAE3_FEC_BASER); BIT 73 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CMD_FLAG_IN BIT(0) BIT 74 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CMD_FLAG_OUT BIT(1) BIT 75 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CMD_FLAG_NEXT BIT(2) BIT 76 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CMD_FLAG_WR BIT(3) BIT 77 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CMD_FLAG_NO_INTR BIT(4) BIT 78 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) BIT 429 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) BIT 430 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) BIT 544 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) BIT 555 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_PROMISC_TX_EN_B BIT(4) BIT 556 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_PROMISC_RX_EN_B BIT(5) BIT 605 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) BIT 624 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) BIT 707 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) BIT 708 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) BIT 709 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) BIT 917 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_PF_RESET_DONE_BIT BIT(0) BIT 924 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) BIT 925 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) BIT 926 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CMD_SERDES_DONE_B BIT(0) BIT 927 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) BIT 956 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B) BIT 295 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c if ((prio_tc[j] == i) && (pfc_map & BIT(i))) BIT 296 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c pfc->pfc_en |= BIT(j); BIT 335 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c if ((prio_tc[j] == i) && (pfc->pfc_en & BIT(j))) { BIT 336 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c pfc_map |= BIT(i); BIT 13 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h #define HCLGE_DBG_MNG_VLAN_MASK_B BIT(0) BIT 14 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h #define HCLGE_DBG_MNG_MAC_MASK_B BIT(1) BIT 15 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h #define HCLGE_DBG_MNG_ETHER_MASK_B BIT(2) BIT 16 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h #define HCLGE_DBG_MNG_E_TYPE_B BIT(11) BIT 17 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h #define HCLGE_DBG_MNG_DROP_B BIT(13) BIT 7 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "imp_itcm0_ecc_mbit_err", BIT 9 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "imp_itcm1_ecc_mbit_err", BIT 11 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "imp_itcm2_ecc_mbit_err", BIT 13 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "imp_itcm3_ecc_mbit_err", BIT 15 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "imp_dtcm0_mem0_ecc_mbit_err", BIT 17 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(11), .msg = "imp_dtcm0_mem1_ecc_mbit_err", BIT 19 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(13), .msg = "imp_dtcm1_mem0_ecc_mbit_err", BIT 21 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(15), .msg = "imp_dtcm1_mem1_ecc_mbit_err", BIT 23 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(17), .msg = "imp_itcm4_ecc_mbit_err", BIT 29 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "cmdq_nic_rx_depth_ecc_mbit_err", BIT 31 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "cmdq_nic_tx_depth_ecc_mbit_err", BIT 33 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "cmdq_nic_rx_tail_ecc_mbit_err", BIT 35 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "cmdq_nic_tx_tail_ecc_mbit_err", BIT 37 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "cmdq_nic_rx_head_ecc_mbit_err", BIT 39 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(11), .msg = "cmdq_nic_tx_head_ecc_mbit_err", BIT 41 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(13), .msg = "cmdq_nic_rx_addr_ecc_mbit_err", BIT 43 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(15), .msg = "cmdq_nic_tx_addr_ecc_mbit_err", BIT 45 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(17), .msg = "cmdq_rocee_rx_depth_ecc_mbit_err", BIT 47 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(19), .msg = "cmdq_rocee_tx_depth_ecc_mbit_err", BIT 49 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(21), .msg = "cmdq_rocee_rx_tail_ecc_mbit_err", BIT 51 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(23), .msg = "cmdq_rocee_tx_tail_ecc_mbit_err", BIT 53 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(25), .msg = "cmdq_rocee_rx_head_ecc_mbit_err", BIT 55 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(27), .msg = "cmdq_rocee_tx_head_ecc_mbit_err", BIT 57 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(29), .msg = "cmdq_rocee_rx_addr_ecc_mbit_err", BIT 59 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(31), .msg = "cmdq_rocee_tx_addr_ecc_mbit_err", BIT 65 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(6), .msg = "tqp_int_cfg_even_ecc_mbit_err", BIT 67 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "tqp_int_cfg_odd_ecc_mbit_err", BIT 69 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(8), .msg = "tqp_int_ctrl_even_ecc_mbit_err", BIT 71 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "tqp_int_ctrl_odd_ecc_mbit_err", BIT 73 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(10), .msg = "tx_que_scan_int_ecc_mbit_err", BIT 75 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(11), .msg = "rx_que_scan_int_ecc_mbit_err", BIT 81 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "msix_nic_ecc_mbit_err", BIT 83 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "msix_rocee_ecc_mbit_err", BIT 89 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err", BIT 91 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err", BIT 97 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "rx_buf_overflow", BIT 99 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow", BIT 101 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "rx_stp_fifo_underflow", BIT 103 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "tx_buf_overflow", BIT 105 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "tx_buf_underrun", BIT 107 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "rx_stp_buf_overflow", BIT 113 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err", BIT 119 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_mbit_err", BIT 121 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_mbit_err", BIT 123 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_mbit_err", BIT 125 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_mbit_err", BIT 127 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_mbit_err", BIT 129 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_mbit_err", BIT 131 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_mbit_err", BIT 133 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_mbit_err", BIT 135 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_mbit_err", BIT 137 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_mbit_err", BIT 139 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_mbit_err", BIT 141 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_mbit_err", BIT 143 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_mbit_err", BIT 145 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_mbit_err", BIT 147 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_mbit_err", BIT 149 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_mbit_err", BIT 151 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_mbit_err", BIT 153 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_mbit_err", BIT 155 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_m1bit_err", BIT 157 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_mbit_err", BIT 159 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_mbit_err", BIT 161 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_mbit_err", BIT 163 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_mbit_err", BIT 165 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_mbit_err", BIT 167 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_mbit_err", BIT 169 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_mbit_err", BIT 171 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_mbit_err", BIT 173 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(27), .msg = "flow_director_ad_mem0_ecc_mbit_err", BIT 175 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(28), .msg = "flow_director_ad_mem1_ecc_mbit_err", BIT 177 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(29), .msg = "rx_vlan_tag_memory_ecc_mbit_err", BIT 179 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(30), .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", BIT 185 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "tx_vlan_tag_err", BIT 187 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err", BIT 193 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_mbit_err", BIT 195 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_mbit_err", BIT 197 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_mbit_err", BIT 199 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_mbit_err", BIT 201 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_mbit_err", BIT 203 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_mbit_err", BIT 209 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err", BIT 211 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_err", BIT 213 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_err", BIT 215 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", BIT 217 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", BIT 219 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", BIT 221 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", BIT 223 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", BIT 225 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", BIT 227 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", BIT 229 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", BIT 231 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(12), .msg = "tm_sch_port_shap_offset_fifo_wr_err", BIT 233 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(13), .msg = "tm_sch_port_shap_offset_fifo_rd_err", BIT 235 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(14), .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", BIT 237 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(15), .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", BIT 239 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(16), .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", BIT 241 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(17), .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", BIT 243 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(18), .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", BIT 245 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(19), .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", BIT 247 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(20), .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", BIT 249 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(21), .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", BIT 251 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_err", BIT 253 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_err", BIT 255 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_err", BIT 257 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_err", BIT 259 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_err", BIT 261 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_err", BIT 263 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_err", BIT 265 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_err", BIT 267 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_err", BIT 269 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_err", BIT 275 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "qcn_shap_gp0_sch_fifo_rd_err", BIT 277 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "qcn_shap_gp0_sch_fifo_wr_err", BIT 279 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "qcn_shap_gp1_sch_fifo_rd_err", BIT 281 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "qcn_shap_gp1_sch_fifo_wr_err", BIT 283 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "qcn_shap_gp2_sch_fifo_rd_err", BIT 285 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "qcn_shap_gp2_sch_fifo_wr_err", BIT 287 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(6), .msg = "qcn_shap_gp3_sch_fifo_rd_err", BIT 289 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "qcn_shap_gp3_sch_fifo_wr_err", BIT 291 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(8), .msg = "qcn_shap_gp0_offset_fifo_rd_err", BIT 293 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "qcn_shap_gp0_offset_fifo_wr_err", BIT 295 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(10), .msg = "qcn_shap_gp1_offset_fifo_rd_err", BIT 297 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(11), .msg = "qcn_shap_gp1_offset_fifo_wr_err", BIT 299 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(12), .msg = "qcn_shap_gp2_offset_fifo_rd_err", BIT 301 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(13), .msg = "qcn_shap_gp2_offset_fifo_wr_err", BIT 303 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(14), .msg = "qcn_shap_gp3_offset_fifo_rd_err", BIT 305 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(15), .msg = "qcn_shap_gp3_offset_fifo_wr_err", BIT 307 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(16), .msg = "qcn_byte_info_fifo_rd_err", BIT 309 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(17), .msg = "qcn_byte_info_fifo_wr_err", BIT 315 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err", BIT 317 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err", BIT 319 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err", BIT 321 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err", BIT 323 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err", BIT 325 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err", BIT 327 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err", BIT 329 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", BIT 331 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", BIT 333 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", BIT 335 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err", BIT 341 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err", BIT 343 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err", BIT 345 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err", BIT 347 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err", BIT 349 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err", BIT 351 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err", BIT 353 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err", BIT 355 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err", BIT 357 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err", BIT 359 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err", BIT 361 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err", BIT 363 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err", BIT 365 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err", BIT 367 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err", BIT 373 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", BIT 375 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", BIT 377 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", BIT 379 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", BIT 381 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err", BIT 383 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err", BIT 385 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err", BIT 387 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err", BIT 389 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err", BIT 391 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err", BIT 393 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err", BIT 395 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err", BIT 397 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err", BIT 399 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(26), .msg = "rd_bus_err", BIT 401 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(27), .msg = "wr_bus_err", BIT 403 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(28), .msg = "reg_search_miss", BIT 405 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(29), .msg = "rx_q_search_miss", BIT 407 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(30), .msg = "ooo_ecc_err_detect", BIT 409 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl", BIT 415 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err", BIT 417 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err", BIT 419 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err", BIT 421 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err", BIT 427 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "over_8bd_no_fe", BIT 429 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err", BIT 431 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err", BIT 433 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "tx_rd_fbd_poison", BIT 435 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "rx_rd_ebd_poison", BIT 437 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "buf_wait_timeout", BIT 443 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "buf_sum_err", BIT 445 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "ppp_mb_num_err", BIT 447 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "ppp_mbid_err", BIT 449 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "ppp_rlt_mac_err", BIT 451 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "ppp_rlt_host_err", BIT 453 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "cks_edit_position_err", BIT 455 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(6), .msg = "cks_edit_condition_err", BIT 457 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "vlan_edit_condition_err", BIT 459 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(8), .msg = "vlan_num_ot_err", BIT 461 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "vlan_num_in_err", BIT 467 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(x), .msg = "ssu_mem" #x "_ecc_mbit_err", \ BIT 507 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port", BIT 509 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port", BIT 511 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "igu_pkt_without_key_port", BIT 513 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "roc_eof_mis_match_port", BIT 515 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port", BIT 517 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "igu_eof_mis_match_port", BIT 519 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(6), .msg = "roc_sof_mis_match_port", BIT 521 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port", BIT 523 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(8), .msg = "igu_sof_mis_match_port", BIT 525 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(11), .msg = "ets_rd_int_rx_port", BIT 527 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(12), .msg = "ets_wr_int_rx_port", BIT 529 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(13), .msg = "ets_rd_int_tx_port", BIT 531 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(14), .msg = "ets_wr_int_tx_port", BIT 537 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "ig_mac_inf_int", BIT 539 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "ig_host_inf_int", BIT 541 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "ig_roc_buf_int", BIT 543 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "ig_host_data_fifo_int", BIT 545 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(4), .msg = "ig_host_key_fifo_int", BIT 547 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(5), .msg = "tx_qcn_fifo_int", BIT 549 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(6), .msg = "rx_qcn_fifo_int", BIT 551 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int", BIT 553 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int", BIT 555 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "qm_eof_fifo_int", BIT 557 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(10), .msg = "mb_rlt_fifo_int", BIT 559 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int", BIT 561 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int", BIT 563 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int", BIT 565 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int", BIT 567 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(15), .msg = "host_cmd_fifo_int", BIT 569 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(16), .msg = "mac_cmd_fifo_int", BIT 571 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int", BIT 573 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int", BIT 575 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(19), .msg = "dup_bitmap_empty_int", BIT 577 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int", BIT 579 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int", BIT 581 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int", BIT 583 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int", BIT 589 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg", BIT 591 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg", BIT 593 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg", BIT 595 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg", BIT 601 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port", BIT 603 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(9), .msg = "low_water_line_err_port", BIT 605 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c { .int_msk = BIT(10), .msg = "hi_water_line_err_port", BIT 1049 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c cpu_to_le32(HCLGE_SSU_COMMON_INT_EN & ~BIT(5)); BIT 1153 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c if ((le32_to_cpu(desc[0].data[2])) & BIT(0)) BIT 1176 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c status = le32_to_cpu(*(desc_data + 3)) & BIT(0); BIT 1588 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c .msk = BIT(0), .name = "IGU_EGU", BIT 1592 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c .msk = BIT(1), .name = "PPP", BIT 1596 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c .msk = BIT(2), .name = "SSU", BIT 1600 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c .msk = BIT(3), .name = "PPU", BIT 1604 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c .msk = BIT(4), .name = "TM", BIT 1608 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c .msk = BIT(5), .name = "COMMON", BIT 1612 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c .msk = BIT(8), .name = "MAC", BIT 90 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK BIT(29) BIT 102 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_ROCEE_RERR_INT_MASK BIT(0) BIT 103 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_ROCEE_BERR_INT_MASK BIT(1) BIT 105 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_ROCEE_ECC_INT_MASK BIT(2) BIT 106 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_ROCEE_OVF_INT_MASK BIT(3) BIT 1101 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO); BIT 1108 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | BIT 1109 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(HNAE3_FEC_AUTO); BIT 1113 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO); BIT 1681 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) BIT 1723 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (hdev->hw_tc_map & BIT(i)) BIT 1738 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if ((hdev->tm_info.hw_pfc_map & BIT(i)) && BIT 1756 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (hdev->hw_tc_map & BIT(i) && BIT 1757 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c !(hdev->tm_info.hw_pfc_map & BIT(i)) && BIT 1866 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (hdev->hw_tc_map & BIT(i)) { BIT 1896 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (!(hdev->hw_tc_map & BIT(i))) BIT 1901 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (hdev->tm_info.hw_pfc_map & BIT(i)) { BIT 1927 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c unsigned int mask = BIT((unsigned int)i); BIT 1957 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c unsigned int mask = BIT((unsigned int)i); BIT 2012 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (!(hdev->hw_tc_map & BIT(i))) BIT 2124 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); BIT 2128 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); BIT 2168 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); BIT 2172 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); BIT 2196 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); BIT 2199 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); BIT 2533 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (fec_mode & BIT(HNAE3_FEC_AUTO)) BIT 2535 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (fec_mode & BIT(HNAE3_FEC_RS)) BIT 2538 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (fec_mode & BIT(HNAE3_FEC_BASER)) BIT 2565 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); BIT 2608 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { BIT 2816 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c mac->fec_mode = BIT(resp->active_fec); BIT 2894 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) { BIT 2898 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); BIT 2903 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { BIT 2907 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); BIT 2921 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { BIT 2922 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); BIT 2954 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | BIT 2955 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(HCLGE_VECTOR0_CORERESET_INT_B) | BIT 2956 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); BIT 3320 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { BIT 3322 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); BIT 3326 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { BIT 3328 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); BIT 3445 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); BIT 3448 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); BIT 3542 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); BIT 4431 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (!(hdev->hw_tc_map & BIT(i))) BIT 4776 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | BIT 4777 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | BIT 4778 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | BIT 4779 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); BIT 4785 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); BIT 4791 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); BIT 4898 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(INNER_DST_MAC): BIT 4907 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(INNER_SRC_MAC): BIT 4916 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(INNER_VLAN_TAG_FST): BIT 4925 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(INNER_ETH_TYPE): BIT 4934 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(INNER_IP_TOS): BIT 4939 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(INNER_IP_PROTO): BIT 4946 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(INNER_SRC_IP): BIT 4955 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(INNER_DST_IP): BIT 4964 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(INNER_SRC_PORT): BIT 4973 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(INNER_DST_PORT): BIT 5017 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c tuple_bit = key_cfg->meta_data_active & BIT(i); BIT 5020 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(ROCE_TYPE): BIT 5024 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c case BIT(DST_VPORT): BIT 5069 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c check_tuple = key_cfg->tuple_active & BIT(i); BIT 5160 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); BIT 5163 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_IP); BIT 5166 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_DST_IP); BIT 5169 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_PORT); BIT 5172 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_DST_PORT); BIT 5175 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_IP_TOS); BIT 5180 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | BIT 5181 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); BIT 5184 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_IP); BIT 5187 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_DST_IP); BIT 5190 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_IP_TOS); BIT 5193 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_IP_PROTO); BIT 5206 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | BIT 5207 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_IP_TOS); BIT 5212 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_IP); BIT 5216 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_DST_IP); BIT 5219 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_PORT); BIT 5222 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_DST_PORT); BIT 5230 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | BIT 5231 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) | BIT 5232 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_DST_PORT); BIT 5237 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_IP); BIT 5241 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_DST_IP); BIT 5244 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_IP_PROTO); BIT 5255 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | BIT 5256 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | BIT 5257 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); BIT 5260 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_SRC_MAC); BIT 5263 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_DST_MAC); BIT 5266 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_ETH_TYPE); BIT 5277 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_VLAN_TAG_FST); BIT 5284 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_VLAN_TAG_FST); BIT 5292 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused |= BIT(INNER_DST_MAC); BIT 5294 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *unused &= ~(BIT(INNER_DST_MAC)); BIT 5802 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_SRC_IP) ? BIT 5808 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_DST_IP) ? BIT 5813 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_SRC_PORT) ? BIT 5818 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_DST_PORT) ? BIT 5823 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_IP_TOS) ? BIT 5831 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_SRC_IP) ? BIT 5837 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_DST_IP) ? BIT 5842 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_IP_TOS) ? BIT 5847 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_IP_PROTO) ? BIT 5858 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (rule->unused_tuple & BIT(INNER_SRC_IP)) BIT 5867 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (rule->unused_tuple & BIT(INNER_DST_IP)) BIT 5876 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_SRC_PORT) ? BIT 5881 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_DST_PORT) ? BIT 5888 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (rule->unused_tuple & BIT(INNER_SRC_IP)) BIT 5897 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (rule->unused_tuple & BIT(INNER_DST_IP)) BIT 5906 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_IP_PROTO) ? BIT 5913 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (rule->unused_tuple & BIT(INNER_SRC_MAC)) BIT 5921 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (rule->unused_tuple & BIT(INNER_DST_MAC)) BIT 5930 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_ETH_TYPE) ? BIT 5942 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? BIT 5949 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (rule->unused_tuple & BIT(INNER_DST_MAC)) BIT 6047 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | BIT 6048 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | BIT 6049 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(INNER_SRC_PORT); BIT 6568 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); BIT 7583 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) BIT 7584 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) BIT 7585 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) BIT 7586 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) BIT 7587 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) BIT 9581 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (!(hdev->hw_tc_map & BIT(i))) BIT 103 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_D_PORT_BIT BIT(0) BIT 104 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_S_PORT_BIT BIT(1) BIT 105 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_D_IP_BIT BIT(2) BIT 106 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_S_IP_BIT BIT(3) BIT 107 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_V_TAG_BIT BIT(4) BIT 192 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_SUPPORT_1G_BIT BIT(0) BIT 193 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_SUPPORT_10G_BIT BIT(1) BIT 194 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_SUPPORT_25G_BIT BIT(2) BIT 195 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_SUPPORT_50G_BIT BIT(3) BIT 196 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_SUPPORT_100G_BIT BIT(4) BIT 198 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_SUPPORT_40G_BIT BIT(5) BIT 199 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_SUPPORT_100M_BIT BIT(6) BIT 200 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_SUPPORT_10M_BIT BIT(7) BIT 794 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_FLAG_MAIN BIT(0) BIT 795 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_FLAG_DCB_CAPABLE BIT(1) BIT 796 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_FLAG_DCB_ENABLE BIT(2) BIT 797 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) BIT 376 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c vf_tc_map |= BIT(i); BIT 559 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c if (hdev->hw_tc_map & BIT(i) && i < kinfo->num_tc) { BIT 990 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c if (!(hdev->hw_tc_map & BIT(i))) BIT 1383 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c bit_map |= BIT(i); BIT 10 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_TX_MAC_PAUSE_EN_MSK BIT(0) BIT 11 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_RX_MAC_PAUSE_EN_MSK BIT(1) BIT 13 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_TM_PORT_BASE_MODE_MSK BIT(0) BIT 19 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_TM_TX_SCHD_DWRR_MSK BIT(0) BIT 32 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_TM_QS_PRI_LINK_VLD_MSK BIT(0) BIT 39 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_TM_Q_QS_LINK_VLD_MSK BIT(10) BIT 83 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h #define HCLGEVF_CMD_FLAG_IN BIT(HCLGEVF_CMD_FLAG_IN_VALID_SHIFT) BIT 84 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h #define HCLGEVF_CMD_FLAG_OUT BIT(HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT) BIT 85 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h #define HCLGEVF_CMD_FLAG_NEXT BIT(HCLGEVF_CMD_FLAG_NEXT_SHIFT) BIT 86 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h #define HCLGEVF_CMD_FLAG_WR BIT(HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT) BIT 87 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h #define HCLGEVF_CMD_FLAG_NO_INTR BIT(HCLGEVF_CMD_FLAG_NO_INTR_SHIFT) BIT 88 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h #define HCLGEVF_CMD_FLAG_ERR_INTR BIT(HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT) BIT 210 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h #define HCLGEVF_LINK_STATUS BIT(HCLGEVF_LINK_STS_B) BIT 250 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h #define HCLGEVF_NIC_SW_RST_RDY BIT(HCLGEVF_NIC_SW_RST_RDY_B) BIT 395 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c if (hdev->hw_tc_map & BIT(i)) BIT 647 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); BIT 1905 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { BIT 1924 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { BIT 1936 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); BIT 100 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_FUN_RST_ING_BIT BIT(0) BIT 101 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) BIT 102 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_CORE_RST_ING_BIT BIT(6) BIT 103 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_IMP_RST_ING_BIT BIT(7) BIT 109 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_VF_RST_ING_BIT BIT(16) BIT 122 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_D_PORT_BIT BIT(0) BIT 123 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_S_PORT_BIT BIT(1) BIT 124 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_D_IP_BIT BIT(2) BIT 125 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_S_IP_BIT BIT(3) BIT 126 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_V_TAG_BIT BIT(4) BIT 23 drivers/net/ethernet/huawei/hinic/hinic_dev.h HINIC_LINK_UP = BIT(0), BIT 24 drivers/net/ethernet/huawei/hinic/hinic_dev.h HINIC_INTF_UP = BIT(1), BIT 25 drivers/net/ethernet/huawei/hinic/hinic_dev.h HINIC_RSS_ENABLE = BIT(2), BIT 30 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.c #define API_CMD_CELL_SIZE_MIN (BIT(API_CMD_CELL_SIZE_SHIFT)) BIT 120 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h HINIC_CB_ENABLED = BIT(0), BIT 121 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h HINIC_CB_RUNNING = BIT(1), BIT 158 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h HINIC_EQE_ENABLED = BIT(0), BIT 159 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h HINIC_EQE_RUNNING = BIT(1), BIT 213 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c hwif->attr.num_aeqs = BIT(HINIC_FA1_GET(attr1, AEQS_PER_FUNC)); BIT 214 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c hwif->attr.num_ceqs = BIT(HINIC_FA1_GET(attr1, CEQS_PER_FUNC)); BIT 215 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c hwif->attr.num_irqs = BIT(HINIC_FA1_GET(attr1, IRQS_PER_FUNC)); BIT 216 drivers/net/ethernet/huawei/hinic/hinic_hw_if.c hwif->attr.num_dma_attr = BIT(HINIC_FA1_GET(attr1, DMA_ATTR_PER_FUNC)); BIT 81 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h HINIC_MGMT_CB_ENABLED = BIT(0), BIT 82 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h HINIC_MGMT_CB_RUNNING = BIT(1), BIT 33 drivers/net/ethernet/huawei/hinic/hinic_port.h HINIC_RX_MODE_UC = BIT(0), BIT 34 drivers/net/ethernet/huawei/hinic/hinic_port.h HINIC_RX_MODE_MC = BIT(1), BIT 35 drivers/net/ethernet/huawei/hinic/hinic_port.h HINIC_RX_MODE_BC = BIT(2), BIT 36 drivers/net/ethernet/huawei/hinic/hinic_port.h HINIC_RX_MODE_MC_ALL = BIT(3), BIT 37 drivers/net/ethernet/huawei/hinic/hinic_port.h HINIC_RX_MODE_PROMISC = BIT(4), BIT 18 drivers/net/ethernet/huawei/hinic/hinic_rx.h #define HINIC_RX_CSUM_HW_CHECK_NONE BIT(7) BIT 19 drivers/net/ethernet/huawei/hinic/hinic_rx.h #define HINIC_RX_CSUM_IPSU_OTHER_ERR BIT(8) BIT 66 drivers/net/ethernet/huawei/hinic/hinic_tx.c TX_OFFLOAD_TSO = BIT(0), BIT 67 drivers/net/ethernet/huawei/hinic/hinic_tx.c TX_OFFLOAD_CSUM = BIT(1), BIT 68 drivers/net/ethernet/huawei/hinic/hinic_tx.c TX_OFFLOAD_VLAN = BIT(2), BIT 69 drivers/net/ethernet/huawei/hinic/hinic_tx.c TX_OFFLOAD_INVALID = BIT(3), BIT 106 drivers/net/ethernet/intel/e1000e/80003es2lan.c nvm->word_size = BIT(size); BIT 843 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg |= BIT(22); BIT 848 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg |= BIT(22); BIT 855 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg &= ~BIT(20); BIT 861 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg &= ~BIT(28); BIT 863 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg |= BIT(28); BIT 170 drivers/net/ethernet/intel/e1000e/82571.c nvm->word_size = BIT(size); BIT 1148 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(22); BIT 1153 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(22); BIT 1162 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26); BIT 1166 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(26); BIT 1178 drivers/net/ethernet/intel/e1000e/82571.c reg &= ~(BIT(29) | BIT(30)); BIT 1179 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26); BIT 1181 drivers/net/ethernet/intel/e1000e/82571.c reg &= ~BIT(28); BIT 1183 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(28); BIT 1196 drivers/net/ethernet/intel/e1000e/82571.c reg &= ~BIT(29); BIT 1209 drivers/net/ethernet/intel/e1000e/82571.c reg &= ~BIT(23); BIT 1210 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(22); BIT 1246 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(22); BIT 1293 drivers/net/ethernet/intel/e1000e/82571.c BIT(hw->mng_cookie.vlan_id & BIT 99 drivers/net/ethernet/intel/e1000e/e1000.h #define E1000_TIDV_FPD BIT(31) BIT 100 drivers/net/ethernet/intel/e1000e/e1000.h #define E1000_RDTR_FPD BIT(31) BIT 391 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_HAS_AMT BIT(0) BIT 392 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_HAS_FLASH BIT(1) BIT 393 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_HAS_HW_VLAN_FILTER BIT(2) BIT 394 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_HAS_WOL BIT(3) BIT 396 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5) BIT 397 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_HAS_SWSM_ON_LOAD BIT(6) BIT 398 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_HAS_JUMBO_FRAMES BIT(7) BIT 399 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_READ_ONLY_NVM BIT(8) BIT 400 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_IS_ICH BIT(9) BIT 401 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_HAS_MSIX BIT(10) BIT 402 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_HAS_SMART_POWER_DOWN BIT(11) BIT 403 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_IS_QUAD_PORT_A BIT(12) BIT 404 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_IS_QUAD_PORT BIT(13) BIT 405 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_HAS_HW_TIMESTAMP BIT(14) BIT 406 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_APME_IN_WUC BIT(15) BIT 407 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_APME_IN_CTRL3 BIT(16) BIT 408 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_APME_CHECK_PORT_B BIT(17) BIT 409 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_DISABLE_FC_PAUSE_TIME BIT(18) BIT 410 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_NO_WAKE_UCAST BIT(19) BIT 411 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_MNG_PT_ENABLED BIT(20) BIT 412 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_RESET_OVERWRITES_LAA BIT(21) BIT 413 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_TARC_SPEED_MODE_BIT BIT(22) BIT 414 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_TARC_SET_BIT_ZERO BIT(23) BIT 415 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_RX_NEEDS_RESTART BIT(24) BIT 416 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_LSC_GIG_SPEED_DROP BIT(25) BIT 417 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_SMART_POWER_DOWN BIT(26) BIT 418 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_MSI_ENABLED BIT(27) BIT 420 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_TSO_FORCE BIT(29) BIT 421 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_RESTART_NOW BIT(30) BIT 422 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG_MSI_TEST_FAILED BIT(31) BIT 424 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_CRC_STRIPPING BIT(0) BIT 425 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_HAS_PHY_WAKEUP BIT(1) BIT 426 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_IS_DISCARDING BIT(2) BIT 427 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_DISABLE_ASPM_L1 BIT(3) BIT 428 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_HAS_PHY_STATS BIT(4) BIT 429 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_HAS_EEE BIT(5) BIT 430 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_DMA_BURST BIT(6) BIT 431 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_DISABLE_ASPM_L0S BIT(7) BIT 432 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_DISABLE_AIM BIT(8) BIT 433 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_CHECK_PHY_HANG BIT(9) BIT 434 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_NO_DISABLE_RX BIT(10) BIT 435 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_PCIM2PCI_ARBITER_WA BIT(11) BIT 436 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_DFLT_CRC_STRIPPING BIT(12) BIT 437 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_CHECK_RX_HWTSTAMP BIT(13) BIT 438 drivers/net/ethernet/intel/e1000e/e1000.h #define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14) BIT 899 drivers/net/ethernet/intel/e1000e/ethtool.c mask |= BIT(18); BIT 917 drivers/net/ethernet/intel/e1000e/ethtool.c mask |= BIT(30); BIT 919 drivers/net/ethernet/intel/e1000e/ethtool.c mask &= ~BIT(30); BIT 927 drivers/net/ethernet/intel/e1000e/ethtool.c mask |= BIT(30); BIT 1022 drivers/net/ethernet/intel/e1000e/ethtool.c mask = BIT(i); BIT 1388 drivers/net/ethernet/intel/e1000e/ethtool.c e1e_wphy(hw, PHY_REG(0, 21), phy_reg & ~BIT(3)); BIT 1454 drivers/net/ethernet/intel/e1000e/ethtool.c ctrl &= ~BIT(31); BIT 2285 drivers/net/ethernet/intel/e1000e/ethtool.c info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); BIT 2287 drivers/net/ethernet/intel/e1000e/ethtool.c info->rx_filters = (BIT(HWTSTAMP_FILTER_NONE) | BIT 2288 drivers/net/ethernet/intel/e1000e/ethtool.c BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | BIT 2289 drivers/net/ethernet/intel/e1000e/ethtool.c BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | BIT 2290 drivers/net/ethernet/intel/e1000e/ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | BIT 2291 drivers/net/ethernet/intel/e1000e/ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | BIT 2292 drivers/net/ethernet/intel/e1000e/ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | BIT 2293 drivers/net/ethernet/intel/e1000e/ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | BIT 2294 drivers/net/ethernet/intel/e1000e/ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | BIT 2295 drivers/net/ethernet/intel/e1000e/ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) | BIT 2296 drivers/net/ethernet/intel/e1000e/ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | BIT 2297 drivers/net/ethernet/intel/e1000e/ethtool.c BIT(HWTSTAMP_FILTER_ALL)); BIT 1036 drivers/net/ethernet/intel/e1000e/ich8lan.c value = DIV_ROUND_UP(value, BIT(5)); BIT 1569 drivers/net/ethernet/intel/e1000e/ich8lan.c phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); BIT 2045 drivers/net/ethernet/intel/e1000e/ich8lan.c phy_data |= (freq & BIT(0)) << BIT 2047 drivers/net/ethernet/intel/e1000e/ich8lan.c phy_data |= (freq & BIT(1)) << BIT 2534 drivers/net/ethernet/intel/e1000e/ich8lan.c ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); BIT 2565 drivers/net/ethernet/intel/e1000e/ich8lan.c mac_reg &= ~BIT(14); BIT 2580 drivers/net/ethernet/intel/e1000e/ich8lan.c data | BIT(0)); BIT 2604 drivers/net/ethernet/intel/e1000e/ich8lan.c data &= ~BIT(13); BIT 2618 drivers/net/ethernet/intel/e1000e/ich8lan.c ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); BIT 2638 drivers/net/ethernet/intel/e1000e/ich8lan.c data & ~BIT(0)); BIT 2661 drivers/net/ethernet/intel/e1000e/ich8lan.c data |= BIT(13); BIT 2675 drivers/net/ethernet/intel/e1000e/ich8lan.c ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); BIT 2681 drivers/net/ethernet/intel/e1000e/ich8lan.c return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); BIT 4846 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(22); BIT 4854 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(22); BIT 4859 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(22); BIT 4865 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(28) | BIT(29); BIT 4866 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); BIT 4872 drivers/net/ethernet/intel/e1000e/ich8lan.c reg &= ~BIT(28); BIT 4874 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(28); BIT 4875 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(24) | BIT(26) | BIT(30); BIT 4881 drivers/net/ethernet/intel/e1000e/ich8lan.c reg &= ~BIT(31); BIT 331 drivers/net/ethernet/intel/e1000e/mac.c hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit); BIT 303 drivers/net/ethernet/intel/e1000e/netdev.c (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : BIT 304 drivers/net/ethernet/intel/e1000e/netdev.c ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), BIT 2017 drivers/net/ethernet/intel/e1000e/netdev.c ivar |= BIT(31); BIT 2709 drivers/net/ethernet/intel/e1000e/netdev.c vfta |= BIT((vid & 0x1F)); BIT 2737 drivers/net/ethernet/intel/e1000e/netdev.c vfta &= ~BIT((vid & 0x1F)); BIT 2878 drivers/net/ethernet/intel/e1000e/netdev.c manc2h |= BIT(i); BIT 2891 drivers/net/ethernet/intel/e1000e/netdev.c manc2h |= BIT(1); BIT 2971 drivers/net/ethernet/intel/e1000e/netdev.c #define SPEED_MODE_BIT BIT(21) BIT 3076 drivers/net/ethernet/intel/e1000e/netdev.c phy_data |= BIT(2); BIT 3081 drivers/net/ethernet/intel/e1000e/netdev.c phy_data |= BIT(14); BIT 3278 drivers/net/ethernet/intel/e1000e/netdev.c ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); BIT 3501 drivers/net/ethernet/intel/e1000e/netdev.c if (!(fextnvm7 & BIT(0))) { BIT 3502 drivers/net/ethernet/intel/e1000e/netdev.c ew32(FEXTNVM7, fextnvm7 | BIT(0)); BIT 3844 drivers/net/ethernet/intel/e1000e/netdev.c rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); BIT 6957 drivers/net/ethernet/intel/e1000e/netdev.c if (!ret_val && (!(buf & BIT(0)))) { BIT 52 drivers/net/ethernet/intel/e1000e/nvm.c mask = BIT(count - 1); BIT 2880 drivers/net/ethernet/intel/e1000e/phy.c !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) { BIT 2884 drivers/net/ethernet/intel/e1000e/phy.c BIT(6) | 0x3, BIT 89 drivers/net/ethernet/intel/e1000e/phy.h #define BM_WUC_ENABLE_BIT BIT(2) BIT 90 drivers/net/ethernet/intel/e1000e/phy.h #define BM_WUC_HOST_WU_BIT BIT(4) BIT 91 drivers/net/ethernet/intel/e1000e/phy.h #define BM_WUC_ME_WU_BIT BIT(5) BIT 109 drivers/net/ethernet/intel/e1000e/phy.h #define I82577_CFG_ASSERT_CRS_ON_TX BIT(15) BIT 359 drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c regs->version = BIT(24) | (hw->revision_id << 16) | hw->device_id; BIT 896 drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c for (attr_flag = BIT(FM10K_TEST_MSG_UNSET); BIT 897 drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c attr_flag < BIT(2 * FM10K_TEST_MSG_NESTED); BIT 960 drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c if (priv_flags >= BIT(FM10K_PRV_FLAG_LEN)) BIT 1108 drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c max_combined = BIT((fls(max_combined / tcs) - 1)); BIT 391 drivers/net/ethernet/intel/fm10k/fm10k_main.c (BIT(FM10K_RSSTYPE_IPV4_TCP) | \ BIT 392 drivers/net/ethernet/intel/fm10k/fm10k_main.c BIT(FM10K_RSSTYPE_IPV4_UDP) | \ BIT 393 drivers/net/ethernet/intel/fm10k/fm10k_main.c BIT(FM10K_RSSTYPE_IPV6_TCP) | \ BIT 394 drivers/net/ethernet/intel/fm10k/fm10k_main.c BIT(FM10K_RSSTYPE_IPV6_UDP)) BIT 410 drivers/net/ethernet/intel/fm10k/fm10k_main.c (BIT(rss_type) & FM10K_RSS_L4_TYPES_MASK) ? BIT 1399 drivers/net/ethernet/intel/fm10k/fm10k_main.c avg_wire_size += BIT(itr_round) - 1; BIT 1504 drivers/net/ethernet/intel/fm10k/fm10k_main.c f->mask = BIT(fls(pcs - 1)) - 1; BIT 1508 drivers/net/ethernet/intel/fm10k/fm10k_main.c rss_i = BIT(fls(rss_i) - 1); BIT 1514 drivers/net/ethernet/intel/fm10k/fm10k_main.c f->mask = BIT(fls(rss_i - 1)) - 1; BIT 1544 drivers/net/ethernet/intel/fm10k/fm10k_main.c f->mask = BIT(fls(rss_i - 1)) - 1; BIT 1671 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c interface->msg_enable = BIT(DEFAULT_DEBUG_LEVEL_SHIFT) - 1; BIT 874 drivers/net/ethernet/intel/fm10k/fm10k_pci.c u32 txdctl = BIT(FM10K_TXDCTL_MAX_TIME_SHIFT) | FM10K_TXDCTL_ENABLE; BIT 1026 drivers/net/ethernet/intel/fm10k/fm10k_pci.c if (!(rx_pause & BIT(ring->qos_pc))) BIT 1077 drivers/net/ethernet/intel/fm10k/fm10k_pci.c if (!(rx_pause & BIT(ring->qos_pc))) BIT 1341 drivers/net/ethernet/intel/fm10k/fm10k_pci.c if (maxholdq & BIT(31)) { BIT 516 drivers/net/ethernet/intel/fm10k/fm10k_pf.c queue_count = BIT(dglort->rss_l + dglort->pc_l); BIT 517 drivers/net/ethernet/intel/fm10k/fm10k_pf.c vsi_count = BIT(dglort->vsi_l + dglort->queue_l); BIT 533 drivers/net/ethernet/intel/fm10k/fm10k_pf.c queue_count = BIT(dglort->queue_l + dglort->rss_l + dglort->vsi_l); BIT 534 drivers/net/ethernet/intel/fm10k/fm10k_pf.c pc_count = BIT(dglort->pc_l); BIT 957 drivers/net/ethernet/intel/fm10k/fm10k_pf.c fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), BIT(vf_idx % 32)); BIT 1375 drivers/net/ethernet/intel/fm10k/fm10k_pf.c if (!(FM10K_VF_FLAG_ENABLED(vf_info) & BIT(mode))) BIT 209 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c attr[1] = (u32)value & (BIT(8 * len) - 1); BIT 642 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_STRING)) BIT 645 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_MAC_ADDR)) BIT 648 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_U8)) BIT 650 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_U16)) BIT 652 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_U32)) BIT 654 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_U64)) BIT 656 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_S8)) BIT 658 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_S16)) BIT 660 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_S32)) BIT 662 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_S64)) BIT 664 drivers/net/ethernet/intel/fm10k/fm10k_tlv.c if (attr_flags & BIT(FM10K_TEST_MSG_LE_STRUCT)) BIT 338 drivers/net/ethernet/intel/fm10k/fm10k_type.h #define FM10K_VLAN_CLEAR BIT(15) BIT 596 drivers/net/ethernet/intel/fm10k/fm10k_type.h #define FM10K_VF_FLAG_ALLMULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI)) BIT 597 drivers/net/ethernet/intel/fm10k/fm10k_type.h #define FM10K_VF_FLAG_MULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_MULTI)) BIT 598 drivers/net/ethernet/intel/fm10k/fm10k_type.h #define FM10K_VF_FLAG_PROMISC_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_PROMISC)) BIT 599 drivers/net/ethernet/intel/fm10k/fm10k_type.h #define FM10K_VF_FLAG_NONE_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_NONE)) BIT 72 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) BIT 246 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_CLOUD_FIELD_OMAC BIT(0) BIT 247 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_CLOUD_FIELD_IMAC BIT(1) BIT 248 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_CLOUD_FIELD_IVLAN BIT(2) BIT 249 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_CLOUD_FIELD_TEN_ID BIT(3) BIT 250 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_CLOUD_FIELD_IIP BIT(4) BIT 522 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_RSS_AQ_CAPABLE BIT(0) BIT 523 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) BIT 524 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) BIT 525 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) BIT 526 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) BIT 527 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) BIT 528 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_100M_SGMII_CAPABLE BIT(6) BIT 529 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_NO_DCB_SUPPORT BIT(7) BIT 530 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_USE_SET_LLDP_MIB BIT(8) BIT 531 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) BIT 532 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_PTP_L4_CAPABLE BIT(10) BIT 533 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) BIT 534 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12) BIT 535 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_HAVE_CRT_RETIMER BIT(13) BIT 536 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) BIT 537 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) BIT 538 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_STOP_FW_LLDP BIT(16) BIT 539 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_PORT_ID_VALID BIT(17) BIT 540 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_HW_RESTART_AUTONEG BIT(18) BIT 543 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) BIT 544 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_MSI_ENABLED BIT(1) BIT 545 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_MSIX_ENABLED BIT(2) BIT 546 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_RSS_ENABLED BIT(3) BIT 547 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_VMDQ_ENABLED BIT(4) BIT 548 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_SRIOV_ENABLED BIT(5) BIT 549 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_DCB_CAPABLE BIT(6) BIT 550 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_DCB_ENABLED BIT(7) BIT 551 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_FD_SB_ENABLED BIT(8) BIT 552 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_FD_ATR_ENABLED BIT(9) BIT 553 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_MFP_ENABLED BIT(10) BIT 554 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) BIT 555 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) BIT 556 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) BIT 557 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) BIT 558 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) BIT 559 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_LEGACY_RX BIT(16) BIT 560 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_PTP BIT(17) BIT 561 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_IWARP_ENABLED BIT(18) BIT 562 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) BIT 563 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) BIT 564 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_TC_MQPRIO BIT(21) BIT 565 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_FD_SB_INACTIVE BIT(22) BIT 566 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) BIT 567 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) BIT 568 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_RS_FEC BIT(25) BIT 569 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_FLAG_BASE_R_FEC BIT(26) BIT 739 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) BIT 740 drivers/net/ethernet/intel/i40e/i40e.h #define I40E_VSI_FLAG_VEB_OWNER BIT(1) BIT 70 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ BIT 71 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ BIT 72 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ BIT 73 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ BIT 74 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ BIT 75 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ BIT 76 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ BIT 77 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ BIT 78 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ BIT 79 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ BIT 80 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ BIT 1526 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) BIT 1954 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), BIT 1955 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), BIT 1958 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), BIT 1959 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), BIT 1960 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), BIT 1961 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), BIT 2043 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) BIT 2044 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) BIT 2045 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) BIT 2046 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) BIT 2047 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_SET_FEC_AUTO BIT(4) BIT 2314 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) BIT 2316 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) BIT 2625 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) BIT 2629 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) BIT 2647 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) BIT 2710 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) BIT 2730 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) BIT 2736 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) BIT 57 drivers/net/ethernet/intel/i40e/i40e_client.c if (!(vsi->tc_config.enabled_tc & BIT(tc))) BIT 112 drivers/net/ethernet/intel/i40e/i40e_client.h #define I40E_CLIENT_VSI_FLAG_TCP_ENABLE BIT(1) BIT 187 drivers/net/ethernet/intel/i40e/i40e_client.h #define I40E_CLIENT_FLAGS_LAUNCH_ON_PROBE BIT(0) BIT 188 drivers/net/ethernet/intel/i40e/i40e_client.h #define I40E_TX_FLAGS_NOTIFY_OTHER_EVENTS BIT(2) BIT 1528 drivers/net/ethernet/intel/i40e/i40e_common.c gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); BIT 1530 drivers/net/ethernet/intel/i40e/i40e_common.c gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); BIT 378 drivers/net/ethernet/intel/i40e/i40e_dcb.c if (app->prio_map & BIT(up)) BIT 49 drivers/net/ethernet/intel/i40e/i40e_dcb.h #define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT) BIT 51 drivers/net/ethernet/intel/i40e/i40e_dcb.h #define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT) BIT 70 drivers/net/ethernet/intel/i40e/i40e_dcb.h #define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT) BIT 72 drivers/net/ethernet/intel/i40e/i40e_dcb.h #define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT) BIT 168 drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c tc_map = BIT(dcbxcfg->etscfg.prioritytable[prio]); BIT 1118 drivers/net/ethernet/intel/i40e/i40e_debugfs.c i40e_do_reset_safe(pf, BIT(__I40E_PF_RESET_REQUESTED)); BIT 1122 drivers/net/ethernet/intel/i40e/i40e_debugfs.c i40e_do_reset_safe(pf, BIT(__I40E_CORE_RESET_REQUESTED)); BIT 1126 drivers/net/ethernet/intel/i40e/i40e_debugfs.c i40e_do_reset_safe(pf, BIT(__I40E_GLOBAL_RESET_REQUESTED)); BIT 126 drivers/net/ethernet/intel/i40e/i40e_diag.c BIT(I40E_SR_CONTROL_WORD_1_SHIFT))) BIT 1850 drivers/net/ethernet/intel/i40e/i40e_ethtool.c val = (64 * 1024) * BIT(val); BIT 2424 drivers/net/ethernet/intel/i40e/i40e_ethtool.c info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); BIT 2426 drivers/net/ethernet/intel/i40e/i40e_ethtool.c info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT 2427 drivers/net/ethernet/intel/i40e/i40e_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | BIT 2428 drivers/net/ethernet/intel/i40e/i40e_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | BIT 2429 drivers/net/ethernet/intel/i40e/i40e_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ); BIT 2432 drivers/net/ethernet/intel/i40e/i40e_ethtool.c info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | BIT 2433 drivers/net/ethernet/intel/i40e/i40e_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | BIT 2434 drivers/net/ethernet/intel/i40e/i40e_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | BIT 2435 drivers/net/ethernet/intel/i40e/i40e_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | BIT 2436 drivers/net/ethernet/intel/i40e/i40e_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) | BIT 2437 drivers/net/ethernet/intel/i40e/i40e_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | BIT 2438 drivers/net/ethernet/intel/i40e/i40e_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | BIT 2439 drivers/net/ethernet/intel/i40e/i40e_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ); BIT 2562 drivers/net/ethernet/intel/i40e/i40e_ethtool.c i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true); BIT 2578 drivers/net/ethernet/intel/i40e/i40e_ethtool.c i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true); BIT 2610 drivers/net/ethernet/intel/i40e/i40e_ethtool.c if ((BIT(hw->port) & wol_nvm_bits) || (hw->partition_id != 1)) { BIT 2643 drivers/net/ethernet/intel/i40e/i40e_ethtool.c if (BIT(hw->port) & wol_nvm_bits) BIT 4847 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ret_flags |= BIT(i); BIT 4859 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ret_flags |= BIT(i + j); BIT 4889 drivers/net/ethernet/intel/i40e/i40e_ethtool.c if (flags & BIT(i)) BIT 4896 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ((orig_flags ^ new_flags) & ~BIT(i))) BIT 4908 drivers/net/ethernet/intel/i40e/i40e_ethtool.c if (flags & BIT(i + j)) BIT 4915 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ((orig_flags ^ new_flags) & ~BIT(i))) BIT 5071 drivers/net/ethernet/intel/i40e/i40e_ethtool.c i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true); BIT 107 drivers/net/ethernet/intel/i40e/i40e_hmc.h BIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \ BIT 743 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask = (u8)(BIT(ce_info->width) - 1); BIT 784 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask = BIT(ce_info->width) - 1; BIT 834 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask = BIT(ce_info->width) - 1; BIT 1701 drivers/net/ethernet/intel/i40e/i40e_main.c if (vsi->tc_config.enabled_tc & BIT(i)) { BIT 1785 drivers/net/ethernet/intel/i40e/i40e_main.c if (enabled_tc & BIT(i)) /* TC is enabled */ BIT 1807 drivers/net/ethernet/intel/i40e/i40e_main.c if (vsi->tc_config.enabled_tc & BIT(i)) { BIT 5014 drivers/net/ethernet/intel/i40e/i40e_main.c enabled_tc |= BIT(tc); BIT 5039 drivers/net/ethernet/intel/i40e/i40e_main.c num_tc |= BIT(dcbcfg->etscfg.prioritytable[i]); BIT 5045 drivers/net/ethernet/intel/i40e/i40e_main.c if (num_tc & BIT(i)) { BIT 5078 drivers/net/ethernet/intel/i40e/i40e_main.c enabled_tc |= BIT(i); BIT 5097 drivers/net/ethernet/intel/i40e/i40e_main.c enabled_tc |= BIT(i); BIT 5132 drivers/net/ethernet/intel/i40e/i40e_main.c if (enabled_tc & BIT(i)) BIT 5307 drivers/net/ethernet/intel/i40e/i40e_main.c if (vsi->tc_config.enabled_tc & BIT(i)) BIT 5375 drivers/net/ethernet/intel/i40e/i40e_main.c if (enabled_tc & BIT(i)) BIT 5944 drivers/net/ethernet/intel/i40e/i40e_main.c if (ch->enabled_tc & BIT(i)) BIT 6256 drivers/net/ethernet/intel/i40e/i40e_main.c if (vsi->tc_config.enabled_tc & BIT(i)) { BIT 6318 drivers/net/ethernet/intel/i40e/i40e_main.c if (enabled_tc & BIT(i)) BIT 7450 drivers/net/ethernet/intel/i40e/i40e_main.c enabled_tc |= BIT(i); BIT 7753 drivers/net/ethernet/intel/i40e/i40e_main.c ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | BIT 7754 drivers/net/ethernet/intel/i40e/i40e_main.c BIT(FLOW_DISSECTOR_KEY_BASIC) | BIT 7755 drivers/net/ethernet/intel/i40e/i40e_main.c BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | BIT 7756 drivers/net/ethernet/intel/i40e/i40e_main.c BIT(FLOW_DISSECTOR_KEY_VLAN) | BIT 7757 drivers/net/ethernet/intel/i40e/i40e_main.c BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | BIT 7758 drivers/net/ethernet/intel/i40e/i40e_main.c BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | BIT 7759 drivers/net/ethernet/intel/i40e/i40e_main.c BIT(FLOW_DISSECTOR_KEY_PORTS) | BIT 7760 drivers/net/ethernet/intel/i40e/i40e_main.c BIT(FLOW_DISSECTOR_KEY_ENC_KEYID))) { BIT 7958 drivers/net/ethernet/intel/i40e/i40e_main.c } else if (vsi->tc_config.enabled_tc & BIT(tc)) { BIT 9135 drivers/net/ethernet/intel/i40e/i40e_main.c reset_flags |= BIT(__I40E_REINIT_REQUESTED); BIT 9139 drivers/net/ethernet/intel/i40e/i40e_main.c reset_flags |= BIT(__I40E_PF_RESET_REQUESTED); BIT 9143 drivers/net/ethernet/intel/i40e/i40e_main.c reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED); BIT 9147 drivers/net/ethernet/intel/i40e/i40e_main.c reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED); BIT 9151 drivers/net/ethernet/intel/i40e/i40e_main.c reset_flags |= BIT(__I40E_DOWN_REQUESTED); BIT 11747 drivers/net/ethernet/intel/i40e/i40e_main.c bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id)); BIT 11865 drivers/net/ethernet/intel/i40e/i40e_main.c pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width); BIT 15020 drivers/net/ethernet/intel/i40e/i40e_main.c if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1) BIT 30 drivers/net/ethernet/intel/i40e/i40e_nvm.c nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; BIT 187 drivers/net/ethernet/intel/i40e/i40e_nvm.c BIT(I40E_GLNVM_SRCTL_START_SHIFT); BIT 23 drivers/net/ethernet/intel/i40e/i40e_ptp.c #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) BIT 249 drivers/net/ethernet/intel/i40e/i40e_ptp.c if (new_latch_events & BIT(i)) BIT 294 drivers/net/ethernet/intel/i40e/i40e_ptp.c if ((pf->latch_event_flags & BIT(i)) && BIT 297 drivers/net/ethernet/intel/i40e/i40e_ptp.c pf->latch_event_flags &= ~BIT(i); BIT 428 drivers/net/ethernet/intel/i40e/i40e_ptp.c if (!(prttsyn_stat & BIT(index))) { BIT 434 drivers/net/ethernet/intel/i40e/i40e_ptp.c pf->latch_event_flags &= ~BIT(index); BIT 543 drivers/net/ethernet/intel/i40e/i40e_txrx.c if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { BIT 589 drivers/net/ethernet/intel/i40e/i40e_txrx.c } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { BIT 1659 drivers/net/ethernet/intel/i40e/i40e_txrx.c if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) BIT 1672 drivers/net/ethernet/intel/i40e/i40e_txrx.c (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | BIT 1673 drivers/net/ethernet/intel/i40e/i40e_txrx.c BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) BIT 1678 drivers/net/ethernet/intel/i40e/i40e_txrx.c rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) BIT 1683 drivers/net/ethernet/intel/i40e/i40e_txrx.c if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) BIT 1690 drivers/net/ethernet/intel/i40e/i40e_txrx.c if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) BIT 1798 drivers/net/ethernet/intel/i40e/i40e_txrx.c if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) { BIT 1837 drivers/net/ethernet/intel/i40e/i40e_txrx.c BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { BIT 2169 drivers/net/ethernet/intel/i40e/i40e_txrx.c #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) BIT 37 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define INTRL_ENA BIT(6) BIT 267 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TX_FLAGS_HW_VLAN BIT(1) BIT 268 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TX_FLAGS_SW_VLAN BIT(2) BIT 269 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TX_FLAGS_TSO BIT(3) BIT 270 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TX_FLAGS_IPV4 BIT(4) BIT 271 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TX_FLAGS_IPV6 BIT(5) BIT 272 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TX_FLAGS_FCCRC BIT(6) BIT 273 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TX_FLAGS_FSO BIT(7) BIT 274 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TX_FLAGS_TSYN BIT(8) BIT 275 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TX_FLAGS_FD_SB BIT(9) BIT 276 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TX_FLAGS_UDP_TUNNEL BIT(10) BIT 390 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TXR_FLAGS_WB_ON_ITR BIT(0) BIT 391 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_RXR_FLAGS_BUILD_SKB_ENABLED BIT(1) BIT 392 drivers/net/ethernet/intel/i40e/i40e_txrx.h #define I40E_TXR_FLAGS_XDP BIT(2) BIT 24 drivers/net/ethernet/intel/i40e/i40e_txrx_common.h #define I40E_XDP_CONSUMED BIT(0) BIT 25 drivers/net/ethernet/intel/i40e/i40e_txrx_common.h #define I40E_XDP_TX BIT(1) BIT 26 drivers/net/ethernet/intel/i40e/i40e_txrx_common.h #define I40E_XDP_REDIR BIT(2) BIT 756 drivers/net/ethernet/intel/i40e/i40e_type.h #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \ BIT 1328 drivers/net/ethernet/intel/i40e/i40e_type.h #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) BIT 1329 drivers/net/ethernet/intel/i40e/i40e_type.h #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) BIT 1330 drivers/net/ethernet/intel/i40e/i40e_type.h #define I40E_PTR_TYPE BIT(15) BIT 1332 drivers/net/ethernet/intel/i40e/i40e_type.h #define I40E_SR_OCP_ENABLED BIT(15) BIT 311 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c linklistmap |= (BIT(I40E_VIRTCHNL_SUPPORTED_QTYPES * BIT 317 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c linklistmap |= (BIT(I40E_VIRTCHNL_SUPPORTED_QTYPES * BIT 363 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) | BIT 1271 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx)); BIT 1564 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx)); BIT 2334 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c vqs->rx_queues >= BIT(I40E_MAX_VF_QUEUES) || BIT 2335 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c vqs->tx_queues >= BIT(I40E_MAX_VF_QUEUES)) BIT 3911 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (reg & BIT(bit_idx)) BIT 251 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_RX_CSUM_ENABLED BIT(0) BIT 252 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_PF_COMMS_FAILED BIT(3) BIT 253 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_RESET_PENDING BIT(4) BIT 254 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_RESET_NEEDED BIT(5) BIT 255 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_WB_ON_ITR_CAPABLE BIT(6) BIT 256 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_SERVICE_CLIENT_REQUESTED BIT(9) BIT 257 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_CLIENT_NEEDS_OPEN BIT(10) BIT 258 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_CLIENT_NEEDS_CLOSE BIT(11) BIT 259 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_CLIENT_NEEDS_L2_PARAMS BIT(12) BIT 260 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_PROMISC_ON BIT(13) BIT 261 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_ALLMULTI_ON BIT(14) BIT 262 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_LEGACY_RX BIT(15) BIT 263 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_REINIT_ITR_NEEDED BIT(16) BIT 264 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_QUEUES_DISABLED BIT(17) BIT 269 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_ENABLE_QUEUES BIT(0) BIT 270 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_DISABLE_QUEUES BIT(1) BIT 271 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_ADD_MAC_FILTER BIT(2) BIT 272 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_ADD_VLAN_FILTER BIT(3) BIT 273 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_DEL_MAC_FILTER BIT(4) BIT 274 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_DEL_VLAN_FILTER BIT(5) BIT 275 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_CONFIGURE_QUEUES BIT(6) BIT 276 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_MAP_VECTORS BIT(7) BIT 277 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_HANDLE_RESET BIT(8) BIT 278 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_CONFIGURE_RSS BIT(9) /* direct AQ config */ BIT 279 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_GET_CONFIG BIT(10) BIT 281 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_GET_HENA BIT(11) BIT 282 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_SET_HENA BIT(12) BIT 283 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_SET_RSS_KEY BIT(13) BIT 284 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_SET_RSS_LUT BIT(14) BIT 285 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_REQUEST_PROMISC BIT(15) BIT 286 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_RELEASE_PROMISC BIT(16) BIT 287 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_REQUEST_ALLMULTI BIT(17) BIT 288 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_RELEASE_ALLMULTI BIT(18) BIT 289 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_ENABLE_VLAN_STRIPPING BIT(19) BIT 290 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_DISABLE_VLAN_STRIPPING BIT(20) BIT 291 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_ENABLE_CHANNELS BIT(21) BIT 292 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_DISABLE_CHANNELS BIT(22) BIT 293 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_ADD_CLOUD_FILTER BIT(23) BIT 294 drivers/net/ethernet/intel/iavf/iavf.h #define IAVF_FLAG_AQ_DEL_CLOUD_FILTER BIT(24) BIT 66 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_DD BIT(IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */ BIT 67 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_CMP BIT(IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */ BIT 68 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_ERR BIT(IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */ BIT 69 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_VFE BIT(IAVF_AQ_FLAG_VFE_SHIFT) /* 0x8 */ BIT 70 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_LB BIT(IAVF_AQ_FLAG_LB_SHIFT) /* 0x200 */ BIT 71 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_RD BIT(IAVF_AQ_FLAG_RD_SHIFT) /* 0x400 */ BIT 72 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_VFC BIT(IAVF_AQ_FLAG_VFC_SHIFT) /* 0x800 */ BIT 73 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_BUF BIT(IAVF_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ BIT 74 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_SI BIT(IAVF_AQ_FLAG_SI_SHIFT) /* 0x2000 */ BIT 75 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_EI BIT(IAVF_AQ_FLAG_EI_SHIFT) /* 0x4000 */ BIT 76 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQ_FLAG_FE BIT(IAVF_AQ_FLAG_FE_SHIFT) /* 0x8000 */ BIT 468 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h IAVF_LINK_SPEED_100MB = BIT(IAVF_LINK_SPEED_100MB_SHIFT), BIT 469 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h IAVF_LINK_SPEED_1GB = BIT(IAVF_LINK_SPEED_1000MB_SHIFT), BIT 470 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h IAVF_LINK_SPEED_10GB = BIT(IAVF_LINK_SPEED_10GB_SHIFT), BIT 471 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h IAVF_LINK_SPEED_40GB = BIT(IAVF_LINK_SPEED_40GB_SHIFT), BIT 472 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h IAVF_LINK_SPEED_20GB = BIT(IAVF_LINK_SPEED_20GB_SHIFT), BIT 473 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h IAVF_LINK_SPEED_25GB = BIT(IAVF_LINK_SPEED_25GB_SHIFT), BIT 490 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQC_SET_RSS_KEY_VSI_VALID BIT(15) BIT 510 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h #define IAVF_AQC_SET_RSS_LUT_VSI_VALID BIT(15) BIT 517 drivers/net/ethernet/intel/iavf/iavf_adminq_cmd.h BIT(IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) BIT 475 drivers/net/ethernet/intel/iavf/iavf_client.c adapter->client_pending |= BIT(VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP); BIT 491 drivers/net/ethernet/intel/iavf/iavf_client.c BIT(VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP))) { BIT 159 drivers/net/ethernet/intel/iavf/iavf_client.h #define IAVF_CLIENT_FLAGS_LAUNCH_ON_PROBE BIT(0) BIT 160 drivers/net/ethernet/intel/iavf/iavf_client.h #define IAVF_TX_FLAGS_NOTIFY_OTHER_EVENTS BIT(2) BIT 450 drivers/net/ethernet/intel/iavf/iavf_ethtool.c ret_flags |= BIT(i); BIT 475 drivers/net/ethernet/intel/iavf/iavf_ethtool.c if (flags & BIT(i)) BIT 481 drivers/net/ethernet/intel/iavf/iavf_ethtool.c ((orig_flags ^ new_flags) & ~BIT(i))) BIT 233 drivers/net/ethernet/intel/iavf/iavf_main.c if (mask & BIT(i - 1)) { BIT 315 drivers/net/ethernet/intel/iavf/iavf_main.c q_vector->ring_mask |= BIT(r_idx); BIT 2702 drivers/net/ethernet/intel/iavf/iavf_main.c ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | BIT 2703 drivers/net/ethernet/intel/iavf/iavf_main.c BIT(FLOW_DISSECTOR_KEY_BASIC) | BIT 2704 drivers/net/ethernet/intel/iavf/iavf_main.c BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | BIT 2705 drivers/net/ethernet/intel/iavf/iavf_main.c BIT(FLOW_DISSECTOR_KEY_VLAN) | BIT 2706 drivers/net/ethernet/intel/iavf/iavf_main.c BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | BIT 2707 drivers/net/ethernet/intel/iavf/iavf_main.c BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | BIT 2708 drivers/net/ethernet/intel/iavf/iavf_main.c BIT(FLOW_DISSECTOR_KEY_PORTS) | BIT 2709 drivers/net/ethernet/intel/iavf/iavf_main.c BIT(FLOW_DISSECTOR_KEY_ENC_KEYID))) { BIT 3701 drivers/net/ethernet/intel/iavf/iavf_main.c adapter->msg_enable = BIT(DEFAULT_DEBUG_LEVEL_SHIFT) - 1; BIT 970 drivers/net/ethernet/intel/iavf/iavf_txrx.c if (!(rx_status & BIT(IAVF_RX_DESC_STATUS_L3L4P_SHIFT))) BIT 983 drivers/net/ethernet/intel/iavf/iavf_txrx.c (rx_error & (BIT(IAVF_RX_DESC_ERROR_IPE_SHIFT) | BIT 984 drivers/net/ethernet/intel/iavf/iavf_txrx.c BIT(IAVF_RX_DESC_ERROR_EIPE_SHIFT)))) BIT 989 drivers/net/ethernet/intel/iavf/iavf_txrx.c rx_status & BIT(IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT)) BIT 994 drivers/net/ethernet/intel/iavf/iavf_txrx.c if (rx_error & BIT(IAVF_RX_DESC_ERROR_L4E_SHIFT)) BIT 1001 drivers/net/ethernet/intel/iavf/iavf_txrx.c if (rx_error & BIT(IAVF_RX_DESC_ERROR_PPRS_SHIFT)) BIT 1457 drivers/net/ethernet/intel/iavf/iavf_txrx.c #define IAVF_RXD_EOF BIT(IAVF_RX_DESC_STATUS_EOF_SHIFT) BIT 1514 drivers/net/ethernet/intel/iavf/iavf_txrx.c #define IAVF_RXD_DD BIT(IAVF_RX_DESC_STATUS_DD_SHIFT) BIT 1551 drivers/net/ethernet/intel/iavf/iavf_txrx.c if (unlikely(iavf_test_staterr(rx_desc, BIT(IAVF_RXD_QW1_ERROR_SHIFT)))) { BIT 1573 drivers/net/ethernet/intel/iavf/iavf_txrx.c vlan_tag = (qword & BIT(IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? BIT 35 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define INTRL_ENA BIT(6) BIT 246 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_TX_FLAGS_HW_VLAN BIT(1) BIT 247 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_TX_FLAGS_SW_VLAN BIT(2) BIT 248 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_TX_FLAGS_TSO BIT(3) BIT 249 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_TX_FLAGS_IPV4 BIT(4) BIT 250 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_TX_FLAGS_IPV6 BIT(5) BIT 251 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_TX_FLAGS_FCCRC BIT(6) BIT 252 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_TX_FLAGS_FSO BIT(7) BIT 253 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_TX_FLAGS_FD_SB BIT(9) BIT 254 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_TX_FLAGS_VXLAN_TUNNEL BIT(10) BIT 363 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_TXR_FLAGS_WB_ON_ITR BIT(0) BIT 364 drivers/net/ethernet/intel/iavf/iavf_txrx.h #define IAVF_RXR_FLAGS_BUILD_SKB_ENABLED BIT(1) BIT 305 drivers/net/ethernet/intel/iavf/iavf_type.h #define IAVF_RXD_QW1_STATUS_MASK ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \ BIT 311 drivers/net/ethernet/intel/iavf/iavf_virtchnl.c vqs.tx_queues = BIT(adapter->num_active_queues) - 1; BIT 336 drivers/net/ethernet/intel/iavf/iavf_virtchnl.c vqs.tx_queues = BIT(adapter->num_active_queues) - 1; BIT 1401 drivers/net/ethernet/intel/iavf/iavf_virtchnl.c ~(BIT(VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP)); BIT 55 drivers/net/ethernet/intel/ice/ice.h #define ICE_DFLT_TRAFFIC_CLASS BIT(0) BIT 50 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_DRIVER_UNLOADING BIT(0) BIT 129 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) BIT 130 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) BIT 131 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) BIT 132 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) BIT 155 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) BIT 156 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) BIT 160 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) BIT 216 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) BIT 275 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_IS_VALID BIT(15) BIT 307 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) BIT 308 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) BIT 309 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) BIT 310 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) BIT 311 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) BIT 312 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) BIT 313 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) BIT 314 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) BIT 315 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) BIT 316 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) BIT 317 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) BIT 321 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) BIT 322 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) BIT 323 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) BIT 328 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) BIT 329 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) BIT 333 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) BIT 336 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) BIT 337 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) BIT 340 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) BIT 351 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) BIT 392 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) BIT 393 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) BIT 398 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) BIT 425 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) BIT 427 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) BIT 435 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_FD_ENABLE BIT(0) BIT 436 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) BIT 437 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) BIT 450 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) BIT 455 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) BIT 494 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) BIT 495 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) BIT 505 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_SINGLE_ACT_VSI_LIST BIT(14) BIT 506 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_SINGLE_ACT_VALID_BIT BIT(17) BIT 507 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_SINGLE_ACT_DROP BIT(18) BIT 515 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) BIT 519 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_SINGLE_ACT_EGRESS BIT(15) BIT 520 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_SINGLE_ACT_INGRESS BIT(16) BIT 521 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_SINGLE_ACT_PRUNET BIT(17) BIT 529 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_SINGLE_ACT_PTR_BIT BIT(18) BIT 581 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_LG_ACT_VSI_LIST BIT(13) BIT 583 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_LG_ACT_VALID_BIT BIT(16) BIT 591 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) BIT 595 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_LG_ACT_EGRESS BIT(14) BIT 596 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_LG_ACT_INGRESS BIT(15) BIT 597 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_LG_ACT_PRUNET BIT(16) BIT 707 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) BIT 708 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_ELEM_VALID_CIR BIT(1) BIT 709 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_ELEM_VALID_EIR BIT(2) BIT 710 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_ELEM_VALID_SHARED BIT(3) BIT 831 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_GET_PHY_RQM BIT(0) BIT 840 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_REPORT_TOPO_CAP BIT(1) BIT 841 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_REPORT_SW_CFG BIT(2) BIT 927 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) BIT 928 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) BIT 929 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) BIT 930 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EN_LINK BIT(3) BIT 931 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_AN_MODE BIT(4) BIT 932 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) BIT 933 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) BIT 936 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) BIT 938 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) BIT 939 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) BIT 940 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) BIT 941 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) BIT 942 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) BIT 943 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) BIT 944 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) BIT 949 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) BIT 950 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) BIT 951 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) BIT 952 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) BIT 953 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) BIT 954 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) BIT 955 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) BIT 963 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) BIT 964 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) BIT 965 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) BIT 966 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) BIT 967 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) BIT 968 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) BIT 999 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) BIT 1000 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) BIT 1001 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) BIT 1002 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_PHY_ENA_LINK BIT(3) BIT 1003 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) BIT 1004 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_PHY_ENA_LESM BIT(6) BIT 1005 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) BIT 1020 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) BIT 1021 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) BIT 1044 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) BIT 1045 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) BIT 1046 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) BIT 1049 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ BIT 1050 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_FAULT BIT(1) BIT 1051 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_FAULT_TX BIT(2) BIT 1052 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_FAULT_RX BIT(3) BIT 1053 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) BIT 1054 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ BIT 1055 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_MEDIA_AVAILABLE BIT(6) BIT 1056 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_SIGNAL_DETECT BIT(7) BIT 1058 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_AN_COMPLETED BIT(0) BIT 1059 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LP_AN_ABILITY BIT(1) BIT 1060 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ BIT 1061 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_FEC_EN BIT(3) BIT 1062 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ BIT 1063 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_PAUSE_TX BIT(5) BIT 1064 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_PAUSE_RX BIT(6) BIT 1065 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_QUALIFIED_MODULE BIT(7) BIT 1067 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) BIT 1068 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ BIT 1078 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) BIT 1079 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) BIT 1080 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) BIT 1085 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) BIT 1098 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_10MB BIT(0) BIT 1099 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_100MB BIT(1) BIT 1100 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_1000MB BIT(2) BIT 1101 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_2500MB BIT(3) BIT 1102 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_5GB BIT(4) BIT 1103 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_10GB BIT(5) BIT 1104 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_20GB BIT(6) BIT 1105 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_25GB BIT(7) BIT 1106 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_40GB BIT(8) BIT 1107 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_50GB BIT(9) BIT 1108 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_100GB BIT(10) BIT 1109 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) BIT 1120 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) BIT 1121 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) BIT 1122 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) BIT 1123 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) BIT 1124 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) BIT 1125 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) BIT 1126 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) BIT 1127 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) BIT 1128 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) BIT 1135 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_MAC_LB_EN BIT(0) BIT 1136 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) BIT 1145 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) BIT 1158 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_NVM_LAST_CMD BIT(0) BIT 1159 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ BIT 1163 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) BIT 1165 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_NVM_FLASH_ONLY BIT(7) BIT 1176 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) BIT 1177 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) BIT 1242 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) BIT 1245 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) BIT 1252 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LLDP_AGENT_START BIT(0) BIT 1253 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) BIT 1292 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) BIT 1294 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) BIT 1311 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_START_STOP_AGENT_M BIT(0) BIT 1319 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) BIT 1341 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) BIT 1413 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) BIT 1416 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) BIT 1417 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) BIT 1461 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_AQ_EN BIT(0) BIT 1462 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_UART_EN BIT(1) BIT 1465 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) BIT 1466 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_UART_VALID BIT(1) BIT 1513 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ BIT 1517 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ BIT 1518 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ BIT 1519 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ BIT 1520 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ BIT 1526 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_CLEAR BIT(0) BIT 1527 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) BIT 1662 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ BIT 1663 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ BIT 1664 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ BIT 1665 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ BIT 1666 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ BIT 1914 drivers/net/ethernet/intel/ice/ice_common.c if (valid_func & BIT(i)) BIT 2948 drivers/net/ethernet/intel/ice/ice_common.c mask = (u8)(BIT(ce_info->width) - 1); BIT 2988 drivers/net/ethernet/intel/ice/ice_common.c mask = BIT(ce_info->width) - 1; BIT 3037 drivers/net/ethernet/intel/ice/ice_common.c mask = BIT(ce_info->width) - 1; BIT 513 drivers/net/ethernet/intel/ice/ice_dcb.c if (app->prio_map & BIT(up)) BIT 1094 drivers/net/ethernet/intel/ice/ice_dcb.c maxtcwilling = BIT(ICE_IEEE_ETS_WILLING_S); BIT 1162 drivers/net/ethernet/intel/ice/ice_dcb.c buf[0] = BIT(ICE_IEEE_PFC_WILLING_S); BIT 1165 drivers/net/ethernet/intel/ice/ice_dcb.c buf[0] |= BIT(ICE_IEEE_PFC_MBC_S); BIT 43 drivers/net/ethernet/intel/ice/ice_dcb.h #define ICE_IEEE_ETS_CBS_M BIT(ICE_IEEE_ETS_CBS_S) BIT 45 drivers/net/ethernet/intel/ice/ice_dcb.h #define ICE_IEEE_ETS_WILLING_M BIT(ICE_IEEE_ETS_WILLING_S) BIT 64 drivers/net/ethernet/intel/ice/ice_dcb.h #define ICE_IEEE_PFC_MBC_M BIT(ICE_IEEE_PFC_MBC_S) BIT 66 drivers/net/ethernet/intel/ice/ice_dcb.h #define ICE_IEEE_PFC_WILLING_M BIT(ICE_IEEE_PFC_WILLING_S) BIT 33 drivers/net/ethernet/intel/ice/ice_dcb_lib.c if (vsi->tc_cfg.ena_tc & BIT(i)) BIT 59 drivers/net/ethernet/intel/ice/ice_dcb_lib.c ena_tc |= BIT(i); BIT 79 drivers/net/ethernet/intel/ice/ice_dcb_lib.c num_tc |= BIT(dcbcfg->etscfg.prio_table[i]); BIT 83 drivers/net/ethernet/intel/ice/ice_dcb_lib.c if (num_tc & BIT(i)) { BIT 126 drivers/net/ethernet/intel/ice/ice_dcb_lib.c if (!(vsi->tc_cfg.ena_tc & BIT(n))) BIT 1139 drivers/net/ethernet/intel/ice/ice_ethtool.c ret_flags |= BIT(i); BIT 1160 drivers/net/ethernet/intel/ice/ice_ethtool.c if (flags > BIT(ICE_PRIV_FLAG_ARRAY_SIZE)) BIT 1171 drivers/net/ethernet/intel/ice/ice_ethtool.c if (flags & BIT(i)) BIT 22 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_FW_ARQLEN_ARQVFE_M BIT(28) BIT 23 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_FW_ARQLEN_ARQOVFL_M BIT(29) BIT 24 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_FW_ARQLEN_ARQCRIT_M BIT(30) BIT 25 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_FW_ARQLEN_ARQENABLE_M BIT(31) BIT 33 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_FW_ATQLEN_ATQVFE_M BIT(28) BIT 34 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_FW_ATQLEN_ATQOVFL_M BIT(29) BIT 35 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_FW_ATQLEN_ATQCRIT_M BIT(30) BIT 37 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_FW_ATQLEN_ATQENABLE_M BIT(31) BIT 45 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31) BIT 53 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_MBX_ATQLEN_ATQENABLE_M BIT(31) BIT 102 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLGEN_RTRIG_CORER_M BIT(0) BIT 103 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLGEN_RTRIG_GLOBR_M BIT(1) BIT 107 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFGEN_CTRL_PFSWR_M BIT(0) BIT 112 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VPGEN_VFRSTAT_VFRD_M BIT(0) BIT 114 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VPGEN_VFRTRIG_VFSWR_M BIT(0) BIT 118 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLINT_CTL_DIS_AUTOMASK_M BIT(0) BIT 128 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLINT_DYN_CTL_INTENA_M BIT(0) BIT 129 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLINT_DYN_CTL_CLEARPBA_M BIT(1) BIT 130 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2) BIT 136 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30) BIT 137 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLINT_DYN_CTL_INTENA_MSK_M BIT(31) BIT 140 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLINT_RATE_INTRL_ENA_M BIT(6) BIT 147 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLINT_VECT2FUNC_IS_PF_M BIT(16) BIT 152 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_FW_CTL_CAUSE_ENA_M BIT(30) BIT 157 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30) BIT 159 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_OICR_ECC_ERR_M BIT(16) BIT 160 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_OICR_MAL_DETECT_M BIT(19) BIT 161 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_OICR_GRST_M BIT(20) BIT 162 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_OICR_PCI_EXCEPTION_M BIT(21) BIT 163 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_OICR_HMC_ERR_M BIT(26) BIT 164 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_OICR_PE_CRITERR_M BIT(28) BIT 165 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_OICR_VFLR_M BIT(29) BIT 166 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_OICR_SWINT_M BIT(31) BIT 171 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30) BIT 178 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define QINT_RQCTL_CAUSE_ENA_M BIT(30) BIT 184 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define QINT_TQCTL_CAUSE_ENA_M BIT(30) BIT 190 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VPINT_ALLOC_VALID_M BIT(31) BIT 196 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VPINT_ALLOC_PCI_VALID_M BIT(31) BIT 198 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30) BIT 204 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define QRX_CTRL_QENA_REQ_M BIT(0) BIT 206 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define QRX_CTRL_QENA_STAT_M BIT(2) BIT 218 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0) BIT 225 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0) BIT 235 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GL_MDET_RX_VALID_M BIT(31) BIT 245 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GL_MDET_TX_PQM_VALID_M BIT(31) BIT 255 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GL_MDET_TX_TCLAN_VALID_M BIT(31) BIT 257 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_MDET_RX_VALID_M BIT(0) BIT 259 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_MDET_TX_PQM_VALID_M BIT(0) BIT 261 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define PF_MDET_TX_TCLAN_VALID_M BIT(0) BIT 263 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VP_MDET_RX_VALID_M BIT(0) BIT 265 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VP_MDET_TX_PQM_VALID_M BIT(0) BIT 267 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VP_MDET_TX_TCLAN_VALID_M BIT(0) BIT 269 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VP_MDET_TX_TDPU_VALID_M BIT(0) BIT 271 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLNVM_FLA_LOCKED_M BIT(6) BIT 276 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLNVM_ULD_PCIER_DONE_M BIT(0) BIT 277 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLNVM_ULD_PCIER_DONE_1_M BIT(1) BIT 278 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLNVM_ULD_CORER_DONE_M BIT(3) BIT 279 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLNVM_ULD_GLOBR_DONE_M BIT(4) BIT 280 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLNVM_ULD_POR_DONE_M BIT(5) BIT 281 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLNVM_ULD_POR_DONE_1_M BIT(8) BIT 282 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLNVM_ULD_PCIER_DONE_2_M BIT(9) BIT 283 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLNVM_ULD_PE_DONE_M BIT(10) BIT 285 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1) BIT 350 drivers/net/ethernet/intel/ice/ice_hw_autogen.h #define VFINT_DYN_CTLN_CLEARPBA_M BIT(1) BIT 802 drivers/net/ethernet/intel/ice/ice_lib.c BIT(cap->rss_table_entry_width)); BIT 811 drivers/net/ethernet/intel/ice/ice_lib.c BIT(cap->rss_table_entry_width)); BIT 881 drivers/net/ethernet/intel/ice/ice_lib.c if (!(vsi->tc_cfg.ena_tc & BIT(0))) BIT 929 drivers/net/ethernet/intel/ice/ice_lib.c if (!(vsi->tc_cfg.ena_tc & BIT(i))) { BIT 1796 drivers/net/ethernet/intel/ice/ice_lib.c if (!(vsi->tc_cfg.ena_tc & BIT(tc))) BIT 2259 drivers/net/ethernet/intel/ice/ice_lib.c if (!(vsi->tc_cfg.ena_tc & BIT(tc))) BIT 3207 drivers/net/ethernet/intel/ice/ice_lib.c if (ena_tc & BIT(i)) BIT 2804 drivers/net/ethernet/intel/ice/ice_main.c err = pcim_iomap_regions(pdev, BIT(ICE_BAR0), pci_name(pdev)); BIT 258 drivers/net/ethernet/intel/ice/ice_nvm.c nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB; BIT 11 drivers/net/ethernet/intel/ice/ice_switch.h #define ICE_FLTR_RX BIT(0) BIT 12 drivers/net/ethernet/intel/ice/ice_switch.h #define ICE_FLTR_TX BIT(1) BIT 834 drivers/net/ethernet/intel/ice/ice_txrx.c #define ICE_RXD_EOF BIT(ICE_RX_FLEX_DESC_STATUS0_EOF_S) BIT 912 drivers/net/ethernet/intel/ice/ice_txrx.c if (!(rx_status & BIT(ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))) BIT 923 drivers/net/ethernet/intel/ice/ice_txrx.c if (ipv4 && (rx_error & (BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | BIT 924 drivers/net/ethernet/intel/ice/ice_txrx.c BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))) BIT 927 drivers/net/ethernet/intel/ice/ice_txrx.c (BIT(ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S)))) BIT 933 drivers/net/ethernet/intel/ice/ice_txrx.c if (rx_error & BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)) BIT 1029 drivers/net/ethernet/intel/ice/ice_txrx.c stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_DD_S); BIT 1065 drivers/net/ethernet/intel/ice/ice_txrx.c stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_RXE_S); BIT 1071 drivers/net/ethernet/intel/ice/ice_txrx.c stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S); BIT 44 drivers/net/ethernet/intel/ice/ice_txrx.h #define ICE_TX_FLAGS_TSO BIT(0) BIT 45 drivers/net/ethernet/intel/ice/ice_txrx.h #define ICE_TX_FLAGS_HW_VLAN BIT(1) BIT 46 drivers/net/ethernet/intel/ice/ice_txrx.h #define ICE_TX_FLAGS_SW_VLAN BIT(2) BIT 134 drivers/net/ethernet/intel/ice/ice_txrx.h #define ICE_ITR_GRAN_US BIT(ICE_ITR_GRAN_S) BIT 349 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx)); BIT 407 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx)); BIT 1495 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c if (reg & BIT(bit_idx)) BIT 347 drivers/net/ethernet/intel/igb/e1000_82575.c nvm->word_size = BIT(size); BIT 366 drivers/net/ethernet/intel/igb/e1000_82575.c if (nvm->word_size == BIT(15)) BIT 377 drivers/net/ethernet/intel/igb/e1000_82575.c if (nvm->word_size < BIT(15)) BIT 2093 drivers/net/ethernet/intel/igb/e1000_82575.c reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS)); BIT 151 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */ BIT 152 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */ BIT 153 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */ BIT 154 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */ BIT 157 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ BIT 158 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ BIT 159 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */ BIT 160 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ BIT 169 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_ETQF_FILTER_ENABLE BIT(26) BIT 170 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_ETQF_1588 BIT(30) BIT 171 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_ETQF_IMM_INT BIT(29) BIT 172 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_ETQF_QUEUE_ENABLE BIT(31) BIT 191 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31) /* global VF LB enable */ BIT 198 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_VT_CTL_IGNORE_MAC BIT(28) BIT 199 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_VT_CTL_DISABLE_DEF_POOL BIT(29) BIT 200 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_VT_CTL_VM_REPL_EN BIT(30) BIT 240 drivers/net/ethernet/intel/igb/e1000_82575.h #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT BIT(14) BIT 551 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSINTR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */ BIT 552 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSINTR_TXTS BIT(1) /* Transmit Timestamp. */ BIT 553 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSINTR_RXTS BIT(2) /* Receive Timestamp. */ BIT 554 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSINTR_TT0 BIT(3) /* Target Time 0 Trigger. */ BIT 555 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSINTR_TT1 BIT(4) /* Target Time 1 Trigger. */ BIT 556 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSINTR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */ BIT 557 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSINTR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */ BIT 558 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSINTR_TADJ BIT(7) /* Time Adjust Done. */ BIT 564 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */ BIT 565 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */ BIT 566 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */ BIT 567 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_SAMP_AUT0 BIT(3) /* Latch SYSTIML/H into AUXSTMPL/0. */ BIT 568 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_ST0 BIT(4) /* Start Clock 0 Toggle on Target Time 0. */ BIT 569 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */ BIT 570 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_SAMP_AUT1 BIT(6) /* Latch SYSTIML/H into AUXSTMPL/1. */ BIT 571 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */ BIT 572 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */ BIT 573 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_AUTT0 BIT(9) /* Auxiliary Timestamp Taken. */ BIT 574 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */ BIT 575 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_AUTT1 BIT(11) /* Auxiliary Timestamp Taken. */ BIT 576 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_PLSG BIT(17) /* Generate a pulse. */ BIT 577 drivers/net/ethernet/intel/igb/e1000_defines.h #define TSAUXC_DISABLE BIT(31) /* Disable SYSTIM Count Operation. */ BIT 1019 drivers/net/ethernet/intel/igb/e1000_defines.h #define E1000_EEE_ADV_100_SUPPORTED BIT(1) /* 100BaseTx EEE Supported */ BIT 1020 drivers/net/ethernet/intel/igb/e1000_defines.h #define E1000_EEE_ADV_1000_SUPPORTED BIT(2) /* 1000BaseT EEE Supported */ BIT 1051 drivers/net/ethernet/intel/igb/e1000_defines.h #define E1000_TQAVCTRL_XMIT_MODE BIT(0) BIT 1052 drivers/net/ethernet/intel/igb/e1000_defines.h #define E1000_TQAVCTRL_DATAFETCHARB BIT(4) BIT 1053 drivers/net/ethernet/intel/igb/e1000_defines.h #define E1000_TQAVCTRL_DATATRANARB BIT(8) BIT 1054 drivers/net/ethernet/intel/igb/e1000_defines.h #define E1000_TQAVCTRL_DATATRANTIM BIT(9) BIT 1055 drivers/net/ethernet/intel/igb/e1000_defines.h #define E1000_TQAVCTRL_SP_WAIT_SR BIT(10) BIT 1073 drivers/net/ethernet/intel/igb/e1000_defines.h #define E1000_TQAVCC_QUEUEMODE BIT(31) BIT 1076 drivers/net/ethernet/intel/igb/e1000_defines.h #define E1000_TXDCTL_PRIORITY BIT(27) BIT 195 drivers/net/ethernet/intel/igb/e1000_mac.c vfta_delta = BIT(vlan % 32); BIT 226 drivers/net/ethernet/intel/igb/e1000_mac.c bits |= BIT(E1000_VLVF_POOLSEL_SHIFT + vind); BIT 231 drivers/net/ethernet/intel/igb/e1000_mac.c bits ^= BIT(E1000_VLVF_POOLSEL_SHIFT + vind); BIT 410 drivers/net/ethernet/intel/igb/e1000_mac.c mta |= BIT(hash_bit); BIT 510 drivers/net/ethernet/intel/igb/e1000_mac.c hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit); BIT 304 drivers/net/ethernet/intel/igb/e1000_mbx.c if (vflre & BIT(vf_number)) { BIT 306 drivers/net/ethernet/intel/igb/e1000_mbx.c wr32(E1000_VFLRE, BIT(vf_number)); BIT 74 drivers/net/ethernet/intel/igb/e1000_phy.h #define I82580_CFG_ASSERT_CRS_ON_TX BIT(15) BIT 600 drivers/net/ethernet/intel/igb/igb.h #define IGB_PTP_ENABLED BIT(0) BIT 601 drivers/net/ethernet/intel/igb/igb.h #define IGB_PTP_OVERFLOW_CHECK BIT(1) BIT 603 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_HAS_MSI BIT(0) BIT 604 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_DCA_ENABLED BIT(1) BIT 605 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_QUAD_PORT_A BIT(2) BIT 606 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_QUEUE_PAIRS BIT(3) BIT 607 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_DMAC BIT(4) BIT 608 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6) BIT 609 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7) BIT 610 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_WOL_SUPPORTED BIT(8) BIT 611 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_NEED_LINK_UPDATE BIT(9) BIT 612 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_MEDIA_RESET BIT(10) BIT 613 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_MAS_CAPABLE BIT(11) BIT 614 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_MAS_ENABLE BIT(12) BIT 615 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_HAS_MSIX BIT(13) BIT 616 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_EEE BIT(14) BIT 617 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_VLAN_PROMISC BIT(15) BIT 618 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_RX_LEGACY BIT(16) BIT 619 drivers/net/ethernet/intel/igb/igb.h #define IGB_FLAG_FQTSS BIT(17) BIT 129 drivers/net/ethernet/intel/igb/igb_ethtool.c #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0) BIT 1452 drivers/net/ethernet/intel/igb/igb_ethtool.c mask = BIT(i); BIT 2430 drivers/net/ethernet/intel/igb/igb_ethtool.c BIT(HWTSTAMP_TX_OFF) | BIT 2431 drivers/net/ethernet/intel/igb/igb_ethtool.c BIT(HWTSTAMP_TX_ON); BIT 2433 drivers/net/ethernet/intel/igb/igb_ethtool.c info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); BIT 2437 drivers/net/ethernet/intel/igb/igb_ethtool.c info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); BIT 2440 drivers/net/ethernet/intel/igb/igb_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | BIT 2441 drivers/net/ethernet/intel/igb/igb_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | BIT 2442 drivers/net/ethernet/intel/igb/igb_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); BIT 833 drivers/net/ethernet/intel/igb/igb_main.c q_vector->eims_value = BIT(msix_vector); BIT 854 drivers/net/ethernet/intel/igb/igb_main.c q_vector->eims_value = BIT(msix_vector); BIT 916 drivers/net/ethernet/intel/igb/igb_main.c adapter->eims_other = BIT(vector); BIT 2592 drivers/net/ethernet/intel/igb/igb_main.c ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | BIT 2593 drivers/net/ethernet/intel/igb/igb_main.c BIT(FLOW_DISSECTOR_KEY_CONTROL) | BIT 2594 drivers/net/ethernet/intel/igb/igb_main.c BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | BIT 2595 drivers/net/ethernet/intel/igb/igb_main.c BIT(FLOW_DISSECTOR_KEY_VLAN))) { BIT 4885 drivers/net/ethernet/intel/igb/igb_main.c vlvf |= BIT(pf_id); BIT 4912 drivers/net/ethernet/intel/igb/igb_main.c vfta[(vid - vid_start) / 32] |= BIT(vid % 32); BIT 4931 drivers/net/ethernet/intel/igb/igb_main.c vfta[(vid - vid_start) / 32] |= BIT(vid % 32); BIT 4939 drivers/net/ethernet/intel/igb/igb_main.c bits = ~BIT(pf_id); BIT 5109 drivers/net/ethernet/intel/igb/igb_main.c if (adapter->wvbr & BIT(j) || BIT 5110 drivers/net/ethernet/intel/igb/igb_main.c adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { BIT 5114 drivers/net/ethernet/intel/igb/igb_main.c ~(BIT(j) | BIT 5115 drivers/net/ethernet/intel/igb/igb_main.c BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); BIT 6849 drivers/net/ethernet/intel/igb/igb_main.c vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); BIT 6852 drivers/net/ethernet/intel/igb/igb_main.c pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + BIT 6876 drivers/net/ethernet/intel/igb/igb_main.c vfta_mask = BIT(vid % 32); BIT 6927 drivers/net/ethernet/intel/igb/igb_main.c bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; BIT 6933 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_VLVF(idx), BIT(pf_id)); BIT 7119 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_VFTE, reg | BIT(vf)); BIT 7121 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_VFRE, reg | BIT(vf)); BIT 9206 drivers/net/ethernet/intel/igb/igb_main.c rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / BIT 9296 drivers/net/ethernet/intel/igb/igb_main.c reg_val |= (BIT(vf) | BIT 9297 drivers/net/ethernet/intel/igb/igb_main.c BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); BIT 9299 drivers/net/ethernet/intel/igb/igb_main.c reg_val &= ~(BIT(vf) | BIT 9300 drivers/net/ethernet/intel/igb/igb_main.c BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); BIT 66 drivers/net/ethernet/intel/igb/igb_ptp.c #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT) BIT 94 drivers/net/ethernet/intel/igbvf/defines.h #define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */ BIT 268 drivers/net/ethernet/intel/igbvf/igbvf.h #define IGBVF_FLAG_RX_CSUM_DISABLED BIT(0) BIT 269 drivers/net/ethernet/intel/igbvf/igbvf.h #define IGBVF_FLAG_RX_LB_VLAN_BSWAP BIT(1) BIT 944 drivers/net/ethernet/intel/igbvf/netdev.c adapter->rx_ring[rx_queue].eims_value = BIT(msix_vector); BIT 959 drivers/net/ethernet/intel/igbvf/netdev.c adapter->tx_ring[tx_queue].eims_value = BIT(msix_vector); BIT 995 drivers/net/ethernet/intel/igbvf/netdev.c adapter->eims_other = BIT(vector - 1); BIT 252 drivers/net/ethernet/intel/igbvf/vf.c msgbuf[0] |= BIT(E1000_VT_MSGINFO_SHIFT); BIT 50 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_HAS_MSI BIT(0) BIT 51 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_QUEUE_PAIRS BIT(3) BIT 52 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_DMAC BIT(4) BIT 53 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) BIT 54 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_MEDIA_RESET BIT(10) BIT 55 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_MAS_ENABLE BIT(12) BIT 56 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_HAS_MSIX BIT(13) BIT 57 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_VLAN_PROMISC BIT(15) BIT 58 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_RX_LEGACY BIT(16) BIT 60 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) BIT 61 drivers/net/ethernet/intel/igc/igc.h #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) BIT 174 drivers/net/ethernet/intel/igc/igc.h #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) BIT 86 drivers/net/ethernet/intel/igc/igc_base.c nvm->word_size = BIT(size); BIT 94 drivers/net/ethernet/intel/igc/igc_base.c if (nvm->word_size == BIT(15)) BIT 183 drivers/net/ethernet/intel/igc/igc_defines.h #define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */ BIT 184 drivers/net/ethernet/intel/igc/igc_defines.h #define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */ BIT 185 drivers/net/ethernet/intel/igc/igc_defines.h #define IGC_ICR_LSC BIT(2) /* Link Status Change */ BIT 186 drivers/net/ethernet/intel/igc/igc_defines.h #define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */ BIT 187 drivers/net/ethernet/intel/igc/igc_defines.h #define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */ BIT 188 drivers/net/ethernet/intel/igc/igc_defines.h #define IGC_ICR_RXO BIT(6) /* Rx overrun */ BIT 189 drivers/net/ethernet/intel/igc/igc_defines.h #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */ BIT 190 drivers/net/ethernet/intel/igc/igc_defines.h #define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */ BIT 193 drivers/net/ethernet/intel/igc/igc_defines.h #define IGC_ICR_INT_ASSERTED BIT(31) BIT 120 drivers/net/ethernet/intel/igc/igc_ethtool.c #define IGC_PRIV_FLAGS_LEGACY_RX BIT(0) BIT 2613 drivers/net/ethernet/intel/igc/igc_main.c q_vector->eims_value = BIT(msix_vector); BIT 2653 drivers/net/ethernet/intel/igc/igc_main.c adapter->eims_other = BIT(vector); BIT 90 drivers/net/ethernet/intel/igc/igc_regs.h #define IGC_ETQF_FILTER_ENABLE BIT(26) BIT 91 drivers/net/ethernet/intel/igc/igc_regs.h #define IGC_ETQF_QUEUE_ENABLE BIT(31) BIT 571 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_MSI_ENABLED BIT(1) BIT 572 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_MSIX_ENABLED BIT(3) BIT 573 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) BIT 574 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) BIT 575 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_RX_PS_ENABLED BIT(6) BIT 576 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_DCA_ENABLED BIT(8) BIT 577 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_DCA_CAPABLE BIT(9) BIT 578 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_IMIR_ENABLED BIT(10) BIT 579 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_MQ_CAPABLE BIT(11) BIT 580 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_DCB_ENABLED BIT(12) BIT 581 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) BIT 582 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_VMDQ_ENABLED BIT(14) BIT 583 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) BIT 584 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) BIT 585 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) BIT 586 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) BIT 587 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) BIT 588 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_FCOE_CAPABLE BIT(20) BIT 589 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_FCOE_ENABLED BIT(21) BIT 590 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) BIT 591 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_SRIOV_ENABLED BIT(23) BIT 592 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24) BIT 593 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) BIT 594 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) BIT 595 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_DCB_CAPABLE BIT(27) BIT 596 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE BIT(28) BIT 599 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_RSC_CAPABLE BIT(0) BIT 600 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_RSC_ENABLED BIT(1) BIT 601 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) BIT 602 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) BIT 603 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) BIT 604 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) BIT 605 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) BIT 606 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) BIT 607 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) BIT 608 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) BIT 609 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) BIT 610 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_UDP_TUN_REREG_NEEDED BIT(12) BIT 611 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) BIT 612 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_EEE_CAPABLE BIT(14) BIT 613 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_EEE_ENABLED BIT(15) BIT 614 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_RX_LEGACY BIT(16) BIT 615 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_IPSEC_ENABLED BIT(17) BIT 616 drivers/net/ethernet/intel/ixgbe/ixgbe.h #define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18) BIT 747 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c gheccr &= ~(BIT(21) | BIT(18) | BIT(9) | BIT(6)); BIT 869 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c bits |= BIT(bitindex); BIT 872 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c bits &= ~BIT(bitindex); BIT 1272 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n)) \ BIT 1274 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \ BIT 1276 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n)) \ BIT 1278 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n + 16)) \ BIT 1280 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \ BIT 1282 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n + 16)) \ BIT 1417 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \ BIT 1419 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \ BIT 875 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c eeprom->word_size = BIT(eeprom_size + BIT 1552 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c mask = BIT(count - 1); BIT 2052 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); BIT 2988 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c mpsar_lo &= ~BIT(vmdq); BIT 2991 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c mpsar_hi &= ~BIT(vmdq - 32); BIT 3022 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c mpsar |= BIT(vmdq); BIT 3026 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c mpsar |= BIT(vmdq - 32); BIT 3047 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); BIT 3051 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); BIT 3153 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c vfta_delta = BIT(vlan % 32); BIT 3184 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c bits |= BIT(vind % 32); BIT 3189 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c bits ^= BIT(vind % 32); BIT 3457 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c pfvfspoof |= BIT(vf_target_shift); BIT 3459 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c pfvfspoof &= ~BIT(vf_target_shift); BIT 3481 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c pfvfspoof |= BIT(vf_target_shift); BIT 3483 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c pfvfspoof &= ~BIT(vf_target_shift); BIT 169 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c *pfc_en |= BIT(tc); BIT 215 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c u8 prio_mask = BIT(up); BIT 196 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c if (!(pfc_en & BIT(i))) { BIT 228 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c if ((prio_tc[j] == i) && (pfc_en & BIT(j))) { BIT 40 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c if (up && !(up & BIT(adapter->fcoe.up))) BIT 635 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c if (app_mask & BIT(adapter->fcoe.up)) BIT 678 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c if (app_mask & BIT(adapter->fcoe.up)) BIT 137 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c #define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0) BIT 139 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c #define IXGBE_PRIV_FLAGS_VF_IPSEC_EN BIT(1) BIT 1626 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask = BIT(i); BIT 3050 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); BIT 3056 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); BIT 3061 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | BIT 3062 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | BIT 3063 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); BIT 3083 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c BIT(HWTSTAMP_TX_OFF) | BIT 3084 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c BIT(HWTSTAMP_TX_ON); BIT 489 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c #define MANC_EN_IPV4_FILTER BIT(24) BIT 510 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c if (!(mfval & BIT(MFVAL_IPV4_FILTER_SHIFT + i))) BIT 531 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c if (!(mfval & BIT(MFVAL_IPV6_FILTER_SHIFT + i))) BIT 2444 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; BIT 4471 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c bits = ~BIT(VMDQ_P(0) % 32); BIT 4606 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c vlvfb |= BIT(VMDQ_P(0) % 32); BIT 4636 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c vfta[(vid - vid_start) / 32] |= BIT(vid % 32); BIT 4645 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c bits = ~BIT(VMDQ_P(0) % 32); BIT 10836 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (!(eec & BIT(8))) BIT 292 drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c if (vflre & BIT(vf_shift)) { BIT 293 drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), BIT(vf_shift)); BIT 87 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h #define IXGBE_PE_BIT1 BIT(1) BIT 477 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c BIT(IXGBE_INCPER_SHIFT_82599) | BIT 1275 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c BIT(IXGBE_INCPER_SHIFT_82599) | incval); BIT 394 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c mta_reg |= BIT(vector_bit); BIT 421 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c mta_reg |= BIT(vector_bit); BIT 525 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c vfre &= ~BIT(vf_shift); BIT 527 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c vfre |= BIT(vf_shift); BIT 581 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c pool_mask = ~BIT(VMDQ_P(0) % 32); BIT 582 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c vlvfb_mask = BIT(vf % 32); BIT 618 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c mask = BIT(vid % 32); BIT 852 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg |= BIT(vf_shift); BIT 864 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg |= BIT(vf_shift); BIT 880 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg &= ~BIT(vf_shift); BIT 889 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg |= BIT(vf_shift); BIT 8 drivers/net/ethernet/intel/ixgbe/ixgbe_txrx_common.h #define IXGBE_XDP_CONSUMED BIT(0) BIT 9 drivers/net/ethernet/intel/ixgbe/ixgbe_txrx_common.h #define IXGBE_XDP_TX BIT(1) BIT 10 drivers/net/ethernet/intel/ixgbe/ixgbe_txrx_common.h #define IXGBE_XDP_REDIR BIT(2) BIT 728 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCBUFF_VALID BIT(0) /* DMA Context Valid */ BIT 730 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCBUFF_WRCONTX BIT(7) /* 0: Initiator, 1: Target */ BIT 736 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCDMARW_WE BIT(14) /* Write enable */ BIT 737 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCDMARW_RE BIT(15) /* Read enable */ BIT 754 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCFLT_VALID BIT(0) /* Filter Context Valid */ BIT 755 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCFLT_FIRST BIT(1) /* Filter First */ BIT 758 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCFLTRW_RVALDT BIT(13) /* Fast Re-Validation */ BIT 759 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCFLTRW_WE BIT(14) /* Write Enable */ BIT 760 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCFLTRW_RE BIT(15) /* Read Enable */ BIT 763 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCRXCTRL_FCOELLI BIT(0) /* Low latency interrupt */ BIT 764 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCRXCTRL_SAVBAD BIT(1) /* Save Bad Frames */ BIT 765 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCRXCTRL_FRSTRDH BIT(2) /* EN 1st Read Header */ BIT 766 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCRXCTRL_LASTSEQH BIT(3) /* EN Last Header in Seq */ BIT 767 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCRXCTRL_ALLH BIT(4) /* EN All Headers */ BIT 768 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCRXCTRL_FRSTSEQH BIT(5) /* EN 1st Seq. Header */ BIT 769 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCRXCTRL_ICRC BIT(6) /* Ignore Bad FC CRC */ BIT 770 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FCRXCTRL_FCCRCBO BIT(7) /* FC CRC Byte Ordering */ BIT 927 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FWSM_FW_NVM_RECOVERY_MODE BIT(5) BIT 929 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FWSM_FW_VAL_BIT BIT(15) BIT 1279 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */ BIT 1280 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */ BIT 1281 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */ BIT 1282 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */ BIT 1283 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */ BIT 1284 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */ BIT 1289 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ BIT 1290 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ BIT 1291 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */ BIT 1292 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ BIT 1762 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_ETQF_POOL_ENABLE BIT(26) /* bit 26 */ BIT 1842 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_X557_LED_MANUAL_SET_MASK BIT(8) BIT 2142 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR BIT(7) BIT 2678 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_10 BIT(0) BIT 2679 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_100 BIT(1) BIT 2680 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_1G BIT(2) BIT 2681 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_2_5G BIT(3) BIT 2682 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_5G BIT(4) BIT 2683 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_10G BIT(5) BIT 2684 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_20G BIT(6) BIT 2685 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_25G BIT(7) BIT 2686 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_40G BIT(8) BIT 2687 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_50G BIT(9) BIT 2688 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_LINK_SPEED_100G BIT(10) BIT 2696 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_SETUP_LINK_LP BIT(18) BIT 2697 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_SETUP_LINK_HP BIT(19) BIT 2698 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_SETUP_LINK_EEE BIT(20) BIT 2699 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_SETUP_LINK_AN BIT(22) BIT 2700 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_SETUP_LINK_RSP_DOWN BIT(0) BIT 2702 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_GET_LINK_INFO_EEE BIT(19) BIT 2703 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_GET_LINK_INFO_FC_TX BIT(20) BIT 2704 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_GET_LINK_INFO_FC_RX BIT(21) BIT 2705 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_GET_LINK_INFO_POWER BIT(22) BIT 2706 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE BIT(24) BIT 2707 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_GET_LINK_INFO_TEMP BIT(25) BIT 2708 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX BIT(28) BIT 2709 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX BIT(29) BIT 2711 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_FORCE_LINK_DOWN_OFF BIT(0) BIT 2716 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_UD_2_10G_KR_EEE BIT(6) BIT 2717 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_UD_2_10G_KX4_EEE BIT(5) BIT 2718 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_UD_2_1G_KX_EEE BIT(4) BIT 2719 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_UD_2_10G_T_EEE BIT(3) BIT 2720 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_UD_2_1G_T_EEE BIT(2) BIT 2721 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define FW_PHY_ACT_UD_2_100M_TX_EEE BIT(1) BIT 2937 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_ADVTXD_FCOEF_SOF (BIT(2) << 10) /* FC SOF index */ BIT 2938 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_ADVTXD_FCOEF_PARINC (BIT(3) << 10) /* Rel_Off in F_CTL */ BIT 2939 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_ADVTXD_FCOEF_ORIE (BIT(4) << 10) /* Orientation: End */ BIT 2940 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_ADVTXD_FCOEF_ORIS (BIT(5) << 10) /* Orientation: Start */ BIT 3704 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_FUSES0_300MHZ BIT(5) BIT 3723 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR BIT(20) BIT 3725 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN BIT(25) BIT 3726 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN BIT(26) BIT 3727 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN BIT(27) BIT 3729 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M BIT(28) BIT 3735 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART BIT(31) BIT 3737 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B BIT(9) BIT 3738 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS BIT(11) BIT 3743 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN BIT(12) BIT 3744 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN BIT(13) BIT 3745 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ BIT(14) BIT 3746 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC BIT(15) BIT 3747 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX BIT(16) BIT 3748 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR BIT(18) BIT 3749 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX BIT(24) BIT 3750 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR BIT(26) BIT 3751 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE BIT(28) BIT 3752 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE BIT(29) BIT 3753 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART BIT(31) BIT 3755 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE BIT(28) BIT 3756 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE BIT(29) BIT 3758 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_AN_CNTL_8_LINEAR BIT(0) BIT 3759 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_AN_CNTL_8_LIMITING BIT(1) BIT 3761 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE BIT(10) BIT 3762 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE BIT(11) BIT 3763 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D BIT(12) BIT 3764 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D BIT(19) BIT 3766 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN BIT(6) BIT 3767 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN BIT(15) BIT 3768 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN BIT(16) BIT 3770 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL BIT(4) BIT 3771 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS BIT(2) BIT 3775 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN BIT(1) BIT 3776 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN BIT(2) BIT 3777 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN BIT(3) BIT 3778 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN BIT(31) BIT 3794 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_SB_IOSF_CTRL_BUSY BIT(IXGBE_SB_IOSF_CTRL_BUSY_SHIFT) BIT 3798 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT BIT(1) BIT 3799 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M BIT(17) BIT 3800 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M BIT(18) BIT 3801 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G BIT(19) BIT 3802 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G BIT(20) BIT 3803 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G BIT(21) BIT 3804 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE BIT(25) BIT 3805 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE BIT(24) /* X552 only */ BIT 200 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c eeprom->word_size = BIT(eeprom_size + BIT 641 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c eeprom->word_size = BIT(eeprom_size + BIT 3517 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c pfvfspoof |= BIT(vf_target_shift); BIT 3519 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c pfvfspoof &= ~BIT(vf_target_shift); BIT 60 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */ BIT 290 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* Rx Desc enable */ BIT 291 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* Rx Desc header ena */ BIT 292 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* Rx Desc payload ena */ BIT 293 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* Rx rd Desc Relax Order */ BIT 294 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */ BIT 295 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */ BIT 297 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ BIT 298 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ BIT 299 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */ BIT 300 drivers/net/ethernet/intel/ixgbevf/defines.h #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ BIT 78 drivers/net/ethernet/intel/ixgbevf/ethtool.c #define IXGBEVF_PRIV_FLAGS_LEGACY_RX BIT(0) BIT 20 drivers/net/ethernet/intel/ixgbevf/ixgbevf.h #define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR) BIT 163 drivers/net/ethernet/intel/ixgbevf/ixgbevf.h #define IXGBE_TX_FLAGS_CSUM BIT(0) BIT 164 drivers/net/ethernet/intel/ixgbevf/ixgbevf.h #define IXGBE_TX_FLAGS_VLAN BIT(1) BIT 165 drivers/net/ethernet/intel/ixgbevf/ixgbevf.h #define IXGBE_TX_FLAGS_TSO BIT(2) BIT 166 drivers/net/ethernet/intel/ixgbevf/ixgbevf.h #define IXGBE_TX_FLAGS_IPV4 BIT(3) BIT 167 drivers/net/ethernet/intel/ixgbevf/ixgbevf.h #define IXGBE_TX_FLAGS_IPSEC BIT(4) BIT 390 drivers/net/ethernet/intel/ixgbevf/ixgbevf.h #define IXGBEVF_FLAGS_LEGACY_RX BIT(1) BIT 1308 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c BIT(q_vector->v_idx)); BIT 1377 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c adapter->eims_enable_mask |= BIT(v_idx); BIT 1384 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c adapter->eims_other = BIT(v_idx); BIT 1787 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c psrtype |= BIT(29); BIT 3208 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c eics |= BIT(i); BIT 57 drivers/net/ethernet/lantiq_etop.c #define ETOP_FTCU BIT(28) BIT 33 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_ADD BIT(0) BIT 35 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_TAG BIT(1) BIT 37 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_AC BIT(2) BIT 39 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_AS BIT(3) BIT 41 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_RC BIT(4) BIT 43 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_RL2 BIT(5) BIT 45 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_RXSH BIT(6) BIT 47 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_AST BIT(7) BIT 49 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_RST BIT(8) BIT 51 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_CCRC BIT(9) BIT 53 drivers/net/ethernet/lantiq_xrx200.c #define PMAC_HD_CTL_FC BIT(10) BIT 36 drivers/net/ethernet/marvell/mvmdio.c #define MVMDIO_SMI_READ_OPERATION BIT(26) BIT 38 drivers/net/ethernet/marvell/mvmdio.c #define MVMDIO_SMI_READ_VALID BIT(27) BIT 39 drivers/net/ethernet/marvell/mvmdio.c #define MVMDIO_SMI_BUSY BIT(28) BIT 49 drivers/net/ethernet/marvell/mvmdio.c #define MVMDIO_XSMI_READ_VALID BIT(29) BIT 50 drivers/net/ethernet/marvell/mvmdio.c #define MVMDIO_XSMI_BUSY BIT(30) BIT 43 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) BIT 65 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_PORT_RX_DMA_RESET BIT(0) BIT 71 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_PHY_POLLING_ENABLE BIT(1) BIT 78 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_UNI_PROMISC_MODE BIT(0) BIT 81 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TX_UNSET_ERR_SUM BIT(12) BIT 85 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) BIT 99 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RX_NO_DATA_SWAP BIT(4) BIT 100 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TX_NO_DATA_SWAP BIT(5) BIT 101 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_DESC_SWAP BIT(6) BIT 104 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TX_IN_PRGRS BIT(1) BIT 105 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TX_FIFO_EMPTY BIT(8) BIT 111 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_FORCE_UNI BIT(21) BIT 119 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) BIT 125 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) BIT 126 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) BIT 151 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_MISCINTR_INTR_MASK BIT(31) BIT 160 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) BIT 161 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_LINK_CHANGE BIT(1) BIT 162 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_PTP BIT(4) BIT 164 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) BIT 165 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_RX_OVERRUN BIT(8) BIT 166 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) BIT 167 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) BIT 168 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_TX_UNDERUN BIT(11) BIT 169 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_PRBS_ERR BIT(12) BIT 170 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) BIT 171 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) BIT 193 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) BIT 194 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC0_PORT_ENABLE BIT(0) BIT 196 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) BIT 197 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC2_PCS_ENABLE BIT(3) BIT 198 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC2_PORT_RGMII BIT(4) BIT 199 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC2_PORT_RESET BIT(6) BIT 201 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_LINK_UP BIT(0) BIT 202 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_SPEED_1000 BIT(1) BIT 203 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_SPEED_100 BIT(2) BIT 204 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_FULL_DUPLEX BIT(3) BIT 205 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) BIT 206 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) BIT 207 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) BIT 208 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) BIT 209 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_AN_COMPLETE BIT(11) BIT 210 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_SYNC_OK BIT(14) BIT 212 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) BIT 213 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) BIT 214 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) BIT 215 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) BIT 216 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) BIT 217 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) BIT 218 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) BIT 219 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_AN_SPEED_EN BIT(7) BIT 220 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) BIT 221 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) BIT 222 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) BIT 223 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) BIT 224 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) BIT 226 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) BIT 243 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_PORT_TX_DMA_RESET BIT(0) BIT 252 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_LPI_REQUEST_ENABLE BIT(0) BIT 471 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TX_L4_UDP BIT(16) BIT 472 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TX_L3_IP6 BIT(17) BIT 473 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TXD_IP_CSUM BIT(18) BIT 474 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TXD_Z_PAD BIT(19) BIT 475 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TXD_L_DESC BIT(20) BIT 476 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TXD_F_DESC BIT(21) BIT 480 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TX_L4_CSUM_FULL BIT(30) BIT 481 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_TX_L4_CSUM_NOT BIT(31) BIT 485 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) BIT 486 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXD_ERR_SUMMARY BIT(16) BIT 487 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXD_ERR_OVERRUN BIT(17) BIT 488 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXD_ERR_LEN BIT(18) BIT 489 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) BIT 490 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) BIT 491 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXD_L3_IP4 BIT(25) BIT 492 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXD_LAST_DESC BIT(26) BIT 493 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXD_FIRST_DESC BIT(27) BIT 496 drivers/net/ethernet/marvell/mvneta.c #define MVNETA_RXD_L4_CSUM_OK BIT(30) BIT 4458 drivers/net/ethernet/marvell/mvneta.c win_enable &= ~BIT(0); BIT 19 drivers/net/ethernet/marvell/mvneta_bm.h #define MVNETA_BM_ACTIVE_MASK BIT(4) BIT 21 drivers/net/ethernet/marvell/mvneta_bm.h #define MVNETA_BM_MAX_IN_BURST_SIZE_16BP BIT(18) BIT 22 drivers/net/ethernet/marvell/mvneta_bm.h #define MVNETA_BM_EMPTY_LIMIT_MASK BIT(19) BIT 26 drivers/net/ethernet/marvell/mvneta_bm.h #define MVNETA_BM_START_MASK BIT(0) BIT 27 drivers/net/ethernet/marvell/mvneta_bm.h #define MVNETA_BM_STOP_MASK BIT(1) BIT 28 drivers/net/ethernet/marvell/mvneta_bm.h #define MVNETA_BM_PAUSE_MASK BIT(2) BIT 48 drivers/net/ethernet/marvell/mvneta_bm.h #define MVNETA_BM_POOL_ENABLE_MASK BIT(0) BIT 30 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) BIT 35 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) BIT 44 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXQ_DISABLE_MASK BIT(31) BIT 48 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_DSA_EXTENDED BIT(5) BIT 63 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_PRS_TCAM_INV_MASK BIT(31) BIT 67 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_PRS_TCAM_EN_MASK BIT(0) BIT 84 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) BIT 92 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) BIT 95 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_CLS_FLOW_TBL0_LAST BIT(0) BIT 101 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL BIT(23) BIT 132 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_CLS_C2_TCAM_INV_BIT BIT(31) BIT 149 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_CLS_C2_ATTR2_RSS_EN BIT(30) BIT 152 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_CLS_C2_TCAM_BYPASS_FIFO BIT(0) BIT 182 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) BIT 183 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) BIT 185 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) BIT 269 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) BIT 270 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) BIT 271 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) BIT 272 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) BIT 273 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) BIT 274 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) BIT 279 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) BIT 295 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) BIT 297 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_START_MASK BIT(0) BIT 298 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_STOP_MASK BIT(1) BIT 299 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_STATE_MASK BIT(4) BIT 309 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) BIT 310 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) BIT 311 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) BIT 312 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_BPPE_FULL_MASK BIT(3) BIT 313 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) BIT 316 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) BIT 323 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) BIT 324 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) BIT 325 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) BIT 338 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7)) BIT 389 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) BIT 395 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_PORT_EN_MASK BIT(0) BIT 396 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) BIT 399 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) BIT 401 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) BIT 402 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) BIT 404 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) BIT 407 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) BIT 409 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) BIT 410 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) BIT 411 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_DISABLE_PADDING BIT(5) BIT 412 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) BIT 414 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) BIT 415 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) BIT 416 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) BIT 417 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) BIT 418 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4) BIT 419 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) BIT 420 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) BIT 421 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_AN_SPEED_EN BIT(7) BIT 422 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_FC_ADV_EN BIT(9) BIT 423 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10) BIT 424 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) BIT 425 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) BIT 426 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) BIT 428 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) BIT 429 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1) BIT 430 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2) BIT 431 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3) BIT 432 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(4) BIT 433 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(5) BIT 434 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11) BIT 441 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_GMAC_INT_STAT_LINK BIT(1) BIT 443 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1) BIT 445 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) BIT 446 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_CTRL4_RX_FC_EN BIT(3) BIT 447 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_CTRL4_TX_FC_EN BIT(4) BIT 448 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) BIT 449 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) BIT 450 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) BIT 452 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) BIT 458 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) BIT 459 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) BIT 460 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL0_FORCE_LINK_DOWN BIT(2) BIT 461 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL0_FORCE_LINK_PASS BIT(3) BIT 462 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) BIT 463 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8) BIT 464 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) BIT 469 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_STATUS_LINK_UP BIT(0) BIT 471 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_INT_STAT_LINK BIT(1) BIT 473 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_INT_MASK_LINK BIT(1) BIT 479 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) BIT 480 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) BIT 482 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) BIT 483 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) BIT 484 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) BIT 485 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14) BIT 489 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_SMI_POLLING_EN BIT(10) BIT 502 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10) BIT 504 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MAC_CLK_RESET_SD_TX BIT(0) BIT 505 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MAC_CLK_RESET_SD_RX BIT(1) BIT 506 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MAC_CLK_RESET_MAC BIT(2) BIT 508 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) BIT 513 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_XPCS_CFG0_RESET_DIS BIT(0) BIT 519 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define GENCONF_SOFT_RESET1_GOP BIT(6) BIT 521 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) BIT 522 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) BIT 523 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) BIT 525 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define GENCONF_PORT_CTRL1_EN(p) BIT(p) BIT 526 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) BIT 528 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define GENCONF_CTRL0_PORT0_RGMII BIT(0) BIT 529 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) BIT 530 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define GENCONF_CTRL0_PORT1_RGMII BIT(2) BIT 654 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_F_LOOPBACK BIT(0) BIT 655 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_F_DT_COMPAT BIT(1) BIT 971 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) BIT 972 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_TXD_L4_CSUM_NOT BIT(14) BIT 973 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) BIT 974 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_TXD_PADDING_DISABLE BIT(23) BIT 975 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_TXD_L4_UDP BIT(24) BIT 976 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_TXD_L3_IP6 BIT(26) BIT 977 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_TXD_L_DESC BIT(28) BIT 978 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_TXD_F_DESC BIT(29) BIT 980 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_ERR_SUMMARY BIT(15) BIT 981 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) BIT 983 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_ERR_OVERRUN BIT(13) BIT 984 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) BIT 986 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) BIT 987 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_HWF_SYNC BIT(21) BIT 988 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_L4_CSUM_OK BIT(22) BIT 989 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) BIT 990 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_L4_TCP BIT(25) BIT 991 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_L4_UDP BIT(26) BIT 992 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_L3_IP4 BIT(28) BIT 993 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_L3_IP6 BIT(30) BIT 994 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_RXD_BUF_HDR BIT(31) BIT 605 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c mvpp2_cls_flow_port_add(&fe, BIT(i)); BIT 620 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c mvpp2_cls_flow_port_add(&fe, BIT(i)); BIT 653 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c switch (BIT(i)) { BIT 870 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c pmap = BIT(port->id); BIT 1056 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c c2.tcam[4] &= ~(MVPP22_CLS_C2_PORT_ID(BIT(port->id))); BIT 1105 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c pmap = BIT(port->id); BIT 1186 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c mvpp2_cls_flow_port_remove(&fe, BIT(port->id)); BIT 1669 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c switch (BIT(i)) { BIT 35 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_CLS_HEK_OPT_MAC_DA BIT(0) BIT 36 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_CLS_HEK_OPT_VLAN_PRI BIT(1) BIT 37 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_CLS_HEK_OPT_VLAN BIT(2) BIT 38 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_CLS_HEK_OPT_L3_PROTO BIT(3) BIT 39 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_CLS_HEK_OPT_IP4SA BIT(4) BIT 40 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_CLS_HEK_OPT_IP4DA BIT(5) BIT 41 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_CLS_HEK_OPT_IP6SA BIT(6) BIT 42 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_CLS_HEK_OPT_IP6DA BIT(7) BIT 43 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_CLS_HEK_OPT_L4SIP BIT(8) BIT 44 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_CLS_HEK_OPT_L4DIP BIT(9) BIT 126 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_FLOW_ETHER_BIT BIT(0) BIT 127 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_FLOW_IP4_BIT BIT(1) BIT 128 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_FLOW_IP6_BIT BIT(2) BIT 129 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_FLOW_TCP_BIT BIT(3) BIT 130 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h #define MVPP22_FLOW_UDP_BIT BIT(4) BIT 881 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c port->pool_long->port_map |= BIT(port->id); BIT 894 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c port->pool_short->port_map |= BIT(port->id); BIT 916 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c port->priv->bm_pools[i].port_map |= BIT(port->id); BIT 926 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c port->priv->bm_pools[i + port->nrxqs].port_map |= BIT(port->id); BIT 987 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c port->pool_long->port_map &= ~BIT(port->id); BIT 992 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c port->pool_short->port_map &= ~BIT(port->id); BIT 4451 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c v->sw_thread_mask = BIT(i); BIT 114 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(BIT(port)); BIT 116 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(BIT(port)); BIT 175 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (!(enable & BIT(i))) BIT 178 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (bits & BIT(i)) BIT 179 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= BIT(i); BIT 181 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c pe->tcam[MVPP2_PRS_TCAM_AI_WORD] &= ~BIT(i); BIT 230 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (!(mask & BIT(i))) BIT 233 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (bits & BIT(i)) BIT 258 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (!(mask & BIT(i))) BIT 261 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (bits & BIT(i)) BIT 2222 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c tid = mvpp2_prs_mac_da_range_find(priv, BIT(port->id), da, mask, BIT 25 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5) BIT 39 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_CAST_MASK BIT(0) BIT 40 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_MCAST_VAL BIT(0) BIT 188 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3)) BIT 190 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) BIT 191 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) BIT 192 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) BIT 194 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) BIT 195 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) BIT 197 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L2_MCAST BIT(9) BIT 198 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L2_BCAST BIT(10) BIT 200 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14)) BIT 202 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L3_IP4 BIT(12) BIT 203 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) BIT 204 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) BIT 205 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L3_IP6 BIT(14) BIT 206 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) BIT 207 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) BIT 208 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16)) BIT 210 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L3_MCAST BIT(15) BIT 211 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) BIT 213 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_IP_FRAG_TRUE BIT(17) BIT 215 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21) BIT 217 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L4_TCP BIT(22) BIT 218 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L4_UDP BIT(23) BIT 219 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23)) BIT 221 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29) BIT 229 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0) BIT 230 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0) BIT 231 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1) BIT 232 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2) BIT 233 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3) BIT 234 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4) BIT 236 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7) BIT 237 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h #define MVPP2_PRS_EDSA_VID_AI_BIT BIT(0) BIT 575 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_FLOW_KEY_TYPE_PORT BIT(0) BIT 576 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) BIT 577 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) BIT 578 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_FLOW_KEY_TYPE_TCP BIT(3) BIT 579 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_FLOW_KEY_TYPE_UDP BIT(4) BIT 580 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) BIT 611 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_RX_MODE_UCAST BIT(0) BIT 612 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_RX_MODE_PROMISC BIT(1) BIT 613 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_RX_MODE_ALLMULTI BIT(2) BIT 619 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_RX_OL3_VERIFY BIT(0) BIT 620 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_RX_OL4_VERIFY BIT(1) BIT 622 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define NIX_RX_CSUM_OL4_VERIFY BIT(0) BIT 2029 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c key_type = BIT(idx); BIT 2538 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (req->len_verify & BIT(0)) BIT 2543 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (req->len_verify & BIT(1)) BIT 2548 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (req->csum_verify & BIT(0)) BIT 2971 drivers/net/ethernet/mediatek/mtk_eth_soc.c if (eth->soc->required_clks & BIT(i)) { BIT 62 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RST_GL_PSE BIT(0) BIT 66 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_GDM1_AF BIT(28) BIT 67 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_GDM2_AF BIT(29) BIT 77 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_CDMQ_STAG_EN BIT(0) BIT 84 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_GDMA_ICS_EN BIT(22) BIT 85 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_GDMA_TCS_EN BIT(21) BIT 86 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_GDMA_UCS_EN BIT(20) BIT 108 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_LRO_EN BIT(0) BIT 109 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_L3_CKS_UPD_EN BIT(7) BIT 110 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) BIT 117 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_ADMA_MODE BIT(15) BIT 122 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_MULTI_EN BIT(10) BIT 127 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_PST_DRX_IDX0 BIT(16) BIT 132 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_PDMA_DELAY_RX_EN BIT(15) BIT 156 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RING_MYIP_VLD BIT(9) BIT 168 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RING_VLD BIT(8) BIT 194 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RX_2B_OFFSET BIT(31) BIT 196 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_NDP_CO_PRO BIT(10) BIT 197 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_TX_WB_DDONE BIT(6) BIT 199 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RX_DMA_BUSY BIT(3) BIT 200 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_TX_DMA_BUSY BIT(1) BIT 201 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RX_DMA_EN BIT(2) BIT 202 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_TX_DMA_EN BIT(0) BIT 213 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define FC_THRES_DROP_MODE BIT(20) BIT 219 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RX_DONE_DLY BIT(30) BIT 220 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RX_DONE_INT3 BIT(19) BIT 221 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RX_DONE_INT2 BIT(18) BIT 222 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RX_DONE_INT1 BIT(17) BIT 223 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RX_DONE_INT0 BIT(16) BIT 224 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_TX_DONE_INT3 BIT(3) BIT 225 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_TX_DONE_INT2 BIT(2) BIT 226 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_TX_DONE_INT1 BIT(1) BIT 227 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_TX_DONE_INT0 BIT(0) BIT 235 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RLS_DONE_INT BIT(0) BIT 273 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TX_DMA_TSO BIT(28) BIT 276 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TX_DMA_INS_VLAN BIT(16) BIT 279 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TX_DMA_OWNER_CPU BIT(31) BIT 280 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TX_DMA_LS0 BIT(30) BIT 283 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TX_DMA_SWC BIT(14) BIT 287 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TX_DMA_DONE BIT(31) BIT 288 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TX_DMA_LS1 BIT(14) BIT 292 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RX_DMA_DONE BIT(31) BIT 293 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RX_DMA_LSO BIT(30) BIT 301 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RX_DMA_L4_VALID BIT(24) BIT 302 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ BIT 308 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define PHY_IAC_ACCESS BIT(31) BIT 309 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define PHY_IAC_READ BIT(19) BIT 310 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define PHY_IAC_WRITE BIT(18) BIT 311 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define PHY_IAC_START BIT(16) BIT 317 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_MUX_TO_ESW BIT(0) BIT 321 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_MAX_RX_1536 BIT(24) BIT 322 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) BIT 323 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_FORCE_MODE BIT(15) BIT 324 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_TX_EN BIT(14) BIT 325 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_RX_EN BIT(13) BIT 326 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_BACKOFF_EN BIT(9) BIT 327 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_BACKPR_EN BIT(8) BIT 328 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_FORCE_RX_FC BIT(5) BIT 329 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_FORCE_TX_FC BIT(4) BIT 330 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_SPEED_1000 BIT(3) BIT 331 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_SPEED_100 BIT(2) BIT 332 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_FORCE_DPX BIT(1) BIT 333 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MCR_FORCE_LINK BIT(0) BIT 338 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MSR_EEE1G BIT(7) BIT 339 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MSR_EEE100M BIT(6) BIT 340 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MSR_RX_FC BIT(5) BIT 341 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MSR_TX_FC BIT(4) BIT 342 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MSR_SPEED_1000 BIT(3) BIT 343 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MSR_SPEED_100 BIT(2) BIT 345 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MSR_DPX BIT(1) BIT 346 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MAC_MSR_LINK BIT(0) BIT 353 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RXC_RST BIT(31) BIT 354 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RXC_DQSISEL BIT(30) BIT 363 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TXC_INV BIT(30) BIT 374 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TRGMII_INTF_DIS BIT(0) BIT 375 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TRGMII_MODE BIT(1) BIT 376 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TRGMII_CENTRAL_ALIGNED BIT(2) BIT 394 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) BIT 403 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) BIT 404 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) BIT 409 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) BIT 410 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) BIT 411 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define ETHSYS_TRGMII_MT7621_APLL BIT(6) BIT 412 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) BIT 416 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RSTCTRL_FE BIT(6) BIT 417 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RSTCTRL_PPE BIT(31) BIT 422 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_AN_RESTART BIT(9) BIT 423 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_ISOLATE BIT(10) BIT 424 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_AN_ENABLE BIT(12) BIT 425 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_LINK_STATYS BIT(18) BIT 426 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_AN_ABILITY BIT(19) BIT 427 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_AN_COMPLETE BIT(21) BIT 428 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_PCS_FAULT BIT(23) BIT 429 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_AN_EXPANSION_CLR BIT(30) BIT 437 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_IF_MODE_BIT0 BIT(0) BIT 438 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_SPEED_DUPLEX_AN BIT(1) BIT 440 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_SPEED_100 BIT(2) BIT 441 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_SPEED_1000 BIT(3) BIT 442 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_DUPLEX_FULL BIT(4) BIT 443 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_IF_MODE_BIT5 BIT(5) BIT 444 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_REMOTE_FAULT_DIS BIT(8) BIT 445 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_CODE_SYNC_SET_VAL BIT(9) BIT 446 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_CODE_SYNC_SET_EN BIT(10) BIT 447 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_SEND_AN_ERROR_EN BIT(11) BIT 452 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) BIT 454 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RG_PHY_SPEED_3_125G BIT(2) BIT 458 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_PHYA_PWD BIT(4) BIT 462 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define CO_QPHY_SEL BIT(0) BIT 463 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define GEPHY_MAC_SEL BIT(1) BIT 473 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MT7628_PST_DTX_IDX0 BIT(0) BIT 562 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ BIT 563 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ BIT 564 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_TRGPLL)) BIT 565 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ BIT 566 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ BIT 567 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_GP2) | \ BIT 568 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII_TX_250M) | \ BIT 569 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII_RX_250M) | \ BIT 570 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII_CDR_REF) | \ BIT 571 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII_CDR_FB) | \ BIT 572 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII_CK) | \ BIT 573 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_ETH2PLL)) BIT 576 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ BIT 577 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ BIT 578 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ BIT 579 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII_TX_250M) | \ BIT 580 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII_RX_250M) | \ BIT 581 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII_CDR_REF) | \ BIT 582 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII_CDR_FB) | \ BIT 583 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII2_TX_250M) | \ BIT 584 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII2_RX_250M) | \ BIT 585 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII2_CDR_REF) | \ BIT 586 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII2_CDR_FB) | \ BIT 587 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_SGMII_CK) | \ BIT 588 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) BIT 696 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_RGMII BIT(MTK_RGMII_BIT) BIT 697 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_TRGMII BIT(MTK_TRGMII_BIT) BIT 698 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_SGMII BIT(MTK_SGMII_BIT) BIT 699 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_ESW BIT(MTK_ESW_BIT) BIT 700 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_GEPHY BIT(MTK_GEPHY_BIT) BIT 701 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_MUX BIT(MTK_MUX_BIT) BIT 702 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_INFRA BIT(MTK_INFRA_BIT) BIT 703 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) BIT 704 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_HWLRO BIT(MTK_HWLRO_BIT) BIT 705 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) BIT 706 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) BIT 707 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_QDMA BIT(MTK_QDMA_BIT) BIT 708 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) BIT 711 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) BIT 713 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) BIT 715 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) BIT 717 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) BIT 719 drivers/net/ethernet/mediatek/mtk_eth_soc.h BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) BIT 722 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) BIT 723 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) BIT 724 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) BIT 725 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) BIT 726 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) BIT 727 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) BIT 728 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) BIT 803 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_SGMII_PHYSPEED_AN BIT(31) BIT 805 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_SGMII_PHYSPEED_1000 BIT(0) BIT 806 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_SGMII_PHYSPEED_2500 BIT(1) BIT 37 drivers/net/ethernet/mellanox/mlx4/crdump.c #define CR_ENABLE_BIT swab32(BIT(6)) BIT 391 drivers/net/ethernet/mellanox/mlx4/fw.c #define QUERY_FUNC_CAP_SUPPORTS_VST_QINQ BIT(30) BIT 392 drivers/net/ethernet/mellanox/mlx4/fw.c #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS BIT(31) BIT 2420 drivers/net/ethernet/mellanox/mlx4/fw.c #define MLX4_ROCE_V2_UDP_DPORT BIT(3) BIT 2421 drivers/net/ethernet/mellanox/mlx4/fw.c #define MLX4_DISABLE_RX_PORT BIT(18) BIT 2524 drivers/net/ethernet/mellanox/mlx4/fw.c #define CONFIG_DISABLE_RX_PORT BIT(15) BIT 241 drivers/net/ethernet/mellanox/mlx4/main.c BIT(DEVLINK_PARAM_CMODE_RUNTIME) | BIT 242 drivers/net/ethernet/mellanox/mlx4/main.c BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), BIT 246 drivers/net/ethernet/mellanox/mlx4/main.c BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), BIT 249 drivers/net/ethernet/mellanox/mlx4/main.c BIT(DEVLINK_PARAM_CMODE_RUNTIME) | BIT 250 drivers/net/ethernet/mellanox/mlx4/main.c BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), BIT 255 drivers/net/ethernet/mellanox/mlx4/main.c BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), BIT 259 drivers/net/ethernet/mellanox/mlx4/main.c BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), BIT 69 drivers/net/ethernet/mellanox/mlx4/mlx4.h #define MLX4_QUERY_IF_STAT_RESET BIT(31) BIT 77 drivers/net/ethernet/mellanox/mlx4/mlx4_en.h #define TXBB_SIZE BIT(LOG_TXBB_SIZE) BIT 53 drivers/net/ethernet/mellanox/mlx4/port.c #define MLX4_FLAG2_V_IGNORE_FCS_MASK BIT(1) BIT 54 drivers/net/ethernet/mellanox/mlx4/port.c #define MLX4_FLAG2_V_USER_MTU_MASK BIT(5) BIT 55 drivers/net/ethernet/mellanox/mlx4/port.c #define MLX4_FLAG2_V_USER_MAC_MASK BIT(6) BIT 56 drivers/net/ethernet/mellanox/mlx4/port.c #define MLX4_FLAG_V_MTU_MASK BIT(0) BIT 57 drivers/net/ethernet/mellanox/mlx4/port.c #define MLX4_FLAG_V_PPRX_MASK BIT(1) BIT 58 drivers/net/ethernet/mellanox/mlx4/port.c #define MLX4_FLAG_V_PPTX_MASK BIT(2) BIT 85 drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h MLX5_ACCEL_TLS_TX = BIT(0), BIT 86 drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h MLX5_ACCEL_TLS_RX = BIT(1), BIT 87 drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h MLX5_ACCEL_TLS_V12 = BIT(2), BIT 88 drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h MLX5_ACCEL_TLS_V13 = BIT(3), BIT 89 drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h MLX5_ACCEL_TLS_LRO = BIT(4), BIT 90 drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h MLX5_ACCEL_TLS_IPV6 = BIT(5), BIT 91 drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h MLX5_ACCEL_TLS_AES_GCM128 = BIT(30), BIT 92 drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h MLX5_ACCEL_TLS_AES_GCM256 = BIT(31), BIT 186 drivers/net/ethernet/mellanox/mlx5/core/devlink.c BIT(DEVLINK_PARAM_CMODE_RUNTIME), BIT 54 drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.h #define MESSAGE_HASH_SIZE BIT(MESSAGE_HASH_BITS) BIT 92 drivers/net/ethernet/mellanox/mlx5/core/en.h #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) BIT 136 drivers/net/ethernet/mellanox/mlx5/core/en.h #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) BIT 239 drivers/net/ethernet/mellanox/mlx5/core/en.h (params)->pflags |= BIT(pflag); \ BIT 241 drivers/net/ethernet/mellanox/mlx5/core/en.h (params)->pflags &= ~(BIT(pflag)); \ BIT 244 drivers/net/ethernet/mellanox/mlx5/core/en.h #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) BIT 37 drivers/net/ethernet/mellanox/mlx5/core/en/fs.h #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) BIT 126 drivers/net/ethernet/mellanox/mlx5/core/en/fs.h #define MLX5E_TTC_GROUP1_SIZE (BIT(3) + MLX5E_NUM_TUNNEL_TT) BIT 127 drivers/net/ethernet/mellanox/mlx5/core/en/fs.h #define MLX5E_TTC_GROUP2_SIZE BIT(1) BIT 128 drivers/net/ethernet/mellanox/mlx5/core/en/fs.h #define MLX5E_TTC_GROUP3_SIZE BIT(0) BIT 134 drivers/net/ethernet/mellanox/mlx5/core/en/fs.h #define MLX5E_INNER_TTC_GROUP1_SIZE BIT(3) BIT 135 drivers/net/ethernet/mellanox/mlx5/core/en/fs.h #define MLX5E_INNER_TTC_GROUP2_SIZE BIT(1) BIT 136 drivers/net/ethernet/mellanox/mlx5/core/en/fs.h #define MLX5E_INNER_TTC_GROUP3_SIZE BIT(0) BIT 175 drivers/net/ethernet/mellanox/mlx5/core/en/fs.h #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) BIT 84 drivers/net/ethernet/mellanox/mlx5/core/en/health.c err = devlink_fmsg_u64_pair_put(fmsg, "stride size", BIT(cq_log_stride)); BIT 87 drivers/net/ethernet/mellanox/mlx5/core/en/params.c #define MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ ((BIT(__mlx5_bit_sz(wq, log_wqe_stride_size)) - 1) + \ BIT 504 drivers/net/ethernet/mellanox/mlx5/core/en/port.c u8 fec_policy_nofec = BIT(MLX5E_FEC_NOFEC); BIT 47 drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h MLX5E_PORT_BUFFER_CABLE_LEN = BIT(0), BIT 48 drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h MLX5E_PORT_BUFFER_PFC = BIT(1), BIT 49 drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h MLX5E_PORT_BUFFER_PRIO2BUFFER = BIT(2), BIT 50 drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h MLX5E_PORT_BUFFER_SIZE = BIT(3), BIT 319 drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c rq_stride = BIT(mlx5e_mpwqe_get_log_stride_size(priv->mdev, params, NULL)); BIT 214 drivers/net/ethernet/mellanox/mlx5/core/en_arfs.c #define MLX5E_ARFS_GROUP1_SIZE (BIT(16) - 1) BIT 215 drivers/net/ethernet/mellanox/mlx5/core/en_arfs.c #define MLX5E_ARFS_GROUP2_SIZE BIT(0) BIT 1376 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT 1377 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c BIT(HWTSTAMP_TX_ON); BIT 1379 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT 1380 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c BIT(HWTSTAMP_FILTER_ALL); BIT 1905 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c bool enable = !!(wanted_flags & BIT(flag)); BIT 1909 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c if (!(changes & BIT(flag))) BIT 1276 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c #define MLX5E_L2_GROUP1_SIZE BIT(0) BIT 1277 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c #define MLX5E_L2_GROUP2_SIZE BIT(15) BIT 1278 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c #define MLX5E_L2_GROUP3_SIZE BIT(0) BIT 1386 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c #define MLX5E_VLAN_GROUP0_SIZE BIT(12) BIT 1387 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c #define MLX5E_VLAN_GROUP1_SIZE BIT(12) BIT 1388 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c #define MLX5E_VLAN_GROUP2_SIZE BIT(1) BIT 1389 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c #define MLX5E_VLAN_GROUP3_SIZE BIT(0) BIT 102 drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c table_size = min_t(u32, BIT(MLX5_CAP_FLOWTABLE(priv->mdev, BIT 493 drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c #define MAX_NUM_OF_ETHTOOL_RULES BIT(10) BIT 96 drivers/net/ethernet/mellanox/mlx5/core/en_main.c BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) : BIT 97 drivers/net/ethernet/mellanox/mlx5/core/en_main.c BIT(params->log_rq_mtu_frames), BIT 98 drivers/net/ethernet/mellanox/mlx5/core/en_main.c BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)), BIT 473 drivers/net/ethernet/mellanox/mlx5/core/en_main.c BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); BIT 1338 drivers/net/ethernet/mellanox/mlx5/core/en_main.c sq->state |= BIT(MLX5E_SQ_STATE_AM); BIT 150 drivers/net/ethernet/mellanox/mlx5/core/en_rep.h MLX5_ENCAP_ENTRY_VALID = BIT(0), BIT 1265 drivers/net/ethernet/mellanox/mlx5/core/en_rx.c ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz)); BIT 326 drivers/net/ethernet/mellanox/mlx5/core/en_stats.h MLX5E_NDO_UPDATE_STATS = BIT(0x1), BIT 152 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16) BIT 966 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size))); BIT 1821 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c ~(BIT(FLOW_DISSECTOR_KEY_META) | BIT 1822 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_CONTROL) | BIT 1823 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_BASIC) | BIT 1824 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | BIT 1825 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_VLAN) | BIT 1826 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_CVLAN) | BIT 1827 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | BIT 1828 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | BIT 1829 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_PORTS) | BIT 1830 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) | BIT 1831 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) | BIT 1832 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) | BIT 1833 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) | BIT 1834 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) | BIT 1835 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_TCP) | BIT 1836 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_IP) | BIT 1837 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_ENC_IP) | BIT 1838 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) { BIT 3471 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS); BIT 3473 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS); BIT 3476 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH); BIT 3478 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC); BIT 3600 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH); BIT 3739 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC); BIT 50 drivers/net/ethernet/mellanox/mlx5/core/en_tc.h #define MLX5_TC_FLAG(flag) BIT(MLX5E_TC_FLAG_##flag##_BIT) BIT 340 drivers/net/ethernet/mellanox/mlx5/core/eswitch.c table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size)); BIT 107 drivers/net/ethernet/mellanox/mlx5/core/eswitch.h MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), BIT 108 drivers/net/ethernet/mellanox/mlx5/core/eswitch.h MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), BIT 109 drivers/net/ethernet/mellanox/mlx5/core/eswitch.h MLX5_VPORT_PROMISC_CHANGE = BIT(3), BIT 137 drivers/net/ethernet/mellanox/mlx5/core/eswitch.h ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0), BIT 214 drivers/net/ethernet/mellanox/mlx5/core/eswitch.h MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), BIT 353 drivers/net/ethernet/mellanox/mlx5/core/eswitch.h SET_VLAN_STRIP = BIT(0), BIT 354 drivers/net/ethernet/mellanox/mlx5/core/eswitch.h SET_VLAN_INSERT = BIT(1) BIT 368 drivers/net/ethernet/mellanox/mlx5/core/eswitch.h MLX5_ESW_DEST_ENCAP = BIT(0), BIT 369 drivers/net/ethernet/mellanox/mlx5/core/eswitch.h MLX5_ESW_DEST_ENCAP_VALID = BIT(1), BIT 444 drivers/net/ethernet/mellanox/mlx5/core/eswitch.h #define MLX5_DEBUG_ESWITCH_MASK BIT(3) BIT 64 drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h MLX5_FPGA_QPC_STATE = BIT(0), BIT 127 drivers/net/ethernet/mellanox/mlx5/core/fpga/tls.c #define SWID_END BIT(24) BIT 537 drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c int max_list_size = BIT(MLX5_CAP_FLOWTABLE_TYPE(dev, BIT 493 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c BIT(MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION) | BIT 494 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c BIT(MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS); BIT 502 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c BIT(MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST); BIT 893 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c int modify_mask = BIT(MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST); BIT 1227 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c static int count = BIT(MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS); BIT 1228 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c static int dst = BIT(MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST); BIT 1298 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c modify_mask |= BIT(MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION); BIT 42 drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c #define MLX5_SW_MAX_COUNTERS_BULK BIT(15) BIT 43 drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c #define MLX5_FC_POOL_MAX_THRESHOLD BIT(18) BIT 61 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c MLX5_MTPPS_FS_ENABLE = BIT(0x0), BIT 62 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c MLX5_MTPPS_FS_PATTERN = BIT(0x2), BIT 63 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c MLX5_MTPPS_FS_PIN_MODE = BIT(0x3), BIT 64 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c MLX5_MTPPS_FS_TIME_STAMP = BIT(0x4), BIT 65 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c MLX5_MTPPS_FS_OUT_PULSE_DURATION = BIT(0x5), BIT 66 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c MLX5_MTPPS_FS_ENH_OUT_PER_ADJ = BIT(0x7), BIT 34 drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c BIT(MLX5_CAP_DEV_MEM(dev, log_steering_sw_icm_size) - BIT 46 drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c BIT(MLX5_CAP_DEV_MEM(dev, log_header_modify_sw_icm_size) - BIT 76 drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c BIT(MLX5_CAP_DEV_MEM(dev, log_steering_sw_icm_size) - BIT 83 drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c BIT(MLX5_CAP_DEV_MEM(dev, BIT 138 drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c max_blocks = BIT(log_icm_size - MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)); BIT 86 drivers/net/ethernet/mellanox/mlx5/core/lib/hv_vhca.c if (!(BIT(agent->type) & hwork->block_mask)) BIT 112 drivers/net/ethernet/mellanox/mlx5/core/lib/hv_vhca.c #define AGENT_MASK(type) (type ? BIT(type - 1) : 0 /* control */) BIT 248 drivers/net/ethernet/mellanox/mlx5/core/lib/hv_vhca.c mlx5_hv_vhca_invalidate(hv_vhca, BIT(MLX5_HV_VHCA_AGENT_CONTROL)); BIT 40 drivers/net/ethernet/mellanox/mlx5/core/lib/mpfs.h #define MLX5_L2_ADDR_HASH_SIZE (BIT(BITS_PER_BYTE)) BIT 73 drivers/net/ethernet/mellanox/mlx5/core/qp.c mask = BIT(MLX5_EVENT_TYPE_PATH_MIG) | BIT 74 drivers/net/ethernet/mellanox/mlx5/core/qp.c BIT(MLX5_EVENT_TYPE_COMM_EST) | BIT 75 drivers/net/ethernet/mellanox/mlx5/core/qp.c BIT(MLX5_EVENT_TYPE_SQ_DRAINED) | BIT 76 drivers/net/ethernet/mellanox/mlx5/core/qp.c BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) | BIT 77 drivers/net/ethernet/mellanox/mlx5/core/qp.c BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | BIT 78 drivers/net/ethernet/mellanox/mlx5/core/qp.c BIT(MLX5_EVENT_TYPE_PATH_MIG_FAILED) | BIT 79 drivers/net/ethernet/mellanox/mlx5/core/qp.c BIT(MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | BIT 80 drivers/net/ethernet/mellanox/mlx5/core/qp.c BIT(MLX5_EVENT_TYPE_WQ_ACCESS_ERROR); BIT 89 drivers/net/ethernet/mellanox/mlx5/core/qp.c mask = BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) | BIT 90 drivers/net/ethernet/mellanox/mlx5/core/qp.c BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR); BIT 97 drivers/net/ethernet/mellanox/mlx5/core/qp.c return BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR); BIT 102 drivers/net/ethernet/mellanox/mlx5/core/qp.c return BIT(MLX5_EVENT_TYPE_DCT_DRAINED); BIT 109 drivers/net/ethernet/mellanox/mlx5/core/qp.c return BIT(event_type) & qp_allowed_event_types(); BIT 111 drivers/net/ethernet/mellanox/mlx5/core/qp.c return BIT(event_type) & rq_allowed_event_types(); BIT 113 drivers/net/ethernet/mellanox/mlx5/core/qp.c return BIT(event_type) & sq_allowed_event_types(); BIT 115 drivers/net/ethernet/mellanox/mlx5/core/qp.c return BIT(event_type) & dct_allowed_event_types(); BIT 18 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c #define DR_STE_ENABLE_FLOW_TAG BIT(31) BIT 353 drivers/net/ethernet/mellanox/mlxsw/core.h #define MLXSW_BUS_F_TXRX BIT(0) BIT 354 drivers/net/ethernet/mellanox/mlxsw/core.h #define MLXSW_BUS_F_RESET BIT(1) BIT 510 drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c if (tacho_active & BIT(type_index)) { BIT 521 drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c if (pwm_active & BIT(type_index)) BIT 93 drivers/net/ethernet/mellanox/mlxsw/core_thermal.c #define MLXSW_THERMAL_TRIP_MASK (BIT(MLXSW_THERMAL_NUM_TRIPS) - 1) BIT 1003 drivers/net/ethernet/mellanox/mlxsw/core_thermal.c if (tacho_active & BIT(i)) { BIT 1023 drivers/net/ethernet/mellanox/mlxsw/core_thermal.c if (pwm_active & BIT(i)) { BIT 27 drivers/net/ethernet/mellanox/mlxsw/i2c.c #define MLXSW_I2C_EVENT_BIT BIT(MLXSW_I2C_EVENT_BIT_SHIFT) BIT 28 drivers/net/ethernet/mellanox/mlxsw/i2c.c #define MLXSW_I2C_GO_BIT BIT(MLXSW_I2C_GO_BIT_SHIFT) BIT 29 drivers/net/ethernet/mellanox/mlxsw/i2c.c #define MLXSW_I2C_GO_OPMODE BIT(MLXSW_I2C_OPMOD_SHIFT) BIT 22 drivers/net/ethernet/mellanox/mlxsw/pci_hw.h #define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23) BIT 23 drivers/net/ethernet/mellanox/mlxsw/pci_hw.h #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22) BIT 29 drivers/net/ethernet/mellanox/mlxsw/pci_hw.h #define MLXSW_PCI_SW_RESET_RST_BIT BIT(0) BIT 1385 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) BIT 1387 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) BIT 1389 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) BIT 1394 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) BIT 1396 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) BIT 1401 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) BIT 1403 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) BIT 1408 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) BIT 1410 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) BIT 1415 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) BIT 1417 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) BIT 1419 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) BIT 1421 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) BIT 1423 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) BIT 1425 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) BIT 1427 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) BIT 1429 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) BIT 1431 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) BIT 1433 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) BIT 4078 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) BIT 4079 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) BIT 4102 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) BIT 4103 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) BIT 4104 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2) BIT 4105 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) BIT 4106 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) BIT 4107 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) BIT 4108 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) BIT 4109 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) BIT 4110 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) BIT 4111 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) BIT 4112 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) BIT 4113 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) BIT 4121 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) BIT 4122 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) BIT 4123 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) BIT 4124 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) BIT 4125 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) BIT 4126 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) BIT 4127 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) BIT 4128 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) BIT 4129 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) BIT 4130 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) BIT 4131 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) BIT 4132 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) BIT 4133 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) BIT 4134 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) BIT 4135 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) BIT 4136 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) BIT 4137 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) BIT 4138 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) BIT 4139 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) BIT 4140 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) BIT 4141 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) BIT 4142 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) BIT 4143 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) BIT 4144 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) BIT 4145 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) BIT 4146 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) BIT 4147 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) BIT 4161 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) BIT 4162 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) BIT 4163 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) BIT 4164 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) BIT 4165 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) BIT 4166 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) BIT 5358 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) BIT 6837 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) BIT 6838 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) BIT 6839 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) BIT 7288 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) BIT 7289 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) BIT 7507 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) BIT 7509 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) BIT 7511 drivers/net/ethernet/mellanox/mlxsw/reg.h #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) BIT 8152 drivers/net/ethernet/mellanox/mlxsw/reg.h *fault = limit & BIT(tacho); BIT 947 drivers/net/ethernet/mellanox/mlxsw/spectrum.c pfc = pfc_en & BIT(j); BIT 2914 drivers/net/ethernet/mellanox/mlxsw/spectrum.c #define MLXSW_SP_PORT_MASK_WIDTH_1X BIT(0) BIT 2915 drivers/net/ethernet/mellanox/mlxsw/spectrum.c #define MLXSW_SP_PORT_MASK_WIDTH_2X BIT(1) BIT 2916 drivers/net/ethernet/mellanox/mlxsw/spectrum.c #define MLXSW_SP_PORT_MASK_WIDTH_4X BIT(2) BIT 5271 drivers/net/ethernet/mellanox/mlxsw/spectrum.c BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), BIT 5326 drivers/net/ethernet/mellanox/mlxsw/spectrum.c BIT(DEVLINK_PARAM_CMODE_RUNTIME), BIT 338 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c ~(BIT(FLOW_DISSECTOR_KEY_META) | BIT 339 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c BIT(FLOW_DISSECTOR_KEY_CONTROL) | BIT 340 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c BIT(FLOW_DISSECTOR_KEY_BASIC) | BIT 341 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | BIT 342 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | BIT 343 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | BIT 344 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c BIT(FLOW_DISSECTOR_KEY_PORTS) | BIT 345 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c BIT(FLOW_DISSECTOR_KEY_TCP) | BIT 346 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c BIT(FLOW_DISSECTOR_KEY_IP) | BIT 347 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c BIT(FLOW_DISSECTOR_KEY_VLAN))) { BIT 849 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c message_type = BIT(MLXSW_SP_PTP_MESSAGE_TYPE_SYNC) | BIT 850 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c BIT(MLXSW_SP_PTP_MESSAGE_TYPE_DELAY_REQ) | BIT 851 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c BIT(MLXSW_SP_PTP_MESSAGE_TYPE_PDELAY_REQ) | BIT 852 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c BIT(MLXSW_SP_PTP_MESSAGE_TYPE_PDELAY_RESP); BIT 1106 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT 1107 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c BIT(HWTSTAMP_TX_ON); BIT 1109 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT 1110 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c BIT(HWTSTAMP_FILTER_ALL); BIT 222 drivers/net/ethernet/mellanox/mlxsw/spectrum_qdisc.c if (prio_bitmap & BIT(i)) { BIT 536 drivers/net/ethernet/mellanox/mlxsw/spectrum_qdisc.c child_qdisc->prio_bitmap |= BIT(i); BIT 537 drivers/net/ethernet/mellanox/mlxsw/spectrum_qdisc.c if (BIT(i) & old_priomap) BIT 239 drivers/net/ethernet/mellanox/mlxsw/switchib.c BIT(3) - 1); BIT 1185 drivers/net/ethernet/mellanox/mlxsw/switchx2.c BIT(3) - 1); BIT 684 drivers/net/ethernet/microchip/lan743x_ethtool.c ts_info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT 685 drivers/net/ethernet/microchip/lan743x_ethtool.c BIT(HWTSTAMP_TX_ON) | BIT 686 drivers/net/ethernet/microchip/lan743x_ethtool.c BIT(HWTSTAMP_TX_ONESTEP_SYNC); BIT 687 drivers/net/ethernet/microchip/lan743x_ethtool.c ts_info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT 688 drivers/net/ethernet/microchip/lan743x_ethtool.c BIT(HWTSTAMP_FILTER_ALL); BIT 2732 drivers/net/ethernet/microchip/lan743x_main.c adapter->mdiobus->phy_mask = ~(u32)BIT(1); BIT 30 drivers/net/ethernet/microchip/lan743x_main.h #define HW_CFG_EE_OTP_RELOAD_ BIT(4) BIT 31 drivers/net/ethernet/microchip/lan743x_main.h #define HW_CFG_LRST_ BIT(1) BIT 34 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) BIT 35 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) BIT 36 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) BIT 37 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) BIT 38 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) BIT 39 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) BIT 40 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) BIT 41 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_READY_ BIT(7) BIT 42 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_ETH_PHY_RST_ BIT(4) BIT 43 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_WOL_EN_ BIT(3) BIT 44 drivers/net/ethernet/microchip/lan743x_main.h #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) BIT 48 drivers/net/ethernet/microchip/lan743x_main.h #define DP_SEL_DPRDY_ BIT(31) BIT 63 drivers/net/ethernet/microchip/lan743x_main.h #define E2P_CMD_EPC_BUSY_ BIT(31) BIT 67 drivers/net/ethernet/microchip/lan743x_main.h #define E2P_CMD_EPC_TIMEOUT_ BIT(10) BIT 73 drivers/net/ethernet/microchip/lan743x_main.h #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) BIT 74 drivers/net/ethernet/microchip/lan743x_main.h #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) BIT 77 drivers/net/ethernet/microchip/lan743x_main.h #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit)) BIT 78 drivers/net/ethernet/microchip/lan743x_main.h #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit)) BIT 81 drivers/net/ethernet/microchip/lan743x_main.h #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit)) BIT 84 drivers/net/ethernet/microchip/lan743x_main.h #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit)) BIT 85 drivers/net/ethernet/microchip/lan743x_main.h #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit)) BIT 88 drivers/net/ethernet/microchip/lan743x_main.h #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) BIT 89 drivers/net/ethernet/microchip/lan743x_main.h #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) BIT 90 drivers/net/ethernet/microchip/lan743x_main.h #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) BIT 93 drivers/net/ethernet/microchip/lan743x_main.h #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) BIT 94 drivers/net/ethernet/microchip/lan743x_main.h #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) BIT 95 drivers/net/ethernet/microchip/lan743x_main.h #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) BIT 101 drivers/net/ethernet/microchip/lan743x_main.h #define FCT_FLOW_CTL_REQ_EN_ BIT(7) BIT 107 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_CR_EEE_EN_ BIT(17) BIT 108 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_CR_ADD_ BIT(12) BIT 109 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_CR_ASD_ BIT(11) BIT 110 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_CR_CNTR_RST_ BIT(5) BIT 111 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_CR_RST_ BIT(0) BIT 116 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_RX_RXD_ BIT(1) BIT 117 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_RX_RXEN_ BIT(0) BIT 120 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_TX_TXD_ BIT(1) BIT 121 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_TX_TXEN_ BIT(0) BIT 124 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_FLOW_CR_TX_FCEN_ BIT(30) BIT 125 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_FLOW_CR_RX_FCEN_ BIT(29) BIT 139 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_MII_ACC_MII_BUSY_ BIT(0) BIT 146 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) BIT 147 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_WUCSR_PFDA_EN_ BIT(3) BIT 148 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_WUCSR_WAKE_EN_ BIT(2) BIT 149 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_WUCSR_MPEN_ BIT(1) BIT 150 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_WUCSR_BCST_EN_ BIT(0) BIT 158 drivers/net/ethernet/microchip/lan743x_main.h #define MAC_WUF_CFG_EN_ BIT(31) BIT 179 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_ADDR_FILT_HI_VALID_ BIT(31) BIT 185 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_CTL_AB_ BIT(10) BIT 186 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_CTL_AM_ BIT(9) BIT 187 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_CTL_AU_ BIT(8) BIT 188 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_CTL_MCAST_HASH_ BIT(3) BIT 189 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_CTL_DA_PERFECT_ BIT(1) BIT 192 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16) BIT 193 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15) BIT 194 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_IPV6_EX_ BIT(14) BIT 195 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_UDP_IPV6_ BIT(13) BIT 196 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_TCP_IPV6_ BIT(12) BIT 197 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_IPV6_ BIT(11) BIT 198 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_UDP_IPV4_ BIT(10) BIT 199 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_TCP_IPV4_ BIT(9) BIT 200 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_IPV4_ BIT(8) BIT 202 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2) BIT 203 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1) BIT 204 drivers/net/ethernet/microchip/lan743x_main.h #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0) BIT 213 drivers/net/ethernet/microchip/lan743x_main.h #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) BIT 215 drivers/net/ethernet/microchip/lan743x_main.h #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) BIT 217 drivers/net/ethernet/microchip/lan743x_main.h #define INT_BIT_SW_GP_ BIT(9) BIT 218 drivers/net/ethernet/microchip/lan743x_main.h #define INT_BIT_1588_ BIT(7) BIT 220 drivers/net/ethernet/microchip/lan743x_main.h #define INT_BIT_MAS_ BIT(0) BIT 233 drivers/net/ethernet/microchip/lan743x_main.h #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) BIT 261 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) BIT 262 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) BIT 263 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) BIT 264 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) BIT 265 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2) BIT 266 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1) BIT 267 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_CMD_CTL_PTP_RESET_ BIT(0) BIT 279 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) BIT 284 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) BIT 285 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_INT_BIT_TX_TS_ BIT(12) BIT 286 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_INT_BIT_TIMER_B_ BIT(1) BIT 287 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_INT_BIT_TIMER_A_ BIT(0) BIT 293 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31) BIT 295 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31) BIT 326 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_CFG_COAL_EN_ BIT(16) BIT 333 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) BIT 340 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) BIT 341 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) BIT 342 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) BIT 343 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) BIT 360 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_CMD_SWR_ BIT(31) BIT 361 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) BIT 362 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) BIT 363 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) BIT 364 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) BIT 365 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) BIT 366 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) BIT 371 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) BIT 372 drivers/net/ethernet/microchip/lan743x_main.h #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) BIT 375 drivers/net/ethernet/microchip/lan743x_main.h #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) BIT 385 drivers/net/ethernet/microchip/lan743x_main.h #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) BIT 388 drivers/net/ethernet/microchip/lan743x_main.h #define RX_CFG_B_TS_ALL_RX_ BIT(29) BIT 406 drivers/net/ethernet/microchip/lan743x_main.h #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) BIT 407 drivers/net/ethernet/microchip/lan743x_main.h #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) BIT 410 drivers/net/ethernet/microchip/lan743x_main.h #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) BIT 411 drivers/net/ethernet/microchip/lan743x_main.h #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) BIT 412 drivers/net/ethernet/microchip/lan743x_main.h #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) BIT 416 drivers/net/ethernet/microchip/lan743x_main.h #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) BIT 424 drivers/net/ethernet/microchip/lan743x_main.h #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) BIT 444 drivers/net/ethernet/microchip/lan743x_main.h #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) BIT 445 drivers/net/ethernet/microchip/lan743x_main.h #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) BIT 446 drivers/net/ethernet/microchip/lan743x_main.h #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) BIT 449 drivers/net/ethernet/microchip/lan743x_main.h #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) BIT 450 drivers/net/ethernet/microchip/lan743x_main.h #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) BIT 451 drivers/net/ethernet/microchip/lan743x_main.h #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) BIT 452 drivers/net/ethernet/microchip/lan743x_main.h #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) BIT 456 drivers/net/ethernet/microchip/lan743x_main.h #define OTP_PWR_DN_PWRDN_N_ BIT(0) BIT 464 drivers/net/ethernet/microchip/lan743x_main.h #define OTP_PRGM_MODE_BYTE_ BIT(0) BIT 469 drivers/net/ethernet/microchip/lan743x_main.h #define OTP_FUNC_CMD_READ_ BIT(0) BIT 472 drivers/net/ethernet/microchip/lan743x_main.h #define OTP_TST_CMD_PRGVRFY_ BIT(3) BIT 475 drivers/net/ethernet/microchip/lan743x_main.h #define OTP_CMD_GO_GO_ BIT(0) BIT 478 drivers/net/ethernet/microchip/lan743x_main.h #define OTP_STATUS_BUSY_ BIT(0) BIT 562 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_CSR_FLAG_IS_A0 BIT(0) BIT 563 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_CSR_FLAG_IS_B0 BIT(1) BIT 564 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) BIT 576 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) BIT 577 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) BIT 578 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) BIT 579 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) BIT 580 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) BIT 581 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) BIT 582 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) BIT 583 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) BIT 584 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) BIT 585 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) BIT 586 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) BIT 587 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) BIT 588 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) BIT 589 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) BIT 590 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) BIT 591 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) BIT 634 drivers/net/ethernet/microchip/lan743x_main.h #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) BIT 636 drivers/net/ethernet/microchip/lan743x_main.h #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0) BIT 637 drivers/net/ethernet/microchip/lan743x_main.h #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1) BIT 721 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_ADAPTER_FLAG_OTP BIT(0) BIT 725 drivers/net/ethernet/microchip/lan743x_main.h #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) BIT 727 drivers/net/ethernet/microchip/lan743x_main.h #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) BIT 728 drivers/net/ethernet/microchip/lan743x_main.h #define INTR_FLAG_MSI_ENABLED BIT(8) BIT 729 drivers/net/ethernet/microchip/lan743x_main.h #define INTR_FLAG_MSIX_ENABLED BIT(9) BIT 734 drivers/net/ethernet/microchip/lan743x_main.h #define PHY_FLAG_OPENED BIT(0) BIT 735 drivers/net/ethernet/microchip/lan743x_main.h #define PHY_FLAG_ATTACHED BIT(1) BIT 781 drivers/net/ethernet/microchip/lan743x_main.h #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) BIT 782 drivers/net/ethernet/microchip/lan743x_main.h #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1) BIT 783 drivers/net/ethernet/microchip/lan743x_main.h #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) BIT 784 drivers/net/ethernet/microchip/lan743x_main.h #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) BIT 819 drivers/net/ethernet/microchip/lan743x_main.h #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) BIT 101 drivers/net/ethernet/microchip/lan743x_ptp.c BIT(i)) != 0); BIT 151 drivers/net/ethernet/microchip/lan743x_ptp.c ptp->used_event_ch |= BIT(index); BIT 167 drivers/net/ethernet/microchip/lan743x_ptp.c ptp->used_event_ch &= ~BIT(event_channel); BIT 187 drivers/net/ethernet/microchip/lan743x_ptp.c int bit_mask = BIT(bit); BIT 231 drivers/net/ethernet/microchip/lan743x_ptp.c int bit_mask = BIT(bit); BIT 820 drivers/net/ethernet/microchip/lan743x_ptp.c BIT(ptp->tx_ts_skb_queue_size); BIT 43 drivers/net/ethernet/microchip/lan743x_ptp.h #define PTP_FLAG_PTP_CLOCK_REGISTERED BIT(1) BIT 44 drivers/net/ethernet/microchip/lan743x_ptp.h #define PTP_FLAG_ISR_ENABLED BIT(2) BIT 121 drivers/net/ethernet/moxa/moxart_ether.h #define RPKT_FINISH BIT(0) /* DMA data received */ BIT 122 drivers/net/ethernet/moxa/moxart_ether.h #define NORXBUF BIT(1) /* receive buffer unavailable */ BIT 123 drivers/net/ethernet/moxa/moxart_ether.h #define XPKT_FINISH BIT(2) /* DMA moved data to TX FIFO */ BIT 124 drivers/net/ethernet/moxa/moxart_ether.h #define NOTXBUF BIT(3) /* transmit buffer unavailable */ BIT 125 drivers/net/ethernet/moxa/moxart_ether.h #define XPKT_OK_INT_STS BIT(4) /* transmit to ethernet success */ BIT 126 drivers/net/ethernet/moxa/moxart_ether.h #define XPKT_LOST_INT_STS BIT(5) /* transmit ethernet lost (collision) */ BIT 127 drivers/net/ethernet/moxa/moxart_ether.h #define RPKT_SAV BIT(6) /* FIFO receive success */ BIT 128 drivers/net/ethernet/moxa/moxart_ether.h #define RPKT_LOST_INT_STS BIT(7) /* FIFO full, receive failed */ BIT 129 drivers/net/ethernet/moxa/moxart_ether.h #define AHB_ERR BIT(8) /* AHB error */ BIT 130 drivers/net/ethernet/moxa/moxart_ether.h #define PHYSTS_CHG BIT(9) /* PHY link status change */ BIT 133 drivers/net/ethernet/moxa/moxart_ether.h #define RPKT_FINISH_M BIT(0) BIT 134 drivers/net/ethernet/moxa/moxart_ether.h #define NORXBUF_M BIT(1) BIT 135 drivers/net/ethernet/moxa/moxart_ether.h #define XPKT_FINISH_M BIT(2) BIT 136 drivers/net/ethernet/moxa/moxart_ether.h #define NOTXBUF_M BIT(3) BIT 137 drivers/net/ethernet/moxa/moxart_ether.h #define XPKT_OK_M BIT(4) BIT 138 drivers/net/ethernet/moxa/moxart_ether.h #define XPKT_LOST_M BIT(5) BIT 139 drivers/net/ethernet/moxa/moxart_ether.h #define RPKT_SAV_M BIT(6) BIT 140 drivers/net/ethernet/moxa/moxart_ether.h #define RPKT_LOST_M BIT(7) BIT 141 drivers/net/ethernet/moxa/moxart_ether.h #define AHB_ERR_M BIT(8) BIT 142 drivers/net/ethernet/moxa/moxart_ether.h #define PHYSTS_CHG_M BIT(9) BIT 148 drivers/net/ethernet/moxa/moxart_ether.h #define TXINT_TIME_SEL BIT(15) /* TX cycle time period */ BIT 151 drivers/net/ethernet/moxa/moxart_ether.h #define RXINT_TIME_SEL BIT(7) /* RX cycle time period */ BIT 156 drivers/net/ethernet/moxa/moxart_ether.h #define TXPOLL_TIME_SEL BIT(12) /* TX poll time period */ BIT 159 drivers/net/ethernet/moxa/moxart_ether.h #define RXPOLL_TIME_SEL BIT(4) /* RX poll time period */ BIT 164 drivers/net/ethernet/moxa/moxart_ether.h #define RX_THR_EN BIT(9) /* RX FIFO threshold arbitration */ BIT 167 drivers/net/ethernet/moxa/moxart_ether.h #define INCR16_EN BIT(2) /* AHB bus INCR16 burst command */ BIT 168 drivers/net/ethernet/moxa/moxart_ether.h #define INCR8_EN BIT(1) /* AHB bus INCR8 burst command */ BIT 169 drivers/net/ethernet/moxa/moxart_ether.h #define INCR4_EN BIT(0) /* AHB bus INCR4 burst command */ BIT 172 drivers/net/ethernet/moxa/moxart_ether.h #define RX_BROADPKT BIT(17) /* receive broadcast packets */ BIT 173 drivers/net/ethernet/moxa/moxart_ether.h #define RX_MULTIPKT BIT(16) /* receive all multicast packets */ BIT 174 drivers/net/ethernet/moxa/moxart_ether.h #define FULLDUP BIT(15) /* full duplex */ BIT 175 drivers/net/ethernet/moxa/moxart_ether.h #define CRC_APD BIT(14) /* append CRC to transmitted packet */ BIT 176 drivers/net/ethernet/moxa/moxart_ether.h #define RCV_ALL BIT(12) /* ignore incoming packet destination */ BIT 177 drivers/net/ethernet/moxa/moxart_ether.h #define RX_FTL BIT(11) /* accept packets larger than 1518 B */ BIT 178 drivers/net/ethernet/moxa/moxart_ether.h #define RX_RUNT BIT(10) /* accept packets smaller than 64 B */ BIT 179 drivers/net/ethernet/moxa/moxart_ether.h #define HT_MULTI_EN BIT(9) /* accept on hash and mcast pass */ BIT 180 drivers/net/ethernet/moxa/moxart_ether.h #define RCV_EN BIT(8) /* receiver enable */ BIT 181 drivers/net/ethernet/moxa/moxart_ether.h #define ENRX_IN_HALFTX BIT(6) /* enable receive in half duplex mode */ BIT 182 drivers/net/ethernet/moxa/moxart_ether.h #define XMT_EN BIT(5) /* transmit enable */ BIT 183 drivers/net/ethernet/moxa/moxart_ether.h #define CRC_DIS BIT(4) /* disable CRC check when receiving */ BIT 184 drivers/net/ethernet/moxa/moxart_ether.h #define LOOP_EN BIT(3) /* internal loop-back */ BIT 185 drivers/net/ethernet/moxa/moxart_ether.h #define SW_RST BIT(2) /* software reset, last 64 AHB clocks */ BIT 186 drivers/net/ethernet/moxa/moxart_ether.h #define RDMA_EN BIT(1) /* enable receive DMA chan */ BIT 187 drivers/net/ethernet/moxa/moxart_ether.h #define XDMA_EN BIT(0) /* enable transmit DMA chan */ BIT 190 drivers/net/ethernet/moxa/moxart_ether.h #define COL_EXCEED BIT(11) /* more than 16 collisions */ BIT 191 drivers/net/ethernet/moxa/moxart_ether.h #define LATE_COL BIT(10) /* transmit late collision detected */ BIT 192 drivers/net/ethernet/moxa/moxart_ether.h #define XPKT_LOST BIT(9) /* transmit to ethernet lost */ BIT 193 drivers/net/ethernet/moxa/moxart_ether.h #define XPKT_OK BIT(8) /* transmit to ethernet success */ BIT 194 drivers/net/ethernet/moxa/moxart_ether.h #define RUNT_MAC_STS BIT(7) /* receive runt detected */ BIT 195 drivers/net/ethernet/moxa/moxart_ether.h #define FTL_MAC_STS BIT(6) /* receive frame too long detected */ BIT 196 drivers/net/ethernet/moxa/moxart_ether.h #define CRC_ERR_MAC_STS BIT(5) BIT 197 drivers/net/ethernet/moxa/moxart_ether.h #define RPKT_LOST BIT(4) /* RX FIFO full, receive failed */ BIT 198 drivers/net/ethernet/moxa/moxart_ether.h #define RPKT_SAVE BIT(3) /* RX FIFO receive success */ BIT 199 drivers/net/ethernet/moxa/moxart_ether.h #define COL BIT(2) /* collision, incoming packet dropped */ BIT 200 drivers/net/ethernet/moxa/moxart_ether.h #define MCPU_BROADCAST BIT(1) BIT 201 drivers/net/ethernet/moxa/moxart_ether.h #define MCPU_MULTICAST BIT(0) BIT 204 drivers/net/ethernet/moxa/moxart_ether.h #define MIIWR BIT(27) /* init write sequence (auto cleared)*/ BIT 205 drivers/net/ethernet/moxa/moxart_ether.h #define MIIRD BIT(26) BIT 217 drivers/net/ethernet/moxa/moxart_ether.h #define RX_PAUSE BIT(4) /* receive pause frame */ BIT 218 drivers/net/ethernet/moxa/moxart_ether.h #define TX_PAUSED BIT(3) /* transmit pause due to receive */ BIT 219 drivers/net/ethernet/moxa/moxart_ether.h #define FCTHR_EN BIT(2) /* enable threshold mode. */ BIT 220 drivers/net/ethernet/moxa/moxart_ether.h #define TX_PAUSE BIT(1) /* transmit pause frame */ BIT 221 drivers/net/ethernet/moxa/moxart_ether.h #define FC_EN BIT(0) /* flow control mode enable */ BIT 226 drivers/net/ethernet/moxa/moxart_ether.h #define BACKP_MODE BIT(1) /* address mode */ BIT 227 drivers/net/ethernet/moxa/moxart_ether.h #define BACKP_ENABLE BIT(0) BIT 233 drivers/net/ethernet/moxa/moxart_ether.h #define TX_DMA_REQUEST BIT(31) BIT 234 drivers/net/ethernet/moxa/moxart_ether.h #define RX_DMA_REQUEST BIT(30) BIT 235 drivers/net/ethernet/moxa/moxart_ether.h #define TX_DMA_GRANT BIT(29) BIT 236 drivers/net/ethernet/moxa/moxart_ether.h #define RX_DMA_GRANT BIT(28) BIT 237 drivers/net/ethernet/moxa/moxart_ether.h #define TX_FIFO_EMPTY BIT(27) BIT 238 drivers/net/ethernet/moxa/moxart_ether.h #define RX_FIFO_EMPTY BIT(26) BIT 245 drivers/net/ethernet/moxa/moxart_ether.h #define SINGLE_PKT BIT(26) /* single packet mode */ BIT 246 drivers/net/ethernet/moxa/moxart_ether.h #define PTIMER_TEST BIT(25) /* automatic polling timer test mode */ BIT 247 drivers/net/ethernet/moxa/moxart_ether.h #define ITIMER_TEST BIT(24) /* interrupt timer test mode */ BIT 248 drivers/net/ethernet/moxa/moxart_ether.h #define TEST_SEED_SELECT BIT(22) BIT 249 drivers/net/ethernet/moxa/moxart_ether.h #define SEED_SELECT BIT(21) BIT 250 drivers/net/ethernet/moxa/moxart_ether.h #define TEST_MODE BIT(20) BIT 182 drivers/net/ethernet/mscc/ocelot.c val |= BIT(p); BIT 184 drivers/net/ethernet/mscc/ocelot.c val &= ~BIT(p); BIT 254 drivers/net/ethernet/mscc/ocelot.c ocelot->vlan_mask[vid] |= BIT(port->chip_port); BIT 296 drivers/net/ethernet/mscc/ocelot.c ocelot->vlan_mask[vid] &= ~BIT(port->chip_port); BIT 359 drivers/net/ethernet/mscc/ocelot.c if (value >= BIT(8)) BIT 360 drivers/net/ethernet/mscc/ocelot.c return BIT(8) | (value / 16); BIT 568 drivers/net/ethernet/mscc/ocelot.c if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || BIT 569 drivers/net/ethernet/mscc/ocelot.c (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) BIT 575 drivers/net/ethernet/mscc/ocelot.c info.port = BIT(port->chip_port); BIT 1190 drivers/net/ethernet/mscc/ocelot.c info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | BIT 1191 drivers/net/ethernet/mscc/ocelot.c BIT(HWTSTAMP_TX_ONESTEP_SYNC); BIT 1192 drivers/net/ethernet/mscc/ocelot.c info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); BIT 1217 drivers/net/ethernet/mscc/ocelot.c if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask)) BIT 1225 drivers/net/ethernet/mscc/ocelot.c ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port); BIT 1233 drivers/net/ethernet/mscc/ocelot.c ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port); BIT 1244 drivers/net/ethernet/mscc/ocelot.c if (ocelot->bridge_fwd_mask & BIT(port)) { BIT 1245 drivers/net/ethernet/mscc/ocelot.c unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port); BIT 1253 drivers/net/ethernet/mscc/ocelot.c if (bond_mask & BIT(port)) { BIT 1260 drivers/net/ethernet/mscc/ocelot.c BIT(ocelot->num_phys_ports) | mask, BIT 1267 drivers/net/ethernet/mscc/ocelot.c BIT(ocelot->num_phys_ports), BIT 1418 drivers/net/ethernet/mscc/ocelot.c mc->ports |= BIT(port->chip_port); BIT 1447 drivers/net/ethernet/mscc/ocelot.c mc->ports &= ~BIT(port->chip_port); BIT 1518 drivers/net/ethernet/mscc/ocelot.c ocelot->bridge_mask |= BIT(ocelot_port->chip_port); BIT 1528 drivers/net/ethernet/mscc/ocelot.c ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port); BIT 1545 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); BIT 1574 drivers/net/ethernet/mscc/ocelot.c ac |= BIT(aggr_idx[i % aggr_count]); BIT 1610 drivers/net/ethernet/mscc/ocelot.c bond_mask |= BIT(port->chip_port); BIT 1622 drivers/net/ethernet/mscc/ocelot.c bond_mask &= ~BIT(p); BIT 1629 drivers/net/ethernet/mscc/ocelot.c ocelot->lags[lp] |= BIT(p); BIT 1648 drivers/net/ethernet/mscc/ocelot.c ocelot->lags[i] &= ~BIT(ocelot_port->chip_port); BIT 2135 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); BIT 2147 drivers/net/ethernet/mscc/ocelot.c ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); BIT 57 drivers/net/ethernet/mscc/ocelot.h #define IFH_INJ_BYPASS BIT(31) BIT 355 drivers/net/ethernet/mscc/ocelot_ace.c VCAP_KEY_SET(IGR_PORT_MASK, 0, ~BIT(ace->chip_port)); BIT 11 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_ANAGEFIL_B_DOM_EN BIT(22) BIT 12 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_ANAGEFIL_B_DOM_VAL BIT(21) BIT 13 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_ANAGEFIL_AGE_LOCKED BIT(20) BIT 14 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_ANAGEFIL_PID_EN BIT(19) BIT 18 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_ANAGEFIL_VID_EN BIT(13) BIT 27 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2) BIT 31 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AUTOAGE_AGE_FAST BIT(21) BIT 35 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0) BIT 37 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1) BIT 38 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_MACTOPTIONS_SHADOW BIT(0) BIT 43 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11) BIT 44 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10) BIT 45 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9) BIT 46 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8) BIT 47 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_MIRROR_CPU BIT(7) BIT 48 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6) BIT 49 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5) BIT 50 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4) BIT 51 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3) BIT 52 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2) BIT 53 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1) BIT 54 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_RED_COUNT_MODE BIT(0) BIT 84 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1) BIT 85 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0) BIT 89 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3) BIT 93 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_MODE_L3_PARSE_CFG BIT(0) BIT 111 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16) BIT 115 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8) BIT 119 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15) BIT 120 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_SRC_KILL BIT(14) BIT 121 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13) BIT 122 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12) BIT 123 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_VALID BIT(11) BIT 150 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17) BIT 151 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16) BIT 152 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15) BIT 153 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14) BIT 154 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13) BIT 155 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12) BIT 171 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14) BIT 172 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10) BIT 187 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3) BIT 188 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2) BIT 198 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14) BIT 202 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7) BIT 203 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6) BIT 204 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5) BIT 217 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0) BIT 219 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22) BIT 223 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18) BIT 230 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26) BIT 234 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17) BIT 247 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) BIT 254 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20) BIT 258 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(28) BIT 264 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4) BIT 270 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16) BIT 274 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24) BIT 278 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21) BIT 279 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20) BIT 283 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17) BIT 284 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16) BIT 285 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15) BIT 294 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) BIT 295 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5) BIT 296 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4) BIT 297 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) BIT 298 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) BIT 299 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1) BIT 300 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) BIT 304 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8) BIT 308 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4) BIT 309 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3) BIT 310 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2) BIT 316 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_CFG_S1_ENA BIT(14) BIT 346 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14) BIT 368 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3) BIT 374 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7) BIT 375 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6) BIT 376 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5) BIT 377 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4) BIT 378 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3) BIT 379 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2) BIT 380 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1) BIT 381 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0) BIT 409 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15) BIT 410 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14) BIT 411 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13) BIT 412 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12) BIT 413 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11) BIT 414 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_LEARNDROP BIT(10) BIT 415 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_LEARNCPU BIT(9) BIT 416 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8) BIT 417 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7) BIT 418 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6) BIT 422 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1) BIT 423 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_LSR_MODE BIT(0) BIT 427 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19) BIT 428 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18) BIT 429 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17) BIT 438 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0) BIT 447 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_SFID_CFG_SFID_VALID BIT(8) BIT 470 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0) BIT 493 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGGR_CFG_AC_RND_ENA BIT(7) BIT 494 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6) BIT 495 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5) BIT 496 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4) BIT 497 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3) BIT 498 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2) BIT 499 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1) BIT 500 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0) BIT 545 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11) BIT 552 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1) BIT 553 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0) BIT 567 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12) BIT 571 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3) BIT 572 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2) BIT 573 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1) BIT 574 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0) BIT 576 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FID_CFG_VID_MC_ENA BIT(0) BIT 602 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2) BIT 603 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MODE_CFG_CIR_ENA BIT(1) BIT 604 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0) BIT 614 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_FLOWC_POL_FLOWC BIT(0) BIT 622 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1) BIT 623 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0) BIT 93 drivers/net/ethernet/mscc/ocelot_board.c if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))) BIT 178 drivers/net/ethernet/mscc/ocelot_board.c if (ocelot->bridge_mask & BIT(info.port)) BIT 185 drivers/net/ethernet/mscc/ocelot_board.c } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)); BIT 188 drivers/net/ethernet/mscc/ocelot_board.c while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) BIT 13 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) BIT 14 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) BIT 15 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) BIT 16 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) BIT 17 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_CLOCK_CFG_PORT_RST BIT(3) BIT 18 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_CLOCK_CFG_PHY_RST BIT(2) BIT 24 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4) BIT 25 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3) BIT 26 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2) BIT 27 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1) BIT 28 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PORT_MISC_HDX_FAST_DIS BIT(0) BIT 34 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_EEE_ENA BIT(22) BIT 44 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_PORT_LPI BIT(0) BIT 60 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) BIT 61 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) BIT 65 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) BIT 66 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) BIT 67 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_MODE_CFG_FDX_ENA BIT(0) BIT 76 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2) BIT 77 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_TAGS_CFG_PB_ENA BIT(1) BIT 78 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) BIT 82 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) BIT 86 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) BIT 87 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16) BIT 99 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) BIT 100 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_HDX_CFG_OB_ENA BIT(25) BIT 101 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_HDX_CFG_WEXC_DIS BIT(24) BIT 105 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) BIT 106 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8) BIT 112 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_DBG_CFG_TBI_MODE BIT(4) BIT 113 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0) BIT 121 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9) BIT 122 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8) BIT 123 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7) BIT 124 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6) BIT 125 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_STICKY_RX_JUNK_STICKY BIT(5) BIT 126 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4) BIT 127 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_STICKY_TX_JAM_STICKY BIT(3) BIT 128 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2) BIT 129 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1) BIT 130 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0) BIT 134 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_CFG_LINK_STATUS_TYPE BIT(4) BIT 135 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1) BIT 136 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_CFG_PCS_ENA BIT(0) BIT 140 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) BIT 141 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) BIT 145 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_SD_CFG_SD_SEL BIT(8) BIT 146 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_SD_CFG_SD_POL BIT(4) BIT 147 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_SD_CFG_SD_ENA BIT(0) BIT 154 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) BIT 155 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1) BIT 156 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_CFG_ANEG_ENA BIT(0) BIT 163 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT BIT(0) BIT 167 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LB_CFG_RA_ENA BIT(4) BIT 168 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1) BIT 169 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0) BIT 173 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_DBG_CFG_UDLT BIT(0) BIT 177 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_CDET_CFG_CDET_ENA BIT(0) BIT 184 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_STATUS_PR BIT(4) BIT 185 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3) BIT 186 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) BIT 195 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8) BIT 196 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LINK_STATUS_LINK_STATUS BIT(4) BIT 197 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) BIT 203 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) BIT 204 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0) BIT 210 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_CFG_QSGMII_MS_SEL BIT(20) BIT 211 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_CFG_RX_LPI_OUT_DIS BIT(17) BIT 212 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_CFG_LPI_TESTMODE BIT(16) BIT 216 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE BIT(0) BIT 222 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_STATUS_RX_LPI_FAIL BIT(16) BIT 223 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY BIT(12) BIT 224 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_STATUS_RX_QUIET BIT(9) BIT 225 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_STATUS_RX_LPI_MODE BIT(8) BIT 226 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4) BIT 227 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_STATUS_TX_QUIET BIT(1) BIT 228 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_STATUS_TX_LPI_MODE BIT(0) BIT 237 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4) BIT 238 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_TSTPAT_STATUS_JTP_LOCK BIT(0) BIT 242 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_SD_SEL BIT(26) BIT 243 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_SD_POL BIT(25) BIT 244 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_SD_ENA BIT(24) BIT 245 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_LOOPBACK_ENA BIT(20) BIT 246 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_SWAP_MII_ENA BIT(16) BIT 253 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8) BIT 257 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3) BIT 258 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_FEFCHK_ENA BIT(2) BIT 259 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_FEFGEN_ENA BIT(1) BIT 260 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_PCS_ENA BIT(0) BIT 267 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7) BIT 268 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6) BIT 269 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5) BIT 270 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4) BIT 271 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_STATUS_FEF_STATUS BIT(2) BIT 272 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1) BIT 273 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_STATUS_SYNC_STATUS BIT(0) BIT 48 drivers/net/ethernet/mscc/ocelot_flower.c ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | BIT 49 drivers/net/ethernet/mscc/ocelot_flower.c BIT(FLOW_DISSECTOR_KEY_BASIC) | BIT 50 drivers/net/ethernet/mscc/ocelot_flower.c BIT(FLOW_DISSECTOR_KEY_PORTS) | BIT 51 drivers/net/ethernet/mscc/ocelot_flower.c BIT(FLOW_DISSECTOR_KEY_VLAN) | BIT 52 drivers/net/ethernet/mscc/ocelot_flower.c BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | BIT 53 drivers/net/ethernet/mscc/ocelot_flower.c BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | BIT 54 drivers/net/ethernet/mscc/ocelot_flower.c BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) { BIT 73 drivers/net/ethernet/mscc/ocelot_flower.c (BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | BIT 74 drivers/net/ethernet/mscc/ocelot_flower.c BIT(FLOW_DISSECTOR_KEY_BASIC) | BIT 75 drivers/net/ethernet/mscc/ocelot_flower.c BIT(FLOW_DISSECTOR_KEY_CONTROL))) != BIT 76 drivers/net/ethernet/mscc/ocelot_flower.c (BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | BIT 77 drivers/net/ethernet/mscc/ocelot_flower.c BIT(FLOW_DISSECTOR_KEY_BASIC) | BIT 78 drivers/net/ethernet/mscc/ocelot_flower.c BIT(FLOW_DISSECTOR_KEY_CONTROL))) BIT 17 drivers/net/ethernet/mscc/ocelot_ptp.h #define PTP_PIN_CFG_DOM BIT(0) BIT 18 drivers/net/ethernet/mscc/ocelot_ptp.h #define PTP_PIN_CFG_SYNC BIT(2) BIT 32 drivers/net/ethernet/mscc/ocelot_ptp.h #define PTP_CFG_MISC_PTP_EN BIT(2) BIT 36 drivers/net/ethernet/mscc/ocelot_ptp.h #define PTP_CFG_CLK_ADJ_CFG_ENA BIT(0) BIT 37 drivers/net/ethernet/mscc/ocelot_ptp.h #define PTP_CFG_CLK_ADJ_CFG_DIR BIT(1) BIT 39 drivers/net/ethernet/mscc/ocelot_ptp.h #define PTP_CFG_CLK_ADJ_FREQ_NS BIT(30) BIT 27 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) BIT 28 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) BIT 48 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) BIT 57 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_CTRL_ABORT BIT(20) BIT 58 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_CTRL_EOF BIT(19) BIT 59 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_CTRL_SOF BIT(18) BIT 75 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_ERR_ABORT_ERR_STICKY BIT(1) BIT 76 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_ERR_WR_ERR_STICKY BIT(0) BIT 13 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) BIT 14 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0) BIT 18 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14) BIT 22 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SWITCH_PORT_MODE_YEL_RSRVD BIT(10) BIT 23 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(9) BIT 27 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SWITCH_PORT_MODE_TX_PFC_MODE BIT(0) BIT 29 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5) BIT 30 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4) BIT 31 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3) BIT 32 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2) BIT 33 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1) BIT 34 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0) BIT 70 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8) BIT 71 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7) BIT 145 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0) BIT 152 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CFG_SE_RR_ENA BIT(5) BIT 153 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CFG_SE_AVB_ENA BIT(4) BIT 157 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CFG_SE_EXC_ENA BIT(1) BIT 158 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CFG_SE_EXC_FWD BIT(0) BIT 177 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_TERMINAL BIT(0) BIT 190 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2) BIT 191 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1) BIT 192 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0) BIT 209 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_STATE_SE_WAS_YEL BIT(0) BIT 211 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8) BIT 215 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2) BIT 216 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1) BIT 217 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0) BIT 221 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAG_CONFIG_ENABLE BIT(0) BIT 234 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8) BIT 235 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16) BIT 262 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24) BIT 16 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_VLAN_CFG_PORT_DEI BIT(15) BIT 31 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_VID_CFG BIT(4) BIT 40 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_CFG_ES0_EN BIT(5) BIT 44 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_CFG_FCS_UPDATE_CPU_ENA BIT(2) BIT 45 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_CFG_FLUSH_ENA BIT(1) BIT 46 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_CFG_AGE_DIS BIT(0) BIT 53 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PCP_DEI_QOS_MAP_CFG_DEI_QOS_VAL BIT(3) BIT 59 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PTP_CFG_PTP_BACKPLANE_MODE BIT(7) BIT 63 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PTP_CFG_PTP_1STEP_DIS BIT(2) BIT 64 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PTP_CFG_PTP_2STEP_DIS BIT(1) BIT 65 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PTP_CFG_PTP_UDP_KEEP BIT(0) BIT 71 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_RED_TAG_CFG_RED_TAG_CFG BIT(0) BIT 77 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_REW_STICKY_ES0_TAGB_PUSH_FAILED BIT(0) BIT 12 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) BIT 13 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) BIT 14 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) BIT 18 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2) BIT 19 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1) BIT 20 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0) BIT 36 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) BIT 38 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_CTRL_TCAM_BIST BIT(1) BIT 39 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_CTRL_TCAM_INIT BIT(0) BIT 41 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8) BIT 42 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_CFG_TCAM_HCG_DIS BIT(7) BIT 43 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_CFG_TCAM_CG_DIS BIT(6) BIT 47 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_RT_ERR BIT(15) BIT 48 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_PENC_ERR BIT(14) BIT 49 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_COMP_ERR BIT(13) BIT 50 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_ADDR_ERR BIT(12) BIT 51 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_BL1E_ERR BIT(11) BIT 52 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_BL1_ERR BIT(10) BIT 53 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_BL0E_ERR BIT(9) BIT 54 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_BL0_ERR BIT(8) BIT 55 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_PH1_ERR BIT(7) BIT 56 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_PH0_ERR BIT(6) BIT 57 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_PV1_ERR BIT(5) BIT 58 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_PV0_ERR BIT(4) BIT 59 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_RUN BIT(3) BIT 60 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_ERR BIT(2) BIT 61 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_BIST_BUSY BIT(1) BIT 62 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_STAT_TCAM_RDY BIT(0) BIT 26 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PORT_MODE_INJ_HDR_ERR BIT(0) BIT 30 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(0) BIT 32 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) BIT 44 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_SW_STATUS_PORT_RX_PAUSED BIT(0) BIT 46 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MISC_CFG_PTP_RSRV_CLR BIT(1) BIT 47 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MISC_CFG_PTP_DIS_NEG_RO BIT(0) BIT 67 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) BIT 85 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) BIT 86 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) BIT 87 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) BIT 111 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_EVENTS_CORE_EV_FWR BIT(2) BIT 117 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_TXSTAMP_OAM BIT(29) BIT 118 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_OVFL BIT(28) BIT 119 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_MESS_VLD BIT(27) BIT 131 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC BIT(31) BIT 133 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_NXT_PTP_NXT BIT(0) BIT 141 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_RAM_INIT_RAM_INIT BIT(1) BIT 142 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_RAM_INIT_RAM_CFG_HOOK BIT(0) BIT 64 drivers/net/ethernet/mscc/ocelot_vcap.h #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7) BIT 874 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_RESOURCE_NO_PFN_OR_VF BIT(3) BIT 3407 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_FIFO_ERR BIT(11) BIT 3584 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_ONE BIT(3) BIT 3617 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_MRPCIM_MSG_INT BIT(3) BIT 3618 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT BIT(7) BIT 3620 drivers/net/ethernet/neterion/vxge/vxge-reg.h BIT(11) BIT 3623 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT BIT(3) BIT 3627 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT BIT(0) BIT 3628 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT BIT(1) BIT 3629 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT BIT(2) BIT 3630 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT BIT(3) BIT 3631 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT BIT(4) BIT 3632 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT BIT(5) BIT 3633 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT BIT(6) BIT 3634 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT BIT(7) BIT 3635 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT BIT(8) BIT 3636 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT BIT(9) BIT 3637 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT BIT(10) BIT 3638 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT BIT(11) BIT 3639 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT BIT(12) BIT 3640 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT BIT(13) BIT 3641 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT BIT(14) BIT 3642 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT BIT(15) BIT 3643 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT BIT(16) BIT 3652 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG BIT(0) BIT 3665 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PIC_INT BIT(0) BIT 3666 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PCI_INT BIT(3) BIT 3667 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_XMAC_INT BIT(7) BIT 3671 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PIC_INT BIT(0) BIT 3672 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PCI_INT BIT(3) BIT 3673 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_XMAC_INT BIT(7) BIT 3680 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR BIT(3) BIT 3681 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR BIT(7) BIT 3682 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR BIT(11) BIT 3683 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT BIT(15) BIT 3684 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET BIT(19) BIT 3685 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS BIT(23) BIT 3689 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM BIT(3) BIT 3701 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN BIT(19) BIT 3702 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN BIT(23) BIT 3703 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN BIT(27) BIT 3704 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN BIT(31) BIT 3705 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN BIT(35) BIT 3706 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN BIT(39) BIT 3713 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK BIT(0) BIT 3715 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK BIT(0) BIT 3717 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT BIT(0) BIT 3719 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG BIT(7) BIT 3721 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED BIT(7) BIT 3725 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK BIT(3) BIT 3726 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR BIT(7) BIT 3730 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_ASIC_NTWK_SR_INT BIT(3) BIT 3733 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT BIT(3) BIT 3734 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK BIT(7) BIT 3736 drivers/net/ethernet/neterion/vxge/vxge-reg.h BIT(11) BIT 3737 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED BIT(15) BIT 3752 drivers/net/ethernet/neterion/vxge/vxge-reg.h BIT(0) BIT 3754 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_START BIT(0) BIT 3755 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_END BIT(1) BIT 3756 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS0_FORCE_QB_START BIT(2) BIT 3757 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS0_FORCE_QB_END BIT(3) BIT 3758 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_START BIT(4) BIT 3759 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_END BIT(5) BIT 3760 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS0_MWB_OPT_EN BIT(6) BIT 3761 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS0_QB_OPT_EN BIT(7) BIT 3762 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS0_MPSB_OPT_EN BIT(8) BIT 3763 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_START BIT(9) BIT 3764 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_END BIT(10) BIT 3765 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS1_FORCE_QB_START BIT(11) BIT 3766 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS1_FORCE_QB_END BIT(12) BIT 3767 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_START BIT(13) BIT 3768 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_END BIT(14) BIT 3769 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS1_MWB_OPT_EN BIT(15) BIT 3770 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS1_QB_OPT_EN BIT(16) BIT 3771 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_NS1_MPSB_OPT_EN BIT(17) BIT 3772 drivers/net/ethernet/neterion/vxge/vxge-reg.h #define VXGE_HW_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR BIT(19) BIT 386 drivers/net/ethernet/netronome/nfp/abm/ctrl.c BIT(NFP_ABM_ACT_MARK_DROP)); BIT 232 drivers/net/ethernet/netronome/nfp/abm/main.h return abm->action_mask & BIT(NFP_ABM_ACT_DROP); BIT 237 drivers/net/ethernet/netronome/nfp/abm/main.h return abm->action_mask & BIT(NFP_ABM_ACT_MARK_DROP); BIT 43 drivers/net/ethernet/netronome/nfp/bpf/fw.h #define NFP_BPF_ADJUST_HEAD_NO_META BIT(0) BIT 254 drivers/net/ethernet/netronome/nfp/bpf/main.h #define FLAG_INSN_IS_JUMP_DST BIT(0) BIT 255 drivers/net/ethernet/netronome/nfp/bpf/main.h #define FLAG_INSN_IS_SUBPROG_START BIT(1) BIT 256 drivers/net/ethernet/netronome/nfp/bpf/main.h #define FLAG_INSN_PTR_CALLER_STACK_FRAME BIT(2) BIT 258 drivers/net/ethernet/netronome/nfp/bpf/main.h #define FLAG_INSN_SKIP_NOOP BIT(3) BIT 260 drivers/net/ethernet/netronome/nfp/bpf/main.h #define FLAG_INSN_SKIP_PREC_DEPENDENT BIT(4) BIT 262 drivers/net/ethernet/netronome/nfp/bpf/main.h #define FLAG_INSN_SKIP_VERIFIER_OPT BIT(5) BIT 264 drivers/net/ethernet/netronome/nfp/bpf/main.h #define FLAG_INSN_DO_ZEXT BIT(6) BIT 35 drivers/net/ethernet/netronome/nfp/ccm.h #define __NFP_CCM_REPLY(req) (BIT(NFP_CCM_TYPE_REPLY_BIT) | (req)) BIT 474 drivers/net/ethernet/netronome/nfp/ccm_mbox.c if (unlikely(!(nn->tlv_caps.mbox_cmsg_types & BIT(type)))) { BIT 16 drivers/net/ethernet/netronome/nfp/crypto/tls.c (BIT(NFP_CCM_TYPE_CRYPTO_RESET) | \ BIT 17 drivers/net/ethernet/netronome/nfp/crypto/tls.c BIT(NFP_CCM_TYPE_CRYPTO_ADD) | \ BIT 18 drivers/net/ethernet/netronome/nfp/crypto/tls.c BIT(NFP_CCM_TYPE_CRYPTO_DEL) | \ BIT 19 drivers/net/ethernet/netronome/nfp/crypto/tls.c BIT(NFP_CCM_TYPE_CRYPTO_UPDATE)) BIT 22 drivers/net/ethernet/netronome/nfp/crypto/tls.c BIT(NFP_NET_CRYPTO_OP_TLS_1_2_AES_GCM_128_DEC) BIT 25 drivers/net/ethernet/netronome/nfp/crypto/tls.c BIT(NFP_NET_CRYPTO_OP_TLS_1_2_AES_GCM_128_ENC) BIT 38 drivers/net/ethernet/netronome/nfp/crypto/tls.c val |= BIT(opcode & 31); BIT 40 drivers/net/ethernet/netronome/nfp/crypto/tls.c val &= ~BIT(opcode & 31); BIT 259 drivers/net/ethernet/netronome/nfp/crypto/tls.c return nn->tlv_caps.crypto_ops & BIT(bit); BIT 196 drivers/net/ethernet/netronome/nfp/devlink_param.c BIT(DEVLINK_PARAM_CMODE_PERMANENT), BIT 201 drivers/net/ethernet/netronome/nfp/devlink_param.c BIT(DEVLINK_PARAM_CMODE_PERMANENT), BIT 17 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER_EXT_META BIT(0) BIT 18 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER_PORT BIT(1) BIT 19 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER_MAC BIT(2) BIT 20 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER_TP BIT(3) BIT 21 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER_IPV4 BIT(4) BIT 22 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER_IPV6 BIT(5) BIT 23 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER_CT BIT(6) BIT 24 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER_VXLAN BIT(7) BIT 26 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER2_GRE BIT(0) BIT 27 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER2_GENEVE BIT(5) BIT 28 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_LAYER2_GENEVE_OP BIT(6) BIT 31 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_MASK_VLAN_PRESENT BIT(12) BIT 36 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_MASK_MPLS_BOS BIT(8) BIT 37 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_MASK_MPLS_Q BIT(0) BIT 39 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_IP_FRAG_FIRST BIT(7) BIT 40 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_IP_FRAGMENTED BIT(6) BIT 43 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_GRE_FLAG_KEY BIT(2) BIT 46 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_TCP_FLAG_URG BIT(4) BIT 47 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_TCP_FLAG_PSH BIT(3) BIT 48 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_TCP_FLAG_RST BIT(2) BIT 49 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_TCP_FLAG_SYN BIT(1) BIT 50 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_TCP_FLAG_FIN BIT(0) BIT 88 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_OUT_FLAGS_LAST BIT(15) BIT 89 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_OUT_FLAGS_USE_TUN BIT(4) BIT 513 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORTMOD_INFO_LINK BIT(0) BIT 514 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORTMOD_MTU_CHANGE_ONLY BIT(1) BIT 523 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORTREIFY_INFO_EXIST BIT(0) BIT 7 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_FL_LAG_LAST BIT(1) BIT 8 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_FL_LAG_FIRST BIT(2) BIT 9 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_FL_LAG_DATA BIT(3) BIT 10 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_FL_LAG_XON BIT(4) BIT 11 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_FL_LAG_SYNC BIT(5) BIT 12 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_FL_LAG_SWITCH BIT(6) BIT 13 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_FL_LAG_RESET BIT(7) BIT 16 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_PORT_LAG_LINK_UP BIT(0) BIT 17 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_PORT_LAG_TX_ENABLED BIT(1) BIT 18 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_PORT_LAG_CHANGED BIT(2) BIT 720 drivers/net/ethernet/netronome/nfp/flower/main.c ctx_count = BIT(17); BIT 33 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_META_FLAG_MANAGE_MASK BIT(7) BIT 39 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_FEATS_GENEVE BIT(0) BIT 40 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_NBI_MTU_SETTING BIT(1) BIT 41 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_FEATS_GENEVE_OPT BIT(2) BIT 42 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_FEATS_VLAN_PCP BIT(3) BIT 43 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_FEATS_VF_RLIM BIT(4) BIT 44 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_FEATS_FLOW_MOD BIT(5) BIT 45 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_FEATS_PRE_TUN_RULES BIT(6) BIT 46 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_FEATS_FLOW_MERGE BIT(30) BIT 47 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_FEATS_LAG BIT(31) BIT 26 drivers/net/ethernet/netronome/nfp/flower/offload.c (BIT(FLOW_DISSECTOR_KEY_CONTROL) | \ BIT 27 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_BASIC) | \ BIT 28 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | \ BIT 29 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | \ BIT 30 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_TCP) | \ BIT 31 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_PORTS) | \ BIT 32 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | \ BIT 33 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_VLAN) | \ BIT 34 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) | \ BIT 35 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) | \ BIT 36 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) | \ BIT 37 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) | \ BIT 38 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) | \ BIT 39 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) | \ BIT 40 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_IP) | \ BIT 41 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_MPLS) | \ BIT 42 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_IP)) BIT 45 drivers/net/ethernet/netronome/nfp/flower/offload.c (BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) | \ BIT 46 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) | \ BIT 47 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) | \ BIT 48 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) | \ BIT 49 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) | \ BIT 50 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) | \ BIT 51 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_IP)) BIT 54 drivers/net/ethernet/netronome/nfp/flower/offload.c (BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) | \ BIT 55 drivers/net/ethernet/netronome/nfp/flower/offload.c BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS)) BIT 258 drivers/net/ethernet/netronome/nfp/nfp_asm.h #define CMD_OVE_LEN BIT(7) BIT 288 drivers/net/ethernet/netronome/nfp/nfp_asm.h #define NN_REG_LM_IDX_HI BIT(23) BIT 289 drivers/net/ethernet/netronome/nfp/nfp_asm.h #define NN_REG_LM_IDX_LO BIT(22) BIT 294 drivers/net/ethernet/netronome/nfp/nfp_asm.h NN_REG_GPR_A = BIT(0), BIT 295 drivers/net/ethernet/netronome/nfp/nfp_asm.h NN_REG_GPR_B = BIT(1), BIT 297 drivers/net/ethernet/netronome/nfp/nfp_asm.h NN_REG_NNR = BIT(2), BIT 298 drivers/net/ethernet/netronome/nfp/nfp_asm.h NN_REG_XFER = BIT(3), BIT 299 drivers/net/ethernet/netronome/nfp/nfp_asm.h NN_REG_IMM = BIT(4), BIT 300 drivers/net/ethernet/netronome/nfp/nfp_asm.h NN_REG_NONE = BIT(5), BIT 301 drivers/net/ethernet/netronome/nfp/nfp_asm.h NN_REG_LMEM = BIT(6), BIT 54 drivers/net/ethernet/netronome/nfp/nfp_hwmon.c if (!(pf->nspi->sensor_mask & BIT(id))) BIT 127 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_EOP BIT(7) BIT 132 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_CSUM BIT(7) BIT 133 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_IP4_CSUM BIT(6) BIT 134 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_TCP_CSUM BIT(5) BIT 135 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_UDP_CSUM BIT(4) BIT 136 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_VLAN BIT(3) BIT 137 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_LSO BIT(2) BIT 138 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_ENCAP BIT(1) BIT 139 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_O_IP4_CSUM BIT(0) BIT 233 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_DD BIT(7) BIT 237 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_RSS cpu_to_le16(BIT(15)) BIT 238 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_I_IP4_CSUM cpu_to_le16(BIT(14)) BIT 239 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_I_IP4_CSUM_OK cpu_to_le16(BIT(13)) BIT 240 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_I_TCP_CSUM cpu_to_le16(BIT(12)) BIT 241 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_I_TCP_CSUM_OK cpu_to_le16(BIT(11)) BIT 242 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_I_UDP_CSUM cpu_to_le16(BIT(10)) BIT 243 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_I_UDP_CSUM_OK cpu_to_le16(BIT(9)) BIT 244 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_DECRYPTED cpu_to_le16(BIT(8)) BIT 245 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_EOP cpu_to_le16(BIT(7)) BIT 246 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_IP4_CSUM cpu_to_le16(BIT(6)) BIT 247 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_IP4_CSUM_OK cpu_to_le16(BIT(5)) BIT 248 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_TCP_CSUM cpu_to_le16(BIT(4)) BIT 249 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_TCP_CSUM_OK cpu_to_le16(BIT(3)) BIT 250 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_UDP_CSUM cpu_to_le16(BIT(2)) BIT 251 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_UDP_CSUM_OK cpu_to_le16(BIT(1)) BIT 252 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_VLAN cpu_to_le16(BIT(0)) BIT 393 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpp.h #define NFP_SIGNAL_MASK_A BIT(0) /* Signal A fired */ BIT 394 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpp.h #define NFP_SIGNAL_MASK_B BIT(1) /* Signal B fired */ BIT 242 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c #define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE BIT(12) BIT 244 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c #define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE_40_BIT BIT(12) BIT 85 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_hwinfo.c #define NFP_HWINFO_VERSION_UPDATING BIT(0) BIT 100 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h #define NFP_FEC_AUTO BIT(NFP_FEC_AUTO_BIT) BIT 101 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h #define NFP_FEC_BASER BIT(NFP_FEC_BASER_BIT) BIT 102 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h #define NFP_FEC_REED_SOLOMON BIT(NFP_FEC_REED_SOLOMON_BIT) BIT 103 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h #define NFP_FEC_DISABLED BIT(NFP_FEC_DISABLED_BIT) BIT 81 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_cmds.c ret = nfp_nsp_read_sensors(nsp, BIT(id), &s, sizeof(s)); BIT 81 drivers/net/ethernet/ni/nixge.c #define NIXGE_ID_LED_CTL_EN BIT(0) BIT 82 drivers/net/ethernet/ni/nixge.c #define NIXGE_ID_LED_CTL_VAL BIT(1) BIT 84 drivers/net/ethernet/ni/nixge.c #define NIXGE_MDIO_CLAUSE45 BIT(12) BIT 88 drivers/net/ethernet/ni/nixge.c #define NIXGE_MDIO_C45_WRITE BIT(0) BIT 89 drivers/net/ethernet/ni/nixge.c #define NIXGE_MDIO_C45_READ (BIT(1) | BIT(0)) BIT 90 drivers/net/ethernet/ni/nixge.c #define NIXGE_MDIO_C22_WRITE BIT(0) BIT 91 drivers/net/ethernet/ni/nixge.c #define NIXGE_MDIO_C22_READ BIT(1) BIT 2133 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK); BIT 14 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c #define PRIV_F_SW_DBG_STATS BIT(0) BIT 311 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_LIF_CAP_ETH = BIT(0), BIT 312 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_LIF_CAP_RDMA = BIT(1), BIT 879 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), BIT 880 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), BIT 881 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), BIT 882 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_RX_HASH = BIT(3), BIT 883 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_RX_CSUM = BIT(4), BIT 884 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TX_SG = BIT(5), BIT 885 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_RX_SG = BIT(6), BIT 886 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TX_CSUM = BIT(7), BIT 887 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TSO = BIT(8), BIT 888 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TSO_IPV6 = BIT(9), BIT 889 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TSO_ECN = BIT(10), BIT 890 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TSO_GRE = BIT(11), BIT 891 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), BIT 892 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), BIT 893 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), BIT 894 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TSO_UDP = BIT(15), BIT 895 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), BIT 1370 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RSS_TYPE_IPV4 = BIT(0), BIT 1371 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RSS_TYPE_IPV4_TCP = BIT(1), BIT 1372 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RSS_TYPE_IPV4_UDP = BIT(2), BIT 1373 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RSS_TYPE_IPV6 = BIT(3), BIT 1374 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RSS_TYPE_IPV6_TCP = BIT(4), BIT 1375 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RSS_TYPE_IPV6_UDP = BIT(5), BIT 1487 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RX_MODE_F_UNICAST = BIT(0), BIT 1488 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RX_MODE_F_MULTICAST = BIT(1), BIT 1489 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RX_MODE_F_BROADCAST = BIT(2), BIT 1490 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RX_MODE_F_PROMISC = BIT(3), BIT 1491 drivers/net/ethernet/pensando/ionic/ionic_if.h IONIC_RX_MODE_F_ALLMULTI = BIT(4), BIT 1665 drivers/net/ethernet/pensando/ionic/ionic_if.h #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) BIT 1666 drivers/net/ethernet/pensando/ionic/ionic_if.h #define IONIC_QOS_CONFIG_F_DROP BIT(1) BIT 1667 drivers/net/ethernet/pensando/ionic/ionic_if.h #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) BIT 1668 drivers/net/ethernet/pensando/ionic/ionic_if.h #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) BIT 42 drivers/net/ethernet/pensando/ionic/ionic_lif.h #define IONIC_QCQ_F_INITED BIT(0) BIT 43 drivers/net/ethernet/pensando/ionic/ionic_lif.h #define IONIC_QCQ_F_SG BIT(1) BIT 44 drivers/net/ethernet/pensando/ionic/ionic_lif.h #define IONIC_QCQ_F_INTR BIT(2) BIT 45 drivers/net/ethernet/pensando/ionic/ionic_lif.h #define IONIC_QCQ_F_TX_STATS BIT(3) BIT 46 drivers/net/ethernet/pensando/ionic/ionic_lif.h #define IONIC_QCQ_F_RX_STATS BIT(4) BIT 47 drivers/net/ethernet/pensando/ionic/ionic_lif.h #define IONIC_QCQ_F_NOTIFYQ BIT(5) BIT 18 drivers/net/ethernet/pensando/ionic/ionic_rx_filter.h #define IONIC_RX_FILTER_HLISTS BIT(IONIC_RX_FILTER_HASH_BITS) BIT 833 drivers/net/ethernet/qlogic/qed/qed.h #define QED_FLAG_STORAGE_STARTED (BIT(0)) BIT 931 drivers/net/ethernet/qlogic/qed/qed.h #define PQ_FLAGS_RLS (BIT(0)) BIT 932 drivers/net/ethernet/qlogic/qed/qed.h #define PQ_FLAGS_MCOS (BIT(1)) BIT 933 drivers/net/ethernet/qlogic/qed/qed.h #define PQ_FLAGS_LB (BIT(2)) BIT 934 drivers/net/ethernet/qlogic/qed/qed.h #define PQ_FLAGS_OOO (BIT(3)) BIT 935 drivers/net/ethernet/qlogic/qed/qed.h #define PQ_FLAGS_ACK (BIT(4)) BIT 936 drivers/net/ethernet/qlogic/qed/qed.h #define PQ_FLAGS_OFLD (BIT(5)) BIT 937 drivers/net/ethernet/qlogic/qed/qed.h #define PQ_FLAGS_VFS (BIT(6)) BIT 938 drivers/net/ethernet/qlogic/qed/qed.h #define PQ_FLAGS_LLT (BIT(7)) BIT 939 drivers/net/ethernet/qlogic/qed/qed.h #define PQ_FLAGS_MTC (BIT(8)) BIT 64 drivers/net/ethernet/qlogic/qed/qed_cxt.c #define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT) BIT 71 drivers/net/ethernet/qlogic/qed/qed_cxt.c #define TM_ALIGN BIT(TM_SHIFT) BIT 113 drivers/net/ethernet/qlogic/qed/qed_cxt.c #define CDUT_SEG_ALIGNMET_IN_BYTES BIT(CDUT_SEG_ALIGNMET + 12) BIT 1836 drivers/net/ethernet/qlogic/qed/qed_cxt.c active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0); BIT 1070 drivers/net/ethernet/qlogic/qed/qed_dcbx.c pfc_map |= BIT(i); BIT 2027 drivers/net/ethernet/qlogic/qed/qed_dcbx.c pfc->pfc_en |= BIT(i); BIT 2095 drivers/net/ethernet/qlogic/qed/qed_dcbx.c pfc->pfc_en |= BIT(i); BIT 2134 drivers/net/ethernet/qlogic/qed/qed_dcbx.c dcbx_set.config.params.pfc.prio[i] = !!(pfc->pfc_en & BIT(i)); BIT 2389 drivers/net/ethernet/qlogic/qed/qed_dcbx.c dcbx_set.config.params.app_entry[i].prio = BIT(app->priority); BIT 66 drivers/net/ethernet/qlogic/qed/qed_dcbx.h #define QED_DCBX_OVERRIDE_STATE BIT(0) BIT 67 drivers/net/ethernet/qlogic/qed/qed_dcbx.h #define QED_DCBX_OVERRIDE_PFC_CFG BIT(1) BIT 68 drivers/net/ethernet/qlogic/qed/qed_dcbx.h #define QED_DCBX_OVERRIDE_ETS_CFG BIT(2) BIT 69 drivers/net/ethernet/qlogic/qed/qed_dcbx.h #define QED_DCBX_OVERRIDE_APP_CFG BIT(3) BIT 70 drivers/net/ethernet/qlogic/qed/qed_dcbx.h #define QED_DCBX_OVERRIDE_DSCP_CFG BIT(4) BIT 2173 drivers/net/ethernet/qlogic/qed/qed_debug.c !(reg_val[block->reset_reg] & BIT(block->reset_bit_offset)); BIT 2194 drivers/net/ethernet/qlogic/qed/qed_debug.c old_reset_reg_val & ~BIT(dbg_block->reset_bit_offset); BIT 2361 drivers/net/ethernet/qlogic/qed/qed_debug.c BIT(block->reset_bit_offset); BIT 2572 drivers/net/ethernet/qlogic/qed/qed_debug.c fid = BIT(PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT) | BIT 3700 drivers/net/ethernet/qlogic/qed/qed_debug.c BIT(big_ram->is_256b_bit_offset[dev_data->chip_id]) ? 256 BIT 3957 drivers/net/ethernet/qlogic/qed/qed_debug.c BIT(dbg_client_id)); BIT 7679 drivers/net/ethernet/qlogic/qed/qed_debug.c if (!(reg_result->sts_val & BIT(bit_idx))) { BIT 7691 drivers/net/ethernet/qlogic/qed/qed_debug.c masked_str = reg_result->mask_val & BIT(bit_idx) ? BIT 2852 drivers/net/ethernet/qlogic/qed/qed_dev.c if (hw_mode & BIT(MODE_MF_SD)) { BIT 2865 drivers/net/ethernet/qlogic/qed/qed_dev.c if (hw_mode & BIT(MODE_MF_SI)) { BIT 2920 drivers/net/ethernet/qlogic/qed/qed_dev.c qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2)); BIT 2994 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(p_hwfn->abs_pf_id)); BIT 4121 drivers/net/ethernet/qlogic/qed/qed_dev.c cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS); BIT 4124 drivers/net/ethernet/qlogic/qed/qed_dev.c cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | BIT 4125 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_LLH_PROTO_CLSS) | BIT 4126 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_UFP_SPECIFIC) | BIT 4127 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_8021Q_TAGGING) | BIT 4128 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_DONT_ADD_VLAN0_TAG); BIT 4131 drivers/net/ethernet/qlogic/qed/qed_dev.c cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | BIT 4132 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_LLH_PROTO_CLSS) | BIT 4133 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_8021AD_TAGGING) | BIT 4134 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_DONT_ADD_VLAN0_TAG); BIT 4137 drivers/net/ethernet/qlogic/qed/qed_dev.c cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | BIT 4138 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_LLH_PROTO_CLSS) | BIT 4139 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_LL2_NON_UNICAST) | BIT 4140 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_INTER_PF_SWITCH); BIT 4143 drivers/net/ethernet/qlogic/qed/qed_dev.c cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | BIT 4144 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_LLH_PROTO_CLSS) | BIT 4145 drivers/net/ethernet/qlogic/qed/qed_dev.c BIT(QED_MF_LL2_NON_UNICAST); BIT 4147 drivers/net/ethernet/qlogic/qed/qed_dev.c cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF); BIT 385 drivers/net/ethernet/qlogic/qed/qed_fcoe.c active_segs &= ~BIT(QED_CXT_FCOE_TID_SEG); BIT 2666 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1) BIT 11804 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define EEE_CFG_EEE_ENABLED BIT(0) BIT 11805 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define EEE_CFG_TX_LPI BIT(1) BIT 11806 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define EEE_CFG_ADV_SPEED_1G BIT(2) BIT 11807 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define EEE_CFG_ADV_SPEED_10G BIT(3) BIT 12281 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define EEE_ACTIVE_BIT BIT(0) BIT 12284 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define EEE_1G_ADV BIT(1) BIT 12285 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define EEE_10G_ADV BIT(2) BIT 12290 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define EEE_1G_SUPPORTED BIT(1) BIT 12291 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define EEE_10G_SUPPORTED BIT(2) BIT 543 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c BIT((pq_id % QM_PF_QUEUE_GROUP_SIZE)); BIT 994 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c pq_mask |= BIT((pq_id % QM_STOP_PQ_MASK_WIDTH)); BIT 1021 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c *__p_var = (*__p_var & ~BIT(__offset)) | \ BIT 1022 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c ((enable) ? BIT(__offset) : 0); \ BIT 1181 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c cfg_mask = BIT(PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET); BIT 459 drivers/net/ethernet/qlogic/qed/qed_init_ops.c return (modes & BIT(tree_val)) ? 1 : 0; BIT 85 drivers/net/ethernet/qlogic/qed/qed_int.c #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) BIT 97 drivers/net/ethernet/qlogic/qed/qed_int.c #define ATTENTION_BB_DIFFERENT BIT(23) BIT 356 drivers/net/ethernet/qlogic/qed/qed_int.c qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2)); BIT 976 drivers/net/ethernet/qlogic/qed/qed_int.c mask = ~BIT(bit_index); BIT 1026 drivers/net/ethernet/qlogic/qed/qed_int.c !!(parities & BIT(bit_idx))) BIT 1957 drivers/net/ethernet/qlogic/qed/qed_int.c if (val & BIT((igu_sb_id % 32))) BIT 76 drivers/net/ethernet/qlogic/qed/qed_iwarp.c #define QED_IWARP_TS_EN BIT(0) BIT 77 drivers/net/ethernet/qlogic/qed/qed_iwarp.c #define QED_IWARP_DA_EN BIT(1) BIT 377 drivers/net/ethernet/qlogic/qed/qed_l2.h #define QED_QCID_LEGACY_VF_RX_PROD (BIT(0)) BIT 378 drivers/net/ethernet/qlogic/qed/qed_l2.h #define QED_QCID_LEGACY_VF_CID (BIT(1)) BIT 2548 drivers/net/ethernet/qlogic/qed/qed_ll2.c flags |= BIT(CORE_TX_BD_DATA_IP_CSUM_SHIFT); BIT 2552 drivers/net/ethernet/qlogic/qed/qed_ll2.c flags |= BIT(CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT); BIT 387 drivers/net/ethernet/qlogic/qed/qed_main.c BIT(DEVLINK_PARAM_CMODE_RUNTIME), BIT 1297 drivers/net/ethernet/qlogic/qed/qed_main.c cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) | BIT 1298 drivers/net/ethernet/qlogic/qed/qed_main.c BIT(QED_MODE_L2GENEVE_TUNN) | BIT 1299 drivers/net/ethernet/qlogic/qed/qed_main.c BIT(QED_MODE_IPGENEVE_TUNN) | BIT 1300 drivers/net/ethernet/qlogic/qed/qed_main.c BIT(QED_MODE_L2GRE_TUNN) | BIT 1301 drivers/net/ethernet/qlogic/qed/qed_main.c BIT(QED_MODE_IPGRE_TUNN)); BIT 2049 drivers/net/ethernet/qlogic/qed/qed_main.c is_crc = !!(**data & BIT(0)); BIT 2128 drivers/net/ethernet/qlogic/qed/qed_main.c *check_resp = !!(**data & BIT(0)); BIT 2166 drivers/net/ethernet/qlogic/qed/qed_main.c *check_resp = !!(**data & BIT(0)); BIT 763 drivers/net/ethernet/qlogic/qed/qed_mcp.c #define CONFIG_QEDE_BITMAP_IDX BIT(0) BIT 764 drivers/net/ethernet/qlogic/qed/qed_mcp.c #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) BIT 765 drivers/net/ethernet/qlogic/qed/qed_mcp.c #define CONFIG_QEDR_BITMAP_IDX BIT(2) BIT 766 drivers/net/ethernet/qlogic/qed/qed_mcp.c #define CONFIG_QEDF_BITMAP_IDX BIT(4) BIT 767 drivers/net/ethernet/qlogic/qed/qed_mcp.c #define CONFIG_QEDI_BITMAP_IDX BIT(5) BIT 768 drivers/net/ethernet/qlogic/qed/qed_mcp.c #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) BIT 96 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_LINK_PARTNER_SPEED_1G_HD BIT(0) BIT 97 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_LINK_PARTNER_SPEED_1G_FD BIT(1) BIT 98 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_LINK_PARTNER_SPEED_10G BIT(2) BIT 99 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_LINK_PARTNER_SPEED_20G BIT(3) BIT 100 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_LINK_PARTNER_SPEED_25G BIT(4) BIT 101 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_LINK_PARTNER_SPEED_40G BIT(5) BIT 102 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_LINK_PARTNER_SPEED_50G BIT(6) BIT 103 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_LINK_PARTNER_SPEED_100G BIT(7) BIT 254 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_NVM_CFG_OPTION_ALL BIT(0) BIT 255 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_NVM_CFG_OPTION_INIT BIT(1) BIT 256 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_NVM_CFG_OPTION_COMMIT BIT(2) BIT 257 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_NVM_CFG_OPTION_FREE BIT(3) BIT 258 drivers/net/ethernet/qlogic/qed/qed_mcp.h #define QED_NVM_CFG_OPTION_ENTITY_SEL BIT(4) BIT 46 drivers/net/ethernet/qlogic/qed/qed_ptp.c #define QED_TIMESTAMP_MASK BIT(16) BIT 554 drivers/net/ethernet/qlogic/qed/qed_rdma.c BIT(31)); BIT 872 drivers/net/ethernet/qlogic/qed/qed_sriov.c val = enable ? (vf->abs_vf_id | BIT(8)) : 0; BIT 1294 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (!(tlvs_mask & BIT(i))) BIT 1300 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (tlvs_accepted & BIT(i)) BIT 1779 drivers/net/ethernet/qlogic/qed/qed_sriov.c if ((events & BIT(VLAN_ADDR_FORCED)) && BIT 1795 drivers/net/ethernet/qlogic/qed/qed_sriov.c if ((events & BIT(MAC_ADDR_FORCED)) || BIT 1817 drivers/net/ethernet/qlogic/qed/qed_sriov.c BIT(VFPF_BULLETIN_MAC_ADDR); BIT 1820 drivers/net/ethernet/qlogic/qed/qed_sriov.c BIT(MAC_ADDR_FORCED); BIT 1823 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (events & BIT(VLAN_ADDR_FORCED)) { BIT 1895 drivers/net/ethernet/qlogic/qed/qed_sriov.c p_vf->configured_features &= ~BIT(VLAN_ADDR_FORCED); BIT 1955 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (!(*p_bitmap & BIT(VFPF_BULLETIN_UNTAGGED_DEFAULT_FORCED))) { BIT 2211 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (p_req->tun_mode_update_mask & BIT(mask)) { BIT 2214 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (p_req->tunn_mode & BIT(mask)) BIT 2796 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (!(p_vf->configured_features & BIT(VLAN_ADDR_FORCED))) { BIT 3010 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (!(*tlvs & BIT(QED_IOV_VP_UPDATE_ACCEPT_PARAM))) BIT 3145 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (p_vf->bulletin.p_virt->valid_bitmap & BIT(VLAN_ADDR_FORCED)) BIT 3179 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (p_vf->bulletin.p_virt->valid_bitmap & BIT(MAC_ADDR_FORCED)) BIT 3325 drivers/net/ethernet/qlogic/qed/qed_sriov.c if ((p_bulletin->valid_bitmap & BIT(VLAN_ADDR_FORCED)) && BIT 3337 drivers/net/ethernet/qlogic/qed/qed_sriov.c if ((p_bulletin->valid_bitmap & BIT(MAC_ADDR_FORCED)) && BIT 3723 drivers/net/ethernet/qlogic/qed/qed_sriov.c ack_vfs[vfid / 32] |= BIT((vfid % 32)); BIT 3780 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (BIT((vfid % 32)) & p_disabled_vfs[vfid / 32]) { BIT 4143 drivers/net/ethernet/qlogic/qed/qed_sriov.c feature = BIT(VFPF_BULLETIN_MAC_ADDR); BIT 4146 drivers/net/ethernet/qlogic/qed/qed_sriov.c ~BIT(MAC_ADDR_FORCED); BIT 4148 drivers/net/ethernet/qlogic/qed/qed_sriov.c feature = BIT(MAC_ADDR_FORCED); BIT 4151 drivers/net/ethernet/qlogic/qed/qed_sriov.c ~BIT(VFPF_BULLETIN_MAC_ADDR); BIT 4179 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (vf_info->bulletin.p_virt->valid_bitmap & BIT(MAC_ADDR_FORCED)) { BIT 4185 drivers/net/ethernet/qlogic/qed/qed_sriov.c feature = BIT(VFPF_BULLETIN_MAC_ADDR); BIT 4318 drivers/net/ethernet/qlogic/qed/qed_sriov.c BIT(VFPF_BULLETIN_MAC_ADDR))) BIT 4333 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (!(p_vf->bulletin.p_virt->valid_bitmap & BIT(MAC_ADDR_FORCED))) BIT 4348 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (!(p_vf->bulletin.p_virt->valid_bitmap & BIT(VLAN_ADDR_FORCED))) BIT 5057 drivers/net/ethernet/qlogic/qed/qed_sriov.c (vf->bulletin.p_virt->valid_bitmap & BIT(MAC_ADDR_FORCED))) { BIT 5079 drivers/net/ethernet/qlogic/qed/qed_sriov.c ~BIT(MAC_ADDR_FORCED); BIT 587 drivers/net/ethernet/qlogic/qed/qed_vf.c p_req->tun_mode_update_mask |= BIT(mask); BIT 590 drivers/net/ethernet/qlogic/qed/qed_vf.c p_req->tunn_mode |= BIT(mask); BIT 633 drivers/net/ethernet/qlogic/qed/qed_vf.c if (feature_mask & BIT(val)) { BIT 121 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_ACQUIRE_CAP_QUEUE_QIDS BIT(2) BIT 127 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_ACQUIRE_CAP_PHYSICAL_BAR BIT(3) BIT 153 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_UPDATE_RSS_CONFIG_FLAG BIT(0) BIT 154 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_UPDATE_RSS_CAPS_FLAG BIT(1) BIT 155 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_UPDATE_RSS_IND_TABLE_FLAG BIT(2) BIT 156 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_UPDATE_RSS_KEY_FLAG BIT(3) BIT 190 drivers/net/ethernet/qlogic/qed/qed_vf.h #define PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED BIT(0) BIT 191 drivers/net/ethernet/qlogic/qed/qed_vf.h #define PFVF_ACQUIRE_CAP_100G BIT(1) /* If set, 100g PF */ BIT 198 drivers/net/ethernet/qlogic/qed/qed_vf.h #define PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE BIT(2) BIT 201 drivers/net/ethernet/qlogic/qed/qed_vf.h #define PFVF_ACQUIRE_CAP_QUEUE_QIDS BIT(3) BIT 331 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_RXQ_UPD_INIT_SGE_DEPRECATE_FLAG BIT(0) BIT 332 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_RXQ_UPD_COMPLETE_CQE_FLAG BIT(1) BIT 333 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG BIT(2) BIT 423 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_TPA_IPV4_EN_FLAG BIT(0) BIT 424 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_TPA_IPV6_EN_FLAG BIT(1) BIT 425 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_TPA_PKT_SPLIT_FLAG BIT(2) BIT 426 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_TPA_HDR_DATA_SPLIT_FLAG BIT(3) BIT 427 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_TPA_GRO_CONSIST_FLAG BIT(4) BIT 430 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_UPDATE_SGE_DEPRECATED_FLAG BIT(0) BIT 431 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_UPDATE_TPA_EN_FLAG BIT(1) BIT 432 drivers/net/ethernet/qlogic/qed/qed_vf.h #define VFPF_UPDATE_TPA_PARAM_FLAG BIT(2) BIT 254 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_RSS_INDIR_INITED BIT(0) BIT 255 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_RSS_KEY_INITED BIT(1) BIT 256 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_RSS_CAPS_INITED BIT(2) BIT 388 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_TSO_SPLIT_BD BIT(0) BIT 456 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_FASTPATH_TX BIT(0) BIT 457 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_FASTPATH_RX BIT(1) BIT 458 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_FASTPATH_XDP BIT(2) BIT 477 drivers/net/ethernet/qlogic/qede/qede.h #define XMIT_L4_CSUM BIT(0) BIT 478 drivers/net/ethernet/qlogic/qede/qede.h #define XMIT_LSO BIT(1) BIT 479 drivers/net/ethernet/qlogic/qede/qede.h #define XMIT_ENC BIT(2) BIT 480 drivers/net/ethernet/qlogic/qede/qede.h #define XMIT_ENC_GSO_L4_CSUM BIT(3) BIT 482 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_CSUM_ERROR BIT(0) BIT 483 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_CSUM_UNNECESSARY BIT(1) BIT 484 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_TUNN_CSUM_UNNECESSARY BIT(2) BIT 574 drivers/net/ethernet/qlogic/qede/qede.h #define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW)) BIT 577 drivers/net/ethernet/qlogic/qede/qede.h #define NUM_RX_BDS_DEF ((u16)BIT(10) - 1) BIT 580 drivers/net/ethernet/qlogic/qede/qede.h #define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW)) BIT 92 drivers/net/ethernet/qlogic/qede/qede_ethtool.c BIT(QEDE_STAT_PF_ONLY)) BIT 96 drivers/net/ethernet/qlogic/qede/qede_ethtool.c BIT(QEDE_STAT_PF_ONLY) | BIT(QEDE_STAT_BB_ONLY)) BIT 100 drivers/net/ethernet/qlogic/qede/qede_ethtool.c BIT(QEDE_STAT_PF_ONLY) | BIT(QEDE_STAT_AH_ONLY)) BIT 415 drivers/net/ethernet/qlogic/qede/qede_ethtool.c flags |= BIT(QEDE_PRI_FLAG_CMT); BIT 418 drivers/net/ethernet/qlogic/qede/qede_ethtool.c flags |= BIT(QEDE_PRI_FLAG_SMART_AN_SUPPORT); BIT 1908 drivers/net/ethernet/qlogic/qede/qede_filter.c ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | BIT 1909 drivers/net/ethernet/qlogic/qede/qede_filter.c BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | BIT 1910 drivers/net/ethernet/qlogic/qede/qede_filter.c BIT(FLOW_DISSECTOR_KEY_BASIC) | BIT 1911 drivers/net/ethernet/qlogic/qede/qede_filter.c BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | BIT 1912 drivers/net/ethernet/qlogic/qede/qede_filter.c BIT(FLOW_DISSECTOR_KEY_PORTS))) { BIT 347 drivers/net/ethernet/qlogic/qede/qede_fp.c BIT(ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT); BIT 375 drivers/net/ethernet/qlogic/qede/qede_ptp.c info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT 376 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | BIT 377 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | BIT 378 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | BIT 379 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | BIT 380 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | BIT 381 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | BIT 382 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | BIT 383 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | BIT 384 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | BIT 385 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | BIT 386 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) | BIT 387 drivers/net/ethernet/qlogic/qede/qede_ptp.c BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); BIT 389 drivers/net/ethernet/qlogic/qede/qede_ptp.c info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); BIT 231 drivers/net/ethernet/qualcomm/emac/emac-ethtool.c #define EMAC_PRIV_ENABLE_SINGLE_PAUSE BIT(0) BIT 76 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define RXQ_EN BIT(31) BIT 77 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define CUT_THRU_EN BIT(30) BIT 78 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define RSS_HASH_EN BIT(29) BIT 202 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define EMAC_WRAPPER_TX_TS_EMPTY BIT(31) BIT 218 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define EMAC_RRD_L4F BIT(14) BIT 219 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define EMAC_RRD_IPF BIT(15) BIT 220 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define EMAC_RRD_CRC BIT(21) BIT 221 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define EMAC_RRD_FAE BIT(22) BIT 222 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define EMAC_RRD_TRN BIT(23) BIT 223 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define EMAC_RRD_RNT BIT(24) BIT 224 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define EMAC_RRD_INC BIT(25) BIT 225 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define EMAC_RRD_FOV BIT(29) BIT 226 drivers/net/ethernet/qualcomm/emac/emac-mac.c #define EMAC_RRD_LEN BIT(30) BIT 264 drivers/net/ethernet/qualcomm/emac/emac-mac.c mta |= BIT(bit); BIT 20 drivers/net/ethernet/qualcomm/emac/emac-phy.c #define MDIO_MODE BIT(30) BIT 21 drivers/net/ethernet/qualcomm/emac/emac-phy.c #define MDIO_PR BIT(29) BIT 22 drivers/net/ethernet/qualcomm/emac/emac-phy.c #define MDIO_AP_EN BIT(28) BIT 23 drivers/net/ethernet/qualcomm/emac/emac-phy.c #define MDIO_BUSY BIT(27) BIT 26 drivers/net/ethernet/qualcomm/emac/emac-phy.c #define MDIO_START BIT(23) BIT 27 drivers/net/ethernet/qualcomm/emac/emac-phy.c #define SUP_PREAMBLE BIT(22) BIT 28 drivers/net/ethernet/qualcomm/emac/emac-phy.c #define MDIO_RD_NWR BIT(21) BIT 63 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define SYSCLK_CM BIT(4) BIT 64 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define SYSCLK_AC_COUPLE BIT(3) BIT 66 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define OCP_EN BIT(5) BIT 67 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define PLL_DIV_FFEN BIT(2) BIT 68 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define PLL_DIV_ORD BIT(1) BIT 70 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define SYSCLK_SEL_CMOS BIT(3) BIT 72 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define FRQ_TUNE_MODE BIT(4) BIT 74 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define PLLLOCK_CMP_EN BIT(0) BIT 76 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define DEC_START1_MUX BIT(7) BIT 79 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define DIV_FRAC_START_MUX BIT(7) BIT 82 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define DIV_FRAC_START3_MUX BIT(4) BIT 85 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define DEC_START2_MUX BIT(1) BIT 86 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define DEC_START2 BIT(0) BIT 88 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define READY BIT(5) BIT 90 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define TX_EMP_POST1_LVL_MUX BIT(5) BIT 93 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define TX_DRV_LVL_MUX BIT(4) BIT 96 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define EMP_EN_MUX BIT(1) BIT 97 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define EMP_EN BIT(0) BIT 99 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define SECONDORDERENABLE BIT(6) BIT 106 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define SERDES_START BIT(0) BIT 108 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define BIAS_EN BIT(6) BIT 109 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define PLL_EN BIT(5) BIT 110 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define SYSCLK_EN BIT(4) BIT 111 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define CLKBUF_L_EN BIT(3) BIT 112 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define PLL_TXCLK_EN BIT(1) BIT 113 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define PLL_RXCLK_EN BIT(0) BIT 115 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define L0_RX_SIGDET_EN BIT(7) BIT 117 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define L0_RX_I_EN BIT(1) BIT 119 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define L0_TX_EN BIT(5) BIT 120 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define L0_CLKBUF_EN BIT(4) BIT 121 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define L0_TRAN_BIAS_EN BIT(1) BIT 123 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define L0_RX_EQUALIZE_ENABLE BIT(6) BIT 124 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define L0_RESET_TSYNC_EN BIT(4) BIT 127 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c #define PWRDN_B BIT(0) BIT 47 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define UCDR_STEP_BY_TWO_MODE0 BIT(7) BIT 49 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define UCDR_ENABLE BIT(6) BIT 52 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define SIGDET_LP_BYP_PS4 BIT(7) BIT 53 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define SIGDET_EN_PS0_TO_PS2 BIT(6) BIT 55 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define TXVAL_VALID_INIT BIT(4) BIT 56 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define KR_PCIGEN3_MODE BIT(0) BIT 58 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define MAIN_EN BIT(0) BIT 60 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define TX_MARGINING_MUX BIT(6) BIT 63 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define TX_PRE_MUX BIT(6) BIT 65 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define TX_POST_MUX BIT(6) BIT 77 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define SIGDET_LP_BYP_PS0_TO_PS2 BIT(5) BIT 78 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define SIGDET_FLT_BYP BIT(0) BIT 84 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define INVERT_PCS_RX_CLK BIT(7) BIT 86 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define DRVR_LOGIC_CLK_EN BIT(4) BIT 96 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define EN_DLL_MODE0 BIT(4) BIT 97 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define EN_IQ_DCC_MODE0 BIT(3) BIT 98 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define EN_IQCAL_MODE0 BIT(2) BIT 100 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define BYPASS_RSM_SAMP_CAL BIT(1) BIT 101 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define BYPASS_RSM_DLL_CAL BIT(0) BIT 103 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define L0_RX_EQUALIZE_ENABLE BIT(6) BIT 105 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c #define PWRDN_B BIT(0) BIT 196 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c if (lnstatus & BIT(1)) BIT 45 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define UCDR_STEP_BY_TWO_MODE0 BIT(7) BIT 47 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define UCDR_ENABLE BIT(6) BIT 50 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define SIGDET_LP_BYP_PS4 BIT(7) BIT 51 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define SIGDET_EN_PS0_TO_PS2 BIT(6) BIT 53 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define TXVAL_VALID_INIT BIT(4) BIT 54 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define KR_PCIGEN3_MODE BIT(0) BIT 56 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define MAIN_EN BIT(0) BIT 58 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define TX_MARGINING_MUX BIT(6) BIT 61 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define TX_PRE_MUX BIT(6) BIT 63 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define TX_POST_MUX BIT(6) BIT 73 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define SIGDET_LP_BYP_PS0_TO_PS2 BIT(5) BIT 74 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define SIGDET_FLT_BYP BIT(0) BIT 80 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define DRVR_LOGIC_CLK_EN BIT(4) BIT 90 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define BYPASS_RSM_SAMP_CAL BIT(1) BIT 91 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define BYPASS_RSM_DLL_CAL BIT(0) BIT 93 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define L0_RX_EQUALIZE_ENABLE BIT(6) BIT 95 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c #define PWRDN_B BIT(0) BIT 183 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c if (lnstatus & BIT(1)) BIT 25 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c #define FORCE_AN_TX_CFG BIT(5) BIT 26 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c #define FORCE_AN_RX_CFG BIT(4) BIT 27 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c #define AN_ENABLE BIT(0) BIT 29 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c #define DUPLEX_MODE BIT(4) BIT 30 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c #define SPDMODE_1000 BIT(1) BIT 31 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c #define SPDMODE_100 BIT(0) BIT 34 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c #define CDR_ALIGN_DET BIT(6) BIT 36 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c #define IRQ_GLOBAL_CLEAR BIT(0) BIT 38 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c #define DECODE_CODE_ERR BIT(7) BIT 39 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c #define DECODE_DISP_ERR BIT(6) BIT 117 drivers/net/ethernet/qualcomm/emac/emac.h #define DIS_INT BIT(31) BIT 118 drivers/net/ethernet/qualcomm/emac/emac.h #define PTP_INT BIT(30) BIT 119 drivers/net/ethernet/qualcomm/emac/emac.h #define RFD4_UR_INT BIT(29) BIT 120 drivers/net/ethernet/qualcomm/emac/emac.h #define TX_PKT_INT3 BIT(26) BIT 121 drivers/net/ethernet/qualcomm/emac/emac.h #define TX_PKT_INT2 BIT(25) BIT 122 drivers/net/ethernet/qualcomm/emac/emac.h #define TX_PKT_INT1 BIT(24) BIT 123 drivers/net/ethernet/qualcomm/emac/emac.h #define RX_PKT_INT3 BIT(19) BIT 124 drivers/net/ethernet/qualcomm/emac/emac.h #define RX_PKT_INT2 BIT(18) BIT 125 drivers/net/ethernet/qualcomm/emac/emac.h #define RX_PKT_INT1 BIT(17) BIT 126 drivers/net/ethernet/qualcomm/emac/emac.h #define RX_PKT_INT0 BIT(16) BIT 127 drivers/net/ethernet/qualcomm/emac/emac.h #define TX_PKT_INT BIT(15) BIT 128 drivers/net/ethernet/qualcomm/emac/emac.h #define TXQ_TO_INT BIT(14) BIT 129 drivers/net/ethernet/qualcomm/emac/emac.h #define GPHY_WAKEUP_INT BIT(13) BIT 130 drivers/net/ethernet/qualcomm/emac/emac.h #define GPHY_LINK_DOWN_INT BIT(12) BIT 131 drivers/net/ethernet/qualcomm/emac/emac.h #define GPHY_LINK_UP_INT BIT(11) BIT 132 drivers/net/ethernet/qualcomm/emac/emac.h #define DMAW_TO_INT BIT(10) BIT 133 drivers/net/ethernet/qualcomm/emac/emac.h #define DMAR_TO_INT BIT(9) BIT 134 drivers/net/ethernet/qualcomm/emac/emac.h #define TXF_UR_INT BIT(8) BIT 135 drivers/net/ethernet/qualcomm/emac/emac.h #define RFD3_UR_INT BIT(7) BIT 136 drivers/net/ethernet/qualcomm/emac/emac.h #define RFD2_UR_INT BIT(6) BIT 137 drivers/net/ethernet/qualcomm/emac/emac.h #define RFD1_UR_INT BIT(5) BIT 138 drivers/net/ethernet/qualcomm/emac/emac.h #define RFD0_UR_INT BIT(4) BIT 139 drivers/net/ethernet/qualcomm/emac/emac.h #define RXF_OF_INT BIT(3) BIT 140 drivers/net/ethernet/qualcomm/emac/emac.h #define SW_MAN_INT BIT(2) BIT 157 drivers/net/ethernet/qualcomm/emac/emac.h #define TX_INDX_FIFO_SYNC_RST BIT(23) BIT 158 drivers/net/ethernet/qualcomm/emac/emac.h #define TX_TS_FIFO_SYNC_RST BIT(22) BIT 159 drivers/net/ethernet/qualcomm/emac/emac.h #define RX_TS_FIFO2_SYNC_RST BIT(21) BIT 160 drivers/net/ethernet/qualcomm/emac/emac.h #define RX_TS_FIFO1_SYNC_RST BIT(20) BIT 161 drivers/net/ethernet/qualcomm/emac/emac.h #define TX_TS_ENABLE BIT(16) BIT 162 drivers/net/ethernet/qualcomm/emac/emac.h #define DIS_1588_CLKS BIT(11) BIT 163 drivers/net/ethernet/qualcomm/emac/emac.h #define FREQ_MODE BIT(9) BIT 164 drivers/net/ethernet/qualcomm/emac/emac.h #define ENABLE_RRD_TIMESTAMP BIT(3) BIT 169 drivers/net/ethernet/qualcomm/emac/emac.h #define SLB_EN BIT(9) BIT 170 drivers/net/ethernet/qualcomm/emac/emac.h #define PLB_EN BIT(8) BIT 171 drivers/net/ethernet/qualcomm/emac/emac.h #define WOL_EN BIT(3) BIT 172 drivers/net/ethernet/qualcomm/emac/emac.h #define PHY_RESET BIT(0) BIT 204 drivers/net/ethernet/qualcomm/emac/emac.h #define EMAC_LINK_SPEED_10_HALF BIT(0) BIT 205 drivers/net/ethernet/qualcomm/emac/emac.h #define EMAC_LINK_SPEED_10_FULL BIT(1) BIT 206 drivers/net/ethernet/qualcomm/emac/emac.h #define EMAC_LINK_SPEED_100_HALF BIT(2) BIT 207 drivers/net/ethernet/qualcomm/emac/emac.h #define EMAC_LINK_SPEED_100_FULL BIT(3) BIT 208 drivers/net/ethernet/qualcomm/emac/emac.h #define EMAC_LINK_SPEED_1GB_FULL BIT(5) BIT 57 drivers/net/ethernet/qualcomm/qca_7k.h #define QCASPI_SLAVE_RESET_BIT BIT(6) BIT 60 drivers/net/ethernet/qualcomm/qca_7k.h #define SPI_INT_WRBUF_BELOW_WM BIT(10) BIT 61 drivers/net/ethernet/qualcomm/qca_7k.h #define SPI_INT_CPU_ON BIT(6) BIT 62 drivers/net/ethernet/qualcomm/qca_7k.h #define SPI_INT_ADDR_ERR BIT(3) BIT 63 drivers/net/ethernet/qualcomm/qca_7k.h #define SPI_INT_WRBUF_ERR BIT(2) BIT 64 drivers/net/ethernet/qualcomm/qca_7k.h #define SPI_INT_RDBUF_ERR BIT(1) BIT 65 drivers/net/ethernet/qualcomm/qca_7k.h #define SPI_INT_PKT_AVLBL BIT(0) BIT 400 drivers/net/ethernet/realtek/r8169_main.c #define RX_VLAN_INNER_8125 BIT(22) BIT 401 drivers/net/ethernet/realtek/r8169_main.c #define RX_VLAN_OUTER_8125 BIT(23) BIT 1341 drivers/net/ethernet/realtek/r8169_main.c rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); BIT 1342 drivers/net/ethernet/realtek/r8169_main.c rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); BIT 1486 drivers/net/ethernet/realtek/r8169_main.c r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); BIT 1488 drivers/net/ethernet/realtek/r8169_main.c r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); BIT 2296 drivers/net/ethernet/realtek/r8169_main.c r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); BIT 2297 drivers/net/ethernet/realtek/r8169_main.c r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); BIT 2306 drivers/net/ethernet/realtek/r8169_main.c phy_set_bits(phydev, 0x15, BIT(8)); BIT 2310 drivers/net/ethernet/realtek/r8169_main.c phy_set_bits(phydev, 0x06, BIT(13)); BIT 2317 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4)); BIT 3236 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0); BIT 3243 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); BIT 3244 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); BIT 3247 drivers/net/ethernet/realtek/r8169_main.c phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13)); BIT 3248 drivers/net/ethernet/realtek/r8169_main.c phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0)); BIT 3260 drivers/net/ethernet/realtek/r8169_main.c if (ret & BIT(8)) BIT 3261 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0); BIT 3263 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15)); BIT 3266 drivers/net/ethernet/realtek/r8169_main.c if (ret & BIT(8)) BIT 3267 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1)); BIT 3269 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0); BIT 3272 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); BIT 3277 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); BIT 3284 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); BIT 3381 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); BIT 3384 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); BIT 3404 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); BIT 3434 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); BIT 3470 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); BIT 3480 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); BIT 3485 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); BIT 3494 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); BIT 3512 drivers/net/ethernet/realtek/r8169_main.c phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); BIT 3698 drivers/net/ethernet/realtek/r8169_main.c phy_set_bits(phydev, 0x14, BIT(8)); BIT 3700 drivers/net/ethernet/realtek/r8169_main.c phy_clear_bits(phydev, 0x14, BIT(8)); BIT 3774 drivers/net/ethernet/realtek/r8169_main.c phy_set_bits(phydev, 0x14, BIT(8)); BIT 4330 drivers/net/ethernet/realtek/r8169_main.c mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); BIT 4656 drivers/net/ethernet/realtek/r8169_main.c rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); BIT 4682 drivers/net/ethernet/realtek/r8169_main.c rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); BIT 4683 drivers/net/ethernet/realtek/r8169_main.c rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); BIT 4753 drivers/net/ethernet/realtek/r8169_main.c rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); BIT 4982 drivers/net/ethernet/realtek/r8169_main.c rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); BIT 5000 drivers/net/ethernet/realtek/r8169_main.c rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); BIT 5248 drivers/net/ethernet/realtek/r8169_main.c return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); BIT 5875 drivers/net/ethernet/realtek/r8169_main.c RTL_W16(tp, TxPoll_8125, BIT(0)); BIT 6939 drivers/net/ethernet/realtek/r8169_main.c r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); BIT 6944 drivers/net/ethernet/realtek/r8169_main.c r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); BIT 6962 drivers/net/ethernet/realtek/r8169_main.c r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); BIT 7124 drivers/net/ethernet/realtek/r8169_main.c rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); BIT 764 drivers/net/ethernet/renesas/ravb_main.c if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { BIT 768 drivers/net/ethernet/renesas/ravb_main.c ravb_write(ndev, ric0 & ~BIT(q), RIC0); BIT 769 drivers/net/ethernet/renesas/ravb_main.c ravb_write(ndev, tic & ~BIT(q), TIC); BIT 771 drivers/net/ethernet/renesas/ravb_main.c ravb_write(ndev, BIT(q), RID0); BIT 772 drivers/net/ethernet/renesas/ravb_main.c ravb_write(ndev, BIT(q), TID); BIT 912 drivers/net/ethernet/renesas/ravb_main.c int mask = BIT(q); BIT 64 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_TEST_DMA_CTRL_CLEAR BIT(0) BIT 65 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_TEST_DMA_CTRL_FILL BIT(1) BIT 66 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_TEST_DMA_CTRL_INVERT BIT(2) BIT 78 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_DMA_DESC_CTRL_RESET BIT(0) BIT 110 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_DMA_DESC_COMP_ERR_GEN BIT(15) BIT 237 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_RX_FLAGS_IPV4 BIT(0) BIT 238 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_RX_FLAGS_IPV6 BIT(1) BIT 239 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_RX_FLAGS_CSUM_CALC BIT(2) BIT 240 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_RX_FLAGS_IPV4_CSUM_GOOD BIT(3) BIT 241 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_RX_FLAGS_IP_FRAG BIT(4) BIT 242 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_RX_FLAGS_TCP BIT(5) BIT 243 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_RX_FLAGS_UDP BIT(6) BIT 244 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD BIT(7) BIT 245 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_RX_FLAGS_FWD_OFFLOAD BIT(8) BIT 461 drivers/net/ethernet/rocker/rocker_hw.h #define ROCKER_CONTROL_RESET BIT(0) BIT 290 drivers/net/ethernet/rocker/rocker_ofdpa.c #define OFDPA_OP_FLAG_REMOVE BIT(0) BIT 291 drivers/net/ethernet/rocker/rocker_ofdpa.c #define OFDPA_OP_FLAG_NOWAIT BIT(1) BIT 292 drivers/net/ethernet/rocker/rocker_ofdpa.c #define OFDPA_OP_FLAG_LEARNED BIT(2) BIT 293 drivers/net/ethernet/rocker/rocker_ofdpa.c #define OFDPA_OP_FLAG_REFRESH BIT(3) BIT 125 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_INT_STATUS BIT(5) BIT 132 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_TXA BIT(19) BIT 133 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_PLSDIS BIT(18) BIT 134 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_PLS BIT(17) BIT 135 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_LPIEN BIT(16) BIT 136 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_TXRSTP BIT(11) BIT 137 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_RXRSTP BIT(10) BIT 138 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_RLPIST BIT(9) BIT 139 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_TLPIST BIT(8) BIT 140 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_RLPIEX BIT(3) BIT 141 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_RLPIEN BIT(2) BIT 142 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_TLPIEX BIT(1) BIT 143 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define LPI_CTRL_STATUS_TLPIEN BIT(0) BIT 146 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h tx_hard_error = BIT(0), BIT 147 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h tx_bump_tc = BIT(1), BIT 148 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h handle_tx = BIT(2), BIT 149 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h rx_hard_error = BIT(3), BIT 150 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h rx_bump_tc = BIT(4), BIT 151 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h handle_rx = BIT(5), BIT 18 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.h #define SXGBE_MTL_RXQ_OP_FEP BIT(4) BIT 19 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.h #define SXGBE_MTL_RXQ_OP_FUP BIT(3) BIT 199 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_CORE_RSS_CTL_UDP4TE BIT(3) BIT 200 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_CORE_RSS_CTL_TCP4TE BIT(2) BIT 201 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_CORE_RSS_CTL_IP2TE BIT(1) BIT 202 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_CORE_RSS_CTL_RSSE BIT(0) BIT 263 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_MTL_SFMODE BIT(1) BIT 278 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_MTL_SFMODE BIT(5) BIT 295 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_SOFT_RESET BIT(0) BIT 297 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_AXI_UNDEF_BURST BIT(0) BIT 298 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_ENHACE_ADDR_MODE BIT(11) BIT 314 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_PBL_X8MODE BIT(16) BIT 315 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_CHA_TXCTL_TSE_ENABLE BIT(12) BIT 356 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_TX_START_DMA BIT(0) BIT 364 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_TX_ENABLE BIT(0) BIT 365 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_TX_DISDIC_ALGO BIT(1) BIT 366 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_TX_JABBER_DISABLE BIT(16) BIT 369 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_ENABLE BIT(0) BIT 370 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_ACS_ENABLE BIT(1) BIT 371 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_WATCHDOG_DISABLE BIT(7) BIT 372 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_JUMBPKT_ENABLE BIT(8) BIT 373 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_CSUMOFFLOAD_ENABLE BIT(9) BIT 374 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_LOOPBACK_ENABLE BIT(10) BIT 375 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_ARPOFFLOAD_ENABLE BIT(31) BIT 378 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_VLAN_SVLAN_ENABLE BIT(18) BIT 379 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_VLAN_DOUBLEVLAN_ENABLE BIT(26) BIT 380 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_VLAN_INNERVLAN_ENABLE BIT(27) BIT 392 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_VLAN_PRTY_CTL BIT(18) BIT 393 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_VLAN_CSVL_CTL BIT(19) BIT 396 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_TX_FLOW_CTL_FCB BIT(0) BIT 397 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_TX_FLOW_CTL_TFB BIT(1) BIT 400 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_FLOW_CTL_ENABLE BIT(0) BIT 401 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_UNICAST_DETECT BIT(1) BIT 402 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_RX_PRTYFLOW_CTL_ENABLE BIT(8) BIT 446 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_ENA_NIE BIT(16) /* Normal Summary */ BIT 447 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_ENA_TIE BIT(0) /* Transmit Interrupt */ BIT 448 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_ENA_TUE BIT(2) /* Transmit Buffer Unavailable */ BIT 449 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_ENA_RIE BIT(6) /* Receive Interrupt */ BIT 456 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_ENA_AIE BIT(15) /* Abnormal Summary */ BIT 457 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_ENA_TSE BIT(1) /* Transmit Stopped */ BIT 458 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_ENA_RUE BIT(7) /* Receive Buffer Unavailable */ BIT 459 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_ENA_RSE BIT(8) /* Receive Stopped */ BIT 460 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_ENA_FBE BIT(12) /* Fatal Bus Error */ BIT 461 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_ENA_CDEE BIT(13) /* Context Descriptor Error */ BIT 471 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_REB2 BIT(21) BIT 472 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_REB1 BIT(20) BIT 473 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_REB0 BIT(19) BIT 474 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_TEB2 BIT(18) BIT 475 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_TEB1 BIT(17) BIT 476 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_TEB0 BIT(16) BIT 477 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_NIS BIT(15) BIT 478 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_AIS BIT(14) BIT 479 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_CTXTERR BIT(13) BIT 480 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_FBE BIT(12) BIT 481 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_RPS BIT(8) BIT 482 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_RBU BIT(7) BIT 483 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_RI BIT(6) BIT 484 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_TBU BIT(2) BIT 485 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_TPS BIT(1) BIT 486 drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h #define SXGBE_DMA_INT_STATUS_TI BIT(0) BIT 2399 drivers/net/ethernet/sfc/ef10.c tso_versions |= BIT(1); BIT 2402 drivers/net/ethernet/sfc/ef10.c tso_versions |= BIT(2); BIT 908 drivers/net/ethernet/sfc/mcdi_port.c #define SFF_DIAG_ADDR_CHANGE BIT(2) BIT 619 drivers/net/ethernet/sgi/meth.c #define TX_CATBUF1 BIT(25) BIT 644 drivers/net/ethernet/sgi/meth.c #define TX_CATBUF2 BIT(26) BIT 117 drivers/net/ethernet/sgi/meth.h #define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */ BIT 118 drivers/net/ethernet/sgi/meth.h #define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */ BIT 119 drivers/net/ethernet/sgi/meth.h #define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */ BIT 121 drivers/net/ethernet/sgi/meth.h #define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */ BIT 122 drivers/net/ethernet/sgi/meth.h #define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */ BIT 132 drivers/net/ethernet/sgi/meth.h #define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */ BIT 155 drivers/net/ethernet/sgi/meth.h #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */ BIT 156 drivers/net/ethernet/sgi/meth.h #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */ BIT 157 drivers/net/ethernet/sgi/meth.h #define METH_DMA_RX_EN BIT(15) /* Enable RX */ BIT 158 drivers/net/ethernet/sgi/meth.h #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */ BIT 167 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_VALID BIT(63) BIT 168 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_RCV_CODE_VIOLATION BIT(16) BIT 169 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_DRBL_NBL BIT(17) BIT 170 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_CRC_ERR BIT(18) BIT 171 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_MCAST_PKT BIT(19) BIT 172 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_BCAST_PKT BIT(20) BIT 173 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_INV_PREAMBLE_CTX BIT(21) BIT 174 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_LONG_EVT_SEEN BIT(22) BIT 175 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_BAD_PACKET BIT(23) BIT 176 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_CARRIER_EVT_SEEN BIT(24) BIT 177 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_MCAST_FILTER_MATCH BIT(25) BIT 178 drivers/net/ethernet/sgi/meth.h #define METH_RX_ST_PHYS_ADDR_MATCH BIT(26) BIT 191 drivers/net/ethernet/sgi/meth.h #define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */ BIT 192 drivers/net/ethernet/sgi/meth.h #define METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */ BIT 194 drivers/net/ethernet/sgi/meth.h #define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */ BIT 195 drivers/net/ethernet/sgi/meth.h #define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */ BIT 197 drivers/net/ethernet/sgi/meth.h #define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */ BIT 198 drivers/net/ethernet/sgi/meth.h #define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */ BIT 199 drivers/net/ethernet/sgi/meth.h #define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */ BIT 200 drivers/net/ethernet/sgi/meth.h #define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */ BIT 219 drivers/net/ethernet/sgi/meth.h #define METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */ BIT 222 drivers/net/ethernet/sgi/meth.h #define METH_TX_ST_DONE BIT(63) /* TX complete */ BIT 223 drivers/net/ethernet/sgi/meth.h #define METH_TX_ST_SUCCESS BIT(23) /* Packet was transmitted successfully */ BIT 224 drivers/net/ethernet/sgi/meth.h #define METH_TX_ST_TOOLONG BIT(24) /* TX abort due to excessive length */ BIT 225 drivers/net/ethernet/sgi/meth.h #define METH_TX_ST_UNDERRUN BIT(25) /* TX abort due to underrun (?) */ BIT 226 drivers/net/ethernet/sgi/meth.h #define METH_TX_ST_EXCCOLL BIT(26) /* TX abort due to excess collisions */ BIT 227 drivers/net/ethernet/sgi/meth.h #define METH_TX_ST_DEFER BIT(27) /* TX abort due to excess deferals */ BIT 228 drivers/net/ethernet/sgi/meth.h #define METH_TX_ST_LATECOLL BIT(28) /* TX abort due to late collision */ BIT 232 drivers/net/ethernet/sgi/meth.h #define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */ BIT 235 drivers/net/ethernet/sgi/meth.h #define MDIO_BUSY BIT(16) BIT 42 drivers/net/ethernet/smsc/smsc9420.h #define BUS_MODE_SWR_ (BIT(0)) BIT 43 drivers/net/ethernet/smsc/smsc9420.h #define BUS_MODE_DMA_BURST_LENGTH_1 (BIT(8)) BIT 44 drivers/net/ethernet/smsc/smsc9420.h #define BUS_MODE_DMA_BURST_LENGTH_2 (BIT(9)) BIT 45 drivers/net/ethernet/smsc/smsc9420.h #define BUS_MODE_DMA_BURST_LENGTH_4 (BIT(10)) BIT 46 drivers/net/ethernet/smsc/smsc9420.h #define BUS_MODE_DMA_BURST_LENGTH_8 (BIT(11)) BIT 47 drivers/net/ethernet/smsc/smsc9420.h #define BUS_MODE_DMA_BURST_LENGTH_16 (BIT(12)) BIT 48 drivers/net/ethernet/smsc/smsc9420.h #define BUS_MODE_DMA_BURST_LENGTH_32 (BIT(13)) BIT 49 drivers/net/ethernet/smsc/smsc9420.h #define BUS_MODE_DBO_ (BIT(20)) BIT 62 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_STS_NIS_ (BIT(16)) BIT 63 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_STS_AIS_ (BIT(15)) BIT 64 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_STS_RWT_ (BIT(9)) BIT 65 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_STS_RXPS_ (BIT(8)) BIT 66 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_STS_RXBU_ (BIT(7)) BIT 67 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_STS_RX_ (BIT(6)) BIT 68 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_STS_TXUNF_ (BIT(5)) BIT 69 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_STS_TXBU_ (BIT(2)) BIT 70 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_STS_TXPS_ (BIT(1)) BIT 71 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_STS_TX_ (BIT(0)) BIT 74 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_CONTROL_TTM_ (BIT(22)) BIT 75 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_CONTROL_SF_ (BIT(21)) BIT 76 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_CONTROL_ST_ (BIT(13)) BIT 77 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_CONTROL_OSF_ (BIT(2)) BIT 78 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_CONTROL_SR_ (BIT(1)) BIT 81 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_INTR_ENA_NIS_ (BIT(16)) BIT 82 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_INTR_ENA_AIS_ (BIT(15)) BIT 83 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_INTR_ENA_RWT_ (BIT(9)) BIT 84 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_INTR_ENA_RXPS_ (BIT(8)) BIT 85 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_INTR_ENA_RXBU_ (BIT(7)) BIT 86 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_INTR_ENA_RX_ (BIT(6)) BIT 87 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_INTR_ENA_TXBU_ (BIT(2)) BIT 88 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_INTR_ENA_TXPS_ (BIT(1)) BIT 89 drivers/net/ethernet/smsc/smsc9420.h #define DMAC_INTR_ENA_TX_ (BIT(0)) BIT 114 drivers/net/ethernet/smsc/smsc9420.h #define TDES1_TER_ (BIT(25)) BIT 24 drivers/net/ethernet/socionext/netsec.c #define NETSEC_IRQ_RX BIT(1) BIT 25 drivers/net/ethernet/socionext/netsec.c #define NETSEC_IRQ_TX BIT(0) BIT 35 drivers/net/ethernet/socionext/netsec.c #define NRM_TX_ST_NTOWNR BIT(17) BIT 36 drivers/net/ethernet/socionext/netsec.c #define NRM_TX_ST_TR_ERR BIT(16) BIT 37 drivers/net/ethernet/socionext/netsec.c #define NRM_TX_ST_TXDONE BIT(15) BIT 38 drivers/net/ethernet/socionext/netsec.c #define NRM_TX_ST_TMREXP BIT(14) BIT 44 drivers/net/ethernet/socionext/netsec.c #define NRM_RX_ST_RC_ERR BIT(16) BIT 45 drivers/net/ethernet/socionext/netsec.c #define NRM_RX_ST_PKTCNT BIT(15) BIT 46 drivers/net/ethernet/socionext/netsec.c #define NRM_RX_ST_TMREXP BIT(14) BIT 144 drivers/net/ethernet/socionext/netsec.c #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20) BIT 145 drivers/net/ethernet/socionext/netsec.c #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4) BIT 147 drivers/net/ethernet/socionext/netsec.c #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20) BIT 148 drivers/net/ethernet/socionext/netsec.c #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19) BIT 158 drivers/net/ethernet/socionext/netsec.c #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28) BIT 159 drivers/net/ethernet/socionext/netsec.c #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27) BIT 160 drivers/net/ethernet/socionext/netsec.c #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3) BIT 161 drivers/net/ethernet/socionext/netsec.c #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2) BIT 162 drivers/net/ethernet/socionext/netsec.c #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1) BIT 163 drivers/net/ethernet/socionext/netsec.c #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0) BIT 165 drivers/net/ethernet/socionext/netsec.c #define NETSEC_CLK_EN_REG_DOM_G BIT(5) BIT 166 drivers/net/ethernet/socionext/netsec.c #define NETSEC_CLK_EN_REG_DOM_C BIT(1) BIT 167 drivers/net/ethernet/socionext/netsec.c #define NETSEC_CLK_EN_REG_DOM_D BIT(0) BIT 169 drivers/net/ethernet/socionext/netsec.c #define NETSEC_COM_INIT_REG_DB BIT(2) BIT 170 drivers/net/ethernet/socionext/netsec.c #define NETSEC_COM_INIT_REG_CLS BIT(1) BIT 175 drivers/net/ethernet/socionext/netsec.c #define NETSEC_SOFT_RST_REG_RUN BIT(31) BIT 178 drivers/net/ethernet/socionext/netsec.c #define MH_CTRL__MODE_TRANS BIT(20) BIT 181 drivers/net/ethernet/socionext/netsec.c #define NETSEC_GMAC_CMD_ST_WRITE BIT(28) BIT 182 drivers/net/ethernet/socionext/netsec.c #define NETSEC_GMAC_CMD_ST_BUSY BIT(31) BIT 188 drivers/net/ethernet/socionext/netsec.c #define NETSEC_GMAC_OMR_REG_ST BIT(13) BIT 189 drivers/net/ethernet/socionext/netsec.c #define NETSEC_GMAC_OMR_REG_SR BIT(1) BIT 191 drivers/net/ethernet/socionext/netsec.c #define NETSEC_GMAC_MCR_REG_IBN BIT(30) BIT 192 drivers/net/ethernet/socionext/netsec.c #define NETSEC_GMAC_MCR_REG_CST BIT(25) BIT 193 drivers/net/ethernet/socionext/netsec.c #define NETSEC_GMAC_MCR_REG_JE BIT(20) BIT 194 drivers/net/ethernet/socionext/netsec.c #define NETSEC_MCR_PS BIT(15) BIT 195 drivers/net/ethernet/socionext/netsec.c #define NETSEC_GMAC_MCR_REG_FES BIT(14) BIT 199 drivers/net/ethernet/socionext/netsec.c #define NETSEC_FCR_RFE BIT(2) BIT 200 drivers/net/ethernet/socionext/netsec.c #define NETSEC_FCR_TFE BIT(1) BIT 202 drivers/net/ethernet/socionext/netsec.c #define NETSEC_GMAC_GAR_REG_GW BIT(1) BIT 203 drivers/net/ethernet/socionext/netsec.c #define NETSEC_GMAC_GAR_REG_GB BIT(0) BIT 221 drivers/net/ethernet/socionext/netsec.c #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31) BIT 222 drivers/net/ethernet/socionext/netsec.c #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30) BIT 252 drivers/net/ethernet/socionext/netsec.c #define NETSEC_XDP_CONSUMED BIT(0) BIT 253 drivers/net/ethernet/socionext/netsec.c #define NETSEC_XDP_TX BIT(1) BIT 254 drivers/net/ethernet/socionext/netsec.c #define NETSEC_XDP_REDIR BIT(2) BIT 85 drivers/net/ethernet/socionext/sni_ave.c #define AVE_RSTCTRL_RMIIRST BIT(16) BIT 87 drivers/net/ethernet/socionext/sni_ave.c #define AVE_LINKSEL_100M BIT(0) BIT 90 drivers/net/ethernet/socionext/sni_ave.c #define AVE_GRR_RXFFR BIT(5) /* Reset RxFIFO */ BIT 91 drivers/net/ethernet/socionext/sni_ave.c #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */ BIT 92 drivers/net/ethernet/socionext/sni_ave.c #define AVE_GRR_GRST BIT(0) /* Reset all MAC */ BIT 95 drivers/net/ethernet/socionext/sni_ave.c #define AVE_CFGR_FLE BIT(31) /* Filter Function */ BIT 96 drivers/net/ethernet/socionext/sni_ave.c #define AVE_CFGR_CHE BIT(30) /* Checksum Function */ BIT 97 drivers/net/ethernet/socionext/sni_ave.c #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */ BIT 98 drivers/net/ethernet/socionext/sni_ave.c #define AVE_CFGR_IPFCEN BIT(24) /* IP fragment sum Enable */ BIT 101 drivers/net/ethernet/socionext/sni_ave.c #define AVE_GI_PHY BIT(24) /* PHY interrupt */ BIT 102 drivers/net/ethernet/socionext/sni_ave.c #define AVE_GI_TX BIT(16) /* Tx complete */ BIT 103 drivers/net/ethernet/socionext/sni_ave.c #define AVE_GI_RXERR BIT(8) /* Receive frame more than max size */ BIT 104 drivers/net/ethernet/socionext/sni_ave.c #define AVE_GI_RXOVF BIT(7) /* Overflow at the RxFIFO */ BIT 105 drivers/net/ethernet/socionext/sni_ave.c #define AVE_GI_RXDROP BIT(6) /* Drop packet */ BIT 106 drivers/net/ethernet/socionext/sni_ave.c #define AVE_GI_RXIINT BIT(5) /* Interval interrupt */ BIT 109 drivers/net/ethernet/socionext/sni_ave.c #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */ BIT 110 drivers/net/ethernet/socionext/sni_ave.c #define AVE_TXCR_TXSPD_1G BIT(17) BIT 111 drivers/net/ethernet/socionext/sni_ave.c #define AVE_TXCR_TXSPD_100 BIT(16) BIT 114 drivers/net/ethernet/socionext/sni_ave.c #define AVE_RXCR_RXEN BIT(30) /* Rx enable */ BIT 115 drivers/net/ethernet/socionext/sni_ave.c #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */ BIT 116 drivers/net/ethernet/socionext/sni_ave.c #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */ BIT 117 drivers/net/ethernet/socionext/sni_ave.c #define AVE_RXCR_AFEN BIT(19) /* MAC address filter */ BIT 118 drivers/net/ethernet/socionext/sni_ave.c #define AVE_RXCR_DRPEN BIT(18) /* Drop pause frame */ BIT 122 drivers/net/ethernet/socionext/sni_ave.c #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */ BIT 123 drivers/net/ethernet/socionext/sni_ave.c #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */ BIT 126 drivers/net/ethernet/socionext/sni_ave.c #define AVE_MDIOSR_STS BIT(0) /* access status */ BIT 130 drivers/net/ethernet/socionext/sni_ave.c #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */ BIT 131 drivers/net/ethernet/socionext/sni_ave.c #define AVE_DESCC_RDSTP BIT(4) /* Pause Rx descriptor */ BIT 132 drivers/net/ethernet/socionext/sni_ave.c #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */ BIT 145 drivers/net/ethernet/socionext/sni_ave.c #define AVE_IIRQC_EN0 BIT(27) /* Enable interval interrupt Ring0 */ BIT 149 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_OWN BIT(31) /* Descriptor ownership */ BIT 150 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_INTR BIT(29) /* Request for interrupt */ BIT 151 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_OK BIT(27) /* Normal transmit */ BIT 153 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_NOCSUM BIT(28) /* No use HW checksum */ BIT 154 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_1ST BIT(26) /* Head of buffer chain */ BIT 155 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */ BIT 156 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_OWC BIT(21) /* Out of window,Late Collision */ BIT 157 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_EC BIT(20) /* Excess collision occurred */ BIT 160 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_CSSV BIT(21) /* Checksum check performed */ BIT 161 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_CSER BIT(20) /* Checksum error detected */ BIT 205 drivers/net/ethernet/socionext/sni_ave.c #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ BIT 206 drivers/net/ethernet/socionext/sni_ave.c #define SG_ETPINMODE_RMII(ins) BIT(ins) BIT 990 drivers/net/ethernet/socionext/sni_ave.c writel(val | BIT(entry), priv->base + AVE_PFEN); BIT 1004 drivers/net/ethernet/socionext/sni_ave.c writel(val & ~BIT(entry), priv->base + AVE_PFEN); BIT 21 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII BIT(1) BIT 22 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII BIT(2) BIT 26 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_CONTROL_AN_EN_MASK BIT(12) BIT 28 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_CONTROL_RESTART_AN_MASK BIT(9) BIT 34 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_STATUS_AN_COMPLETED_MASK BIT(5) BIT 37 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_SGMII_SPEED_1000 BIT(3) BIT 38 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_SGMII_SPEED_100 BIT(2) BIT 46 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_PARTNER_SPEED_1000 BIT(11) BIT 47 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_PARTNER_SPEED_100 BIT(10) BIT 49 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_PARTNER_SPEED_1000 BIT(11) BIT 50 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_PARTNER_SPEED_100 BIT(10) BIT 56 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_USE_SGMII_AN_MASK BIT(1) BIT 57 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_USE_SGMII_ENA BIT(0) BIT 244 drivers/net/ethernet/stmicro/stmmac/common.h #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ BIT 245 drivers/net/ethernet/stmicro/stmmac/common.h #define PCS_LINK_IRQ BIT(1) /* PCS Link */ BIT 246 drivers/net/ethernet/stmicro/stmmac/common.h #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ BIT 298 drivers/net/ethernet/stmicro/stmmac/common.h #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) BIT 18 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_PAYLOAD_CSUM_ERR BIT(0) BIT 19 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_CRC_ERROR BIT(1) BIT 20 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_DRIBBLING BIT(2) BIT 21 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_MII_ERROR BIT(3) BIT 22 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_RECEIVE_WATCHDOG BIT(4) BIT 23 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_FRAME_TYPE BIT(5) BIT 24 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_COLLISION BIT(6) BIT 25 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_IPC_CSUM_ERROR BIT(7) BIT 26 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_LAST_DESCRIPTOR BIT(8) BIT 27 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_FIRST_DESCRIPTOR BIT(9) BIT 28 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_VLAN_TAG BIT(10) BIT 29 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_OVERFLOW_ERROR BIT(11) BIT 30 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_LENGTH_ERROR BIT(12) BIT 31 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_SA_FILTER_FAIL BIT(13) BIT 32 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_DESCRIPTOR_ERROR BIT(14) BIT 33 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_ERROR_SUMMARY BIT(15) BIT 36 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_DA_FILTER_FAIL BIT(30) BIT 37 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES0_OWN BIT(31) BIT 42 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES1_SECOND_ADDRESS_CHAINED BIT(24) BIT 43 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES1_END_RING BIT(25) BIT 44 drivers/net/ethernet/stmicro/stmmac/descs.h #define RDES1_DISABLE_IC BIT(31) BIT 49 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES0_RX_MAC_ADDR BIT(0) BIT 53 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES1_SECOND_ADDRESS_CHAINED BIT(14) BIT 54 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES1_END_RING BIT(15) BIT 57 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES1_DISABLE_IC BIT(31) BIT 61 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_DEFERRED BIT(0) BIT 62 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_UNDERFLOW_ERROR BIT(1) BIT 63 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_EXCESSIVE_DEFERRAL BIT(2) BIT 65 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_VLAN_FRAME BIT(7) BIT 66 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_EXCESSIVE_COLLISIONS BIT(8) BIT 67 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_LATE_COLLISION BIT(9) BIT 68 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_NO_CARRIER BIT(10) BIT 69 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_LOSS_CARRIER BIT(11) BIT 70 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_PAYLOAD_ERROR BIT(12) BIT 71 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_FRAME_FLUSHED BIT(13) BIT 72 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_JABBER_TIMEOUT BIT(14) BIT 73 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_ERROR_SUMMARY BIT(15) BIT 74 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_IP_HEADER_ERROR BIT(16) BIT 75 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_TIME_STAMP_STATUS BIT(17) BIT 76 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES0_OWN ((u32)BIT(31)) /* silence sparse */ BIT 81 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES1_TIME_STAMP_ENABLE BIT(22) BIT 82 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES1_DISABLE_PADDING BIT(23) BIT 83 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES1_SECOND_ADDRESS_CHAINED BIT(24) BIT 84 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES1_END_RING BIT(25) BIT 85 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES1_CRC_DISABLE BIT(26) BIT 88 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES1_FIRST_SEGMENT BIT(29) BIT 89 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES1_LAST_SEGMENT BIT(30) BIT 90 drivers/net/ethernet/stmicro/stmmac/descs.h #define TDES1_INTERRUPT BIT(31) BIT 94 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_DEFERRED BIT(0) BIT 95 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_UNDERFLOW_ERROR BIT(1) BIT 96 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_EXCESSIVE_DEFERRAL BIT(2) BIT 98 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_VLAN_FRAME BIT(7) BIT 99 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_EXCESSIVE_COLLISIONS BIT(8) BIT 100 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_LATE_COLLISION BIT(9) BIT 101 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_NO_CARRIER BIT(10) BIT 102 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_LOSS_CARRIER BIT(11) BIT 103 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_PAYLOAD_ERROR BIT(12) BIT 104 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_FRAME_FLUSHED BIT(13) BIT 105 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_JABBER_TIMEOUT BIT(14) BIT 106 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_ERROR_SUMMARY BIT(15) BIT 107 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_IP_HEADER_ERROR BIT(16) BIT 108 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_TIME_STAMP_STATUS BIT(17) BIT 109 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_SECOND_ADDRESS_CHAINED BIT(20) BIT 110 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_END_RING BIT(21) BIT 113 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_TIME_STAMP_ENABLE BIT(25) BIT 114 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_DISABLE_PADDING BIT(26) BIT 115 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_CRC_DISABLE BIT(27) BIT 116 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_FIRST_SEGMENT BIT(28) BIT 117 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_LAST_SEGMENT BIT(29) BIT 118 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_INTERRUPT BIT(30) BIT 119 drivers/net/ethernet/stmicro/stmmac/descs.h #define ETDES0_OWN ((u32)BIT(31)) /* silence sparse */ BIT 127 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_IP_HDR_ERR BIT(3) BIT 128 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_IP_PAYLOAD_ERR BIT(4) BIT 129 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_IP_CSUM_BYPASSED BIT(5) BIT 130 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_IPV4_PKT_RCVD BIT(6) BIT 131 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_IPV6_PKT_RCVD BIT(7) BIT 133 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_PTP_FRAME_TYPE BIT(12) BIT 134 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_PTP_VER BIT(13) BIT 135 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_TIMESTAMP_DROPPED BIT(14) BIT 136 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_AV_PKT_RCVD BIT(16) BIT 137 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_AV_TAGGED_PKT_RCVD BIT(17) BIT 139 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_L3_FILTER_MATCH BIT(24) BIT 140 drivers/net/ethernet/stmicro/stmmac/descs.h #define ERDES4_L4_FILTER_MATCH BIT(25) BIT 173 drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c #define SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31) BIT 176 drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c #define AUTO_CAL_CONFIG_START BIT(31) BIT 177 drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c #define AUTO_CAL_CONFIG_ENABLE BIT(29) BIT 180 drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c #define AUTO_CAL_STATUS_ACTIVE BIT(31) BIT 34 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x) BIT 35 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2)) BIT 36 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2)) BIT 37 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x) BIT 38 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x) BIT 55 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define NSS_COMMON_GMAC_CTL_CSYS_REQ BIT(19) BIT 56 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL BIT(16) BIT 68 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19) BIT 73 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define QSGMII_PHY_CDR_EN BIT(0) BIT 74 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define QSGMII_PHY_RX_FRONT_EN BIT(1) BIT 75 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2) BIT 76 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define QSGMII_PHY_TX_DRIVER_EN BIT(3) BIT 77 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c #define QSGMII_PHY_QSGMII_EN BIT(7) BIT 24 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define RMII_CLK_SRC_RXC BIT(4) BIT 25 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define RMII_CLK_SRC_INTERNAL BIT(5) BIT 28 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_DLY_GTXC_INV BIT(6) BIT 29 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_DLY_GTXC_ENABLE BIT(5) BIT 31 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_DLY_TXC_INV BIT(20) BIT 32 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_DLY_TXC_ENABLE BIT(19) BIT 34 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_DLY_RXC_INV BIT(13) BIT 35 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_DLY_RXC_ENABLE BIT(12) BIT 39 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_RMII_DLY_TX_INV BIT(2) BIT 40 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_FINE_DLY_GTXC BIT(1) BIT 41 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_FINE_DLY_RXC BIT(0) BIT 18 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c #define ETHMAC_SPEED_100 BIT(1) BIT 25 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c #define PRG_ETH0_RGMII_MODE BIT(0) BIT 44 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c #define PRG_ETH0_INVERTED_RMII_CLK BIT(11) BIT 45 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) BIT 79 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c value |= BIT(DWMAC_CKEN_GTX) | BIT 81 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c BIT(DWMAC_SIMPLE_MUX) | BIT 83 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c BIT(DWMAC_AUTO_TX_SOURCE) | BIT 85 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c BIT(DWMAC_CKEN_TX_OUT) | BIT 86 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c BIT(DWMAC_CKEN_TXN_OUT) | BIT 87 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c BIT(DWMAC_CKEN_TX_IN) | BIT 88 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c BIT(DWMAC_CKEN_RX_OUT) | BIT 89 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c BIT(DWMAC_CKEN_RXN_OUT) | BIT 90 drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c BIT(DWMAC_CKEN_RX_IN); BIT 23 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) BIT 24 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) BIT 30 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) BIT 31 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_LOOPBACK_EN BIT(2) BIT 32 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_PROG_SWAP BIT(1) BIT 33 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_DDR_MODE BIT(0) BIT 36 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG_DLL_RST BIT(30) BIT 37 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG_PDN BIT(29) BIT 40 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) BIT 41 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) BIT 42 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG_CDR_EN BIT(17) BIT 43 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG_DLL_EN BIT(16) BIT 44 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_MCLK_GATING_EN BIT(5) BIT 48 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) BIT 51 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) BIT 55 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) BIT 58 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) BIT 59 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) BIT 62 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDC4_STATUS_DLL_LOCK BIT(7) BIT 66 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) BIT 67 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) BIT 68 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) BIT 69 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) BIT 70 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) BIT 71 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) BIT 251 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c BIT(2), SDCC_HC_REG_DLL_CONFIG2); BIT 318 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c BIT(6), RGMII_IO_MACRO_CONFIG); BIT 325 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); BIT 351 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c BIT(12) | GENMASK(9, 8), BIT 359 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); BIT 418 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL); BIT 71 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) BIT 72 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define GRF_CLR_BIT(nr) (BIT(nr+16)) BIT 74 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8) BIT 75 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) BIT 76 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6) BIT 96 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) BIT 97 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK BIT(6) BIT 100 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define ENMII BIT(5) BIT 102 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define EN BIT(1) BIT 112 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define ETH_PHY_SEL_RMII BIT(4) BIT 113 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define ETH_PHY_SEL_SGMII BIT(3) BIT 114 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define ETH_PHY_SEL_RGMII BIT(2) BIT 25 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c #define SYSCFG_MCU_ETH_MASK BIT(23) BIT 29 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c #define SYSCFG_PMCR_ETH_CLK_SEL BIT(16) BIT 30 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c #define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17) BIT 45 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c #define SYSCFG_PMCR_ETH_SEL_MII BIT(20) BIT 46 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c #define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21) BIT 47 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c #define SYSCFG_PMCR_ETH_SEL_RMII BIT(23) BIT 179 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_DUPLEX_FULL BIT(0) BIT 180 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_LOOPBACK BIT(1) BIT 189 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_FRM_FLT_RXALL BIT(0) BIT 190 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_FRM_FLT_CTL BIT(13) BIT 191 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_FRM_FLT_MULTICAST BIT(16) BIT 194 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_MD BIT(1) BIT 200 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_DMA_EN BIT(30) BIT 201 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_DMA_START BIT(31) BIT 204 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_MD BIT(1) BIT 205 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_NEXT_FRM BIT(2) BIT 211 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_DMA_EN BIT(30) BIT 212 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_DMA_START BIT(31) BIT 215 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_RECEIVER_EN BIT(31) BIT 216 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_DO_CRC BIT(27) BIT 217 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_FLOW_CTL_EN BIT(16) BIT 220 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_TRANSMITTER_EN BIT(31) BIT 223 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_FLOW_CTL_EN BIT(0) BIT 226 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_INT BIT(0) BIT 227 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_DMA_STOP_INT BIT(1) BIT 228 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_BUF_UA_INT BIT(2) BIT 229 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_TIMEOUT_INT BIT(3) BIT 230 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_UNDERFLOW_INT BIT(4) BIT 231 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_EARLY_INT BIT(5) BIT 232 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_INT BIT(8) BIT 233 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_BUF_UA_INT BIT(9) BIT 234 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_DMA_STOP_INT BIT(10) BIT 235 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_TIMEOUT_INT BIT(11) BIT 236 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_OVERFLOW_INT BIT(12) BIT 237 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_EARLY_INT BIT(13) BIT 238 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RGMII_STA_INT BIT(16) BIT 240 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define MAC_ADDR_TYPE_DST BIT(31) BIT 244 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ BIT 245 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ BIT 246 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ BIT 247 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ BIT 253 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ BIT 259 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ BIT 26 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_STATUS_PMT BIT(3) BIT 27 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_STATUS_MMCIS BIT(4) BIT 28 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_STATUS_MMCRIS BIT(5) BIT 29 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_STATUS_MMCTIS BIT(6) BIT 30 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_STATUS_MMCCSUM BIT(7) BIT 31 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_STATUS_TSTAMP BIT(9) BIT 32 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_STATUS_LPIIS BIT(10) BIT 36 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_DISABLE_RGMII BIT(0) BIT 37 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_DISABLE_PCSLINK BIT(1) BIT 38 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_DISABLE_PCSAN BIT(2) BIT 39 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_DISABLE_PMT BIT(3) BIT 40 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_INT_DISABLE_TIMESTAMP BIT(9) BIT 89 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_RGSMIIIS_LNKMODE BIT(0) BIT 92 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_RGSMIIIS_LNKSTS BIT(3) BIT 93 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_RGSMIIIS_JABTO BIT(4) BIT 94 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_RGSMIIIS_FALSECARDET BIT(5) BIT 95 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_RGSMIIIS_SMIDRXS BIT(16) BIT 157 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_TXSTSFSTS BIT(25) /* MTL TxStatus FIFO Full Status */ BIT 158 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */ BIT 159 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */ BIT 167 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */ BIT 176 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_TPESTS BIT(16) BIT 189 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */ BIT 194 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_RPESTS BIT(0) BIT 58 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RXQCTRL_MCBCQEN BIT(20) BIT 60 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RXQCTRL_TACPQE BIT(21) BIT 64 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PACKET_FILTER_PR BIT(0) BIT 65 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PACKET_FILTER_HMC BIT(2) BIT 66 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PACKET_FILTER_PM BIT(4) BIT 67 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PACKET_FILTER_PCF BIT(7) BIT 68 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PACKET_FILTER_HPF BIT(10) BIT 69 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PACKET_FILTER_VTFE BIT(16) BIT 74 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_VLAN_EDVLP BIT(26) BIT 75 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_VLAN_VTHM BIT(25) BIT 76 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_VLAN_DOVLTC BIT(20) BIT 77 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_VLAN_ESVL BIT(18) BIT 78 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_VLAN_ETV BIT(16) BIT 80 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_VLAN_VLTI BIT(20) BIT 81 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_VLAN_CSVL BIT(19) BIT 87 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2) BIT 88 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1) BIT 91 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RX_FLOW_CTRL_RFE BIT(0) BIT 102 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_TX_FLOW_CTRL_TFE BIT(1) BIT 106 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_INT_RGSMIIS BIT(0) BIT 107 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_INT_PCS_LINK BIT(1) BIT 108 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_INT_PCS_ANE BIT(2) BIT 109 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_INT_PCS_PHYIS BIT(3) BIT 110 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_INT_PMT_EN BIT(4) BIT 111 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_INT_LPI_EN BIT(5) BIT 147 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */ BIT 148 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */ BIT 149 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */ BIT 150 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */ BIT 151 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */ BIT 152 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */ BIT 153 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */ BIT 154 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */ BIT 163 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_DEBUG_TPESTS BIT(16) BIT 166 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_DEBUG_RPESTS BIT(0) BIT 169 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_ARPEN BIT(31) BIT 172 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_IPC BIT(27) BIT 173 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_2K BIT(22) BIT 174 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_ACS BIT(20) BIT 175 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_BE BIT(18) BIT 176 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_JD BIT(17) BIT 177 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_JE BIT(16) BIT 178 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_PS BIT(15) BIT 179 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_FES BIT(14) BIT 180 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_DM BIT(13) BIT 181 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_LM BIT(12) BIT 182 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_DCRS BIT(9) BIT 183 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_TE BIT(1) BIT 184 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_RE BIT(0) BIT 187 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_SAVLANINS BIT(27) BIT 188 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_ADDMAC BIT(18) BIT 189 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_RXCOESEL BIT(16) BIT 190 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_TXCOSEL BIT(14) BIT 191 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_EEESEL BIT(13) BIT 192 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_TSSEL BIT(12) BIT 193 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_ARPOFFSEL BIT(9) BIT 194 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_MMCSEL BIT(8) BIT 195 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_MGKSEL BIT(7) BIT 196 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_RWKSEL BIT(6) BIT 197 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_SMASEL BIT(5) BIT 198 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_VLHASH BIT(4) BIT 199 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_PCSSEL BIT(3) BIT 200 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_HDSEL BIT(2) BIT 201 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_GMIISEL BIT(1) BIT 202 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_MIISEL BIT(0) BIT 206 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_AVSEL BIT(20) BIT 207 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_TSOEN BIT(18) BIT 222 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_FRPSEL BIT(10) BIT 223 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_DVLAN BIT(5) BIT 228 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HI_REG_AE BIT(31) BIT 232 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_FRPE BIT(15) BIT 238 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OPERATION_RAA BIT(2) BIT 243 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_INT_QX(x) BIT(x) BIT 263 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OP_MODE_RSF BIT(5) BIT 265 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OP_MODE_TXQEN_AV BIT(2) BIT 266 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OP_MODE_TXQEN BIT(3) BIT 267 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OP_MODE_TSF BIT(1) BIT 293 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OP_MODE_EHFC BIT(7) BIT 309 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_ETS_CTRL_CC BIT(3) BIT 310 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_ETS_CTRL_AVALG BIT(2) BIT 344 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_TXSTSFSTS BIT(5) BIT 345 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_TXFSTS BIT(4) BIT 346 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_TWCSTS BIT(3) BIT 355 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_TXPAUSED BIT(0) BIT 370 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_RWCSTS BIT(0) BIT 373 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_RX_OVERFLOW_INT_EN BIT(24) BIT 374 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_RX_OVERFLOW_INT BIT(16) BIT 385 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_TXSTSFSTS BIT(5) BIT 386 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_TXFSTS BIT(4) BIT 387 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_TWCSTS BIT(3) BIT 396 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_TXPAUSED BIT(0) BIT 411 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_RWCSTS BIT(0) BIT 414 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) BIT 415 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) BIT 416 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) BIT 417 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) BIT 420 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) BIT 421 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) BIT 422 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) BIT 26 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_IVLTV BIT(17) BIT 27 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES2_TIMESTAMP_ENABLE BIT(30) BIT 30 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES2_INTERRUPT_ON_COMPLETION BIT(31) BIT 35 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_VLTV BIT(16) BIT 39 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_TCP_SEGMENTATION_ENABLE BIT(18) BIT 47 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_IP_HDR_ERROR BIT(0) BIT 48 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_DEFERRED BIT(1) BIT 49 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_UNDERFLOW_ERROR BIT(2) BIT 50 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_EXCESSIVE_DEFERRAL BIT(3) BIT 53 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_EXCESSIVE_COLLISION BIT(8) BIT 54 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_LATE_COLLISION BIT(9) BIT 55 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_NO_CARRIER BIT(10) BIT 56 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_LOSS_CARRIER BIT(11) BIT 57 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_PAYLOAD_ERROR BIT(12) BIT 58 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_PACKET_FLUSHED BIT(13) BIT 59 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_JABBER_TIMEOUT BIT(14) BIT 60 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_ERROR_SUMMARY BIT(15) BIT 61 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_TIMESTAMP_STATUS BIT(17) BIT 65 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_CTXT_TCMSSV BIT(26) BIT 68 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_RS1V BIT(26) BIT 70 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_LAST_DESCRIPTOR BIT(28) BIT 72 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_FIRST_DESCRIPTOR BIT(29) BIT 73 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_CONTEXT_TYPE BIT(30) BIT 77 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_OWN BIT(31) BIT 87 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_IP_HDR_ERROR BIT(3) BIT 88 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_IPV4_HEADER BIT(4) BIT 89 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_IPV6_HEADER BIT(5) BIT 90 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_IP_CSUM_BYPASSED BIT(6) BIT 91 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_IP_CSUM_ERROR BIT(7) BIT 93 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_PTP_PACKET_TYPE BIT(12) BIT 94 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_PTP_VER BIT(13) BIT 95 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_TIMESTAMP_AVAILABLE BIT(14) BIT 97 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_TIMESTAMP_DROPPED BIT(15) BIT 102 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES2_VLAN_FILTER_STATUS BIT(15) BIT 103 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES2_SA_FILTER_FAIL BIT(16) BIT 104 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES2_DA_FILTER_FAIL BIT(17) BIT 105 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES2_HASH_FILTER_STATUS BIT(18) BIT 108 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES2_L3_FILTER_MATCH BIT(27) BIT 109 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES2_L4_FILTER_MATCH BIT(28) BIT 115 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_ERROR_SUMMARY BIT(15) BIT 117 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_DRIBBLE_ERROR BIT(19) BIT 118 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_RECEIVE_ERROR BIT(20) BIT 119 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_OVERFLOW_ERROR BIT(21) BIT 120 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_RECEIVE_WATCHDOG BIT(22) BIT 121 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_GIANT_PACKET BIT(23) BIT 122 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_CRC_ERROR BIT(24) BIT 123 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_RDES0_VALID BIT(25) BIT 124 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_RDES1_VALID BIT(26) BIT 125 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_RDES2_VALID BIT(27) BIT 126 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_LAST_DESCRIPTOR BIT(28) BIT 127 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_FIRST_DESCRIPTOR BIT(29) BIT 128 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_CONTEXT_DESCRIPTOR BIT(30) BIT 132 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_BUFFER1_VALID_ADDR BIT(24) BIT 133 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_BUFFER2_VALID_ADDR BIT(25) BIT 134 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_INT_ON_COMPLETION_EN BIT(30) BIT 137 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_OWN BIT(31) BIT 27 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_BUS_MODE_SFT_RESET BIT(0) BIT 30 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_BUS_MODE_SPH BIT(24) BIT 31 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_BUS_MODE_PBL BIT(16) BIT 34 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_BUS_MODE_MB BIT(14) BIT 35 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_BUS_MODE_FB BIT(0) BIT 38 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_STATUS_MAC BIT(17) BIT 39 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_STATUS_MTL BIT(16) BIT 40 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_STATUS_CHAN7 BIT(7) BIT 41 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_STATUS_CHAN6 BIT(6) BIT 42 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_STATUS_CHAN5 BIT(5) BIT 43 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_STATUS_CHAN4 BIT(4) BIT 44 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_STATUS_CHAN3 BIT(3) BIT 45 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_STATUS_CHAN2 BIT(2) BIT 46 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_STATUS_CHAN1 BIT(1) BIT 47 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_STATUS_CHAN0 BIT(0) BIT 54 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_EN_LPI BIT(31) BIT 55 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_LPI_XIT_FRM BIT(30) BIT 65 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_SYS_BUS_MB BIT(14) BIT 66 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_1KBBE BIT(13) BIT 67 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_SYS_BUS_AAL BIT(12) BIT 68 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_BLEN256 BIT(7) BIT 69 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_BLEN128 BIT(6) BIT 70 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_BLEN64 BIT(5) BIT 71 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_BLEN32 BIT(4) BIT 72 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_BLEN16 BIT(3) BIT 73 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_BLEN8 BIT(2) BIT 74 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_BLEN4 BIT(1) BIT 75 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_SYS_BUS_FB BIT(0) BIT 113 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CONTROL_TSE BIT(12) BIT 114 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CONTROL_OSP BIT(4) BIT 115 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CONTROL_ST BIT(0) BIT 118 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CONTROL_SR BIT(0) BIT 127 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_NIS BIT(15) BIT 128 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_AIS BIT(14) BIT 129 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_CDE BIT(13) BIT 130 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_FBE BIT(12) BIT 131 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_ERI BIT(11) BIT 132 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_ETI BIT(10) BIT 133 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_RWT BIT(9) BIT 134 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_RPS BIT(8) BIT 135 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_RBU BIT(7) BIT 136 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_RI BIT(6) BIT 137 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_TBU BIT(2) BIT 138 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_TPS BIT(1) BIT 139 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_TI BIT(0) BIT 142 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_NIE BIT(16) BIT 143 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_AIE BIT(15) BIT 144 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15) BIT 145 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14) BIT 146 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_CDE BIT(13) BIT 147 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_FBE BIT(12) BIT 148 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_ERE BIT(11) BIT 149 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_ETE BIT(10) BIT 150 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_RWE BIT(9) BIT 151 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_RSE BIT(8) BIT 152 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_RBUE BIT(7) BIT 153 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_RIE BIT(6) BIT 154 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_TBUE BIT(2) BIT 155 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_TSE BIT(1) BIT 156 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_INTR_ENA_TIE BIT(0) BIT 11 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define PRTYEN BIT(1) BIT 12 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define TMOUTEN BIT(0) BIT 18 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define MCGRENx(x) BIT(PPS_MAXIDX(x)) BIT 25 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define PPSEN0 BIT(4) BIT 28 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define TRGTBUSY0 BIT(31) BIT 34 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define RXPI BIT(31) BIT 38 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define STARTBUSY BIT(31) BIT 40 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define RXPEIEE BIT(20) BIT 41 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define WRRDN BIT(16) BIT 45 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define TSOEE BIT(4) BIT 46 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define MRXPEE BIT(3) BIT 47 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define MESTEE BIT(2) BIT 48 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define MRXEE BIT(1) BIT 49 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define MTXEE BIT(0) BIT 52 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define MCSIS BIT(31) BIT 53 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define MEUIS BIT(1) BIT 54 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define MECIS BIT(0) BIT 56 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define RPCEIE BIT(12) BIT 57 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define ECEIE BIT(8) BIT 58 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define RXCEIE BIT(4) BIT 59 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define TXCEIE BIT(0) BIT 62 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define EPSI BIT(2) BIT 63 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define OPE BIT(1) BIT 64 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define EDPP BIT(0) BIT 67 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define MSUIS BIT(29) BIT 68 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define MSCIS BIT(28) BIT 69 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define DEUIS BIT(1) BIT 70 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define DECIS BIT(0) BIT 72 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define TCEIE BIT(0) BIT 34 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_EN_LPI BIT(31) BIT 35 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_LPI_XIT_FRM BIT(30) BIT 46 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_1KBBE BIT(13) BIT 47 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_AAL BIT(12) BIT 48 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_BLEN256 BIT(7) BIT 49 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_BLEN128 BIT(6) BIT 50 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_BLEN64 BIT(5) BIT 51 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_BLEN32 BIT(4) BIT 52 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_BLEN16 BIT(3) BIT 53 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_BLEN8 BIT(2) BIT 54 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_BLEN4 BIT(1) BIT 60 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_UNDEF BIT(0) BIT 28 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_JD BIT(16) BIT 29 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_TE BIT(0) BIT 32 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_ARPEN BIT(31) BIT 38 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_S2KP BIT(11) BIT 39 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_LM BIT(10) BIT 40 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_IPC BIT(9) BIT 41 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_JE BIT(8) BIT 42 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_WD BIT(7) BIT 43 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_GPSLCE BIT(6) BIT 44 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_CST BIT(2) BIT 45 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_ACS BIT(1) BIT 46 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_RE BIT(0) BIT 50 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_FILTER_RA BIT(31) BIT 51 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_FILTER_IPFE BIT(20) BIT 52 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_FILTER_VTFE BIT(16) BIT 53 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_FILTER_HPF BIT(10) BIT 54 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_FILTER_PCF BIT(7) BIT 55 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_FILTER_PM BIT(4) BIT 56 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_FILTER_HMC BIT(2) BIT 57 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_FILTER_PR BIT(0) BIT 61 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_VLAN_EDVLP BIT(26) BIT 62 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_VLAN_VTHM BIT(25) BIT 63 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_VLAN_DOVLTC BIT(20) BIT 64 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_VLAN_ESVL BIT(18) BIT 65 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_VLAN_ETV BIT(16) BIT 69 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_VLAN_VLTI BIT(20) BIT 70 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_VLAN_CSVL BIT(19) BIT 81 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_LPIIS BIT(5) BIT 82 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PMTIS BIT(4) BIT 84 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TSIE BIT(12) BIT 85 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_LPIIE BIT(5) BIT 86 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PMTIE BIT(4) BIT 91 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TFE BIT(1) BIT 93 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RFE BIT(0) BIT 95 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_GLBLUCAST BIT(9) BIT 96 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RWKPKTEN BIT(2) BIT 97 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_MGKPKTEN BIT(1) BIT 98 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PWRDWN BIT(0) BIT 100 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TXCGE BIT(21) BIT 101 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_LPITXA BIT(19) BIT 102 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PLS BIT(17) BIT 103 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_LPITXEN BIT(16) BIT 104 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RLPIEX BIT(3) BIT 105 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RLPIEN BIT(2) BIT 106 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TLPIEX BIT(1) BIT 107 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TLPIEN BIT(0) BIT 110 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_SAVLANINS BIT(27) BIT 111 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_RXCOESEL BIT(16) BIT 112 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_TXCOESEL BIT(14) BIT 113 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_EEESEL BIT(13) BIT 114 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_TSSEL BIT(12) BIT 115 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_AVSEL BIT(11) BIT 116 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_RAVSEL BIT(10) BIT 117 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_ARPOFFSEL BIT(9) BIT 118 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_MMCSEL BIT(8) BIT 119 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_MGKSEL BIT(7) BIT 120 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_RWKSEL BIT(6) BIT 121 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_VLHASH BIT(4) BIT 122 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_GMIISEL BIT(1) BIT 126 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_RSSEN BIT(20) BIT 127 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_TSOEN BIT(18) BIT 128 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_SPHEN BIT(17) BIT 140 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_DVLAN BIT(13) BIT 143 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_FRPSEL BIT(3) BIT 146 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PRTYEN BIT(1) BIT 147 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TMOUTEN BIT(0) BIT 153 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_AE BIT(31) BIT 161 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TT BIT(1) BIT 162 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_XB BIT(0) BIT 165 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L4DPIM0 BIT(21) BIT 166 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L4DPM0 BIT(20) BIT 167 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L4SPIM0 BIT(19) BIT 168 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L4SPM0 BIT(18) BIT 169 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L4PEN0 BIT(16) BIT 172 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L3DAIM0 BIT(5) BIT 173 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L3DAM0 BIT(4) BIT 174 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L3SAIM0 BIT(3) BIT 175 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L3SAM0 BIT(2) BIT 176 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L3PEN0 BIT(0) BIT 187 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_UDP4TE BIT(3) BIT 188 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TCP4TE BIT(2) BIT 189 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_IP2TE BIT(1) BIT 190 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RSSE BIT(0) BIT 193 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_ADDRT BIT(2) BIT 194 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CT BIT(1) BIT 195 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_OB BIT(0) BIT 198 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TXTSC BIT(15) BIT 215 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PPSEN0 BIT(4) BIT 218 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TRGTBUSY0 BIT(31) BIT 224 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_FRPE BIT(15) BIT 229 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RAA BIT(2) BIT 235 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_QDDMACH BIT(7) BIT 241 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RXPI BIT(31) BIT 245 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_STARTBUSY BIT(31) BIT 246 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_WRRDN BIT(16) BIT 251 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_MEUIS BIT(1) BIT 252 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_MECIS BIT(0) BIT 254 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RPCEIE BIT(12) BIT 255 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_ECEIE BIT(8) BIT 256 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RXCEIE BIT(4) BIT 257 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TXCEIE BIT(0) BIT 268 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TSF BIT(1) BIT 274 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CC BIT(3) BIT 282 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_EHFC BIT(7) BIT 283 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RSF BIT(5) BIT 292 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RXOIE BIT(16) BIT 294 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RXOVFIS BIT(16) BIT 295 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_ABPSIS BIT(1) BIT 296 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TXUNFIS BIT(0) BIT 301 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_SWR BIT(0) BIT 307 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_EN_LPI BIT(15) BIT 308 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_LPI_XIT_PKT BIT(14) BIT 309 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_AAL BIT(12) BIT 310 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_EAME BIT(11) BIT 312 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_BLEN256 BIT(7) BIT 313 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_BLEN128 BIT(6) BIT 314 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_BLEN64 BIT(5) BIT 315 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_BLEN32 BIT(4) BIT 316 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_BLEN16 BIT(3) BIT 317 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_BLEN8 BIT(2) BIT 318 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_BLEN4 BIT(1) BIT 319 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_UNDEF BIT(0) BIT 325 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_MCSIS BIT(31) BIT 326 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_MSUIS BIT(29) BIT 327 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_MSCIS BIT(28) BIT 328 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_DEUIS BIT(1) BIT 329 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_DECIS BIT(0) BIT 331 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_DCEIE BIT(1) BIT 332 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TCEIE BIT(0) BIT 335 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_SPH BIT(24) BIT 336 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PBLx8 BIT(16) BIT 340 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TSE BIT(12) BIT 341 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_OSP BIT(4) BIT 342 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TXST BIT(0) BIT 348 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RXST BIT(0) BIT 358 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_NIE BIT(15) BIT 359 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_AIE BIT(14) BIT 360 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RBUE BIT(7) BIT 361 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RIE BIT(6) BIT 362 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TBUE BIT(2) BIT 363 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TIE BIT(0) BIT 369 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_NIS BIT(15) BIT 370 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_AIS BIT(14) BIT 371 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_FBE BIT(12) BIT 372 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RBU BIT(7) BIT 373 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RI BIT(6) BIT 374 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TBU BIT(2) BIT 375 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TPS BIT(1) BIT 376 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TI BIT(0) BIT 382 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES2_IOC BIT(31) BIT 383 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES2_TTSE BIT(30) BIT 389 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_OWN BIT(31) BIT 390 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_CTXT BIT(30) BIT 391 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_FD BIT(29) BIT 392 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_LD BIT(28) BIT 395 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_TCMSSV BIT(26) BIT 402 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_TSE BIT(18) BIT 403 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_IVLTV BIT(17) BIT 407 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_VLTV BIT(16) BIT 411 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_OWN BIT(31) BIT 412 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_CTXT BIT(30) BIT 413 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_IOC BIT(30) BIT 414 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_LD BIT(28) BIT 415 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_CDA BIT(27) BIT 416 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_RSV BIT(26) BIT 423 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_ES BIT(15) BIT 425 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_TSD BIT(6) BIT 426 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_TSA BIT(4) BIT 285 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c if (status & BIT(chan)) { BIT 131 drivers/net/ethernet/stmicro/stmmac/stmmac.h #define STMMAC_FLOW_ACTION_DROP BIT(0) BIT 4392 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c (BIT(priv->dma_cap.hash_tb_sz) << 5); BIT 34 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c #define MII_GMAC4_C45E BIT(1) BIT 37 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c #define MII_XGMAC_SADDR BIT(18) BIT 41 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c #define MII_XGMAC_BUSY BIT(22) BIT 62 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c tmp |= BIT(phyaddr); BIT 495 drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev)); BIT 538 drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c pcim_iounmap_regions(pdev, BIT(i)); BIT 25 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_AN_CTRL_RAN BIT(9) /* Restart Auto-Negotiation */ BIT 26 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_AN_CTRL_ANE BIT(12) /* Auto-Negotiation Enable */ BIT 27 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_AN_CTRL_ELE BIT(14) /* External Loopback Enable */ BIT 28 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_AN_CTRL_ECD BIT(16) /* Enable Comma Detect */ BIT 29 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_AN_CTRL_LR BIT(17) /* Lock to Reference */ BIT 30 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_AN_CTRL_SGMRAL BIT(18) /* SGMII RAL Control */ BIT 33 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_AN_STATUS_LS BIT(2) /* Link Status 0:down 1:up */ BIT 34 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_AN_STATUS_ANA BIT(3) /* Auto-Negotiation Ability */ BIT 35 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_AN_STATUS_ANC BIT(5) /* Auto-Negotiation Complete */ BIT 36 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_AN_STATUS_ES BIT(8) /* Extended Status */ BIT 39 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_ANE_FD BIT(5) BIT 40 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_ANE_HD BIT(6) BIT 45 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_ANE_ACK BIT(14) BIT 32 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSENA BIT(0) /* Timestamp Enable */ BIT 33 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSCFUPDT BIT(1) /* Timestamp Fine/Coarse Update */ BIT 34 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSINIT BIT(2) /* Timestamp Initialize */ BIT 35 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSUPDT BIT(3) /* Timestamp Update */ BIT 36 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSTRIG BIT(4) /* Timestamp Interrupt Trigger Enable */ BIT 37 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSADDREG BIT(5) /* Addend Reg Update */ BIT 38 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSENALL BIT(8) /* Enable Timestamp for All Frames */ BIT 39 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSCTRLSSR BIT(9) /* Digital or Binary Rollover Control */ BIT 41 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSVER2ENA BIT(10) BIT 43 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSIPENA BIT(11) BIT 45 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSIPV6ENA BIT(12) BIT 47 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSIPV4ENA BIT(13) BIT 49 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSEVNTENA BIT(14) BIT 51 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSMSTRENA BIT(15) BIT 59 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_SNAPTYPSEL_1 BIT(16) BIT 61 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h #define PTP_TCR_TSENMACADDR BIT(18) BIT 40 drivers/net/ethernet/synopsys/dwc-xlgmac-pci.c ret = pcim_iomap_regions(pcidev, BIT(i), XLGMAC_DRV_NAME); BIT 24 drivers/net/ethernet/ti/cpsw-phy-sel.c #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7) BIT 25 drivers/net/ethernet/ti/cpsw-phy-sel.c #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6) BIT 26 drivers/net/ethernet/ti/cpsw-phy-sel.c #define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5) BIT 27 drivers/net/ethernet/ti/cpsw-phy-sel.c #define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4) BIT 76 drivers/net/ethernet/ti/cpsw-phy-sel.c mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6); BIT 77 drivers/net/ethernet/ti/cpsw-phy-sel.c mask |= BIT(slave + 4); BIT 355 drivers/net/ethernet/ti/cpsw.c return (unsigned long)handle & BIT(0); BIT 360 drivers/net/ethernet/ti/cpsw.c return (void *)((unsigned long)xdpf | BIT(0)); BIT 365 drivers/net/ethernet/ti/cpsw.c return (struct xdp_frame *)((unsigned long)handle & ~BIT(0)); BIT 1516 drivers/net/ethernet/ti/cpsw.c val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT); BIT 1518 drivers/net/ethernet/ti/cpsw.c val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT); BIT 21 drivers/net/ethernet/ti/cpsw_ale.c #define BITMASK(bits) (BIT(bits) - 1) BIT 45 drivers/net/ethernet/ti/cpsw_ale.c #define ALE_TABLE_WRITE BIT(31) BIT 491 drivers/net/ethernet/ti/cpsw_ale.c if (port != -1 && !(vlan_members & BIT(port))) BIT 77 drivers/net/ethernet/ti/cpsw_ale.h #define ALE_SECURE BIT(0) BIT 78 drivers/net/ethernet/ti/cpsw_ale.h #define ALE_BLOCKED BIT(1) BIT 79 drivers/net/ethernet/ti/cpsw_ale.h #define ALE_SUPER BIT(2) BIT 80 drivers/net/ethernet/ti/cpsw_ale.h #define ALE_VLAN BIT(3) BIT 82 drivers/net/ethernet/ti/cpsw_ale.h #define ALE_PORT_HOST BIT(0) BIT 83 drivers/net/ethernet/ti/cpsw_ale.h #define ALE_PORT_1 BIT(1) BIT 84 drivers/net/ethernet/ti/cpsw_ale.h #define ALE_PORT_2 BIT(2) BIT 98 drivers/net/ethernet/ti/cpsw_priv.h #define CPSW_VLAN_AWARE BIT(1) BIT 99 drivers/net/ethernet/ti/cpsw_priv.h #define CPSW_RX_VLAN_ENCAP BIT(2) BIT 206 drivers/net/ethernet/ti/cpsw_priv.h #define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */ BIT 207 drivers/net/ethernet/ti/cpsw_priv.h #define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */ BIT 208 drivers/net/ethernet/ti/cpsw_priv.h #define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */ BIT 209 drivers/net/ethernet/ti/cpsw_priv.h #define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */ BIT 210 drivers/net/ethernet/ti/cpsw_priv.h #define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */ BIT 211 drivers/net/ethernet/ti/cpsw_priv.h #define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */ BIT 212 drivers/net/ethernet/ti/cpsw_priv.h #define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */ BIT 213 drivers/net/ethernet/ti/cpsw_priv.h #define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */ BIT 214 drivers/net/ethernet/ti/cpsw_priv.h #define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */ BIT 215 drivers/net/ethernet/ti/cpsw_priv.h #define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */ BIT 216 drivers/net/ethernet/ti/cpsw_priv.h #define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */ BIT 217 drivers/net/ethernet/ti/cpsw_priv.h #define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */ BIT 218 drivers/net/ethernet/ti/cpsw_priv.h #define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */ BIT 219 drivers/net/ethernet/ti/cpsw_priv.h #define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */ BIT 220 drivers/net/ethernet/ti/cpsw_priv.h #define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */ BIT 221 drivers/net/ethernet/ti/cpsw_priv.h #define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */ BIT 222 drivers/net/ethernet/ti/cpsw_priv.h #define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */ BIT 223 drivers/net/ethernet/ti/cpsw_priv.h #define TS_RX_EN BIT(0) /* Time Sync Receive Enable */ BIT 253 drivers/net/ethernet/ti/cpsw_priv.h #define CPSW_V1_TS_RX_EN BIT(0) BIT 254 drivers/net/ethernet/ti/cpsw_priv.h #define CPSW_V1_TS_TX_EN BIT(4) BIT 74 drivers/net/ethernet/ti/cpsw_sl.c #define CPSW_SL_SOFT_RESET_BIT BIT(0) BIT 76 drivers/net/ethernet/ti/cpsw_sl.c #define CPSW_SL_STATUS_PN_IDLE BIT(31) BIT 77 drivers/net/ethernet/ti/cpsw_sl.c #define CPSW_SL_AM65_STATUS_PN_E_IDLE BIT(30) BIT 78 drivers/net/ethernet/ti/cpsw_sl.c #define CPSW_SL_AM65_STATUS_PN_P_IDLE BIT(29) BIT 79 drivers/net/ethernet/ti/cpsw_sl.c #define CPSW_SL_AM65_STATUS_PN_TX_IDLE BIT(28) BIT 30 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */ BIT 31 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */ BIT 32 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */ BIT 33 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */ BIT 34 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */ BIT 35 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */ BIT 36 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */ BIT 37 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */ BIT 38 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_XGIG = BIT(8), /* 10 Gigabit Mode */ BIT 39 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_TX_SHORT_GAP_EN = BIT(10), /* Transmit Short Gap Enable */ BIT 40 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_CMD_IDLE = BIT(11), /* Command Idle */ BIT 41 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_CRC_TYPE = BIT(12), /* Port CRC Type */ BIT 42 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_XGMII_EN = BIT(13), /* XGMII Enable */ BIT 43 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_IFCTL_A = BIT(15), /* Interface Control A */ BIT 44 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_IFCTL_B = BIT(16), /* Interface Control B */ BIT 45 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_GIG_FORCE = BIT(17), /* Gigabit Mode Force */ BIT 46 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_EXT_EN = BIT(18), /* External Control Enable */ BIT 47 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */ BIT 48 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */ BIT 49 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_TX_SG_LIM_EN = BIT(21), /* TXt Short Gap Limit Enable */ BIT 50 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_RX_CEF_EN = BIT(22), /* RX Copy Error Frames Enable */ BIT 51 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_RX_CSF_EN = BIT(23), /* RX Copy Short Frames Enable */ BIT 52 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_RX_CMF_EN = BIT(24), /* RX Copy MAC Control Frames Enable */ BIT 53 drivers/net/ethernet/ti/cpsw_sl.h CPSW_SL_CTL_EXT_EN_XGIG = BIT(25), /* Ext XGIG Control En, k3 only */ BIT 43 drivers/net/ethernet/ti/davinci_cpdma.c #define CPDMA_DMAINT_HOSTERR BIT(1) BIT 52 drivers/net/ethernet/ti/davinci_cpdma.c #define CPDMA_DESC_SOP BIT(31) BIT 53 drivers/net/ethernet/ti/davinci_cpdma.c #define CPDMA_DESC_EOP BIT(30) BIT 54 drivers/net/ethernet/ti/davinci_cpdma.c #define CPDMA_DESC_OWNER BIT(29) BIT 55 drivers/net/ethernet/ti/davinci_cpdma.c #define CPDMA_DESC_EOQ BIT(28) BIT 56 drivers/net/ethernet/ti/davinci_cpdma.c #define CPDMA_DESC_TD_COMPLETE BIT(27) BIT 57 drivers/net/ethernet/ti/davinci_cpdma.c #define CPDMA_DESC_PASS_CRC BIT(26) BIT 58 drivers/net/ethernet/ti/davinci_cpdma.c #define CPDMA_DESC_TO_PORT_EN BIT(20) BIT 60 drivers/net/ethernet/ti/davinci_cpdma.c #define CPDMA_DESC_PORT_MASK (BIT(18) | BIT(17) | BIT(16)) BIT 132 drivers/net/ethernet/ti/davinci_cpdma.c #define ACCESS_RO BIT(0) BIT 133 drivers/net/ethernet/ti/davinci_cpdma.c #define ACCESS_WO BIT(1) BIT 188 drivers/net/ethernet/ti/davinci_cpdma.c #define CPDMA_DMA_EXT_MAP BIT(16) BIT 922 drivers/net/ethernet/ti/davinci_cpdma.c chan->mask = BIT(chan_linear(chan)); BIT 15 drivers/net/ethernet/ti/davinci_cpdma.h #define CPDMA_RX_VLAN_ENCAP BIT(19) BIT 132 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_RXMBP_PASSCRC_MASK BIT(30) BIT 133 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_RXMBP_QOSEN_MASK BIT(29) BIT 134 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_RXMBP_NOCHAIN_MASK BIT(28) BIT 135 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_RXMBP_CMFEN_MASK BIT(24) BIT 136 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_RXMBP_CSFEN_MASK BIT(23) BIT 137 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_RXMBP_CEFEN_MASK BIT(22) BIT 138 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_RXMBP_CAFEN_MASK BIT(21) BIT 141 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_RXMBP_BROADEN_MASK BIT(13) BIT 144 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_RXMBP_MULTIEN_MASK BIT(5) BIT 158 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_MACCONTROL_TXPTYPE BIT(9) BIT 159 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_MACCONTROL_TXPACEEN BIT(6) BIT 160 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_MACCONTROL_GMIIEN BIT(5) BIT 161 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_MACCONTROL_GIGABITEN BIT(7) BIT 162 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) BIT 163 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) BIT 166 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_DM646X_MACCONTORL_GIG BIT(7) BIT 167 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) BIT 184 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) BIT 185 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) BIT 186 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) BIT 187 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) BIT 190 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) BIT 191 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) BIT 192 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) BIT 193 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) BIT 196 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_CPPI_SOP_BIT BIT(31) BIT 197 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_CPPI_EOP_BIT BIT(30) BIT 198 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_CPPI_OWNERSHIP_BIT BIT(29) BIT 199 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_CPPI_EOQ_BIT BIT(28) BIT 200 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) BIT 201 drivers/net/ethernet/ti/davinci_emac.c #define EMAC_CPPI_PASS_CRC_BIT BIT(26) BIT 613 drivers/net/ethernet/ti/davinci_emac.c hash_bit = BIT(hash_value); BIT 616 drivers/net/ethernet/ti/davinci_emac.c hash_bit = BIT((hash_value - 32)); BIT 652 drivers/net/ethernet/ti/davinci_emac.c hash_bit = BIT(hash_value); BIT 655 drivers/net/ethernet/ti/davinci_emac.c hash_bit = BIT((hash_value - 32)); BIT 1021 drivers/net/ethernet/ti/davinci_emac.c val |= BIT(ch); BIT 1024 drivers/net/ethernet/ti/davinci_emac.c val &= ~BIT(ch); BIT 1071 drivers/net/ethernet/ti/davinci_emac.c (match << 19) | BIT(20)); BIT 49 drivers/net/ethernet/ti/davinci_mdio.c #define CONTROL_IDLE BIT(31) BIT 50 drivers/net/ethernet/ti/davinci_mdio.c #define CONTROL_ENABLE BIT(30) BIT 66 drivers/net/ethernet/ti/davinci_mdio.c #define USERACCESS_GO BIT(31) BIT 67 drivers/net/ethernet/ti/davinci_mdio.c #define USERACCESS_WRITE BIT(30) BIT 68 drivers/net/ethernet/ti/davinci_mdio.c #define USERACCESS_ACK BIT(29) BIT 41 drivers/net/ethernet/ti/netcp.h #define SWITCH_TO_PORT_IN_TAGINFO BIT(0) BIT 47 drivers/net/ethernet/ti/netcp.h #define ADDR_NEW BIT(0) BIT 48 drivers/net/ethernet/ti/netcp.h #define ADDR_VALID BIT(1) BIT 99 drivers/net/ethernet/ti/netcp.h #define ETH_SW_CAN_REMOVE_ETH_FCS BIT(0) BIT 109 drivers/net/ethernet/ti/netcp_ethss.c #define SOFT_RESET_MASK BIT(0) BIT 110 drivers/net/ethernet/ti/netcp_ethss.c #define SOFT_RESET BIT(0) BIT 114 drivers/net/ethernet/ti/netcp_ethss.c #define MACSL_RX_ENABLE_CSF BIT(23) BIT 115 drivers/net/ethernet/ti/netcp_ethss.c #define MACSL_ENABLE_EXT_CTL BIT(18) BIT 116 drivers/net/ethernet/ti/netcp_ethss.c #define MACSL_XGMII_ENABLE BIT(13) BIT 117 drivers/net/ethernet/ti/netcp_ethss.c #define MACSL_XGIG_MODE BIT(8) BIT 118 drivers/net/ethernet/ti/netcp_ethss.c #define MACSL_GIG_MODE BIT(7) BIT 119 drivers/net/ethernet/ti/netcp_ethss.c #define MACSL_GMII_ENABLE BIT(5) BIT 120 drivers/net/ethernet/ti/netcp_ethss.c #define MACSL_FULLDUPLEX BIT(0) BIT 122 drivers/net/ethernet/ti/netcp_ethss.c #define GBE_CTL_P0_ENABLE BIT(2) BIT 123 drivers/net/ethernet/ti/netcp_ethss.c #define ETH_SW_CTL_P0_TX_CRC_REMOVE BIT(13) BIT 126 drivers/net/ethernet/ti/netcp_ethss.c #define GBE_STATS_CD_SEL BIT(28) BIT 128 drivers/net/ethernet/ti/netcp_ethss.c #define GBE_PORT_MASK(x) (BIT(x) - 1) BIT 186 drivers/net/ethernet/ti/netcp_ethss.c #define TS_RX_ANX_F_EN BIT(0) BIT 187 drivers/net/ethernet/ti/netcp_ethss.c #define TS_RX_VLAN_LT1_EN BIT(1) BIT 188 drivers/net/ethernet/ti/netcp_ethss.c #define TS_RX_VLAN_LT2_EN BIT(2) BIT 189 drivers/net/ethernet/ti/netcp_ethss.c #define TS_RX_ANX_D_EN BIT(3) BIT 190 drivers/net/ethernet/ti/netcp_ethss.c #define TS_TX_ANX_F_EN BIT(4) BIT 191 drivers/net/ethernet/ti/netcp_ethss.c #define TS_TX_VLAN_LT1_EN BIT(5) BIT 192 drivers/net/ethernet/ti/netcp_ethss.c #define TS_TX_VLAN_LT2_EN BIT(6) BIT 193 drivers/net/ethernet/ti/netcp_ethss.c #define TS_TX_ANX_D_EN BIT(7) BIT 194 drivers/net/ethernet/ti/netcp_ethss.c #define TS_LT2_EN BIT(8) BIT 195 drivers/net/ethernet/ti/netcp_ethss.c #define TS_RX_ANX_E_EN BIT(9) BIT 196 drivers/net/ethernet/ti/netcp_ethss.c #define TS_TX_ANX_E_EN BIT(10) BIT 205 drivers/net/ethernet/ti/netcp_ethss.c #define TS_107 BIT(16) BIT 206 drivers/net/ethernet/ti/netcp_ethss.c #define TS_129 BIT(17) BIT 207 drivers/net/ethernet/ti/netcp_ethss.c #define TS_130 BIT(18) BIT 208 drivers/net/ethernet/ti/netcp_ethss.c #define TS_131 BIT(19) BIT 209 drivers/net/ethernet/ti/netcp_ethss.c #define TS_132 BIT(20) BIT 210 drivers/net/ethernet/ti/netcp_ethss.c #define TS_319 BIT(21) BIT 211 drivers/net/ethernet/ti/netcp_ethss.c #define TS_320 BIT(22) BIT 212 drivers/net/ethernet/ti/netcp_ethss.c #define TS_TTL_NONZERO BIT(23) BIT 213 drivers/net/ethernet/ti/netcp_ethss.c #define TS_UNI_EN BIT(24) BIT 231 drivers/net/ethernet/ti/netcp_ethss.c #define EVENT_MSG_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) BIT 2128 drivers/net/ethernet/ti/netcp_ethss.c #define RGMII_REG_STATUS_LINK BIT(0) BIT 14 drivers/net/ethernet/ti/netcp_sgmii.c #define SGMII_SRESET_RESET BIT(0) BIT 15 drivers/net/ethernet/ti/netcp_sgmii.c #define SGMII_SRESET_RTRESET BIT(1) BIT 17 drivers/net/ethernet/ti/netcp_sgmii.c #define SGMII_REG_STATUS_LOCK BIT(4) BIT 18 drivers/net/ethernet/ti/netcp_sgmii.c #define SGMII_REG_STATUS_LINK BIT(0) BIT 19 drivers/net/ethernet/ti/netcp_sgmii.c #define SGMII_REG_STATUS_AUTONEG BIT(2) BIT 20 drivers/net/ethernet/ti/netcp_sgmii.c #define SGMII_REG_CONTROL_AUTONEG BIT(0) BIT 19 drivers/net/ethernet/ti/netcp_xgbepcsr.c #define POR_EN BIT(29) BIT 212 drivers/net/ethernet/ti/netcp_xgbepcsr.c val_0 = (readl(sw_regs + XGBE_SGMII_1_OFFSET) & BIT(4)); BIT 213 drivers/net/ethernet/ti/netcp_xgbepcsr.c val_1 = (readl(sw_regs + XGBE_SGMII_2_OFFSET) & BIT(4)); BIT 258 drivers/net/ethernet/wiznet/w5100-spi.c ((W5500_SPI_BLOCK_SELECT(addr) << 3) | BIT(2)) BIT 1180 drivers/net/hyperv/hyperv_net.h #define RNDIS_PKTINFO_SUBALLOC BIT(0) BIT 1181 drivers/net/hyperv/hyperv_net.h #define RNDIS_PKTINFO_1ST_FRAG BIT(1) BIT 1182 drivers/net/hyperv/hyperv_net.h #define RNDIS_PKTINFO_LAST_FRAG BIT(2) BIT 118 drivers/net/ieee802154/adf7242.c #define EXTPA_BIAS_SRC BIT(3) BIT 128 drivers/net/ieee802154/adf7242.c #define REG_PA_BIAS_DFL BIT(0) BIT 151 drivers/net/ieee802154/adf7242.c #define ACCEPT_BEACON_FRAMES BIT(0) BIT 152 drivers/net/ieee802154/adf7242.c #define ACCEPT_DATA_FRAMES BIT(1) BIT 153 drivers/net/ieee802154/adf7242.c #define ACCEPT_ACK_FRAMES BIT(2) BIT 154 drivers/net/ieee802154/adf7242.c #define ACCEPT_MACCMD_FRAMES BIT(3) BIT 155 drivers/net/ieee802154/adf7242.c #define ACCEPT_RESERVED_FRAMES BIT(4) BIT 156 drivers/net/ieee802154/adf7242.c #define ACCEPT_ALL_ADDRESS BIT(5) BIT 159 drivers/net/ieee802154/adf7242.c #define AUTO_ACK_FRAMEPEND BIT(0) BIT 160 drivers/net/ieee802154/adf7242.c #define IS_PANCOORD BIT(1) BIT 161 drivers/net/ieee802154/adf7242.c #define RX_AUTO_ACK_EN BIT(3) BIT 162 drivers/net/ieee802154/adf7242.c #define CSMA_CA_RX_TURNAROUND BIT(4) BIT 225 drivers/net/ieee802154/adf7242.c #define CMD_RC_PC_RESET_NO_WAIT (CMD_RC_PC_RESET | BIT(31)) BIT 229 drivers/net/ieee802154/adf7242.c #define STAT_SPI_READY BIT(7) BIT 230 drivers/net/ieee802154/adf7242.c #define STAT_IRQ_STATUS BIT(6) BIT 231 drivers/net/ieee802154/adf7242.c #define STAT_RC_READY BIT(5) BIT 232 drivers/net/ieee802154/adf7242.c #define STAT_CCA_RESULT BIT(4) BIT 252 drivers/net/ieee802154/adf7242.c #define IRQ_CCA_COMPLETE BIT(0) BIT 253 drivers/net/ieee802154/adf7242.c #define IRQ_SFD_RX BIT(1) BIT 254 drivers/net/ieee802154/adf7242.c #define IRQ_SFD_TX BIT(2) BIT 255 drivers/net/ieee802154/adf7242.c #define IRQ_RX_PKT_RCVD BIT(3) BIT 256 drivers/net/ieee802154/adf7242.c #define IRQ_TX_PKT_SENT BIT(4) BIT 257 drivers/net/ieee802154/adf7242.c #define IRQ_FRAME_VALID BIT(5) BIT 258 drivers/net/ieee802154/adf7242.c #define IRQ_ADDRESS_VALID BIT(6) BIT 259 drivers/net/ieee802154/adf7242.c #define IRQ_CSMA_CA BIT(7) BIT 261 drivers/net/ieee802154/adf7242.c #define AUTO_TX_TURNAROUND BIT(3) BIT 262 drivers/net/ieee802154/adf7242.c #define ADDON_EN BIT(4) BIT 1048 drivers/net/ieee802154/adf7242.c adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2)); BIT 1111 drivers/net/ieee802154/adf7242.c adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2)); BIT 1223 drivers/net/ieee802154/adf7242.c hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY); BIT 1546 drivers/net/ieee802154/at86rf230.c lp->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) | BIT 1547 drivers/net/ieee802154/at86rf230.c BIT(NL802154_CCA_CARRIER) | BIT(NL802154_CCA_ENERGY_CARRIER); BIT 1548 drivers/net/ieee802154/at86rf230.c lp->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) | BIT 1549 drivers/net/ieee802154/at86rf230.c BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR); BIT 176 drivers/net/ieee802154/at86rf230.h #define IRQ_BAT_LOW BIT(7) BIT 177 drivers/net/ieee802154/at86rf230.h #define IRQ_TRX_UR BIT(6) BIT 178 drivers/net/ieee802154/at86rf230.h #define IRQ_AMI BIT(5) BIT 179 drivers/net/ieee802154/at86rf230.h #define IRQ_CCA_ED BIT(4) BIT 180 drivers/net/ieee802154/at86rf230.h #define IRQ_TRX_END BIT(3) BIT 181 drivers/net/ieee802154/at86rf230.h #define IRQ_RX_START BIT(2) BIT 182 drivers/net/ieee802154/at86rf230.h #define IRQ_PLL_UNL BIT(1) BIT 183 drivers/net/ieee802154/at86rf230.h #define IRQ_PLL_LOCK BIT(0) BIT 896 drivers/net/ieee802154/atusb.c hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) | BIT 897 drivers/net/ieee802154/atusb.c BIT(NL802154_CCA_CARRIER) | BIT 898 drivers/net/ieee802154/atusb.c BIT(NL802154_CCA_ENERGY_CARRIER); BIT 899 drivers/net/ieee802154/atusb.c hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) | BIT 900 drivers/net/ieee802154/atusb.c BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR); BIT 44 drivers/net/ieee802154/cc2520.c #define CC2520_STATUS_XOSC32M_STABLE BIT(7) BIT 45 drivers/net/ieee802154/cc2520.c #define CC2520_STATUS_RSSI_VALID BIT(6) BIT 46 drivers/net/ieee802154/cc2520.c #define CC2520_STATUS_TX_UNDERFLOW BIT(3) BIT 190 drivers/net/ieee802154/cc2520.c #define FRMFILT0_FRAME_FILTER_EN BIT(0) BIT 191 drivers/net/ieee802154/cc2520.c #define FRMFILT0_PAN_COORDINATOR BIT(1) BIT 194 drivers/net/ieee802154/cc2520.c #define FRMCTRL0_AUTOACK BIT(5) BIT 195 drivers/net/ieee802154/cc2520.c #define FRMCTRL0_AUTOCRC BIT(6) BIT 198 drivers/net/ieee802154/cc2520.c #define FRMCTRL1_SET_RXENMASK_ON_TX BIT(0) BIT 199 drivers/net/ieee802154/cc2520.c #define FRMCTRL1_IGNORE_TX_UNDERF BIT(1) BIT 577 drivers/net/ieee802154/cc2520.c crc_ok = skb->data[len - 1] & BIT(7); BIT 29 drivers/net/ieee802154/mcr20a.c #define REGISTER_READ BIT(7) BIT 32 drivers/net/ieee802154/mcr20a.c #define PACKET_BUFF_BURST_ACCESS BIT(6) BIT 33 drivers/net/ieee802154/mcr20a.c #define PACKET_BUFF_BYTE_ACCESS BIT(5) BIT 989 drivers/net/ieee802154/mcr20a.c phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) | BIT 990 drivers/net/ieee802154/mcr20a.c BIT(NL802154_CCA_CARRIER) | BIT(NL802154_CCA_ENERGY_CARRIER); BIT 991 drivers/net/ieee802154/mcr20a.c phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) | BIT 992 drivers/net/ieee802154/mcr20a.c BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR); BIT 257 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS1_RX_FRM_PEND BIT(7) BIT 258 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS1_PLL_UNLOCK_IRQ BIT(6) BIT 259 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS1_FILTERFAIL_IRQ BIT(5) BIT 260 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS1_RXWTRMRKIRQ BIT(4) BIT 261 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS1_CCAIRQ BIT(3) BIT 262 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS1_RXIRQ BIT(2) BIT 263 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS1_TXIRQ BIT(1) BIT 264 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS1_SEQIRQ BIT(0) BIT 267 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS2_CRCVALID BIT(7) BIT 268 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS2_CCA BIT(6) BIT 269 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS2_SRCADDR BIT(5) BIT 270 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS2_PI BIT(4) BIT 271 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS2_TMRSTATUS BIT(3) BIT 272 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS2_ASM_IRQ BIT(2) BIT 273 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS2_PB_ERR_IRQ BIT(1) BIT 274 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS2_WAKE_IRQ BIT(0) BIT 277 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS3_TMR4MSK BIT(7) BIT 278 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS3_TMR3MSK BIT(6) BIT 279 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS3_TMR2MSK BIT(5) BIT 280 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS3_TMR1MSK BIT(4) BIT 281 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS3_TMR4IRQ BIT(3) BIT 282 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS3_TMR3IRQ BIT(2) BIT 283 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS3_TMR2IRQ BIT(1) BIT 284 drivers/net/ieee802154/mcr20a.h #define DAR_IRQSTS3_TMR1IRQ BIT(0) BIT 287 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL1_TMRTRIGEN BIT(7) BIT 288 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL1_SLOTTED BIT(6) BIT 289 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL1_CCABFRTX BIT(5) BIT 291 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL1_RXACKRQD BIT(4) BIT 292 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL1_AUTOACK BIT(3) BIT 296 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL2_CRC_MSK BIT(7) BIT 297 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6) BIT 298 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL2_FILTERFAIL_MSK BIT(5) BIT 299 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL2_RX_WMRK_MSK BIT(4) BIT 300 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL2_CCAMSK BIT(3) BIT 301 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL2_RXMSK BIT(2) BIT 302 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL2_TXMSK BIT(1) BIT 303 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL2_SEQMSK BIT(0) BIT 306 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL3_TMR4CMP_EN BIT(7) BIT 307 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL3_TMR3CMP_EN BIT(6) BIT 308 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL3_TMR2CMP_EN BIT(5) BIT 309 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL3_TMR1CMP_EN BIT(4) BIT 310 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL3_ASM_MSK BIT(2) BIT 311 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL3_PB_ERR_MSK BIT(1) BIT 312 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL3_WAKE_MSK BIT(0) BIT 318 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL4_TRCV_MSK BIT(7) BIT 319 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL4_TC3TMOUT BIT(6) BIT 320 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL4_PANCORDNTR0 BIT(5) BIT 324 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL4_TMRLOAD BIT(2) BIT 325 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL4_PROMISCUOUS BIT(1) BIT 326 drivers/net/ieee802154/mcr20a.h #define DAR_PHY_CTRL4_TC2PRIME_EN BIT(0) BIT 331 drivers/net/ieee802154/mcr20a.h #define DAR_SRC_CTRL_ACK_FRM_PND BIT(3) BIT 332 drivers/net/ieee802154/mcr20a.h #define DAR_SRC_CTRL_SRCADDR_EN BIT(2) BIT 333 drivers/net/ieee802154/mcr20a.h #define DAR_SRC_CTRL_INDEX_EN BIT(1) BIT 334 drivers/net/ieee802154/mcr20a.h #define DAR_SRC_CTRL_INDEX_DISABLE BIT(0) BIT 337 drivers/net/ieee802154/mcr20a.h #define DAR_ASM_CTRL1_CLEAR BIT(7) BIT 338 drivers/net/ieee802154/mcr20a.h #define DAR_ASM_CTRL1_START BIT(6) BIT 339 drivers/net/ieee802154/mcr20a.h #define DAR_ASM_CTRL1_SELFTST BIT(5) BIT 340 drivers/net/ieee802154/mcr20a.h #define DAR_ASM_CTRL1_CTR BIT(4) BIT 341 drivers/net/ieee802154/mcr20a.h #define DAR_ASM_CTRL1_CBC BIT(3) BIT 342 drivers/net/ieee802154/mcr20a.h #define DAR_ASM_CTRL1_AES BIT(2) BIT 343 drivers/net/ieee802154/mcr20a.h #define DAR_ASM_CTRL1_LOAD_MAC BIT(1) BIT 348 drivers/net/ieee802154/mcr20a.h #define DAR_ASM_CTRL2_TSTPAS BIT(1) BIT 351 drivers/net/ieee802154/mcr20a.h #define DAR_CLK_OUT_CTRL_EXTEND BIT(7) BIT 352 drivers/net/ieee802154/mcr20a.h #define DAR_CLK_OUT_CTRL_HIZ BIT(6) BIT 353 drivers/net/ieee802154/mcr20a.h #define DAR_CLK_OUT_CTRL_SR BIT(5) BIT 354 drivers/net/ieee802154/mcr20a.h #define DAR_CLK_OUT_CTRL_DS BIT(4) BIT 355 drivers/net/ieee802154/mcr20a.h #define DAR_CLK_OUT_CTRL_EN BIT(3) BIT 359 drivers/net/ieee802154/mcr20a.h #define DAR_PWR_MODES_XTAL_READY BIT(5) BIT 360 drivers/net/ieee802154/mcr20a.h #define DAR_PWR_MODES_XTALEN BIT(4) BIT 361 drivers/net/ieee802154/mcr20a.h #define DAR_PWR_MODES_ASM_CLK_EN BIT(3) BIT 362 drivers/net/ieee802154/mcr20a.h #define DAR_PWR_MODES_AUTODOZE BIT(1) BIT 363 drivers/net/ieee802154/mcr20a.h #define DAR_PWR_MODES_PMC_MODE BIT(0) BIT 368 drivers/net/ieee802154/mcr20a.h #define IAR_RX_FRAME_FLT_ACTIVE_PROMISCUOUS BIT(5) BIT 369 drivers/net/ieee802154/mcr20a.h #define IAR_RX_FRAME_FLT_NS_FT BIT(4) BIT 370 drivers/net/ieee802154/mcr20a.h #define IAR_RX_FRAME_FLT_CMD_FT BIT(3) BIT 371 drivers/net/ieee802154/mcr20a.h #define IAR_RX_FRAME_FLT_ACK_FT BIT(2) BIT 372 drivers/net/ieee802154/mcr20a.h #define IAR_RX_FRAME_FLT_DATA_FT BIT(1) BIT 373 drivers/net/ieee802154/mcr20a.h #define IAR_RX_FRAME_FLT_BEACON_FT BIT(0) BIT 378 drivers/net/ieee802154/mcr20a.h #define IAR_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3) BIT 379 drivers/net/ieee802154/mcr20a.h #define IAR_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2) BIT 380 drivers/net/ieee802154/mcr20a.h #define IAR_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1) BIT 381 drivers/net/ieee802154/mcr20a.h #define IAR_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0) BIT 384 drivers/net/ieee802154/mcr20a.h #define IAR_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7) BIT 385 drivers/net/ieee802154/mcr20a.h #define IAR_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6) BIT 389 drivers/net/ieee802154/mcr20a.h #define IAR_CCA_CTRL_AGC_FRZ_EN BIT(6) BIT 390 drivers/net/ieee802154/mcr20a.h #define IAR_CCA_CTRL_CONT_RSSI_EN BIT(5) BIT 391 drivers/net/ieee802154/mcr20a.h #define IAR_CCA_CTRL_LQI_RSSI_NOT_CORR BIT(4) BIT 392 drivers/net/ieee802154/mcr20a.h #define IAR_CCA_CTRL_CCA3_AND_NOT_OR BIT(3) BIT 393 drivers/net/ieee802154/mcr20a.h #define IAR_CCA_CTRL_POWER_COMP_EN_LQI BIT(2) BIT 394 drivers/net/ieee802154/mcr20a.h #define IAR_CCA_CTRL_POWER_COMP_EN_ED BIT(1) BIT 395 drivers/net/ieee802154/mcr20a.h #define IAR_CCA_CTRL_POWER_COMP_EN_CCA1 BIT(0) BIT 400 drivers/net/ieee802154/mcr20a.h #define IAR_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3) BIT 401 drivers/net/ieee802154/mcr20a.h #define IAR_ANT_PAD_CTRL_ANTX_HZ BIT(2) BIT 405 drivers/net/ieee802154/mcr20a.h #define IAR_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3) BIT 406 drivers/net/ieee802154/mcr20a.h #define IAR_MISC_PAD_CTRL_IRQ_B_OD BIT(2) BIT 407 drivers/net/ieee802154/mcr20a.h #define IAR_MISC_PAD_CTRL_NON_GPIO_DS BIT(1) BIT 414 drivers/net/ieee802154/mcr20a.h #define IAR_ANT_AGC_CTRL_ANTX_MASK BIT(AR_ANT_AGC_CTRL_ANTX_SHIFT) BIT 420 drivers/net/ieee802154/mcr20a.h #define IAR_SOFT_RESET_SOG_RST BIT(7) BIT 421 drivers/net/ieee802154/mcr20a.h #define IAR_SOFT_RESET_REGS_RST BIT(4) BIT 422 drivers/net/ieee802154/mcr20a.h #define IAR_SOFT_RESET_PLL_RST BIT(3) BIT 423 drivers/net/ieee802154/mcr20a.h #define IAR_SOFT_RESET_TX_RST BIT(2) BIT 424 drivers/net/ieee802154/mcr20a.h #define IAR_SOFT_RESET_RX_RST BIT(1) BIT 425 drivers/net/ieee802154/mcr20a.h #define IAR_SOFT_RESET_SEQ_MGR_RST BIT(0) BIT 430 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5) BIT 431 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4) BIT 432 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3) BIT 433 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2) BIT 434 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1) BIT 435 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0) BIT 438 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7) BIT 439 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_STS_RX_MODE BIT(6) BIT 440 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5) BIT 441 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4) BIT 442 drivers/net/ieee802154/mcr20a.h #define IAR_SEQ_MGR_STS_SEQ_IDLE BIT(3) BIT 446 drivers/net/ieee802154/mcr20a.h #define IAR_ABORT_STS_PLL_ABORTED BIT(2) BIT 447 drivers/net/ieee802154/mcr20a.h #define IAR_ABORT_STS_TC3_ABORTED BIT(1) BIT 448 drivers/net/ieee802154/mcr20a.h #define IAR_ABORT_STS_SW_ABORTED BIT(0) BIT 451 drivers/net/ieee802154/mcr20a.h #define IAR_FILTERFAIL_CODE2_PAN_SEL BIT(7) BIT 455 drivers/net/ieee802154/mcr20a.h #define IAR_PHY_STS_PLL_UNLOCK BIT(7) BIT 456 drivers/net/ieee802154/mcr20a.h #define IAR_PHY_STS_PLL_LOCK_ERR BIT(6) BIT 457 drivers/net/ieee802154/mcr20a.h #define IAR_PHY_STS_PLL_LOCK BIT(5) BIT 458 drivers/net/ieee802154/mcr20a.h #define IAR_PHY_STS_CRCVALID BIT(3) BIT 459 drivers/net/ieee802154/mcr20a.h #define IAR_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2) BIT 460 drivers/net/ieee802154/mcr20a.h #define IAR_PHY_STS_SFD_DET BIT(1) BIT 461 drivers/net/ieee802154/mcr20a.h #define IAR_PHY_STS_PREAMBLE_DET BIT(0) BIT 464 drivers/net/ieee802154/mcr20a.h #define IAR_TEST_MODE_CTRL_HOT_ANT BIT(4) BIT 465 drivers/net/ieee802154/mcr20a.h #define IAR_TEST_MODE_CTRL_IDEAL_RSSI_EN BIT(3) BIT 466 drivers/net/ieee802154/mcr20a.h #define IAR_TEST_MODE_CTRL_IDEAL_PFC_EN BIT(2) BIT 467 drivers/net/ieee802154/mcr20a.h #define IAR_TEST_MODE_CTRL_CONTINUOUS_EN BIT(1) BIT 468 drivers/net/ieee802154/mcr20a.h #define IAR_TEST_MODE_CTRL_FPGA_EN BIT(0) BIT 471 drivers/net/ieee802154/mcr20a.h #define IAR_DTM_CTRL1_ATM_LOCKED BIT(7) BIT 472 drivers/net/ieee802154/mcr20a.h #define IAR_DTM_CTRL1_DTM_EN BIT(6) BIT 473 drivers/net/ieee802154/mcr20a.h #define IAR_DTM_CTRL1_PAGE5 BIT(5) BIT 474 drivers/net/ieee802154/mcr20a.h #define IAR_DTM_CTRL1_PAGE4 BIT(4) BIT 475 drivers/net/ieee802154/mcr20a.h #define IAR_DTM_CTRL1_PAGE3 BIT(3) BIT 476 drivers/net/ieee802154/mcr20a.h #define IAR_DTM_CTRL1_PAGE2 BIT(2) BIT 477 drivers/net/ieee802154/mcr20a.h #define IAR_DTM_CTRL1_PAGE1 BIT(1) BIT 478 drivers/net/ieee802154/mcr20a.h #define IAR_DTM_CTRL1_PAGE0 BIT(0) BIT 481 drivers/net/ieee802154/mcr20a.h #define IAR_TX_MODE_CTRL_TX_INV BIT(4) BIT 482 drivers/net/ieee802154/mcr20a.h #define IAR_TX_MODE_CTRL_BT_EN BIT(3) BIT 483 drivers/net/ieee802154/mcr20a.h #define IAR_TX_MODE_CTRL_DTS2 BIT(2) BIT 484 drivers/net/ieee802154/mcr20a.h #define IAR_TX_MODE_CTRL_DTS1 BIT(1) BIT 485 drivers/net/ieee802154/mcr20a.h #define IAR_TX_MODE_CTRL_DTS0 BIT(0) BIT 21 drivers/net/ieee802154/mrf24j40.c #define BIT_PROMI BIT(0) BIT 22 drivers/net/ieee802154/mrf24j40.c #define BIT_ERRPKT BIT(1) BIT 23 drivers/net/ieee802154/mrf24j40.c #define BIT_NOACKRSP BIT(5) BIT 24 drivers/net/ieee802154/mrf24j40.c #define BIT_PANCOORD BIT(3) BIT 55 drivers/net/ieee802154/mrf24j40.c #define BIT_TXNTRIG BIT(0) BIT 56 drivers/net/ieee802154/mrf24j40.c #define BIT_TXNSECEN BIT(1) BIT 57 drivers/net/ieee802154/mrf24j40.c #define BIT_TXNACKREQ BIT(2) BIT 79 drivers/net/ieee802154/mrf24j40.c #define BIT_TXNIF BIT(0) BIT 80 drivers/net/ieee802154/mrf24j40.c #define BIT_RXIF BIT(3) BIT 81 drivers/net/ieee802154/mrf24j40.c #define BIT_SECIF BIT(4) BIT 82 drivers/net/ieee802154/mrf24j40.c #define BIT_SECIGNORE BIT(7) BIT 85 drivers/net/ieee802154/mrf24j40.c #define BIT_TXNIE BIT(0) BIT 86 drivers/net/ieee802154/mrf24j40.c #define BIT_RXIE BIT(3) BIT 87 drivers/net/ieee802154/mrf24j40.c #define BIT_SECIE BIT(4) BIT 93 drivers/net/ieee802154/mrf24j40.c #define BIT_RFRST BIT(2) BIT 98 drivers/net/ieee802154/mrf24j40.c #define BIT_RXDECINV BIT(2) BIT 147 drivers/net/ieee802154/mrf24j40.c #define BIT_INTEDGE BIT(1) BIT 1250 drivers/net/ieee802154/mrf24j40.c devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) | BIT 1251 drivers/net/ieee802154/mrf24j40.c BIT(NL802154_CCA_CARRIER) | BIT 1252 drivers/net/ieee802154/mrf24j40.c BIT(NL802154_CCA_ENERGY_CARRIER); BIT 1253 drivers/net/ieee802154/mrf24j40.c devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND); BIT 253 drivers/net/netdevsim/dev.c BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), BIT 257 drivers/net/netdevsim/dev.c BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), BIT 31 drivers/net/netdevsim/netdevsim.h #define NSIM_IPSEC_VALID BIT(31) BIT 24 drivers/net/phy/adin.c #define ADIN1300_AUTO_MDI_EN BIT(10) BIT 25 drivers/net/phy/adin.c #define ADIN1300_MAN_MDIX_EN BIT(9) BIT 30 drivers/net/phy/adin.c #define ADIN1300_NRG_PD_EN BIT(3) BIT 31 drivers/net/phy/adin.c #define ADIN1300_NRG_PD_TX_EN BIT(2) BIT 32 drivers/net/phy/adin.c #define ADIN1300_NRG_PD_STATUS BIT(1) BIT 35 drivers/net/phy/adin.c #define ADIN1300_DOWNSPEED_AN_100_EN BIT(11) BIT 36 drivers/net/phy/adin.c #define ADIN1300_DOWNSPEED_AN_10_EN BIT(10) BIT 37 drivers/net/phy/adin.c #define ADIN1300_GROUP_MDIO_EN BIT(6) BIT 42 drivers/net/phy/adin.c #define ADIN1300_LINKING_EN BIT(13) BIT 46 drivers/net/phy/adin.c #define ADIN1300_INT_MDIO_SYNC_EN BIT(9) BIT 47 drivers/net/phy/adin.c #define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8) BIT 48 drivers/net/phy/adin.c #define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6) BIT 49 drivers/net/phy/adin.c #define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5) BIT 50 drivers/net/phy/adin.c #define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4) BIT 51 drivers/net/phy/adin.c #define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3) BIT 52 drivers/net/phy/adin.c #define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2) BIT 53 drivers/net/phy/adin.c #define ADIN1300_INT_SPEED_CHNG_EN BIT(1) BIT 54 drivers/net/phy/adin.c #define ADIN1300_INT_HW_IRQ_EN BIT(0) BIT 60 drivers/net/phy/adin.c #define ADIN1300_PAIR_01_SWAP BIT(11) BIT 73 drivers/net/phy/adin.c #define ADIN1300_GE_SOFT_RESET BIT(0) BIT 82 drivers/net/phy/adin.c #define ADIN1300_GE_RGMII_RXID_EN BIT(2) BIT 83 drivers/net/phy/adin.c #define ADIN1300_GE_RGMII_TXID_EN BIT(1) BIT 84 drivers/net/phy/adin.c #define ADIN1300_GE_RGMII_EN BIT(0) BIT 97 drivers/net/phy/adin.c #define ADIN1300_GE_RMII_EN BIT(0) BIT 23 drivers/net/phy/aquantia_hwmon.c #define VEND1_THERMAL_STAT2_VALID BIT(0) BIT 25 drivers/net/phy/aquantia_hwmon.c #define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14) BIT 26 drivers/net/phy/aquantia_hwmon.c #define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13) BIT 27 drivers/net/phy/aquantia_hwmon.c #define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12) BIT 28 drivers/net/phy/aquantia_hwmon.c #define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11) BIT 35 drivers/net/phy/aquantia_main.c #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) BIT 36 drivers/net/phy/aquantia_main.c #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) BIT 37 drivers/net/phy/aquantia_main.c #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) BIT 49 drivers/net/phy/aquantia_main.c #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) BIT 52 drivers/net/phy/aquantia_main.c #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) BIT 57 drivers/net/phy/aquantia_main.c #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) BIT 60 drivers/net/phy/aquantia_main.c #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) BIT 61 drivers/net/phy/aquantia_main.c #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) BIT 62 drivers/net/phy/aquantia_main.c #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) BIT 63 drivers/net/phy/aquantia_main.c #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) BIT 64 drivers/net/phy/aquantia_main.c #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) BIT 71 drivers/net/phy/aquantia_main.c #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) BIT 102 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) BIT 103 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) BIT 104 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) BIT 105 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) BIT 106 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) BIT 107 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) BIT 108 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) BIT 109 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) BIT 110 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) BIT 111 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) BIT 112 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) BIT 115 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) BIT 116 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) BIT 117 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) BIT 118 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) BIT 119 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) BIT 120 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) BIT 121 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) BIT 122 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) BIT 23 drivers/net/phy/at803x.c #define AT803X_SS_DUPLEX BIT(13) BIT 24 drivers/net/phy/at803x.c #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) BIT 25 drivers/net/phy/at803x.c #define AT803X_SS_MDIX BIT(6) BIT 28 drivers/net/phy/at803x.c #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) BIT 29 drivers/net/phy/at803x.c #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) BIT 30 drivers/net/phy/at803x.c #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) BIT 31 drivers/net/phy/at803x.c #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) BIT 32 drivers/net/phy/at803x.c #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) BIT 33 drivers/net/phy/at803x.c #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) BIT 34 drivers/net/phy/at803x.c #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) BIT 35 drivers/net/phy/at803x.c #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) BIT 36 drivers/net/phy/at803x.c #define AT803X_INTR_ENABLE_WOL BIT(0) BIT 60 drivers/net/phy/at803x.c #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) BIT 63 drivers/net/phy/at803x.c #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) BIT 23 drivers/net/phy/bcm7xxx.c #define MII_BCM7XXX_64CLK_MDIO BIT(12) BIT 25 drivers/net/phy/bcm7xxx.c #define MII_BCM7XXX_SHD_MODE_2 BIT(2) BIT 33 drivers/net/phy/bcm7xxx.c #define MII_BCM7XXX_AN_NULL_MSG_EN BIT(0) BIT 34 drivers/net/phy/bcm7xxx.c #define MII_BCM7XXX_AN_EEE_EN BIT(1) BIT 38 drivers/net/phy/bcm7xxx.c #define MII_BCM7XXX_TL4_RST_MSK (BIT(2) | BIT(1)) BIT 27 drivers/net/phy/dp83822.c #define DP83822_HW_RESET BIT(15) BIT 28 drivers/net/phy/dp83822.c #define DP83822_SW_RESET BIT(14) BIT 31 drivers/net/phy/dp83822.c #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ BIT 32 drivers/net/phy/dp83822.c #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ BIT 35 drivers/net/phy/dp83822.c #define DP83822_RX_ERR_HF_INT_EN BIT(0) BIT 36 drivers/net/phy/dp83822.c #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) BIT 37 drivers/net/phy/dp83822.c #define DP83822_ANEG_COMPLETE_INT_EN BIT(2) BIT 38 drivers/net/phy/dp83822.c #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) BIT 39 drivers/net/phy/dp83822.c #define DP83822_SPEED_CHANGED_INT_EN BIT(4) BIT 40 drivers/net/phy/dp83822.c #define DP83822_LINK_STAT_INT_EN BIT(5) BIT 41 drivers/net/phy/dp83822.c #define DP83822_ENERGY_DET_INT_EN BIT(6) BIT 42 drivers/net/phy/dp83822.c #define DP83822_LINK_QUAL_INT_EN BIT(7) BIT 45 drivers/net/phy/dp83822.c #define DP83822_JABBER_DET_INT_EN BIT(0) BIT 46 drivers/net/phy/dp83822.c #define DP83822_WOL_PKT_INT_EN BIT(1) BIT 47 drivers/net/phy/dp83822.c #define DP83822_SLEEP_MODE_INT_EN BIT(2) BIT 48 drivers/net/phy/dp83822.c #define DP83822_MDI_XOVER_INT_EN BIT(3) BIT 49 drivers/net/phy/dp83822.c #define DP83822_LB_FIFO_INT_EN BIT(4) BIT 50 drivers/net/phy/dp83822.c #define DP83822_PAGE_RX_INT_EN BIT(5) BIT 51 drivers/net/phy/dp83822.c #define DP83822_ANEG_ERR_INT_EN BIT(6) BIT 52 drivers/net/phy/dp83822.c #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) BIT 55 drivers/net/phy/dp83822.c #define DP83822_WOL_INT_EN BIT(4) BIT 56 drivers/net/phy/dp83822.c #define DP83822_WOL_INT_STAT BIT(12) BIT 70 drivers/net/phy/dp83822.c #define DP83822_WOL_MAGIC_EN BIT(0) BIT 71 drivers/net/phy/dp83822.c #define DP83822_WOL_SECURE_ON BIT(5) BIT 72 drivers/net/phy/dp83822.c #define DP83822_WOL_EN BIT(7) BIT 73 drivers/net/phy/dp83822.c #define DP83822_WOL_INDICATION_SEL BIT(8) BIT 74 drivers/net/phy/dp83822.c #define DP83822_WOL_CLR_INDICATION BIT(11) BIT 21 drivers/net/phy/dp83848.c #define DP83848_MICR_INT_OE BIT(0) /* Interrupt Output Enable */ BIT 22 drivers/net/phy/dp83848.c #define DP83848_MICR_INTEN BIT(1) /* Interrupt Enable */ BIT 25 drivers/net/phy/dp83848.c #define DP83848_MISR_RHF_INT_EN BIT(0) /* Receive Error Counter */ BIT 26 drivers/net/phy/dp83848.c #define DP83848_MISR_FHF_INT_EN BIT(1) /* False Carrier Counter */ BIT 27 drivers/net/phy/dp83848.c #define DP83848_MISR_ANC_INT_EN BIT(2) /* Auto-negotiation complete */ BIT 28 drivers/net/phy/dp83848.c #define DP83848_MISR_DUP_INT_EN BIT(3) /* Duplex Status */ BIT 29 drivers/net/phy/dp83848.c #define DP83848_MISR_SPD_INT_EN BIT(4) /* Speed status */ BIT 30 drivers/net/phy/dp83848.c #define DP83848_MISR_LINK_INT_EN BIT(5) /* Link status */ BIT 31 drivers/net/phy/dp83848.c #define DP83848_MISR_ED_INT_EN BIT(6) /* Energy detect */ BIT 32 drivers/net/phy/dp83848.c #define DP83848_MISR_LQM_INT_EN BIT(7) /* Link Quality Monitor */ BIT 30 drivers/net/phy/dp83867.c #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) BIT 43 drivers/net/phy/dp83867.c #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) BIT 45 drivers/net/phy/dp83867.c #define DP83867_SW_RESET BIT(15) BIT 46 drivers/net/phy/dp83867.c #define DP83867_SW_RESTART BIT(14) BIT 49 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) BIT 50 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) BIT 51 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) BIT 52 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) BIT 53 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) BIT 54 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) BIT 55 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) BIT 56 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) BIT 57 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_WOL_INT_EN BIT(3) BIT 58 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) BIT 59 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) BIT 60 drivers/net/phy/dp83867.c #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) BIT 63 drivers/net/phy/dp83867.c #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) BIT 64 drivers/net/phy/dp83867.c #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) BIT 67 drivers/net/phy/dp83867.c #define DP83867_SGMII_TYPE BIT(14) BIT 70 drivers/net/phy/dp83867.c #define DP83867_STRAP_STS1_RESERVED BIT(11) BIT 77 drivers/net/phy/dp83867.c #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) BIT 78 drivers/net/phy/dp83867.c #define DP83867_STRAP_STS2_STRAP_FLD BIT(10) BIT 84 drivers/net/phy/dp83867.c #define DP83867_PHYCR_RESERVED_MASK BIT(11) BIT 85 drivers/net/phy/dp83867.c #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) BIT 97 drivers/net/phy/dp83867.c #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) BIT 102 drivers/net/phy/dp83867.c #define DP83867_CFG3_INT_OE BIT(7) BIT 103 drivers/net/phy/dp83867.c #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9) BIT 106 drivers/net/phy/dp83867.c #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) BIT 324 drivers/net/phy/dp83867.c BIT(7)); BIT 27 drivers/net/phy/dp83tc811.c #define DP83811_HW_RESET BIT(15) BIT 28 drivers/net/phy/dp83tc811.c #define DP83811_SW_RESET BIT(14) BIT 31 drivers/net/phy/dp83tc811.c #define DP83811_RX_ERR_HF_INT_EN BIT(0) BIT 32 drivers/net/phy/dp83tc811.c #define DP83811_MS_TRAINING_INT_EN BIT(1) BIT 33 drivers/net/phy/dp83tc811.c #define DP83811_ANEG_COMPLETE_INT_EN BIT(2) BIT 34 drivers/net/phy/dp83tc811.c #define DP83811_ESD_EVENT_INT_EN BIT(3) BIT 35 drivers/net/phy/dp83tc811.c #define DP83811_WOL_INT_EN BIT(4) BIT 36 drivers/net/phy/dp83tc811.c #define DP83811_LINK_STAT_INT_EN BIT(5) BIT 37 drivers/net/phy/dp83tc811.c #define DP83811_ENERGY_DET_INT_EN BIT(6) BIT 38 drivers/net/phy/dp83tc811.c #define DP83811_LINK_QUAL_INT_EN BIT(7) BIT 41 drivers/net/phy/dp83tc811.c #define DP83811_JABBER_DET_INT_EN BIT(0) BIT 42 drivers/net/phy/dp83tc811.c #define DP83811_POLARITY_INT_EN BIT(1) BIT 43 drivers/net/phy/dp83tc811.c #define DP83811_SLEEP_MODE_INT_EN BIT(2) BIT 44 drivers/net/phy/dp83tc811.c #define DP83811_OVERTEMP_INT_EN BIT(3) BIT 45 drivers/net/phy/dp83tc811.c #define DP83811_OVERVOLTAGE_INT_EN BIT(6) BIT 46 drivers/net/phy/dp83tc811.c #define DP83811_UNDERVOLTAGE_INT_EN BIT(7) BIT 49 drivers/net/phy/dp83tc811.c #define DP83811_LPS_INT_EN BIT(0) BIT 50 drivers/net/phy/dp83tc811.c #define DP83811_NO_FRAME_INT_EN BIT(3) BIT 51 drivers/net/phy/dp83tc811.c #define DP83811_POR_DONE_INT_EN BIT(4) BIT 65 drivers/net/phy/dp83tc811.c #define DP83811_WOL_MAGIC_EN BIT(0) BIT 66 drivers/net/phy/dp83tc811.c #define DP83811_WOL_SECURE_ON BIT(5) BIT 67 drivers/net/phy/dp83tc811.c #define DP83811_WOL_EN BIT(7) BIT 68 drivers/net/phy/dp83tc811.c #define DP83811_WOL_INDICATION_SEL BIT(8) BIT 69 drivers/net/phy/dp83tc811.c #define DP83811_WOL_CLR_INDICATION BIT(11) BIT 72 drivers/net/phy/dp83tc811.c #define DP83811_TDR_AUTO BIT(8) BIT 73 drivers/net/phy/dp83tc811.c #define DP83811_SGMII_EN BIT(12) BIT 74 drivers/net/phy/dp83tc811.c #define DP83811_SGMII_AUTO_NEG_EN BIT(13) BIT 75 drivers/net/phy/dp83tc811.c #define DP83811_SGMII_TX_ERR_DIS BIT(14) BIT 76 drivers/net/phy/dp83tc811.c #define DP83811_SGMII_SOFT_RESET BIT(15) BIT 35 drivers/net/phy/icplus.c #define IP1001_RXPHASE_SEL BIT(0) /* Add delay on RX_CLK */ BIT 36 drivers/net/phy/icplus.c #define IP1001_TXPHASE_SEL BIT(1) /* Add delay on TX_CLK */ BIT 39 drivers/net/phy/icplus.c #define IP101A_G_APS_ON BIT(1) /* IP101A/G APS Mode bit */ BIT 41 drivers/net/phy/icplus.c #define IP101A_G_IRQ_PIN_USED BIT(15) /* INTR pin used */ BIT 42 drivers/net/phy/icplus.c #define IP101A_G_IRQ_ALL_MASK BIT(11) /* IRQ's inactive */ BIT 43 drivers/net/phy/icplus.c #define IP101A_G_IRQ_SPEED_CHANGE BIT(2) BIT 44 drivers/net/phy/icplus.c #define IP101A_G_IRQ_DUPLEX_CHANGE BIT(1) BIT 45 drivers/net/phy/icplus.c #define IP101A_G_IRQ_LINK_CHANGE BIT(0) BIT 48 drivers/net/phy/icplus.c #define IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32 BIT(2) BIT 15 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */ BIT 16 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_MSRE BIT(14) BIT 17 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_NPRX BIT(13) BIT 18 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_NPTX BIT(12) BIT 19 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */ BIT 20 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */ BIT 21 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_ADSC BIT(5) /* Link auto-downspeed detect */ BIT 22 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_MPIPC BIT(4) BIT 23 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_MDIXC BIT(3) BIT 24 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_DXMC BIT(2) /* Duplex mode change */ BIT 25 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_LSPC BIT(1) /* Link speed change */ BIT 26 drivers/net/phy/intel-xway.c #define XWAY_MDIO_INIT_LSTC BIT(0) /* Link state change */ BIT 30 drivers/net/phy/intel-xway.c #define ADVERTISED_MPD BIT(10) /* Multi-port device */ BIT 55 drivers/net/phy/marvell.c #define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11) BIT 66 drivers/net/phy/marvell.c #define MII_M1111_RGMII_RX_DELAY BIT(7) BIT 67 drivers/net/phy/marvell.c #define MII_M1111_RGMII_TX_DELAY BIT(1) BIT 76 drivers/net/phy/marvell.c #define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13) BIT 77 drivers/net/phy/marvell.c #define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15) BIT 80 drivers/net/phy/marvell.c #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5) BIT 81 drivers/net/phy/marvell.c #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4) BIT 82 drivers/net/phy/marvell.c #define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4)) BIT 87 drivers/net/phy/marvell.c #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7) BIT 88 drivers/net/phy/marvell.c #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6) BIT 89 drivers/net/phy/marvell.c #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5) BIT 101 drivers/net/phy/marvell.c #define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9) BIT 105 drivers/net/phy/marvell.c #define MII_88E6390_MISC_TEST_SAMPLE_10MS BIT(14) BIT 106 drivers/net/phy/marvell.c #define MII_88E6390_MISC_TEST_SAMPLE_DISABLE BIT(15) BIT 115 drivers/net/phy/marvell.c #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6) BIT 120 drivers/net/phy/marvell.c #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7) BIT 124 drivers/net/phy/marvell.c #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15) BIT 125 drivers/net/phy/marvell.c #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7) BIT 126 drivers/net/phy/marvell.c #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11) BIT 134 drivers/net/phy/marvell.c #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12) BIT 135 drivers/net/phy/marvell.c #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14) BIT 35 drivers/net/phy/marvell10g.c MV_PMA_BOOT_FATAL = BIT(0), BIT 17 drivers/net/phy/mdio-aspeed.c #define ASPEED_MDIO_CTRL_FIRE BIT(31) BIT 18 drivers/net/phy/mdio-aspeed.c #define ASPEED_MDIO_CTRL_ST BIT(28) BIT 30 drivers/net/phy/mdio-aspeed.c #define ASPEED_MDIO_DATA_MDIO_EDGE BIT(23) BIT 32 drivers/net/phy/mdio-aspeed.c #define ASPEED_MDIO_DATA_IDLE BIT(16) BIT 48 drivers/net/phy/mdio-bcm-iproc.c if ((val & BIT(MII_CTRL_BUSY_SHIFT)) == 0) BIT 62 drivers/net/phy/mdio-bcm-iproc.c BIT(MII_CTRL_PRE_SHIFT); BIT 80 drivers/net/phy/mdio-bcm-iproc.c BIT(MII_DATA_SB_SHIFT) | BIT 109 drivers/net/phy/mdio-bcm-iproc.c BIT(MII_DATA_SB_SHIFT) | BIT 18 drivers/net/phy/mdio-hisi-femac.c #define MDIO_WRITE BIT(13) BIT 19 drivers/net/phy/mdio-hisi-femac.c #define MDIO_RW_FINISH BIT(15) BIT 21 drivers/net/phy/mdio-moxart.c #define MIIWR BIT(27) /* init write sequence (auto cleared)*/ BIT 22 drivers/net/phy/mdio-moxart.c #define MIIRD BIT(26) BIT 19 drivers/net/phy/mdio-mscc-miim.c #define MSCC_MIIM_STATUS_STAT_BUSY BIT(3) BIT 21 drivers/net/phy/mdio-mscc-miim.c #define MSCC_MIIM_CMD_OPR_WRITE BIT(1) BIT 22 drivers/net/phy/mdio-mscc-miim.c #define MSCC_MIIM_CMD_OPR_READ BIT(2) BIT 26 drivers/net/phy/mdio-mscc-miim.c #define MSCC_MIIM_CMD_VLD BIT(31) BIT 28 drivers/net/phy/mdio-mscc-miim.c #define MSCC_MIIM_DATA_ERROR (BIT(16) | BIT(17)) BIT 31 drivers/net/phy/mdio-mscc-miim.c #define PHY_CFG_PHY_ENA (BIT(0) | BIT(1) | BIT(2) | BIT(3)) BIT 32 drivers/net/phy/mdio-mscc-miim.c #define PHY_CFG_PHY_COMMON_RESET BIT(4) BIT 33 drivers/net/phy/mdio-mscc-miim.c #define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8)) BIT 63 drivers/net/phy/mdio-mux-bcm-iproc.c val |= BIT(MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR); BIT 122 drivers/net/phy/mdio-mux-bcm-iproc.c param |= BIT(MDIO_PARAM_C45_SEL); BIT 19 drivers/net/phy/mdio-mux-meson-g12a.c #define PLL_CTL0_LOCK_DIG BIT(30) BIT 20 drivers/net/phy/mdio-mux-meson-g12a.c #define PLL_CTL0_RST BIT(29) BIT 21 drivers/net/phy/mdio-mux-meson-g12a.c #define PLL_CTL0_EN BIT(28) BIT 22 drivers/net/phy/mdio-mux-meson-g12a.c #define PLL_CTL0_SEL BIT(23) BIT 43 drivers/net/phy/mdio-mux-meson-g12a.c #define PHY_CNTL1_CLK_EN BIT(16) BIT 44 drivers/net/phy/mdio-mux-meson-g12a.c #define PHY_CNTL1_CLKFREQ BIT(17) BIT 45 drivers/net/phy/mdio-mux-meson-g12a.c #define PHY_CNTL1_PHY_ENB BIT(18) BIT 47 drivers/net/phy/mdio-mux-meson-g12a.c #define PHY_CNTL2_USE_INTERNAL BIT(5) BIT 48 drivers/net/phy/mdio-mux-meson-g12a.c #define PHY_CNTL2_SMI_SRC_MAC BIT(6) BIT 49 drivers/net/phy/mdio-mux-meson-g12a.c #define PHY_CNTL2_RX_CLK_EPHY BIT(9) BIT 132 drivers/net/phy/mdio-mux-mmioreg.c if (be32_to_cpup(iprop) >= BIT(s->iosize * 8)) { BIT 33 drivers/net/phy/mdio-xgene.h #define SOFT_RESET BIT(31) BIT 62 drivers/net/phy/mdio-xgene.h #define HSTLDCMD BIT(3) BIT 66 drivers/net/phy/mdio-xgene.h #define BUSY_MASK BIT(0) BIT 67 drivers/net/phy/mdio-xgene.h #define READ_CYCLE_MASK BIT(0) BIT 70 drivers/net/phy/mdio-xgene.h XGENE_ENET_WR_CMD = BIT(31), BIT 71 drivers/net/phy/mdio-xgene.h XGENE_ENET_RD_CMD = BIT(30) BIT 18 drivers/net/phy/meson-gxl.c #define TSTCNTL_READ BIT(15) BIT 19 drivers/net/phy/meson-gxl.c #define TSTCNTL_WRITE BIT(14) BIT 21 drivers/net/phy/meson-gxl.c #define TSTCNTL_TEST_MODE BIT(10) BIT 27 drivers/net/phy/meson-gxl.c #define INTSRC_ANEG_PR BIT(1) BIT 28 drivers/net/phy/meson-gxl.c #define INTSRC_PARALLEL_FAULT BIT(2) BIT 29 drivers/net/phy/meson-gxl.c #define INTSRC_ANEG_LP_ACK BIT(3) BIT 30 drivers/net/phy/meson-gxl.c #define INTSRC_LINK_DOWN BIT(4) BIT 31 drivers/net/phy/meson-gxl.c #define INTSRC_REMOTE_FAULT BIT(5) BIT 32 drivers/net/phy/meson-gxl.c #define INTSRC_ANEG_COMPLETE BIT(6) BIT 41 drivers/net/phy/meson-gxl.c #define LPI_STATUS_RSV12 BIT(12) BIT 32 drivers/net/phy/micrel.c #define KSZPHY_OMSO_FACTORY_TEST BIT(15) BIT 33 drivers/net/phy/micrel.c #define KSZPHY_OMSO_B_CAST_OFF BIT(9) BIT 34 drivers/net/phy/micrel.c #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) BIT 35 drivers/net/phy/micrel.c #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) BIT 36 drivers/net/phy/micrel.c #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) BIT 40 drivers/net/phy/micrel.c #define KSZPHY_INTCS_JABBER BIT(15) BIT 41 drivers/net/phy/micrel.c #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) BIT 42 drivers/net/phy/micrel.c #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) BIT 43 drivers/net/phy/micrel.c #define KSZPHY_INTCS_PARELLEL BIT(12) BIT 44 drivers/net/phy/micrel.c #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) BIT 45 drivers/net/phy/micrel.c #define KSZPHY_INTCS_LINK_DOWN BIT(10) BIT 46 drivers/net/phy/micrel.c #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) BIT 47 drivers/net/phy/micrel.c #define KSZPHY_INTCS_LINK_UP BIT(8) BIT 58 drivers/net/phy/micrel.c #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) BIT 59 drivers/net/phy/micrel.c #define KSZPHY_RMII_REF_CLK_SEL BIT(7) BIT 126 drivers/net/phy/micrel.c .interrupt_level_mask = BIT(14), BIT 130 drivers/net/phy/micrel.c .interrupt_level_mask = BIT(14), BIT 499 drivers/net/phy/micrel.c #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) BIT 762 drivers/net/phy/micrel.c #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) BIT 763 drivers/net/phy/micrel.c #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) BIT 94 drivers/net/phy/mscc.c #define MSCC_PHY_CSR_CNTL_19_READ BIT(14) BIT 95 drivers/net/phy/mscc.c #define MSCC_PHY_CSR_CNTL_19_CMD BIT(15) BIT 101 drivers/net/phy/mscc.c #define PHY_MCB_S6G_WRITE BIT(31) BIT 102 drivers/net/phy/mscc.c #define PHY_MCB_S6G_READ BIT(30) BIT 273 drivers/net/phy/mscc.c #define VSC8584_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \ BIT 274 drivers/net/phy/mscc.c BIT(VSC8531_LINK_1000_ACTIVITY) | \ BIT 275 drivers/net/phy/mscc.c BIT(VSC8531_LINK_100_ACTIVITY) | \ BIT 276 drivers/net/phy/mscc.c BIT(VSC8531_LINK_10_ACTIVITY) | \ BIT 277 drivers/net/phy/mscc.c BIT(VSC8531_LINK_100_1000_ACTIVITY) | \ BIT 278 drivers/net/phy/mscc.c BIT(VSC8531_LINK_10_1000_ACTIVITY) | \ BIT 279 drivers/net/phy/mscc.c BIT(VSC8531_LINK_10_100_ACTIVITY) | \ BIT 280 drivers/net/phy/mscc.c BIT(VSC8584_LINK_100FX_1000X_ACTIVITY) | \ BIT 281 drivers/net/phy/mscc.c BIT(VSC8531_DUPLEX_COLLISION) | \ BIT 282 drivers/net/phy/mscc.c BIT(VSC8531_COLLISION) | \ BIT 283 drivers/net/phy/mscc.c BIT(VSC8531_ACTIVITY) | \ BIT 284 drivers/net/phy/mscc.c BIT(VSC8584_100FX_1000X_ACTIVITY) | \ BIT 285 drivers/net/phy/mscc.c BIT(VSC8531_AUTONEG_FAULT) | \ BIT 286 drivers/net/phy/mscc.c BIT(VSC8531_SERIAL_MODE) | \ BIT 287 drivers/net/phy/mscc.c BIT(VSC8531_FORCE_LED_OFF) | \ BIT 288 drivers/net/phy/mscc.c BIT(VSC8531_FORCE_LED_ON)) BIT 290 drivers/net/phy/mscc.c #define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \ BIT 291 drivers/net/phy/mscc.c BIT(VSC8531_LINK_1000_ACTIVITY) | \ BIT 292 drivers/net/phy/mscc.c BIT(VSC8531_LINK_100_ACTIVITY) | \ BIT 293 drivers/net/phy/mscc.c BIT(VSC8531_LINK_10_ACTIVITY) | \ BIT 294 drivers/net/phy/mscc.c BIT(VSC8531_LINK_100_1000_ACTIVITY) | \ BIT 295 drivers/net/phy/mscc.c BIT(VSC8531_LINK_10_1000_ACTIVITY) | \ BIT 296 drivers/net/phy/mscc.c BIT(VSC8531_LINK_10_100_ACTIVITY) | \ BIT 297 drivers/net/phy/mscc.c BIT(VSC8531_DUPLEX_COLLISION) | \ BIT 298 drivers/net/phy/mscc.c BIT(VSC8531_COLLISION) | \ BIT 299 drivers/net/phy/mscc.c BIT(VSC8531_ACTIVITY) | \ BIT 300 drivers/net/phy/mscc.c BIT(VSC8531_AUTONEG_FAULT) | \ BIT 301 drivers/net/phy/mscc.c BIT(VSC8531_SERIAL_MODE) | \ BIT 302 drivers/net/phy/mscc.c BIT(VSC8531_FORCE_LED_OFF) | \ BIT 303 drivers/net/phy/mscc.c BIT(VSC8531_FORCE_LED_ON)) BIT 752 drivers/net/phy/mscc.c if (!err && !(BIT(led_mode) & priv->supp_led_modes)) { BIT 1824 drivers/net/phy/mscc.c reg |= BIT(15); BIT 1835 drivers/net/phy/mscc.c reg &= ~BIT(15); BIT 2098 drivers/net/phy/mscc.c } while (time_before(jiffies, deadline) && (reg & BIT(12))); BIT 2100 drivers/net/phy/mscc.c if (reg & BIT(12)) { BIT 2125 drivers/net/phy/mscc.c } while (time_before(jiffies, deadline) && !(reg & BIT(8))); BIT 2127 drivers/net/phy/mscc.c if (!(reg & BIT(8))) { BIT 108 drivers/net/phy/national.c u16 lb_dis = BIT(1); BIT 20 drivers/net/phy/nxp-tja11xx.c #define MII_ECTRL_LINK_CONTROL BIT(15) BIT 25 drivers/net/phy/nxp-tja11xx.c #define MII_ECTRL_CONFIG_EN BIT(2) BIT 26 drivers/net/phy/nxp-tja11xx.c #define MII_ECTRL_WAKE_REQUEST BIT(0) BIT 29 drivers/net/phy/nxp-tja11xx.c #define MII_CFG1_AUTO_OP BIT(14) BIT 30 drivers/net/phy/nxp-tja11xx.c #define MII_CFG1_SLEEP_CONFIRM BIT(6) BIT 33 drivers/net/phy/nxp-tja11xx.c #define MII_CFG1_LED_ENABLE BIT(3) BIT 40 drivers/net/phy/nxp-tja11xx.c #define MII_INTSRC_TEMP_ERR BIT(1) BIT 41 drivers/net/phy/nxp-tja11xx.c #define MII_INTSRC_UV_ERR BIT(3) BIT 44 drivers/net/phy/nxp-tja11xx.c #define MII_COMMSTAT_LINK_UP BIT(15) BIT 47 drivers/net/phy/nxp-tja11xx.c #define MII_GENSTAT_PLL_LOCKED BIT(14) BIT 50 drivers/net/phy/nxp-tja11xx.c #define MII_COMMCFG_AUTO_OP BIT(15) BIT 66 drivers/net/phy/nxp-tja11xx.c { "phy_polarity_detect", 25, 6, BIT(6) }, BIT 67 drivers/net/phy/nxp-tja11xx.c { "phy_open_detect", 25, 7, BIT(7) }, BIT 68 drivers/net/phy/nxp-tja11xx.c { "phy_short_detect", 25, 8, BIT(8) }, BIT 238 drivers/net/phy/phy-c45.c mmd_mask &= ~BIT(devad); BIT 152 drivers/net/phy/phy.c if (phydev->is_c45 && !(phydev->c45_ids.devices_in_package & BIT(0))) BIT 514 drivers/net/phy/phy.c if (phydev->is_c45 && !(phydev->c45_ids.devices_in_package & BIT(0))) BIT 692 drivers/net/phy/phy_device.c *devices_in_package &= ~BIT(0); BIT 16 drivers/net/phy/realtek.c #define RTL821x_PHYSR_DUPLEX BIT(13) BIT 21 drivers/net/phy/realtek.c #define RTL8211E_INER_LINK_STATUS BIT(10) BIT 22 drivers/net/phy/realtek.c #define RTL8211F_INER_LINK_STATUS BIT(4) BIT 31 drivers/net/phy/realtek.c #define RTL8211F_TX_DELAY BIT(8) BIT 32 drivers/net/phy/realtek.c #define RTL8211E_TX_DELAY BIT(1) BIT 33 drivers/net/phy/realtek.c #define RTL8211E_RX_DELAY BIT(2) BIT 34 drivers/net/phy/realtek.c #define RTL8211E_MODE_MII_GMII BIT(3) BIT 40 drivers/net/phy/realtek.c #define RTL8366RB_POWER_SAVE_ON BIT(12) BIT 42 drivers/net/phy/realtek.c #define RTL_SUPPORTS_5000FULL BIT(14) BIT 43 drivers/net/phy/realtek.c #define RTL_SUPPORTS_2500FULL BIT(13) BIT 44 drivers/net/phy/realtek.c #define RTL_SUPPORTS_10000FULL BIT(0) BIT 45 drivers/net/phy/realtek.c #define RTL_ADV_2500FULL BIT(7) BIT 46 drivers/net/phy/realtek.c #define RTL_LPADV_10000FULL BIT(11) BIT 47 drivers/net/phy/realtek.c #define RTL_LPADV_5000FULL BIT(6) BIT 48 drivers/net/phy/realtek.c #define RTL_LPADV_2500FULL BIT(5) BIT 98 drivers/net/phy/realtek.c val = BIT(13) | BIT(12) | BIT(11); BIT 260 drivers/net/phy/realtek.c phy_write(phydev, MII_MMD_DATA, BIT(9)); BIT 28 drivers/net/phy/rockchip.c #define MII_AUTO_MDIX_EN BIT(7) BIT 29 drivers/net/phy/rockchip.c #define MII_MDIX_EN BIT(6) BIT 31 drivers/net/phy/rockchip.c #define MII_SPEED_10 BIT(2) BIT 32 drivers/net/phy/rockchip.c #define MII_SPEED_100 BIT(3) BIT 34 drivers/net/phy/rockchip.c #define TSTCNTL_RD (BIT(15) | BIT(10)) BIT 35 drivers/net/phy/rockchip.c #define TSTCNTL_WR (BIT(14) | BIT(10)) BIT 31 drivers/net/phy/sfp.c SFP_F_PRESENT = BIT(GPIO_MODDEF0), BIT 32 drivers/net/phy/sfp.c SFP_F_LOS = BIT(GPIO_LOS), BIT 33 drivers/net/phy/sfp.c SFP_F_TX_FAULT = BIT(GPIO_TX_FAULT), BIT 34 drivers/net/phy/sfp.c SFP_F_TX_DISABLE = BIT(GPIO_TX_DISABLE), BIT 35 drivers/net/phy/sfp.c SFP_F_RATE_SELECT = BIT(GPIO_RATE_SELECT), BIT 252 drivers/net/phy/sfp.c state |= BIT(i); BIT 1423 drivers/net/phy/sfp.c val |= BIT(0); BIT 1794 drivers/net/phy/sfp.c if (changed & BIT(i)) BIT 1796 drivers/net/phy/sfp.c !!(sfp->state & BIT(i)), !!(state & BIT(i))); BIT 1935 drivers/net/phy/sfp.c if (sff->gpios & BIT(i)) { BIT 34 drivers/net/thunderbolt.c #define TBNET_MATCH_FRAGS_ID BIT(1) BIT 865 drivers/net/thunderbolt.c sof_mask = BIT(TBIP_PDF_FRAME_START); BIT 866 drivers/net/thunderbolt.c eof_mask = BIT(TBIP_PDF_FRAME_END); BIT 550 drivers/net/usb/aqc111.c m_filter[crc_bits >> 3] |= BIT(crc_bits & 7); BIT 133 drivers/net/usb/aqc111.h #define AQ_ADV_100M BIT(0) BIT 134 drivers/net/usb/aqc111.h #define AQ_ADV_1G BIT(1) BIT 135 drivers/net/usb/aqc111.h #define AQ_ADV_2G5 BIT(2) BIT 136 drivers/net/usb/aqc111.h #define AQ_ADV_5G BIT(3) BIT 139 drivers/net/usb/aqc111.h #define AQ_PAUSE BIT(16) BIT 140 drivers/net/usb/aqc111.h #define AQ_ASYM_PAUSE BIT(17) BIT 141 drivers/net/usb/aqc111.h #define AQ_LOW_POWER BIT(18) BIT 142 drivers/net/usb/aqc111.h #define AQ_PHY_POWER_EN BIT(19) BIT 143 drivers/net/usb/aqc111.h #define AQ_WOL BIT(20) BIT 144 drivers/net/usb/aqc111.h #define AQ_DOWNSHIFT BIT(21) BIT 187 drivers/net/usb/aqc111.h #define AQ_TX_DESC_DROP_PADD BIT(28) BIT 188 drivers/net/usb/aqc111.h #define AQ_TX_DESC_VLAN BIT(29) BIT 197 drivers/net/usb/aqc111.h #define AQ_RX_PD_L4_ERR BIT(0) BIT 198 drivers/net/usb/aqc111.h #define AQ_RX_PD_L3_ERR BIT(1) BIT 206 drivers/net/usb/aqc111.h #define AQ_RX_PD_VLAN BIT(10) BIT 207 drivers/net/usb/aqc111.h #define AQ_RX_PD_RX_OK BIT(11) BIT 208 drivers/net/usb/aqc111.h #define AQ_RX_PD_DROP BIT(31) BIT 75 drivers/net/usb/asix.h #define AX_PHY_SELECT_MASK (BIT(3) | BIT(2)) BIT 77 drivers/net/usb/asix.h #define AX_PHY_SELECT_EXTERNAL BIT(2) BIT 22 drivers/net/usb/ax88179_178a.c #define AX_INT_PPLS_LINK ((u32)BIT(16)) BIT 28 drivers/net/usb/ax88179_178a.c #define AX_RXHDR_CRC_ERR ((u32)BIT(29)) BIT 29 drivers/net/usb/ax88179_178a.c #define AX_RXHDR_DROP_ERR ((u32)BIT(31)) BIT 124 drivers/net/usb/ax88179_178a.c #define GMII_LED0_ACTIVE BIT(4) BIT 125 drivers/net/usb/ax88179_178a.c #define GMII_LED1_ACTIVE BIT(5) BIT 126 drivers/net/usb/ax88179_178a.c #define GMII_LED2_ACTIVE BIT(6) BIT 130 drivers/net/usb/ax88179_178a.c #define GMII_LED0_LINK_10 BIT(0) BIT 131 drivers/net/usb/ax88179_178a.c #define GMII_LED0_LINK_100 BIT(1) BIT 132 drivers/net/usb/ax88179_178a.c #define GMII_LED0_LINK_1000 BIT(2) BIT 133 drivers/net/usb/ax88179_178a.c #define GMII_LED1_LINK_10 BIT(4) BIT 134 drivers/net/usb/ax88179_178a.c #define GMII_LED1_LINK_100 BIT(5) BIT 135 drivers/net/usb/ax88179_178a.c #define GMII_LED1_LINK_1000 BIT(6) BIT 136 drivers/net/usb/ax88179_178a.c #define GMII_LED2_LINK_10 BIT(8) BIT 137 drivers/net/usb/ax88179_178a.c #define GMII_LED2_LINK_100 BIT(9) BIT 138 drivers/net/usb/ax88179_178a.c #define GMII_LED2_LINK_1000 BIT(10) BIT 139 drivers/net/usb/ax88179_178a.c #define LED0_ACTIVE BIT(0) BIT 140 drivers/net/usb/ax88179_178a.c #define LED0_LINK_10 BIT(1) BIT 141 drivers/net/usb/ax88179_178a.c #define LED0_LINK_100 BIT(2) BIT 142 drivers/net/usb/ax88179_178a.c #define LED0_LINK_1000 BIT(3) BIT 143 drivers/net/usb/ax88179_178a.c #define LED0_FD BIT(4) BIT 145 drivers/net/usb/ax88179_178a.c #define LED1_ACTIVE BIT(5) BIT 146 drivers/net/usb/ax88179_178a.c #define LED1_LINK_10 BIT(6) BIT 147 drivers/net/usb/ax88179_178a.c #define LED1_LINK_100 BIT(7) BIT 148 drivers/net/usb/ax88179_178a.c #define LED1_LINK_1000 BIT(8) BIT 149 drivers/net/usb/ax88179_178a.c #define LED1_FD BIT(9) BIT 151 drivers/net/usb/ax88179_178a.c #define LED2_ACTIVE BIT(10) BIT 152 drivers/net/usb/ax88179_178a.c #define LED2_LINK_1000 BIT(13) BIT 153 drivers/net/usb/ax88179_178a.c #define LED2_LINK_100 BIT(12) BIT 154 drivers/net/usb/ax88179_178a.c #define LED2_LINK_10 BIT(11) BIT 155 drivers/net/usb/ax88179_178a.c #define LED2_FD BIT(14) BIT 156 drivers/net/usb/ax88179_178a.c #define LED_VALID BIT(15) BIT 145 drivers/net/usb/cdc_eem.c put_unaligned_le16(BIT(14) | len, skb_push(skb, 2)); BIT 190 drivers/net/usb/cdc_eem.c if (header & BIT(15)) { BIT 200 drivers/net/usb/cdc_eem.c if (header & BIT(14)) { BIT 221 drivers/net/usb/cdc_eem.c put_unaligned_le16(BIT(15) | (1 << 11) | len, BIT 301 drivers/net/usb/cdc_eem.c if (header & BIT(14)) { BIT 1909 drivers/net/usb/lan78xx.c data->irqenable &= ~BIT(irqd_to_hwirq(irqd)); BIT 1916 drivers/net/usb/lan78xx.c data->irqenable |= BIT(irqd_to_hwirq(irqd)); BIT 14 drivers/net/usb/lan78xx.h #define INT_ENP_EEE_START_TX_LPI_INT BIT(26) BIT 15 drivers/net/usb/lan78xx.h #define INT_ENP_EEE_STOP_TX_LPI_INT BIT(25) BIT 16 drivers/net/usb/lan78xx.h #define INT_ENP_EEE_RX_LPI_INT BIT(24) BIT 17 drivers/net/usb/lan78xx.h #define INT_ENP_RDFO_INT BIT(22) BIT 18 drivers/net/usb/lan78xx.h #define INT_ENP_TXE_INT BIT(21) BIT 19 drivers/net/usb/lan78xx.h #define INT_ENP_TX_DIS_INT BIT(19) BIT 20 drivers/net/usb/lan78xx.h #define INT_ENP_RX_DIS_INT BIT(18) BIT 21 drivers/net/usb/lan78xx.h #define INT_ENP_PHY_INT BIT(17) BIT 22 drivers/net/usb/lan78xx.h #define INT_ENP_DP_INT BIT(16) BIT 23 drivers/net/usb/lan78xx.h #define INT_ENP_MAC_ERR_INT BIT(15) BIT 24 drivers/net/usb/lan78xx.h #define INT_ENP_TDFU_INT BIT(14) BIT 25 drivers/net/usb/lan78xx.h #define INT_ENP_TDFO_INT BIT(13) BIT 26 drivers/net/usb/lan78xx.h #define INT_ENP_UTX_FP_INT BIT(12) BIT 285 drivers/net/usb/r8152.c #define EFUSE_READ_CMD BIT(15) BIT 286 drivers/net/usb/r8152.c #define EFUSE_DATA_BIT16 BIT(7) BIT 293 drivers/net/usb/r8152.c #define LANWAKE_CLR_EN BIT(0) BIT 307 drivers/net/usb/r8152.c #define TEST_IO_OFF BIT(4) BIT 317 drivers/net/usb/r8152.c #define MAC_CLK_SPDWN_EN BIT(15) BIT 320 drivers/net/usb/r8152.c #define PLA_MCU_SPDWN_EN BIT(14) BIT 352 drivers/net/usb/r8152.c #define LANWAKE_PIN BIT(7) BIT 355 drivers/net/usb/r8152.c #define LINK_CHG_EVENT BIT(0) BIT 358 drivers/net/usb/r8152.c #define UPCOMING_RUNTIME_D3 BIT(0) BIT 361 drivers/net/usb/r8152.c #define LINK_CHANGE_FLAG BIT(8) BIT 368 drivers/net/usb/r8152.c #define DELAY_PHY_PWR_CHG BIT(1) BIT 386 drivers/net/usb/r8152.c #define LPM_U1U2_EN BIT(0) BIT 406 drivers/net/usb/r8152.c #define OWN_UPDATE BIT(0) BIT 407 drivers/net/usb/r8152.c #define OWN_CLEAR BIT(1) BIT 425 drivers/net/usb/r8152.c #define UPS_EN BIT(4) BIT 426 drivers/net/usb/r8152.c #define USP_PREWAKE BIT(5) BIT 457 drivers/net/usb/r8152.c #define UPS_FLAGS_R_TUNE BIT(0) BIT 458 drivers/net/usb/r8152.c #define UPS_FLAGS_EN_10M_CKDIV BIT(1) BIT 459 drivers/net/usb/r8152.c #define UPS_FLAGS_250M_CKDIV BIT(2) BIT 460 drivers/net/usb/r8152.c #define UPS_FLAGS_EN_ALDPS BIT(3) BIT 461 drivers/net/usb/r8152.c #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) BIT 463 drivers/net/usb/r8152.c #define UPS_FLAGS_EN_EEE BIT(20) BIT 464 drivers/net/usb/r8152.c #define UPS_FLAGS_EN_500M_EEE BIT(21) BIT 465 drivers/net/usb/r8152.c #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) BIT 466 drivers/net/usb/r8152.c #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23) BIT 467 drivers/net/usb/r8152.c #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) BIT 468 drivers/net/usb/r8152.c #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) BIT 469 drivers/net/usb/r8152.c #define UPS_FLAGS_EN_GREEN BIT(26) BIT 470 drivers/net/usb/r8152.c #define UPS_FLAGS_EN_FLOW_CTR BIT(27) BIT 497 drivers/net/usb/r8152.c #define PGA_RETURN_EN BIT(1) BIT 540 drivers/net/usb/r8152.c #define EN_EEE_CMODE BIT(14) BIT 541 drivers/net/usb/r8152.c #define EN_EEE_1000 BIT(13) BIT 542 drivers/net/usb/r8152.c #define EN_EEE_100 BIT(12) BIT 543 drivers/net/usb/r8152.c #define EN_10M_CLKDIV BIT(11) BIT 551 drivers/net/usb/r8152.c #define PATCH_READY BIT(6) BIT 554 drivers/net/usb/r8152.c #define PATCH_REQUEST BIT(4) BIT 565 drivers/net/usb/r8152.c #define GREEN_ETH_EN BIT(15) BIT 566 drivers/net/usb/r8152.c #define R_TUNE_EN BIT(11) BIT 674 drivers/net/usb/r8152.c #define RD_UDP_CS BIT(23) BIT 675 drivers/net/usb/r8152.c #define RD_TCP_CS BIT(22) BIT 676 drivers/net/usb/r8152.c #define RD_IPV6_CS BIT(20) BIT 677 drivers/net/usb/r8152.c #define RD_IPV4_CS BIT(19) BIT 680 drivers/net/usb/r8152.c #define IPF BIT(23) /* IP checksum fail */ BIT 681 drivers/net/usb/r8152.c #define UDPF BIT(22) /* UDP checksum fail */ BIT 682 drivers/net/usb/r8152.c #define TCPF BIT(21) /* TCP checksum fail */ BIT 683 drivers/net/usb/r8152.c #define RX_VLAN_TAG BIT(16) BIT 692 drivers/net/usb/r8152.c #define TX_FS BIT(31) /* First segment of a packet */ BIT 693 drivers/net/usb/r8152.c #define TX_LS BIT(30) /* Final segment of a packet */ BIT 694 drivers/net/usb/r8152.c #define GTSENDV4 BIT(28) BIT 695 drivers/net/usb/r8152.c #define GTSENDV6 BIT(27) BIT 701 drivers/net/usb/r8152.c #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ BIT 702 drivers/net/usb/r8152.c #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ BIT 703 drivers/net/usb/r8152.c #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ BIT 704 drivers/net/usb/r8152.c #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ BIT 709 drivers/net/usb/r8152.c #define TX_VLAN_TAG BIT(16) BIT 825 drivers/net/usb/r8152.c #define RTL_ADVERTISED_10_HALF BIT(0) BIT 826 drivers/net/usb/r8152.c #define RTL_ADVERTISED_10_FULL BIT(1) BIT 827 drivers/net/usb/r8152.c #define RTL_ADVERTISED_100_HALF BIT(2) BIT 828 drivers/net/usb/r8152.c #define RTL_ADVERTISED_100_FULL BIT(3) BIT 829 drivers/net/usb/r8152.c #define RTL_ADVERTISED_1000_HALF BIT(4) BIT 830 drivers/net/usb/r8152.c #define RTL_ADVERTISED_1000_FULL BIT(5) BIT 3027 drivers/net/usb/r8152.c ocp_data |= BIT(0); BIT 3036 drivers/net/usb/r8152.c ocp_data &= ~BIT(0); BIT 4595 drivers/net/usb/r8152.c if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { BIT 401 drivers/net/usb/smsc75xx.h #define INT_ENP_RDFO_INT ((u32)BIT(22)) BIT 402 drivers/net/usb/smsc75xx.h #define INT_ENP_TXE_INT ((u32)BIT(21)) BIT 403 drivers/net/usb/smsc75xx.h #define INT_ENP_TX_DIS_INT ((u32)BIT(19)) BIT 404 drivers/net/usb/smsc75xx.h #define INT_ENP_RX_DIS_INT ((u32)BIT(18)) BIT 405 drivers/net/usb/smsc75xx.h #define INT_ENP_PHY_INT ((u32)BIT(17)) BIT 406 drivers/net/usb/smsc75xx.h #define INT_ENP_MAC_ERR_INT ((u32)BIT(15)) BIT 407 drivers/net/usb/smsc75xx.h #define INT_ENP_RX_FIFO_DATA_INT ((u32)BIT(12)) BIT 343 drivers/net/usb/smsc95xx.h #define INT_ENP_MAC_RTO_ ((u32)BIT(18)) /* MAC Reset Time Out */ BIT 344 drivers/net/usb/smsc95xx.h #define INT_ENP_TX_STOP_ ((u32)BIT(17)) /* TX Stopped */ BIT 345 drivers/net/usb/smsc95xx.h #define INT_ENP_RX_STOP_ ((u32)BIT(16)) /* RX Stopped */ BIT 346 drivers/net/usb/smsc95xx.h #define INT_ENP_PHY_INT_ ((u32)BIT(15)) /* PHY Interrupt */ BIT 347 drivers/net/usb/smsc95xx.h #define INT_ENP_TXE_ ((u32)BIT(14)) /* TX Error */ BIT 348 drivers/net/usb/smsc95xx.h #define INT_ENP_TDFU_ ((u32)BIT(13)) /* TX FIFO Underrun */ BIT 349 drivers/net/usb/smsc95xx.h #define INT_ENP_TDFO_ ((u32)BIT(12)) /* TX FIFO Overrun */ BIT 350 drivers/net/usb/smsc95xx.h #define INT_ENP_RXDF_ ((u32)BIT(11)) /* RX Dropped Frame */ BIT 33 drivers/net/veth.c #define VETH_XDP_FLAG BIT(0) BIT 38 drivers/net/veth.c #define VETH_XDP_TX BIT(0) BIT 39 drivers/net/veth.c #define VETH_XDP_REDIR BIT(1) BIT 44 drivers/net/virtio_net.c #define VIRTIO_XDP_TX BIT(0) BIT 45 drivers/net/virtio_net.c #define VIRTIO_XDP_REDIR BIT(1) BIT 47 drivers/net/virtio_net.c #define VIRTIO_XDP_FLAG BIT(0) BIT 1883 drivers/net/wireless/admtek/adm8211.c dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); BIT 1685 drivers/net/wireless/ath/ar5523/ar5523.c hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); BIT 91 drivers/net/wireless/ath/ath.h ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0), BIT 92 drivers/net/wireless/ath/ath.h ATH_CRYPT_CAP_MIC_COMBINED = BIT(1), BIT 47 drivers/net/wireless/ath/ath10k/ahb.h #define TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK BIT(25) BIT 29 drivers/net/wireless/ath/ath10k/ce.h #define CE_WCN3990_DESC_FLAGS_GATHER BIT(31) BIT 267 drivers/net/wireless/ath/ath10k/ce.h #define CE_ATTR_NO_SNOOP BIT(0) BIT 270 drivers/net/wireless/ath/ath10k/ce.h #define CE_ATTR_BYTE_SWAP_DATA BIT(1) BIT 273 drivers/net/wireless/ath/ath10k/ce.h #define CE_ATTR_SWIZZLE_DESCRIPTORS BIT(2) BIT 276 drivers/net/wireless/ath/ath10k/ce.h #define CE_ATTR_DIS_INTR BIT(3) BIT 279 drivers/net/wireless/ath/ath10k/ce.h #define CE_ATTR_POLL BIT(4) BIT 37 drivers/net/wireless/ath/ath10k/core.c unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) | BIT 38 drivers/net/wireless/ath/ath10k/core.c BIT(ATH10K_FW_CRASH_DUMP_CE_DATA); BIT 106 drivers/net/wireless/ath/ath10k/core.h ATH10K_SKB_F_NO_HWCRYPT = BIT(0), BIT 107 drivers/net/wireless/ath/ath10k/core.h ATH10K_SKB_F_DTIM_ZERO = BIT(1), BIT 108 drivers/net/wireless/ath/ath10k/core.h ATH10K_SKB_F_DELIVER_CAB = BIT(2), BIT 109 drivers/net/wireless/ath/ath10k/core.h ATH10K_SKB_F_MGMT = BIT(3), BIT 110 drivers/net/wireless/ath/ath10k/core.h ATH10K_SKB_F_QOS = BIT(4), BIT 111 drivers/net/wireless/ath/ath10k/core.h ATH10K_SKB_F_RAW_TX = BIT(5), BIT 56 drivers/net/wireless/ath/ath10k/debugfs_sta.c if (tid > IEEE80211_NUM_TIDS || !(ar->sta_tid_stats_mask & BIT(tid))) BIT 100 drivers/net/wireless/ath/ath10k/debugfs_sta.c if (!(ar->sta_tid_stats_mask & BIT(tid)) || non_data_frm) BIT 545 drivers/net/wireless/ath/ath10k/debugfs_sta.c if (ar->sta_tid_stats_mask & BIT(j)) { \ BIT 107 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0) BIT 108 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1) BIT 109 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2) BIT 110 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3) BIT 111 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4) BIT 119 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16) BIT 120 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17) BIT 121 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18) BIT 122 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19) BIT 123 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20) BIT 124 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21) BIT 546 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0) BIT 564 drivers/net/wireless/ath/ath10k/htt.h #define HTT_RX_INDICATION_INFO0_PPDU_DURATION BIT(7) BIT 577 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_CMPL_FLAG_DATA_RSSI BIT(0) BIT 578 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_CMPL_FLAG_PPID_PRESENT BIT(1) BIT 579 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_CMPL_FLAG_PA_PRESENT BIT(2) BIT 580 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT BIT(3) BIT 582 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_DATA_RSSI_ENABLE_WCN3990 BIT(3) BIT 583 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_DATA_APPEND_RETRIES BIT(0) BIT 584 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_DATA_APPEND_TIMESTAMP BIT(1) BIT 1046 drivers/net/wireless/ath/ath10k/htt.h #define ATH10K_IEEE80211_EXTIV BIT(5) BIT 1562 drivers/net/wireless/ath/ath10k/htt.h #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2) BIT 1563 drivers/net/wireless/ath/ath10k/htt.h #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3) BIT 1564 drivers/net/wireless/ath/ath10k/htt.h #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4) BIT 1696 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0) BIT 1159 drivers/net/wireless/ath/ath10k/htt_rx.c status->chains &= ~BIT(i); BIT 1165 drivers/net/wireless/ath/ath10k/htt_rx.c status->chains |= BIT(i); BIT 2239 drivers/net/wireless/ath/ath10k/htt_rx.c rx_status->chains |= BIT(0); BIT 67 drivers/net/wireless/ath/ath10k/htt_tx.c bit = BIT(peer_id % 32); BIT 694 drivers/net/wireless/ath/ath10k/hw.h #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) BIT 695 drivers/net/wireless/ath/ath10k/hw.h #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) BIT 734 drivers/net/wireless/ath/ath10k/hw.h #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) BIT 735 drivers/net/wireless/ath/ath10k/hw.h #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) BIT 112 drivers/net/wireless/ath/ath10k/mac.c (ath10k_mac_bitrate_is_cck(bitrate) ? BIT(7) : 0); BIT 168 drivers/net/wireless/ath/ath10k/mac.c case IEEE80211_VHT_MCS_SUPPORT_0_7: return BIT(8) - 1; BIT 169 drivers/net/wireless/ath/ath10k/mac.c case IEEE80211_VHT_MCS_SUPPORT_0_8: return BIT(9) - 1; BIT 170 drivers/net/wireless/ath/ath10k/mac.c case IEEE80211_VHT_MCS_SUPPORT_0_9: return BIT(10) - 1; BIT 2357 drivers/net/wireless/ath/ath10k/mac.c if ((ht_cap->mcs.rx_mask[i / 8] & BIT(i % 8)) && BIT 2358 drivers/net/wireless/ath/ath10k/mac.c (ht_mcs_mask[i / 8] & BIT(i % 8))) { BIT 3300 drivers/net/wireless/ath/ath10k/mac.c ar->tx_paused |= BIT(reason); BIT 3321 drivers/net/wireless/ath/ath10k/mac.c ar->tx_paused &= ~BIT(reason); BIT 3341 drivers/net/wireless/ath/ath10k/mac.c arvif->tx_paused |= BIT(reason); BIT 3352 drivers/net/wireless/ath/ath10k/mac.c arvif->tx_paused &= ~BIT(reason); BIT 4565 drivers/net/wireless/ath/ath10k/mac.c if ((i < ar->num_rf_chains) && (ar->cfg_tx_chainmask & BIT(i))) BIT 4649 drivers/net/wireless/ath/ath10k/mac.c if (ar->cfg_rx_chainmask & BIT(i)) BIT 7242 drivers/net/wireless/ath/ath10k/mac.c ht_nss_mask |= BIT(i); BIT 7252 drivers/net/wireless/ath/ath10k/mac.c vht_nss_mask |= BIT(i); BIT 7263 drivers/net/wireless/ath/ath10k/mac.c if (BIT(fls(ht_nss_mask)) - 1 != ht_nss_mask) BIT 7396 drivers/net/wireless/ath/ath10k/mac.c case BIT(8) - 1: BIT 7397 drivers/net/wireless/ath/ath10k/mac.c case BIT(9) - 1: BIT 7398 drivers/net/wireless/ath/ath10k/mac.c case BIT(10) - 1: BIT 8340 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_STATION) BIT 8341 drivers/net/wireless/ath/ath10k/mac.c | BIT(NL80211_IFTYPE_P2P_CLIENT) BIT 8345 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_P2P_GO) BIT 8349 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_P2P_DEVICE) BIT 8353 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_AP) BIT 8355 drivers/net/wireless/ath/ath10k/mac.c | BIT(NL80211_IFTYPE_MESH_POINT) BIT 8363 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_AP) BIT 8365 drivers/net/wireless/ath/ath10k/mac.c | BIT(NL80211_IFTYPE_MESH_POINT) BIT 8370 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_STATION) BIT 8393 drivers/net/wireless/ath/ath10k/mac.c .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT 8394 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_CHAN_WIDTH_20) | BIT 8395 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_CHAN_WIDTH_40) | BIT 8396 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_CHAN_WIDTH_80), BIT 8404 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_STATION), BIT 8408 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_AP) | BIT 8410 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 8412 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 8413 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_P2P_GO), BIT 8417 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_P2P_DEVICE), BIT 8424 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_STATION), BIT 8428 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_P2P_CLIENT), BIT 8432 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_AP) | BIT 8434 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 8436 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_P2P_GO), BIT 8440 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_P2P_DEVICE), BIT 8447 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_STATION), BIT 8451 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_ADHOC), BIT 8497 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_STATION), BIT 8501 drivers/net/wireless/ath/ath10k/mac.c .types = BIT(NL80211_IFTYPE_AP) BIT 8503 drivers/net/wireless/ath/ath10k/mac.c | BIT(NL80211_IFTYPE_MESH_POINT) BIT 8517 drivers/net/wireless/ath/ath10k/mac.c .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT 8518 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_CHAN_WIDTH_20) | BIT 8519 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_CHAN_WIDTH_40) | BIT 8520 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_CHAN_WIDTH_80), BIT 8535 drivers/net/wireless/ath/ath10k/mac.c .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT 8536 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_CHAN_WIDTH_20) | BIT 8537 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_CHAN_WIDTH_40) | BIT 8538 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_CHAN_WIDTH_80), BIT 8761 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_STATION) | BIT 8762 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_AP) | BIT 8763 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_MESH_POINT); BIT 8770 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_P2P_DEVICE) | BIT 8771 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 8772 drivers/net/wireless/ath/ath10k/mac.c BIT(NL80211_IFTYPE_P2P_GO); BIT 8908 drivers/net/wireless/ath/ath10k/mac.c ar->hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_ADHOC); BIT 8921 drivers/net/wireless/ath/ath10k/mac.c ar->hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_ADHOC); BIT 9009 drivers/net/wireless/ath/ath10k/mac.c ar->hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP_VLAN); BIT 9010 drivers/net/wireless/ath/ath10k/mac.c ar->hw->wiphy->software_iftypes |= BIT(NL80211_IFTYPE_AP_VLAN); BIT 35 drivers/net/wireless/ath/ath10k/qmi.c src_perms = BIT(QCOM_SCM_VMID_HLOS); BIT 66 drivers/net/wireless/ath/ath10k/qmi.c src_perms = BIT(QCOM_SCM_VMID_MSS_MSA) | BIT(QCOM_SCM_VMID_WLAN); BIT 69 drivers/net/wireless/ath/ath10k/qmi.c src_perms |= BIT(QCOM_SCM_VMID_WLAN_CE); BIT 13 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0), BIT 14 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1), BIT 15 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2), BIT 16 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3), BIT 17 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4), BIT 18 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5), BIT 19 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_NON_QOS = BIT(6), BIT 20 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_NULL_DATA = BIT(7), BIT 21 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_MGMT_TYPE = BIT(8), BIT 22 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_CTRL_TYPE = BIT(9), BIT 23 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_MORE_DATA = BIT(10), BIT 24 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_EOSP = BIT(11), BIT 25 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_U_APSD_TRIGGER = BIT(12), BIT 26 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_FRAGMENT = BIT(13), BIT 27 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_ORDER = BIT(14), BIT 28 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_CLASSIFICATION = BIT(15), BIT 29 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_OVERFLOW_ERR = BIT(16), BIT 30 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR = BIT(17), BIT 31 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = BIT(18), BIT 32 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL = BIT(19), BIT 33 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_SA_IDX_INVALID = BIT(20), BIT 34 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_DA_IDX_INVALID = BIT(21), BIT 35 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT = BIT(22), BIT 36 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT = BIT(23), BIT 37 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED = BIT(24), BIT 38 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_DIRECTED = BIT(25), BIT 39 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_BUFFER_FRAGMENT = BIT(26), BIT 40 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR = BIT(27), BIT 41 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_TKIP_MIC_ERR = BIT(28), BIT 42 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_DECRYPT_ERR = BIT(29), BIT 43 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_FCS_ERR = BIT(30), BIT 44 drivers/net/wireless/ath/ath10k/rx_desc.h RX_ATTENTION_FLAGS_MSDU_DONE = BIT(31), BIT 248 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_START_INFO0_FROM_DS BIT(11) BIT 249 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_START_INFO0_TO_DS BIT(12) BIT 250 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_START_INFO0_ENCRYPTED BIT(13) BIT 251 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_START_INFO0_RETRY BIT(14) BIT 252 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_START_INFO0_TXBF_H_INFO BIT(15) BIT 256 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_START_INFO1_DIRECTED BIT(16) BIT 351 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_END_INFO0_OVERFLOW_ERR BIT(13) BIT 352 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_END_INFO0_LAST_MPDU BIT(14) BIT 353 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_END_INFO0_POST_DELIM_ERR BIT(15) BIT 354 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR BIT(28) BIT 355 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_END_INFO0_TKIP_MIC_ERR BIT(29) BIT 356 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_END_INFO0_DECRYPT_ERR BIT(30) BIT 357 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MPDU_END_INFO0_FCS_ERR BIT(31) BIT 416 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_START_INFO1_IPV4_PROTO BIT(10) BIT 417 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_START_INFO1_IPV6_PROTO BIT(11) BIT 418 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_START_INFO1_TCP_PROTO BIT(12) BIT 419 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_START_INFO1_UDP_PROTO BIT(13) BIT 420 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_START_INFO1_IP_FRAG BIT(14) BIT 421 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_START_INFO1_TCP_ONLY_ACK BIT(15) BIT 427 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_START_INFO2_DA_BCAST_MCAST BIT(11) BIT 562 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_END_INFO0_FIRST_MSDU BIT(14) BIT 563 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_END_INFO0_LAST_MSDU BIT(15) BIT 564 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_END_INFO0_MSDU_LIMIT_ERR BIT(18) BIT 565 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_END_INFO0_PRE_DELIM_ERR BIT(30) BIT 566 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_END_INFO0_RESERVED_3B BIT(31) BIT 583 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_MSDU_END_INFO1_IRO_ELIGIBLE BIT(9) BIT 692 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_START_INFO0_IS_GREENFIELD BIT(0) BIT 702 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT BIT(4) BIT 703 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_START_INFO1_L_SIG_PARITY BIT(17) BIT 710 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_START_INFO3_TXBF_H_INFO BIT(24) BIT 719 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_START_RATE_FLAG BIT(3) BIT 899 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_FLAGS_PHY_ERR BIT(0) BIT 900 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_FLAGS_RX_LOCATION BIT(1) BIT 901 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_FLAGS_TXBF_H_INFO BIT(2) BIT 905 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK BIT(24) BIT 906 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL BIT(25) BIT 910 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_INFO1_BB_DATA BIT(0) BIT 911 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_INFO1_PEER_IDX_VALID BIT(1) BIT 912 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_INFO1_PPDU_DONE BIT(15) BIT 948 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_RTT_NORMAL_MODE BIT(31) BIT 960 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PKT_END_INFO0_RX_SUCCESS BIT(0) BIT 961 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PKT_END_INFO0_ERR_TX_INTERRUPT_RX BIT(3) BIT 962 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PKT_END_INFO0_ERR_OFDM_POWER_DROP BIT(4) BIT 963 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PKT_END_INFO0_ERR_OFDM_RESTART BIT(5) BIT 964 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PKT_END_INFO0_ERR_CCK_POWER_DROP BIT(6) BIT 965 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PKT_END_INFO0_ERR_CCK_RESTART BIT(7) BIT 975 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO_CIR_STATUS BIT(17) BIT 976 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO_RTT_MAC_PHY_PHASE BIT(25) BIT 977 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO_RTT_TX_DATA_START_X BIT(26) BIT 978 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO_HW_IFFT_MODE BIT(30) BIT 979 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO_RX_LOCATION_VALID BIT(31) BIT 999 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS BIT(14) BIT 1000 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS BIT(29) BIT 1016 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO1_RTT_CFR_STATUS BIT(0) BIT 1017 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO1_RTT_CIR_STATUS BIT(1) BIT 1018 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO1_RTT_GI_TYPE BIT(7) BIT 1019 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE BIT(29) BIT 1020 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE BIT(30) BIT 1021 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_LOCATION_INFO1_RX_LOCATION_VALID BIT(31) BIT 1035 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_RADAR = BIT(2), BIT 1036 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT = BIT(3), BIT 1037 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_RX_NAP = BIT(4), BIT 1038 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_OFDM_TIMING = BIT(5), BIT 1039 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_OFDM_PARITY = BIT(6), BIT 1040 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_OFDM_RATE = BIT(7), BIT 1041 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_OFDM_LENGTH = BIT(8), BIT 1042 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_OFDM_RESTART = BIT(9), BIT 1043 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_OFDM_SERVICE = BIT(10), BIT 1044 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_OFDM_POWER_DROP = BIT(11), BIT 1045 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_CCK_BLOCKER = BIT(12), BIT 1046 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_CCK_TIMING = BIT(13), BIT 1047 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_CCK_HEADER_CRC = BIT(14), BIT 1048 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_CCK_RATE = BIT(15), BIT 1049 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_CCK_LENGTH = BIT(16), BIT 1050 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_CCK_RESTART = BIT(17), BIT 1051 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_CCK_SERVICE = BIT(18), BIT 1052 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_CCK_POWER_DROP = BIT(19), BIT 1053 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_HT_CRC = BIT(20), BIT 1054 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_HT_LENGTH = BIT(21), BIT 1055 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_HT_RATE = BIT(22), BIT 1056 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_HT_ZLF = BIT(23), BIT 1057 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_FALSE_RADAR_EXT = BIT(24), BIT 1058 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_GREEN_FIELD = BIT(25), BIT 1059 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_SPECTRAL_SCAN = BIT(26), BIT 1060 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_RX_DYN_BW = BIT(27), BIT 1061 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_LEG_HT_MISMATCH = BIT(28), BIT 1062 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_VHT_CRC = BIT(29), BIT 1063 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_VHT_SIGA = BIT(30), BIT 1064 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO0_ERR_VHT_LSIG = BIT(31), BIT 1068 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP = BIT(0), BIT 1069 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_VHT_NSYM = BIT(1), BIT 1070 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_EXT_SYM = BIT(2), BIT 1071 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID0 = BIT(3), BIT 1072 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID1_62 = BIT(4), BIT 1073 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID63 = BIT(5), BIT 1074 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_OFDM_LDPC_DECODER = BIT(6), BIT 1075 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_DEFER_NAP = BIT(7), BIT 1076 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_FDOMAIN_TIMEOUT = BIT(8), BIT 1077 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_LSIG_REL_CHECK = BIT(9), BIT 1078 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_BT_COLLISION = BIT(10), BIT 1079 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_MU_FEEDBACK = BIT(11), BIT 1080 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_TX_INTERRUPT_RX = BIT(12), BIT 1081 drivers/net/wireless/ath/ath10k/rx_desc.h RX_PHY_PPDU_END_INFO1_ERR_RX_CBF = BIT(13), BIT 1094 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_RX_INFO_TX_HT_VHT_ACK BIT(24) BIT 1095 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_RX_INFO_RX_PKT_END_VALID BIT(25) BIT 1096 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_RX_INFO_RX_PHY_PPDU_END_VALID BIT(26) BIT 1097 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_RX_INFO_RX_TIMING_OFFSET_VALID BIT(27) BIT 1098 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_RX_INFO_BB_CAPTURED_CHANNEL BIT(28) BIT 1099 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_RX_INFO_UNSUPPORTED_MU_NC BIT(29) BIT 1100 drivers/net/wireless/ath/ath10k/rx_desc.h #define RX_PPDU_END_RX_INFO_OTP_TXBF_DISABLE BIT(30) BIT 1266 drivers/net/wireless/ath/ath10k/rx_desc.h #define FW_RX_DESC_INFO0_DISCARD BIT(0) BIT 1267 drivers/net/wireless/ath/ath10k/rx_desc.h #define FW_RX_DESC_INFO0_FORWARD BIT(1) BIT 1268 drivers/net/wireless/ath/ath10k/rx_desc.h #define FW_RX_DESC_INFO0_INSPECT BIT(5) BIT 86 drivers/net/wireless/ath/ath10k/sdio.c *arg = FIELD_PREP(BIT(31), write) | BIT 87 drivers/net/wireless/ath/ath10k/sdio.c FIELD_PREP(BIT(27), raw) | BIT 88 drivers/net/wireless/ath/ath10k/sdio.c FIELD_PREP(BIT(26), 1) | BIT 90 drivers/net/wireless/ath/ath10k/sdio.c FIELD_PREP(BIT(8), 1) | BIT 46 drivers/net/wireless/ath/ath10k/sdio.h #define ATH10K_HTC_MAILBOX_MASK BIT(ATH10K_HTC_MAILBOX) BIT 78 drivers/net/wireless/ath/ath10k/sdio.h #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ BIT(0) BIT 79 drivers/net/wireless/ath/ath10k/sdio.h #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_SDIO3 BIT(1) BIT 89 drivers/net/wireless/ath/ath10k/usb.h #define ATH10K_USB_PIPE_FLAG_TX BIT(0) BIT 385 drivers/net/wireless/ath/ath10k/wmi-tlv.c if (!(vdev_map & BIT(vdev_id))) BIT 388 drivers/net/wireless/ath/ath10k/wmi-tlv.c vdev_map &= ~BIT(vdev_id); BIT 1042 drivers/net/wireless/ath/ath10k/wmi-tlv.c if (map & BIT(0)) BIT 17 drivers/net/wireless/ath/ath10k/wmi-tlv.h #define WMI_RSRC_CFG_FLAG_TX_ACK_RSSI BIT(18) BIT 1420 drivers/net/wireless/ath/ath10k/wmi-tlv.h BIT(((((svc_id) - (len)) % 32) & 0x1f))) BIT 1616 drivers/net/wireless/ath/ath10k/wmi-tlv.h #define WMI_TLV_FLAG_MGMT_BUNDLE_TX_COMPL BIT(9) BIT 2134 drivers/net/wireless/ath/ath10k/wmi-tlv.h WMI_TLV_TDLS_OFFCHAN_EN = BIT(0), BIT 2135 drivers/net/wireless/ath/ath10k/wmi-tlv.h WMI_TLV_TDLS_BUFFER_STA_EN = BIT(1), BIT 2136 drivers/net/wireless/ath/ath10k/wmi-tlv.h WMI_TLV_TDLS_SLEEP_STA_EN = BIT(2), BIT 2162 drivers/net/wireless/ath/ath10k/wmi-tlv.h WMI_TLV_TDLS_PEER_QOS_AC_VO = BIT(0), BIT 2163 drivers/net/wireless/ath/ath10k/wmi-tlv.h WMI_TLV_TDLS_PEER_QOS_AC_VI = BIT(1), BIT 2164 drivers/net/wireless/ath/ath10k/wmi-tlv.h WMI_TLV_TDLS_PEER_QOS_AC_BK = BIT(2), BIT 2165 drivers/net/wireless/ath/ath10k/wmi-tlv.h WMI_TLV_TDLS_PEER_QOS_AC_BE = BIT(3), BIT 3603 drivers/net/wireless/ath/ath10k/wmi.c if (!(map & BIT(0))) BIT 3649 drivers/net/wireless/ath/ath10k/wmi.c if (!(map & BIT(0))) BIT 3693 drivers/net/wireless/ath/ath10k/wmi.c if (!(map & BIT(0))) BIT 7558 drivers/net/wireless/ath/ath10k/wmi.c BIT(PEER_BW_RXNSS_OVERRIDE_OFFSET)); BIT 512 drivers/net/wireless/ath/ath10k/wmi.h BIT((svc_id) % (sizeof(u32)))) BIT 522 drivers/net/wireless/ath/ath10k/wmi.h BIT(((((svc_id) - (len)) % 28) & 0x1f) + 4)) BIT 2716 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_2_RX_BATCH_MODE = BIT(0), BIT 2717 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_2_ATF_CONFIG = BIT(1), BIT 2718 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_2_COEX_GPIO = BIT(3), BIT 2719 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_2_BSS_CHAN_INFO = BIT(6), BIT 2720 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_2_PEER_STATS = BIT(7), BIT 2734 drivers/net/wireless/ath/ath10k/wmi.h #define NUM_UNITS_IS_NUM_VDEVS BIT(0) BIT 2735 drivers/net/wireless/ath/ath10k/wmi.h #define NUM_UNITS_IS_NUM_PEERS BIT(1) BIT 2736 drivers/net/wireless/ath/ath10k/wmi.h #define NUM_UNITS_IS_NUM_ACTIVE_PEERS BIT(2) BIT 2989 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_LTEU_SUPPORT = BIT(0), BIT 2990 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_COEX_GPIO_SUPPORT = BIT(1), BIT 2991 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_AUX_RADIO_SPECTRAL_INTF = BIT(2), BIT 2992 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_AUX_RADIO_CHAN_LOAD_INTF = BIT(3), BIT 2993 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_BSS_CHANNEL_INFO_64 = BIT(4), BIT 2994 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_PEER_STATS = BIT(5), BIT 2995 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_VDEV_STATS = BIT(6), BIT 2996 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_TDLS = BIT(7), BIT 2997 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_TDLS_OFFCHAN = BIT(8), BIT 2998 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_TDLS_UAPSD_BUFFER_STA = BIT(9), BIT 2999 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_TDLS_UAPSD_SLEEP_STA = BIT(10), BIT 3000 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_TDLS_CONN_TRACKER_IN_HOST_MODE = BIT(11), BIT 3001 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_TDLS_EXPLICIT_MODE_ONLY = BIT(12), BIT 3002 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_TX_DATA_ACK_RSSI = BIT(16), BIT 3003 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT = BIT(17), BIT 3004 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_REPORT_AIRTIME = BIT(18), BIT 3323 drivers/net/wireless/ath/ath10k/wmi.h WMI_SCAN_EVENT_STARTED = BIT(0), BIT 3324 drivers/net/wireless/ath/ath10k/wmi.h WMI_SCAN_EVENT_COMPLETED = BIT(1), BIT 3325 drivers/net/wireless/ath/ath10k/wmi.h WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2), BIT 3326 drivers/net/wireless/ath/ath10k/wmi.h WMI_SCAN_EVENT_FOREIGN_CHANNEL = BIT(3), BIT 3327 drivers/net/wireless/ath/ath10k/wmi.h WMI_SCAN_EVENT_DEQUEUED = BIT(4), BIT 3329 drivers/net/wireless/ath/ath10k/wmi.h WMI_SCAN_EVENT_PREEMPTED = BIT(5), BIT 3330 drivers/net/wireless/ath/ath10k/wmi.h WMI_SCAN_EVENT_START_FAILED = BIT(6), BIT 3331 drivers/net/wireless/ath/ath10k/wmi.h WMI_SCAN_EVENT_RESTARTED = BIT(7), BIT 3332 drivers/net/wireless/ath/ath10k/wmi.h WMI_SCAN_EVENT_FOREIGN_CHANNEL_EXIT = BIT(8), BIT 3333 drivers/net/wireless/ath/ath10k/wmi.h WMI_SCAN_EVENT_MAX = BIT(15), BIT 4528 drivers/net/wireless/ath/ath10k/wmi.h WMI_STAT_PEER = BIT(0), BIT 4529 drivers/net/wireless/ath/ath10k/wmi.h WMI_STAT_AP = BIT(1), BIT 4530 drivers/net/wireless/ath/ath10k/wmi.h WMI_STAT_PDEV = BIT(2), BIT 4531 drivers/net/wireless/ath/ath10k/wmi.h WMI_STAT_VDEV = BIT(3), BIT 4532 drivers/net/wireless/ath/ath10k/wmi.h WMI_STAT_BCNFLT = BIT(4), BIT 4533 drivers/net/wireless/ath/ath10k/wmi.h WMI_STAT_VDEV_RATE = BIT(5), BIT 4537 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_STAT_PEER = BIT(0), BIT 4538 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_STAT_AP = BIT(1), BIT 4539 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_STAT_INST = BIT(2), BIT 4540 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_STAT_PEER_EXTD = BIT(3), BIT 4541 drivers/net/wireless/ath/ath10k/wmi.h WMI_10_4_STAT_VDEV_EXTD = BIT(4), BIT 4545 drivers/net/wireless/ath/ath10k/wmi.h WMI_TLV_STAT_PEER = BIT(0), BIT 4546 drivers/net/wireless/ath/ath10k/wmi.h WMI_TLV_STAT_AP = BIT(1), BIT 4547 drivers/net/wireless/ath/ath10k/wmi.h WMI_TLV_STAT_PDEV = BIT(2), BIT 4548 drivers/net/wireless/ath/ath10k/wmi.h WMI_TLV_STAT_VDEV = BIT(3), BIT 4549 drivers/net/wireless/ath/ath10k/wmi.h WMI_TLV_STAT_PEER_EXTD = BIT(10), BIT 4691 drivers/net/wireless/ath/ath10k/wmi.h #define WMI_VDEV_STATS_FTM_COUNT_VALID BIT(31) BIT 5498 drivers/net/wireless/ath/ath10k/wmi.h #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) BIT 5499 drivers/net/wireless/ath/ath10k/wmi.h #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) BIT 5500 drivers/net/wireless/ath/ath10k/wmi.h #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) BIT 5501 drivers/net/wireless/ath/ath10k/wmi.h #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) BIT 5505 drivers/net/wireless/ath/ath10k/wmi.h #define WMI_TXBF_CONF_IMPLICIT_BF BIT(7) BIT 6055 drivers/net/wireless/ath/ath10k/wmi.h #define WMI_P2P_OPPPS_ENABLE_BIT BIT(0) BIT 6057 drivers/net/wireless/ath/ath10k/wmi.h #define WMI_P2P_NOA_CHANGED_BIT BIT(0) BIT 6554 drivers/net/wireless/ath/ath10k/wmi.h #define WMI_CHAN_INFO_FLAG_COMPLETE BIT(0) BIT 6555 drivers/net/wireless/ath/ath10k/wmi.h #define WMI_CHAN_INFO_FLAG_PRE_COMPLETE BIT(1) BIT 7074 drivers/net/wireless/ath/ath10k/wmi.h WMI_TDLS_OFFCHAN_EN = BIT(0), BIT 7075 drivers/net/wireless/ath/ath10k/wmi.h WMI_TDLS_BUFFER_STA_EN = BIT(1), BIT 7076 drivers/net/wireless/ath/ath10k/wmi.h WMI_TDLS_SLEEP_STA_EN = BIT(2), BIT 7080 drivers/net/wireless/ath/ath10k/wmi.h WMI_TDLS_PEER_QOS_AC_VO = BIT(0), BIT 7081 drivers/net/wireless/ath/ath10k/wmi.h WMI_TDLS_PEER_QOS_AC_VI = BIT(1), BIT 7082 drivers/net/wireless/ath/ath10k/wmi.h WMI_TDLS_PEER_QOS_AC_BK = BIT(2), BIT 7083 drivers/net/wireless/ath/ath10k/wmi.h WMI_TDLS_PEER_QOS_AC_BE = BIT(3), BIT 337 drivers/net/wireless/ath/ath10k/wow.c if (patterns[i].mask[j / 8] & BIT(j % 8)) BIT 1793 drivers/net/wireless/ath/ath5k/base.c if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) BIT 2513 drivers/net/wireless/ath/ath5k/base.c { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, BIT 2516 drivers/net/wireless/ath/ath5k/base.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 2518 drivers/net/wireless/ath/ath5k/base.c BIT(NL80211_IFTYPE_AP) }, BIT 2546 drivers/net/wireless/ath/ath5k/base.c BIT(NL80211_IFTYPE_AP) | BIT 2547 drivers/net/wireless/ath/ath5k/base.c BIT(NL80211_IFTYPE_STATION) | BIT 2548 drivers/net/wireless/ath/ath5k/base.c BIT(NL80211_IFTYPE_ADHOC) | BIT 2549 drivers/net/wireless/ath/ath5k/base.c BIT(NL80211_IFTYPE_MESH_POINT); BIT 404 drivers/net/wireless/ath/ath6kl/cfg80211.c if ((ar->avail_idx_map) & BIT(i)) { BIT 414 drivers/net/wireless/ath/ath6kl/cfg80211.c if ((ar->avail_idx_map) & BIT(i)) { BIT 3017 drivers/net/wireless/ath/ath6kl/cfg80211.c if (params->sta_flags_set & BIT(NL80211_STA_FLAG_AUTHORIZED)) BIT 3408 drivers/net/wireless/ath/ath6kl/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 3409 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 3410 drivers/net/wireless/ath/ath6kl/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 3411 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 3414 drivers/net/wireless/ath/ath6kl/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 3415 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 3416 drivers/net/wireless/ath/ath6kl/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 3417 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 3420 drivers/net/wireless/ath/ath6kl/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 3421 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 3422 drivers/net/wireless/ath/ath6kl/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 3423 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 3426 drivers/net/wireless/ath/ath6kl/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 3427 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 3428 drivers/net/wireless/ath/ath6kl/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 3429 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 3643 drivers/net/wireless/ath/ath6kl/cfg80211.c ar->avail_idx_map |= BIT(vif->fw_vif_idx); BIT 3829 drivers/net/wireless/ath/ath6kl/cfg80211.c ar->avail_idx_map &= ~BIT(fw_vif_idx); BIT 3876 drivers/net/wireless/ath/ath6kl/cfg80211.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 3877 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(NL80211_IFTYPE_ADHOC) | BIT 3878 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(NL80211_IFTYPE_AP); BIT 3880 drivers/net/wireless/ath/ath6kl/cfg80211.c wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_GO) | BIT 3881 drivers/net/wireless/ath/ath6kl/cfg80211.c BIT(NL80211_IFTYPE_P2P_CLIENT); BIT 212 drivers/net/wireless/ath/ath6kl/core.c ar->avail_idx_map |= BIT(i); BIT 167 drivers/net/wireless/ath/ath6kl/core.h ATH6KL_HW_SDIO_CRC_ERROR_WAR = BIT(3), BIT 248 drivers/net/wireless/ath/ath6kl/core.h #define STA_PS_AWAKE BIT(0) BIT 249 drivers/net/wireless/ath/ath6kl/core.h #define STA_PS_SLEEP BIT(1) BIT 250 drivers/net/wireless/ath/ath6kl/core.h #define STA_PS_POLLED BIT(2) BIT 251 drivers/net/wireless/ath/ath6kl/core.h #define STA_PS_APSD_TRIGGER BIT(3) BIT 252 drivers/net/wireless/ath/ath6kl/core.h #define STA_PS_APSD_EOSP BIT(4) BIT 296 drivers/net/wireless/ath/ath6kl/core.h #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0) BIT 297 drivers/net/wireless/ath/ath6kl/core.h #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1) BIT 298 drivers/net/wireless/ath/ath6kl/core.h #define ATH6KL_CONF_ENABLE_11N BIT(2) BIT 299 drivers/net/wireless/ath/ath6kl/core.h #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3) BIT 300 drivers/net/wireless/ath/ath6kl/core.h #define ATH6KL_CONF_UART_DEBUG BIT(4) BIT 25 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_CREDIT = BIT(0), BIT 27 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_WLAN_TX = BIT(2), /* wlan tx */ BIT 28 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_WLAN_RX = BIT(3), /* wlan rx */ BIT 29 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_BMI = BIT(4), /* bmi tracing */ BIT 30 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_HTC = BIT(5), BIT 31 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_HIF = BIT(6), BIT 32 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_IRQ = BIT(7), /* interrupt processing */ BIT 35 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_WMI = BIT(10), /* wmi tracing */ BIT 36 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_TRC = BIT(11), /* generic func tracing */ BIT 37 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_SCATTER = BIT(12), /* hif scatter tracing */ BIT 38 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_WLAN_CFG = BIT(13), /* cfg80211 i/f file tracing */ BIT 39 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_RAW_BYTES = BIT(14), /* dump tx/rx frames */ BIT 40 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_AGGR = BIT(15), /* aggregation */ BIT 41 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_SDIO = BIT(16), BIT 42 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_SDIO_DUMP = BIT(17), BIT 43 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_BOOT = BIT(18), /* driver init and fw boot */ BIT 44 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_WMI_DUMP = BIT(19), BIT 45 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_SUSPEND = BIT(20), BIT 46 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_USB = BIT(21), BIT 47 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_USB_BULK = BIT(22), BIT 48 drivers/net/wireless/ath/ath6kl/debug.h ATH6KL_DBG_RECOVERY = BIT(23), BIT 2070 drivers/net/wireless/ath/ath6kl/wmi.c if ((BIT(i) & ratemask) == 0) BIT 2091 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_SSID = BIT(1), BIT 2092 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_MAGIC_PACKET = BIT(2), BIT 2093 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_EAP_REQ = BIT(3), BIT 2094 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_PATTERNS = BIT(4), BIT 2095 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_OFFLOAD_ARP = BIT(5), BIT 2096 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_OFFLOAD_NS = BIT(6), BIT 2097 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_OFFLOAD_GTK = BIT(7), BIT 2098 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_8021X_4WAYHS = BIT(8), BIT 2099 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_NLO_DISCVRY = BIT(9), BIT 2100 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_NWK_DISASSOC = BIT(10), BIT 2101 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_GTK_ERROR = BIT(11), BIT 2102 drivers/net/wireless/ath/ath6kl/wmi.h WOW_FILTER_OPTION_TEST_MODE = BIT(15), BIT 24 drivers/net/wireless/ath/ath9k/ar9002_calib.c ADC_GAIN_CAL = BIT(0), BIT 25 drivers/net/wireless/ath/ath9k/ar9002_calib.c ADC_DC_CAL = BIT(1), BIT 26 drivers/net/wireless/ath/ath9k/ar9002_calib.c IQ_MISMATCH_CAL = BIT(2), BIT 343 drivers/net/wireless/ath/ath9k/ar9002_phy.c if (!(ah->rxchainmask & BIT(1))) BIT 35 drivers/net/wireless/ath/ath9k/ar9003_calib.c IQ_MISMATCH_CAL = BIT(0), BIT 181 drivers/net/wireless/ath/ath9k/ar9003_calib.c if (ah->txchainmask & BIT(i)) { BIT 1261 drivers/net/wireless/ath/ath9k/ar9003_calib.c offset[i] = BIT(i - 1); BIT 2999 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c return !!(pBase->featureEnable & BIT(5)); BIT 3547 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0))); BIT 3548 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1))); BIT 3549 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2))); BIT 3550 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3))); BIT 3551 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4))); BIT 3552 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5))); BIT 3553 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0))); BIT 3554 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1))); BIT 3714 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if ((ah->rxchainmask & BIT(chain)) || BIT 3715 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c (ah->txchainmask & BIT(chain))) { BIT 3802 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c drive_strength = pBase->miscConfiguration & BIT(0); BIT 3914 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (ah->txchainmask & BIT(i)) { BIT 3958 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (pBase->featureEnable & BIT(4)) { BIT 4071 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (!(pBase->miscConfiguration & BIT(4))) BIT 4162 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (pCap->chip_chainmask & BIT(1)) BIT 4165 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (pCap->chip_chainmask & BIT(2)) BIT 4172 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (pCap->chip_chainmask & BIT(1)) { BIT 4177 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (pCap->chip_chainmask & BIT(2)) { BIT 4216 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (!(eep->base_ext1.misc_enable & BIT(2))) BIT 4219 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (!(eep->base_ext1.misc_enable & BIT(3))) BIT 4224 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (!(ah->caps.tx_chainmask & BIT(chain))) BIT 4817 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (ah->caps.tx_chainmask & BIT(1)) BIT 4821 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (ah->caps.tx_chainmask & BIT(2)) BIT 4830 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (ah->caps.tx_chainmask & BIT(1)) BIT 4834 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (ah->caps.tx_chainmask & BIT(2)) BIT 4903 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (txmask & BIT(0)) BIT 4907 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (txmask & BIT(1)) BIT 4911 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (txmask & BIT(2)) BIT 4916 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (txmask & BIT(0)) BIT 4920 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (txmask & BIT(1)) BIT 4924 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (txmask & BIT(2)) BIT 4934 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (txmask & BIT(0)) BIT 4937 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (txmask & BIT(1)) BIT 4940 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c if (txmask & BIT(2)) BIT 1150 drivers/net/wireless/ath/ath9k/ar9003_hw.c chk_dcu |= BIT(i); BIT 1435 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_WRITE(ah, AR_BTCOEX_CTRL2, (btcoex_ctrl2 | BIT(23))); BIT 1443 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18))); BIT 32 drivers/net/wireless/ath/ath9k/ar9003_mci.h MCI_GPM_COEX_QUERY_BT_ALL_INFO = BIT(0), BIT 33 drivers/net/wireless/ath/ath9k/ar9003_mci.h MCI_GPM_COEX_QUERY_BT_TOPOLOGY = BIT(1), BIT 34 drivers/net/wireless/ath/ath9k/ar9003_mci.h MCI_GPM_COEX_QUERY_BT_DEBUG = BIT(2), BIT 42 drivers/net/wireless/ath/ath9k/ar9003_paprd.c & BIT(30)) BIT 46 drivers/net/wireless/ath/ath9k/ar9003_paprd.c & BIT(29)) BIT 50 drivers/net/wireless/ath/ath9k/ar9003_paprd.c & BIT(28)) BIT 62 drivers/net/wireless/ath/ath9k/ar9003_paprd.c if (ah->caps.tx_chainmask & BIT(1)) BIT 65 drivers/net/wireless/ath/ath9k/ar9003_paprd.c if (ah->caps.tx_chainmask & BIT(2)) BIT 786 drivers/net/wireless/ath/ath9k/ar9003_paprd.c if (ah->caps.tx_chainmask & BIT(1)) BIT 791 drivers/net/wireless/ath/ath9k/ar9003_paprd.c if (ah->caps.tx_chainmask & BIT(2)) BIT 1360 drivers/net/wireless/ath/ath9k/ar9003_phy.c if (ah->rxchainmask & BIT(i)) { BIT 133 drivers/net/wireless/ath/ath9k/ar9003_wow.c REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count)); BIT 135 drivers/net/wireless/ath/ath9k/ar9003_wow.c REG_SET_BIT(ah, AR_MAC_PCU_WOW4, BIT(pattern_count - 8)); BIT 152 drivers/net/wireless/ath/ath9k/ar9003_wow.c BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT); BIT 155 drivers/net/wireless/ath/ath9k/ar9003_wow.c BIT((pattern_count - 8) + AR_WOW_PAT_FOUND_SHIFT); BIT 441 drivers/net/wireless/ath/ath9k/ar9003_wow.c REG_SET_BIT(ah, AR_PCIE_PHY_REG3, BIT(13)); BIT 449 drivers/net/wireless/ath/ath9k/ar9003_wow.c REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, BIT(5)); BIT 202 drivers/net/wireless/ath/ath9k/ath9k.h BUF_AMPDU = BIT(0), BIT 203 drivers/net/wireless/ath/ath9k/ath9k.h BUF_AGGR = BIT(1), BIT 973 drivers/net/wireless/ath/ath9k/ath9k.h #define PS_WAIT_FOR_BEACON BIT(0) BIT 974 drivers/net/wireless/ath/ath9k/ath9k.h #define PS_WAIT_FOR_CAB BIT(1) BIT 975 drivers/net/wireless/ath/ath9k/ath9k.h #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) BIT 976 drivers/net/wireless/ath/ath9k/ath9k.h #define PS_WAIT_FOR_TX_ACK BIT(3) BIT 977 drivers/net/wireless/ath/ath9k/ath9k.h #define PS_BEACON_SYNC BIT(4) BIT 978 drivers/net/wireless/ath/ath9k/ath9k.h #define PS_WAIT_FOR_ANI BIT(5) BIT 617 drivers/net/wireless/ath/ath9k/channel.c if (avp->noa_duration && tsf_time - avp->noa_start > BIT(30)) BIT 1273 drivers/net/wireless/ath/ath9k/channel.c __ath9k_flush(sc->hw, BIT(IEEE80211_AC_VO), BIT 1532 drivers/net/wireless/ath/ath9k/channel.c noa->oppps_ctwindow |= BIT(7); BIT 1578 drivers/net/wireless/ath/ath9k/channel.c avp->noa.next_tsf - tsf > BIT(31)) BIT 243 drivers/net/wireless/ath/ath9k/common.c if (!(ah->rxchainmask & BIT(i))) BIT 248 drivers/net/wireless/ath/ath9k/common.c rxs->chains |= BIT(j); BIT 221 drivers/net/wireless/ath/ath9k/eeprom.h #define LNA_CTL_BUF_MODE BIT(0) BIT 222 drivers/net/wireless/ath/ath9k/eeprom.h #define LNA_CTL_ISEL_LO BIT(1) BIT 223 drivers/net/wireless/ath/ath9k/eeprom.h #define LNA_CTL_ISEL_HI BIT(2) BIT 224 drivers/net/wireless/ath/ath9k/eeprom.h #define LNA_CTL_BUF_IN BIT(3) BIT 225 drivers/net/wireless/ath/ath9k/eeprom.h #define LNA_CTL_FEM_BAND BIT(4) BIT 226 drivers/net/wireless/ath/ath9k/eeprom.h #define LNA_CTL_LOCAL_BIAS BIT(5) BIT 227 drivers/net/wireless/ath/ath9k/eeprom.h #define LNA_CTL_FORCE_XPA BIT(6) BIT 228 drivers/net/wireless/ath/ath9k/eeprom.h #define LNA_CTL_USE_ANT1 BIT(7) BIT 1012 drivers/net/wireless/ath/ath9k/eeprom_4k.c mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25); BIT 1020 drivers/net/wireless/ath/ath9k/eeprom_4k.c mask = BIT(0)|BIT(5)|BIT(15); BIT 1025 drivers/net/wireless/ath/ath9k/eeprom_4k.c mask = BIT(0)|BIT(5); BIT 94 drivers/net/wireless/ath/ath9k/hif_usb.h #define HIF_USB_TX_STOP BIT(0) BIT 95 drivers/net/wireless/ath/ath9k/hif_usb.h #define HIF_USB_TX_FLUSH BIT(1) BIT 112 drivers/net/wireless/ath/ath9k/hif_usb.h #define HIF_USB_START BIT(0) BIT 113 drivers/net/wireless/ath/ath9k/hif_usb.h #define HIF_USB_READY BIT(1) BIT 292 drivers/net/wireless/ath/ath9k/htc.h #define ATH9K_HTC_OP_TX_QUEUES_STOP BIT(0) BIT 293 drivers/net/wireless/ath/ath9k/htc.h #define ATH9K_HTC_OP_TX_DRAIN BIT(1) BIT 698 drivers/net/wireless/ath/ath9k/htc_drv_init.c { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) | BIT 699 drivers/net/wireless/ath/ath9k/htc_drv_init.c BIT(NL80211_IFTYPE_P2P_CLIENT) }, BIT 700 drivers/net/wireless/ath/ath9k/htc_drv_init.c { .max = 2, .types = BIT(NL80211_IFTYPE_AP) | BIT 702 drivers/net/wireless/ath/ath9k/htc_drv_init.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 704 drivers/net/wireless/ath/ath9k/htc_drv_init.c BIT(NL80211_IFTYPE_P2P_GO) }, BIT 736 drivers/net/wireless/ath/ath9k/htc_drv_init.c BIT(NL80211_IFTYPE_STATION) | BIT 737 drivers/net/wireless/ath/ath9k/htc_drv_init.c BIT(NL80211_IFTYPE_ADHOC) | BIT 738 drivers/net/wireless/ath/ath9k/htc_drv_init.c BIT(NL80211_IFTYPE_AP) | BIT 739 drivers/net/wireless/ath/ath9k/htc_drv_init.c BIT(NL80211_IFTYPE_P2P_GO) | BIT 740 drivers/net/wireless/ath/ath9k/htc_drv_init.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 741 drivers/net/wireless/ath/ath9k/htc_drv_init.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 742 drivers/net/wireless/ath/ath9k/htc_drv_init.c BIT(NL80211_IFTYPE_OCB); BIT 605 drivers/net/wireless/ath/ath9k/htc_drv_main.c if (sta->supp_rates[sband->band] & BIT(i)) { BIT 113 drivers/net/wireless/ath/ath9k/htc_hst.h #define HTC_OP_START_WAIT BIT(0) BIT 114 drivers/net/wireless/ath/ath9k/htc_hst.h #define HTC_OP_CONFIG_PIPE_CREDITS BIT(1) BIT 1624 drivers/net/wireless/ath/ath9k/hw.c ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); BIT 2666 drivers/net/wireless/ath/ath9k/hw.c if (tx_chainmask & BIT(0)) BIT 2668 drivers/net/wireless/ath/ath9k/hw.c if (rx_chainmask & BIT(0)) BIT 2733 drivers/net/wireless/ath/ath9k/hw.c if (ah->caps.gpio_requested & BIT(gpio)) BIT 2742 drivers/net/wireless/ath/ath9k/hw.c ah->caps.gpio_requested |= BIT(gpio); BIT 2776 drivers/net/wireless/ath/ath9k/hw.c if (BIT(gpio) & ah->caps.gpio_mask) BIT 2804 drivers/net/wireless/ath/ath9k/hw.c if (ah->caps.gpio_requested & BIT(gpio)) { BIT 2806 drivers/net/wireless/ath/ath9k/hw.c ah->caps.gpio_requested &= ~BIT(gpio); BIT 2816 drivers/net/wireless/ath/ath9k/hw.c (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y)) BIT 2820 drivers/net/wireless/ath/ath9k/hw.c if (BIT(gpio) & ah->caps.gpio_mask) { BIT 2830 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio); BIT 2832 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio); BIT 2835 drivers/net/wireless/ath/ath9k/hw.c } else if (BIT(gpio) & ah->caps.gpio_requested) { BIT 2836 drivers/net/wireless/ath/ath9k/hw.c val = gpio_get_value(gpio) & BIT(gpio); BIT 2854 drivers/net/wireless/ath/ath9k/hw.c if (BIT(gpio) & ah->caps.gpio_mask) { BIT 2858 drivers/net/wireless/ath/ath9k/hw.c REG_RMW(ah, out_addr, val << gpio, BIT(gpio)); BIT 2859 drivers/net/wireless/ath/ath9k/hw.c } else if (BIT(gpio) & ah->caps.gpio_requested) { BIT 3169 drivers/net/wireless/ath/ath9k/hw.c timer_table->timer_mask |= BIT(timer->index); BIT 3234 drivers/net/wireless/ath/ath9k/hw.c timer_table->timer_mask &= ~BIT(timer->index); BIT 3276 drivers/net/wireless/ath/ath9k/hw.c trigger_mask &= ~BIT(index); BIT 231 drivers/net/wireless/ath/ath9k/hw.h #define AH_WOW_USER_PATTERN_EN BIT(0) BIT 232 drivers/net/wireless/ath/ath9k/hw.h #define AH_WOW_MAGIC_PATTERN_EN BIT(1) BIT 233 drivers/net/wireless/ath/ath9k/hw.h #define AH_WOW_LINK_CHANGE BIT(2) BIT 234 drivers/net/wireless/ath/ath9k/hw.h #define AH_WOW_BEACON_MISS BIT(3) BIT 251 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_HT = BIT(0), BIT 252 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_RFSILENT = BIT(1), BIT 253 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_AUTOSLEEP = BIT(2), BIT 254 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), BIT 255 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_EDMA = BIT(4), BIT 256 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), BIT 257 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_LDPC = BIT(6), BIT 258 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_FASTCLOCK = BIT(7), BIT 259 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_SGI_20 = BIT(8), BIT 260 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), BIT 261 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_2GHZ = BIT(11), BIT 262 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_5GHZ = BIT(12), BIT 263 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_APM = BIT(13), BIT 265 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_RTT = BIT(14), BIT 266 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_MCI = BIT(15), BIT 267 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_BT_ANT_DIV = BIT(17), BIT 273 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_DFS = BIT(18), BIT 274 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_PAPRD = BIT(19), BIT 275 drivers/net/wireless/ath/ath9k/hw.h ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20), BIT 320 drivers/net/wireless/ath/ath9k/hw.h HW_BB_WATCHDOG = BIT(0), BIT 321 drivers/net/wireless/ath/ath9k/hw.h HW_PHYRESTART_CLC_WAR = BIT(1), BIT 322 drivers/net/wireless/ath/ath9k/hw.h HW_BB_RIFS_HANG = BIT(2), BIT 323 drivers/net/wireless/ath/ath9k/hw.h HW_BB_DFS_HANG = BIT(3), BIT 324 drivers/net/wireless/ath/ath9k/hw.h HW_BB_RX_CLEAR_STUCK_HANG = BIT(4), BIT 325 drivers/net/wireless/ath/ath9k/hw.h HW_MAC_HANG = BIT(5), BIT 328 drivers/net/wireless/ath/ath9k/hw.h #define AR_PCIE_PLL_PWRSAVE_CONTROL BIT(0) BIT 329 drivers/net/wireless/ath/ath9k/hw.h #define AR_PCIE_PLL_PWRSAVE_ON_D3 BIT(1) BIT 330 drivers/net/wireless/ath/ath9k/hw.h #define AR_PCIE_PLL_PWRSAVE_ON_D0 BIT(2) BIT 331 drivers/net/wireless/ath/ath9k/hw.h #define AR_PCIE_CDR_PWRSAVE_ON_D3 BIT(3) BIT 332 drivers/net/wireless/ath/ath9k/hw.h #define AR_PCIE_CDR_PWRSAVE_ON_D0 BIT(4) BIT 456 drivers/net/wireless/ath/ath9k/hw.h #define CHANNEL_5GHZ BIT(0) BIT 457 drivers/net/wireless/ath/ath9k/hw.h #define CHANNEL_HALF BIT(1) BIT 458 drivers/net/wireless/ath/ath9k/hw.h #define CHANNEL_QUARTER BIT(2) BIT 459 drivers/net/wireless/ath/ath9k/hw.h #define CHANNEL_HT BIT(3) BIT 460 drivers/net/wireless/ath/ath9k/hw.h #define CHANNEL_HT40PLUS BIT(4) BIT 461 drivers/net/wireless/ath/ath9k/hw.h #define CHANNEL_HT40MINUS BIT(5) BIT 763 drivers/net/wireless/ath/ath9k/hw.h TX_IQ_CAL = BIT(0), BIT 764 drivers/net/wireless/ath/ath9k/hw.h TX_IQ_ON_AGC_CAL = BIT(1), BIT 765 drivers/net/wireless/ath/ath9k/hw.h TX_CL_CAL = BIT(2), BIT 1018 drivers/net/wireless/ath/ath9k/hw.h return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); BIT 826 drivers/net/wireless/ath/ath9k/init.c { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, BIT 829 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 831 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_AP) }, BIT 832 drivers/net/wireless/ath/ath9k/init.c { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 833 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_P2P_GO) }, BIT 838 drivers/net/wireless/ath/ath9k/init.c { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) }, BIT 845 drivers/net/wireless/ath/ath9k/init.c { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) | BIT 846 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_AP) | BIT 847 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 848 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_P2P_GO) }, BIT 849 drivers/net/wireless/ath/ath9k/init.c { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) }, BIT 850 drivers/net/wireless/ath/ath9k/init.c { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) }, BIT 873 drivers/net/wireless/ath/ath9k/init.c .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT 874 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_CHAN_WIDTH_20) | BIT 875 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_CHAN_WIDTH_40), BIT 901 drivers/net/wireless/ath/ath9k/init.c hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS); BIT 951 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_P2P_GO) | BIT 952 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 953 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_AP) | BIT 954 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_STATION) | BIT 955 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_ADHOC) | BIT 956 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 958 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_WDS) | BIT 960 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_OCB); BIT 964 drivers/net/wireless/ath/ath9k/init.c BIT(NL80211_IFTYPE_P2P_DEVICE); BIT 988 drivers/net/wireless/ath/ath9k/init.c hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; BIT 989 drivers/net/wireless/ath/ath9k/init.c hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; BIT 993 drivers/net/wireless/ath/ath9k/init.c hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); BIT 162 drivers/net/wireless/ath/ath9k/link.c if (!(ah->txchainmask & BIT(chain))) BIT 193 drivers/net/wireless/ath/ath9k/link.c txctl.paprd = BIT(chain); BIT 254 drivers/net/wireless/ath/ath9k/link.c if (!(ah->txchainmask & BIT(chain))) BIT 1041 drivers/net/wireless/ath/ath9k/mac.c filter |= BIT(destidx % ATH9K_HW_BIT_IN_SLICE); BIT 2205 drivers/net/wireless/ath/ath9k/main.c if (!(cap & BIT(0))) BIT 2208 drivers/net/wireless/ath/ath9k/main.c if (new & BIT(0)) BIT 2209 drivers/net/wireless/ath/ath9k/main.c filled |= BIT(i); BIT 943 drivers/net/wireless/ath/ath9k/pci.c ret = pcim_iomap_regions(pdev, BIT(0), "ath9k"); BIT 51 drivers/net/wireless/ath/ath9k/wmi.h #define ATH9K_HTC_TXSTAT_ACK BIT(0) BIT 52 drivers/net/wireless/ath/ath9k/wmi.h #define ATH9K_HTC_TXSTAT_FILT BIT(1) BIT 53 drivers/net/wireless/ath/ath9k/wmi.h #define ATH9K_HTC_TXSTAT_RTC_CTS BIT(2) BIT 54 drivers/net/wireless/ath/ath9k/wmi.h #define ATH9K_HTC_TXSTAT_MCS BIT(3) BIT 55 drivers/net/wireless/ath/ath9k/wmi.h #define ATH9K_HTC_TXSTAT_CW40 BIT(4) BIT 56 drivers/net/wireless/ath/ath9k/wmi.h #define ATH9K_HTC_TXSTAT_SGI BIT(5) BIT 1886 drivers/net/wireless/ath/ath9k/xmit.c npend |= BIT(i); BIT 190 drivers/net/wireless/ath/carl9170/carl9170.h CARL9170_WPS_BUTTON = BIT(0), BIT 191 drivers/net/wireless/ath/carl9170/carl9170.h CARL9170_ONE_LED = BIT(1), BIT 467 drivers/net/wireless/ath/carl9170/carl9170.h PS_OFF_VIF = BIT(0), BIT 468 drivers/net/wireless/ath/carl9170/carl9170.h PS_OFF_BCN = BIT(1), BIT 312 drivers/net/wireless/ath/carl9170/fw.c if_comb_types = BIT(NL80211_IFTYPE_STATION) | BIT 313 drivers/net/wireless/ath/carl9170/fw.c BIT(NL80211_IFTYPE_P2P_CLIENT); BIT 338 drivers/net/wireless/ath/carl9170/fw.c ar->hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_ADHOC); BIT 342 drivers/net/wireless/ath/carl9170/fw.c BIT(NL80211_IFTYPE_AP) | BIT 343 drivers/net/wireless/ath/carl9170/fw.c BIT(NL80211_IFTYPE_P2P_GO); BIT 347 drivers/net/wireless/ath/carl9170/fw.c BIT(NL80211_IFTYPE_MESH_POINT); BIT 247 drivers/net/wireless/ath/carl9170/fwdesc.h return le32_to_cpu(list) & BIT(feature); BIT 115 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_TXC BIT(0) BIT 116 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_RXC BIT(1) BIT 117 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_RETRY_FAIL BIT(2) BIT 118 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_WAKEUP BIT(3) BIT 119 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_ATIM BIT(4) BIT 120 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_DTIM BIT(5) BIT 121 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_CFG_BCN BIT(6) BIT 122 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_ABORT BIT(7) BIT 123 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_QOS BIT(8) BIT 124 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_MIMO_PS BIT(9) BIT 125 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_KEY_GEN BIT(10) BIT 126 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_DECRY_NOUSER BIT(11) BIT 127 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_RADAR BIT(12) BIT 128 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_QUIET_FRAME BIT(13) BIT 129 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_INT_PRETBTT BIT(14) BIT 143 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_AP_MODE BIT(24) BIT 144 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_IBSS_MODE BIT(25) BIT 145 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_PWR_MGT BIT(26) BIT 146 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_STA_PS BIT(27) BIT 174 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_SNIFFER_ENABLE_PROMISC BIT(0) BIT 177 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_ENCRYPTION_MGMT_RX_SOFTWARE BIT(2) BIT 178 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_ENCRYPTION_RX_SOFTWARE BIT(3) BIT 186 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_ASSOC_REQ BIT(0) BIT 187 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_ASSOC_RESP BIT(1) BIT 188 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_REASSOC_REQ BIT(2) BIT 189 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_REASSOC_RESP BIT(3) BIT 190 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_PRB_REQ BIT(4) BIT 191 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_PRB_RESP BIT(5) BIT 192 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_BIT6 BIT(6) BIT 193 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_BIT7 BIT(7) BIT 194 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_BEACON BIT(8) BIT 195 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_ATIM BIT(9) BIT 196 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_DEASSOC BIT(10) BIT 197 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_AUTH BIT(11) BIT 198 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_DEAUTH BIT(12) BIT 199 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_BIT13 BIT(13) BIT 200 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_BIT14 BIT(14) BIT 201 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_BIT15 BIT(15) BIT 202 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_BAR BIT(24) BIT 203 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_BA BIT(25) BIT 204 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_PSPOLL BIT(26) BIT 205 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_RTS BIT(27) BIT 206 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_CTS BIT(28) BIT 207 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_ACK BIT(29) BIT 208 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_CFE BIT(30) BIT 209 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_FTF_CFE_ACK BIT(31) BIT 226 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BACKOFF_CCA BIT(24) BIT 227 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BACKOFF_TX_PEX BIT(25) BIT 228 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BACKOFF_RX_PE BIT(26) BIT 229 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BACKOFF_MD_READY BIT(27) BIT 230 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BACKOFF_TX_PE BIT(28) BIT 293 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_VIRTUAL_CCA_Q0 BIT(15) BIT 294 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_VIRTUAL_CCA_Q1 BIT(16) BIT 295 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_VIRTUAL_CCA_Q2 BIT(17) BIT 296 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_VIRTUAL_CCA_Q3 BIT(18) BIT 297 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_VIRTUAL_CCA_Q4 BIT(19) BIT 325 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_RX_CTRL_PASS_TO_HOST BIT(28) BIT 326 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER BIT(30) BIT 358 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_DMA_TRIGGER_TXQ0 BIT(0) BIT 359 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_DMA_TRIGGER_TXQ1 BIT(1) BIT 360 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_DMA_TRIGGER_TXQ2 BIT(2) BIT 361 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_DMA_TRIGGER_TXQ3 BIT(3) BIT 362 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_DMA_TRIGGER_TXQ4 BIT(4) BIT 363 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_DMA_TRIGGER_RXQ BIT(8) BIT 399 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT1_HT_EN BIT(0) BIT 400 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT1_GF_PMB BIT(1) BIT 401 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT1_SP_EXP BIT(2) BIT 402 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT1_TX_BF BIT(3) BIT 405 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT1_TX_ANT1 BIT(7) BIT 406 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT1_TX_ANT0 BIT(8) BIT 409 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT1_BWC_20M_EXT BIT(16) BIT 410 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT1_BWC_40M_SHARED BIT(17) BIT 411 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT1_BWC_40M_DUP (BIT(16) | BIT(17)) BIT 422 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT2_BW40 BIT(8) BIT 423 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT2_SMOOTHING BIT(9) BIT 424 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT2_SS BIT(10) BIT 425 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT2_NSS BIT(11) BIT 428 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT2_ADV_COD BIT(14) BIT 429 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_MAC_BCN_HT2_SGI BIT(15) BIT 459 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_SPI_CONTROL0_BUSY BIT(0) BIT 460 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_SPI_CONTROL0_CMD_GO BIT(1) BIT 461 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_SPI_CONTROL0_PAGE_WR BIT(2) BIT 462 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_SPI_CONTROL0_SEQ_RD BIT(3) BIT 463 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_SPI_CONTROL0_CMD_ABORT BIT(4) BIT 470 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_SPI_CONTROL1_SCK_RATE BIT(0) BIT 471 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_SPI_CONTROL1_DRIVE_SDO BIT(1) BIT 474 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_SPI_CONTROL1_WRITE_PROTECT BIT(4) BIT 516 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_EEPROM_CLOCK_DIV_SOFT_RST BIT(9) BIT 519 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_EEPROM_MODE_EEPROM_SIZE_16K_PLUS BIT(31) BIT 522 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_EEPROM_WRITE_PROTECT_WP_STATUS BIT(0) BIT 523 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_EEPROM_WRITE_PROTECT_WP_SET BIT(8) BIT 559 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PWR_RESET_COMMIT_RESET_MASK BIT(0) BIT 560 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PWR_RESET_WLAN_MASK BIT(1) BIT 561 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PWR_RESET_DMA_MASK BIT(2) BIT 562 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PWR_RESET_BRIDGE_MASK BIT(3) BIT 563 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PWR_RESET_AHB_MASK BIT(9) BIT 564 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PWR_RESET_BB_WARM_RESET BIT(10) BIT 565 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PWR_RESET_BB_COLD_RESET BIT(11) BIT 566 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PWR_RESET_ADDA_CLK_COLD_RESET BIT(12) BIT 567 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PWR_RESET_PLL BIT(13) BIT 568 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PWR_RESET_USB_PLL BIT(14) BIT 587 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP BIT(0) BIT 588 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT BIT(2) BIT 589 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_MAIN_CTRL_GO_TO_SUSPEND BIT(3) BIT 590 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_MAIN_CTRL_RESET BIT(4) BIT 591 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_MAIN_CTRL_CHIP_ENABLE BIT(5) BIT 592 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_MAIN_CTRL_HIGHSPEED BIT(6) BIT 595 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DEVICE_ADDRESS_CONFIGURE BIT(7) BIT 609 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_DISABLE_OUT_INT (BIT(7) | BIT(6)) BIT 613 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_DISABLE_IN_INT BIT(6) BIT 620 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC0_SETUP BIT(0) BIT 621 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC0_IN BIT(1) BIT 622 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC0_OUT BIT(2) BIT 623 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC0_FAIL BIT(3) /* ??? */ BIT 624 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC0_END BIT(4) /* ??? */ BIT 625 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC0_ABORT BIT(7) BIT 634 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC7_USB_RESET BIT(1) BIT 635 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC7_USB_SUSPEND BIT(2) BIT 636 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC7_USB_RESUME BIT(3) BIT 637 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC7_ISO_SEQ_ERR BIT(4) BIT 638 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC7_ISO_SEQ_ABORT BIT(5) BIT 639 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC7_TX0BYTE BIT(6) BIT 640 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_INTR_SRC7_RX0BYTE BIT(7) BIT 702 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE BIT(0) BIT 703 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE BIT(1) BIT 704 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_CTL_HIGH_SPEED BIT(2) BIT 705 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_CTL_UP_PACKET_MODE BIT(3) BIT 707 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_CTL_UP_STREAM (BIT(4) | BIT(5)) BIT 709 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_CTL_UP_STREAM_8K BIT(4) BIT 710 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_CTL_UP_STREAM_16K BIT(5) BIT 711 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_CTL_UP_STREAM_32K (BIT(4) | BIT(5)) BIT 712 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_CTL_DOWN_STREAM BIT(6) BIT 715 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_STATUS_UP_IDLE BIT(8) BIT 716 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_DMA_STATUS_DN_IDLE BIT(16) BIT 722 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_WAKE_UP_WAKE BIT(0) BIT 725 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_USB_CBUS_CTRL_BUFFER_END (BIT(1)) BIT 780 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PTA_DMA_MODE_CTRL_RESET BIT(0) BIT 781 drivers/net/wireless/ath/carl9170/hw.h #define AR9170_PTA_DMA_MODE_CTRL_DISABLE_USB BIT(1) BIT 1238 drivers/net/wireless/ath/carl9170/main.c if (!(ar->usedkeys & BIT(i))) BIT 1267 drivers/net/wireless/ath/carl9170/main.c ar->usedkeys |= BIT(i); BIT 1278 drivers/net/wireless/ath/carl9170/main.c ar->usedkeys &= ~BIT(key->hw_key_idx); BIT 451 drivers/net/wireless/ath/carl9170/rx.c status->antenna |= BIT(i); BIT 37 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_VLD BIT(0) BIT 39 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_EOP BIT(3) BIT 41 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_BDH BIT(4) BIT 43 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_SIQ BIT(5) BIT 45 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_DIQ BIT(6) BIT 47 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_PIQ BIT(7) BIT 49 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_PDU_REL BIT(8) BIT 51 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_STOP BIT(16) BIT 53 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_INT BIT(17) BIT 55 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_SWAP BIT(20) BIT 57 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_ENDIANNESS BIT(21) BIT 144 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_EN BIT(0) BIT 146 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_EOP BIT(3) BIT 148 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_BDH BIT(4) BIT 150 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_SIQ BIT(5) BIT 152 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_DIQ BIT(6) BIT 154 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_PIQ BIT(7) BIT 156 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_PDU_REL BIT(8) BIT 158 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_STOP BIT(16) BIT 160 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_INE_ED BIT(17) BIT 162 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_INE_ERR BIT(18) BIT 164 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_INE_DONE BIT(19) BIT 166 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_EDEN BIT(20) BIT 168 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_EDVEN BIT(21) BIT 170 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_ENDIANNESS BIT(26) BIT 172 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_ABORT BIT(27) BIT 174 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_DFMT BIT(28) BIT 176 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_SWAP BIT(31) BIT 1179 drivers/net/wireless/ath/wcn36xx/main.c wcn->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 1180 drivers/net/wireless/ath/wcn36xx/main.c BIT(NL80211_IFTYPE_AP) | BIT 1181 drivers/net/wireless/ath/wcn36xx/main.c BIT(NL80211_IFTYPE_ADHOC) | BIT 1182 drivers/net/wireless/ath/wcn36xx/main.c BIT(NL80211_IFTYPE_MESH_POINT); BIT 64 drivers/net/wireless/ath/wil6210/boot_loader.h #define BL_SHUTDOWN_HS_GRTD BIT(0) BIT 65 drivers/net/wireless/ath/wil6210/boot_loader.h #define BL_SHUTDOWN_HS_RTD BIT(1) BIT 28 drivers/net/wireless/ath/wil6210/cfg80211.c #define WIL_EDMG_CHANNEL_9_SUBCHANNELS (BIT(0) | BIT(1)) BIT 29 drivers/net/wireless/ath/wil6210/cfg80211.c #define WIL_EDMG_CHANNEL_10_SUBCHANNELS (BIT(1) | BIT(2)) BIT 30 drivers/net/wireless/ath/wil6210/cfg80211.c #define WIL_EDMG_CHANNEL_11_SUBCHANNELS (BIT(2) | BIT(3)) BIT 42 drivers/net/wireless/ath/wil6210/cfg80211.c #define WIL_EDMG_CHANNELS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) BIT 286 drivers/net/wireless/ath/wil6210/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 287 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 288 drivers/net/wireless/ath/wil6210/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 289 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 292 drivers/net/wireless/ath/wil6210/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 293 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4) | BIT 294 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_ASSOC_RESP >> 4) | BIT 295 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 296 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 297 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_REASSOC_RESP >> 4), BIT 298 drivers/net/wireless/ath/wil6210/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 299 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 300 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 301 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 302 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 303 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 304 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) BIT 307 drivers/net/wireless/ath/wil6210/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 308 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 309 drivers/net/wireless/ath/wil6210/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 310 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 313 drivers/net/wireless/ath/wil6210/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 314 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 315 drivers/net/wireless/ath/wil6210/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 316 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 319 drivers/net/wireless/ath/wil6210/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 320 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 321 drivers/net/wireless/ath/wil6210/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 322 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 2276 drivers/net/wireless/ath/wil6210/cfg80211.c if (!(params->sta_flags_mask & BIT(NL80211_STA_FLAG_AUTHORIZED))) BIT 2296 drivers/net/wireless/ath/wil6210/cfg80211.c authorize = params->sta_flags_set & BIT(NL80211_STA_FLAG_AUTHORIZED); BIT 2637 drivers/net/wireless/ath/wil6210/cfg80211.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 2638 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(NL80211_IFTYPE_AP) | BIT 2639 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 2640 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(NL80211_IFTYPE_P2P_GO) | BIT 2641 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(NL80211_IFTYPE_P2P_DEVICE) | BIT 2642 drivers/net/wireless/ath/wil6210/cfg80211.c BIT(NL80211_IFTYPE_MONITOR); BIT 2876 drivers/net/wireless/ath/wil6210/cfg80211.c if (rf_modules_vec >= BIT(WMI_MAX_RF_MODULES_NUM)) { BIT 2910 drivers/net/wireless/ath/wil6210/cfg80211.c if (!(rf_modules_vec & BIT(i))) BIT 3028 drivers/net/wireless/ath/wil6210/cfg80211.c rf_modules_vec |= BIT(rf_module_index); BIT 134 drivers/net/wireless/ath/wil6210/debugfs.c seq_printf(s, "%c", (d->dma.status & BIT(0)) ? BIT 251 drivers/net/wireless/ath/wil6210/debugfs.c seq_printf(s, "%c", (*sdword_0 & BIT(31)) ? BIT 254 drivers/net/wireless/ath/wil6210/debugfs.c seq_printf(s, "%c", (*sdword_0 & BIT(31)) ? BIT 1491 drivers/net/wireless/ath/wil6210/debugfs.c #define CHECK_QSTATE(x) (state & BIT(__QUEUE_STATE_ ## x)) ? \ BIT 190 drivers/net/wireless/ath/wil6210/fw.h #define WIL_FW_GW_CTL_BUSY BIT(29) /* gateway busy performing operation */ BIT 191 drivers/net/wireless/ath/wil6210/fw.h #define WIL_FW_GW_CTL_RUN BIT(30) /* start gateway operation */ BIT 480 drivers/net/wireless/ath/wil6210/interrupt.c isr &= ~(BIT(25) - 1UL); BIT 1127 drivers/net/wireless/ath/wil6210/main.c wil_s(wil, RGF_HP_CTRL, BIT(15)); BIT 1146 drivers/net/wireless/ath/wil6210/main.c wil_c(wil, RGF_USER_USAGE_6, BIT(0)); BIT 1271 drivers/net/wireless/ath/wil6210/main.c BIT(WIL_PLATFORM_FEATURE_FW_EXT_CLK_CONTROL) : 0; BIT 1274 drivers/net/wireless/ath/wil6210/main.c features |= BIT(WIL_PLATFORM_FEATURE_TRIPLE_MSI); BIT 1607 drivers/net/wireless/ath/wil6210/main.c unsigned long status_flags = BIT(wil_status_resetting); BIT 1671 drivers/net/wireless/ath/wil6210/main.c status_flags |= BIT(wil_status_suspending); BIT 179 drivers/net/wireless/ath/wil6210/pmc.c d->dma.d0 = BIT(9) | RX_DMA_D0_CMD_DMA_IT; BIT 328 drivers/net/wireless/ath/wil6210/rx_reorder.c wil->amsdu_en && (param_set & BIT(0)); BIT 329 drivers/net/wireless/ath/wil6210/rx_reorder.c int ba_policy = param_set & BIT(1); BIT 1144 drivers/net/wireless/ath/wil6210/txrx.c d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) | BIT 1650 drivers/net/wireless/ath/wil6210/txrx.c d->dma.d0 |= (BIT(DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS)) | BIT 1656 drivers/net/wireless/ath/wil6210/txrx.c d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS); BIT 1658 drivers/net/wireless/ath/wil6210/txrx.c d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS); BIT 1683 drivers/net/wireless/ath/wil6210/txrx.c d->dma.b11 |= BIT(DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS); BIT 1710 drivers/net/wireless/ath/wil6210/txrx.c d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS); BIT 1712 drivers/net/wireless/ath/wil6210/txrx.c d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS); BIT 1719 drivers/net/wireless/ath/wil6210/txrx.c d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS) | BIT 1720 drivers/net/wireless/ath/wil6210/txrx.c BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS) | BIT 1721 drivers/net/wireless/ath/wil6210/txrx.c BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS); BIT 2079 drivers/net/wireless/ath/wil6210/txrx.c d->mac.d[0] |= BIT(MAC_CFG_DESC_TX_0_MCS_EN_POS); /* MCS 0 */ BIT 2121 drivers/net/wireless/ath/wil6210/txrx.c d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS); BIT 2122 drivers/net/wireless/ath/wil6210/txrx.c d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS); BIT 2123 drivers/net/wireless/ath/wil6210/txrx.c d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS); BIT 250 drivers/net/wireless/ath/wil6210/txrx.h #define TX_DMA_STATUS_DU BIT(0) BIT 403 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_D0_CMD_DMA_EOP BIT(8) BIT 404 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_D0_CMD_DMA_RT BIT(9) /* always 1 */ BIT 405 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_D0_CMD_DMA_IT BIT(10) /* interrupt */ BIT 406 drivers/net/wireless/ath/wil6210/txrx.h #define RX_MAC_D0_MAC_ID_VALID BIT(7) BIT 409 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_ERROR_FCS BIT(0) BIT 410 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_ERROR_MIC BIT(1) BIT 411 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_ERROR_KEY BIT(2) /* Key missing */ BIT 412 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_ERROR_REPLAY BIT(3) BIT 413 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_ERROR_L3_ERR BIT(4) BIT 414 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_ERROR_L4_ERR BIT(5) BIT 417 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_STATUS_DU BIT(0) BIT 418 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_STATUS_EOP BIT(1) BIT 419 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_STATUS_ERROR BIT(2) BIT 420 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_STATUS_MI BIT(3) /* MAC Interrupt is asserted */ BIT 421 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_STATUS_L3I BIT(4) BIT 422 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_STATUS_L4I BIT(5) BIT 423 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_STATUS_PHY_INFO BIT(6) BIT 424 drivers/net/wireless/ath/wil6210/txrx.h #define RX_DMA_STATUS_FFM BIT(7) /* EtherType Flex Filter Match */ BIT 427 drivers/net/wireless/ath/wil6210/txrx.h #define WIL_KEY_INFO_KEY_TYPE BIT(3) /* val of 1 = Pairwise, 0 = Group key */ BIT 429 drivers/net/wireless/ath/wil6210/txrx.h #define WIL_KEY_INFO_MIC BIT(8) BIT 430 drivers/net/wireless/ath/wil6210/txrx.h #define WIL_KEY_INFO_ENCR_KEY_DATA BIT(12) /* for rsn only */ BIT 1137 drivers/net/wireless/ath/wil6210/txrx_edma.c d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) | BIT 1339 drivers/net/wireless/ath/wil6210/txrx_edma.c d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) | BIT 1341 drivers/net/wireless/ath/wil6210/txrx_edma.c BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) | BIT 1342 drivers/net/wireless/ath/wil6210/txrx_edma.c BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) | BIT 1343 drivers/net/wireless/ath/wil6210/txrx_edma.c BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS); BIT 1345 drivers/net/wireless/ath/wil6210/txrx_edma.c d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) | BIT 1346 drivers/net/wireless/ath/wil6210/txrx_edma.c BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS); BIT 48 drivers/net/wireless/ath/wil6210/txrx_edma.h #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1)) BIT 49 drivers/net/wireless/ath/wil6210/txrx_edma.h #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1)) BIT 51 drivers/net/wireless/ath/wil6210/txrx_edma.h #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11) BIT 60 drivers/net/wireless/ath/wil6210/txrx_edma.h #define WIL_RX_EDMA_MID_VALID_BIT BIT(22) BIT 191 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_USER_OOB_MODE BIT(31) BIT 192 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_USER_OOB_R2_MODE BIT(30) BIT 194 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_USER_PREVENT_DEEP_SLEEP BIT(0) BIT 195 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_USER_SUPPORT_T_POWER_ON_0 BIT(1) BIT 196 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_USER_EXT_CLK BIT(2) BIT 200 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ BIT 203 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ BIT 212 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ BIT 213 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ BIT 219 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_HPAL_PERST_FROM_PAD BIT(6) BIT 220 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_CAR_PERST_RST BIT(7) BIT 222 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) BIT 226 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) BIT 228 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_OTP_SIGNATURE_ERR_TALYN_MB BIT(0) BIT 229 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_OTP_HW_SECTION_DONE_TALYN_MB BIT(2) BIT 230 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_NO_FLASH_INDICATION BIT(8) BIT 244 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) BIT 245 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ BIT 247 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) BIT 248 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) BIT 250 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) BIT 251 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) BIT 252 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) BIT 253 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ BIT 259 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) BIT 260 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) BIT 261 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) BIT 262 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) BIT 263 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) BIT 267 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) BIT 268 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) BIT 269 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) BIT 270 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) BIT 277 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) BIT 278 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) BIT 279 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) BIT 280 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) BIT 281 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) BIT 282 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) BIT 283 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) BIT 287 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) BIT 288 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) BIT 289 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) BIT 290 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) BIT 291 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) BIT 296 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) BIT 297 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) BIT 298 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) BIT 299 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) BIT 300 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) BIT 301 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) BIT 302 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) BIT 306 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) BIT 307 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) BIT 308 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) BIT 309 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) BIT 310 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) BIT 312 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_OFUL34_RDY_VALID_BUG_FIX_EN BIT(7) BIT 317 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) BIT 318 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) BIT 319 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) BIT 331 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_CAF_OSC_XTAL_EN BIT(0) BIT 333 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) BIT 336 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_BOOT_FROM_ROM BIT(31) BIT 351 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_CONTROL_0 BIT(0) BIT 355 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_RX_STATUS_IRQ BIT(WIL_RX_STATUS_IRQ_IDX) BIT 357 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_TX_STATUS_IRQ BIT(WIL_TX_STATUS_IRQ_IDX) BIT 364 drivers/net/wireless/ath/wil6210/wil6210.h #define BIT_PMU_DEVICE_RDY BIT(0) BIT 2359 drivers/net/wireless/atmel/at76c50x-usb.c priv->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); BIT 5574 drivers/net/wireless/broadcom/b43/main.c BIT(NL80211_IFTYPE_AP) | BIT 5575 drivers/net/wireless/broadcom/b43/main.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 5576 drivers/net/wireless/broadcom/b43/main.c BIT(NL80211_IFTYPE_STATION) | BIT 5578 drivers/net/wireless/broadcom/b43/main.c BIT(NL80211_IFTYPE_WDS) | BIT 5580 drivers/net/wireless/broadcom/b43/main.c BIT(NL80211_IFTYPE_ADHOC); BIT 3806 drivers/net/wireless/broadcom/b43legacy/main.c BIT(NL80211_IFTYPE_AP) | BIT 3807 drivers/net/wireless/broadcom/b43legacy/main.c BIT(NL80211_IFTYPE_STATION) | BIT 3809 drivers/net/wireless/broadcom/b43legacy/main.c BIT(NL80211_IFTYPE_WDS) | BIT 3811 drivers/net/wireless/broadcom/b43legacy/main.c BIT(NL80211_IFTYPE_ADHOC); BIT 58 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c #define RSN_CAP_PTK_REPLAY_CNTR_MASK (BIT(2) | BIT(3)) BIT 59 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c #define RSN_CAP_MFPR_MASK BIT(6) BIT 60 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c #define RSN_CAP_MFPC_MASK BIT(7) BIT 743 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c cfg->int_escan_map &= ~BIT(bucket); BIT 2502 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c sfu->mask = BIT(NL80211_STA_FLAG_WME) | BIT 2503 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_STA_FLAG_AUTHENTICATED) | BIT 2504 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_STA_FLAG_ASSOCIATED) | BIT 2505 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_STA_FLAG_AUTHORIZED); BIT 2507 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c sfu->set |= BIT(NL80211_STA_FLAG_WME); BIT 2509 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c sfu->set |= BIT(NL80211_STA_FLAG_AUTHENTICATED); BIT 2511 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c sfu->set |= BIT(NL80211_STA_FLAG_ASSOCIATED); BIT 2513 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c sfu->set |= BIT(NL80211_STA_FLAG_AUTHORIZED); BIT 2645 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c sinfo->sta_flags.mask |= BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 2647 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c sinfo->sta_flags.set |= BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 2649 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c sinfo->sta_flags.set &= ~BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 3172 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_IFTYPE_ADHOC))) { BIT 4825 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c if (!(params->sta_flags_mask & BIT(NL80211_STA_FLAG_AUTHORIZED))) BIT 4828 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c if (params->sta_flags_set & BIT(NL80211_STA_FLAG_AUTHORIZED)) BIT 4853 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c vif->mgmt_rx_reg |= BIT(mgmt_type); BIT 4855 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c vif->mgmt_rx_reg &= ~BIT(mgmt_type); BIT 6404 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 6405 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 6409 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 6410 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 6414 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 6415 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 6416 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 6417 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 6418 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 6419 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 6420 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_ACTION >> 4) BIT 6424 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 6425 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 6429 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 6430 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 6431 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 6432 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 6433 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 6434 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 6435 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(IEEE80211_STYPE_ACTION >> 4) BIT 6486 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 6487 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_IFTYPE_ADHOC) | BIT 6488 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_IFTYPE_AP); BIT 6496 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c c0_limits[i++].types = BIT(NL80211_IFTYPE_STATION); BIT 6502 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 6503 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_IFTYPE_P2P_GO) | BIT 6504 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_IFTYPE_P2P_DEVICE); BIT 6506 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c c0_limits[i++].types = BIT(NL80211_IFTYPE_P2P_DEVICE); BIT 6508 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c c0_limits[i++].types = BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 6509 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_IFTYPE_P2P_GO); BIT 6513 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c c0_limits[i++].types = BIT(NL80211_IFTYPE_AP); BIT 6526 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c p2p_limits[i++].types = BIT(NL80211_IFTYPE_STATION); BIT 6528 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c p2p_limits[i++].types = BIT(NL80211_IFTYPE_AP); BIT 6530 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c p2p_limits[i++].types = BIT(NL80211_IFTYPE_P2P_CLIENT); BIT 6532 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c p2p_limits[i++].types = BIT(NL80211_IFTYPE_P2P_DEVICE); BIT 6546 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c mbss_limits[i++].types = BIT(NL80211_IFTYPE_AP); BIT 6637 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c addr[0] |= BIT(1); BIT 6649 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c wiphy->bss_select_support = BIT(NL80211_BSS_SELECT_ATTR_RSSI) | BIT 6650 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_BSS_SELECT_ATTR_BAND_PREF) | BIT 6651 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c BIT(NL80211_BSS_SELECT_ATTR_RSSI_ADJUST); BIT 1344 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c pmu_cc3_mask = BIT(2); BIT 35 drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c #define RXS_PBPRES BIT(2) BIT 156 drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.h BRCMF_NETIF_STOP_REASON_FWS_FC = BIT(0), BIT 157 drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.h BRCMF_NETIF_STOP_REASON_FLOW = BIT(1), BIT 158 drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.h BRCMF_NETIF_STOP_REASON_DISCONNECTED = BIT(2) BIT 71 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c if (feats & BIT(id)) BIT 75 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c if (quirks & BIT(id)) BIT 93 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c { "01-6cb8e269", BIT(BRCMF_FEAT_MONITOR) }, BIT 95 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c { "01-c47a91a4", BIT(BRCMF_FEAT_MONITOR) }, BIT 97 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c { "01-801fb449", BIT(BRCMF_FEAT_MONITOR_FMT_HW_RX_HDR) }, BIT 99 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c { "01-d2cbb8fd", BIT(BRCMF_FEAT_MONITOR_FMT_HW_RX_HDR) }, BIT 120 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c if (feat_flags & BIT(i)) BIT 145 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c ifp->drvr->feat_flags |= BIT(id); BIT 166 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c ifp->drvr->feat_flags |= BIT(id); BIT 196 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c ifp->drvr->feat_flags |= BIT(id); BIT 258 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c ifp->drvr->feat_flags |= BIT(BRCMF_FEAT_WOWL_ARP_ND); BIT 261 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c BIT(BRCMF_FEAT_WOWL_ND); BIT 264 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c BIT(BRCMF_FEAT_WOWL_GTK); BIT 271 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c ifp->drvr->feat_flags &= ~BIT(BRCMF_FEAT_MBSS); BIT 284 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c ifp->drvr->feat_flags |= BIT(BRCMF_FEAT_SCAN_RANDOM_MAC); BIT 299 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c drvr->chip_quirks |= BIT(BRCMF_FEAT_QUIRK_AUTO_AUTH); BIT 302 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c drvr->chip_quirks |= BIT(BRCMF_FEAT_QUIRK_NEED_MPC); BIT 318 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c return (ifp->drvr->feat_flags & BIT(id)); BIT 324 drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c return (ifp->drvr->chip_quirks & BIT(quirk)); BIT 706 drivers/net/wireless/broadcom/brcm80211/brcmfmac/firmware.c mapping_table[i].revmask & BIT(chiprev)) BIT 62 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h #define BRCMF_WSEC_PASSPHRASE BIT(0) BIT 144 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h #define BRCMF_TXBF_SU_BFE_CAP BIT(0) BIT 145 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h #define BRCMF_TXBF_MU_BFE_CAP BIT(1) BIT 146 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h #define BRCMF_TXBF_SU_BFR_CAP BIT(0) BIT 147 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h #define BRCMF_TXBF_MU_BFR_CAP BIT(1) BIT 153 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h #define BRCMF_PFN_MAC_OUI_ONLY BIT(0) BIT 154 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h #define BRCMF_PFN_SET_MAC_UNASSOC BIT(1) BIT 949 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h #define BRCMF_PNO_REPORT_NO_BATCH BIT(2) BIT 983 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h BRCMF_GSCAN_CFG_FLAGS_ALL_RESULTS = BIT(0), BIT 984 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h BRCMF_GSCAN_CFG_ALL_BUCKETS_IN_1ST_SCAN = BIT(3), BIT 985 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h BRCMF_GSCAN_CFG_FLAGS_CHANGE_ONLY = BIT(7), BIT 811 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c return closed || !(entry->ac_bitmap & BIT(fifo)); BIT 1363 drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c if ((ifp->vif->mgmt_rx_reg & BIT(mgmt_type)) == 0) BIT 1901 drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c if ((vif->mgmt_rx_reg & BIT(mgmt_type)) == 0) BIT 111 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c flags = BIT(BRCMF_PNO_IMMEDIATE_SCAN_BIT) | BIT 112 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c BIT(BRCMF_PNO_ENABLE_ADAPTSCAN_BIT); BIT 137 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c flags |= BIT(BRCMF_PNO_ENABLE_BD_SCAN_BIT); BIT 579 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c bucket_map |= BIT(i); BIT 584 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c bucket_map |= BIT(i); BIT 34 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h #define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT BIT(1) BIT 35 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h #define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT BIT(2) BIT 36 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h #define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC BIT(3) BIT 39 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h #define SDIO_CCCR_IEN_FUNC0 BIT(0) BIT 40 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h #define SDIO_CCCR_IEN_FUNC1 BIT(1) BIT 41 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h #define SDIO_CCCR_IEN_FUNC2 BIT(2) BIT 44 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h #define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET BIT(1) BIT 47 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h #define SDIO_CCCR_BRCM_SEPINT_MASK BIT(0) BIT 48 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h #define SDIO_CCCR_BRCM_SEPINT_OE BIT(1) BIT 49 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h #define SDIO_CCCR_BRCM_SEPINT_ACT_HI BIT(2) BIT 1100 drivers/net/wireless/broadcom/brcm80211/brcmsmac/mac80211_if.c hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 1101 drivers/net/wireless/broadcom/brcm80211/brcmsmac/mac80211_if.c BIT(NL80211_IFTYPE_AP) | BIT 1102 drivers/net/wireless/broadcom/brcm80211/brcmsmac/mac80211_if.c BIT(NL80211_IFTYPE_ADHOC); BIT 77 drivers/net/wireless/broadcom/brcm80211/include/brcmu_wifi.h #define WLC_BW_20MHZ_BIT BIT(0) BIT 78 drivers/net/wireless/broadcom/brcm80211/include/brcmu_wifi.h #define WLC_BW_40MHZ_BIT BIT(1) BIT 79 drivers/net/wireless/broadcom/brcm80211/include/brcmu_wifi.h #define WLC_BW_80MHZ_BIT BIT(2) BIT 80 drivers/net/wireless/broadcom/brcm80211/include/brcmu_wifi.h #define WLC_BW_160MHZ_BIT BIT(3) BIT 262 drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h #define CC_SR_CTL0_ENABLE_MASK BIT(0) BIT 140 drivers/net/wireless/intel/ipw2x00/libipw_module.c ieee->wdev.wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) BIT 141 drivers/net/wireless/intel/ipw2x00/libipw_module.c | BIT(NL80211_IFTYPE_ADHOC); BIT 3542 drivers/net/wireless/intel/iwlegacy/3945-mac.c BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC); BIT 551 drivers/net/wireless/intel/iwlegacy/3945.h #define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24) BIT 552 drivers/net/wireless/intel/iwlegacy/3945.h #define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) (BIT(_ch) << 16) BIT 697 drivers/net/wireless/intel/iwlegacy/4965-calib.c active_chains |= BIT(first_chain); BIT 840 drivers/net/wireless/intel/iwlegacy/4965-mac.c if (valid & BIT(ind)) { BIT 979 drivers/net/wireless/intel/iwlegacy/4965-mac.c rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS; BIT 1122 drivers/net/wireless/intel/iwlegacy/4965-mac.c res = (chain_bitmap & BIT(0)) >> 0; BIT 1123 drivers/net/wireless/intel/iwlegacy/4965-mac.c res += (chain_bitmap & BIT(1)) >> 1; BIT 1124 drivers/net/wireless/intel/iwlegacy/4965-mac.c res += (chain_bitmap & BIT(2)) >> 2; BIT 1125 drivers/net/wireless/intel/iwlegacy/4965-mac.c res += (chain_bitmap & BIT(3)) >> 3; BIT 1589 drivers/net/wireless/intel/iwlegacy/4965-mac.c rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS; BIT 3827 drivers/net/wireless/intel/iwlegacy/4965-mac.c rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS; BIT 5750 drivers/net/wireless/intel/iwlegacy/4965-mac.c BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC); BIT 6462 drivers/net/wireless/intel/iwlegacy/4965-mac.c il->hw_params.ht40_channel = BIT(NL80211_BAND_5GHZ); BIT 1088 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_TX_FIFO_BK_MSK cpu_to_le32(BIT(0)) BIT 1089 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_TX_FIFO_BE_MSK cpu_to_le32(BIT(1)) BIT 1090 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_TX_FIFO_VI_MSK cpu_to_le32(BIT(2)) BIT 1091 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_TX_FIFO_VO_MSK cpu_to_le32(BIT(3)) BIT 2085 drivers/net/wireless/intel/iwlegacy/commands.h #define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0) BIT 2086 drivers/net/wireless/intel/iwlegacy/commands.h #define BT_ENABLE_PRIORITY BIT(1) BIT 2273 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0)) BIT 2274 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2)) BIT 2275 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3)) BIT 2385 drivers/net/wireless/intel/iwlegacy/commands.h #define IL39_SCAN_PROBE_MASK(n) ((BIT(n) | (BIT(n) - BIT(1)))) BIT 2404 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1)))) BIT 2599 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_PROBE_STATUS_TX_FAILED BIT(0) BIT 2601 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_PROBE_STATUS_FAIL_TTL BIT(1) BIT 2602 drivers/net/wireless/intel/iwlegacy/commands.h #define IL_PROBE_STATUS_FAIL_BT BIT(2) BIT 3386 drivers/net/wireless/intel/iwlegacy/common.c if (il->hw_params.ht40_channel & BIT(band)) { BIT 2105 drivers/net/wireless/intel/iwlegacy/common.h #define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */ BIT 2106 drivers/net/wireless/intel/iwlegacy/common.h #define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */ BIT 2107 drivers/net/wireless/intel/iwlegacy/common.h #define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of BIT 2109 drivers/net/wireless/intel/iwlegacy/common.h #define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211; BIT 2111 drivers/net/wireless/intel/iwlegacy/common.h #define IL_STA_BCAST BIT(4) /* this station is the special bcast station */ BIT 2714 drivers/net/wireless/intel/iwlegacy/common.h #define ANT_A BIT(0) BIT 2715 drivers/net/wireless/intel/iwlegacy/common.h #define ANT_B BIT(1) BIT 2717 drivers/net/wireless/intel/iwlegacy/common.h #define ANT_C BIT(2) BIT 53 drivers/net/wireless/intel/iwlwifi/cfg/1000.c .ht40_bands = BIT(NL80211_BAND_2GHZ), BIT 78 drivers/net/wireless/intel/iwlwifi/cfg/2000.c .ht40_bands = BIT(NL80211_BAND_2GHZ), BIT 155 drivers/net/wireless/intel/iwlwifi/cfg/22000.c .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ), BIT 51 drivers/net/wireless/intel/iwlwifi/cfg/5000.c .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ), BIT 99 drivers/net/wireless/intel/iwlwifi/cfg/6000.c .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ), BIT 147 drivers/net/wireless/intel/iwlwifi/cfg/7000.c .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ), BIT 270 drivers/net/wireless/intel/iwlwifi/cfg/7000.c .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ), BIT 112 drivers/net/wireless/intel/iwlwifi/cfg/8000.c .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ), BIT 98 drivers/net/wireless/intel/iwlwifi/cfg/9000.c .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ), BIT 296 drivers/net/wireless/intel/iwlwifi/dvm/agn.h #define IWL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */ BIT 297 drivers/net/wireless/intel/iwlwifi/dvm/agn.h #define IWL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */ BIT 298 drivers/net/wireless/intel/iwlwifi/dvm/agn.h #define IWL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of BIT 300 drivers/net/wireless/intel/iwlwifi/dvm/agn.h #define IWL_STA_LOCAL BIT(3) /* station state not directed by mac80211; BIT 302 drivers/net/wireless/intel/iwlwifi/dvm/agn.h #define IWL_STA_BCAST BIT(4) /* this station is the special bcast station */ BIT 375 drivers/net/wireless/intel/iwlwifi/dvm/agn.h return BIT(ant_idx) << RATE_MCS_ANT_POS; BIT 853 drivers/net/wireless/intel/iwlwifi/dvm/calib.c active_chains |= BIT(first_chain); BIT 959 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_SCD_BK_MSK BIT(0) BIT 960 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_SCD_BE_MSK BIT(1) BIT 961 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_SCD_VI_MSK BIT(2) BIT 962 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_SCD_VO_MSK BIT(3) BIT 963 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_SCD_MGMT_MSK BIT(3) BIT 966 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_PAN_SCD_BK_MSK BIT(4) BIT 967 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_PAN_SCD_BE_MSK BIT(5) BIT 968 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_PAN_SCD_VI_MSK BIT(6) BIT 969 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_PAN_SCD_VO_MSK BIT(7) BIT 970 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_PAN_SCD_MGMT_MSK BIT(7) BIT 971 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_PAN_SCD_MULTICAST_MSK BIT(8) BIT 975 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_DROP_ALL BIT(1) BIT 1810 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0) BIT 1811 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define BT_ENABLE_PRIORITY BIT(1) BIT 1812 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define BT_ENABLE_2_WIRE BIT(2) BIT 1857 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_FLAG_CHANNEL_INHIBITION BIT(0) BIT 1859 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_FLAG_COEX_MODE_MASK (BIT(3)|BIT(4)|BIT(5)) BIT 1866 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_FLAG_UCODE_DEFAULT BIT(6) BIT 1868 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7) BIT 1897 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_VALID_ENABLE_FLAGS cpu_to_le16(BIT(0)) BIT 1898 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_VALID_BOOST cpu_to_le16(BIT(1)) BIT 1899 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_VALID_MAX_KILL cpu_to_le16(BIT(2)) BIT 1900 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_VALID_3W_TIMERS cpu_to_le16(BIT(3)) BIT 1901 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_VALID_KILL_ACK_MASK cpu_to_le16(BIT(4)) BIT 1902 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_VALID_KILL_CTS_MASK cpu_to_le16(BIT(5)) BIT 1903 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_VALID_REDUCED_TX_PWR cpu_to_le16(BIT(6)) BIT 1904 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_VALID_3W_LUT cpu_to_le16(BIT(7)) BIT 1915 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_REDUCED_TX_PWR BIT(0) BIT 1962 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWLAGN_BT_SCO_ACTIVE cpu_to_le32(BIT(0)) BIT 2131 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0)) BIT 2132 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0)) BIT 2133 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1)) BIT 2134 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2)) BIT 2135 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3)) BIT 2136 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_FAST_PD cpu_to_le16(BIT(4)) BIT 2137 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5)) BIT 2138 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6)) BIT 2139 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7)) BIT 2140 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8)) BIT 2141 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9)) BIT 2262 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1)))) BIT 2340 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_SCAN_FLAGS_ACTION_FRAME_TX = BIT(1), BIT 2415 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_PROBE_STATUS_TX_FAILED BIT(0) BIT 2417 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_PROBE_STATUS_FAIL_TTL BIT(1) BIT 2418 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_PROBE_STATUS_FAIL_BT BIT(2) BIT 3130 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_RX_BB_IDX = BIT(0), BIT 3131 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_DC_IDX = BIT(1), BIT 3132 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_LO_IDX = BIT(2), BIT 3133 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_TX_IQ_IDX = BIT(3), BIT 3134 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_RX_IQ_IDX = BIT(4), BIT 3135 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_NOISE_IDX = BIT(5), BIT 3136 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_CRYSTAL_IDX = BIT(6), BIT 3137 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(7), BIT 3138 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_PAPD_IDX = BIT(8), BIT 3139 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(9), BIT 3140 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWL_CALIB_CFG_TX_PWR_IDX = BIT(10), BIT 3160 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0)) BIT 3741 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_D3_WAKEUP_RFKILL = BIT(0), BIT 3742 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_D3_WAKEUP_SYSASSERT = BIT(1), BIT 3775 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0), BIT 3776 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1), BIT 3777 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_WOWLAN_WAKEUP_BEACON_MISS = BIT(2), BIT 3778 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3), BIT 3779 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4), BIT 3780 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(5), BIT 3781 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(6), BIT 3782 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_WOWLAN_WAKEUP_ALWAYS = BIT(7), BIT 3783 drivers/net/wireless/intel/iwlwifi/dvm/commands.h IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT = BIT(8), BIT 3908 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS BIT(1) /* reserved */ BIT 3909 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET BIT(2) /* reserved */ BIT 3910 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE BIT(3) /* reserved */ BIT 3911 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF BIT(4) BIT 3912 drivers/net/wireless/intel/iwlwifi/dvm/commands.h #define IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE BIT(5) BIT 620 drivers/net/wireless/intel/iwlwifi/dvm/dev.h IWL_SENSITIVITY_CALIB_DISABLED = BIT(0), BIT 621 drivers/net/wireless/intel/iwlwifi/dvm/dev.h IWL_CHAIN_NOISE_CALIB_DISABLED = BIT(1), BIT 622 drivers/net/wireless/intel/iwlwifi/dvm/dev.h IWL_TX_POWER_CALIB_DISABLED = BIT(2), BIT 912 drivers/net/wireless/intel/iwlwifi/dvm/dev.h if (priv->valid_contexts & BIT(ctx->ctxid)) BIT 132 drivers/net/wireless/intel/iwlwifi/dvm/lib.c if ((priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))) BIT 765 drivers/net/wireless/intel/iwlwifi/dvm/lib.c res = (chain_bitmap & BIT(0)) >> 0; BIT 766 drivers/net/wireless/intel/iwlwifi/dvm/lib.c res += (chain_bitmap & BIT(1)) >> 1; BIT 767 drivers/net/wireless/intel/iwlwifi/dvm/lib.c res += (chain_bitmap & BIT(2)) >> 2; BIT 768 drivers/net/wireless/intel/iwlwifi/dvm/lib.c res += (chain_bitmap & BIT(3)) >> 3; BIT 852 drivers/net/wireless/intel/iwlwifi/dvm/lib.c if (valid & BIT(ind)) BIT 49 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c .types = BIT(NL80211_IFTYPE_STATION), BIT 53 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c .types = BIT(NL80211_IFTYPE_AP), BIT 60 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c .types = BIT(NL80211_IFTYPE_STATION), BIT 140 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_AP)) { BIT 1102 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c scd_queues = BIT(priv->trans->trans_cfg->base_params->num_of_queues) - 1; BIT 1103 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c scd_queues &= ~(BIT(IWL_IPAN_CMD_QUEUE_NUM) | BIT 1104 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c BIT(IWL_DEFAULT_CMD_QUEUE_NUM)); BIT 1300 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c BIT(tmp->vif->type)) { BIT 1307 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c if (!(possible_modes & BIT(viftype))) BIT 1440 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c if (!(interface_modes & BIT(newtype))) { BIT 1445 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c if (ctx->exclusive_interface_modes & BIT(newtype)) { BIT 610 drivers/net/wireless/intel/iwlwifi/dvm/main.c priv->valid_contexts = BIT(IWL_RXON_CTX_BSS); BIT 612 drivers/net/wireless/intel/iwlwifi/dvm/main.c priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN); BIT 627 drivers/net/wireless/intel/iwlwifi/dvm/main.c BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_MONITOR); BIT 629 drivers/net/wireless/intel/iwlwifi/dvm/main.c BIT(NL80211_IFTYPE_STATION); BIT 650 drivers/net/wireless/intel/iwlwifi/dvm/main.c BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP); BIT 729 drivers/net/wireless/intel/iwlwifi/dvm/rs.c mask = BIT(i); BIT 2818 drivers/net/wireless/intel/iwlwifi/dvm/rs.c lq_sta->active_legacy_rate |= BIT(sband->bitrates[i].hw_value); BIT 521 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c if (priv->valid_contexts == BIT(IWL_RXON_CTX_BSS)) BIT 766 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(0); BIT 770 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(1); BIT 775 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(2); BIT 779 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(3); BIT 784 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(4); BIT 791 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(5); BIT 796 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(6); BIT 802 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(7); BIT 808 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(8); BIT 815 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(9); BIT 820 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c errors |= BIT(10); BIT 937 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c ofdm |= BIT(hw - IWL_FIRST_OFDM_RATE); BIT 943 drivers/net/wireless/intel/iwlwifi/dvm/rxon.c cck |= BIT(hw); BIT 660 drivers/net/wireless/intel/iwlwifi/dvm/tx.c if (iwlagn_txfifo_flush(priv, BIT(txq_id))) BIT 69 drivers/net/wireless/intel/iwlwifi/fw/api/alive.h #define ALIVE_RESP_UCODE_OK BIT(0) BIT 70 drivers/net/wireless/intel/iwlwifi/fw/api/alive.h #define ALIVE_RESP_RFKILL BIT(1) BIT 97 drivers/net/wireless/intel/iwlwifi/fw/api/alive.h #define IWL_ALIVE_FLG_RFKILL BIT(0) BIT 206 drivers/net/wireless/intel/iwlwifi/fw/api/alive.h ERROR_RECOVERY_UPDATE_DB = BIT(0), BIT 207 drivers/net/wireless/intel/iwlwifi/fw/api/alive.h ERROR_RECOVERY_END_OF_RECOVERY = BIT(1), BIT 146 drivers/net/wireless/intel/iwlwifi/fw/api/binding.h IWL_QUOTA_LOW_LATENCY_TX = BIT(0), BIT 147 drivers/net/wireless/intel/iwlwifi/fw/api/binding.h IWL_QUOTA_LOW_LATENCY_RX = BIT(1), BIT 70 drivers/net/wireless/intel/iwlwifi/fw/api/coex.h #define BITS(nb) (BIT(nb) - 1) BIT 81 drivers/net/wireless/intel/iwlwifi/fw/api/coex.h #define BT_REDUCED_TX_POWER_BIT BIT(7) BIT 91 drivers/net/wireless/intel/iwlwifi/fw/api/coex.h BT_COEX_MPLUT_ENABLED = BIT(0), BIT 92 drivers/net/wireless/intel/iwlwifi/fw/api/coex.h BT_COEX_MPLUT_BOOST_ENABLED = BIT(1), BIT 93 drivers/net/wireless/intel/iwlwifi/fw/api/coex.h BT_COEX_SYNC2SCO_ENABLED = BIT(2), BIT 94 drivers/net/wireless/intel/iwlwifi/fw/api/coex.h BT_COEX_CORUN_ENABLED = BIT(3), BIT 95 drivers/net/wireless/intel/iwlwifi/fw/api/coex.h BT_COEX_HIGH_BAND_RET = BIT(4), BIT 101 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_XTAL_IDX = BIT(0), BIT 102 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(1), BIT 103 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_VOLTAGE_READ_IDX = BIT(2), BIT 104 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_PAPD_IDX = BIT(3), BIT 105 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_TX_PWR_IDX = BIT(4), BIT 106 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_DC_IDX = BIT(5), BIT 107 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_BB_FILTER_IDX = BIT(6), BIT 108 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_LO_LEAKAGE_IDX = BIT(7), BIT 109 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_TX_IQ_IDX = BIT(8), BIT 110 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_TX_IQ_SKEW_IDX = BIT(9), BIT 111 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_RX_IQ_IDX = BIT(10), BIT 112 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_RX_IQ_SKEW_IDX = BIT(11), BIT 113 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(12), BIT 114 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_CHAIN_NOISE_IDX = BIT(13), BIT 115 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_DISCONNECTED_ANT_IDX = BIT(14), BIT 116 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_ANT_COUPLING_IDX = BIT(15), BIT 117 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_DAC_IDX = BIT(16), BIT 118 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_ABS_IDX = BIT(17), BIT 119 drivers/net/wireless/intel/iwlwifi/fw/api/config.h IWL_CALIB_CFG_AGC_IDX = BIT(18), BIT 72 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WAKEUP_D3_CONFIG_FW_ERROR = BIT(0), BIT 100 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_D3_PROTO_OFFLOAD_ARP = BIT(0), BIT 101 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_D3_PROTO_OFFLOAD_NS = BIT(1), BIT 102 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_D3_PROTO_IPV4_VALID = BIT(2), BIT 103 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_D3_PROTO_IPV6_VALID = BIT(3), BIT 363 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0), BIT 364 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1), BIT 365 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BEACON_MISS = BIT(2), BIT 366 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3), BIT 367 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4), BIT 368 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(5), BIT 369 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(6), BIT 370 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_ENABLE_NET_DETECT = BIT(7), BIT 371 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_RF_KILL_DEASSERT = BIT(8), BIT 372 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_REMOTE_LINK_LOSS = BIT(9), BIT 373 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_REMOTE_SIGNATURE_TABLE = BIT(10), BIT 374 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_REMOTE_TCP_EXTERNAL = BIT(11), BIT 375 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_REMOTE_WAKEUP_PACKET = BIT(12), BIT 376 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_IOAC_MAGIC_PACKET = BIT(13), BIT 377 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_HOST_TIMER = BIT(14), BIT 378 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_RX_FRAME = BIT(15), BIT 379 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BCN_FILTERING = BIT(16), BIT 383 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IS_11W_ASSOC = BIT(0), BIT 384 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h ENABLE_L3_FILTERING = BIT(1), BIT 385 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h ENABLE_NBNS_FILTERING = BIT(2), BIT 386 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h ENABLE_DHCP_FILTERING = BIT(3), BIT 387 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h ENABLE_STORE_BEACON = BIT(4), BIT 491 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_MAGIC_PACKET = BIT(0), BIT 492 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_PATTERN = BIT(1), BIT 493 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_DISCONNECTION_ON_MISSED_BEACON = BIT(2), BIT 494 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_DISCONNECTION_ON_DEAUTH = BIT(3), BIT 495 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_GTK_REKEY_FAILURE = BIT(4), BIT 496 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_RFKILL_DEASSERTED = BIT(5), BIT 497 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_UCODE_ERROR = BIT(6), BIT 498 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_EAPOL_REQUEST = BIT(7), BIT 499 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_FOUR_WAY_HANDSHAKE = BIT(8), BIT 500 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_REM_WAKE_LINK_LOSS = BIT(9), BIT 501 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_REM_WAKE_SIGNATURE_TABLE = BIT(10), BIT 502 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_REM_WAKE_TCP_EXTERNAL = BIT(11), BIT 503 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_REM_WAKE_WAKEUP_PACKET = BIT(12), BIT 504 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_IOAC_MAGIC_PACKET = BIT(13), BIT 505 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_D3_WAKEUP_HOST_TIMER = BIT(14), BIT 506 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_RXFRAME_FILTERED_IN = BIT(15), BIT 507 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WOWLAN_WAKEUP_BY_BEACON_FILTERED_IN = BIT(16), BIT 508 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WAKEUP_BY_11W_UNPROTECTED_DEAUTH_OR_DISASSOC = BIT(17), BIT 509 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WAKEUP_BY_PATTERN_IPV4_TCP_SYN = BIT(18), BIT 510 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WAKEUP_BY_PATTERN_IPV4_TCP_SYN_WILDCARD = BIT(19), BIT 511 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WAKEUP_BY_PATTERN_IPV6_TCP_SYN = BIT(20), BIT 512 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h IWL_WAKEUP_BY_PATTERN_IPV6_TCP_SYN_WILDCARD = BIT(21), BIT 548 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h #define IWL_WOWLAN_GTK_IDX_MASK (BIT(0) | BIT(1)) BIT 166 drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h IWL_CHANNEL_ESTIMATION_ENABLE = BIT(0), BIT 167 drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h IWL_CHANNEL_ESTIMATION_TIMER = BIT(1), BIT 168 drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h IWL_CHANNEL_ESTIMATION_COUNTER = BIT(2), BIT 201 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_CHAN_INFO = BIT(0), BIT 202 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_TOA_OFFSET = BIT(1), BIT 203 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_COMMON_CALIB = BIT(2), BIT 204 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_SPECIFIC_CALIB = BIT(3), BIT 205 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_BSSID = BIT(4), BIT 206 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_TX_ANT = BIT(5), BIT 207 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_ALGO_TYPE = BIT(6), BIT 208 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_NON_ASAP_SUPPORT = BIT(7), BIT 209 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_STATISTICS_REPORT_SUPPORT = BIT(8), BIT 210 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_MCSI_NOTIF_SUPPORT = BIT(9), BIT 211 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_FAST_ALGO_SUPPORT = BIT(10), BIT 212 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_RETRY_ON_ALGO_FAIL = BIT(11), BIT 213 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_CMD_VALID_STA_ID = BIT(12), BIT 230 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_FLAGS_NON_ASAP_SUPPORT = BIT(0), BIT 231 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_FLAGS_REPORT_STATISTICS = BIT(1), BIT 232 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_FLAGS_REPORT_MCSI = BIT(2), BIT 233 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_FLAGS_ALGO_TYPE = BIT(3) | BIT(4) | BIT(5), BIT 234 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_FLAGS_TOA_OFFSET_MODE = BIT(6), BIT 235 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_FLAGS_COMMON_CALIB_MODE = BIT(7), BIT 236 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_FLAGS_SPECIFIC_CALIB_MODE = BIT(8), BIT 237 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_FLAGS_FAST_ALGO_SUPPORT = BIT(9), BIT 238 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_RESPONDER_FLAGS_RETRY_ON_ALGO_FAIL = BIT(10), BIT 396 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_INITIATOR_AP_FLAGS_ASAP = BIT(1), BIT 397 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_INITIATOR_AP_FLAGS_LCI_REQUEST = BIT(2), BIT 398 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_INITIATOR_AP_FLAGS_CIVIC_REQUEST = BIT(3), BIT 399 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_INITIATOR_AP_FLAGS_DYN_ACK = BIT(4), BIT 400 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_INITIATOR_AP_FLAGS_ALGO_LR = BIT(5), BIT 401 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_INITIATOR_AP_FLAGS_ALGO_FFT = BIT(6), BIT 402 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_INITIATOR_AP_FLAGS_MCSI_REPORT = BIT(8), BIT 472 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_FAST_ALGO_DISABLED = BIT(0), BIT 473 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_RX_CHAIN_SEL_A = BIT(1), BIT 474 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_RX_CHAIN_SEL_B = BIT(2), BIT 475 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_RX_CHAIN_SEL_C = BIT(3), BIT 476 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_TX_CHAIN_SEL_A = BIT(4), BIT 477 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_TX_CHAIN_SEL_B = BIT(5), BIT 478 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_TX_CHAIN_SEL_C = BIT(6), BIT 479 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_MACADDR_RANDOM = BIT(7), BIT 480 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_SPECIFIC_CALIB = BIT(15), BIT 481 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_COMMON_CALIB = BIT(16), BIT 482 drivers/net/wireless/intel/iwlwifi/fw/api/location.h IWL_TOF_INITIATOR_FLAGS_NON_ASAP_SUPPORT = BIT(20), BIT 882 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_NON_ASAP_STARTED = BIT(0), BIT 883 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_NON_ASAP_IN_WIN = BIT(1), BIT 884 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_NON_ASAP_OUT_WIN = BIT(2), BIT 885 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_TRIGGER_DUP = BIT(3), BIT 886 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_DUP = BIT(4), BIT 887 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_DUP_IN_WIN = BIT(5), BIT 888 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_DUP_OUT_WIN = BIT(6), BIT 889 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_SCHED_SUCCESS = BIT(7), BIT 890 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_ASAP_REQ = BIT(8), BIT 891 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_NON_ASAP_REQ = BIT(9), BIT 892 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_ASAP_RESP = BIT(10), BIT 893 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_NON_ASAP_RESP = BIT(11), BIT 894 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_FAIL_INITIATOR_INACTIVE = BIT(12), BIT 895 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_FAIL_INITIATOR_OUT_WIN = BIT(13), BIT 896 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_FAIL_INITIATOR_RETRY_LIM = BIT(14), BIT 897 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_FAIL_NEXT_SERVED = BIT(15), BIT 898 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_FAIL_TRIGGER_ERR = BIT(16), BIT 899 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_FAIL_GC = BIT(17), BIT 900 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_SUCCESS = BIT(18), BIT 901 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_INTEL_IE = BIT(19), BIT 902 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_INITIATOR_ACTIVE = BIT(20), BIT 903 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_MEASUREMENTS_AVAILABLE = BIT(21), BIT 904 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_TRIGGER_UNKNOWN = BIT(22), BIT 905 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_PROCESS_FAIL = BIT(23), BIT 906 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_ACK = BIT(24), BIT 907 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_NACK = BIT(25), BIT 908 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_INVALID_INITIATOR_ID = BIT(26), BIT 909 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_TIMER_MIN_DELTA = BIT(27), BIT 910 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_INITIATOR_REMOVED = BIT(28), BIT 911 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_INITIATOR_ADDED = BIT(29), BIT 912 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_ERR_LIST_FULL = BIT(30), BIT 913 drivers/net/wireless/intel/iwlwifi/fw/api/location.h FTM_RESP_STAT_INITIATOR_SCHED_NOW = BIT(31), BIT 96 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_PROT_FLG_TGG_PROTECT = BIT(3), BIT 97 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_PROT_FLG_HT_PROT = BIT(23), BIT 98 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_PROT_FLG_FAT_PROT = BIT(24), BIT 99 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_PROT_FLG_SELF_CTS_EN = BIT(30), BIT 102 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h #define MAC_FLG_SHORT_SLOT BIT(4) BIT 103 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h #define MAC_FLG_SHORT_PREAMBLE BIT(5) BIT 193 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h TWT_SUPPORTED = BIT(0), BIT 283 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_FILTER_IN_PROMISC = BIT(0), BIT 284 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_FILTER_IN_CONTROL_AND_MGMT = BIT(1), BIT 285 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_FILTER_ACCEPT_GRP = BIT(2), BIT 286 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_FILTER_DIS_DECRYPT = BIT(3), BIT 287 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_FILTER_DIS_GRP_DECRYPT = BIT(4), BIT 288 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_FILTER_IN_BEACON = BIT(6), BIT 289 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_FILTER_OUT_BCAST = BIT(8), BIT 290 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_FILTER_IN_CRC32 = BIT(11), BIT 291 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_FILTER_IN_PROBE_REQUEST = BIT(12), BIT 295 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_FILTER_IN_11AX = BIT(14), BIT 306 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_QOS_FLG_UPDATE_EDCA = BIT(0), BIT 307 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_QOS_FLG_TGN = BIT(1), BIT 308 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h MAC_QOS_FLG_TXOP_TYPE = BIT(4), BIT 508 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h STA_CTXT_HE_REF_BSSID_VALID = BIT(4), BIT 509 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h STA_CTXT_HE_BSS_COLOR_DIS = BIT(5), BIT 510 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h STA_CTXT_HE_PARTIAL_BSS_COLOR = BIT(6), BIT 511 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h STA_CTXT_HE_32BIT_BA_BITMAP = BIT(7), BIT 512 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h STA_CTXT_HE_PACKET_EXT = BIT(8), BIT 513 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h STA_CTXT_HE_TRIG_RND_ALLOC = BIT(9), BIT 514 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h STA_CTXT_HE_CONST_TRIG_RND_ALLOC = BIT(10), BIT 515 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h STA_CTXT_HE_ACK_ENABLED = BIT(11), BIT 516 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h STA_CTXT_HE_MU_EDCA_CW = BIT(12), BIT 517 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h STA_CTXT_HE_RU_2MHZ_BLOCK = BIT(14), BIT 530 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h IWL_HE_HTC_SUPPORT = BIT(0), BIT 531 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h IWL_HE_HTC_UL_MU_RESP_SCHED = BIT(3), BIT 532 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h IWL_HE_HTC_BSR_SUPP = BIT(4), BIT 533 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h IWL_HE_HTC_OMI_SUPP = BIT(5), BIT 534 drivers/net/wireless/intel/iwlwifi/fw/api/mac.h IWL_HE_HTC_BQR_SUPP = BIT(6), BIT 175 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h NVM_GENERAL_FLAGS_EMPTY_OTP = BIT(0), BIT 204 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED = BIT(0), BIT 205 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED = BIT(1), BIT 206 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h NVM_MAC_SKU_FLAGS_802_11N_ENABLED = BIT(2), BIT 207 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h NVM_MAC_SKU_FLAGS_802_11AC_ENABLED = BIT(3), BIT 211 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h NVM_MAC_SKU_FLAGS_802_11AX_ENABLED = BIT(4), BIT 212 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h NVM_MAC_SKU_FLAGS_MIMO_DISABLED = BIT(5), BIT 213 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h NVM_MAC_SKU_FLAGS_WAPI_ENABLED = BIT(8), BIT 214 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED = BIT(14), BIT 215 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED = BIT(15), BIT 327 drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h GEO_WMM_ETSI_5GHZ_INFO = BIT(0), BIT 115 drivers/net/wireless/intel/iwlwifi/fw/api/phy.h DTS_TRIGGER_CMD_FLAGS_TEMP = BIT(0), BIT 116 drivers/net/wireless/intel/iwlwifi/fw/api/phy.h DTS_TRIGGER_CMD_FLAGS_VOLT = BIT(1), BIT 86 drivers/net/wireless/intel/iwlwifi/fw/api/power.h LTR_CFG_FLAG_FEATURE_ENABLE = BIT(0), BIT 87 drivers/net/wireless/intel/iwlwifi/fw/api/power.h LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS = BIT(1), BIT 88 drivers/net/wireless/intel/iwlwifi/fw/api/power.h LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH = BIT(2), BIT 89 drivers/net/wireless/intel/iwlwifi/fw/api/power.h LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 = BIT(3), BIT 90 drivers/net/wireless/intel/iwlwifi/fw/api/power.h LTR_CFG_FLAG_SW_SET_SHORT = BIT(4), BIT 91 drivers/net/wireless/intel/iwlwifi/fw/api/power.h LTR_CFG_FLAG_SW_SET_LONG = BIT(5), BIT 92 drivers/net/wireless/intel/iwlwifi/fw/api/power.h LTR_CFG_FLAG_DENIE_C10_ON_PD = BIT(6), BIT 93 drivers/net/wireless/intel/iwlwifi/fw/api/power.h LTR_CFG_FLAG_UPDATE_VALUES = BIT(7), BIT 152 drivers/net/wireless/intel/iwlwifi/fw/api/power.h POWER_FLAGS_POWER_SAVE_ENA_MSK = BIT(0), BIT 153 drivers/net/wireless/intel/iwlwifi/fw/api/power.h POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = BIT(1), BIT 154 drivers/net/wireless/intel/iwlwifi/fw/api/power.h POWER_FLAGS_SKIP_OVER_DTIM_MSK = BIT(2), BIT 155 drivers/net/wireless/intel/iwlwifi/fw/api/power.h POWER_FLAGS_SNOOZE_ENA_MSK = BIT(5), BIT 156 drivers/net/wireless/intel/iwlwifi/fw/api/power.h POWER_FLAGS_BT_SCO_ENA = BIT(8), BIT 157 drivers/net/wireless/intel/iwlwifi/fw/api/power.h POWER_FLAGS_ADVANCE_PM_ENA_MSK = BIT(9), BIT 158 drivers/net/wireless/intel/iwlwifi/fw/api/power.h POWER_FLAGS_LPRX_ENA_MSK = BIT(11), BIT 159 drivers/net/wireless/intel/iwlwifi/fw/api/power.h POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = BIT(12), BIT 210 drivers/net/wireless/intel/iwlwifi/fw/api/power.h DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = BIT(0), BIT 211 drivers/net/wireless/intel/iwlwifi/fw/api/power.h DEVICE_POWER_FLAGS_ALLOW_MEM_RETENTION_MSK = BIT(1), BIT 212 drivers/net/wireless/intel/iwlwifi/fw/api/power.h DEVICE_POWER_FLAGS_32K_CLK_VALID_MSK = BIT(12), BIT 82 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0), BIT 83 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1), BIT 84 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2), BIT 85 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3), BIT 86 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4), BIT 111 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h IWL_TLC_MNG_CHAIN_A_MSK = BIT(0), BIT 112 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h IWL_TLC_MNG_CHAIN_B_MSK = BIT(1), BIT 218 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h IWL_TLC_NOTIF_FLAG_RATE = BIT(0), BIT 219 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1), BIT 284 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h #define IWL_RATE_BIT_MSK(r) BIT(IWL_RATE_##r##M_INDEX) BIT 407 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h #define RATE_MCS_HE_MSK BIT(RATE_MCS_HE_POS) BIT 437 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h #define RATE_MCS_STBC_MSK BIT(RATE_MCS_STBC_POS) BIT 441 drivers/net/wireless/intel/iwlwifi/fw/api/rs.h #define RATE_HE_DUAL_CARRIER_MODE_MSK BIT(RATE_HE_DUAL_CARRIER_MODE) BIT 140 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h CSUM_RXA_PADD = BIT(13), BIT 141 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h CSUM_RXA_AMSDU = BIT(14), BIT 142 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h CSUM_RXA_ENA = BIT(15) BIT 169 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_RES_PHY_FLAGS_BAND_24 = BIT(0), BIT 170 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), BIT 171 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), BIT 172 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), BIT 175 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_RES_PHY_FLAGS_AGG = BIT(7), BIT 176 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), BIT 177 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), BIT 178 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), BIT 214 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_CRC_OK = BIT(0), BIT 215 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), BIT 216 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), BIT 217 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), BIT 218 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4), BIT 219 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_ICV_OK = BIT(5), BIT 220 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_MIC_OK = BIT(6), BIT 221 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), BIT 222 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), BIT 231 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), BIT 232 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13), BIT 233 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14), BIT 234 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15), BIT 235 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), BIT 236 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), BIT 277 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), BIT 278 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), BIT 279 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), BIT 280 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_L3L4_TCP_ACK = BIT(3), BIT 287 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), BIT 288 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), BIT 289 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), BIT 290 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), BIT 291 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_KEY_PARAM_OK = BIT(4), BIT 292 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), BIT 293 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), BIT 294 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), BIT 303 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), BIT 304 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_WEP_MATCH = BIT(12), BIT 305 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_EXT_IV_MATCH = BIT(13), BIT 306 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_KEY_ID_MATCH = BIT(14), BIT 307 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), BIT 333 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_PHY_AMPDU = BIT(5), BIT 334 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), BIT 335 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), BIT 337 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), BIT 338 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), BIT 901 drivers/net/wireless/intel/iwlwifi/fw/api/rx.h #define BA_WINDOW_STATUS_VALID_MSK BIT(9) BIT 110 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CLIENT_SCHED_SCAN = BIT(0), BIT 111 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CLIENT_NETDETECT = BIT(1), BIT 112 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CLIENT_ASSET_TRACKING = BIT(2), BIT 221 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UNIFIED_SCAN_CHANNEL_FULL = BIT(27), BIT 222 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UNIFIED_SCAN_CHANNEL_PARTIAL = BIT(28), BIT 277 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_SCAN_CHANNEL_FLAG_EBS = BIT(0), BIT 278 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE = BIT(1), BIT 279 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_SCAN_CHANNEL_FLAG_CACHE_ADD = BIT(2), BIT 280 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_SCAN_CHANNEL_FLAG_EBS_FRAG = BIT(3), BIT 311 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_MVM_LMAC_SCAN_FLAG_PASS_ALL = BIT(0), BIT 312 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_MVM_LMAC_SCAN_FLAG_PASSIVE = BIT(1), BIT 313 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = BIT(2), BIT 314 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = BIT(3), BIT 315 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = BIT(4), BIT 316 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_MVM_LMAC_SCAN_FLAG_FRAGMENTED = BIT(5), BIT 317 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = BIT(6), BIT 318 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = BIT(7), BIT 319 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_MVM_LMAC_SCAN_FLAG_MATCH = BIT(9), BIT 456 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_ACTIVATE = BIT(0), BIT 457 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_DEACTIVATE = BIT(1), BIT 458 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = BIT(2), BIT 459 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = BIT(3), BIT 460 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_TX_CHAINS = BIT(8), BIT 461 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_RX_CHAINS = BIT(9), BIT 462 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_AUX_STA_ID = BIT(10), BIT 463 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_ALL_TIMES = BIT(11), BIT 464 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = BIT(12), BIT 465 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = BIT(13), BIT 466 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_LEGACY_RATES = BIT(14), BIT 467 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_MAC_ADDR = BIT(15), BIT 468 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_FRAGMENTED = BIT(16), BIT 469 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = BIT(17), BIT 470 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_CAM_MODE = BIT(18), BIT 471 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = BIT(19), BIT 472 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_PROMISC_MODE = BIT(20), BIT 473 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = BIT(21), BIT 474 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_SET_LMAC2_FRAGMENTED = BIT(22), BIT 475 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_FLAG_CLEAR_LMAC2_FRAGMENTED = BIT(23), BIT 483 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_6M = BIT(0), BIT 484 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_9M = BIT(1), BIT 485 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_12M = BIT(2), BIT 486 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_18M = BIT(3), BIT 487 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_24M = BIT(4), BIT 488 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_36M = BIT(5), BIT 489 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_48M = BIT(6), BIT 490 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_54M = BIT(7), BIT 492 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_1M = BIT(8), BIT 493 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_2M = BIT(9), BIT 494 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_5M = BIT(10), BIT 495 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h SCAN_CONFIG_RATE_11M = BIT(11), BIT 502 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_CHANNEL_FLAG_EBS = BIT(0), BIT 503 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_CHANNEL_FLAG_ACCURATE_EBS = BIT(1), BIT 504 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_CHANNEL_FLAG_EBS_ADD = BIT(2), BIT 505 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = BIT(3), BIT 597 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_FLAG_PREEMPTIVE = BIT(0), BIT 598 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_FLAG_START_NOTIF = BIT(1), BIT 607 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_PERIODIC = BIT(0), BIT 608 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_OVER_BT = BIT(1), BIT 609 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_PASS_ALL = BIT(2), BIT 610 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_PASSIVE = BIT(3), BIT 611 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = BIT(4), BIT 612 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = BIT(5), BIT 613 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = BIT(6), BIT 614 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = BIT(7), BIT 615 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = BIT(8), BIT 616 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_MATCH = BIT(9), BIT 617 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = BIT(10), BIT 621 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP = BIT(10), BIT 622 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED = BIT(11), BIT 623 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL = BIT(13), BIT 624 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME = BIT(14), BIT 625 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE = BIT(15), BIT 636 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL = BIT(0), BIT 637 drivers/net/wireless/intel/iwlwifi/fw/api/scan.h IWL_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER = BIT(1), BIT 121 drivers/net/wireless/intel/iwlwifi/fw/api/sf.h #define SF_CFG_DUMMY_NOTIF_OFF BIT(16) BIT 110 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_FLG_REDUCED_TX_PWR_CTRL = BIT(3), BIT 111 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_FLG_REDUCED_TX_PWR_DATA = BIT(6), BIT 113 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_FLG_DISABLE_TX = BIT(4), BIT 115 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_FLG_PS = BIT(8), BIT 116 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_FLG_DRAIN_FLOW = BIT(12), BIT 117 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_FLG_PAN = BIT(13), BIT 118 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_FLG_CLASS_AUTH = BIT(14), BIT 119 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_FLG_CLASS_ASSOC = BIT(15), BIT 120 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_FLG_RTS_MIMO_PROT = BIT(17), BIT 184 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_KEY_FLG_WEP_KEY_MAP = BIT(3), BIT 187 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_KEY_NOT_VALID = BIT(11), BIT 188 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_KEY_FLG_WEP_13BYTES = BIT(12), BIT 189 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_KEY_FLG_KEY_32BYTES = BIT(12), BIT 190 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_KEY_MULTICAST = BIT(14), BIT 191 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_KEY_MFP = BIT(15), BIT 206 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_MODIFY_QUEUE_REMOVAL = BIT(0), BIT 207 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_MODIFY_TID_DISABLE_TX = BIT(1), BIT 208 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_MODIFY_UAPSD_ACS = BIT(2), BIT 209 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_MODIFY_ADD_BA_TID = BIT(3), BIT 210 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_MODIFY_REMOVE_BA_TID = BIT(4), BIT 211 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_MODIFY_SLEEPING_STA_TX_COUNT = BIT(5), BIT 212 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_MODIFY_PROT_TH = BIT(6), BIT 213 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_MODIFY_QUEUES = BIT(7), BIT 236 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_SLEEP_STATE_PS_POLL = BIT(0), BIT 237 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_SLEEP_STATE_UAPSD = BIT(1), BIT 238 drivers/net/wireless/intel/iwlwifi/fw/api/sta.h STA_SLEEP_STATE_MOREDATA = BIT(2), BIT 135 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_DEP_OTHER = BIT(0), BIT 136 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_DEP_TSF = BIT(1), BIT 137 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_EVENT_SOCIOPATHIC = BIT(2), BIT 159 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_NOTIF_HOST_EVENT_START = BIT(0), BIT 160 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_NOTIF_HOST_EVENT_END = BIT(1), BIT 161 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_NOTIF_INTERNAL_EVENT_START = BIT(2), BIT 162 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_NOTIF_INTERNAL_EVENT_END = BIT(3), BIT 163 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_NOTIF_HOST_FRAG_START = BIT(4), BIT 164 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_NOTIF_HOST_FRAG_END = BIT(5), BIT 165 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_NOTIF_INTERNAL_FRAG_START = BIT(6), BIT 166 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V1_NOTIF_INTERNAL_FRAG_END = BIT(7), BIT 226 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_NOTIF_HOST_EVENT_START = BIT(0), BIT 227 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_NOTIF_HOST_EVENT_END = BIT(1), BIT 228 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_NOTIF_INTERNAL_EVENT_START = BIT(2), BIT 229 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_NOTIF_INTERNAL_EVENT_END = BIT(3), BIT 231 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_NOTIF_HOST_FRAG_START = BIT(4), BIT 232 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_NOTIF_HOST_FRAG_END = BIT(5), BIT 233 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_NOTIF_INTERNAL_FRAG_START = BIT(6), BIT 234 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_NOTIF_INTERNAL_FRAG_END = BIT(7), BIT 235 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_START_IMMEDIATELY = BIT(11), BIT 238 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_DEP_OTHER = BIT(TE_V2_PLACEMENT_POS), BIT 239 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_DEP_TSF = BIT(TE_V2_PLACEMENT_POS + 1), BIT 240 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_EVENT_SOCIOPATHIC = BIT(TE_V2_PLACEMENT_POS + 2), BIT 243 drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h TE_V2_ABSENCE = BIT(TE_V2_ABSENCE_POS), BIT 99 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_PROT_REQUIRE = BIT(0), BIT 100 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_WRITE_TX_POWER = BIT(1), BIT 101 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_ACK = BIT(3), BIT 102 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_STA_RATE = BIT(4), BIT 103 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_BAR = BIT(6), BIT 104 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_TXOP_PROT = BIT(7), BIT 105 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_VHT_NDPA = BIT(8), BIT 106 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_HT_NDPA = BIT(9), BIT 107 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_CSI_FDBK2HOST = BIT(10), BIT 109 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_BT_DIS = BIT(12), BIT 110 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_SEQ_CTL = BIT(13), BIT 111 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_MORE_FRAG = BIT(14), BIT 112 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_TSF = BIT(16), BIT 113 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_CALIB = BIT(17), BIT 114 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_KEEP_SEQ_CTL = BIT(18), BIT 115 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_MH_PAD = BIT(20), BIT 116 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_RESP_TO_DRV = BIT(21), BIT 117 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_TKIP_MIC_DONE = BIT(23), BIT 118 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_DUR = BIT(25), BIT 119 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_FW_DROP = BIT(26), BIT 120 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_EXEC_PAPD = BIT(27), BIT 121 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_PAPD_TYPE = BIT(28), BIT 122 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h TX_CMD_FLG_HCCA_CHUNK = BIT(31) BIT 134 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h IWL_TX_FLAGS_CMD_RATE = BIT(0), BIT 135 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h IWL_TX_FLAGS_ENCRYPT_DIS = BIT(1), BIT 136 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h IWL_TX_FLAGS_HIGH_PRI = BIT(2), BIT 812 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h IWL_MAC_BEACON_CCK = BIT(8), BIT 813 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h IWL_MAC_BEACON_ANT_A = BIT(9), BIT 814 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h IWL_MAC_BEACON_ANT_B = BIT(10), BIT 815 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h IWL_MAC_BEACON_ANT_C = BIT(11), BIT 883 drivers/net/wireless/intel/iwlwifi/fw/api/tx.h DUMP_TX_FIFO_FLUSH = BIT(1), BIT 132 drivers/net/wireless/intel/iwlwifi/fw/api/txq.h TX_QUEUE_CFG_ENABLE_QUEUE = BIT(0), BIT 133 drivers/net/wireless/intel/iwlwifi/fw/api/txq.h TX_QUEUE_CFG_TFD_SHORT_FORMAT = BIT(1), BIT 1206 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) BIT 1219 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) BIT 1313 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (fid1 && !WARN_ON_ONCE((~BIT(fifo_idx) & fid1) || BIT 161 drivers/net/wireless/intel/iwlwifi/fw/dbg.h (BIT(fwrt->dump.conf) & le32_to_cpu(trig->stop_conf_ids)))); BIT 289 drivers/net/wireless/intel/iwlwifi/fw/dbg.h return (fwrt->fw->dbg.dump_mask & BIT(type)); BIT 288 drivers/net/wireless/intel/iwlwifi/fw/error-dump.h #define IWL_INI_DUMP_INFO_TYPE BIT(31) BIT 370 drivers/net/wireless/intel/iwlwifi/fw/error-dump.h #define IWL_RXF_UMAC_BIT BIT(31) BIT 235 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_PAN = BIT(0), BIT 236 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1), BIT 237 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_MFP = BIT(2), BIT 238 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_SHORT_BL = BIT(7), BIT 239 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = BIT(10), BIT 240 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_NO_BASIC_SSID = BIT(12), BIT 241 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = BIT(15), BIT 242 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = BIT(16), BIT 243 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT = BIT(24), BIT 244 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_EBS_SUPPORT = BIT(25), BIT 245 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_P2P_PS_UAPSD = BIT(26), BIT 246 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_UCODE_TLV_FLAGS_BCAST_FILTERING = BIT(29), BIT 535 drivers/net/wireless/intel/iwlwifi/fw/file.h FW_PHY_CFG_SHARED_CLK = BIT(31), BIT 692 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_FW_DBG_TRIGGER_START = BIT(0), BIT 693 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_FW_DBG_TRIGGER_STOP = BIT(1), BIT 694 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_FW_DBG_TRIGGER_MONITOR_ONLY = BIT(2), BIT 702 drivers/net/wireless/intel/iwlwifi/fw/file.h IWL_FW_DBG_FORCE_RESTART = BIT(0), BIT 149 drivers/net/wireless/intel/iwlwifi/fw/img.h #define FW_PAGING_SIZE BIT(PAGE_2_EXP_SIZE) /* page size is 4KB */ BIT 152 drivers/net/wireless/intel/iwlwifi/fw/img.h #define NUM_OF_PAGE_PER_GROUP BIT(PAGE_PER_GROUP_2_EXP_SIZE) BIT 163 drivers/net/wireless/intel/iwlwifi/fw/img.h #define NUM_OF_BLOCK_PER_IMAGE BIT(BLOCK_PER_IMAGE_2_EXP_SIZE) BIT 170 drivers/net/wireless/intel/iwlwifi/fw/img.h #define PAGING_CMD_IS_SECURED BIT(9) BIT 171 drivers/net/wireless/intel/iwlwifi/fw/img.h #define PAGING_CMD_IS_ENABLED BIT(8) BIT 108 drivers/net/wireless/intel/iwlwifi/fw/paging.c BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE); BIT 147 drivers/net/wireless/intel/iwlwifi/iwl-config.h #define ANT_A BIT(0) BIT 148 drivers/net/wireless/intel/iwlwifi/iwl-config.h #define ANT_B BIT(1) BIT 149 drivers/net/wireless/intel/iwlwifi/iwl-config.h #define ANT_C BIT(2) BIT 63 drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) BIT 65 drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h #define CSR_AUTO_FUNC_INIT BIT(7) BIT 98 drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), BIT 99 drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), BIT 100 drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), BIT 101 drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), BIT 102 drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), BIT 103 drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), BIT 104 drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), BIT 105 drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), BIT 86 drivers/net/wireless/intel/iwlwifi/iwl-context-info.h IWL_CTXT_INFO_AUTO_FUNC_INIT = BIT(0), BIT 87 drivers/net/wireless/intel/iwlwifi/iwl-context-info.h IWL_CTXT_INFO_EARLY_DEBUG = BIT(1), BIT 88 drivers/net/wireless/intel/iwlwifi/iwl-context-info.h IWL_CTXT_INFO_ENABLE_CDMP = BIT(2), BIT 90 drivers/net/wireless/intel/iwlwifi/iwl-context-info.h IWL_CTXT_INFO_TFD_FORMAT_LONG = BIT(8), BIT 146 drivers/net/wireless/intel/iwlwifi/iwl-csr.h #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20) BIT 155 drivers/net/wireless/intel/iwlwifi/iwl-csr.h #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19) BIT 207 drivers/net/wireless/intel/iwlwifi/iwl-csr.h #define CSR_MBOX_SET_REG_OS_ALIVE BIT(5) BIT 549 drivers/net/wireless/intel/iwlwifi/iwl-csr.h #define IWL_HOST_INT_OPER_MODE BIT(31) BIT 592 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_FH_INT_CAUSES_Q0 = BIT(0), BIT 593 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_FH_INT_CAUSES_Q1 = BIT(1), BIT 594 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16), BIT 595 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17), BIT 596 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_FH_INT_CAUSES_S2D = BIT(19), BIT 597 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_FH_INT_CAUSES_FH_ERR = BIT(21), BIT 604 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0), BIT 605 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1), BIT 606 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_IPC = BIT(1), BIT 607 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_IML = BIT(2), BIT 608 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = BIT(5), BIT 609 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6), BIT 610 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7), BIT 611 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8), BIT 612 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25), BIT 613 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_SCD = BIT(26), BIT 614 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27), BIT 615 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29), BIT 616 drivers/net/wireless/intel/iwlwifi/iwl-csr.h MSIX_HW_INT_CAUSES_REG_HAP = BIT(30), BIT 621 drivers/net/wireless/intel/iwlwifi/iwl-csr.h #define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) BIT 470 drivers/net/wireless/intel/iwlwifi/iwl-drv.c if (api_flags & BIT(i)) BIT 491 drivers/net/wireless/intel/iwlwifi/iwl-drv.c if (api_flags & BIT(i)) BIT 121 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_SKU_CAP_BAND_24GHZ = BIT(4), BIT 122 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_SKU_CAP_BAND_52GHZ = BIT(5), BIT 123 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_SKU_CAP_11N_ENABLE = BIT(6), BIT 124 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_SKU_CAP_AMT_ENABLE = BIT(7), BIT 125 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_SKU_CAP_IPAN_ENABLE = BIT(8) BIT 296 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_CHANNEL_VALID = BIT(0), BIT 297 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_CHANNEL_IBSS = BIT(1), BIT 298 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_CHANNEL_ACTIVE = BIT(3), BIT 299 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_CHANNEL_RADAR = BIT(4), BIT 300 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_CHANNEL_WIDE = BIT(5), BIT 301 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c EEPROM_CHANNEL_DFS = BIT(7), BIT 316 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0), BIT 317 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1), BIT 318 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2), BIT 319 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3), BIT 320 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4), BIT 321 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5), BIT 322 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6), BIT 323 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7), BIT 789 drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c if (cfg->ht_params->ht40_bands & BIT(band)) { BIT 162 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define TFH_CHUNK_SIZE_128 BIT(8) BIT 163 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define TFH_CHUNK_SPLIT_MODE BIT(10) BIT 186 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define TFH_SRV_DMA_SNOOP BIT(0) BIT 187 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define TFH_SRV_DMA_TO_DRIVER BIT(24) BIT 188 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define TFH_SRV_DMA_START BIT(31) BIT 438 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define RBD_FETCH_IDLE BIT(29) BIT 439 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define SRAM_DMA_IDLE BIT(30) BIT 440 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define RXF_DMA_IDLE BIT(31) BIT 476 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define RFH_DMA_EN_ENABLE_VAL BIT(31) BIT 481 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0) BIT 482 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1) BIT 483 drivers/net/wireless/intel/iwlwifi/iwl-fh.h #define RFH_GEN_CFG_RB_CHUNK_SIZE BIT(4) BIT 510 drivers/net/wireless/intel/iwlwifi/iwl-io.c BIT(cfg_trans->csr->flag_init_done)); BIT 521 drivers/net/wireless/intel/iwlwifi/iwl-io.c BIT(cfg_trans->csr->flag_mac_clock_ready), BIT 522 drivers/net/wireless/intel/iwlwifi/iwl-io.c BIT(cfg_trans->csr->flag_mac_clock_ready), BIT 79 drivers/net/wireless/intel/iwlwifi/iwl-modparams.h IWL_DISABLE_HT_ALL = BIT(0), BIT 80 drivers/net/wireless/intel/iwlwifi/iwl-modparams.h IWL_DISABLE_HT_TXAGG = BIT(1), BIT 81 drivers/net/wireless/intel/iwlwifi/iwl-modparams.h IWL_DISABLE_HT_RXAGG = BIT(2), BIT 82 drivers/net/wireless/intel/iwlwifi/iwl-modparams.h IWL_ENABLE_HT_TXAGG = BIT(3), BIT 95 drivers/net/wireless/intel/iwlwifi/iwl-modparams.h IWL_DISABLE_UAPSD_BSS = BIT(0), BIT 96 drivers/net/wireless/intel/iwlwifi/iwl-modparams.h IWL_DISABLE_UAPSD_P2P_CLIENT = BIT(1), BIT 123 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_SKU_CAP_BAND_24GHZ = BIT(0), BIT 124 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_SKU_CAP_BAND_52GHZ = BIT(1), BIT 125 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_SKU_CAP_11N_ENABLE = BIT(2), BIT 126 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_SKU_CAP_11AC_ENABLE = BIT(3), BIT 127 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_SKU_CAP_MIMO_DISABLE = BIT(5), BIT 214 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_VALID = BIT(0), BIT 215 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_IBSS = BIT(1), BIT 216 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_ACTIVE = BIT(3), BIT 217 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_RADAR = BIT(4), BIT 218 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_INDOOR_ONLY = BIT(5), BIT 219 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_GO_CONCURRENT = BIT(6), BIT 220 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_UNIFORM = BIT(7), BIT 221 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_20MHZ = BIT(8), BIT 222 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_40MHZ = BIT(9), BIT 223 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_80MHZ = BIT(10), BIT 224 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_160MHZ = BIT(11), BIT 225 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c NVM_CHANNEL_DC_HIGH = BIT(12), BIT 246 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c REG_CAPA_BF_CCD_LOW_BAND = BIT(0), BIT 247 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c REG_CAPA_BF_CCD_HIGH_BAND = BIT(1), BIT 248 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c REG_CAPA_160MHZ_ALLOWED = BIT(2), BIT 249 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c REG_CAPA_80MHZ_ALLOWED = BIT(3), BIT 250 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c REG_CAPA_MCS_8_ALLOWED = BIT(4), BIT 251 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c REG_CAPA_MCS_9_ALLOWED = BIT(5), BIT 252 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c REG_CAPA_40MHZ_FORBIDDEN = BIT(7), BIT 253 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c REG_CAPA_DC_HIGH_ENABLED = BIT(9), BIT 517 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c .types_mask = BIT(NL80211_IFTYPE_STATION), BIT 602 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c .types_mask = BIT(NL80211_IFTYPE_AP), BIT 1243 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) BIT 74 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.h IWL_NVM_SBANDS_FLAGS_LAR = BIT(0), BIT 75 drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.h IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ = BIT(1), BIT 111 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define DEVICE_SET_NMI_VAL_DRV BIT(7) BIT 141 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define RELEASE_CPU_RESET_BIT BIT(24) BIT 255 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0) BIT 256 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define SCD_GP_CTRL_AUTO_ACTIVE_MODE BIT(18) BIT 394 drivers/net/wireless/intel/iwlwifi/iwl-prph.h ENABLE_WFPM = BIT(31), BIT 429 drivers/net/wireless/intel/iwlwifi/iwl-prph.h UMAG_GEN_HW_IS_FPGA = BIT(1), BIT 435 drivers/net/wireless/intel/iwlwifi/iwl-prph.h LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0), BIT 441 drivers/net/wireless/intel/iwlwifi/iwl-prph.h LMPM_PAGE_PASS_NOTIF_POS = BIT(20), BIT 445 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define UREG_CHICK_MSI_ENABLE BIT(24) BIT 446 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define UREG_CHICK_MSIX_ENABLE BIT(25) BIT 449 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define PERSISTENCE_BIT BIT(12) BIT 450 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define PREG_WFPM_ACCESS BIT(12) BIT 453 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define HPM_HIPM_GEN_CFG_CR_PG_EN BIT(0) BIT 454 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define HPM_HIPM_GEN_CFG_CR_SLP_EN BIT(1) BIT 455 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE BIT(10) BIT 458 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define UREG_DOORBELL_TO_ISR6_NMI_BIT BIT(0) BIT 459 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define UREG_DOORBELL_TO_ISR6_SUSPEND BIT(18) BIT 460 drivers/net/wireless/intel/iwlwifi/iwl-prph.h #define UREG_DOORBELL_TO_ISR6_RESUME BIT(19) BIT 70 drivers/net/wireless/intel/iwlwifi/iwl-scd.h iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); BIT 76 drivers/net/wireless/intel/iwlwifi/iwl-scd.h iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); BIT 82 drivers/net/wireless/intel/iwlwifi/iwl-scd.h iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); BIT 118 drivers/net/wireless/intel/iwlwifi/iwl-trans.h #define FH_RSCSR_RPA_EN BIT(25) BIT 119 drivers/net/wireless/intel/iwlwifi/iwl-trans.h #define FH_RSCSR_RADA_EN BIT(26) BIT 166 drivers/net/wireless/intel/iwlwifi/iwl-trans.h CMD_ASYNC = BIT(0), BIT 167 drivers/net/wireless/intel/iwlwifi/iwl-trans.h CMD_WANT_SKB = BIT(1), BIT 168 drivers/net/wireless/intel/iwlwifi/iwl-trans.h CMD_SEND_IN_RFKILL = BIT(2), BIT 169 drivers/net/wireless/intel/iwlwifi/iwl-trans.h CMD_WANT_ASYNC_CALLBACK = BIT(3), BIT 232 drivers/net/wireless/intel/iwlwifi/iwl-trans.h IWL_HCMD_DFL_NOCOPY = BIT(0), BIT 233 drivers/net/wireless/intel/iwlwifi/iwl-trans.h IWL_HCMD_DFL_DUP = BIT(1), BIT 237 drivers/net/wireless/intel/iwlwifi/iwl-trans.h IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), BIT 238 drivers/net/wireless/intel/iwlwifi/iwl-trans.h IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), BIT 239 drivers/net/wireless/intel/iwlwifi/iwl-trans.h IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), BIT 374 drivers/net/wireless/intel/iwlwifi/mvm/coex.c (mvm->last_bt_notif.rrc_status & BIT(mvmvif->phy_ctxt->id))) BIT 616 drivers/net/wireless/intel/iwlwifi/mvm/coex.c if (mvm->last_bt_notif.ttc_status & BIT(phy_ctxt->id)) BIT 640 drivers/net/wireless/intel/iwlwifi/mvm/coex.c if (mvm->last_bt_notif.ttc_status & BIT(phy_ctxt->id)) BIT 1578 drivers/net/wireless/intel/iwlwifi/mvm/d3.c status->gtk[0].key_flags = v6->gtk.key_index | BIT(7); BIT 1784 drivers/net/wireless/intel/iwlwifi/mvm/d3.c if (matches[idx].matching_channels[i / 8] & (BIT(i % 8))) BIT 1792 drivers/net/wireless/intel/iwlwifi/mvm/d3.c if (matches[idx].matching_channels[i / 8] & (BIT(i % 8))) BIT 1546 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c attached_filters >= BIT(ARRAY_SIZE(cmd.filters))) BIT 108 drivers/net/wireless/intel/iwlwifi/mvm/fw.c .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) | BIT 109 drivers/net/wireless/intel/iwlwifi/mvm/fw.c BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) | BIT 110 drivers/net/wireless/intel/iwlwifi/mvm/fw.c BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) | BIT 111 drivers/net/wireless/intel/iwlwifi/mvm/fw.c BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) | BIT 112 drivers/net/wireless/intel/iwlwifi/mvm/fw.c BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) | BIT 113 drivers/net/wireless/intel/iwlwifi/mvm/fw.c BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD), BIT 401 drivers/net/wireless/intel/iwlwifi/mvm/fw.c BIT(IWL_MAX_TID_COUNT + 2); BIT 416 drivers/net/wireless/intel/iwlwifi/mvm/fw.c .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)), BIT 424 drivers/net/wireless/intel/iwlwifi/mvm/fw.c init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY)); BIT 388 drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c ofdm |= BIT(hw - IWL_FIRST_OFDM_RATE); BIT 394 drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c cck |= BIT(hw); BIT 570 drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c cmd->ac[ucode_ac].fifos_mask = BIT(txf); BIT 720 drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c u32 tfd_queue_msk = BIT(mvm->snif_queue); BIT 894 drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c cpu_to_le32(BIT(mvm->mgmt_last_antenna_idx) << BIT 1096 drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c cmd->ac[IWL_MVM_TX_FIFO_VO].fifos_mask |= BIT(IWL_MVM_TX_FIFO_MCAST); BIT 89 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .types = BIT(NL80211_IFTYPE_STATION), BIT 93 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .types = BIT(NL80211_IFTYPE_AP) | BIT 94 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 95 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_IFTYPE_P2P_GO), BIT 99 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .types = BIT(NL80211_IFTYPE_P2P_DEVICE), BIT 198 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .bandwidths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT 199 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_CHAN_WIDTH_20) | BIT 200 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_CHAN_WIDTH_40) | BIT 201 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_CHAN_WIDTH_80), BIT 202 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .preambles = BIT(NL80211_PREAMBLE_LEGACY) | BIT 203 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_PREAMBLE_HT) | BIT 204 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_PREAMBLE_VHT), BIT 493 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c cs->iftype = BIT(NL80211_IFTYPE_STATION); BIT 525 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 526 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 527 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_IFTYPE_AP) | BIT 528 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_IFTYPE_P2P_GO) | BIT 529 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_IFTYPE_P2P_DEVICE) | BIT 530 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_IFTYPE_ADHOC); BIT 903 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c if (!(le16_to_cpu(_tid_bm) & BIT(_tid))) \ BIT 1868 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c cpu_to_le16(BIT(data->current_filter)); BIT 1985 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c (BIT(IEEE80211_PPE_THRES_INFO_PPET_SIZE) - 1); BIT 1996 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c (BIT(IEEE80211_PPE_THRES_INFO_PPET_SIZE - residue_bits) - 1)) << BIT 1998 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c res += (ppe[byte_num] >> bit_num) & (BIT(residue_bits) - 1); BIT 2953 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c if (!(tdls_trig->action_bitmap & BIT(action))) BIT 4845 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c if (!(le16_to_cpu(ba_trig->rx_bar) & BIT(event->u.ba.tid))) BIT 4880 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c u32 qmask = BIT(mvm->trans->num_rx_queues) - 1; BIT 4944 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c stats->filled = BIT(NL80211_FTM_STATS_SUCCESS_NUM) | BIT 4945 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_FTM_STATS_PARTIAL_NUM) | BIT 4946 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_FTM_STATS_FAILED_NUM) | BIT 4947 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_FTM_STATS_ASAP_NUM) | BIT 4948 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_FTM_STATS_NON_ASAP_NUM) | BIT 4949 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_FTM_STATS_TOTAL_DURATION_MSEC) | BIT 4950 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_FTM_STATS_UNKNOWN_TRIGGERS_NUM) | BIT 4951 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_FTM_STATS_RESCHEDULE_REQUESTS_NUM) | BIT 4952 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c BIT(NL80211_FTM_STATS_OUT_OF_WINDOW_TRIGGERS_NUM); BIT 196 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_PM_KEEP_ALIVE = BIT(0), BIT 197 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_PM_SKIP_OVER_DTIM = BIT(1), BIT 198 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_PM_SKIP_DTIM_PERIODS = BIT(2), BIT 199 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_PM_RX_DATA_TIMEOUT = BIT(3), BIT 200 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_PM_TX_DATA_TIMEOUT = BIT(4), BIT 201 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_PM_LPRX_ENA = BIT(6), BIT 202 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_PM_LPRX_RSSI_THRESHOLD = BIT(7), BIT 203 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_PM_SNOOZE_ENABLE = BIT(8), BIT 204 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_PM_UAPSD_MISBEHAVING = BIT(9), BIT 205 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_PM_USE_PS_POLL = BIT(10), BIT 225 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BF_ENERGY_DELTA = BIT(0), BIT 226 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BF_ROAMING_ENERGY_DELTA = BIT(1), BIT 227 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BF_ROAMING_STATE = BIT(2), BIT 228 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BF_TEMP_THRESHOLD = BIT(3), BIT 229 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BF_TEMP_FAST_FILTER = BIT(4), BIT 230 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BF_TEMP_SLOW_FILTER = BIT(5), BIT 231 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BF_ENABLE_BEACON_FILTER = BIT(6), BIT 232 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BF_DEBUG_FLAG = BIT(7), BIT 233 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BF_ESCAPE_TIMER = BIT(8), BIT 234 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BA_ESCAPE_TIMER = BIT(9), BIT 235 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h MVM_DEBUGFS_BA_ENABLE_BEACON_ABORT = BIT(10), BIT 297 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h LOW_LATENCY_TRAFFIC = BIT(0), BIT 298 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h LOW_LATENCY_DEBUGFS = BIT(1), BIT 299 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h LOW_LATENCY_VCMD = BIT(2), BIT 300 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h LOW_LATENCY_VIF_TYPE = BIT(3), BIT 301 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h LOW_LATENCY_DEBUGFS_FORCE_ENABLE = BIT(4), BIT 302 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h LOW_LATENCY_DEBUGFS_FORCE = BIT(5), BIT 493 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h IWL_MVM_SCAN_REGULAR = BIT(0), BIT 494 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h IWL_MVM_SCAN_SCHED = BIT(1), BIT 495 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h IWL_MVM_SCAN_NETDETECT = BIT(2), BIT 497 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h IWL_MVM_SCAN_STOPPING_REGULAR = BIT(8), BIT 498 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h IWL_MVM_SCAN_STOPPING_SCHED = BIT(9), BIT 499 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h IWL_MVM_SCAN_STOPPING_NETDETECT = BIT(10), BIT 1184 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h IWL_MVM_INIT_STATUS_THERMAL_INIT_COMPLETE = BIT(0), BIT 1185 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h IWL_MVM_INIT_STATUS_LEDS_INIT_COMPLETE = BIT(1), BIT 1942 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h return ((BIT(mvm->trans->trans_cfg->base_params->num_of_queues) - 1) & BIT 1943 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h ~BIT(IWL_MVM_DQA_CMD_QUEUE)); BIT 1129 drivers/net/wireless/intel/iwlwifi/mvm/ops.c tid_bitmap = BIT(tid); BIT 205 drivers/net/wireless/intel/iwlwifi/mvm/power.c cmd->uapsd_ac_flags |= BIT(ac); BIT 229 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (cmd->uapsd_ac_flags == (BIT(IEEE80211_AC_VO) | BIT 230 drivers/net/wireless/intel/iwlwifi/mvm/power.c BIT(IEEE80211_AC_VI) | BIT 231 drivers/net/wireless/intel/iwlwifi/mvm/power.c BIT(IEEE80211_AC_BE) | BIT 232 drivers/net/wireless/intel/iwlwifi/mvm/power.c BIT(IEEE80211_AC_BK))) { BIT 108 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c supp |= BIT(IWL_TLC_MNG_CH_WIDTH_20MHZ); BIT 110 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c supp |= BIT(IWL_TLC_MNG_CH_WIDTH_40MHZ); BIT 112 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c supp |= BIT(IWL_TLC_MNG_CH_WIDTH_80MHZ); BIT 114 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c supp |= BIT(IWL_TLC_MNG_CH_WIDTH_160MHZ); BIT 209 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c supp = BIT(highest_mcs + 1) - 1; BIT 211 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c supp &= ~BIT(IWL_TLC_MNG_HT_RATE_MCS9); BIT 224 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c return BIT(IWL_TLC_MNG_HT_RATE_MCS7 + 1) - 1; BIT 226 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c return BIT(IWL_TLC_MNG_HT_RATE_MCS9 + 1) - 1; BIT 228 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c return BIT(IWL_TLC_MNG_HT_RATE_MCS11 + 1) - 1; BIT 301 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c supp |= BIT(sband->bitrates[i].hw_value); BIT 384 drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c if (mvmsta->amsdu_enabled & BIT(i)) BIT 648 drivers/net/wireless/intel/iwlwifi/mvm/rs.c (lq_sta->tx_agg_tid_en & BIT(tid)) && BIT 1029 drivers/net/wireless/intel/iwlwifi/mvm/rs.c mask = BIT(i); BIT 1073 drivers/net/wireless/intel/iwlwifi/mvm/rs.c return BIT(rate->index) & rs_get_supported_rates(lq_sta, rate); BIT 1501 drivers/net/wireless/intel/iwlwifi/mvm/rs.c lq_sta->visited_columns = BIT(tbl->column); BIT 1645 drivers/net/wireless/intel/iwlwifi/mvm/rs.c if (lq_sta->visited_columns & BIT(next_col_id)) { BIT 1755 drivers/net/wireless/intel/iwlwifi/mvm/rs.c lq_sta->visited_columns |= BIT(col_id); BIT 1765 drivers/net/wireless/intel/iwlwifi/mvm/rs.c !(BIT(rate_idx) & rate_mask)) { BIT 2143 drivers/net/wireless/intel/iwlwifi/mvm/rs.c if (!(BIT(index) & rate_mask)) { BIT 2513 drivers/net/wireless/intel/iwlwifi/mvm/rs.c (BIT(rate_idx) & lq_sta->optimal_rate_mask)) { BIT 2540 drivers/net/wireless/intel/iwlwifi/mvm/rs.c if (!(lq_sta->pers.chains & BIT(i))) BIT 2545 drivers/net/wireless/intel/iwlwifi/mvm/rs.c best_ant = BIT(i); BIT 2629 drivers/net/wireless/intel/iwlwifi/mvm/rs.c (BIT(rate_idx) & active_rate)) { BIT 2654 drivers/net/wireless/intel/iwlwifi/mvm/rs.c if (!(lq_sta->pers.chains & BIT(i))) BIT 2810 drivers/net/wireless/intel/iwlwifi/mvm/rs.c lq_sta->active_siso_rate |= BIT(i); BIT 2828 drivers/net/wireless/intel/iwlwifi/mvm/rs.c lq_sta->active_mimo2_rate |= BIT(i); BIT 3002 drivers/net/wireless/intel/iwlwifi/mvm/rs.c lq_sta->active_legacy_rate |= BIT(sband->bitrates[i].hw_value); BIT 533 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c IWL_MVM_RELEASE_SEND_RSS_SYNC = BIT(0), BIT 534 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c IWL_MVM_RELEASE_FROM_RSS_SYNC = BIT(1), BIT 838 drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c ieee80211_stop_rx_ba_session(mvmsta->vif, BIT(tid), sta->addr); BIT 214 drivers/net/wireless/intel/iwlwifi/mvm/scan.c tx_ant = BIT(mvm->scan_last_antenna_idx) << RATE_MCS_ANT_POS; BIT 584 drivers/net/wireless/intel/iwlwifi/mvm/scan.c *ssid_bitmap |= BIT(i); BIT 586 drivers/net/wireless/intel/iwlwifi/mvm/scan.c *ssid_bitmap |= BIT(index); BIT 97 drivers/net/wireless/intel/iwlwifi/mvm/sta.c reserved_ids = BIT(0); BIT 101 drivers/net/wireless/intel/iwlwifi/mvm/sta.c if (BIT(sta_id) & reserved_ids) BIT 221 drivers/net/wireless/intel/iwlwifi/mvm/sta.c add_sta_cmd.uapsd_acs |= BIT(AC_BK); BIT 223 drivers/net/wireless/intel/iwlwifi/mvm/sta.c add_sta_cmd.uapsd_acs |= BIT(AC_BE); BIT 225 drivers/net/wireless/intel/iwlwifi/mvm/sta.c add_sta_cmd.uapsd_acs |= BIT(AC_VI); BIT 227 drivers/net/wireless/intel/iwlwifi/mvm/sta.c add_sta_cmd.uapsd_acs |= BIT(AC_VO); BIT 366 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvm->queue_info[queue].tid_bitmap &= ~BIT(tid); BIT 441 drivers/net/wireless/intel/iwlwifi/mvm/sta.c agg_tids |= BIT(tid); BIT 488 drivers/net/wireless/intel/iwlwifi/mvm/sta.c disable_agg_tids |= BIT(tid); BIT 494 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvmsta->tfd_queue_msk &= ~BIT(queue); /* Don't use this queue anymore */ BIT 672 drivers/net/wireless/intel/iwlwifi/mvm/sta.c ret = iwl_trans_wait_tx_queues_empty(mvm->trans, BIT(queue)); BIT 813 drivers/net/wireless/intel/iwlwifi/mvm/sta.c if (mvm->queue_info[queue].tid_bitmap & BIT(tid)) { BIT 823 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvm->queue_info[queue].tid_bitmap |= BIT(tid); BIT 944 drivers/net/wireless/intel/iwlwifi/mvm/sta.c if (tid_bitmap != BIT(tid)) { BIT 977 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvmsta->tid_disable_agg &= ~BIT(tid); BIT 1026 drivers/net/wireless/intel/iwlwifi/mvm/sta.c tid_bitmap &= ~BIT(tid); BIT 1030 drivers/net/wireless/intel/iwlwifi/mvm/sta.c tid_bitmap &= ~BIT(tid); BIT 1047 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvm->queue_info[queue].tid_bitmap &= ~BIT(tid); BIT 1062 drivers/net/wireless/intel/iwlwifi/mvm/sta.c if (!(tid_bitmap & BIT(mvm->queue_info[queue].txq_tid))) BIT 1142 drivers/net/wireless/intel/iwlwifi/mvm/sta.c inactive_tid_bitmap |= BIT(tid); BIT 1332 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvmsta->tfd_queue_msk |= BIT(queue); BIT 2041 drivers/net/wireless/intel/iwlwifi/mvm/sta.c ret = iwl_mvm_allocate_int_sta(mvm, &mvm->aux_sta, BIT(mvm->aux_queue), BIT 2134 drivers/net/wireless/intel/iwlwifi/mvm/sta.c bsta->tfd_queue_msk |= BIT(queue); BIT 2201 drivers/net/wireless/intel/iwlwifi/mvm/sta.c WARN_ON(!(mvmvif->bcast_sta.tfd_queue_msk & BIT(queue))); BIT 2202 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvmvif->bcast_sta.tfd_queue_msk &= ~BIT(queue); BIT 2332 drivers/net/wireless/intel/iwlwifi/mvm/sta.c msta->tfd_queue_msk |= BIT(mvmvif->cab_queue); BIT 2701 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvm_sta->tfd_queue_msk |= BIT(queue); BIT 2702 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvm_sta->tid_disable_agg &= ~BIT(tid); BIT 2705 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvm_sta->tid_disable_agg |= BIT(tid); BIT 2899 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvmsta->agg_tids |= BIT(tid); BIT 2943 drivers/net/wireless/intel/iwlwifi/mvm/sta.c BIT(queue)); BIT 3040 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvmsta->agg_tids &= ~BIT(tid); BIT 3106 drivers/net/wireless/intel/iwlwifi/mvm/sta.c mvmsta->agg_tids &= ~BIT(tid); BIT 3116 drivers/net/wireless/intel/iwlwifi/mvm/sta.c BIT(tid), 0)) BIT 3120 drivers/net/wireless/intel/iwlwifi/mvm/sta.c if (iwl_mvm_flush_tx_path(mvm, BIT(txq_id), 0)) BIT 3122 drivers/net/wireless/intel/iwlwifi/mvm/sta.c iwl_trans_wait_tx_queues_empty(mvm->trans, BIT(txq_id)); BIT 3685 drivers/net/wireless/intel/iwlwifi/mvm/sta.c cmd.awake_acs |= BIT(tid_to_ucode_ac[tid]); BIT 273 drivers/net/wireless/intel/iwlwifi/mvm/time-event.c !(trig_status_bitmap & BIT(le32_to_cpu(notif->status)))) BIT 729 drivers/net/wireless/intel/iwlwifi/mvm/tt.c #define IWL_WRITABLE_TRIPS_MSK (BIT(IWL_MAX_DTS_TRIPS) - 1) BIT 88 drivers/net/wireless/intel/iwlwifi/mvm/tx.c if (!(le16_to_cpu(ba_trig->tx_bar) & BIT(tid))) BIT 159 drivers/net/wireless/intel/iwlwifi/mvm/tx.c offload_assist |= BIT(TX_CMD_OFFLD_L4_EN); BIT 170 drivers/net/wireless/intel/iwlwifi/mvm/tx.c (offload_assist & BIT(TX_CMD_OFFLD_AMSDU))) { BIT 172 drivers/net/wireless/intel/iwlwifi/mvm/tx.c offload_assist |= BIT(TX_CMD_OFFLD_L3_EN); BIT 230 drivers/net/wireless/intel/iwlwifi/mvm/tx.c offload_assist |= BIT(TX_CMD_OFFLD_AMSDU); BIT 299 drivers/net/wireless/intel/iwlwifi/mvm/tx.c !(offload_assist & BIT(TX_CMD_OFFLD_AMSDU))) BIT 300 drivers/net/wireless/intel/iwlwifi/mvm/tx.c offload_assist |= BIT(TX_CMD_OFFLD_PAD); BIT 318 drivers/net/wireless/intel/iwlwifi/mvm/tx.c return BIT(mvmsta->tx_ant) << RATE_MCS_ANT_POS; BIT 321 drivers/net/wireless/intel/iwlwifi/mvm/tx.c return BIT(mvm->mgmt_last_antenna_idx) << RATE_MCS_ANT_POS; BIT 517 drivers/net/wireless/intel/iwlwifi/mvm/tx.c offload_assist |= BIT(TX_CMD_OFFLD_AMSDU); BIT 525 drivers/net/wireless/intel/iwlwifi/mvm/tx.c !(offload_assist & BIT(TX_CMD_OFFLD_AMSDU))) BIT 526 drivers/net/wireless/intel/iwlwifi/mvm/tx.c offload_assist |= BIT(TX_CMD_OFFLD_PAD); BIT 930 drivers/net/wireless/intel/iwlwifi/mvm/tx.c !(mvmsta->amsdu_enabled & BIT(tid))) BIT 2054 drivers/net/wireless/intel/iwlwifi/mvm/tx.c 0xff | BIT(IWL_MGMT_TID), flags); BIT 267 drivers/net/wireless/intel/iwlwifi/mvm/utils.c BUILD_BUG_ON(ANT_A != BIT(0)); /* using ffs is wrong if not */ BIT 269 drivers/net/wireless/intel/iwlwifi/mvm/utils.c return BIT(0); BIT 270 drivers/net/wireless/intel/iwlwifi/mvm/utils.c return BIT(ffs(mask) - 1); BIT 286 drivers/net/wireless/intel/iwlwifi/mvm/utils.c if (valid & BIT(ind)) BIT 1030 drivers/net/wireless/intel/iwlwifi/mvm/utils.c if (!(le16_to_cpu(ba_trig->frame_timeout) & BIT(tid))) BIT 148 drivers/net/wireless/intel/iwlwifi/pcie/internal.h #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0) BIT 424 drivers/net/wireless/intel/iwlwifi/pcie/internal.h IWL_SHARED_IRQ_NON_RX = BIT(0), BIT 425 drivers/net/wireless/intel/iwlwifi/pcie/internal.h IWL_SHARED_IRQ_FIRST_RSS = BIT(1), BIT 626 drivers/net/wireless/intel/iwlwifi/pcie/internal.h iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); BIT 243 drivers/net/wireless/intel/iwlwifi/pcie/rx.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 982 drivers/net/wireless/intel/iwlwifi/pcie/rx.c enabled |= BIT(i) | BIT(i + 16); BIT 136 drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c BIT(trans->trans_cfg->csr->flag_init_done)); BIT 178 drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 188 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_sw_reset)); BIT 216 drivers/net/wireless/intel/iwlwifi/pcie/trans.c size = BIT(power); BIT 234 drivers/net/wireless/intel/iwlwifi/pcie/trans.c (unsigned long)BIT(power - 10), BIT 235 drivers/net/wireless/intel/iwlwifi/pcie/trans.c (unsigned long)BIT(max_power - 10)); BIT 493 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_init_done)); BIT 516 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_stop_master)); BIT 519 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_master_dis), BIT 520 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_master_dis), 100); BIT 570 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_init_done)); BIT 689 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | BIT 690 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | BIT 933 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_set_bit(trans, addr, BIT(val)); BIT 936 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_clear_bit(trans, addr, BIT(val)); BIT 942 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_set_bits_prph(trans, addr, BIT(val)); BIT 945 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_clear_bits_prph(trans, addr, BIT(val)); BIT 948 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (iwl_read_prph(trans, addr) & BIT(val)) { BIT 1171 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val = BIT(MSIX_FH_INT_CAUSES_Q(0)); BIT 1175 drivers/net/wireless/intel/iwlwifi/pcie/trans.c val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); BIT 1274 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 1498 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 1500 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_init_done)); BIT 1565 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 1587 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 2058 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 2083 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_val_mac_access_en), BIT 2084 drivers/net/wireless/intel/iwlwifi/pcie/trans.c (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) | BIT 2166 drivers/net/wireless/intel/iwlwifi/pcie/trans.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 2313 drivers/net/wireless/intel/iwlwifi/pcie/trans.c active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); BIT 2420 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (!(BIT(cnt) & txq_bm)) BIT 3236 drivers/net/wireless/intel/iwlwifi/pcie/trans.c dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); BIT 3245 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) BIT 3251 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) BIT 3255 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) BIT 3259 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { BIT 3284 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) BIT 3297 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { BIT 3337 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) BIT 3339 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) BIT 3346 drivers/net/wireless/intel/iwlwifi/pcie/trans.c dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { BIT 3362 drivers/net/wireless/intel/iwlwifi/pcie/trans.c if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) BIT 3563 drivers/net/wireless/intel/iwlwifi/pcie/trans.c ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); BIT 172 drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c if (meta->tbs & BIT(i)) BIT 455 drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c out_meta->tbs |= BIT(tb_idx); BIT 309 drivers/net/wireless/intel/iwlwifi/pcie/tx.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 423 drivers/net/wireless/intel/iwlwifi/pcie/tx.c if (meta->tbs & BIT(i)) BIT 649 drivers/net/wireless/intel/iwlwifi/pcie/tx.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 1258 drivers/net/wireless/intel/iwlwifi/pcie/tx.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 1261 drivers/net/wireless/intel/iwlwifi/pcie/tx.c BIT(trans->trans_cfg->csr->flag_val_mac_access_en), BIT 1262 drivers/net/wireless/intel/iwlwifi/pcie/tx.c (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) | BIT 1267 drivers/net/wireless/intel/iwlwifi/pcie/tx.c BIT(trans->trans_cfg->csr->flag_mac_access_req)); BIT 1454 drivers/net/wireless/intel/iwlwifi/pcie/tx.c iwl_scd_enable_set_active(trans, BIT(txq_id)); BIT 2050 drivers/net/wireless/intel/iwlwifi/pcie/tx.c out_meta->tbs |= BIT(tb_idx); BIT 472 drivers/net/wireless/intersil/hostap/hostap_80211_tx.c if (((fc & IEEE80211_FCTL_VERS) == BIT(1)) && BIT 619 drivers/net/wireless/intersil/hostap/hostap_ap.c hdr->frame_control |= cpu_to_le16(ok ? BIT(1) : BIT(0)); BIT 1646 drivers/net/wireless/intersil/hostap/hostap_ap.c BIT(14) | BIT(15)); /* AID */ BIT 1884 drivers/net/wireless/intersil/hostap/hostap_ap.c if ((aid & (BIT(15) | BIT(14))) != (BIT(15) | BIT(14))) { BIT 1888 drivers/net/wireless/intersil/hostap/hostap_ap.c aid &= ~(BIT(15) | BIT(14)); BIT 2312 drivers/net/wireless/intersil/hostap/hostap_ap.c hdr->duration_id = cpu_to_le16(sta->aid | BIT(15) | BIT(14)); BIT 13 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_STA_AUTH BIT(0) BIT 14 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_STA_ASSOC BIT(1) BIT 15 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_STA_PS BIT(2) BIT 16 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_STA_TIM BIT(3) /* TIM bit is on for PS stations */ BIT 17 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_STA_PERM BIT(4) /* permanent; do not remove entry on expiration */ BIT 18 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_STA_AUTHORIZED BIT(5) /* If 802.1X is used, this flag is BIT 22 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ BIT 24 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_RATE_1M BIT(0) BIT 25 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_RATE_2M BIT(1) BIT 26 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_RATE_5M5 BIT(2) BIT 27 drivers/net/wireless/intersil/hostap/hostap_ap.h #define WLAN_RATE_11M BIT(3) BIT 133 drivers/net/wireless/intersil/hostap/hostap_ap.h #define PRISM2_AUTH_OPEN BIT(0) BIT 134 drivers/net/wireless/intersil/hostap/hostap_ap.h #define PRISM2_AUTH_SHARED_KEY BIT(1) BIT 409 drivers/net/wireless/intersil/hostap/hostap_common.h #define HOSTAP_CRYPT_FLAG_SET_TX_KEY BIT(0) BIT 410 drivers/net/wireless/intersil/hostap/hostap_common.h #define HOSTAP_CRYPT_FLAG_PERMANENT BIT(1) BIT 607 drivers/net/wireless/intersil/hostap/hostap_hw.c (BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT 608 drivers/net/wireless/intersil/hostap/hostap_hw.c BIT(8))) >> 8; BIT 680 drivers/net/wireless/intersil/hostap/hostap_hw.c (BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT 681 drivers/net/wireless/intersil/hostap/hostap_hw.c BIT(9) | BIT(8))) >> 8; BIT 427 drivers/net/wireless/intersil/hostap/hostap_main.c val &= ~(BIT(2) | BIT(1)); BIT 430 drivers/net/wireless/intersil/hostap/hostap_main.c val |= BIT(1); BIT 435 drivers/net/wireless/intersil/hostap/hostap_main.c val |= BIT(2); BIT 451 drivers/net/wireless/intersil/hostap/hostap_main.c val &= ~(BIT(1) | BIT(0)); BIT 456 drivers/net/wireless/intersil/hostap/hostap_main.c val |= BIT(0); BIT 459 drivers/net/wireless/intersil/hostap/hostap_main.c val |= BIT(0) | BIT(1); BIT 57 drivers/net/wireless/intersil/hostap/hostap_plx.c #define PLX_INTCSR_PCI_INTEN BIT(6) /* PCI Interrupt Enable */ BIT 59 drivers/net/wireless/intersil/hostap/hostap_plx.c #define PLX_CNTRL_SERIAL_EEPROM_PRESENT BIT(28) BIT 367 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_PCI_CTL_FROM_BAP (BIT(5) | BIT(1) | BIT(0)) BIT 368 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_PCI_CTL_TO_BAP (BIT(5) | BIT(0)) BIT 381 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_CMDCODE_ACCESS_WRITE (0x21 | BIT(8)) BIT 394 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_TEST_CFG_BIT_ALC BIT(3) BIT 396 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_CMD_BUSY BIT(15) BIT 398 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_CMD_TX_RECLAIM BIT(8) BIT 400 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_OFFSET_ERR BIT(14) BIT 401 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_OFFSET_BUSY BIT(15) BIT 415 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_AUX_PORT_DISABLE BIT(14) BIT 416 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_AUX_PORT_ENABLE BIT(15) BIT 417 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_AUX_PORT_ENABLED (BIT(14) | BIT(15)) BIT 418 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_AUX_PORT_MASK (BIT(14) | BIT(15)) BIT 424 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_TICK BIT(15) BIT 425 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_WTERR BIT(14) BIT 426 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_INFDROP BIT(13) BIT 428 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_PCI_M1 BIT(9) BIT 429 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_PCI_M0 BIT(8) BIT 431 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_INFO BIT(7) BIT 432 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_DTIM BIT(5) BIT 433 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_CMD BIT(4) BIT 434 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_ALLOC BIT(3) BIT 435 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_TXEXC BIT(2) BIT 436 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_TX BIT(1) BIT 437 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_EV_RX BIT(0) BIT 464 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_RATES_1MBPS BIT(0) BIT 465 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_RATES_2MBPS BIT(1) BIT 466 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_RATES_5MBPS BIT(2) BIT 467 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_RATES_11MBPS BIT(3) BIT 473 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_WEPFLAGS_PRIVACYINVOKED BIT(0) BIT 474 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED BIT(1) BIT 475 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_WEPFLAGS_HOSTENCRYPT BIT(4) BIT 476 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_WEPFLAGS_HOSTDECRYPT BIT(7) BIT 478 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_RX_STATUS_MSGTYPE (BIT(15) | BIT(14) | BIT(13)) BIT 479 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_RX_STATUS_PCF BIT(12) BIT 480 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_RX_STATUS_MACPORT (BIT(10) | BIT(9) | BIT(8)) BIT 481 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_RX_STATUS_UNDECR BIT(1) BIT 482 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_RX_STATUS_FCSERR BIT(0) BIT 493 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_TX_CTRL_ALT_RTRY BIT(5) BIT 494 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_TX_CTRL_802_11 BIT(3) BIT 496 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_TX_CTRL_TX_EX BIT(2) BIT 497 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_TX_CTRL_TX_OK BIT(1) BIT 499 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_TX_STATUS_RETRYERR BIT(0) BIT 500 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_TX_STATUS_AGEDERR BIT(1) BIT 501 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_TX_STATUS_DISCON BIT(2) BIT 502 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HFA384X_TX_STATUS_FORMERR BIT(3) BIT 523 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define PRISM2_DUMP_RX_HDR BIT(0) BIT 524 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define PRISM2_DUMP_TX_HDR BIT(1) BIT 525 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define PRISM2_DUMP_TXEXC_HDR BIT(2) BIT 567 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HOSTAP_HW_NO_DISABLE BIT(0) BIT 568 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HOSTAP_HW_ENABLE_CMDCOMPL BIT(1) BIT 740 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HOSTAP_WDS_BROADCAST_RA BIT(0) BIT 741 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HOSTAP_WDS_AP_CLIENT BIT(1) BIT 742 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HOSTAP_WDS_STANDARD_FRAME BIT(2) BIT 929 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HOSTAP_TX_FLAGS_WDS BIT(0) BIT 930 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HOSTAP_TX_FLAGS_BUFFERED_FRAME BIT(1) BIT 931 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define HOSTAP_TX_FLAGS_ADD_MOREDATA BIT(2) BIT 942 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define DEBUG_FID BIT(0) BIT 943 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define DEBUG_PS BIT(1) BIT 944 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define DEBUG_FLOW BIT(2) BIT 945 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define DEBUG_AP BIT(3) BIT 946 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define DEBUG_HW BIT(4) BIT 947 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define DEBUG_EXTRA BIT(5) BIT 948 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define DEBUG_EXTRA2 BIT(6) BIT 949 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define DEBUG_PS2 BIT(7) BIT 44 drivers/net/wireless/intersil/orinoco/cfg.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); BIT 50 drivers/net/wireless/intersil/orinoco/cfg.c wiphy->interface_modes |= BIT(NL80211_IFTYPE_ADHOC); BIT 53 drivers/net/wireless/intersil/orinoco/cfg.c wiphy->interface_modes |= BIT(NL80211_IFTYPE_MONITOR); BIT 66 drivers/net/wireless/intersil/p54/eeprom.c #define CHAN_HAS_CAL BIT(0) BIT 67 drivers/net/wireless/intersil/p54/eeprom.c #define CHAN_HAS_LIMIT BIT(1) BIT 68 drivers/net/wireless/intersil/p54/eeprom.c #define CHAN_HAS_CURVE BIT(2) BIT 40 drivers/net/wireless/intersil/p54/led.c priv->softled_state |= BIT(i); BIT 52 drivers/net/wireless/intersil/p54/led.c priv->softled_state &= ~BIT(i); BIT 49 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_CONTROL BIT(15) BIT 50 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_CONTROL_OPSET (BIT(15) + BIT(0)) BIT 51 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_ALIGN BIT(14) BIT 53 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_PROMISC BIT(0) BIT 54 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_TIMESTAMP BIT(1) BIT 55 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_SEQNR BIT(2) BIT 56 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_BIT3 BIT(3) BIT 57 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_BURST BIT(4) BIT 58 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_NOCANCEL BIT(5) BIT 59 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_CLEARTIM BIT(6) BIT 60 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_HITCHHIKE BIT(7) BIT 61 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_COMPRESS BIT(8) BIT 62 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_CONCAT BIT(9) BIT 63 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_PCS_ACCEPT BIT(10) BIT 64 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_OUT_WAITEOSP BIT(11) BIT 66 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_IN_FCS_GOOD BIT(0) BIT 67 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_IN_MATCH_MAC BIT(1) BIT 68 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_IN_MCBC BIT(2) BIT 69 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_IN_BEACON BIT(3) BIT 70 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_IN_MATCH_BSS BIT(4) BIT 71 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_IN_BCAST_BSS BIT(5) BIT 72 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_IN_DATA BIT(6) BIT 73 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_IN_TRUNCATED BIT(7) BIT 74 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_IN_BIT8 BIT(8) BIT 75 drivers/net/wireless/intersil/p54/lmac.h #define P54_HDR_FLAG_DATA_IN_TRANSPARENT BIT(9) BIT 279 drivers/net/wireless/intersil/p54/lmac.h #define P54_FILTER_TYPE_STATION BIT(0) BIT 280 drivers/net/wireless/intersil/p54/lmac.h #define P54_FILTER_TYPE_IBSS BIT(1) BIT 281 drivers/net/wireless/intersil/p54/lmac.h #define P54_FILTER_TYPE_AP BIT(2) BIT 282 drivers/net/wireless/intersil/p54/lmac.h #define P54_FILTER_TYPE_TRANSPARENT BIT(3) BIT 283 drivers/net/wireless/intersil/p54/lmac.h #define P54_FILTER_TYPE_PROMISCUOUS BIT(4) BIT 284 drivers/net/wireless/intersil/p54/lmac.h #define P54_FILTER_TYPE_HIBERNATE BIT(5) BIT 285 drivers/net/wireless/intersil/p54/lmac.h #define P54_FILTER_TYPE_NOACK BIT(6) BIT 286 drivers/net/wireless/intersil/p54/lmac.h #define P54_FILTER_TYPE_RX_DISABLED BIT(7) BIT 325 drivers/net/wireless/intersil/p54/lmac.h #define P54_SCAN_EXIT BIT(0) BIT 326 drivers/net/wireless/intersil/p54/lmac.h #define P54_SCAN_TRAP BIT(1) BIT 327 drivers/net/wireless/intersil/p54/lmac.h #define P54_SCAN_ACTIVE BIT(2) BIT 328 drivers/net/wireless/intersil/p54/lmac.h #define P54_SCAN_FILTER BIT(3) BIT 460 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM BIT(0) BIT 461 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM_DTIM BIT(1) BIT 462 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM_MCBC BIT(2) BIT 463 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM_CHECKSUM BIT(3) BIT 464 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM_SKIP_MORE_DATA BIT(4) BIT 465 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM_BEACON_TIMEOUT BIT(5) BIT 466 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM_HFOSLEEP BIT(6) BIT 467 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM_AUTOSWITCH_SLEEP BIT(7) BIT 468 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM_LPIT BIT(8) BIT 469 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM_BF_UCAST_SKIP BIT(9) BIT 470 drivers/net/wireless/intersil/p54/lmac.h #define P54_PSM_BF_MCAST_SKIP BIT(10) BIT 499 drivers/net/wireless/intersil/p54/lmac.h #define P54_TIM_CLEAR BIT(15) BIT 750 drivers/net/wireless/intersil/p54/main.c dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 751 drivers/net/wireless/intersil/p54/main.c BIT(NL80211_IFTYPE_ADHOC) | BIT 752 drivers/net/wireless/intersil/p54/main.c BIT(NL80211_IFTYPE_AP) | BIT 753 drivers/net/wireless/intersil/p54/main.c BIT(NL80211_IFTYPE_MESH_POINT); BIT 40 drivers/net/wireless/intersil/p54/p54.h #define BR_DESC_PRIV_CAP_WEP BIT(0) BIT 41 drivers/net/wireless/intersil/p54/p54.h #define BR_DESC_PRIV_CAP_TKIP BIT(1) BIT 42 drivers/net/wireless/intersil/p54/p54.h #define BR_DESC_PRIV_CAP_MICHAEL BIT(2) BIT 43 drivers/net/wireless/intersil/p54/p54.h #define BR_DESC_PRIV_CAP_CCX_CP BIT(3) BIT 44 drivers/net/wireless/intersil/p54/p54.h #define BR_DESC_PRIV_CAP_CCX_MIC BIT(4) BIT 45 drivers/net/wireless/intersil/p54/p54.h #define BR_DESC_PRIV_CAP_AESCCMP BIT(5) BIT 1200 drivers/net/wireless/mac80211_hwsim.c rtap->present = BIT(0); BIT 2503 drivers/net/wireless/mac80211_hwsim.c .types_mask = BIT(NL80211_IFTYPE_STATION) | BIT 2504 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_AP), BIT 2551 drivers/net/wireless/mac80211_hwsim.c .types_mask = BIT(NL80211_IFTYPE_MESH_POINT), BIT 2593 drivers/net/wireless/mac80211_hwsim.c .types_mask = BIT(NL80211_IFTYPE_STATION) | BIT 2594 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_AP), BIT 2645 drivers/net/wireless/mac80211_hwsim.c .types_mask = BIT(NL80211_IFTYPE_MESH_POINT), BIT 2708 drivers/net/wireless/mac80211_hwsim.c #define HWSIM_MESH_BIT BIT(NL80211_IFTYPE_MESH_POINT) BIT 2714 drivers/net/wireless/mac80211_hwsim.c (BIT(NL80211_IFTYPE_STATION) | \ BIT 2715 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_P2P_CLIENT) | \ BIT 2716 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_AP) | \ BIT 2717 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_P2P_GO) | \ BIT 2721 drivers/net/wireless/mac80211_hwsim.c (BIT(NL80211_IFTYPE_STATION) | \ BIT 2722 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_AP) | \ BIT 2723 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_P2P_CLIENT) | \ BIT 2724 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_P2P_GO) | \ BIT 2725 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_ADHOC) | \ BIT 2726 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_MESH_POINT)) BIT 2816 drivers/net/wireless/mac80211_hwsim.c if (param->iftypes & BIT(NL80211_IFTYPE_ADHOC)) { BIT 2818 drivers/net/wireless/mac80211_hwsim.c data->if_limits[n_limits].types = BIT(NL80211_IFTYPE_ADHOC); BIT 2834 drivers/net/wireless/mac80211_hwsim.c if (param->iftypes & BIT(NL80211_IFTYPE_P2P_DEVICE)) { BIT 2837 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_P2P_DEVICE); BIT 2850 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT 2851 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_CHAN_WIDTH_20) | BIT 2852 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_CHAN_WIDTH_40) | BIT 2853 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_CHAN_WIDTH_80) | BIT 2854 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_CHAN_WIDTH_160); BIT 3159 drivers/net/wireless/mac80211_hwsim.c BIT(NL80211_IFTYPE_P2P_DEVICE)); BIT 3542 drivers/net/wireless/mac80211_hwsim.c param.iftypes & BIT(NL80211_IFTYPE_P2P_DEVICE)) { BIT 3543 drivers/net/wireless/mac80211_hwsim.c param.iftypes |= BIT(NL80211_IFTYPE_P2P_DEVICE); BIT 4011 drivers/net/wireless/mac80211_hwsim.c param.iftypes |= BIT(NL80211_IFTYPE_P2P_DEVICE); BIT 23 drivers/net/wireless/mac80211_hwsim.h HWSIM_TX_CTL_REQ_TX_STATUS = BIT(0), BIT 24 drivers/net/wireless/mac80211_hwsim.h HWSIM_TX_CTL_NO_ACK = BIT(1), BIT 25 drivers/net/wireless/mac80211_hwsim.h HWSIM_TX_STAT_ACK = BIT(2), BIT 216 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_USE_RTS_CTS = BIT(0), BIT 217 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_USE_CTS_PROTECT = BIT(1), BIT 218 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_USE_SHORT_PREAMBLE = BIT(2), BIT 221 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_MCS = BIT(3), BIT 222 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_GREEN_FIELD = BIT(4), BIT 223 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_40_MHZ_WIDTH = BIT(5), BIT 224 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_DUP_DATA = BIT(6), BIT 225 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_SHORT_GI = BIT(7), BIT 226 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_VHT_MCS = BIT(8), BIT 227 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_80_MHZ_WIDTH = BIT(9), BIT 228 drivers/net/wireless/mac80211_hwsim.h MAC80211_HWSIM_TX_RC_160_MHZ_WIDTH = BIT(10), BIT 2113 drivers/net/wireless/marvell/libertas/cfg.c BIT(NL80211_IFTYPE_STATION) | BIT 2114 drivers/net/wireless/marvell/libertas/cfg.c BIT(NL80211_IFTYPE_ADHOC); BIT 2116 drivers/net/wireless/marvell/libertas/cfg.c wdev->wiphy->interface_modes |= BIT(NL80211_IFTYPE_MONITOR); BIT 2118 drivers/net/wireless/marvell/libertas/cfg.c wdev->wiphy->interface_modes |= BIT(NL80211_IFTYPE_MESH_POINT); BIT 586 drivers/net/wireless/marvell/libertas_tf/main.c BIT(NL80211_IFTYPE_STATION) | BIT 587 drivers/net/wireless/marvell/libertas_tf/main.c BIT(NL80211_IFTYPE_ADHOC); BIT 23 drivers/net/wireless/marvell/mwifiex/11ac.h #define VHT_CFG_2GHZ BIT(0) BIT 24 drivers/net/wireless/marvell/mwifiex/11ac.h #define VHT_CFG_5GHZ BIT(1) BIT 35 drivers/net/wireless/marvell/mwifiex/11ac.h #define VHT_BW_80_160_80P80 BIT(2) BIT 30 drivers/net/wireless/marvell/mwifiex/cfg80211.c .max = 3, .types = BIT(NL80211_IFTYPE_STATION) | BIT 31 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_IFTYPE_P2P_GO) | BIT 32 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 33 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_IFTYPE_AP), BIT 44 drivers/net/wireless/marvell/mwifiex/cfg80211.c .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT 45 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_CHAN_WIDTH_20) | BIT 46 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_CHAN_WIDTH_40), BIT 56 drivers/net/wireless/marvell/mwifiex/cfg80211.c .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT 57 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_CHAN_WIDTH_20) | BIT 58 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_CHAN_WIDTH_40) | BIT 59 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_CHAN_WIDTH_80), BIT 280 drivers/net/wireless/marvell/mwifiex/cfg80211.c mask = priv->mgmt_frame_mask | BIT(frame_type >> 4); BIT 282 drivers/net/wireless/marvell/mwifiex/cfg80211.c mask = priv->mgmt_frame_mask & ~BIT(frame_type >> 4); BIT 1294 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (htinfo & BIT(0)) { BIT 1299 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (htinfo & BIT(1)) { BIT 1305 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (htinfo & (BIT(1) | BIT(0))) { BIT 1307 drivers/net/wireless/marvell/mwifiex/cfg80211.c switch (htinfo & (BIT(3) | BIT(2))) { BIT 1311 drivers/net/wireless/marvell/mwifiex/cfg80211.c case (BIT(2)): BIT 1314 drivers/net/wireless/marvell/mwifiex/cfg80211.c case (BIT(3)): BIT 1317 drivers/net/wireless/marvell/mwifiex/cfg80211.c case (BIT(3) | BIT(2)): BIT 1322 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (htinfo & BIT(4)) BIT 1335 drivers/net/wireless/marvell/mwifiex/cfg80211.c if ((htinfo & BIT(0)) && (rateinfo < 16)) { BIT 1339 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (htinfo & BIT(1)) BIT 1341 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (htinfo & BIT(2)) BIT 1347 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (!(htinfo & (BIT(0) | BIT(1)))) { BIT 1448 drivers/net/wireless/marvell/mwifiex/cfg80211.c sinfo->filled |= BIT(NL80211_STA_INFO_RX_BITRATE); BIT 1668 drivers/net/wireless/marvell/mwifiex/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 1669 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 1670 drivers/net/wireless/marvell/mwifiex/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 1671 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4), BIT 1674 drivers/net/wireless/marvell/mwifiex/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 1675 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 1676 drivers/net/wireless/marvell/mwifiex/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 1677 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4), BIT 1680 drivers/net/wireless/marvell/mwifiex/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 1681 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 1682 drivers/net/wireless/marvell/mwifiex/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 1683 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4), BIT 1686 drivers/net/wireless/marvell/mwifiex/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 1687 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(IEEE80211_STYPE_PROBE_RESP >> 4), BIT 1688 drivers/net/wireless/marvell/mwifiex/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 1689 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4), BIT 1882 drivers/net/wireless/marvell/mwifiex/cfg80211.c (tx_ant != BIT(adapter->number_of_antenna) - 1)) BIT 1885 drivers/net/wireless/marvell/mwifiex/cfg80211.c if ((tx_ant == BIT(adapter->number_of_antenna) - 1) && BIT 3922 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (!(params->sta_flags_set & BIT(NL80211_STA_FLAG_TDLS_PEER))) BIT 4159 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (!(params->sta_flags_set & BIT(NL80211_STA_FLAG_TDLS_PEER))) BIT 4322 drivers/net/wireless/marvell/mwifiex/cfg80211.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 4323 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 4324 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_IFTYPE_P2P_GO) | BIT 4325 drivers/net/wireless/marvell/mwifiex/cfg80211.c BIT(NL80211_IFTYPE_AP); BIT 4328 drivers/net/wireless/marvell/mwifiex/cfg80211.c wiphy->interface_modes |= BIT(NL80211_IFTYPE_ADHOC); BIT 4386 drivers/net/wireless/marvell/mwifiex/cfg80211.c wiphy->available_antennas_tx = BIT(adapter->number_of_antenna) - 1; BIT 4387 drivers/net/wireless/marvell/mwifiex/cfg80211.c wiphy->available_antennas_rx = BIT(adapter->number_of_antenna) - 1; BIT 260 drivers/net/wireless/marvell/mwifiex/cfp.c if (ht_info & BIT(0)) { BIT 262 drivers/net/wireless/marvell/mwifiex/cfp.c if (ht_info & BIT(2)) BIT 267 drivers/net/wireless/marvell/mwifiex/cfp.c if (ht_info & BIT(1)) { BIT 268 drivers/net/wireless/marvell/mwifiex/cfp.c if (ht_info & BIT(2)) BIT 275 drivers/net/wireless/marvell/mwifiex/cfp.c if (ht_info & BIT(2)) BIT 413 drivers/net/wireless/marvell/mwifiex/cfp.c if ((BIT(i) & rate_mask) == 0) BIT 525 drivers/net/wireless/marvell/mwifiex/cfp.c if ((rate_info & BIT(0)) && (rate_info & BIT(1))) BIT 528 drivers/net/wireless/marvell/mwifiex/cfp.c else if (rate_info & BIT(0)) /* HT20 */ BIT 86 drivers/net/wireless/marvell/mwifiex/decl.h #define MWIFIEX_BUF_FLAG_REQUEUED_PKT BIT(0) BIT 87 drivers/net/wireless/marvell/mwifiex/decl.h #define MWIFIEX_BUF_FLAG_BRIDGED_PKT BIT(1) BIT 88 drivers/net/wireless/marvell/mwifiex/decl.h #define MWIFIEX_BUF_FLAG_TDLS_PKT BIT(2) BIT 89 drivers/net/wireless/marvell/mwifiex/decl.h #define MWIFIEX_BUF_FLAG_EAPOL_TX_STATUS BIT(3) BIT 90 drivers/net/wireless/marvell/mwifiex/decl.h #define MWIFIEX_BUF_FLAG_ACTION_TX_STATUS BIT(4) BIT 91 drivers/net/wireless/marvell/mwifiex/decl.h #define MWIFIEX_BUF_FLAG_AGGR_PKT BIT(5) BIT 160 drivers/net/wireless/marvell/mwifiex/decl.h #define BSS_ROLE_BIT_MASK BIT(0) BIT 82 drivers/net/wireless/marvell/mwifiex/fw.h #define FW_MULTI_BANDS_SUPPORT (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \ BIT 83 drivers/net/wireless/marvell/mwifiex/fw.h BIT(13)) BIT 116 drivers/net/wireless/marvell/mwifiex/fw.h #define KEY_MCAST BIT(0) BIT 117 drivers/net/wireless/marvell/mwifiex/fw.h #define KEY_UNICAST BIT(1) BIT 118 drivers/net/wireless/marvell/mwifiex/fw.h #define KEY_ENABLED BIT(2) BIT 119 drivers/net/wireless/marvell/mwifiex/fw.h #define KEY_DEFAULT BIT(3) BIT 120 drivers/net/wireless/marvell/mwifiex/fw.h #define KEY_TX_KEY BIT(4) BIT 121 drivers/net/wireless/marvell/mwifiex/fw.h #define KEY_RX_KEY BIT(5) BIT 122 drivers/net/wireless/marvell/mwifiex/fw.h #define KEY_IGTK BIT(10) BIT 240 drivers/net/wireless/marvell/mwifiex/fw.h BIT(DELBA_INITIATOR_POS)) >> DELBA_INITIATOR_POS) BIT 246 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_11NENABLED(FwCapInfo) (FwCapInfo & BIT(11)) BIT 247 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_TDLS_ENABLED(FwCapInfo) (FwCapInfo & BIT(14)) BIT 248 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_DRCS_ENABLED(FwCapInfo) (FwCapInfo & BIT(15)) BIT 249 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_SDIO_SPA_ENABLED(FwCapInfo) (FwCapInfo & BIT(16)) BIT 250 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_ADHOC_ENABLED(FwCapInfo) (FwCapInfo & BIT(25)) BIT 251 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_RANDOM_MAC(FwCapInfo) (FwCapInfo & BIT(27)) BIT 252 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_FIRMWARE_SUPPLICANT(FwCapInfo) (FwCapInfo & BIT(21)) BIT 275 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_CHANWIDTH40(Dot11nDevCap) (Dot11nDevCap & BIT(17)) BIT 276 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_SHORTGI20(Dot11nDevCap) (Dot11nDevCap & BIT(23)) BIT 277 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_SHORTGI40(Dot11nDevCap) (Dot11nDevCap & BIT(24)) BIT 278 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_TXSTBC(Dot11nDevCap) (Dot11nDevCap & BIT(25)) BIT 279 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_RXSTBC(Dot11nDevCap) (Dot11nDevCap & BIT(26)) BIT 280 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_GREENFIELD(Dot11nDevCap) (Dot11nDevCap & BIT(29)) BIT 281 drivers/net/wireless/marvell/mwifiex/fw.h #define ISENABLED_40MHZ_INTOLERANT(Dot11nDevCap) (Dot11nDevCap & BIT(8)) BIT 282 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_RXLDPC(Dot11nDevCap) (Dot11nDevCap & BIT(22)) BIT 283 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_BEAMFORMING(Dot11nDevCap) (Dot11nDevCap & BIT(30)) BIT 284 drivers/net/wireless/marvell/mwifiex/fw.h #define ISALLOWED_CHANWIDTH40(ht_param) (ht_param & BIT(2)) BIT 296 drivers/net/wireless/marvell/mwifiex/fw.h #define MWIFIEX_FW_DEF_HTTXCFG (BIT(1) | BIT(4) | BIT(5) | BIT(6)) BIT 321 drivers/net/wireless/marvell/mwifiex/fw.h #define ISSUPP_11ACENABLED(fw_cap_info) (fw_cap_info & BIT(13)) BIT 451 drivers/net/wireless/marvell/mwifiex/fw.h MWIFIEX_CHANNEL_PASSIVE = BIT(0), BIT 452 drivers/net/wireless/marvell/mwifiex/fw.h MWIFIEX_CHANNEL_DFS = BIT(1), BIT 453 drivers/net/wireless/marvell/mwifiex/fw.h MWIFIEX_CHANNEL_NOHT40 = BIT(2), BIT 454 drivers/net/wireless/marvell/mwifiex/fw.h MWIFIEX_CHANNEL_NOHT80 = BIT(3), BIT 455 drivers/net/wireless/marvell/mwifiex/fw.h MWIFIEX_CHANNEL_DISABLED = BIT(7), BIT 465 drivers/net/wireless/marvell/mwifiex/fw.h #define HostCmd_ACT_MAC_RX_ON BIT(0) BIT 466 drivers/net/wireless/marvell/mwifiex/fw.h #define HostCmd_ACT_MAC_TX_ON BIT(1) BIT 467 drivers/net/wireless/marvell/mwifiex/fw.h #define HostCmd_ACT_MAC_WEP_ENABLE BIT(3) BIT 468 drivers/net/wireless/marvell/mwifiex/fw.h #define HostCmd_ACT_MAC_ETHERNETII_ENABLE BIT(4) BIT 469 drivers/net/wireless/marvell/mwifiex/fw.h #define HostCmd_ACT_MAC_PROMISCUOUS_ENABLE BIT(7) BIT 470 drivers/net/wireless/marvell/mwifiex/fw.h #define HostCmd_ACT_MAC_ALL_MULTICAST_ENABLE BIT(8) BIT 471 drivers/net/wireless/marvell/mwifiex/fw.h #define HostCmd_ACT_MAC_ADHOC_G_PROTECTION_ON BIT(13) BIT 472 drivers/net/wireless/marvell/mwifiex/fw.h #define HostCmd_ACT_MAC_DYNAMIC_BW_ENABLE BIT(16) BIT 614 drivers/net/wireless/marvell/mwifiex/fw.h #define MWIFIEX_CRITERIA_BROADCAST BIT(0) BIT 615 drivers/net/wireless/marvell/mwifiex/fw.h #define MWIFIEX_CRITERIA_UNICAST BIT(1) BIT 616 drivers/net/wireless/marvell/mwifiex/fw.h #define MWIFIEX_CRITERIA_MULTICAST BIT(3) BIT 646 drivers/net/wireless/marvell/mwifiex/fw.h #define MWIFIEX_MASTER_RADAR_DET_MASK BIT(1) BIT 768 drivers/net/wireless/marvell/mwifiex/fw.h MWIFIEX_PASSIVE_SCAN = BIT(0), BIT 769 drivers/net/wireless/marvell/mwifiex/fw.h MWIFIEX_DISABLE_CHAN_FILT = BIT(1), BIT 770 drivers/net/wireless/marvell/mwifiex/fw.h MWIFIEX_HIDDEN_SSID_REPORT = BIT(4), BIT 383 drivers/net/wireless/marvell/mwifiex/ioctl.h #define BITMASK_BCN_RSSI_LOW BIT(0) BIT 384 drivers/net/wireless/marvell/mwifiex/ioctl.h #define BITMASK_BCN_RSSI_HIGH BIT(4) BIT 29 drivers/net/wireless/marvell/mwifiex/join.c #define CAPINFO_MASK (~(BIT(15) | BIT(14) | BIT(12) | BIT(11) | BIT(9))) BIT 662 drivers/net/wireless/marvell/mwifiex/join.c if ((aid & (BIT(15) | BIT(14))) != (BIT(15) | BIT(14))) BIT 667 drivers/net/wireless/marvell/mwifiex/join.c aid &= ~(BIT(15) | BIT(14)); BIT 73 drivers/net/wireless/marvell/mwifiex/main.h #define MWIFIEX_DRIVER_MODE_STA BIT(0) BIT 74 drivers/net/wireless/marvell/mwifiex/main.h #define MWIFIEX_DRIVER_MODE_UAP BIT(1) BIT 75 drivers/net/wireless/marvell/mwifiex/main.h #define MWIFIEX_DRIVER_MODE_P2P BIT(2) BIT 76 drivers/net/wireless/marvell/mwifiex/main.h #define MWIFIEX_DRIVER_MODE_BITMASK (BIT(0) | BIT(1) | BIT(2)) BIT 2191 drivers/net/wireless/marvell/mwifiex/pcie.c if (len & BIT(0)) { BIT 2204 drivers/net/wireless/marvell/mwifiex/pcie.c len &= ~BIT(0); BIT 2371 drivers/net/wireless/marvell/mwifiex/pcie.c pcie_ireg = BIT(msg_id); BIT 85 drivers/net/wireless/marvell/mwifiex/pcie.h #define CPU_INTR_DNLD_RDY BIT(0) BIT 86 drivers/net/wireless/marvell/mwifiex/pcie.h #define CPU_INTR_DOOR_BELL BIT(1) BIT 87 drivers/net/wireless/marvell/mwifiex/pcie.h #define CPU_INTR_SLEEP_CFM_DONE BIT(2) BIT 88 drivers/net/wireless/marvell/mwifiex/pcie.h #define CPU_INTR_RESET BIT(3) BIT 89 drivers/net/wireless/marvell/mwifiex/pcie.h #define CPU_INTR_EVENT_DONE BIT(5) BIT 91 drivers/net/wireless/marvell/mwifiex/pcie.h #define HOST_INTR_DNLD_DONE BIT(0) BIT 92 drivers/net/wireless/marvell/mwifiex/pcie.h #define HOST_INTR_UPLD_RDY BIT(1) BIT 93 drivers/net/wireless/marvell/mwifiex/pcie.h #define HOST_INTR_CMD_DONE BIT(2) BIT 94 drivers/net/wireless/marvell/mwifiex/pcie.h #define HOST_INTR_EVENT_RDY BIT(3) BIT 100 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7) BIT 101 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0) BIT 102 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1) BIT 103 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_SOP BIT(0) BIT 104 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_EOP BIT(1) BIT 105 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_XS_SOP BIT(2) BIT 106 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_XS_EOP BIT(3) BIT 107 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7) BIT 108 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10) BIT 109 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16) BIT 110 drivers/net/wireless/marvell/mwifiex/pcie.h #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26) BIT 249 drivers/net/wireless/marvell/mwifiex/pcie.h .tx_rollover_ind = BIT(28), BIT 250 drivers/net/wireless/marvell/mwifiex/pcie.h .rx_rollover_ind = BIT(12), BIT 1881 drivers/net/wireless/marvell/mwifiex/scan.c (BIT(0) | BIT(1))); BIT 1076 drivers/net/wireless/marvell/mwifiex/sdio.c if (len & BIT(0)) { BIT 1088 drivers/net/wireless/marvell/mwifiex/sdio.c len &= ~BIT(0); BIT 1391 drivers/net/wireless/marvell/mwifiex/sdio.c if (card->mpa_rx.ports & BIT(i)) BIT 1824 drivers/net/wireless/marvell/mwifiex/sdio.c if (card->mpa_tx.ports & BIT(i)) BIT 78 drivers/net/wireless/marvell/mwifiex/sdio.h #define AUTO_RE_ENABLE_INT BIT(4) BIT 224 drivers/net/wireless/marvell/mwifiex/tdls.c ht_oper->ht_param |= BIT(2); BIT 532 drivers/net/wireless/marvell/mwifiex/uap_cmd.c (((bss_cfg->band_cfg & BIT(0)) == BAND_CONFIG_BG && BIT 534 drivers/net/wireless/marvell/mwifiex/uap_cmd.c ((bss_cfg->band_cfg & BIT(0)) == BAND_CONFIG_A && BIT 24 drivers/net/wireless/marvell/mwifiex/wmm.h MWIFIEX_AIFSN = (BIT(0) | BIT(1) | BIT(2) | BIT(3)), BIT 25 drivers/net/wireless/marvell/mwifiex/wmm.h MWIFIEX_ACM = BIT(4), BIT 26 drivers/net/wireless/marvell/mwifiex/wmm.h MWIFIEX_ACI = (BIT(5) | BIT(6)), BIT 30 drivers/net/wireless/marvell/mwifiex/wmm.h MWIFIEX_ECW_MIN = (BIT(0) | BIT(1) | BIT(2) | BIT(3)), BIT 31 drivers/net/wireless/marvell/mwifiex/wmm.h MWIFIEX_ECW_MAX = (BIT(4) | BIT(5) | BIT(6) | BIT(7)), BIT 6059 drivers/net/wireless/marvell/mwl8k.c { .max = 8, .types = BIT(NL80211_IFTYPE_AP) }, BIT 6060 drivers/net/wireless/marvell/mwl8k.c { .max = 1, .types = BIT(NL80211_IFTYPE_STATION) }, BIT 6151 drivers/net/wireless/marvell/mwl8k.c hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP); BIT 6152 drivers/net/wireless/marvell/mwl8k.c hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION); BIT 6158 drivers/net/wireless/marvell/mwl8k.c hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION); BIT 13 drivers/net/wireless/mediatek/mt76/dma.h #define MT_DMA_CTL_LAST_SEC1 BIT(14) BIT 14 drivers/net/wireless/mediatek/mt76/dma.h #define MT_DMA_CTL_BURST BIT(15) BIT 16 drivers/net/wireless/mediatek/mt76/dma.h #define MT_DMA_CTL_LAST_SEC0 BIT(30) BIT 17 drivers/net/wireless/mediatek/mt76/dma.h #define MT_DMA_CTL_DMA_DONE BIT(31) BIT 859 drivers/net/wireless/mediatek/mt76/mac80211.c idx &= ~BIT(2); /* short preamble */ BIT 189 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_WCID_TX_INFO_SET BIT(31) BIT 251 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_TX_CB_DMA_DONE BIT(0) BIT 252 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_TX_CB_TXS_DONE BIT(1) BIT 253 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_TX_CB_TXS_FAILED BIT(2) BIT 259 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_PACKET_ID_HAS_RATE BIT(7) BIT 285 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_TXWI_NO_FREE BIT(0) BIT 346 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_VEND_TYPE_EEPROM BIT(31) BIT 347 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_VEND_TYPE_CFG BIT(30) BIT 19 drivers/net/wireless/mediatek/mt76/mt7603/beacon.c if (!(dev->mt76.beacon_mask & BIT(mvif->idx))) BIT 51 drivers/net/wireless/mediatek/mt76/mt7603/beacon.c if (!(dev->mt76.beacon_mask & BIT(mvif->idx))) BIT 90 drivers/net/wireless/mediatek/mt76/mt7603/beacon.c mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0)); BIT 150 drivers/net/wireless/mediatek/mt76/mt7603/beacon.c dev->mt76.beacon_mask |= BIT(idx); BIT 152 drivers/net/wireless/mediatek/mt76/mt7603/beacon.c dev->mt76.beacon_mask &= ~BIT(idx); BIT 184 drivers/net/wireless/mediatek/mt76/mt7603/beacon.c if (dev->mt76.beacon_mask & ~BIT(0)) BIT 108 drivers/net/wireless/mediatek/mt76/mt7603/init.c mt76_set(dev, MT_SCH_4, BIT(6)); BIT 173 drivers/net/wireless/mediatek/mt76/mt7603/init.c mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13)); BIT 174 drivers/net/wireless/mediatek/mt76/mt7603/init.c mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13)); BIT 176 drivers/net/wireless/mediatek/mt76/mt7603/init.c mt76_clear(dev, MT_WF_RMAC_TMR_PA, BIT(31)); BIT 259 drivers/net/wireless/mediatek/mt76/mt7603/init.c mt76_clear(dev, MT_SEC_SCR, BIT(18)); BIT 336 drivers/net/wireless/mediatek/mt76/mt7603/init.c .types = BIT(NL80211_IFTYPE_ADHOC) BIT 339 drivers/net/wireless/mediatek/mt76/mt7603/init.c .types = BIT(NL80211_IFTYPE_STATION) | BIT 341 drivers/net/wireless/mediatek/mt76/mt7603/init.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 343 drivers/net/wireless/mediatek/mt76/mt7603/init.c BIT(NL80211_IFTYPE_AP) BIT 455 drivers/net/wireless/mediatek/mt76/mt7603/init.c bool sign = val & BIT(6); BIT 457 drivers/net/wireless/mediatek/mt76/mt7603/init.c if (!(val & BIT(7))) BIT 473 drivers/net/wireless/mediatek/mt76/mt7603/init.c int target_power = eeprom[MT_EE_TX_POWER_0_START_2G + 2] & ~BIT(7); BIT 475 drivers/net/wireless/mediatek/mt76/mt7603/init.c bool ext_pa = eeprom[MT_EE_NIC_CONF_0 + 1] & BIT(1); BIT 480 drivers/net/wireless/mediatek/mt76/mt7603/init.c target_power = eeprom[MT_EE_TX_POWER_TSSI_OFF] & ~BIT(7); BIT 482 drivers/net/wireless/mediatek/mt76/mt7603/init.c if (target_power & BIT(6)) BIT 499 drivers/net/wireless/mediatek/mt76/mt7603/init.c if (dev->mt76.antenna_mask & BIT(1)) BIT 535 drivers/net/wireless/mediatek/mt76/mt7603/init.c if (mt76_rr(dev, MT_EFUSE_BASE + 0x64) & BIT(4)) BIT 565 drivers/net/wireless/mediatek/mt76/mt7603/init.c BIT(NL80211_IFTYPE_STATION) | BIT 566 drivers/net/wireless/mediatek/mt76/mt7603/init.c BIT(NL80211_IFTYPE_AP) | BIT 568 drivers/net/wireless/mediatek/mt76/mt7603/init.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 570 drivers/net/wireless/mediatek/mt76/mt7603/init.c BIT(NL80211_IFTYPE_ADHOC); BIT 15 drivers/net/wireless/mediatek/mt76/mt7603/mac.c ret |= GENMASK(3, 0) * !!(mask & BIT(0)); BIT 16 drivers/net/wireless/mediatek/mt76/mt7603/mac.c ret |= GENMASK(8, 5) * !!(mask & BIT(1)); BIT 17 drivers/net/wireless/mediatek/mt76/mt7603/mac.c ret |= GENMASK(13, 10) * !!(mask & BIT(2)); BIT 18 drivers/net/wireless/mediatek/mt76/mt7603/mac.c ret |= GENMASK(19, 16) * !!(mask & BIT(3)); BIT 350 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) | BIT 367 drivers/net/wireless/mediatek/mt76/mt7603/mac.c tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) | BIT 515 drivers/net/wireless/mediatek/mt76/mt7603/mac.c if (status->chains & BIT(1)) BIT 612 drivers/net/wireless/mediatek/mt76/mt7603/mac.c rateset = !(sta->rate_set_tsf & BIT(0)); BIT 706 drivers/net/wireless/mediatek/mt76/mt7603/mac.c sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset; BIT 1006 drivers/net/wireless/mediatek/mt76/mt7603/mac.c rs_idx ^= rate_set_tsf & BIT(0); BIT 1367 drivers/net/wireless/mediatek/mt76/mt7603/mac.c return mt7603_dma_debug(dev, 9) & BIT(9); BIT 1369 drivers/net/wireless/mediatek/mt76/mt7603/mac.c return mt7603_dma_debug(dev, 2) & BIT(8); BIT 1388 drivers/net/wireless/mediatek/mt76/mt7603/mac.c return (val & BIT(8)) && (val & 0xf) != 0xf; BIT 10 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD0_NORMAL_IP_SUM BIT(23) BIT 11 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24) BIT 12 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD0_NORMAL_GROUP_1 BIT(25) BIT 13 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD0_NORMAL_GROUP_2 BIT(26) BIT 14 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD0_NORMAL_GROUP_3 BIT(27) BIT 15 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD0_NORMAL_GROUP_4 BIT(28) BIT 29 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_HDR_TRANS BIT(23) BIT 30 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22) BIT 34 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_BEACON_UC BIT(5) BIT 35 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_BEACON_MC BIT(4) BIT 36 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_BCAST BIT(3) BIT 37 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_MCAST BIT(2) BIT 38 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_U2M BIT(1) BIT 39 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_HTC_VLD BIT(0) BIT 41 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_NON_AMPDU BIT(31) BIT 42 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_NON_AMPDU_SUB BIT(30) BIT 43 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_NDATA BIT(29) BIT 44 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_NULL_FRAME BIT(28) BIT 45 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_FRAG BIT(27) BIT 46 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_UDF_VALID BIT(26) BIT 47 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_LLC_MIS BIT(25) BIT 48 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24) BIT 49 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23) BIT 50 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_LEN_MISMATCH BIT(22) BIT 51 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21) BIT 52 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_ICV_ERR BIT(20) BIT 53 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_CLM BIT(19) BIT 54 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_CM BIT(18) BIT 55 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_FCS_ERR BIT(17) BIT 56 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_SW_BIT BIT(16) BIT 62 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD3_NORMAL_PF_MODE BIT(29) BIT 65 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD3_NORMAL_MAGIC_PKT BIT(13) BIT 67 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD3_NORMAL_CLS BIT(10) BIT 68 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD3_NORMAL_PATTERN_DROP BIT(9) BIT 69 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(8) BIT 74 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_HT_NO_SOUND BIT(21) BIT 75 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_HT_SMOOTH BIT(20) BIT 76 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_HT_SHORT_GI BIT(19) BIT 77 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_HT_AGGR BIT(18) BIT 78 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_VHTA1_B22 BIT(17) BIT 82 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_HT_AD_CODE BIT(9) BIT 90 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV3_F_AGC1_EQ_CAL BIT(28) BIT 93 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV3_F_AGC0_EQ_CAL BIT(16) BIT 95 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV3_SEL_ANT BIT(7) BIT 96 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV3_ACI_DET_X BIT(6) BIT 97 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV3_OFDM_FREQ_TRANS_DETECT BIT(5) BIT 101 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV4_F_AGC2_EQ_CAL BIT(28) BIT 116 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV6_RX_VALID BIT(24) BIT 130 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD0_P_IDX BIT(31) BIT 132 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD0_UTXB BIT(26) BIT 133 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD0_UNXV BIT(25) BIT 134 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD0_UDP_TCP_SUM BIT(24) BIT 135 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD0_IP_SUM BIT(23) BIT 140 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD1_PROTECTED BIT(23) BIT 142 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD1_NO_ACK BIT(19) BIT 144 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD1_LONG_FORMAT BIT(15) BIT 149 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_FIX_RATE BIT(31) BIT 150 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_TIMING_MEASURE BIT(30) BIT 151 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_BA_DISABLE BIT(29) BIT 155 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_HTC_VLD BIT(13) BIT 156 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_DURATION BIT(12) BIT 157 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_BIP BIT(11) BIT 158 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_MULTICAST BIT(10) BIT 159 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_RTS BIT(9) BIT 160 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_SOUNDING BIT(8) BIT 161 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_NDPA BIT(7) BIT 162 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_NDP BIT(6) BIT 166 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD3_SN_VALID BIT(31) BIT 167 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD3_PN_VALID BIT(30) BIT 175 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD5_SW_POWER_MGMT BIT(13) BIT 176 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD5_BA_SEQ_CTRL BIT(12) BIT 177 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD5_DA_SELECT BIT(11) BIT 178 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD5_TX_STATUS_HOST BIT(10) BIT 179 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD5_TX_STATUS_MCU BIT(9) BIT 180 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD5_TX_STATUS_FMT BIT(8) BIT 183 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_SGI BIT(31) BIT 184 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_LDPC BIT(30) BIT 186 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_I_TXBF BIT(17) BIT 187 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_E_TXBF BIT(16) BIT 188 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_DYN_BW BIT(15) BIT 190 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_SPE_EN BIT(11) BIT 191 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_FIXED_BW BIT(10) BIT 194 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_FIXED_RATE BIT(0) BIT 196 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TX_RATE_STBC BIT(11) BIT 203 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_BA_ERROR BIT(22) BIT 204 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_PS_FLAG BIT(21) BIT 205 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_TXOP_TIMEOUT BIT(20) BIT 206 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_BIP_ERROR BIT(19) BIT 208 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_QUEUE_TIMEOUT BIT(18) BIT 209 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_RTS_TIMEOUT BIT(17) BIT 210 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_ACK_TIMEOUT BIT(16) BIT 213 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_TX_STATUS_HOST BIT(15) BIT 214 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_TX_STATUS_MCU BIT(14) BIT 215 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_TXS_FORMAT BIT(13) BIT 216 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_FIXED_RATE BIT(12) BIT 235 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS4_AMPDU BIT(23) BIT 236 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS4_ACKED_MPDU BIT(22) BIT 67 drivers/net/wireless/mediatek/mt76/mt7603/main.c dev->vif_mask |= BIT(mvif->idx); BIT 102 drivers/net/wireless/mediatek/mt76/mt7603/main.c dev->vif_mask &= ~BIT(mvif->idx); BIT 427 drivers/net/wireless/mediatek/mt76/mt7603/main.c if (!(tids & BIT(skb->priority))) BIT 115 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c .mode = cpu_to_le32(BIT(31)), BIT 212 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c if (val & BIT(1)) { BIT 217 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c if (!mt76_poll_msec(dev, MT_TOP_MISC2, BIT(0) | BIT(1), BIT(0), 500)) { BIT 242 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c if (!mt76_poll_msec(dev, MT_TOP_MISC2, BIT(1), BIT(1), 500)) { BIT 251 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c mt76_set(dev, MT_SCH_4, BIT(8)); BIT 252 drivers/net/wireless/mediatek/mt76/mt7603/mcu.c mt76_clear(dev, MT_SCH_4, BIT(8)); BIT 25 drivers/net/wireless/mediatek/mt76/mt7603/pci.c ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); BIT 28 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_INT_RX_DONE(_n) BIT(_n) BIT 31 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_INT_TX_DONE(_n) BIT((_n) + 4) BIT 33 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_INT_RX_COHERENT BIT(20) BIT 34 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_INT_TX_COHERENT BIT(21) BIT 35 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_INT_MAC_IRQ3 BIT(27) BIT 37 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_INT_MCU_CMD BIT(30) BIT 40 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) BIT 41 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) BIT 42 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) BIT 43 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) BIT 45 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) BIT 46 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) BIT 48 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_SW_RESET BIT(24) BIT 49 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_FORCE_TX_EOF BIT(25) BIT 50 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30) BIT 51 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) BIT 57 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_DEBUG_SEL BIT(27) BIT 75 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_SCH_4_BYPASS BIT(5) BIT 76 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_SCH_4_RESET BIT(8) BIT 99 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MCU_DEBUG_RESET_PSE BIT(0) BIT 100 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MCU_DEBUG_RESET_PSE_S BIT(1) BIT 127 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_RTA_REDIRECT_EN BIT(7) BIT 129 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_RTA_WRITE BIT(16) BIT 130 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_RTA_BUSY BIT(31) BIT 153 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_RXTD_13_ACI_TH_EN BIT(0) BIT 163 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PHYCTRL_2_STATUS_RESET BIT(6) BIT 164 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PHYCTRL_2_STATUS_EN BIT(7) BIT 178 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_ARCR_INIT_RATE1 BIT(0) BIT 179 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_ARCR_FB_SGI_DISABLE BIT(1) BIT 180 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_ARCR_RATE8_DOWN_WRAP BIT(2) BIT 183 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19) BIT 203 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_PCR_MM BIT(16) BIT 204 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_PCR_GF BIT(17) BIT 205 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_PCR_BW40 BIT(18) BIT 206 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_PCR_RIFS BIT(19) BIT 207 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_PCR_BW80 BIT(20) BIT 208 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_PCR_BW160 BIT(21) BIT 209 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_PCR_ERP BIT(22) BIT 216 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_CONTROL_NO_BA_RULE BIT(0) BIT 217 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_CONTROL_NO_BA_AR_RULE BIT(1) BIT 218 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_CONTROL_CFEND_SPE_EN BIT(3) BIT 220 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_CONTROL_BAR_SPE_EN BIT(19) BIT 237 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_DCR0_DAMSDU BIT(16) BIT 238 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_DCR0_RX_VEC_DROP BIT(17) BIT 248 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_FQCR0_MODE BIT(29) BIT 249 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_FQCR0_STATUS BIT(30) BIT 250 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_FQCR0_BUSY BIT(31) BIT 258 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_TCFR_TXS_QUEUE BIT(14) BIT 281 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_RQCR_RX_START BIT(0) BIT 282 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_RQCR_RXV_START BIT(4) BIT 283 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_RQCR_RXV_R_EN BIT(7) BIT 284 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_RQCR_RXV_T_EN BIT(8) BIT 289 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_ARB_SCR_TX_DISABLE BIT(8) BIT 290 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_ARB_SCR_RX_DISABLE BIT(9) BIT 291 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_ARB_SCR_BCNQ_EMPTY_SKIP BIT(28) BIT 292 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_ARB_SCR_TTTT_BTIM_PRIO BIT(29) BIT 293 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_ARB_SCR_TBTT_BCN_PRIO BIT(30) BIT 294 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_ARB_SCR_TBTT_BCAST_PRIO BIT(31) BIT 310 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_BCN_START_BSSn(n) BIT(0 + (n)) BIT 311 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_BCN_START_T_PRE_TTTT BIT(10) BIT 312 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_BCN_START_T_TTTT BIT(11) BIT 313 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_BCN_START_T_PRE_TBTT BIT(12) BIT 314 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_BCN_START_T_TBTT BIT(13) BIT 315 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_BCN_START_T_SLOT_IDLE BIT(14) BIT 316 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_BCN_START_T_TX_START BIT(15) BIT 317 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_BCN_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0) BIT 320 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_BCN_FLUSH_BSSn(n) BIT(0 + (n)) BIT 321 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_BCN_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0) BIT 324 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_CAB_START_BSSn(n) BIT(0 + (n)) BIT 325 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_CAB_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0) BIT 328 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_CAB_FLUSH_BSSn(n) BIT(0 + (n)) BIT 329 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_CAB_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0) BIT 341 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TX_ABORT_EN BIT(0) BIT 351 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_RTS_SIGTA BIT(14) BIT 352 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_LDPC_OFS BIT(15) BIT 355 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_SCH_DET_PER_IOD BIT(20) BIT 356 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_DCH_DET_DISABLE BIT(21) BIT 357 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_TX_RIFS BIT(22) BIT 358 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_RX_RIFS_MODE BIT(23) BIT 359 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_TXOP_TBTT_CTL BIT(24) BIT 360 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_TBTT_TX_STOP_CTL BIT(25) BIT 361 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_TXOP_BURST_STOP BIT(26) BIT 362 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_RDG_RA_MODE BIT(27) BIT 363 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_RDG_RESP BIT(29) BIT 364 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_RDG_NO_PENDING BIT(30) BIT 365 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_SMOOTHING BIT(31) BIT 392 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_PCR_RATE_FIXED BIT(15) BIT 394 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_PCR_ANT_ID_SEL BIT(22) BIT 395 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_PCR_SPE_EN BIT(23) BIT 403 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) BIT 404 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) BIT 405 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_VERSION BIT(3) BIT 406 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) BIT 407 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_MCAST BIT(5) BIT 408 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_BCAST BIT(6) BIT 409 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) BIT 410 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_A3_MAC BIT(8) BIT 411 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) BIT 412 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) BIT 413 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) BIT 414 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) BIT 415 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) BIT 416 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_CTS BIT(14) BIT 417 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_RTS BIT(15) BIT 418 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) BIT 419 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) BIT 420 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) BIT 421 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) BIT 422 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_NDPA BIT(20) BIT 423 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) BIT 427 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_BSSID1_VALID BIT(16) BIT 432 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MAC_ADDR1_VALID BIT(16) BIT 438 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_BA_CONTROL_1_IGNORE_TID BIT(20) BIT 439 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_BA_CONTROL_1_IGNORE_ALL BIT(21) BIT 440 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_BA_CONTROL_1_RESET BIT(22) BIT 443 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RMACDR_TSF_PROBERSP_DIS BIT(0) BIT 444 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RMACDR_TSF_TIM BIT(4) BIT 446 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RMACDR_CHECK_HTC_BY_RATE BIT(26) BIT 447 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RMACDR_MAXLEN_20BIT BIT(30) BIT 452 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RMAC_RMCR_SMPS_RTS BIT(25) BIT 470 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_UPDATE_WTBL2 BIT(11) BIT 471 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) BIT 472 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_UPDATE_RATE_UPDATE BIT(13) BIT 473 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14) BIT 474 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_UPDATE_RX_COUNT_CLEAR BIT(15) BIT 475 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_UPDATE_BUSY BIT(16) BIT 478 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RMVTCR_RX_MV_MODE BIT(23) BIT 501 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TBTT_CAL_ENABLE BIT(31) BIT 506 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LPON_SBTOR_SUB_BSS_EN BIT(29) BIT 515 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_HW_INT3_TBTT0 BIT(15) BIT 516 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_HW_INT3_PRE_TBTT0 BIT(31) BIT 548 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MIB_CTL_READ_CLR_DIS BIT(31) BIT 574 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n))) BIT 575 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n))) BIT 576 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n))) BIT 577 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LED_CTRL_TX_MANUAL_BLINK(_n) BIT(3 + (8 * (_n))) BIT 578 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LED_CTRL_TX_OVER_BLINK(_n) BIT(5 + (8 * (_n))) BIT 579 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n))) BIT 603 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_CLIENT_RESET_TX_R_E_1 BIT(16) BIT 604 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_CLIENT_RESET_TX_R_E_2 BIT(17) BIT 605 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_CLIENT_RESET_TX_R_E_1_S BIT(20) BIT 606 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_CLIENT_RESET_TX_R_E_2_S BIT(21) BIT 611 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_EFUSE_BASE_CTRL_EMPTY BIT(30) BIT 619 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_EFUSE_CTRL_VALID BIT(29) BIT 620 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_EFUSE_CTRL_KICK BIT(30) BIT 621 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_EFUSE_CTRL_SEL BIT(31) BIT 643 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_RX_CHECK_A1 BIT(22) BIT 645 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_RX_CHECK_KEY_IDX BIT(25) BIT 646 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_RX_KEY_VALID BIT(26) BIT 647 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_RX_IK_VALID BIT(27) BIT 648 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_RX_VALID BIT(28) BIT 649 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_RX_CHECK_A2 BIT(29) BIT 650 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_RX_DATA_VALID BIT(30) BIT 651 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_WRITE_BURST BIT(31) BIT 657 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_EVEN_PN BIT(7) BIT 658 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_TO_DS BIT(8) BIT 659 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_FROM_DS BIT(9) BIT 660 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_HEADER_TRANS BIT(10) BIT 662 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_PWR_MGMT BIT(14) BIT 663 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_RDG BIT(15) BIT 664 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_RTS BIT(16) BIT 665 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_CFACK BIT(17) BIT 666 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_RDG_BA BIT(18) BIT 667 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_SMPS BIT(19) BIT 668 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_TXS_BAF_REPORT BIT(20) BIT 669 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_DYN_BW BIT(21) BIT 670 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_LDPC BIT(22) BIT 671 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_ITXBF BIT(23) BIT 672 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_ETXBF BIT(24) BIT 673 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_TXOP_PS BIT(25) BIT 674 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_MESH BIT(26) BIT 675 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_QOS BIT(27) BIT 676 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_HT BIT(28) BIT 677 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_VHT BIT(29) BIT 678 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_ADMISSION_CONTROL BIT(30) BIT 679 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_GROUP_ID BIT(31) BIT 684 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W3_CHECK_PER BIT(27) BIT 685 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W3_KEEP_I_PSM BIT(28) BIT 686 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W3_I_PSM BIT(29) BIT 687 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W3_POWER_SAVE BIT(30) BIT 688 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W3_SKIP_TX BIT(31) BIT 728 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_SPATIAL_EXT BIT(5) BIT 733 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_SHORT_GI_20 BIT(16) BIT 734 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_SHORT_GI_40 BIT(17) BIT 735 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_SHORT_GI_80 BIT(18) BIT 736 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_SHORT_GI_160 BIT(19) BIT 762 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W14_CC_NOISE_SEL BIT(15) BIT 770 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_OR_PSM_WRITE BIT(31) BIT 147 drivers/net/wireless/mediatek/mt76/mt7615/dma.c mt76_set(dev, 0x7158, BIT(16)); BIT 148 drivers/net/wireless/mediatek/mt76/mt7615/dma.c mt76_clear(dev, 0x7000, BIT(23)); BIT 27 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.h #define MT_EE_NIC_CONF_TSSI_2G BIT(5) BIT 28 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.h #define MT_EE_NIC_CONF_TSSI_5G BIT(6) BIT 162 drivers/net/wireless/mediatek/mt76/mt7615/init.c .types = BIT(NL80211_IFTYPE_AP) | BIT 164 drivers/net/wireless/mediatek/mt76/mt7615/init.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 166 drivers/net/wireless/mediatek/mt76/mt7615/init.c BIT(NL80211_IFTYPE_STATION) BIT 285 drivers/net/wireless/mediatek/mt76/mt7615/init.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 287 drivers/net/wireless/mediatek/mt76/mt7615/init.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 289 drivers/net/wireless/mediatek/mt76/mt7615/init.c BIT(NL80211_IFTYPE_AP); BIT 186 drivers/net/wireless/mediatek/mt76/mt7615/mac.c if (!(status->chains & BIT(i))) BIT 485 drivers/net/wireless/mediatek/mt76/mt7615/mac.c rateset = !(sta->rate_set_tsf & BIT(0)); BIT 591 drivers/net/wireless/mediatek/mt76/mt7615/mac.c sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset; BIT 653 drivers/net/wireless/mediatek/mt76/mt7615/mac.c if (wcid->cipher & ~BIT(cipher)) { BIT 686 drivers/net/wireless/mediatek/mt76/mt7615/mac.c if (!(wcid->cipher & ~BIT(cipher))) BIT 718 drivers/net/wireless/mediatek/mt76/mt7615/mac.c wcid->cipher & BIT(MT_CIPHER_BIP_CMAC_128)) BIT 722 drivers/net/wireless/mediatek/mt76/mt7615/mac.c else if (!(wcid->cipher & ~BIT(cipher))) BIT 752 drivers/net/wireless/mediatek/mt76/mt7615/mac.c wcid->cipher |= BIT(cipher); BIT 754 drivers/net/wireless/mediatek/mt76/mt7615/mac.c wcid->cipher &= ~BIT(cipher); BIT 889 drivers/net/wireless/mediatek/mt76/mt7615/mac.c rs_idx ^= rate_set_tsf & BIT(0); BIT 1125 drivers/net/wireless/mediatek/mt76/mt7615/mac.c mt76_set(dev, MT_WF_PHY_R0_B0_PHYMUX_5, BIT(22) | BIT(20)); BIT 14 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD0_NORMAL_IP_SUM BIT(23) BIT 15 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24) BIT 16 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD0_NORMAL_GROUP_1 BIT(25) BIT 17 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD0_NORMAL_GROUP_2 BIT(26) BIT 18 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD0_NORMAL_GROUP_3 BIT(27) BIT 19 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD0_NORMAL_GROUP_4 BIT(28) BIT 34 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_HDR_TRANS BIT(23) BIT 35 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22) BIT 39 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_BEACON_UC BIT(5) BIT 40 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_BEACON_MC BIT(4) BIT 41 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_BF_REPORT BIT(3) BIT 44 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_MCAST BIT(2) BIT 45 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_U2M BIT(1) BIT 46 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_HTC_VLD BIT(0) BIT 48 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_NON_AMPDU BIT(31) BIT 49 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_NON_AMPDU_SUB BIT(30) BIT 50 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_NDATA BIT(29) BIT 51 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_NULL_FRAME BIT(28) BIT 52 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_FRAG BIT(27) BIT 53 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_INT_FRAME BIT(26) BIT 54 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25) BIT 55 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24) BIT 56 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23) BIT 57 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_LEN_MISMATCH BIT(22) BIT 58 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21) BIT 59 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_ICV_ERR BIT(20) BIT 60 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_CLM BIT(19) BIT 61 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_CM BIT(18) BIT 62 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_FCS_ERR BIT(17) BIT 63 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_SW_BIT BIT(16) BIT 69 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD3_NORMAL_PF_MODE BIT(29) BIT 72 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD3_NORMAL_MAGIC_PKT BIT(13) BIT 74 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD3_NORMAL_CLS BIT(10) BIT 75 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD3_NORMAL_PATTERN_DROP BIT(9) BIT 76 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(8) BIT 79 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_ACID_DET_H BIT(31) BIT 80 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_ACID_DET_L BIT(30) BIT 83 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_HT_NO_SOUND BIT(21) BIT 84 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_HT_SMOOTH BIT(20) BIT 85 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_HT_SHORT_GI BIT(19) BIT 86 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_HT_AGGR BIT(18) BIT 87 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_VHTA1_B22 BIT(17) BIT 91 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_HT_AD_CODE BIT(9) BIT 95 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV2_SEL_ANT BIT(31) BIT 96 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV2_VALID_BIT BIT(30) BIT 151 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_CT_INFO_APPLY_TXD BIT(0) BIT 152 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1) BIT 153 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_CT_INFO_MGMT_FRAME BIT(2) BIT 154 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3) BIT 155 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_CT_INFO_HSR2_TX BIT(4) BIT 159 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD0_P_IDX BIT(31) BIT 161 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD0_UDP_TCP_SUM BIT(24) BIT 162 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD0_IP_SUM BIT(23) BIT 169 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_AMSDU BIT(20) BIT 170 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_UNXV BIT(19) BIT 172 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_TXD_LEN BIT(16) BIT 173 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_LONG_FORMAT BIT(15) BIT 178 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_FIX_RATE BIT(31) BIT 179 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_TIMING_MEASURE BIT(30) BIT 180 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_BA_DISABLE BIT(29) BIT 184 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_HTC_VLD BIT(13) BIT 185 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_DURATION BIT(12) BIT 186 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_BIP BIT(11) BIT 187 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_MULTICAST BIT(10) BIT 188 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_RTS BIT(9) BIT 189 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_SOUNDING BIT(8) BIT 190 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_NDPA BIT(7) BIT 191 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_NDP BIT(6) BIT 195 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD3_SN_VALID BIT(31) BIT 196 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD3_PN_VALID BIT(30) BIT 200 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD3_PROTECT_FRAME BIT(1) BIT 201 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD3_NO_ACK BIT(0) BIT 206 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD5_SW_POWER_MGMT BIT(13) BIT 207 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD5_DA_SELECT BIT(11) BIT 208 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD5_TX_STATUS_HOST BIT(10) BIT 209 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD5_TX_STATUS_MCU BIT(9) BIT 210 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD5_TX_STATUS_FMT BIT(8) BIT 213 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD6_FIXED_RATE BIT(31) BIT 214 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD6_SGI BIT(30) BIT 215 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD6_LDPC BIT(29) BIT 216 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD6_TX_BF BIT(28) BIT 219 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD6_DYN_BW BIT(3) BIT 220 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD6_FIXED_BW BIT(2) BIT 226 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TX_RATE_STBC BIT(11) BIT 255 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_BA_ERROR BIT(22) BIT 256 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_PS_FLAG BIT(21) BIT 257 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_TXOP_TIMEOUT BIT(20) BIT 258 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_BIP_ERROR BIT(19) BIT 260 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_QUEUE_TIMEOUT BIT(18) BIT 261 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_RTS_TIMEOUT BIT(17) BIT 262 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_ACK_TIMEOUT BIT(16) BIT 265 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_TX_STATUS_HOST BIT(15) BIT 266 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_TX_STATUS_MCU BIT(14) BIT 267 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_TXS_FORMAT BIT(13) BIT 268 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_FIXED_RATE BIT(12) BIT 274 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS1_I_TXBF BIT(13) BIT 275 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS1_E_TXBF BIT(12) BIT 277 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS1_AMPDU BIT(8) BIT 278 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS1_ACKED_MPDU BIT(7) BIT 43 drivers/net/wireless/mediatek/mt76/mt7615/main.c if (~mask & BIT(HW_BSSID_0)) BIT 47 drivers/net/wireless/mediatek/mt76/mt7615/main.c if (~mask & BIT(i)) BIT 54 drivers/net/wireless/mediatek/mt76/mt7615/main.c if (~mask & BIT(i)) BIT 97 drivers/net/wireless/mediatek/mt76/mt7615/main.c dev->vif_mask |= BIT(mvif->idx); BIT 98 drivers/net/wireless/mediatek/mt76/mt7615/main.c dev->omac_mask |= BIT(mvif->omac_idx); BIT 129 drivers/net/wireless/mediatek/mt76/mt7615/main.c dev->vif_mask &= ~BIT(mvif->idx); BIT 130 drivers/net/wireless/mediatek/mt76/mt7615/main.c dev->omac_mask &= ~BIT(mvif->omac_idx); BIT 39 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define FW_FEATURE_SET_ENCRYPT BIT(0) BIT 42 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define DL_MODE_ENCRYPT BIT(0) BIT 44 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define DL_MODE_RESET_SEC_IV BIT(3) BIT 45 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define DL_MODE_WORKING_PDA_CR4 BIT(4) BIT 46 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define DL_MODE_NEED_RSP BIT(31) BIT 48 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define FW_START_OVERRIDE BIT(0) BIT 49 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define FW_START_WORKING_PDA_CR4 BIT(2) BIT 641 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define WMM_AIFS_SET BIT(0) BIT 642 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define WMM_CW_MIN_SET BIT(1) BIT 643 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define WMM_CW_MAX_SET BIT(2) BIT 644 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define WMM_TXOP_SET BIT(3) BIT 809 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c int ret, i, features = BIT(BSS_INFO_BASIC), ntlv = 1; BIT 816 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c features |= BIT(BSS_INFO_OMAC); BIT 819 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c features |= BIT(BSS_INFO_EXT_BSS); BIT 867 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c int tag = ffs(features & BIT(i)) - 1; BIT 131 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define STA_TYPE_STA BIT(0) BIT 132 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define STA_TYPE_AP BIT(1) BIT 133 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define STA_TYPE_ADHOC BIT(2) BIT 134 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define STA_TYPE_WDS BIT(4) BIT 135 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define STA_TYPE_BC BIT(5) BIT 137 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define NETWORK_INFRA BIT(16) BIT 138 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define NETWORK_P2P BIT(17) BIT 139 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define NETWORK_IBSS BIT(18) BIT 140 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define NETWORK_WDS BIT(21) BIT 419 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define EXTRA_INFO_VER BIT(0) BIT 420 drivers/net/wireless/mediatek/mt76/mt7615/mcu.h #define EXTRA_INFO_NEW BIT(1) BIT 94 drivers/net/wireless/mediatek/mt76/mt7615/pci.c ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); BIT 29 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_CFG_LPCR_HOST_FW_OWN BIT(0) BIT 30 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_CFG_LPCR_HOST_DRV_OWN BIT(1) BIT 36 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_INT_RX_DONE(_n) BIT(_n) BIT 39 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_INT_TX_DONE(_n) BIT((_n) + 4) BIT 42 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) BIT 43 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) BIT 44 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) BIT 45 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) BIT 47 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) BIT 48 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) BIT 49 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0 BIT(9) BIT 51 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) BIT 53 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_SW_RESET BIT(24) BIT 54 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26) BIT 55 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28) BIT 72 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN BIT(9) BIT 87 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHY_B0_PD_BLK BIT(19) BIT 92 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHY_B1_PD_BLK BIT(25) BIT 106 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_CFG_CCR_MAC_D1_1X_GC_EN BIT(24) BIT 107 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_CFG_CCR_MAC_D0_1X_GC_EN BIT(25) BIT 108 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_CFG_CCR_MAC_D1_2X_GC_EN BIT(30) BIT 109 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_CFG_CCR_MAC_D0_2X_GC_EN BIT(31) BIT 115 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ARCR_INIT_RATE1 BIT(0) BIT 118 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19) BIT 130 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ACR_NO_BA_RULE BIT(0) BIT 131 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ACR_NO_BA_AR_RULE BIT(1) BIT 132 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ACR_PKT_TIME_EN BIT(2) BIT 137 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_SCR_NLNAV_MID_PTEC_DIS BIT(3) BIT 150 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) BIT 151 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) BIT 157 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) BIT 158 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) BIT 159 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_VERSION BIT(3) BIT 160 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) BIT 161 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_MCAST BIT(5) BIT 162 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_BCAST BIT(6) BIT 163 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) BIT 164 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_A3_MAC BIT(8) BIT 165 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) BIT 166 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) BIT 167 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) BIT 168 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) BIT 169 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) BIT 170 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_CTS BIT(14) BIT 171 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_RTS BIT(15) BIT 172 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) BIT 173 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) BIT 174 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) BIT 175 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) BIT 176 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_NDPA BIT(20) BIT 177 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) BIT 184 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_DMA_DCR0_RX_VEC_DROP BIT(17) BIT 193 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W0_RX_KEY_VALID BIT(26) BIT 194 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W0_RX_IK_VALID BIT(27) BIT 200 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_UPDATE_RXINFO_UPDATE BIT(11) BIT 201 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_UPDATE_RATE_UPDATE BIT(13) BIT 202 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14) BIT 203 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_UPDATE_BUSY BIT(31) BIT 230 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W5_SHORT_GI_20 BIT(8) BIT 231 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W5_SHORT_GI_40 BIT(9) BIT 232 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W5_SHORT_GI_80 BIT(10) BIT 233 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W5_SHORT_GI_160 BIT(11) BIT 263 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_EFUSE_BASE_CTRL_EMPTY BIT(30) BIT 271 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_EFUSE_CTRL_VALID BIT(29) BIT 272 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_EFUSE_CTRL_KICK BIT(30) BIT 273 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_EFUSE_CTRL_SEL BIT(31) BIT 30 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h if (ret & BIT(5)) BIT 31 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h ret -= BIT(6); BIT 125 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c mt76_clear(dev, MT_COEXCFG0, BIT(0)); BIT 132 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c mt76_clear(dev, 0x110, BIT(9)); BIT 133 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c mt76_set(dev, MT_MAX_LEN_CFG, BIT(13)); BIT 176 drivers/net/wireless/mediatek/mt76/mt76x0/pci.c ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); BIT 370 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_set(dev, MT_RF_MISC, BIT(2)); BIT 372 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_set(dev, MT_RF_MISC, BIT(3)); BIT 437 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c ee_ant &= ~(BIT(14) | BIT(12)); BIT 438 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c wlan &= ~(BIT(6) | BIT(5)); BIT 446 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c ee_ant |= BIT(12); BIT 448 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c coex3 |= BIT(4); BIT 449 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c coex3 |= BIT(3); BIT 451 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c wlan |= BIT(6); BIT 455 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c coex3 |= BIT(3) | BIT(4); BIT 457 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c wlan |= BIT(6); BIT 458 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c coex3 |= BIT(1); BIT 463 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c ee_ant |= BIT(14) | BIT(11); BIT 468 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_clear(dev, MT_COEXCFG0, BIT(2)); BIT 516 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); BIT 518 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); BIT 524 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_wr(dev, MT_BBP(TXBE, 6), BIT(31)); BIT 526 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200); BIT 534 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); BIT 536 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); BIT 552 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) { BIT 553 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_clear(dev, MT_BBP(CORE, 34), BIT(4)); BIT 671 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c while (mantissa < BIT(15)) { BIT 722 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c (tssi_offset & BIT(7))) BIT 723 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c tssi_offset -= BIT(8); BIT 728 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (tssi_offset & BIT(7)) BIT 729 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c tssi_offset -= BIT(8); BIT 751 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c offset = (data & BIT(5)) ? 18841 : 12288; BIT 753 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c } else if (data & BIT(5)) { BIT 814 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (ret & BIT(5)) BIT 815 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c ret -= BIT(6); BIT 920 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), BIT 925 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), BIT 930 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)), BIT 935 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)), BIT 1005 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7)); BIT 1031 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) { BIT 1032 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_clear(dev, MT_BBP(CORE, 34), BIT(4)); BIT 1199 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7)); BIT 1200 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_clear(dev, MT_RF(0, 73), BIT(7)); BIT 1201 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7)); BIT 25 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_VCO_BP_CLOSE_LOOP BIT(3) BIT 34 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_SDM_RESET_MASK BIT(7) BIT 36 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_SDM_BP_MASK BIT(1) BIT 53 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c mt76_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx)); BIT 58 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c dev->beacon_data_mask |= BIT(bcn_idx); BIT 60 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c dev->beacon_data_mask &= ~BIT(bcn_idx); BIT 95 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c if (!(dev->beacon_data_mask & BIT(i))) BIT 119 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c dev->mt76.beacon_mask |= BIT(mvif->idx); BIT 121 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c dev->mt76.beacon_mask &= ~BIT(mvif->idx); BIT 181 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c if (!(dev->mt76.beacon_mask & BIT(mvif->idx))) BIT 201 drivers/net/wireless/mediatek/mt76/mt76x02_beacon.c if (!(dev->mt76.beacon_mask & BIT(mvif->idx))) BIT 59 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h #define MT_DFS_EVENT_ENGINE(x) (((x) & BIT(31)) ? 2 : 0) BIT 13 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_TXD_INFO_NEXT_VLD BIT(16) BIT 14 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_TXD_INFO_TX_BURST BIT(17) BIT 15 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_TXD_INFO_80211 BIT(19) BIT 16 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_TXD_INFO_TSO BIT(20) BIT 17 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_TXD_INFO_CSO BIT(21) BIT 18 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_TXD_INFO_WIV BIT(24) BIT 24 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_RX_FCE_INFO_SELF_GEN BIT(15) BIT 27 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_RX_FCE_INFO_PCIE_INTR BIT(24) BIT 38 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_MCU_MSG_TYPE_CMD BIT(30) BIT 100 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_ANTENNA_DUAL BIT(15) BIT 105 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_0_PA_INT_2G BIT(8) BIT 106 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_0_PA_INT_5G BIT(9) BIT 107 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_0_PA_IO_CURRENT BIT(10) BIT 110 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0) BIT 111 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1) BIT 112 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2) BIT 113 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3) BIT 114 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13) BIT 116 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_2_ANT_OPT BIT(3) BIT 117 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_2_ANT_DIV BIT(4) BIT 141 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h bool sign = val & BIT(size - 1); BIT 143 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h val &= BIT(size - 1) - 1; BIT 151 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h bool enable = val & BIT(size); BIT 322 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2)); BIT 776 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c status->chains = BIT(0); BIT 780 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c status->chains |= BIT(1); BIT 969 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) BIT 40 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_BA BIT(0) BIT 41 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_DATA BIT(1) BIT 42 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_NULL BIT(2) BIT 43 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_FRAG BIT(3) BIT 44 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_UNICAST BIT(4) BIT 45 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_MULTICAST BIT(5) BIT 46 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_BROADCAST BIT(6) BIT 47 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_MYBSS BIT(7) BIT 48 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_CRCERR BIT(8) BIT 49 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_ICVERR BIT(9) BIT 50 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_MICERR BIT(10) BIT 51 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_AMSDU BIT(11) BIT 52 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_HTC BIT(12) BIT 53 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_RSSI BIT(13) BIT 54 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_L2PAD BIT(14) BIT 55 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_AMPDU BIT(15) BIT 56 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_DECRYPT BIT(16) BIT 57 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_BSSIDX3 BIT(17) BIT 58 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_WAPI_KEY BIT(18) BIT 60 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_SW_FTYPE0 BIT(22) BIT 61 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_SW_FTYPE1 BIT(23) BIT 62 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_PROBE_RESP BIT(24) BIT 63 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_BEACON BIT(25) BIT 64 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_DISASSOC BIT(26) BIT 65 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_DEAUTH BIT(27) BIT 66 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_ACTION BIT(28) BIT 67 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_TCP_SUM_ERR BIT(30) BIT 68 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_IP_SUM_ERR BIT(31) BIT 75 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_CTL_EOF BIT(31) BIT 81 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_RATE_LDPC BIT(6) BIT 83 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_RATE_SGI BIT(9) BIT 84 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_RATE_STBC BIT(10) BIT 85 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_RATE_LDPC_EXSYM BIT(11) BIT 112 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_FRAG BIT(0) BIT 113 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_MMPS BIT(1) BIT 114 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_CFACK BIT(2) BIT 115 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_TS BIT(3) BIT 116 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_AMPDU BIT(4) BIT 119 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_NDPS BIT(10) BIT 120 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_RTSBWSIG BIT(11) BIT 122 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_SOUND BIT(14) BIT 123 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15) BIT 125 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_ACK_CTL_REQ BIT(0) BIT 126 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_ACK_CTL_NSEQ BIT(1) BIT 121 drivers/net/wireless/mediatek/mt76/mt76x02_mcu.c mt76_rmw(dev, MT_MCU_COM_REG0, BIT(31), 0); BIT 130 drivers/net/wireless/mediatek/mt76/mt76x02_mcu.c BIT(31), BIT(31), 100))) BIT 17 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val &= ~BIT(4); BIT 21 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= BIT(3); BIT 24 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val &= ~BIT(3); BIT 55 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= (v1 & (BIT(6) - 1)) << 0; BIT 56 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= (v2 & (BIT(6) - 1)) << 8; BIT 57 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= (v3 & (BIT(6) - 1)) << 16; BIT 58 drivers/net/wireless/mediatek/mt76/mt76x02_phy.c val |= (v4 & (BIT(6) - 1)) << 24; BIT 15 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CMB_CTRL_XTAL_RDY BIT(22) BIT 16 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CMB_CTRL_PLL_LD BIT(23) BIT 24 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EFUSE_CTRL_KICK BIT(30) BIT 25 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EFUSE_CTRL_SEL BIT(31) BIT 31 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_COEXCFG0_COEX_EN BIT(0) BIT 34 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0) BIT 35 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1) BIT 36 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2) BIT 43 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */ BIT 44 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */ BIT 46 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4) BIT 47 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5) BIT 48 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6) BIT 49 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7) BIT 51 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_THERM_RST BIT(8) /* MT76x2 */ BIT 52 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9) /* MT76x2 */ BIT 80 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_UDMA_TX_WL_DROP BIT(16) BIT 81 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_WAKE_UP_EN BIT(17) BIT 82 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_RX_DROP_OR_PAD BIT(18) BIT 83 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_TX_CLR BIT(19) BIT 84 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_TXOP_HALT BIT(20) BIT 85 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21) BIT 86 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_RX_BULK_EN BIT(22) BIT 87 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_TX_BULK_EN BIT(23) BIT 89 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_RX_BUSY BIT(30) BIT 90 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_TX_BUSY BIT(31) BIT 93 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0) BIT 94 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12) BIT 95 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13) BIT 97 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20) BIT 98 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21) BIT 99 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22) BIT 100 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24) BIT 101 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25) BIT 102 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26) BIT 103 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27) BIT 104 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_STATE_UP BIT(28) BIT 109 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_RX_DONE(_n) BIT(_n) BIT 112 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_TX_DONE(_n) BIT((_n) + 4) BIT 113 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_RX_COHERENT BIT(16) BIT 114 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_TX_COHERENT BIT(17) BIT 115 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_ANY_COHERENT BIT(18) BIT 116 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_MCU_CMD BIT(19) BIT 117 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_TBTT BIT(20) BIT 118 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_PRE_TBTT BIT(21) BIT 119 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_TX_STAT BIT(22) BIT 120 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_AUTO_WAKEUP BIT(23) BIT 121 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_GPTIMER BIT(24) BIT 122 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_RXDELAYINT BIT(26) BIT 123 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_TXDELAYINT BIT(27) BIT 126 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) BIT 127 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) BIT 128 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) BIT 129 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) BIT 131 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) BIT 132 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) BIT 134 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30) BIT 135 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) BIT 176 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_SYS_CTRL_MCU_RESET BIT(0) BIT 177 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_SYS_CTRL_DMA_RESET BIT(1) BIT 178 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_SYS_CTRL_MAC_RESET BIT(2) BIT 179 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_SYS_CTRL_PBF_RESET BIT(3) BIT 180 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_SYS_CTRL_ASY_RESET BIT(4) BIT 183 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_CFG_TX0Q_EN BIT(0) BIT 184 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_CFG_TX1Q_EN BIT(1) BIT 185 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_CFG_TX2Q_EN BIT(2) BIT 186 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_CFG_TX3Q_EN BIT(3) BIT 187 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_CFG_RX0Q_EN BIT(4) BIT 188 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PBF_CFG_RX_DROP_EN BIT(8) BIT 202 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RF_CSR_CFG_WR BIT(30) BIT 203 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RF_CSR_CFG_KICK BIT(31) BIT 214 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RF_CTRL_WRITE BIT(12) BIT 215 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RF_CTRL_BUSY BIT(13) BIT 216 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RF_CTRL_IDX BIT(16) BIT 226 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n))) BIT 227 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n))) BIT 228 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n))) BIT 229 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n))) BIT 253 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_FCE_L2_STUFF_HT_L2_EN BIT(0) BIT 254 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1) BIT 255 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2) BIT 256 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3) BIT 257 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4) BIT 258 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5) BIT 276 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_SYS_CTRL_RESET_CSR BIT(0) BIT 277 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_SYS_CTRL_RESET_BBP BIT(1) BIT 278 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2) BIT 279 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3) BIT 290 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21) BIT 291 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22) BIT 292 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23) BIT 308 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WCID_DROP_MASK(_n) BIT((_n) % 32) BIT 316 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_APC_BSSID0_H_EN BIT(16) BIT 323 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29) BIT 330 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CH_TIME_CFG_TIMER_EN BIT(0) BIT 331 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CH_TIME_CFG_TX_AS_BUSY BIT(1) BIT 332 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CH_TIME_CFG_RX_AS_BUSY BIT(2) BIT 333 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CH_TIME_CFG_NAV_AS_BUSY BIT(3) BIT 334 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CH_TIME_CFG_EIFS_AS_BUSY BIT(4) BIT 335 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CH_TIME_CFG_MDRDY_CNT_EN BIT(5) BIT 336 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CH_CCA_RC_EN BIT(6) BIT 344 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BEACON_TIME_CFG_TIMER_EN BIT(16) BIT 346 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BEACON_TIME_CFG_TBTT_EN BIT(19) BIT 347 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BEACON_TIME_CFG_BEACON_TX BIT(20) BIT 361 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0) BIT 362 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1) BIT 370 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_STATUS_TX BIT(0) BIT 371 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_STATUS_RX BIT(1) BIT 401 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_PIN_RFTR_EN BIT(16) BIT 402 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_PIN_TRSW_EN BIT(18) BIT 405 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_BAND_CFG_UPPER_40M BIT(0) BIT 406 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_BAND_CFG_5G BIT(1) BIT 407 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_BAND_CFG_2G BIT(2) BIT 423 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TXOP_ED_CCA_EN BIT(20) BIT 428 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_RTS_FALLBACK BIT(24) BIT 435 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_CFACK_EN BIT(12) BIT 445 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_CFG_RTS_THRESH BIT(26) BIT 455 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_CTRL_RTS_CTS BIT(16) BIT 456 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_CTRL_CTS2SELF BIT(17) BIT 457 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_NAV_SHORT BIT(18) BIT 458 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_NAV_LONG BIT(19) BIT 459 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_TXOP_ALLOW_CCK BIT(20) BIT 460 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_TXOP_ALLOW_OFDM BIT(21) BIT 461 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_TXOP_ALLOW_MM20 BIT(22) BIT 462 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_TXOP_ALLOW_MM40 BIT(23) BIT 463 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_TXOP_ALLOW_GF20 BIT(24) BIT 464 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_TXOP_ALLOW_GF40 BIT(25) BIT 465 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_RTS_THR_EN BIT(26) BIT 484 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16) BIT 485 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17) BIT 486 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_FBK_LIMIT_RATE_LUT BIT(18) BIT 507 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_ALC_CFG_4_LOWGAIN_CH_EN BIT(31) BIT 520 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_CRC_ERR BIT(0) BIT 521 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_PHY_ERR BIT(1) BIT 522 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_PROMISC BIT(2) BIT 523 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_OTHER_BSS BIT(3) BIT 524 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_VER_ERR BIT(4) BIT 525 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_MCAST BIT(5) BIT 526 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_BCAST BIT(6) BIT 527 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_DUP BIT(7) BIT 528 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_CFACK BIT(8) BIT 529 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_CFEND BIT(9) BIT 530 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_ACK BIT(10) BIT 531 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_CTS BIT(11) BIT 532 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_RTS BIT(12) BIT 533 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_PSPOLL BIT(13) BIT 534 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_BA BIT(14) BIT 535 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_BAR BIT(15) BIT 536 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_FILTR_CFG_CTRL_RSV BIT(16) BIT 539 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_AUTO_RSP_EN BIT(0) BIT 540 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_AUTO_RSP_PREAMB_SHORT BIT(4) BIT 546 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0) BIT 561 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TXOP_HLDR_TX40M_BLK_EN BIT(1) BIT 584 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_STAT_FIFO_VALID BIT(0) BIT 585 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_STAT_FIFO_SUCCESS BIT(5) BIT 586 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_STAT_FIFO_AGGR BIT(6) BIT 587 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_STAT_FIFO_ACKREQ BIT(7) BIT 661 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WCID_ATTR_PAIRWISE BIT(0) BIT 665 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10) BIT 666 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WCID_ATTR_BSS_IDX_EXT BIT(11) BIT 667 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WCID_ATTR_WAPI_MCBC BIT(15) BIT 42 drivers/net/wireless/mediatek/mt76/mt76x02_util.c .types = BIT(NL80211_IFTYPE_ADHOC) BIT 45 drivers/net/wireless/mediatek/mt76/mt76x02_util.c .types = BIT(NL80211_IFTYPE_STATION) | BIT 47 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 49 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_IFTYPE_AP) BIT 56 drivers/net/wireless/mediatek/mt76/mt76x02_util.c .types = BIT(NL80211_IFTYPE_ADHOC) BIT 59 drivers/net/wireless/mediatek/mt76/mt76x02_util.c .types = BIT(NL80211_IFTYPE_STATION) | BIT 61 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 63 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_IFTYPE_AP) BIT 74 drivers/net/wireless/mediatek/mt76/mt76x02_util.c .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT 75 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_CHAN_WIDTH_20) | BIT 76 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_CHAN_WIDTH_40) | BIT 77 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_CHAN_WIDTH_80), BIT 157 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_IFTYPE_STATION) | BIT 158 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_IFTYPE_AP) | BIT 160 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 162 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(NL80211_IFTYPE_ADHOC); BIT 317 drivers/net/wireless/mediatek/mt76/mt76x02_util.c if (vif->addr[0] & BIT(1)) BIT 336 drivers/net/wireless/mediatek/mt76/mt76x02_util.c if (dev->vif_mask & BIT(idx)) BIT 339 drivers/net/wireless/mediatek/mt76/mt76x02_util.c dev->vif_mask |= BIT(idx); BIT 353 drivers/net/wireless/mediatek/mt76/mt76x02_util.c dev->vif_mask &= ~BIT(mvif->idx); BIT 378 drivers/net/wireless/mediatek/mt76/mt76x02_util.c mt76_set(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, BIT(16 + tid)); BIT 383 drivers/net/wireless/mediatek/mt76/mt76x02_util.c BIT(16 + tid)); BIT 687 drivers/net/wireless/mediatek/mt76/mt76x02_util.c addr[0] |= BIT(1); BIT 501 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c dev->mt76.macaddr[0] &= ~BIT(1); BIT 68 drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h if (!(val & BIT(15))) BIT 37 drivers/net/wireless/mediatek/mt76/mt76x2/mac.c mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); BIT 38 drivers/net/wireless/mediatek/mt76/mt76x2/mac.c mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); BIT 40 drivers/net/wireless/mediatek/mt76/mt76x2/mac.c mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); BIT 41 drivers/net/wireless/mediatek/mt76/mt76x2/mac.c mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); BIT 63 drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c val = BIT(31); BIT 85 drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c msg.channel |= cpu_to_le32(BIT(31)); BIT 42 drivers/net/wireless/mediatek/mt76/mt76x2/pci.c ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); BIT 101 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); BIT 168 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_set(dev, 0x10130, BIT(0) | BIT(16)); BIT 177 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_set(dev, 0x10130, BIT(17)); BIT 180 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_clear(dev, 0x10130, BIT(16)); BIT 183 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_set(dev, 0x1014c, BIT(19) | BIT(20)); BIT 192 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_set(dev, 0x10130, BIT(0) << shift); BIT 196 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift); BIT 200 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_clear(dev, 0x10130, BIT(2) << shift); BIT 232 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_clear(dev, 0x11204, BIT(3)); BIT 235 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_set(dev, 0x10080, BIT(0)); BIT 238 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76_clear(dev, 0x10064, BIT(18)); BIT 31 drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c patch_mask = BIT(0); BIT 34 drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c patch_mask = BIT(1); BIT 134 drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c mt76_set(dev, MT_MCU_COM_REG0, BIT(30)); BIT 25 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c flag |= BIT(0); BIT 28 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c flag |= BIT(8); BIT 76 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val &= ~(BIT(4) | BIT(1)); BIT 80 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c mt76_clear(dev, MT_BBP(IBI, 9), BIT(11)); BIT 87 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val &= ~(BIT(3) | BIT(0)); BIT 91 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c mt76_clear(dev, MT_BBP(IBI, 9), BIT(11)); BIT 98 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val &= ~BIT(3); BIT 99 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val |= BIT(0); BIT 104 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c mt76_set(dev, MT_BBP(IBI, 9), BIT(11)); BIT 110 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val &= ~BIT(0); BIT 111 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c val |= BIT(3); BIT 130 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), BIT 135 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), BIT 140 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)), BIT 145 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)), BIT 210 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); BIT 214 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c t.cal_mode = BIT(0); BIT 218 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4)) BIT 227 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c t.cal_mode = BIT(1); BIT 30 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16)); BIT 39 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17)); BIT 42 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16)); BIT 45 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20)); BIT 51 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c u32 val = (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift; BIT 54 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift); BIT 62 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(2) << shift); BIT 94 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1204), BIT(3)); BIT 97 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_set(dev, MT_VEND_ADDR(CFG, 0x80), BIT(0)); BIT 100 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76_clear(dev, MT_VEND_ADDR(CFG, 0x64), BIT(18)); BIT 74 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c mt76_wr(dev, MT_WPDMA_GLO_CFG, BIT(4) | BIT(5)); BIT 98 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); BIT 170 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); BIT 171 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); BIT 173 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); BIT 174 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); BIT 73 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c patch_mask = BIT(0); BIT 76 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c patch_mask = BIT(1); BIT 224 drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c mt76_set(dev, MT_MCU_COM_REG0, BIT(1)); BIT 68 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), BIT 73 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), BIT 78 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)), BIT 83 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)), BIT 145 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); BIT 167 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c mt76_set(dev, MT_BBP(TXO, 4), BIT(25)); BIT 168 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c mt76_set(dev, MT_BBP(RXO, 13), BIT(8)); BIT 190 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c flag |= BIT(0); BIT 192 drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c flag |= BIT(8); BIT 59 drivers/net/wireless/mediatek/mt76/util.c mask[i] |= BIT(idx); BIT 22 drivers/net/wireless/mediatek/mt76/util.h mask[idx / BITS_PER_LONG] &= ~BIT(idx % BITS_PER_LONG); BIT 39 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_PKT_INFO_NEXT_VLD BIT(16) BIT 40 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_PKT_INFO_TX_BURST BIT(17) BIT 41 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_PKT_INFO_80211 BIT(19) BIT 42 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_PKT_INFO_TSO BIT(20) BIT 43 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_PKT_INFO_CSO BIT(21) BIT 44 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_PKT_INFO_WIV BIT(24) BIT 89 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_INFO_PCIE_INTR BIT(24) BIT 95 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_PKT_INFO_UDP_ERR BIT(16) BIT 96 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_PKT_INFO_TCP_ERR BIT(17) BIT 97 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_PKT_INFO_IP_ERR BIT(18) BIT 98 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_PKT_INFO_PKT_80211 BIT(19) BIT 99 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_PKT_INFO_L3L4_DONE BIT(20) BIT 103 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_CMD_INFO_SELF_GEN BIT(15) BIT 212 drivers/net/wireless/mediatek/mt7601u/eeprom.c if (comp & BIT(7)) BIT 296 drivers/net/wireless/mediatek/mt7601u/eeprom.c if (!field_valid(val) || !(val & BIT(7))) BIT 302 drivers/net/wireless/mediatek/mt7601u/eeprom.c if (val & BIT(6)) BIT 51 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0) BIT 52 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1) BIT 53 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2) BIT 54 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3) BIT 55 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13) BIT 59 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_2_HW_ANTDIV BIT(8) BIT 61 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_2_TEMP_DISABLE BIT(11) BIT 127 drivers/net/wireless/mediatek/mt7601u/eeprom.h if (s6 & BIT(5)) BIT 128 drivers/net/wireless/mediatek/mt7601u/eeprom.h s6 -= BIT(6); BIT 612 drivers/net/wireless/mediatek/mt7601u/init.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); BIT 291 drivers/net/wireless/mediatek/mt7601u/mac.c if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) BIT 486 drivers/net/wireless/mediatek/mt7601u/mac.c status->chains = BIT(0); BIT 46 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_BA BIT(0) BIT 47 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_DATA BIT(1) BIT 48 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_NULL BIT(2) BIT 49 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_FRAG BIT(3) BIT 50 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_U2M BIT(4) BIT 51 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_MULTICAST BIT(5) BIT 52 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_BROADCAST BIT(6) BIT 53 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_MYBSS BIT(7) BIT 54 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_CRCERR BIT(8) BIT 55 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_ICVERR BIT(9) BIT 56 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_MICERR BIT(10) BIT 57 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_AMSDU BIT(11) BIT 58 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_HTC BIT(12) BIT 59 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_RSSI BIT(13) BIT 60 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_L2PAD BIT(14) BIT 61 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_AMPDU BIT(15) BIT 62 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_DECRYPT BIT(16) BIT 63 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_BSSIDX3 BIT(17) BIT 64 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_WAPI_KEY BIT(18) BIT 66 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_SW_PKT_80211 BIT(22) BIT 67 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_TCP_SUM_BYPASS BIT(28) BIT 68 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_IP_SUM_BYPASS BIT(29) BIT 69 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_TCP_SUM_ERR BIT(30) BIT 70 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_IP_SUM_ERR BIT(31) BIT 83 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_RATE_BW BIT(7) BIT 84 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_RATE_SGI BIT(8) BIT 86 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_RATE_ETXBF BIT(11) BIT 87 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_RATE_SND BIT(12) BIT 88 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_RATE_ITXBF BIT(13) BIT 93 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_ANT_AUX_LNA BIT(7) BIT 126 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_FRAG BIT(0) BIT 127 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_MMPS BIT(1) BIT 128 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_CFACK BIT(2) BIT 129 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_TS BIT(3) BIT 130 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_AMPDU BIT(4) BIT 134 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_NO_RATE_FALLBACK BIT(13) BIT 135 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_TX_RPT BIT(14) BIT 136 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15) BIT 139 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_RATE_BW BIT(7) BIT 140 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_RATE_SGI BIT(8) BIT 144 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_ACK_CTL_REQ BIT(0) BIT 145 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_ACK_CTL_NSEQ BIT(1) BIT 152 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_CTL_CHAN_CHECK_PKT BIT(4) BIT 153 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_CTL_PIFS_REV BIT(6) BIT 62 drivers/net/wireless/mediatek/mt7601u/main.c if (dev->wcid_mask[wcid / BITS_PER_LONG] & BIT(wcid % BITS_PER_LONG)) BIT 64 drivers/net/wireless/mediatek/mt7601u/main.c dev->wcid_mask[wcid / BITS_PER_LONG] |= BIT(wcid % BITS_PER_LONG); BIT 78 drivers/net/wireless/mediatek/mt7601u/main.c dev->wcid_mask[wcid / BITS_PER_LONG] &= ~BIT(wcid % BITS_PER_LONG); BIT 197 drivers/net/wireless/mediatek/mt7601u/main.c dev->wcid_mask[i] |= BIT(idx); BIT 250 drivers/net/wireless/mediatek/mt7601u/main.c dev->wcid_mask[idx / BITS_PER_LONG] &= ~BIT(idx % BITS_PER_LONG); BIT 361 drivers/net/wireless/mediatek/mt7601u/main.c mt76_set(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, BIT(16 + tid)); BIT 365 drivers/net/wireless/mediatek/mt7601u/main.c BIT(16 + tid)); BIT 347 drivers/net/wireless/mediatek/mt7601u/mcu.c if (!mt76_poll_msec(dev, MT_MCU_COM_REG1, BIT(31), BIT(31), 500)) BIT 267 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_rf_set(dev, 0, 4, BIT(7)); BIT 18 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_CMB_CTRL_XTAL_RDY BIT(22) BIT 19 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_CMB_CTRL_PLL_LD BIT(23) BIT 27 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EFUSE_CTRL_KICK BIT(30) BIT 28 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EFUSE_CTRL_SEL BIT(31) BIT 34 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_COEXCFG0_COEX_EN BIT(0) BIT 37 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0) BIT 38 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1) BIT 39 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2) BIT 41 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */ BIT 42 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */ BIT 44 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4) BIT 45 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5) BIT 46 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6) BIT 47 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7) BIT 49 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_THERM_RST BIT(8) /* MT76x2 */ BIT 50 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9) /* MT76x2 */ BIT 71 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0) BIT 72 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12) BIT 73 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13) BIT 75 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20) BIT 76 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21) BIT 77 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22) BIT 78 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24) BIT 79 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25) BIT 80 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26) BIT 81 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27) BIT 82 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_STATE_UP BIT(28) BIT 87 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_RX_DONE(_n) BIT(_n) BIT 90 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_TX_DONE(_n) BIT(_n + 4) BIT 91 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_RX_COHERENT BIT(16) BIT 92 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_TX_COHERENT BIT(17) BIT 93 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_ANY_COHERENT BIT(18) BIT 94 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_MCU_CMD BIT(19) BIT 95 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_TBTT BIT(20) BIT 96 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_PRE_TBTT BIT(21) BIT 97 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_TX_STAT BIT(22) BIT 98 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_AUTO_WAKEUP BIT(23) BIT 99 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_GPTIMER BIT(24) BIT 100 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_RXDELAYINT BIT(26) BIT 101 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_TXDELAYINT BIT(27) BIT 104 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) BIT 105 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) BIT 106 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) BIT 107 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) BIT 109 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) BIT 110 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) BIT 112 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30) BIT 113 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) BIT 142 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_PHY_CLR BIT(16) BIT 143 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_TX_CLR BIT(19) BIT 144 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_TXOP_HALT BIT(20) BIT 145 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21) BIT 146 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_RX_BULK_EN BIT(22) BIT 147 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_TX_BULK_EN BIT(23) BIT 148 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_UDMA_RX_WL_DROP BIT(25) BIT 150 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_RX_BUSY BIT(30) BIT 151 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_TX_BUSY BIT(31) BIT 167 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_SYS_CTRL_MCU_RESET BIT(0) BIT 168 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_SYS_CTRL_DMA_RESET BIT(1) BIT 169 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_SYS_CTRL_MAC_RESET BIT(2) BIT 170 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_SYS_CTRL_PBF_RESET BIT(3) BIT 171 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_SYS_CTRL_ASY_RESET BIT(4) BIT 174 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_CFG_TX0Q_EN BIT(0) BIT 175 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_CFG_TX1Q_EN BIT(1) BIT 176 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_CFG_TX2Q_EN BIT(2) BIT 177 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_CFG_TX3Q_EN BIT(3) BIT 178 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_CFG_RX0Q_EN BIT(4) BIT 179 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PBF_CFG_RX_DROP_EN BIT(8) BIT 194 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RF_CSR_CFG_WR BIT(30) BIT 195 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RF_CSR_CFG_KICK BIT(31) BIT 205 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RF_CTRL_WRITE BIT(12) BIT 206 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RF_CTRL_BUSY BIT(13) BIT 207 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RF_CTRL_IDX BIT(16) BIT 216 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_FCE_L2_STUFF_HT_L2_EN BIT(0) BIT 217 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1) BIT 218 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2) BIT 219 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3) BIT 220 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4) BIT 221 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5) BIT 241 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_SYS_CTRL_RESET_CSR BIT(0) BIT 242 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_SYS_CTRL_RESET_BBP BIT(1) BIT 243 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2) BIT 244 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3) BIT 255 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21) BIT 256 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22) BIT 257 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23) BIT 266 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_CSR_CFG_READ BIT(16) BIT 267 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_CSR_CFG_BUSY BIT(17) BIT 268 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_CSR_CFG_PAR_DUR BIT(18) BIT 269 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_CSR_CFG_RW_MODE BIT(19) BIT 279 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WCID_DROP_MASK(_n) BIT((_n) % 32) BIT 287 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_APC_BSSID0_H_EN BIT(16) BIT 294 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29) BIT 302 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BEACON_TIME_CFG_TIMER_EN BIT(16) BIT 304 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BEACON_TIME_CFG_TBTT_EN BIT(19) BIT 305 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BEACON_TIME_CFG_BEACON_TX BIT(20) BIT 316 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0) BIT 317 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1) BIT 320 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_STATUS_TX BIT(0) BIT 321 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_STATUS_RX BIT(1) BIT 350 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_BAND_CFG_UPPER_40M BIT(0) BIT 351 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_BAND_CFG_5G BIT(1) BIT 352 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_BAND_CFG_2G BIT(2) BIT 373 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_RTS_FALLBACK BIT(24) BIT 391 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_CTRL_RTS_CTS BIT(16) BIT 392 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_CTRL_CTS2SELF BIT(17) BIT 393 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_NAV_SHORT BIT(18) BIT 394 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_NAV_LONG BIT(19) BIT 395 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_TXOP_ALLOW_CCK BIT(20) BIT 396 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_TXOP_ALLOW_OFDM BIT(21) BIT 397 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_TXOP_ALLOW_MM20 BIT(22) BIT 398 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_TXOP_ALLOW_MM40 BIT(23) BIT 399 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_TXOP_ALLOW_GF20 BIT(24) BIT 400 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_TXOP_ALLOW_GF40 BIT(25) BIT 401 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_RTS_THR_EN BIT(26) BIT 419 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16) BIT 420 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17) BIT 421 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_FBK_LIMIT_RATE_LUT BIT(18) BIT 451 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_CRC_ERR BIT(0) BIT 452 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_PHY_ERR BIT(1) BIT 453 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_PROMISC BIT(2) BIT 454 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_OTHER_BSS BIT(3) BIT 455 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_VER_ERR BIT(4) BIT 456 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_MCAST BIT(5) BIT 457 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_BCAST BIT(6) BIT 458 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_DUP BIT(7) BIT 459 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_CFACK BIT(8) BIT 460 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_CFEND BIT(9) BIT 461 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_ACK BIT(10) BIT 462 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_CTS BIT(11) BIT 463 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_RTS BIT(12) BIT 464 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_PSPOLL BIT(13) BIT 465 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_BA BIT(14) BIT 466 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_BAR BIT(15) BIT 467 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_FILTR_CFG_CTRL_RSV BIT(16) BIT 471 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_AUTO_RSP_PREAMB_SHORT BIT(4) BIT 477 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0) BIT 511 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_STAT_FIFO_VALID BIT(0) BIT 513 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_STAT_FIFO_SUCCESS BIT(5) BIT 514 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_STAT_FIFO_AGGR BIT(6) BIT 515 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_STAT_FIFO_ACKREQ BIT(7) BIT 581 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WCID_ATTR_PAIRWISE BIT(0) BIT 585 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10) BIT 586 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WCID_ATTR_BSS_IDX_EXT BIT(11) BIT 587 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WCID_ATTR_WAPI_MCBC BIT(15) BIT 56 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 57 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c BIT(IEEE80211_STYPE_AUTH >> 4), BIT 58 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 59 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 60 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c BIT(IEEE80211_STYPE_AUTH >> 4), BIT 63 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c .tx = BIT(IEEE80211_STYPE_ACTION >> 4), BIT 64 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 65 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 66 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 67 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 68 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c BIT(IEEE80211_STYPE_AUTH >> 4), BIT 380 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c new_mask = vif->mgmt_frames_bitmask | BIT(mgmt_type); BIT 382 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c new_mask = vif->mgmt_frames_bitmask & ~BIT(mgmt_type); BIT 513 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_AUTHORIZED); BIT 515 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->set |= BIT(NL80211_STA_FLAG_AUTHORIZED); BIT 519 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_SHORT_PREAMBLE); BIT 521 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->set |= BIT(NL80211_STA_FLAG_SHORT_PREAMBLE); BIT 525 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_WME); BIT 527 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->set |= BIT(NL80211_STA_FLAG_WME); BIT 531 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_MFP); BIT 533 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->set |= BIT(NL80211_STA_FLAG_MFP); BIT 537 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_AUTHENTICATED); BIT 539 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->set |= BIT(NL80211_STA_FLAG_AUTHENTICATED); BIT 543 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 545 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->set |= BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 549 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_ASSOCIATED); BIT 551 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->set |= BIT(NL80211_STA_FLAG_ASSOCIATED); BIT 1951 drivers/net/wireless/quantenna/qtnfmac/commands.c if (flags & BIT(NL80211_STA_FLAG_AUTHORIZED)) BIT 1953 drivers/net/wireless/quantenna/qtnfmac/commands.c if (flags & BIT(NL80211_STA_FLAG_SHORT_PREAMBLE)) BIT 1955 drivers/net/wireless/quantenna/qtnfmac/commands.c if (flags & BIT(NL80211_STA_FLAG_WME)) BIT 1957 drivers/net/wireless/quantenna/qtnfmac/commands.c if (flags & BIT(NL80211_STA_FLAG_MFP)) BIT 1959 drivers/net/wireless/quantenna/qtnfmac/commands.c if (flags & BIT(NL80211_STA_FLAG_AUTHENTICATED)) BIT 1961 drivers/net/wireless/quantenna/qtnfmac/commands.c if (flags & BIT(NL80211_STA_FLAG_TDLS_PEER)) BIT 1963 drivers/net/wireless/quantenna/qtnfmac/commands.c if (flags & BIT(NL80211_STA_FLAG_ASSOCIATED)) BIT 543 drivers/net/wireless/quantenna/qtnfmac/core.c if (!(bus->hw_info.mac_bitmap & BIT(macid))) { BIT 791 drivers/net/wireless/quantenna/qtnfmac/core.c if (!(bus->hw_info.mac_bitmap & BIT(macid))) BIT 12 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_HAS_UBOOT BIT(0) BIT 13 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_HAS_FIRMWARE BIT(1) BIT 14 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_REQ_UBOOT BIT(2) BIT 15 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_REQ_FIRMWARE BIT(3) BIT 16 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_ERROR_UBOOT BIT(4) BIT 17 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_ERROR_FIRMWARE BIT(5) BIT 19 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_FW_LOADRDY BIT(8) BIT 20 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_FW_SYNC BIT(9) BIT 21 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_FW_RETRY BIT(10) BIT 22 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_FW_QLINK_DONE BIT(15) BIT 23 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_EP_FW_DONE BIT(16) BIT 26 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_RC_PCIE_LINK BIT(0) BIT 27 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_RC_NET_LINK BIT(1) BIT 28 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_RC_FW_FLASHBOOT BIT(5) BIT 29 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_RC_FW_QLINK BIT(7) BIT 30 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_RC_FW_LOADRDY BIT(8) BIT 31 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_RC_FW_SYNC BIT(9) BIT 71 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h #define QTN_PCIE_TX_DESC_TQE_BIT BIT(24) BIT 90 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define HHBM_CONFIG_SOFT_RESET (BIT(8)) BIT 91 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define HHBM_WR_REQ (BIT(0)) BIT 92 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define HHBM_RD_REQ (BIT(1)) BIT 93 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define HHBM_DONE (BIT(31)) BIT 94 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define HHBM_64BIT (BIT(10)) BIT 97 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_INT_EP_RXDMA (BIT(0)) BIT 98 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_INT_HBM_UF (BIT(1)) BIT 99 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_INT_RX_LEN_ERR (BIT(2)) BIT 100 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_INT_RX_HDR_LEN_ERR (BIT(3)) BIT 101 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_INT_EP_TXDMA (BIT(12)) BIT 102 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_INT_HHBM_UF (BIT(13)) BIT 103 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_INT_EP_TXEMPTY (BIT(15)) BIT 104 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_INT_IPC (BIT(29)) BIT 107 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_INT_MSI (BIT(24)) BIT 108 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_INT_INTX (BIT(23)) BIT 112 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PEARL_ASSERT_INTX (BIT(9)) BIT 117 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define QTN_PEARL_IPC_IRQ_WORD(irq) (BIT(irq) | BIT(irq + 16)) BIT 33 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_RCMODE BIT(1) BIT 34 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_MSI BIT(2) BIT 35 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_HOST_CALCMD BIT(3) BIT 36 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_FLASH_PRESENT BIT(4) BIT 37 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_FLASH_BOOT BIT(5) BIT 38 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_XMIT_UBOOT BIT(6) BIT 39 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_HOST_QLINK_DRV BIT(7) BIT 40 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_TARGET_FBOOT_ERR BIT(8) BIT 41 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_TARGET_FWLOAD_ERR BIT(9) BIT 42 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_HOST_NOFW_ERR BIT(12) BIT 43 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_HOST_MEMALLOC_ERR BIT(13) BIT 44 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h #define QTN_BDA_HOST_MEMMAP_ERR BIT(14) BIT 39 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define TOPAZ_IPC_IRQ_WORD(irq) (BIT(irq) | BIT(irq + 16)) BIT 43 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define TOPAZ_ASSERT_INTX BIT(9) BIT 64 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_HW_CAPAB_REG_UPDATE = BIT(0), BIT 65 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_HW_CAPAB_STA_INACT_TIMEOUT = BIT(1), BIT 66 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_HW_CAPAB_DFS_OFFLOAD = BIT(2), BIT 67 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_HW_CAPAB_SCAN_RANDOM_MAC_ADDR = BIT(3), BIT 68 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_HW_CAPAB_PWR_MGMT = BIT(4), BIT 69 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_HW_CAPAB_OBSS_SCAN = BIT(5), BIT 70 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_HW_CAPAB_SCAN_DWELL = BIT(6), BIT 71 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_HW_CAPAB_SAE = BIT(8), BIT 102 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_FLAG_AUTHORIZED = BIT(0), BIT 103 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_FLAG_SHORT_PREAMBLE = BIT(1), BIT 104 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_FLAG_WME = BIT(2), BIT 105 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_FLAG_MFP = BIT(3), BIT 106 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_FLAG_AUTHENTICATED = BIT(4), BIT 107 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_FLAG_TDLS_PEER = BIT(5), BIT 108 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_FLAG_ASSOCIATED = BIT(6), BIT 331 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_FRAME_TX_FLAG_OFFCHAN = BIT(0), BIT 332 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_FRAME_TX_FLAG_NO_CCK = BIT(1), BIT 333 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_FRAME_TX_FLAG_ACK_NOWAIT = BIT(2), BIT 334 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_FRAME_TX_FLAG_8023 = BIT(3), BIT 450 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_CONNECT_DISABLE_HT = BIT(0), BIT 451 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_CONNECT_DISABLE_VHT = BIT(1), BIT 452 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_CONNECT_USE_RRM = BIT(2), BIT 534 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_BAND_2GHZ = BIT(0), BIT 535 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_BAND_5GHZ = BIT(1), BIT 536 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_BAND_60GHZ = BIT(2), BIT 729 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_WOWLAN_TRIG_DISCONNECT = BIT(0), BIT 730 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_WOWLAN_TRIG_MAGIC_PKT = BIT(1), BIT 731 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_WOWLAN_TRIG_PATTERN_PKT = BIT(2), BIT 877 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_INFO_RATE_FLAG_HT_MCS = BIT(0), BIT 878 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_INFO_RATE_FLAG_VHT_MCS = BIT(1), BIT 879 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_INFO_RATE_FLAG_SHORT_GI = BIT(2), BIT 880 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_STA_INFO_RATE_FLAG_60G = BIT(3), BIT 1100 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_SCAN_ABORTED = BIT(0), BIT 1256 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_NO_OFDM = BIT(0), BIT 1257 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_NO_CCK = BIT(1), BIT 1258 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_NO_INDOOR = BIT(2), BIT 1259 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_NO_OUTDOOR = BIT(3), BIT 1260 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_DFS = BIT(4), BIT 1261 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_PTP_ONLY = BIT(5), BIT 1262 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_PTMP_ONLY = BIT(6), BIT 1263 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_NO_IR = BIT(7), BIT 1264 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_AUTO_BW = BIT(8), BIT 1265 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_IR_CONCURRENT = BIT(9), BIT 1266 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_NO_HT40MINUS = BIT(10), BIT 1267 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_NO_HT40PLUS = BIT(11), BIT 1268 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_NO_80MHZ = BIT(12), BIT 1269 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_RRF_NO_160MHZ = BIT(13), BIT 1299 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_DISABLED = BIT(0), BIT 1300 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_NO_IR = BIT(1), BIT 1301 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_RADAR = BIT(3), BIT 1302 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_NO_HT40PLUS = BIT(4), BIT 1303 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_NO_HT40MINUS = BIT(5), BIT 1304 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_NO_OFDM = BIT(6), BIT 1305 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_NO_80MHZ = BIT(7), BIT 1306 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_NO_160MHZ = BIT(8), BIT 1307 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_INDOOR_ONLY = BIT(9), BIT 1308 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_IR_CONCURRENT = BIT(10), BIT 1309 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_NO_20MHZ = BIT(11), BIT 1310 drivers/net/wireless/quantenna/qtnfmac/qlink.h QLINK_CHAN_NO_10MHZ = BIT(12), BIT 14 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_IFTYPE_AP); BIT 17 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_IFTYPE_STATION); BIT 20 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_IFTYPE_ADHOC); BIT 23 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_IFTYPE_MONITOR); BIT 26 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_IFTYPE_WDS); BIT 29 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_IFTYPE_AP_VLAN); BIT 40 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c if (qlink_mask & BIT(QLINK_CHAN_WIDTH_5)) BIT 41 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_CHAN_WIDTH_5); BIT 43 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c if (qlink_mask & BIT(QLINK_CHAN_WIDTH_10)) BIT 44 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_CHAN_WIDTH_10); BIT 46 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c if (qlink_mask & BIT(QLINK_CHAN_WIDTH_20_NOHT)) BIT 47 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_CHAN_WIDTH_20_NOHT); BIT 49 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c if (qlink_mask & BIT(QLINK_CHAN_WIDTH_20)) BIT 50 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_CHAN_WIDTH_20); BIT 52 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c if (qlink_mask & BIT(QLINK_CHAN_WIDTH_40)) BIT 53 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_CHAN_WIDTH_40); BIT 55 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c if (qlink_mask & BIT(QLINK_CHAN_WIDTH_80)) BIT 56 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_CHAN_WIDTH_80); BIT 58 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c if (qlink_mask & BIT(QLINK_CHAN_WIDTH_80P80)) BIT 59 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_CHAN_WIDTH_80P80); BIT 61 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c if (qlink_mask & BIT(QLINK_CHAN_WIDTH_160)) BIT 62 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c result |= BIT(NL80211_CHAN_WIDTH_160); BIT 27 drivers/net/wireless/quantenna/qtnfmac/shm_ipc.h QTNF_SHM_IPC_OUTBOUND = BIT(0), BIT 28 drivers/net/wireless/quantenna/qtnfmac/shm_ipc.h QTNF_SHM_IPC_INBOUND = BIT(1), BIT 14 drivers/net/wireless/quantenna/qtnfmac/shm_ipc_defs.h QTNF_SHM_IPC_NEW_DATA = BIT(0), BIT 15 drivers/net/wireless/quantenna/qtnfmac/shm_ipc_defs.h QTNF_SHM_IPC_ACK = BIT(1), BIT 14 drivers/net/wireless/quantenna/qtnfmac/trans.h #define QTNF_CMD_FLAG_RESP_REQ BIT(0) BIT 883 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(0), BIT 890 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(1), BIT 897 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(2), BIT 904 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(3), BIT 911 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(4), BIT 918 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(5), BIT 925 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(6), BIT 932 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(7), BIT 939 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(8), BIT 946 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(9), BIT 953 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(10), BIT 960 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c .ratemask = BIT(11), BIT 1328 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c if_limit->types = BIT(NL80211_IFTYPE_AP); BIT 1330 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c if_limit->types |= BIT(NL80211_IFTYPE_MESH_POINT); BIT 1445 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c rt2x00dev->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); BIT 1448 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c BIT(NL80211_IFTYPE_ADHOC) | BIT 1450 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 1453 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c BIT(NL80211_IFTYPE_WDS) | BIT 1455 drivers/net/wireless/ralink/rt2x00/rt2x00dev.c BIT(NL80211_IFTYPE_AP); BIT 134 drivers/net/wireless/ralink/rt2x00/rt2x00queue.h RXDONE_SIGNAL_PLCP = BIT(0), BIT 135 drivers/net/wireless/ralink/rt2x00/rt2x00queue.h RXDONE_SIGNAL_BITRATE = BIT(1), BIT 136 drivers/net/wireless/ralink/rt2x00/rt2x00queue.h RXDONE_SIGNAL_MCS = BIT(2), BIT 137 drivers/net/wireless/ralink/rt2x00/rt2x00queue.h RXDONE_MY_BSS = BIT(3), BIT 138 drivers/net/wireless/ralink/rt2x00/rt2x00queue.h RXDONE_CRYPTO_IV = BIT(4), BIT 139 drivers/net/wireless/ralink/rt2x00/rt2x00queue.h RXDONE_CRYPTO_ICV = BIT(5), BIT 140 drivers/net/wireless/ralink/rt2x00/rt2x00queue.h RXDONE_L2PAD = BIT(6), BIT 1811 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 1812 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c BIT(NL80211_IFTYPE_ADHOC); BIT 1607 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 1608 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c BIT(NL80211_IFTYPE_ADHOC) ; BIT 435 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_BMC BIT(24) BIT 436 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_LSG BIT(26) BIT 437 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_FSG BIT(27) BIT 438 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_OWN BIT(31) BIT 440 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_BROADMULTICAST BIT(0) BIT 441 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_HTC BIT(1) BIT 442 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_LAST_SEGMENT BIT(2) BIT 443 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_FIRST_SEGMENT BIT(3) BIT 444 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_LINIP BIT(4) BIT 445 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_NO_ACM BIT(5) BIT 446 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_GF BIT(6) BIT 447 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_OWN BIT(7) BIT 456 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_AGG_ENABLE BIT(5) BIT 457 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_AGG_BREAK BIT(6) BIT 471 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_RDG_NAV_EXT BIT(13) BIT 472 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_LSIG_TXOP_ENABLE BIT(14) BIT 473 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_PIFS BIT(15) BIT 477 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_NAVUSEHDR BIT(20) BIT 481 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_AGG_EN BIT(29) BIT 482 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_HWPC BIT(31) BIT 489 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_AGG_ENABLE BIT(12) BIT 490 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_RDG_ENABLE BIT(13) BIT 491 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_AGG_BREAK BIT(16) BIT 492 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_MORE_FRAG BIT(17) BIT 493 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_RAW BIT(18) BIT 494 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_ACK_REPORT BIT(19) BIT 495 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_SPE_RPT BIT(19) BIT 497 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_BT_INT BIT(23) BIT 501 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_USE_DRIVER_RATE BIT(8) BIT 502 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_CTS_SELF_ENABLE BIT(11) BIT 503 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_RTS_CTS_ENABLE BIT(12) BIT 504 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_HW_RTS_ENABLE BIT(13) BIT 511 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_QOS BIT(6) BIT 512 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_HW_SEQ_ENABLE BIT(7) BIT 513 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_USE_DRIVER_RATE BIT(8) BIT 514 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_DISABLE_DATA_FB BIT(10) BIT 515 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_CTS_SELF_ENABLE BIT(11) BIT 516 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_RTS_CTS_ENABLE BIT(12) BIT 517 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_HW_RTS_ENABLE BIT(13) BIT 518 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) BIT 519 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) BIT 520 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_SHORT_PREAMBLE BIT(24) BIT 521 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_DATA_BW BIT(25) BIT 522 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_RTS_DATA_BW BIT(27) BIT 523 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) BIT 524 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) BIT 527 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17) BIT 534 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_SHORT_PREAMBLE BIT(4) BIT 535 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_SHORT_GI BIT(6) BIT 536 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC_CCX_TAG BIT(7) BIT 537 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17) BIT 545 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define TXDESC40_HW_SEQ_ENABLE BIT(15) BIT 897 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h #define H2C_EXT BIT(7) BIT 537 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c val32 &= ~BIT(1); BIT 715 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c if (!(reg_eac & BIT(28)) && BIT 771 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c if (!(reg_eac & BIT(28)) && BIT 828 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c if (!(reg_eac & BIT(27)) && BIT 875 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c if (!(reg_eac & BIT(31)) && BIT 934 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c if (!(reg_eac & BIT(31)) && BIT 995 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c if (!(reg_eac & BIT(30)) && BIT 1069 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val32 |= BIT(10); BIT 1072 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val32 |= BIT(10); BIT 1325 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val8 &= ~(BIT(3) | BIT(4)); BIT 1337 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val8 &= ~BIT(7); BIT 1342 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val8 &= ~BIT(2); BIT 1347 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val8 &= ~(BIT(3) | BIT(4)); BIT 1353 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c if (val32 & BIT(17)) BIT 1368 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val8 |= BIT(0); BIT 1470 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val8 |= BIT(1); BIT 1475 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c if ((val8 & BIT(1)) == 0) BIT 1497 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val8 &= ~(BIT(3) | BIT(4)); BIT 1498 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val8 |= BIT(3); BIT 1594 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val32 |= (BIT(22) | BIT(23)); BIT 1598 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val8 |= BIT(5); BIT 1611 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val32 |= (BIT(0) | BIT(1)); BIT 1617 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val32 &= ~BIT(24); BIT 1618 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val32 |= BIT(23); BIT 1625 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c val8 &= ~BIT(0); BIT 235 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c val8 &= ~BIT(4); BIT 247 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c val8 &= ~BIT(2); BIT 253 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c if (val32 & BIT(17)) BIT 268 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c val8 |= BIT(0); BIT 273 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c val8 &= ~BIT(7); BIT 278 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c val8 &= ~(BIT(3) | BIT(4)); BIT 336 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c val8 |= BIT(3); BIT 353 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c val32 &= ~(BIT(28) | BIT(29) | BIT(30)); BIT 334 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 &= ~BIT(1); BIT 338 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 &= ~BIT(0); BIT 346 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 &= ~BIT(1); BIT 350 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(0); BIT 526 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 &= ~(BIT(20) | BIT(24)); BIT 530 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 &= ~BIT(4); BIT 534 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 |= BIT(3); BIT 538 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 |= BIT(24); BIT 542 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 &= ~BIT(23); BIT 546 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 |= (BIT(0) | BIT(1)); BIT 655 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c if (!(reg_eac & BIT(28)) && BIT 765 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c if (!(reg_eac & BIT(28)) && BIT 865 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c if (!(reg_eac & BIT(27)) && BIT 1232 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(1); BIT 1237 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c if ((val8 & BIT(1)) == 0) BIT 1281 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 &= ~BIT(4); BIT 1299 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c if (val32 & BIT(17)) BIT 1353 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(1); BIT 1358 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(1); BIT 1363 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 &= ~BIT(1); BIT 1368 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(0); BIT 1373 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(1); BIT 1382 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(6); BIT 1478 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */ BIT 1483 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(0); BIT 1494 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 |= (BIT(22) | BIT(23)); BIT 1510 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(5); BIT 1534 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 |= BIT(5); BIT 1547 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 |= (BIT(0) | BIT(1)); BIT 1553 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 &= ~BIT(24); BIT 1554 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 |= BIT(23); BIT 1561 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val8 &= ~BIT(0); BIT 1594 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c h2c.bt_info.data = BIT(0); BIT 1637 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 |= BIT(8) | BIT(9) | BIT(10); BIT 1641 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c val32 |= BIT(7); BIT 909 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (!(val8 & BIT(mbox_nr))) BIT 959 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (!(val8 & BIT(mbox_nr))) BIT 996 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(0) | BIT(3); BIT 1000 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(4) | BIT(5)); BIT 1001 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(3); BIT 1003 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(20) | BIT(21)); BIT 1004 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(19); BIT 1043 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(3) | BIT(4) | BIT(5)); BIT 1045 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(19) | BIT(20) | BIT(21)); BIT 1069 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c sps0 &= ~(BIT(0) | BIT(3)); BIT 1078 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~BIT(6); BIT 1083 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~BIT(0); BIT 1290 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(30) | BIT(31)); BIT 1784 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (val32 & BIT(31)) BIT 1887 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (word_mask & BIT(i)) { BIT 1916 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~BIT(0); BIT 1924 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(0); BIT 2016 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~BIT(19); BIT 2244 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); BIT 2268 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(0) | BIT(1)); BIT 2269 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(1); BIT 2291 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(4) | BIT(5)); BIT 2292 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(4); BIT 2296 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(27) | BIT(26)); BIT 2297 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(27); BIT 2301 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(27) | BIT(26)); BIT 2302 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(27); BIT 2306 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(27) | BIT(26)); BIT 2307 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(27); BIT 2311 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(27) | BIT(26)); BIT 2312 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(27); BIT 2316 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(27) | BIT(26)); BIT 2317 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(27); BIT 2417 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(20); /* 0x10 << 16 */ BIT 2422 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(4); BIT 2673 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~BIT(31); BIT 2675 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(31); BIT 2694 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~BIT(29); BIT 2696 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(29); BIT 2750 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~BIT(27); BIT 2752 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(27); BIT 2771 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~BIT(25); BIT 2773 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(25); BIT 3013 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); BIT 3015 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); BIT 3056 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (!(reg_eac & BIT(28)) && BIT 3064 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (!(reg_eac & BIT(27)) && BIT 3093 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (!(reg_eac & BIT(31)) && BIT 3100 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (!(reg_eac & BIT(30)) && BIT 3183 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~BIT(10); BIT 3186 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~BIT(10); BIT 3564 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(1); BIT 3569 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if ((val8 & BIT(1)) == 0) BIT 3639 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ BIT 3657 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~(BIT(3) | BIT(7)); BIT 3662 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~BIT(0); BIT 3667 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~(BIT(3) | BIT(4)); BIT 3680 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~BIT(4); BIT 3681 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(3); BIT 3685 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(7); BIT 3690 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(0); BIT 3784 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= BIT(1); BIT 3812 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~BIT(0); BIT 3816 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(0); BIT 3845 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 &= ~(BIT(22) | BIT(23)); BIT 4119 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~(BIT(4) | BIT(5)); BIT 4120 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(4); BIT 4121 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(1) | BIT(2) | BIT(3); BIT 4128 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(7); BIT 4140 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 |= BIT(5) | BIT(6); BIT 4157 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); BIT 4187 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val8 &= ~BIT(3); BIT 4346 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c h2c.b_macid_cfg.data1 |= BIT(7); BIT 4388 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c h2c.media_status_rpt.parm |= BIT(0); BIT 4390 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c h2c.media_status_rpt.parm &= ~BIT(0); BIT 6097 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); BIT 10 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_ISO_MD2PP BIT(0) BIT 11 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_ISO_ANALOG_IPS BIT(5) BIT 12 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_ISO_DIOR BIT(9) BIT 13 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_ISO_PWC_EV25V BIT(14) BIT 14 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_ISO_PWC_EV12V BIT(15) BIT 17 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_BBRSTB BIT(0) BIT 18 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_BB_GLB_RSTN BIT(1) BIT 19 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_USBA BIT(2) BIT 20 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_UPLL BIT(3) BIT 21 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_USBD BIT(4) BIT 22 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_DIO_PCIE BIT(5) BIT 23 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_PCIEA BIT(6) BIT 24 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_PPLL BIT(7) BIT 25 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_PCIED BIT(8) BIT 26 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_DIOE BIT(9) BIT 27 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_CPU_ENABLE BIT(10) BIT 28 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_DCORE BIT(11) BIT 29 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_ELDR BIT(12) BIT 30 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_DIO_RF BIT(13) BIT 31 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_HWPDN BIT(14) BIT 32 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_FUNC_MREGEN BIT(15) BIT 35 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APS_FSMCO_PFM_ALDN BIT(1) BIT 36 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APS_FSMCO_PFM_WOWL BIT(3) BIT 37 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APS_FSMCO_ENABLE_POWERDOWN BIT(4) BIT 38 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APS_FSMCO_MAC_ENABLE BIT(8) BIT 39 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APS_FSMCO_MAC_OFF BIT(9) BIT 40 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APS_FSMCO_SW_LPS BIT(10) BIT 41 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APS_FSMCO_HW_SUSPEND BIT(11) BIT 42 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APS_FSMCO_PCIE BIT(12) BIT 43 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APS_FSMCO_HW_POWERDOWN BIT(15) BIT 44 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APS_FSMCO_WLON_RESET BIT(16) BIT 47 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_ANAD16V_ENABLE BIT(0) BIT 48 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_ANA8M BIT(1) BIT 49 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_MACSLP BIT(4) BIT 50 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_LOADER_ENABLE BIT(5) BIT 51 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_80M_SSC_DISABLE BIT(7) BIT 52 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) BIT 53 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_PHY_SSC_RSTB BIT(9) BIT 54 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_SEC_CLK_ENABLE BIT(10) BIT 55 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_MAC_CLK_ENABLE BIT(11) BIT 56 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_ENABLE BIT(12) BIT 57 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CLK_RING_CLK_ENABLE BIT(13) BIT 60 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define EEPROM_BOOT BIT(4) BIT 61 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define EEPROM_ENABLE BIT(5) BIT 65 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_MISC_WL_XTAL_CTRL BIT(6) BIT 73 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RF_ENABLE BIT(0) BIT 74 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RF_RSTB BIT(1) BIT 75 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RF_SDMRSTB BIT(2) BIT 78 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define LDOA15_ENABLE BIT(0) BIT 79 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define LDOA15_STANDBY BIT(1) BIT 80 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define LDOA15_OBUF BIT(2) BIT 81 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define LDOA15_REG_VOS BIT(3) BIT 85 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define LDOV12D_ENABLE BIT(0) BIT 86 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define LDOV12D_STANDBY BIT(1) BIT 92 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define LPLDO_HSM BIT(2) BIT 93 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define LPLDO_LSM_DIS BIT(3) BIT 96 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_XTAL_ENABLE BIT(0) BIT 97 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_XTAL_B_SELECT BIT(1) BIT 98 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_XTAL_GATE_USB BIT(8) BIT 99 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_XTAL_GATE_AFE BIT(11) BIT 100 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_XTAL_RF_GATE BIT(14) BIT 101 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_XTAL_GATE_DIG BIT(17) BIT 102 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_XTAL_BT_GATE BIT(20) BIT 108 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_PLL_ENABLE BIT(0) BIT 109 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_PLL_320_ENABLE BIT(1) BIT 110 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APE_PLL_FREF_SELECT BIT(2) BIT 111 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_PLL_EDGE_SELECT BIT(3) BIT 112 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_PLL_WDOGB BIT(4) BIT 113 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AFE_PLL_LPF_ENABLE BIT(5) BIT 119 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define EFUSE_TRPT BIT(7) BIT 121 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define EFUSE_CELL_SEL (BIT(8) | BIT(9)) BIT 122 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define EFUSE_LDOE25_ENABLE BIT(31) BIT 133 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11) BIT 142 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9) BIT 145 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define LEDCFG0_DPDT_SELECT BIT(23) BIT 148 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define LEDCFG2_DPDT_SELECT BIT(7) BIT 159 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1) BIT 160 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9) BIT 164 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0) BIT 169 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW BIT 171 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity BIT 173 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ BIT 175 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW BIT 177 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW BIT 179 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity BIT 181 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ BIT 182 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS BIT 184 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW BIT 186 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity BIT 188 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ BIT 194 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MCU_FW_DL_ENABLE BIT(0) BIT 195 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MCU_FW_DL_READY BIT(1) BIT 196 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MCU_FW_DL_CSUM_REPORT BIT(2) BIT 197 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MCU_MAC_INIT_READY BIT(3) BIT 198 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MCU_BB_INIT_READY BIT(4) BIT 199 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MCU_RF_INIT_READY BIT(5) BIT 200 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MCU_WINT_INIT_READY BIT(6) BIT 201 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ BIT 202 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MCU_CP_RESET BIT(23) BIT 211 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit BIT 213 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */ BIT 214 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */ BIT 215 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */ BIT 216 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */ BIT 217 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */ BIT 218 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle BIT 220 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ BIT 221 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */ BIT 222 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & BIT 224 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt BIT 226 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_ATIMEND BIT(12) /* CTWidnow End or BIT 228 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator BIT 230 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT BIT 232 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT BIT 234 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT BIT 236 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */ BIT 237 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */ BIT 238 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */ BIT 239 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */ BIT 240 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */ BIT 241 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_VODOK BIT(2) /* AC_VO DMA OK */ BIT 242 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */ BIT 243 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR0_ROK BIT(0) /* Receive DMA OK */ BIT 246 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ BIT 247 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ BIT 248 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ BIT 249 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ BIT 250 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ BIT 251 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ BIT 252 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ BIT 253 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */ BIT 254 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */ BIT 255 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */ BIT 256 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */ BIT 257 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */ BIT 258 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */ BIT 259 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */ BIT 260 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension BIT 262 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status, BIT 264 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status, BIT 266 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */ BIT 267 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */ BIT 281 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) BIT 282 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define HPON_FSM_BONDING_1T2R BIT(22) BIT 284 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_XCLK_VLD BIT(0) BIT 285 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_ACLK_VLD BIT(1) BIT 286 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_UCLK_VLD BIT(2) BIT 287 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_PCLK_VLD BIT(3) BIT 288 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_PCIRSTB BIT(4) BIT 289 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_V15_VLD BIT(5) BIT 290 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_TRP_B15V_EN BIT(7) BIT 291 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */ BIT 292 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_SIC_IDLE BIT(8) BIT 293 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_BD_MAC2 BIT(9) BIT 294 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_BD_MAC1 BIT(10) BIT 295 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_IC_MACPHY_MODE BIT(11) BIT 296 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) BIT 297 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_BT_FUNC BIT(16) BIT 298 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_VENDOR_ID BIT(19) BIT 299 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19)) BIT 301 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_VENDOR_ID_SMIC BIT(18) BIT 302 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_VENDOR_ID_UMC BIT(19) BIT 303 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_PAD_HWPD_IDN BIT(22) BIT 304 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_TRP_VAUX_EN BIT(23) BIT 305 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_TRP_BT_EN BIT(24) BIT 306 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */ BIT 307 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_BD_PKG_SEL BIT(25) BIT 308 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_BD_HCI_SEL BIT(26) BIT 309 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_TYPE_ID BIT(27) BIT 310 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, BIT 312 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; BIT 318 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) BIT 319 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) BIT 320 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_HCI_SEL (BIT(4) | BIT(5)) BIT 321 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_PKG_SEL_HCI BIT(6) BIT 322 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_FEN_GPS BIT(7) BIT 323 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_FEN_BT BIT(8) BIT 324 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_FEN_WL BIT(9) BIT 325 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_FEN_PCI BIT(10) BIT 326 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_FEN_USB BIT(11) BIT 327 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_BTRF_HWPDN_N BIT(12) BIT 328 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_WLRF_HWPDN_N BIT(13) BIT 329 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_PDN_BT_N BIT(14) BIT 330 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_PDN_GPS_N BIT(15) BIT 331 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_BT_CTL_HWPDN BIT(16) BIT 332 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_GPS_CTL_HWPDN BIT(17) BIT 333 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_PPHY_SUSB BIT(20) BIT 334 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_UPHY_SUSB BIT(21) BIT 335 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_PCI_SUSEN BIT(22) BIT 336 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_USB_SUSEN BIT(23) BIT 337 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) BIT 343 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_HCI_TXDMA_ENABLE BIT(0) BIT 344 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_HCI_RXDMA_ENABLE BIT(1) BIT 345 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_TXDMA_ENABLE BIT(2) BIT 346 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_RXDMA_ENABLE BIT(3) BIT 347 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_PROTOCOL_ENABLE BIT(4) BIT 348 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_SCHEDULE_ENABLE BIT(5) BIT 349 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_MAC_TX_ENABLE BIT(6) BIT 350 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_MAC_RX_ENABLE BIT(7) BIT 351 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_SW_BEACON_ENABLE BIT(8) BIT 352 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_SECURITY_ENABLE BIT(9) BIT 353 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CR_CALTIMER_ENABLE BIT(10) BIT 373 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2) BIT 439 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RQPN_LOAD BIT(31) BIT 444 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define TXDMA_OFFSET_DROP_DATA_EN BIT(9) BIT 451 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define AUTO_LLT_INIT_LLT BIT(16) BIT 461 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RXDMA_USB_AGG_ENABLE BIT(31) BIT 463 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RXPKT_NUM_RXDMA_IDLE BIT(17) BIT 464 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RXPKT_NUM_RW_RELEASE_EN BIT(18) BIT 493 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) BIT 494 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) BIT 519 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_1M BIT(0) BIT 520 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_2M BIT(1) BIT 521 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_5_5M BIT(2) BIT 522 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_11M BIT(3) BIT 523 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_6M BIT(4) BIT 524 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_9M BIT(5) BIT 525 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_12M BIT(6) BIT 526 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_18M BIT(7) BIT 527 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_24M BIT(8) BIT 528 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_36M BIT(9) BIT 529 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_48M BIT(10) BIT 530 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_54M BIT(11) BIT 531 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_MCS0 BIT(12) BIT 532 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_MCS1 BIT(13) BIT 533 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_MCS2 BIT(14) BIT 534 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_MCS3 BIT(15) BIT 535 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_MCS4 BIT(16) BIT 536 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_MCS5 BIT(17) BIT 537 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_MCS6 BIT(18) BIT 538 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_MCS7 BIT(19) BIT 539 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ BIT 540 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ BIT 543 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RSR_ACK_SHORT_PREAMBLE BIT(23) BIT 591 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1) BIT 622 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define BEACON_ATIM BIT(0) BIT 623 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define BEACON_CTRL_MBSSID BIT(1) BIT 624 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define BEACON_CTRL_TX_BEACON_RPT BIT(2) BIT 625 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define BEACON_FUNCTION_ENABLE BIT(3) BIT 626 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define BEACON_DISABLE_TSF_UPDATE BIT(4) BIT 630 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define DUAL_TSF_RESET_TSF0 BIT(0) BIT 631 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define DUAL_TSF_RESET_TSF1 BIT(1) BIT 632 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define DUAL_TSF_RESET_P2P BIT(4) BIT 633 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define DUAL_TSF_TX_OK BIT(5) BIT 658 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define ACM_HW_CTRL_BK BIT(0) BIT 659 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define ACM_HW_CTRL_BE BIT(1) BIT 660 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define ACM_HW_CTRL_VI BIT(2) BIT 661 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define ACM_HW_CTRL_VO BIT(3) BIT 678 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APSD_CTRL_OFF BIT(6) BIT 679 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define APSD_CTRL_OFF_STATUS BIT(7) BIT 681 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define BW_OPMODE_20MHZ BIT(2) BIT 682 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define BW_OPMODE_5G BIT(1) BIT 683 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define BW_OPMODE_11J BIT(0) BIT 689 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ BIT 690 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ BIT 691 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_MCAST BIT(2) BIT 692 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_BCAST BIT(3) BIT 693 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match BIT 695 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_PM BIT(5) /* Accept power management BIT 697 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ BIT 698 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet BIT 700 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ BIT 701 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ BIT 702 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use BIT 704 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use BIT 706 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use BIT 708 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ BIT 709 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet BIT 711 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet BIT 713 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/ BIT 714 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_MFBEN BIT(22) BIT 715 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection BIT 719 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ BIT 720 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_FORCE_ACK BIT(26) BIT 721 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ BIT 722 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_APPEND_PHYSTAT BIT(28) BIT 723 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_APPEND_ICV BIT(29) BIT 724 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_APPEND_MIC BIT(30) BIT 725 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ BIT 760 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8)) BIT 762 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define WMAC_TRXPTCL_CTL_BW_40 BIT(7) BIT 763 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define WMAC_TRXPTCL_CTL_BW_80 BIT(8) BIT 767 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CAM_CMD_POLLING BIT(31) BIT 768 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CAM_CMD_WRITE BIT(16) BIT 771 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CAM_WRITE_VALID BIT(15) BIT 775 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SEC_CFG_TX_USE_DEFKEY BIT(0) BIT 776 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SEC_CFG_RX_USE_DEFKEY BIT(1) BIT 777 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SEC_CFG_TX_SEC_ENABLE BIT(2) BIT 778 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SEC_CFG_RX_SEC_ENABLE BIT(3) BIT 779 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SEC_CFG_SKBYA2 BIT(4) BIT 780 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SEC_CFG_NO_SKMC BIT(5) BIT 781 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SEC_CFG_TXBC_USE_DEFKEY BIT(6) BIT 782 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define SEC_CFG_RXBC_USE_DEFKEY BIT(7) BIT 821 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define BT_CONTROL_BT_GRANT BIT(12) BIT 826 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA_RF_MODE BIT(0) BIT 827 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA_RF_MODE_JAPAN BIT(1) BIT 828 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA_RF_MODE_CCK BIT(24) BIT 829 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA_RF_MODE_OFDM BIT(25) BIT 832 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_TX_INFO_OFDM_PATH_A BIT(0) BIT 833 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_TX_INFO_OFDM_PATH_B BIT(1) BIT 834 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_TX_INFO_OFDM_PATH_C BIT(2) BIT 835 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_TX_INFO_OFDM_PATH_D BIT(3) BIT 841 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_PS_LOWER_CHANNEL BIT(26) BIT 842 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_PS_UPPER_CHANNEL BIT(27) BIT 845 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_HSSI_PARM1_PI BIT(8) BIT 853 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) BIT 854 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) BIT 875 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_INT_OE_ANTENNA_A BIT(8) BIT 876 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_INT_OE_ANTENNA_B BIT(9) BIT 889 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_3WIRE_DATA BIT(0) BIT 890 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_3WIRE_CLOC BIT(1) BIT 891 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_3WIRE_LOAD BIT(2) BIT 892 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_3WIRE_RW BIT(3) BIT 894 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_RFENV BIT(4) BIT 895 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_TRSW BIT(5) /* Useless now */ BIT 896 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_TRSWB BIT(6) BIT 897 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_ANTSW BIT(8) BIT 898 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_ANTSWB BIT(9) BIT 899 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_PAPE BIT(10) BIT 900 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_PAPE5G BIT(11) BIT 909 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_PARM_RFA_ENABLE BIT(1) BIT 910 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_PARM_RFB_ENABLE BIT(17) BIT 911 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_RF_PARM_CLK_GATE BIT(31) BIT 915 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define FPGA0_ANALOG2_20MHZ BIT(10) BIT 939 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CCK0_SIDEBAND BIT(4) BIT 943 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CCK0_AFE_RX_ANT_AB BIT(24) BIT 945 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26)) BIT 952 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_RF_PATH_RX_A BIT(0) BIT 953 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_RF_PATH_RX_B BIT(1) BIT 954 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_RF_PATH_RX_C BIT(2) BIT 955 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_RF_PATH_RX_D BIT(3) BIT 957 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_RF_PATH_TX_A BIT(4) BIT 958 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_RF_PATH_TX_B BIT(5) BIT 959 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_RF_PATH_TX_C BIT(6) BIT 960 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_RF_PATH_TX_D BIT(7) BIT 972 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1) BIT 1002 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_LSTF_PRIME_CH_LOW BIT(10) BIT 1003 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_LSTF_PRIME_CH_HIGH BIT(11) BIT 1006 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_LSTF_CONTINUE_TX BIT(28) BIT 1007 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_LSTF_SINGLE_CARRIER BIT(29) BIT 1008 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define OFDM_LSTF_SINGLE_TONE BIT(30) BIT 1075 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_TIMEOUT2 BIT(31) BIT 1076 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_TIMEOUT1 BIT(30) BIT 1077 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_PSTIMEOUT BIT(29) BIT 1078 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_GTINT4 BIT(28) BIT 1079 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_GTINT3 BIT(27) BIT 1080 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_TXBCNERR BIT(26) BIT 1081 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_TXBCNOK BIT(25) BIT 1082 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) BIT 1083 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BCNDMAINT3 BIT(23) BIT 1084 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BCNDMAINT2 BIT(22) BIT 1085 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BCNDMAINT1 BIT(21) BIT 1086 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BCNDMAINT0 BIT(20) BIT 1087 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BCNDOK3 BIT(19) BIT 1088 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BCNDOK2 BIT(18) BIT 1089 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BCNDOK1 BIT(17) BIT 1090 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BCNDOK0 BIT(16) BIT 1091 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_HSISR_IND BIT(15) BIT 1092 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BCNDMAINT_E BIT(14) BIT 1094 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_CTW_END BIT(12) BIT 1096 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_C2HCMD BIT(10) BIT 1097 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_CPWM2 BIT(9) BIT 1098 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_CPWM BIT(8) BIT 1099 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK BIT 1101 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK BIT 1103 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ BIT 1104 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ BIT 1105 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ BIT 1106 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ BIT 1107 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_RDU BIT(1) /* Receive Descriptor BIT 1109 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ BIT 1112 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */ BIT 1113 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to BIT 1163 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MODE_AG_CHANNEL_20MHZ BIT(10) BIT 1164 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MODE_AG_BW_MASK (BIT(10) | BIT(11)) BIT 1165 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11)) BIT 1166 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h #define MODE_AG_BW_40MHZ_8723B BIT(10) BIT 392 drivers/net/wireless/realtek/rtlwifi/base.c BIT(NL80211_IFTYPE_AP) | BIT 393 drivers/net/wireless/realtek/rtlwifi/base.c BIT(NL80211_IFTYPE_STATION) | BIT 394 drivers/net/wireless/realtek/rtlwifi/base.c BIT(NL80211_IFTYPE_ADHOC) | BIT 395 drivers/net/wireless/realtek/rtlwifi/base.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 396 drivers/net/wireless/realtek/rtlwifi/base.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 397 drivers/net/wireless/realtek/rtlwifi/base.c BIT(NL80211_IFTYPE_P2P_GO); BIT 198 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c h2c_parameter[0] |= BIT(0); BIT 433 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c h2c_parameter[0] |= BIT(0); BIT 863 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.c if (u8tmp & BIT(0)) { BIT 698 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c h2c_parameter[0] |= BIT(0); BIT 4045 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.c if ((coex_sta->bt_info_ext & BIT(3))) { BIT 35 drivers/net/wireless/realtek/rtlwifi/cam.c target_command = target_command | BIT(31) | BIT(16); BIT 139 drivers/net/wireless/realtek/rtlwifi/cam.c ul_command = ul_command | BIT(31) | BIT(16); BIT 159 drivers/net/wireless/realtek/rtlwifi/cam.c ul_command = BIT(31) | BIT(30); BIT 191 drivers/net/wireless/realtek/rtlwifi/cam.c ul_content |= BIT(15); BIT 193 drivers/net/wireless/realtek/rtlwifi/cam.c ul_command = ul_command | BIT(31) | BIT(16); BIT 236 drivers/net/wireless/realtek/rtlwifi/cam.c ul_content |= BIT(15); BIT 243 drivers/net/wireless/realtek/rtlwifi/cam.c ul_command = ul_command | BIT(31) | BIT(16); BIT 278 drivers/net/wireless/realtek/rtlwifi/cam.c if ((bitmap & BIT(0)) == 0) { BIT 281 drivers/net/wireless/realtek/rtlwifi/cam.c rtlpriv->sec.hwsec_cam_bitmap |= BIT(0) << entry_idx; BIT 311 drivers/net/wireless/realtek/rtlwifi/cam.c if (((bitmap & BIT(0)) == BIT(0)) && BIT 315 drivers/net/wireless/realtek/rtlwifi/cam.c rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i); BIT 9 drivers/net/wireless/realtek/rtlwifi/cam.h #define CFG_VALID BIT(15) BIT 376 drivers/net/wireless/realtek/rtlwifi/core.c crc_bit15 = ((crc & BIT(15)) ? 1 : 0); BIT 377 drivers/net/wireless/realtek/rtlwifi/core.c data_bit = (data & (BIT(0) << i) ? 1 : 0); BIT 382 drivers/net/wireless/realtek/rtlwifi/core.c result &= (~BIT(0)); BIT 384 drivers/net/wireless/realtek/rtlwifi/core.c result |= BIT(0); BIT 386 drivers/net/wireless/realtek/rtlwifi/core.c crc_bit11 = ((crc & BIT(11)) ? 1 : 0) ^ shift_in; BIT 388 drivers/net/wireless/realtek/rtlwifi/core.c result &= (~BIT(12)); BIT 390 drivers/net/wireless/realtek/rtlwifi/core.c result |= BIT(12); BIT 392 drivers/net/wireless/realtek/rtlwifi/core.c crc_bit4 = ((crc & BIT(4)) ? 1 : 0) ^ shift_in; BIT 394 drivers/net/wireless/realtek/rtlwifi/core.c result &= (~BIT(5)); BIT 396 drivers/net/wireless/realtek/rtlwifi/core.c result |= BIT(5); BIT 232 drivers/net/wireless/realtek/rtlwifi/debug.c target_cmd = target_cmd | BIT(31); BIT 239 drivers/net/wireless/realtek/rtlwifi/debug.c if (ulstatus & BIT(31)) BIT 54 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_ERR BIT(0) BIT 55 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_FW BIT(1) BIT 56 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_INIT BIT(2) /*For init/deinit */ BIT 57 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_RECV BIT(3) /*For Rx. */ BIT 58 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_SEND BIT(4) /*For Tx. */ BIT 59 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_MLME BIT(5) /*For MLME. */ BIT 60 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_SCAN BIT(6) /*For Scan. */ BIT 61 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_INTR BIT(7) /*For interrupt Related. */ BIT 62 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_LED BIT(8) /*For LED. */ BIT 63 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_SEC BIT(9) /*For sec. */ BIT 64 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_BEACON BIT(10) /*For beacon. */ BIT 65 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_RATE BIT(11) /*For rate. */ BIT 66 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_RXDESC BIT(12) /*For rx desc. */ BIT 67 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_DIG BIT(13) /*For DIG */ BIT 68 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_TXAGC BIT(14) /*For Tx power */ BIT 69 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_HIPWR BIT(15) /*For High Power Mechanism */ BIT 70 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_POWER BIT(16) /*For lps/ips/aspm. */ BIT 71 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_POWER_TRACKING BIT(17) /*For TX POWER TRACKING */ BIT 72 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_BB_POWERSAVING BIT(18) BIT 73 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_SWAS BIT(19) /*For SW Antenna Switch */ BIT 74 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_RF BIT(20) /*For RF. */ BIT 75 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_TURBO BIT(21) /*For EDCA TURBO. */ BIT 76 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_RATR BIT(22) BIT 77 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_CMD BIT(23) BIT 78 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_EFUSE BIT(24) BIT 79 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_QOS BIT(25) BIT 80 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_MAC80211 BIT(26) BIT 81 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_REGD BIT(27) BIT 82 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_CHAN BIT(28) BIT 83 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_USB BIT(29) BIT 85 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_BT_COEXIST BIT(30) BIT 86 drivers/net/wireless/realtek/rtlwifi/debug.h #define COMP_IQK BIT(31) BIT 93 drivers/net/wireless/realtek/rtlwifi/debug.h #define EEPROM_W BIT(0) BIT 94 drivers/net/wireless/realtek/rtlwifi/debug.h #define EFUSE_PG BIT(1) BIT 95 drivers/net/wireless/realtek/rtlwifi/debug.h #define EFUSE_READ_ALL BIT(2) BIT 98 drivers/net/wireless/realtek/rtlwifi/debug.h #define INIT_EEPROM BIT(0) BIT 99 drivers/net/wireless/realtek/rtlwifi/debug.h #define INIT_TXPOWER BIT(1) BIT 100 drivers/net/wireless/realtek/rtlwifi/debug.h #define INIT_IQK BIT(2) BIT 101 drivers/net/wireless/realtek/rtlwifi/debug.h #define INIT_RF BIT(3) BIT 104 drivers/net/wireless/realtek/rtlwifi/debug.h #define PHY_BBR BIT(0) BIT 105 drivers/net/wireless/realtek/rtlwifi/debug.h #define PHY_BBW BIT(1) BIT 106 drivers/net/wireless/realtek/rtlwifi/debug.h #define PHY_RFR BIT(2) BIT 107 drivers/net/wireless/realtek/rtlwifi/debug.h #define PHY_RFW BIT(3) BIT 108 drivers/net/wireless/realtek/rtlwifi/debug.h #define PHY_MACR BIT(4) BIT 109 drivers/net/wireless/realtek/rtlwifi/debug.h #define PHY_MACW BIT(5) BIT 110 drivers/net/wireless/realtek/rtlwifi/debug.h #define PHY_ALLR BIT(6) BIT 111 drivers/net/wireless/realtek/rtlwifi/debug.h #define PHY_ALLW BIT(7) BIT 112 drivers/net/wireless/realtek/rtlwifi/debug.h #define PHY_TXPWR BIT(8) BIT 113 drivers/net/wireless/realtek/rtlwifi/debug.h #define PHY_PWRDIFF BIT(9) BIT 116 drivers/net/wireless/realtek/rtlwifi/debug.h #define WA_IOT BIT(0) BIT 117 drivers/net/wireless/realtek/rtlwifi/debug.h #define DM_PWDB BIT(1) BIT 118 drivers/net/wireless/realtek/rtlwifi/debug.h #define DM_MONITOR BIT(2) BIT 119 drivers/net/wireless/realtek/rtlwifi/debug.h #define DM_DIG BIT(3) BIT 120 drivers/net/wireless/realtek/rtlwifi/debug.h #define DM_EDCA_TURBO BIT(4) BIT 122 drivers/net/wireless/realtek/rtlwifi/debug.h #define DM_PWDB BIT(1) BIT 440 drivers/net/wireless/realtek/rtlwifi/efuse.c word_en &= ~(BIT(i / 2)); BIT 448 drivers/net/wireless/realtek/rtlwifi/efuse.c word_en &= ~(BIT(i / 2)); BIT 771 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!((target_pkt->word_en & BIT(0)) | BIT 772 drivers/net/wireless/realtek/rtlwifi/efuse.c (tmp_pkt.word_en & BIT(0)))) BIT 773 drivers/net/wireless/realtek/rtlwifi/efuse.c match_word_en &= (~BIT(0)); BIT 775 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!((target_pkt->word_en & BIT(1)) | BIT 776 drivers/net/wireless/realtek/rtlwifi/efuse.c (tmp_pkt.word_en & BIT(1)))) BIT 777 drivers/net/wireless/realtek/rtlwifi/efuse.c match_word_en &= (~BIT(1)); BIT 779 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!((target_pkt->word_en & BIT(2)) | BIT 780 drivers/net/wireless/realtek/rtlwifi/efuse.c (tmp_pkt.word_en & BIT(2)))) BIT 781 drivers/net/wireless/realtek/rtlwifi/efuse.c match_word_en &= (~BIT(2)); BIT 783 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!((target_pkt->word_en & BIT(3)) | BIT 784 drivers/net/wireless/realtek/rtlwifi/efuse.c (tmp_pkt.word_en & BIT(3)))) BIT 785 drivers/net/wireless/realtek/rtlwifi/efuse.c match_word_en &= (~BIT(3)); BIT 804 drivers/net/wireless/realtek/rtlwifi/efuse.c if ((target_pkt->word_en & BIT(0)) ^ BIT 805 drivers/net/wireless/realtek/rtlwifi/efuse.c (match_word_en & BIT(0))) BIT 806 drivers/net/wireless/realtek/rtlwifi/efuse.c tmp_word_en &= (~BIT(0)); BIT 808 drivers/net/wireless/realtek/rtlwifi/efuse.c if ((target_pkt->word_en & BIT(1)) ^ BIT 809 drivers/net/wireless/realtek/rtlwifi/efuse.c (match_word_en & BIT(1))) BIT 810 drivers/net/wireless/realtek/rtlwifi/efuse.c tmp_word_en &= (~BIT(1)); BIT 812 drivers/net/wireless/realtek/rtlwifi/efuse.c if ((target_pkt->word_en & BIT(2)) ^ BIT 813 drivers/net/wireless/realtek/rtlwifi/efuse.c (match_word_en & BIT(2))) BIT 814 drivers/net/wireless/realtek/rtlwifi/efuse.c tmp_word_en &= (~BIT(2)); BIT 816 drivers/net/wireless/realtek/rtlwifi/efuse.c if ((target_pkt->word_en & BIT(3)) ^ BIT 817 drivers/net/wireless/realtek/rtlwifi/efuse.c (match_word_en & BIT(3))) BIT 818 drivers/net/wireless/realtek/rtlwifi/efuse.c tmp_word_en &= (~BIT(3)); BIT 1010 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(0))) { BIT 1015 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(1))) { BIT 1020 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(2))) { BIT 1025 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(3))) { BIT 1044 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(0))) { BIT 1052 drivers/net/wireless/realtek/rtlwifi/efuse.c badworden &= (~BIT(0)); BIT 1055 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(1))) { BIT 1063 drivers/net/wireless/realtek/rtlwifi/efuse.c badworden &= (~BIT(1)); BIT 1066 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(2))) { BIT 1074 drivers/net/wireless/realtek/rtlwifi/efuse.c badworden &= (~BIT(2)); BIT 1077 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(3))) { BIT 1085 drivers/net/wireless/realtek/rtlwifi/efuse.c badworden &= (~BIT(3)); BIT 1139 drivers/net/wireless/realtek/rtlwifi/efuse.c tempval &= ~(BIT(3) | BIT(4) | BIT(5) | BIT(6)); BIT 1204 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(0))) BIT 1206 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(1))) BIT 1208 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(2))) BIT 1210 drivers/net/wireless/realtek/rtlwifi/efuse.c if (!(word_en & BIT(3))) BIT 222 drivers/net/wireless/realtek/rtlwifi/pci.c aspmlevel |= BIT(0) | BIT(1); BIT 224 drivers/net/wireless/realtek/rtlwifi/pci.c pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); BIT 269 drivers/net/wireless/realtek/rtlwifi/pci.c u_pcibridge_aspmsetting &= ~BIT(0); BIT 314 drivers/net/wireless/realtek/rtlwifi/pci.c if (offset_e4 & BIT(23)) BIT 395 drivers/net/wireless/realtek/rtlwifi/pci.c tmp |= BIT(4); BIT 2149 drivers/net/wireless/realtek/rtlwifi/pci.c value |= BIT(5); BIT 2151 drivers/net/wireless/realtek/rtlwifi/pci.c value &= ~BIT(5); BIT 24 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_INTF_SDIO_MSK BIT(0) BIT 25 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_INTF_USB_MSK BIT(1) BIT 26 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_INTF_PCI_MSK BIT(2) BIT 27 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) BIT 29 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_FAB_TSMC_MSK BIT(0) BIT 30 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_FAB_UMC_MSK BIT(1) BIT 31 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) BIT 33 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_CUT_TESTCHIP_MSK BIT(0) BIT 34 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_CUT_A_MSK BIT(1) BIT 35 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_CUT_B_MSK BIT(2) BIT 36 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_CUT_C_MSK BIT(3) BIT 37 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_CUT_D_MSK BIT(4) BIT 38 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_CUT_E_MSK BIT(5) BIT 39 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_CUT_F_MSK BIT(6) BIT 40 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define PWR_CUT_G_MSK BIT(7) BIT 24 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define CHIP_8723 BIT(0) BIT 25 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define CHIP_92D BIT(1) BIT 26 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define NORMAL_CHIP BIT(3) BIT 27 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6))) BIT 28 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define RF_TYPE_1T2R BIT(4) BIT 29 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define RF_TYPE_2T2R BIT(5) BIT 30 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define CHIP_VENDOR_UMC BIT(7) BIT 31 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define B_CUT_VERSION BIT(12) BIT 32 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define C_CUT_VERSION BIT(13) BIT 33 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define D_CUT_VERSION ((BIT(12)|BIT(13))) BIT 34 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define E_CUT_VERSION BIT(14) BIT 37 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) BIT 38 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define CHIP_TYPE_MASK BIT(3) BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) BIT 40 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define MANUFACTUER_MASK BIT(7) BIT 41 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) BIT 42 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) BIT 172 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), BIT 182 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), BIT 196 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(24), 0x00); BIT 204 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(28), 0x00); BIT 356 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); BIT 357 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); BIT 384 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(12), 1); BIT 385 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); BIT 407 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 1); BIT 408 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 0); BIT 409 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 1); BIT 410 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 0); BIT 411 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); BIT 412 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); BIT 413 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 0); BIT 414 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 2); BIT 415 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 0); BIT 416 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 2); BIT 1109 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17)|BIT(16), BIT 1253 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(5) | BIT(4) | BIT(3), default_ant); BIT 1255 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(8) | BIT(7) | BIT(6), optional_ant); BIT 1257 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(14) | BIT(13) | BIT(12), BIT 1260 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(6) | BIT(7), default_ant); BIT 1263 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(5) | BIT(4) | BIT(3), default_ant); BIT 1265 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(8) | BIT(7) | BIT(6), optional_ant); BIT 1286 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c pfat_table->antsel_a[mac_id] = target_ant & BIT(0); BIT 1287 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c pfat_table->antsel_b[mac_id] = (target_ant & BIT(1)) >> 1; BIT 1288 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c pfat_table->antsel_c[mac_id] = (target_ant & BIT(2)) >> 2; BIT 1304 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c MASKDWORD, value32 | (BIT(23) | BIT(25))); BIT 1306 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); BIT 1307 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0); BIT 1308 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 1); BIT 1309 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1); BIT 1313 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1); BIT 1314 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); BIT 1326 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c value32 | (BIT(23) | BIT(25))); BIT 1328 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); BIT 1329 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0); BIT 1330 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0); BIT 1331 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1); BIT 1335 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1); BIT 1336 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); BIT 1338 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 0); BIT 1362 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c MASKDWORD, value32 | (BIT(23) | BIT(25))); BIT 1365 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c MASKDWORD, value32 | (BIT(16) | BIT(17))); BIT 1372 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); BIT 1373 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0); BIT 1374 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0); BIT 1375 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1); BIT 1384 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 1); BIT 1386 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(5) | BIT(4) | BIT(3), 0); BIT 1388 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(8) | BIT(7) | BIT(6), 1); BIT 1390 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(2) | BIT(1) | BIT(0), (ant_combination - 1)); BIT 1392 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1); BIT 1648 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(16), 0); BIT 1649 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0); BIT 1652 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(16), 0); BIT 1653 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT 1654 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(7) | BIT(6), target_ant); BIT 1656 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(21), 1); BIT 1659 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c target_ant & BIT(0); BIT 1661 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c (target_ant & BIT(1)) >> 1; BIT 1663 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c (target_ant & BIT(2)) >> 2; BIT 1666 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0); BIT 1682 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, BIT(16), 1); BIT 1683 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1); BIT 1712 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0); BIT 1714 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(15), 0); BIT 1717 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(21), 0); BIT 1727 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1); BIT 1729 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(15), 1); BIT 1732 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c BIT(21), 1); BIT 151 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.h #define HAL_DM_DIG_DISABLE BIT(0) BIT 152 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.h #define HAL_DM_HIPWR_DISABLE BIT(1) BIT 139 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.c if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) { BIT 160 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.c if (((val_hmetfr >> boxnum) & BIT(0)) == 0) BIT 360 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); BIT 361 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp | BIT(2))); BIT 691 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4)); BIT 38 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_GO_ON BIT(0) BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_TX_NULL BIT(1) BIT 40 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_RF_ON BIT(2) BIT 41 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_REGISTER_ACTIVE BIT(3) BIT 43 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_DPS BIT(0) BIT 45 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_RF_OFF BIT(1) BIT 46 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_ALL_ON BIT(2) BIT 47 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_ST_ACTIVE BIT(3) BIT 48 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_ISR_ENABLE BIT(4) BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_IMR_ENABLE BIT(5) BIT 52 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_ACK BIT(6) BIT 53 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_TOGGLE BIT(7) BIT 57 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.h #define FW_PS_CLOCK_OFF BIT(0) /* 32k*/ BIT 41 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); BIT 44 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c tmp1byte &= ~(BIT(0)); BIT 54 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); BIT 57 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c tmp1byte |= BIT(0); BIT 63 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); BIT 91 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0); BIT 579 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); BIT 596 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (rpwm_val & BIT(7)) { BIT 599 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7)); BIT 632 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c (tmp_regcr | BIT(0))); BIT 634 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 635 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 641 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c tmp_reg422 & (~BIT(6))); BIT 642 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (tmp_reg422 & BIT(6)) BIT 649 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c (bcnvalid_reg | BIT(0))); BIT 656 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c while (!(bcnvalid_reg & BIT(0)) && count < 20) { BIT 663 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); BIT 665 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (bcnvalid_reg & BIT(0)) BIT 666 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0)); BIT 668 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 669 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 678 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c (tmp_regcr & ~(BIT(0)))); BIT 699 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 706 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 826 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0)); BIT 829 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); BIT 842 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); BIT 846 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2)); BIT 849 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7)); BIT 852 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1)); BIT 855 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0)); BIT 862 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3)); BIT 864 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4)))); BIT 961 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31)); BIT 986 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12)); BIT 1063 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) { BIT 1149 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (!(tmp_u1b & BIT(0))) { BIT 1154 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (!(tmp_u1b & BIT(4))) { BIT 1278 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 1281 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 1375 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1))); BIT 1378 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c while (!(u1b_tmp & BIT(1)) && (count++ < 100)) { BIT 1391 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready) BIT 1395 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); BIT 1399 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0)))); BIT 1405 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3)))); BIT 1407 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3))); BIT 1478 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c rtlpci->reg_bcn_ctrl_val |= BIT(3); BIT 1601 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3)) BIT 1611 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3)) BIT 1623 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c BIT(3)) BIT 1635 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c BIT(3)) BIT 1647 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c BIT(3)) BIT 1658 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c BIT(3)) BIT 1681 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3)) BIT 1689 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3)) BIT 1700 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c BIT(3)) BIT 1711 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c BIT(3)) BIT 1738 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3)) BIT 1949 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (tmp_u1b & BIT(4)) { BIT 1956 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c if (tmp_u1b & BIT(5)) { BIT 2184 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 2236 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF; BIT 31 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.c REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5) | BIT(6)); BIT 61 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.c (ledcfg | BIT(3) | BIT(5) | BIT(6))); BIT 67 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.c (ledcfg | BIT(3) | BIT(5) | BIT(6))); BIT 72 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.c rtl_write_byte(rtlpriv, REG_LEDCFG1, (ledcfg | BIT(3))); BIT 174 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c BIT(8)); BIT 177 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c BIT(8)); BIT 243 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c regval | BIT(13) | BIT(0) | BIT(1)); BIT 250 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); BIT 1137 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), BIT 1383 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c if (!(reg_eac & BIT(28)) && BIT 1404 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c if (!(reg_eac & BIT(31)) && BIT 1410 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c if (!(reg_eac & BIT(30)) && BIT 1454 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c if (!(reg_eac & BIT(28)) && BIT 1495 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c if (!(reg_eac & BIT(27)) && BIT 1519 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), BIT 1529 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), BIT 1612 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c (u8) (macbackup[i] & (~BIT(3)))); BIT 1613 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); BIT 1727 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, BIT(8)); BIT 1733 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, 0x800, BIT(24), 0x00); BIT 1738 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, 0x870, BIT(10), 0x01); BIT 1739 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, 0x870, BIT(26), 0x01); BIT 1740 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, 0x860, BIT(10), 0x00); BIT 1741 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, 0x864, BIT(10), 0x00); BIT 1898 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7)); BIT 1899 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); BIT 1904 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c BIT(5) | BIT(6), 0x1); BIT 1907 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c BIT(5) | BIT(6), 0x2); BIT 1909 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); BIT 1918 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c BIT(14) | BIT(13) | BIT(12), 0); BIT 1920 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c BIT(5) | BIT(4) | BIT(3), 0); BIT 1922 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); BIT 1925 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c BIT(14) | BIT(13) | BIT(12), 1); BIT 1927 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c BIT(5) | BIT(4) | BIT(3), 1); BIT 1929 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); BIT 46 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \ BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0 \ BIT 52 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \ BIT 55 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0 \ BIT 58 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0 \ BIT 61 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0) \ BIT 64 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0 \ BIT 67 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \ BIT 70 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \ BIT 78 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \ BIT 81 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1) \ BIT 84 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0 \ BIT 90 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3) \ BIT 93 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4) \ BIT 97 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7) \ BIT 101 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \ BIT 105 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \ BIT 108 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0) \ BIT 111 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \ BIT 116 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \ BIT 119 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1) \ BIT 122 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0 \ BIT 127 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \ BIT 131 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) \ BIT 139 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \ BIT 142 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \ BIT 145 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0) \ BIT 148 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \ BIT 153 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \ BIT 156 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1) \ BIT 159 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0 \ BIT 164 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/}, \ BIT 166 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \ BIT 171 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/}, BIT 190 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0 \ BIT 199 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0 \ BIT 202 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5) \ BIT 220 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \ BIT 223 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0 \ BIT 226 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0 \ BIT 229 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1) \ BIT 235 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0) \ BIT 352 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CMDEEPROM_EN BIT(5) BIT 353 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CMDEEPROM_SEL BIT(4) BIT 354 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CMD9346CR_9356SEL BIT(4) BIT 359 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define GPIOSEL_ENBT BIT(5) BIT 369 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HSIMR_GPIO12_0_INT_EN BIT(0) BIT 370 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HSIMR_SPS_OCP_INT_EN BIT(5) BIT 371 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HSIMR_RON_INT_EN BIT(6) BIT 372 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HSIMR_PDN_INT_EN BIT(7) BIT 373 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HSIMR_GPIO9_INT_EN BIT(25) BIT 378 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HSISR_GPIO12_0_INT BIT(0) BIT 379 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HSISR_SPS_OCP_INT BIT(5) BIT 380 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HSISR_RON_INT_EN BIT(6) BIT 381 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HSISR_PDNINT BIT(7) BIT 382 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HSISR_GPIO9_INT BIT(25) BIT 395 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_1M BIT(0) BIT 396 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_2M BIT(1) BIT 397 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_5_5M BIT(2) BIT 398 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_11M BIT(3) BIT 399 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_6M BIT(4) BIT 400 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_9M BIT(5) BIT 401 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_12M BIT(6) BIT 402 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_18M BIT(7) BIT 403 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_24M BIT(8) BIT 404 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_36M BIT(9) BIT 405 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_48M BIT(10) BIT 406 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_54M BIT(11) BIT 407 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_MCS0 BIT(12) BIT 408 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_MCS1 BIT(13) BIT 409 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_MCS2 BIT(14) BIT 410 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_MCS3 BIT(15) BIT 411 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_MCS4 BIT(16) BIT 412 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_MCS5 BIT(17) BIT 413 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_MCS6 BIT(18) BIT 414 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RRSR_MCS7 BIT(19) BIT 415 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BRSR_ACKSHORTPMB BIT(23) BIT 446 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_1M BIT(0) BIT 447 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_2M BIT(1) BIT 448 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_5_5M BIT(2) BIT 449 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_11M BIT(3) BIT 450 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_6M BIT(4) BIT 451 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_9M BIT(5) BIT 452 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_12M BIT(6) BIT 453 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_18M BIT(7) BIT 454 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_24M BIT(8) BIT 455 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_36M BIT(9) BIT 456 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_48M BIT(10) BIT 457 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_54M BIT(11) BIT 458 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS0 BIT(12) BIT 459 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS1 BIT(13) BIT 460 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS2 BIT(14) BIT 461 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS3 BIT(15) BIT 462 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS4 BIT(16) BIT 463 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS5 BIT(17) BIT 464 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS6 BIT(18) BIT 465 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS7 BIT(19) BIT 466 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS8 BIT(20) BIT 467 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS9 BIT(21) BIT 468 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS10 BIT(22) BIT 469 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS11 BIT(23) BIT 470 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS12 BIT(24) BIT 471 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS13 BIT(25) BIT 472 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS14 BIT(26) BIT 473 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RATE_MCS15 BIT(27) BIT 485 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BW_OPMODE_20MHZ BIT(2) BIT 486 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BW_OPMODE_5G BIT(1) BIT 487 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BW_OPMODE_11J BIT(0) BIT 489 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CAM_VALID BIT(15) BIT 491 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CAM_USEDK BIT(5) BIT 502 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CAM_WRITE BIT(16) BIT 504 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CAM_POLLINIG BIT(31) BIT 510 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WOW_PMEN BIT(0) BIT 511 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WOW_WOMEN BIT(1) BIT 512 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WOW_MAGIC BIT(2) BIT 513 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WOW_UWF BIT(3) BIT 521 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_TXCCK BIT(30) BIT 523 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_PSTIMEOUT BIT(29) BIT 525 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_GTINT4 BIT(28) BIT 527 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_GTINT3 BIT(27) BIT 529 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_TBDER BIT(26) BIT 531 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_TBDOK BIT(25) BIT 533 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_TSF_BIT32_TOGGLE BIT(24) BIT 535 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDMAINT0 BIT(20) BIT 537 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDOK0 BIT(16) BIT 539 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_HSISR_IND_ON_INT BIT(15) BIT 541 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDMAINT_E BIT(14) BIT 543 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_ATIMEND BIT(12) BIT 545 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_HISR1_IND_INT BIT(11) BIT 547 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_C2HCMD BIT(10) BIT 549 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_CPWM2 BIT(9) BIT 551 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_CPWM BIT(8) BIT 553 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_HIGHDOK BIT(7) BIT 555 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_MGNTDOK BIT(6) BIT 557 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BKDOK BIT(5) BIT 559 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BEDOK BIT(4) BIT 561 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_VIDOK BIT(3) BIT 563 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_VODOK BIT(2) BIT 565 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_RDU BIT(1) BIT 567 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_ROK BIT(0) BIT 571 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDMAINT7 BIT(27) BIT 573 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDMAINT6 BIT(26) BIT 575 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDMAINT5 BIT(25) BIT 577 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDMAINT4 BIT(24) BIT 579 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDMAINT3 BIT(23) BIT 581 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDMAINT2 BIT(22) BIT 583 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDMAINT1 BIT(21) BIT 585 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDOK7 BIT(20) BIT 587 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDOK6 BIT(19) BIT 589 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDOK5 BIT(18) BIT 591 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDOK4 BIT(17) BIT 593 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDOK3 BIT(16) BIT 595 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDOK2 BIT(15) BIT 597 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_BCNDOK1 BIT(14) BIT 599 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_ATIMEND_E BIT(13) BIT 601 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_TXERR BIT(11) BIT 603 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_RXERR BIT(10) BIT 605 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_TXFOVW BIT(9) BIT 607 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IMR_RXFOVW BIT(8) BIT 695 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define STOPBECON BIT(6) BIT 696 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define STOPHIGHT BIT(5) BIT 697 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define STOPMGT BIT(4) BIT 698 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define STOPVO BIT(3) BIT 699 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define STOPVI BIT(2) BIT 700 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define STOPBE BIT(1) BIT 701 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define STOPBK BIT(0) BIT 703 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_APPFCS BIT(31) BIT 704 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_APP_MIC BIT(30) BIT 705 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_APP_ICV BIT(29) BIT 706 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_APP_PHYST_RXFF BIT(28) BIT 707 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_APP_BA_SSN BIT(27) BIT 708 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_ENMBID BIT(24) BIT 709 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_LSIGEN BIT(23) BIT 710 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_MFBEN BIT(22) BIT 711 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_HTC_LOC_CTRL BIT(14) BIT 712 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_AMF BIT(13) BIT 713 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_ACF BIT(12) BIT 714 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_ADF BIT(11) BIT 715 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_AICV BIT(9) BIT 716 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_ACRC32 BIT(8) BIT 717 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_CBSSID_BCN BIT(7) BIT 718 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_CBSSID_DATA BIT(6) BIT 720 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_APWRMGT BIT(5) BIT 721 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_ADD3 BIT(4) BIT 722 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_AB BIT(3) BIT 723 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_AM BIT(2) BIT 724 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_APM BIT(1) BIT 725 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RCR_AAP BIT(0) BIT 747 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SW18_FPWM BIT(3) BIT 749 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ISO_MD2PP BIT(0) BIT 750 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ISO_UA2USB BIT(1) BIT 751 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ISO_UD2CORE BIT(2) BIT 752 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ISO_PA2PCIE BIT(3) BIT 753 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ISO_PD2CORE BIT(4) BIT 754 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ISO_IP2MAC BIT(5) BIT 755 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ISO_DIOP BIT(6) BIT 756 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ISO_DIOE BIT(7) BIT 757 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ISO_EB2CORE BIT(8) BIT 758 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ISO_DIOR BIT(9) BIT 760 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PWC_EV25V BIT(14) BIT 761 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PWC_EV12V BIT(15) BIT 763 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_BBRSTB BIT(0) BIT 764 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_BB_GLB_RSTN BIT(1) BIT 765 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_USBA BIT(2) BIT 766 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_UPLL BIT(3) BIT 767 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_USBD BIT(4) BIT 768 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_DIO_PCIE BIT(5) BIT 769 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_PCIEA BIT(6) BIT 770 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_PPLL BIT(7) BIT 771 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_PCIED BIT(8) BIT 772 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_DIOE BIT(9) BIT 773 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_CPUEN BIT(10) BIT 774 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_DCORE BIT(11) BIT 775 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_ELDR BIT(12) BIT 776 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_DIO_RF BIT(13) BIT 777 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_HWPDN BIT(14) BIT 778 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FEN_MREGEN BIT(15) BIT 780 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PFM_LDALL BIT(0) BIT 781 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PFM_ALDN BIT(1) BIT 782 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PFM_LDKP BIT(2) BIT 783 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PFM_WOWL BIT(3) BIT 784 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ENPDN BIT(4) BIT 785 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PDN_PL BIT(5) BIT 786 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APFM_ONMAC BIT(8) BIT 787 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APFM_OFF BIT(9) BIT 788 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APFM_RSM BIT(10) BIT 789 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define AFSM_HSUS BIT(11) BIT 790 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define AFSM_PCIE BIT(12) BIT 791 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APDM_MAC BIT(13) BIT 792 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APDM_HOST BIT(14) BIT 793 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APDM_HPDN BIT(15) BIT 794 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RDY_MACON BIT(16) BIT 795 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SUS_HOST BIT(17) BIT 796 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ROP_ALD BIT(20) BIT 797 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ROP_PWR BIT(21) BIT 798 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ROP_SPS BIT(22) BIT 799 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SOP_MRST BIT(25) BIT 800 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SOP_FUSE BIT(26) BIT 801 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SOP_ABG BIT(27) BIT 802 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SOP_AMB BIT(28) BIT 803 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SOP_RCK BIT(29) BIT 804 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SOP_A8M BIT(30) BIT 805 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define XOP_BTCK BIT(31) BIT 807 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ANAD16V_EN BIT(0) BIT 808 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ANA8M BIT(1) BIT 809 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define MACSLP BIT(4) BIT 810 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LOADER_CLK_EN BIT(5) BIT 811 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define _80M_SSC_DIS BIT(7) BIT 812 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define _80M_SSC_EN_HO BIT(8) BIT 813 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PHY_SSC_RSTB BIT(9) BIT 814 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SEC_CLK_EN BIT(10) BIT 815 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define MAC_CLK_EN BIT(11) BIT 816 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SYS_CLK_EN BIT(12) BIT 817 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RING_CLK_EN BIT(13) BIT 819 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BOOT_FROM_EEPROM BIT(4) BIT 820 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define EEPROM_EN BIT(5) BIT 822 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define AFE_BGEN BIT(0) BIT 823 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define AFE_MBEN BIT(1) BIT 824 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define MAC_ID_EN BIT(7) BIT 826 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WLOCK_ALL BIT(0) BIT 827 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WLOCK_00 BIT(1) BIT 828 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WLOCK_04 BIT(2) BIT 829 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WLOCK_08 BIT(3) BIT 830 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WLOCK_40 BIT(4) BIT 831 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define R_DIS_PRST_0 BIT(5) BIT 832 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define R_DIS_PRST_1 BIT(6) BIT 833 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LOCK_ALL_EN BIT(7) BIT 835 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RF_EN BIT(0) BIT 836 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RF_RSTB BIT(1) BIT 837 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RF_SDMRSTB BIT(2) BIT 839 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LDA15_EN BIT(0) BIT 840 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LDA15_STBY BIT(1) BIT 841 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LDA15_OBUF BIT(2) BIT 842 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LDA15_REG_VOS BIT(3) BIT 845 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LDV12_EN BIT(0) BIT 846 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LDV12_SDBY BIT(1) BIT 847 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LPLDO_HSM BIT(2) BIT 848 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LPLDO_LSM_DIS BIT(3) BIT 851 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define XTAL_EN BIT(0) BIT 852 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define XTAL_BSEL BIT(1) BIT 855 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define XTAL_GATE_USB BIT(8) BIT 857 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define XTAL_GATE_AFE BIT(11) BIT 859 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define XTAL_RF_GATE BIT(14) BIT 861 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define XTAL_GATE_DIG BIT(17) BIT 863 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define XTAL_BT_GATE BIT(20) BIT 867 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CKDLY_AFE BIT(26) BIT 868 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CKDLY_USB BIT(27) BIT 869 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CKDLY_DIG BIT(28) BIT 870 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CKDLY_BT BIT(29) BIT 872 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APLL_EN BIT(0) BIT 873 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APLL_320_EN BIT(1) BIT 874 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APLL_FREF_SEL BIT(2) BIT 875 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APLL_EDGE_SEL BIT(3) BIT 876 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APLL_WDOGB BIT(4) BIT 877 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APLL_LPFEN BIT(5) BIT 887 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APLL_320EN BIT(14) BIT 888 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APLL_80EN BIT(15) BIT 889 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APLL_1MEN BIT(24) BIT 891 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ALD_EN BIT(18) BIT 892 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define EF_PD BIT(19) BIT 893 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define EF_FLAG BIT(31) BIT 895 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define EF_TRPT BIT(7) BIT 896 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LDOE25_EN BIT(31) BIT 898 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RSM_EN BIT(0) BIT 899 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TIMER_EN BIT(4) BIT 901 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TRSW0EN BIT(2) BIT 902 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TRSW1EN BIT(3) BIT 903 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define EROM_EN BIT(4) BIT 904 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ENBT BIT(5) BIT 905 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ENUART BIT(8) BIT 906 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define UART_910 BIT(9) BIT 907 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ENPMAC BIT(10) BIT 908 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SIC_SWRST BIT(11) BIT 909 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ENSIC BIT(12) BIT 910 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SIC_23 BIT(13) BIT 911 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ENHDP BIT(14) BIT 912 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SIC_LBK BIT(15) BIT 914 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LED0PL BIT(4) BIT 915 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LED1PL BIT(12) BIT 916 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LED0DIS BIT(7) BIT 918 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define MCUFWDL_EN BIT(0) BIT 919 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define MCUFWDL_RDY BIT(1) BIT 920 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define FWDL_CHKSUM_RPT BIT(2) BIT 921 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define MACINI_RDY BIT(3) BIT 922 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BBINI_RDY BIT(4) BIT 923 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RFINI_RDY BIT(5) BIT 924 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WINTINI_RDY BIT(6) BIT 925 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CPRST BIT(23) BIT 927 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define XCLK_VLD BIT(0) BIT 928 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACLK_VLD BIT(1) BIT 929 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define UCLK_VLD BIT(2) BIT 930 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PCLK_VLD BIT(3) BIT 931 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PCIRSTB BIT(4) BIT 932 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define V15_VLD BIT(5) BIT 933 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TRP_B15V_EN BIT(7) BIT 934 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SIC_IDLE BIT(8) BIT 935 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BD_MAC2 BIT(9) BIT 936 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BD_MAC1 BIT(10) BIT 937 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define IC_MACPHY_MODE BIT(11) BIT 938 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define VENDOR_ID BIT(19) BIT 939 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PAD_HWPD_IDN BIT(22) BIT 940 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TRP_VAUX_EN BIT(23) BIT 941 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TRP_BT_EN BIT(24) BIT 942 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BD_PKG_SEL BIT(25) BIT 943 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BD_HCI_SEL BIT(26) BIT 944 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TYPE_ID BIT(27) BIT 951 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HCI_TXDMA_EN BIT(0) BIT 952 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HCI_RXDMA_EN BIT(1) BIT 953 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TXDMA_EN BIT(2) BIT 954 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RXDMA_EN BIT(3) BIT 955 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PROTOCOL_EN BIT(4) BIT 956 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SCHEDULE_EN BIT(5) BIT 957 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define MACTXEN BIT(6) BIT 958 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define MACRXEN BIT(7) BIT 959 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ENSWBCN BIT(8) BIT 960 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ENSEC BIT(9) BIT 990 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RXDMA_ARBBW_EN BIT(0) BIT 991 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RXSHFT_EN BIT(1) BIT 992 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RXDMA_AGG_EN BIT(2) BIT 993 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define QS_VO_QUEUE BIT(8) BIT 994 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define QS_VI_QUEUE BIT(9) BIT 995 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define QS_BE_QUEUE BIT(10) BIT 996 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define QS_BK_QUEUE BIT(11) BIT 997 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define QS_MANAGER_QUEUE BIT(12) BIT 998 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define QS_HIGH_QUEUE BIT(13) BIT 1000 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HQSEL_VOQ BIT(0) BIT 1001 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HQSEL_VIQ BIT(1) BIT 1002 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HQSEL_BEQ BIT(2) BIT 1003 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HQSEL_BKQ BIT(3) BIT 1004 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HQSEL_MGTQ BIT(4) BIT 1005 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HQSEL_HIQ BIT(5) BIT 1027 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) BIT 1028 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BB_WRITE_EN BIT(30) BIT 1029 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BB_READ_EN BIT(31) BIT 1036 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HPQ_PUBLIC_DIS BIT(24) BIT 1037 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LPQ_PUBLIC_DIS BIT(25) BIT 1038 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LD_RQPN BIT(31) BIT 1040 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BCN_VALID BIT(16) BIT 1047 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define DROP_DATA_EN BIT(9) BIT 1049 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define EN_AMPDU_RTY_NEW BIT(7) BIT 1066 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define USE_SHORT_G1 BIT(20) BIT 1121 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define DIS_EDCA_CNT_DWN BIT(11) BIT 1123 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define EN_MBSSID BIT(1) BIT 1124 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define EN_TXBCN_RPT BIT(2) BIT 1125 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define EN_BCN_FUNCTION BIT(3) BIT 1127 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TSFTR_RST BIT(0) BIT 1128 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TSFTR1_RST BIT(1) BIT 1130 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define STOP_BCNQ BIT(6) BIT 1132 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) BIT 1133 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define DIS_TSF_UDT0_TEST_CHIP BIT(5) BIT 1135 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACMHW_HWEN BIT(0) BIT 1136 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACMHW_BEQEN BIT(1) BIT 1137 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACMHW_VIQEN BIT(2) BIT 1138 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACMHW_VOQEN BIT(3) BIT 1139 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACMHW_BEQSTATUS BIT(4) BIT 1140 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACMHW_VIQSTATUS BIT(5) BIT 1141 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACMHW_VOQSTATUS BIT(6) BIT 1143 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APSDOFF BIT(6) BIT 1144 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APSDOFF_STATUS BIT(7) BIT 1146 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BW_20MHZ BIT(2) BIT 1152 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define TSFRST BIT(0) BIT 1153 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define DIS_GCLK BIT(1) BIT 1154 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PAD_SEL BIT(2) BIT 1155 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PWR_ST BIT(6) BIT 1156 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define PWRBIT_OW_EN BIT(7) BIT 1157 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACRC BIT(8) BIT 1158 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CFENDFORM BIT(9) BIT 1159 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ICV BIT(10) BIT 1161 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define AAP BIT(0) BIT 1162 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APM BIT(1) BIT 1163 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define AM BIT(2) BIT 1164 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define AB BIT(3) BIT 1165 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ADD3 BIT(4) BIT 1166 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APWRMGT BIT(5) BIT 1167 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CBSSID BIT(6) BIT 1168 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CBSSID_DATA BIT(6) BIT 1169 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define CBSSID_BCN BIT(7) BIT 1170 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACRC32 BIT(8) BIT 1171 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define AICV BIT(9) BIT 1172 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ADF BIT(11) BIT 1173 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ACF BIT(12) BIT 1174 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define AMF BIT(13) BIT 1175 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HTC_LOC_CTRL BIT(14) BIT 1176 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define UC_DATA_EN BIT(16) BIT 1177 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define BM_DATA_EN BIT(17) BIT 1178 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define MFBEN BIT(22) BIT 1179 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define LSIGEN BIT(23) BIT 1180 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define ENMBID BIT(24) BIT 1181 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APP_BASSN BIT(27) BIT 1182 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APP_PHYSTS BIT(28) BIT 1183 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APP_ICV BIT(29) BIT 1184 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APP_MIC BIT(30) BIT 1185 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define APP_FCS BIT(31) BIT 1206 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define RXERR_RPT_RST BIT(27) BIT 1209 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SCR_TXUSEDK BIT(0) BIT 1210 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SCR_RXUSEDK BIT(1) BIT 1211 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SCR_TXENCENABLE BIT(2) BIT 1212 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SCR_RXDECENABLE BIT(3) BIT 1213 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SCR_SKBYA2 BIT(4) BIT 1214 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SCR_NOSKMC BIT(5) BIT 1215 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SCR_TXBCUSEDK BIT(6) BIT 1216 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define SCR_RXBCUSEDK BIT(7) BIT 1220 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define USB_SPEED_MASK BIT(5) BIT 1228 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define USB_AGG_EN BIT(3) BIT 1245 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) BIT 2238 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) BIT 2239 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) BIT 2240 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HAL92C_WOL_DISASSOC_EVENT BIT(2) BIT 2241 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HAL92C_WOL_DEAUTH_EVENT BIT(3) BIT 2242 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4) BIT 2244 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WOL_REASON_PTK_UPDATE BIT(0) BIT 2245 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WOL_REASON_GTK_UPDATE BIT(1) BIT 2246 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WOL_REASON_DISASSOC BIT(2) BIT 2247 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WOL_REASON_DEAUTH BIT(3) BIT 2248 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/reg.h #define WOL_REASON_FW_DISCONNECT BIT(4) BIT 21 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/rf.c 0xfffff3ff) | BIT(10) | BIT(11)); BIT 27 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/rf.c 0xfffff3ff) | BIT(10)); BIT 75 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c rtlpci->transmit_config = CFENDFORM | BIT(15); BIT 67 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c BIT(9)); BIT 405 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c wake_match = BIT(2); BIT 407 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c wake_match = BIT(1); BIT 409 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c wake_match = BIT(0); BIT 830 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4)); BIT 833 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c BIT(0) << (hw_queue)); BIT 29 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(24)); BIT 34 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(25)); BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(26)); BIT 44 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(27)); BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(28)); BIT 54 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 59 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc), BIT(31)); BIT 79 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 1, __val, BIT(20)); BIT 94 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 2, __val, BIT(12)); BIT 99 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 2, __val, BIT(13)); BIT 104 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 2, __val, BIT(17)); BIT 114 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 2, __val, BIT(24)); BIT 119 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 2, __val, BIT(25)); BIT 129 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 3, __val, BIT(31)); BIT 139 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 4, __val, BIT(6)); BIT 144 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 4, __val, BIT(8)); BIT 149 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 4, __val, BIT(10)); BIT 154 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 4, __val, BIT(11)); BIT 159 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 4, __val, BIT(12)); BIT 164 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 4, __val, BIT(13)); BIT 179 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 4, __val, BIT(25)); BIT 184 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 4, __val, BIT(26)); BIT 189 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 4, __val, BIT(27)); BIT 209 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 5, __val, BIT(6)); BIT 229 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc + 7, __val, BIT(29)); BIT 264 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc), BIT(14)); BIT 269 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc), BIT(15)); BIT 284 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc), BIT(23)); BIT 294 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc), BIT(26)); BIT 299 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc), BIT(27)); BIT 304 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc), BIT(28)); BIT 309 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc), BIT(29)); BIT 314 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc), BIT(30)); BIT 319 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc), BIT(31)); BIT 329 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(30)); BIT 334 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 344 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 1), BIT(14)); BIT 349 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 1), BIT(15)); BIT 364 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 1), BIT(24)); BIT 369 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 1), BIT(25)); BIT 374 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 1), BIT(26)); BIT 379 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 1), BIT(27)); BIT 389 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 1), BIT(30)); BIT 394 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 1), BIT(31)); BIT 414 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(6)); BIT 419 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(7)); BIT 424 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(8)); BIT 429 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(9)); BIT 434 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(10)); BIT 439 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(11)); BIT 454 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(29)); BIT 459 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(30)); BIT 464 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(31)); BIT 228 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); BIT 987 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c BIT(31), value32); BIT 991 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c BIT(29), value32); BIT 1000 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c BIT(31) | BIT(29), 0x00); BIT 1085 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c BIT(27), value32); BIT 1089 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c BIT(25), value32); BIT 1099 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c BIT(27) | BIT(25), 0x00); BIT 1209 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c MASKDWORD) & BIT(3)) >> 3; BIT 1244 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0); BIT 1250 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); BIT 1251 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); BIT 1255 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), BIT 1260 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); BIT 1710 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c tmp1byte |= BIT(5); BIT 12 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.h #define HAL_DM_DIG_DISABLE BIT(0) BIT 13 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.h #define HAL_DM_HIPWR_DISABLE BIT(1) BIT 56 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.h #define DYNAMIC_FUNC_DIG BIT(0) BIT 57 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.h #define DYNAMIC_FUNC_HP BIT(1) BIT 58 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.h #define DYNAMIC_FUNC_SS BIT(2) /*Tx Power Tracking*/ BIT 59 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.h #define DYNAMIC_FUNC_BT BIT(3) BIT 60 drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.h #define DYNAMIC_FUNC_ANT_DIV BIT(4) BIT 178 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.c if (((val_hmetfr >> boxnum) & BIT(0)) == 0 && val_mcutst_1 == 0) BIT 297 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.c boxcontent[0] &= ~(BIT(7)); BIT 307 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.c boxcontent[0] &= ~(BIT(7)); BIT 317 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.c boxcontent[0] &= ~(BIT(7)); BIT 327 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.c boxcontent[0] |= (BIT(7)); BIT 344 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.c boxcontent[0] |= (BIT(7)); BIT 413 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.c while (u1b_tmp & BIT(2)) { BIT 739 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.c BIT(4)); BIT 13 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.h #define NORMAL_CHIP BIT(4) BIT 20 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.h #define CUT_VERSION_MASK (BIT(6)|BIT(7)) BIT 21 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.h #define CHIP_VENDOR_UMC BIT(5) BIT 22 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.h #define CHIP_VENDOR_UMC_B_CUT BIT(6) /* Chip version for ECO */ BIT 24 drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.h #define RF_TYPE_MASK (BIT(0)|BIT(1)) BIT 105 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c BIT(8)); BIT 108 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c BIT(8)); BIT 936 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c if (!(reg_eac & BIT(28)) && BIT 943 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c if (!(reg_eac & BIT(27)) && BIT 964 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c if (!(reg_eac & BIT(31)) && BIT 970 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c if (!(reg_eac & BIT(30)) && BIT 994 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), BIT 1004 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), BIT 1034 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), BIT 1044 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), BIT 1127 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c (u8)(macbackup[i] & (~BIT(3)))); BIT 1128 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & (~BIT(5)))); BIT 1237 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c BIT(8)); BIT 1342 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01); BIT 1343 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); BIT 1348 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c BIT(5) | BIT(6), 0x1); BIT 1351 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c BIT(5) | BIT(6), 0x2); BIT 20 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/def.h #define CHIP_VER_B BIT(4) BIT 23 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/def.h #define RF_TYPE_1T2R BIT(1) BIT 24 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/def.h #define CHIP_92C_BITMASK BIT(0) BIT 25 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/def.h #define CHIP_UNKNOWN BIT(7) BIT 7 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/dm.h #define HAL_DM_DIG_DISABLE BIT(0) BIT 8 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/dm.h #define HAL_DM_HIPWR_DISABLE BIT(1) BIT 41 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); BIT 44 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c tmp1byte &= ~(BIT(0)); BIT 54 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); BIT 57 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c tmp1byte |= BIT(0); BIT 63 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); BIT 68 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); BIT 372 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); BIT 392 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c if (rpwm_val & BIT(7)) { BIT 396 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c *val | BIT(7)); BIT 426 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c (tmp_regcr | BIT(0))); BIT 428 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 429 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 434 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c if (tmp_reg422 & BIT(6)) BIT 437 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c tmp_reg422 & (~BIT(6))); BIT 441 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 442 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 451 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c (tmp_regcr & ~(BIT(0)))); BIT 476 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 483 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 683 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); BIT 696 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c while ((bytetmp & BIT(0)) && retry < 1000) { BIT 765 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); BIT 769 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c } while ((retry < 200) && (bytetmp & BIT(7))); BIT 986 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); BIT 1014 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c if (!(tmp_u1b & BIT(0))) { BIT 1019 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c if (!(tmp_u1b & BIT(1)) && is92c) { BIT 1024 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c if (!(tmp_u1b & BIT(4))) { BIT 1058 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c ((((value32 & CHIP_VER_RTL_MASK) == BIT(12)) BIT 1221 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 1224 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 1308 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) BIT 1575 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) BIT 1578 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) BIT 1738 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c if (tmp_u1b & BIT(4)) { BIT 1745 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c if (tmp_u1b & BIT(5)) { BIT 2028 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c REG_MAC_PINMUX_CFG)&~(BIT(3))); BIT 2031 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; BIT 32 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.c REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5) | BIT(6)); BIT 35 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.c rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5)); BIT 62 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.c (ledcfg | BIT(1) | BIT(5) | BIT(6))); BIT 65 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.c (ledcfg | BIT(3) | BIT(5) | BIT(6))); BIT 69 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.c rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3))); BIT 79 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c regval | BIT(13) | BIT(0) | BIT(1)); BIT 88 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); BIT 329 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); BIT 338 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0); BIT 340 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), BIT 334 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CMDEEPROM_EN BIT(5) BIT 335 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CMDEEPROM_SEL BIT(4) BIT 336 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CMD9346CR_9356SEL BIT(4) BIT 341 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define GPIOSEL_ENBT BIT(5) BIT 360 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_1M BIT(0) BIT 361 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_2M BIT(1) BIT 362 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_5_5M BIT(2) BIT 363 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_11M BIT(3) BIT 364 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_6M BIT(4) BIT 365 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_9M BIT(5) BIT 366 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_12M BIT(6) BIT 367 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_18M BIT(7) BIT 368 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_24M BIT(8) BIT 369 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_36M BIT(9) BIT 370 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_48M BIT(10) BIT 371 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_54M BIT(11) BIT 372 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_MCS0 BIT(12) BIT 373 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_MCS1 BIT(13) BIT 374 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_MCS2 BIT(14) BIT 375 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_MCS3 BIT(15) BIT 376 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_MCS4 BIT(16) BIT 377 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_MCS5 BIT(17) BIT 378 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_MCS6 BIT(18) BIT 379 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RRSR_MCS7 BIT(19) BIT 380 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BRSR_ACKSHORTPMB BIT(23) BIT 411 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_1M BIT(0) BIT 412 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_2M BIT(1) BIT 413 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_5_5M BIT(2) BIT 414 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_11M BIT(3) BIT 415 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_6M BIT(4) BIT 416 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_9M BIT(5) BIT 417 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_12M BIT(6) BIT 418 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_18M BIT(7) BIT 419 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_24M BIT(8) BIT 420 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_36M BIT(9) BIT 421 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_48M BIT(10) BIT 422 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_54M BIT(11) BIT 423 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS0 BIT(12) BIT 424 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS1 BIT(13) BIT 425 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS2 BIT(14) BIT 426 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS3 BIT(15) BIT 427 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS4 BIT(16) BIT 428 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS5 BIT(17) BIT 429 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS6 BIT(18) BIT 430 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS7 BIT(19) BIT 431 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS8 BIT(20) BIT 432 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS9 BIT(21) BIT 433 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS10 BIT(22) BIT 434 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS11 BIT(23) BIT 435 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS12 BIT(24) BIT 436 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS13 BIT(25) BIT 437 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS14 BIT(26) BIT 438 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RATE_MCS15 BIT(27) BIT 450 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BW_OPMODE_20MHZ BIT(2) BIT 451 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BW_OPMODE_5G BIT(1) BIT 452 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BW_OPMODE_11J BIT(0) BIT 454 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CAM_VALID BIT(15) BIT 456 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CAM_USEDK BIT(5) BIT 467 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CAM_WRITE BIT(16) BIT 469 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CAM_POLLINIG BIT(31) BIT 475 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WOW_PMEN BIT(0) BIT 476 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WOW_WOMEN BIT(1) BIT 477 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WOW_MAGIC BIT(2) BIT 478 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WOW_UWF BIT(3) BIT 481 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDMAINT6 BIT(31) BIT 482 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDMAINT5 BIT(30) BIT 483 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDMAINT4 BIT(29) BIT 484 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDMAINT3 BIT(28) BIT 485 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDMAINT2 BIT(27) BIT 486 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDMAINT1 BIT(26) BIT 487 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDOK8 BIT(25) BIT 488 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDOK7 BIT(24) BIT 489 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDOK6 BIT(23) BIT 490 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDOK5 BIT(22) BIT 491 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDOK4 BIT(21) BIT 492 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDOK3 BIT(20) BIT 493 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDOK2 BIT(19) BIT 494 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNDOK1 BIT(18) BIT 495 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_TIMEOUT2 BIT(17) BIT 496 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_TIMEOUT1 BIT(16) BIT 497 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_TXFOVW BIT(15) BIT 498 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_PSTIMEOUT BIT(14) BIT 499 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BCNINT BIT(13) BIT 500 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_RXFOVW BIT(12) BIT 501 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_RDU BIT(11) BIT 502 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_ATIMEND BIT(10) BIT 503 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BDOK BIT(9) BIT 504 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_HIGHDOK BIT(8) BIT 505 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_TBDOK BIT(7) BIT 506 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_MGNTDOK BIT(6) BIT 507 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_TBDER BIT(5) BIT 508 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BKDOK BIT(4) BIT 509 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_BEDOK BIT(3) BIT 510 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_VIDOK BIT(2) BIT 511 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_VODOK BIT(1) BIT 512 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_ROK BIT(0) BIT 514 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_TXERR BIT(11) BIT 515 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_RXERR BIT(10) BIT 516 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_C2HCMD BIT(9) BIT 517 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_CPWM BIT(8) BIT 518 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_OCPINT BIT(1) BIT 519 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IMR_WLANOFF BIT(0) BIT 618 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define STOPBECON BIT(6) BIT 619 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define STOPHIGHT BIT(5) BIT 620 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define STOPMGT BIT(4) BIT 621 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define STOPVO BIT(3) BIT 622 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define STOPVI BIT(2) BIT 623 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define STOPBE BIT(1) BIT 624 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define STOPBK BIT(0) BIT 626 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_APPFCS BIT(31) BIT 627 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_APP_FCS BIT(31) BIT 628 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_APP_MIC BIT(30) BIT 629 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_APP_ICV BIT(29) BIT 630 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_APP_PHYSTS BIT(28) BIT 631 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_APP_PHYST_RXFF BIT(28) BIT 632 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_APP_BA_SSN BIT(27) BIT 633 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_ENMBID BIT(24) BIT 634 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_LSIGEN BIT(23) BIT 635 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_MFBEN BIT(22) BIT 636 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_HTC_LOC_CTRL BIT(14) BIT 637 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_AMF BIT(13) BIT 638 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_ACF BIT(12) BIT 639 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_ADF BIT(11) BIT 640 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_AICV BIT(9) BIT 641 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_ACRC32 BIT(8) BIT 642 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_CBSSID_BCN BIT(7) BIT 643 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_CBSSID_DATA BIT(6) BIT 645 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_APWRMGT BIT(5) BIT 646 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_ADD3 BIT(4) BIT 647 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_AB BIT(3) BIT 648 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_AM BIT(2) BIT 649 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_APM BIT(1) BIT 650 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RCR_AAP BIT(0) BIT 666 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SW18_FPWM BIT(3) BIT 668 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ISO_MD2PP BIT(0) BIT 669 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ISO_UA2USB BIT(1) BIT 670 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ISO_UD2CORE BIT(2) BIT 671 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ISO_PA2PCIE BIT(3) BIT 672 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ISO_PD2CORE BIT(4) BIT 673 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ISO_IP2MAC BIT(5) BIT 674 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ISO_DIOP BIT(6) BIT 675 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ISO_DIOE BIT(7) BIT 676 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ISO_EB2CORE BIT(8) BIT 677 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ISO_DIOR BIT(9) BIT 679 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PWC_EV25V BIT(14) BIT 680 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PWC_EV12V BIT(15) BIT 682 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_BBRSTB BIT(0) BIT 683 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_BB_GLB_RSTN BIT(1) BIT 684 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_USBA BIT(2) BIT 685 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_UPLL BIT(3) BIT 686 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_USBD BIT(4) BIT 687 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_DIO_PCIE BIT(5) BIT 688 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_PCIEA BIT(6) BIT 689 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_PPLL BIT(7) BIT 690 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_PCIED BIT(8) BIT 691 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_DIOE BIT(9) BIT 692 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_CPUEN BIT(10) BIT 693 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_DCORE BIT(11) BIT 694 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_ELDR BIT(12) BIT 695 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_DIO_RF BIT(13) BIT 696 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_HWPDN BIT(14) BIT 697 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FEN_MREGEN BIT(15) BIT 699 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PFM_LDALL BIT(0) BIT 700 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PFM_ALDN BIT(1) BIT 701 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PFM_LDKP BIT(2) BIT 702 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PFM_WOWL BIT(3) BIT 703 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ENPDN BIT(4) BIT 704 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PDN_PL BIT(5) BIT 705 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APFM_ONMAC BIT(8) BIT 706 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APFM_OFF BIT(9) BIT 707 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APFM_RSM BIT(10) BIT 708 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define AFSM_HSUS BIT(11) BIT 709 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define AFSM_PCIE BIT(12) BIT 710 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APDM_MAC BIT(13) BIT 711 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APDM_HOST BIT(14) BIT 712 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APDM_HPDN BIT(15) BIT 713 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RDY_MACON BIT(16) BIT 714 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SUS_HOST BIT(17) BIT 715 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ROP_ALD BIT(20) BIT 716 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ROP_PWR BIT(21) BIT 717 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ROP_SPS BIT(22) BIT 718 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SOP_MRST BIT(25) BIT 719 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SOP_FUSE BIT(26) BIT 720 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SOP_ABG BIT(27) BIT 721 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SOP_AMB BIT(28) BIT 722 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SOP_RCK BIT(29) BIT 723 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SOP_A8M BIT(30) BIT 724 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define XOP_BTCK BIT(31) BIT 726 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ANAD16V_EN BIT(0) BIT 727 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ANA8M BIT(1) BIT 728 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define MACSLP BIT(4) BIT 729 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LOADER_CLK_EN BIT(5) BIT 730 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define _80M_SSC_DIS BIT(7) BIT 731 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define _80M_SSC_EN_HO BIT(8) BIT 732 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PHY_SSC_RSTB BIT(9) BIT 733 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SEC_CLK_EN BIT(10) BIT 734 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define MAC_CLK_EN BIT(11) BIT 735 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SYS_CLK_EN BIT(12) BIT 736 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RING_CLK_EN BIT(13) BIT 738 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BOOT_FROM_EEPROM BIT(4) BIT 739 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define EEPROM_EN BIT(5) BIT 741 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define AFE_BGEN BIT(0) BIT 742 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define AFE_MBEN BIT(1) BIT 743 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define MAC_ID_EN BIT(7) BIT 745 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WLOCK_ALL BIT(0) BIT 746 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WLOCK_00 BIT(1) BIT 747 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WLOCK_04 BIT(2) BIT 748 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WLOCK_08 BIT(3) BIT 749 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WLOCK_40 BIT(4) BIT 750 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define R_DIS_PRST_0 BIT(5) BIT 751 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define R_DIS_PRST_1 BIT(6) BIT 752 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LOCK_ALL_EN BIT(7) BIT 754 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RF_EN BIT(0) BIT 755 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RF_RSTB BIT(1) BIT 756 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RF_SDMRSTB BIT(2) BIT 758 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LDA15_EN BIT(0) BIT 759 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LDA15_STBY BIT(1) BIT 760 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LDA15_OBUF BIT(2) BIT 761 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LDA15_REG_VOS BIT(3) BIT 764 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LDV12_EN BIT(0) BIT 765 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LDV12_SDBY BIT(1) BIT 766 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LPLDO_HSM BIT(2) BIT 767 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LPLDO_LSM_DIS BIT(3) BIT 770 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define XTAL_EN BIT(0) BIT 771 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define XTAL_BSEL BIT(1) BIT 774 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define XTAL_GATE_USB BIT(8) BIT 776 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define XTAL_GATE_AFE BIT(11) BIT 778 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define XTAL_RF_GATE BIT(14) BIT 780 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define XTAL_GATE_DIG BIT(17) BIT 782 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define XTAL_BT_GATE BIT(20) BIT 786 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CKDLY_AFE BIT(26) BIT 787 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CKDLY_USB BIT(27) BIT 788 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CKDLY_DIG BIT(28) BIT 789 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CKDLY_BT BIT(29) BIT 791 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APLL_EN BIT(0) BIT 792 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APLL_320_EN BIT(1) BIT 793 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APLL_FREF_SEL BIT(2) BIT 794 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APLL_EDGE_SEL BIT(3) BIT 795 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APLL_WDOGB BIT(4) BIT 796 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APLL_LPFEN BIT(5) BIT 806 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APLL_320EN BIT(14) BIT 807 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APLL_80EN BIT(15) BIT 808 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APLL_1MEN BIT(24) BIT 810 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ALD_EN BIT(18) BIT 811 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define EF_PD BIT(19) BIT 812 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define EF_FLAG BIT(31) BIT 814 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define EF_TRPT BIT(7) BIT 815 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LDOE25_EN BIT(31) BIT 817 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RSM_EN BIT(0) BIT 818 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TIMER_EN BIT(4) BIT 820 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TRSW0EN BIT(2) BIT 821 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TRSW1EN BIT(3) BIT 822 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define EROM_EN BIT(4) BIT 823 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ENBT BIT(5) BIT 824 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ENUART BIT(8) BIT 825 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define UART_910 BIT(9) BIT 826 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ENPMAC BIT(10) BIT 827 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SIC_SWRST BIT(11) BIT 828 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ENSIC BIT(12) BIT 829 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SIC_23 BIT(13) BIT 830 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ENHDP BIT(14) BIT 831 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SIC_LBK BIT(15) BIT 833 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LED0PL BIT(4) BIT 834 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LED1PL BIT(12) BIT 835 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LED0DIS BIT(7) BIT 837 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define MCUFWDL_EN BIT(0) BIT 838 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define MCUFWDL_RDY BIT(1) BIT 839 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define FWDL_CHKSUM_RPT BIT(2) BIT 840 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define MACINI_RDY BIT(3) BIT 841 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BBINI_RDY BIT(4) BIT 842 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RFINI_RDY BIT(5) BIT 843 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WINTINI_RDY BIT(6) BIT 844 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CPRST BIT(23) BIT 846 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define XCLK_VLD BIT(0) BIT 847 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACLK_VLD BIT(1) BIT 848 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define UCLK_VLD BIT(2) BIT 849 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PCLK_VLD BIT(3) BIT 850 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PCIRSTB BIT(4) BIT 851 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define V15_VLD BIT(5) BIT 852 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TRP_B15V_EN BIT(7) BIT 853 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SIC_IDLE BIT(8) BIT 854 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BD_MAC2 BIT(9) BIT 855 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BD_MAC1 BIT(10) BIT 856 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define IC_MACPHY_MODE BIT(11) BIT 857 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BT_FUNC BIT(16) BIT 858 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define VENDOR_ID BIT(19) BIT 859 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PAD_HWPD_IDN BIT(22) BIT 860 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TRP_VAUX_EN BIT(23) BIT 861 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TRP_BT_EN BIT(24) BIT 862 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BD_PKG_SEL BIT(25) BIT 863 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BD_HCI_SEL BIT(26) BIT 864 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TYPE_ID BIT(27) BIT 865 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) BIT 872 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HCI_TXDMA_EN BIT(0) BIT 873 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HCI_RXDMA_EN BIT(1) BIT 874 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TXDMA_EN BIT(2) BIT 875 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RXDMA_EN BIT(3) BIT 876 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PROTOCOL_EN BIT(4) BIT 877 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SCHEDULE_EN BIT(5) BIT 878 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define MACTXEN BIT(6) BIT 879 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define MACRXEN BIT(7) BIT 880 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ENSWBCN BIT(8) BIT 881 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ENSEC BIT(9) BIT 911 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RXDMA_ARBBW_EN BIT(0) BIT 912 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RXSHFT_EN BIT(1) BIT 913 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RXDMA_AGG_EN BIT(2) BIT 914 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define QS_VO_QUEUE BIT(8) BIT 915 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define QS_VI_QUEUE BIT(9) BIT 916 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define QS_BE_QUEUE BIT(10) BIT 917 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define QS_BK_QUEUE BIT(11) BIT 918 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define QS_MANAGER_QUEUE BIT(12) BIT 919 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define QS_HIGH_QUEUE BIT(13) BIT 921 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HQSEL_VOQ BIT(0) BIT 922 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HQSEL_VIQ BIT(1) BIT 923 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HQSEL_BEQ BIT(2) BIT 924 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HQSEL_BKQ BIT(3) BIT 925 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HQSEL_MGTQ BIT(4) BIT 926 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HQSEL_HIQ BIT(5) BIT 948 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) BIT 949 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BB_WRITE_EN BIT(30) BIT 950 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BB_READ_EN BIT(31) BIT 957 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HPQ_PUBLIC_DIS BIT(24) BIT 958 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LPQ_PUBLIC_DIS BIT(25) BIT 959 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LD_RQPN BIT(31) BIT 961 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BCN_VALID BIT(16) BIT 968 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define DROP_DATA_EN BIT(9) BIT 970 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define EN_AMPDU_RTY_NEW BIT(7) BIT 987 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define USE_SHORT_G1 BIT(20) BIT 1043 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define DIS_EDCA_CNT_DWN BIT(11) BIT 1045 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define EN_MBSSID BIT(1) BIT 1046 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define EN_TXBCN_RPT BIT(2) BIT 1047 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define EN_BCN_FUNCTION BIT(3) BIT 1049 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TSFTR_RST BIT(0) BIT 1050 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TSFTR1_RST BIT(1) BIT 1052 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define STOP_BCNQ BIT(6) BIT 1054 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) BIT 1055 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define DIS_TSF_UDT0_TEST_CHIP BIT(5) BIT 1057 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACMHW_HWEN BIT(0) BIT 1058 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACMHW_BEQEN BIT(1) BIT 1059 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACMHW_VIQEN BIT(2) BIT 1060 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACMHW_VOQEN BIT(3) BIT 1061 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACMHW_BEQSTATUS BIT(4) BIT 1062 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACMHW_VIQSTATUS BIT(5) BIT 1063 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACMHW_VOQSTATUS BIT(6) BIT 1065 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APSDOFF BIT(6) BIT 1066 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APSDOFF_STATUS BIT(7) BIT 1068 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BW_20MHZ BIT(2) BIT 1074 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define TSFRST BIT(0) BIT 1075 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define DIS_GCLK BIT(1) BIT 1076 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PAD_SEL BIT(2) BIT 1077 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PWR_ST BIT(6) BIT 1078 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define PWRBIT_OW_EN BIT(7) BIT 1079 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACRC BIT(8) BIT 1080 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CFENDFORM BIT(9) BIT 1081 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ICV BIT(10) BIT 1083 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define AAP BIT(0) BIT 1084 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APM BIT(1) BIT 1085 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define AM BIT(2) BIT 1086 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define AB BIT(3) BIT 1087 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ADD3 BIT(4) BIT 1088 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APWRMGT BIT(5) BIT 1089 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CBSSID BIT(6) BIT 1090 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CBSSID_DATA BIT(6) BIT 1091 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define CBSSID_BCN BIT(7) BIT 1092 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACRC32 BIT(8) BIT 1093 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define AICV BIT(9) BIT 1094 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ADF BIT(11) BIT 1095 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ACF BIT(12) BIT 1096 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define AMF BIT(13) BIT 1097 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HTC_LOC_CTRL BIT(14) BIT 1098 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define UC_DATA_EN BIT(16) BIT 1099 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define BM_DATA_EN BIT(17) BIT 1100 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define MFBEN BIT(22) BIT 1101 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define LSIGEN BIT(23) BIT 1102 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define ENMBID BIT(24) BIT 1103 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APP_BASSN BIT(27) BIT 1104 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APP_PHYSTS BIT(28) BIT 1105 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APP_ICV BIT(29) BIT 1106 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APP_MIC BIT(30) BIT 1107 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define APP_FCS BIT(31) BIT 1128 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define RXERR_RPT_RST BIT(27) BIT 1131 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SCR_TXUSEDK BIT(0) BIT 1132 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SCR_RXUSEDK BIT(1) BIT 1133 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SCR_TXENCENABLE BIT(2) BIT 1134 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SCR_RXDECENABLE BIT(3) BIT 1135 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SCR_SKBYA2 BIT(4) BIT 1136 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SCR_NOSKMC BIT(5) BIT 1137 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SCR_TXBCUSEDK BIT(6) BIT 1138 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define SCR_RXBCUSEDK BIT(7) BIT 1142 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define USB_SPEED_MASK BIT(5) BIT 1150 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define USB_AGG_EN BIT(3) BIT 1165 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define WL_HWPDN_EN BIT(0) BIT 1167 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) BIT 82 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); BIT 98 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c BIT(9)); BIT 729 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4)); BIT 732 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c BIT(0) << (hw_queue)); BIT 31 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits(__pdesc, __val, BIT(24)); BIT 36 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits(__pdesc, __val, BIT(25)); BIT 41 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits(__pdesc, __val, BIT(26)); BIT 46 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits(__pdesc, __val, BIT(27)); BIT 51 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits(__pdesc, __val, BIT(28)); BIT 56 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 61 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*(__pdesc), BIT(31)); BIT 71 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 1), __val, BIT(5)); BIT 76 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 1), __val, BIT(7)); BIT 96 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 2), __val, BIT(17)); BIT 121 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(6)); BIT 126 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(7)); BIT 131 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(8)); BIT 136 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(10)); BIT 141 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(11)); BIT 146 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(12)); BIT 151 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(13)); BIT 161 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(25)); BIT 166 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(26)); BIT 171 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(27)); BIT 191 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits((__pdesc + 5), __val, BIT(6)); BIT 236 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*(__pdesc), BIT(14)); BIT 241 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*(__pdesc), BIT(15)); BIT 256 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*(__pdesc), BIT(26)); BIT 261 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*(__pdesc), BIT(27)); BIT 266 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*(__pdesc), BIT(31)); BIT 276 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits(__pdesc, __val, BIT(30)); BIT 281 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 286 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*((__pdesc + 1)), BIT(14)); BIT 291 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*((__pdesc + 1)), BIT(15)); BIT 301 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*((__pdesc + 3)), BIT(6)); BIT 306 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*((__pdesc + 3)), BIT(8)); BIT 311 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h return le32_get_bits(*((__pdesc + 3)), BIT(9)); BIT 9 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/def.h #define NORMAL_CHIP BIT(4) BIT 10 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/def.h #define CHIP_VENDOR_UMC BIT(5) BIT 11 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/def.h #define CHIP_VENDOR_UMC_B_CUT BIT(6) BIT 237 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) BIT 239 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) BIT 478 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c REG_APSD_CTRL) & ~BIT(6))); BIT 482 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7))); BIT 912 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c if (!(pa_setting & BIT(0))) { BIT 918 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) && BIT 925 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c if (!(pa_setting & BIT(4))) { BIT 1059 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) { BIT 1214 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c tmp1byte & (~BIT(6))); BIT 1217 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c tmp1byte &= ~(BIT(0)); BIT 1221 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6)); BIT 1234 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c tmp1byte | BIT(6)); BIT 1237 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c tmp1byte |= BIT(0); BIT 1241 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6))); BIT 1251 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1)); BIT 1253 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 1262 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0); BIT 1264 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 1363 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c tmp = BIT(4); BIT 1366 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c tmp = BIT(4) | BIT(5); BIT 1376 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c tmp = BIT(4); BIT 1379 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c tmp = BIT(4) | BIT(5); BIT 1411 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00); BIT 1789 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); BIT 1806 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c if (rpwm_val & BIT(7)) BIT 1810 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c *val | BIT(7)); BIT 1834 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 1835 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 1838 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c if (tmp_reg422 & BIT(6)) BIT 1841 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c tmp_reg422 & (~BIT(6))); BIT 1844 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 1845 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 1849 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c tmp_reg422 | BIT(6)); BIT 1869 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 1874 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 2195 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c e_rfpowerstate_toset = (u1tmp & BIT(7)) ? BIT 2202 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c REG_MAC_PINMUX_CFG) & ~(BIT(3))); BIT 2204 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c e_rfpowerstate_toset = (u1tmp & BIT(3)) ? BIT 34 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.c REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5) | BIT(6)); BIT 37 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.c rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5)); BIT 62 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.c (ledcfg | BIT(1) | BIT(5) | BIT(6))); BIT 65 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.c (ledcfg | BIT(3) | BIT(5) | BIT(6))); BIT 69 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.c rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3))); BIT 100 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) | BIT 101 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c BIT(0) | BIT(1)); BIT 108 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c rtl_write_dword(rtlpriv, 0x87c, regval32 & (~BIT(31))); BIT 302 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); BIT 310 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0); BIT 311 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), BIT 621 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c set_tx_desc_pkt_id(pdesc, BIT(3)); /* set bit3 to 1. */ BIT 23 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h #define TX_SELE_HQ BIT(0) /* High Queue */ BIT 24 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h #define TX_SELE_LQ BIT(1) /* Low Queue */ BIT 25 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h #define TX_SELE_NQ BIT(2) /* Normal Queue */ BIT 83 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h return le32_get_bits(*__rxdesc, BIT(14)); BIT 88 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h return le32_get_bits(*__rxdesc, BIT(15)); BIT 103 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h return le32_get_bits(*__rxdesc, BIT(26)); BIT 108 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h return le32_get_bits(*__rxdesc, BIT(27)); BIT 115 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h return le32_get_bits(*(__rxdesc + 1), BIT(14)); BIT 120 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h return le32_get_bits(*(__rxdesc + 1), BIT(15)); BIT 132 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h return le32_get_bits(*(__rxdesc + 3), BIT(6)); BIT 137 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h return le32_get_bits(*(__rxdesc + 3), BIT(8)); BIT 142 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h return le32_get_bits(*(__rxdesc + 3), BIT(9)); BIT 170 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits(__txdesc, __value, BIT(24)); BIT 175 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits(__txdesc, __value, BIT(25)); BIT 180 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits(__txdesc, __value, BIT(26)); BIT 185 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits(__txdesc, __value, BIT(27)); BIT 190 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits(__txdesc, __value, BIT(28)); BIT 195 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits(__txdesc, __value, BIT(31)); BIT 207 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 1), __value, BIT(5)); BIT 212 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 1), __value, BIT(6)); BIT 217 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 1), __value, BIT(7)); BIT 232 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 1), __value, BIT(20)); BIT 249 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 2), __value, BIT(17)); BIT 278 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 4), __value, BIT(6)); BIT 283 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 4), __value, BIT(7)); BIT 288 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 4), __value, BIT(8)); BIT 293 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 4), __value, BIT(10)); BIT 298 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 4), __value, BIT(11)); BIT 303 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 4), __value, BIT(12)); BIT 308 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 4), __value, BIT(13)); BIT 318 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 4), __value, BIT(25)); BIT 323 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 4), __value, BIT(26)); BIT 328 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__txdesc + 4), __value, BIT(27)); BIT 350 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h le32p_replace_bits((__pdesc + 5), __val, BIT(6)); BIT 57 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define CHIP_92D_SINGLEPHY BIT(9) BIT 70 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define CHIP_8723 BIT(0) BIT 71 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define CHIP_92D BIT(1) BIT 72 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define NORMAL_CHIP BIT(3) BIT 73 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6))) BIT 74 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define RF_TYPE_1T2R BIT(4) BIT 75 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define RF_TYPE_2T2R BIT(5) BIT 76 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define CHIP_VENDOR_UMC BIT(7) BIT 77 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define CHIP_92D_B_CUT BIT(12) BIT 78 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define CHIP_92D_C_CUT BIT(13) BIT 79 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define CHIP_92D_D_CUT (BIT(13)|BIT(12)) BIT 80 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define CHIP_92D_E_CUT BIT(14) BIT 83 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) BIT 84 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define CHIP_TYPE_MASK BIT(3) BIT 85 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) BIT 86 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define MANUFACTUER_MASK BIT(7) BIT 87 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) BIT 88 drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) BIT 141 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */ BIT 142 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */ BIT 186 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); BIT 188 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); BIT 1040 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), BIT 1050 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c BIT(24), 0x00); BIT 1126 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c BIT(28), value32); BIT 1135 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c BIT(28), 0x00); BIT 1187 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) | BIT 1188 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c BIT(16), 0x03); BIT 7 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.h #define HAL_DM_DIG_DISABLE BIT(0) BIT 8 drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.h #define HAL_DM_HIPWR_DISABLE BIT(1) BIT 99 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c while (u1b_tmp & BIT(2)) { BIT 193 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5)) BIT 206 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5)) BIT 222 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c value |= BIT(5); BIT 227 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c value |= BIT(5); BIT 236 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) { BIT 247 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c value &= (~BIT(5)); BIT 264 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c if (((val_hmetfr >> boxnum) & BIT(0)) == 0) BIT 382 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c boxcontent[0] &= ~(BIT(7)); BIT 389 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c boxcontent[0] &= ~(BIT(7)); BIT 396 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c boxcontent[0] &= ~(BIT(7)); BIT 403 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c boxcontent[0] |= (BIT(7)); BIT 414 drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c boxcontent[0] |= (BIT(7)); BIT 26 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct); BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct); BIT 59 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); BIT 63 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c tmp1byte &= ~(BIT(0)); BIT 73 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); BIT 77 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c tmp1byte |= BIT(0); BIT 83 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1)); BIT 88 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0); BIT 362 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); BIT 394 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c (tmp_regcr | BIT(0))); BIT 395 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 396 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 399 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c if (tmp_reg422 & BIT(6)) BIT 402 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c tmp_reg422 & (~BIT(6))); BIT 404 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 405 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 411 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c (tmp_regcr & ~(BIT(0)))); BIT 429 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 434 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 642 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); BIT 651 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c while ((bytetmp & BIT(0)) && retry < 1000) { BIT 755 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); BIT 759 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c } while ((retry < 200) && !(bytetmp & BIT(7))); BIT 972 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | BIT 973 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c BIT(11), 3); BIT 976 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) | BIT 977 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c BIT(10), 3); BIT 1013 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c if (((tmp_rega & BIT(11)) == BIT(11))) BIT 1121 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 1124 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 1200 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0); BIT 1201 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0); BIT 1268 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c u1b_tmp &= (~BIT(7)); BIT 1560 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6); BIT 1562 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6); BIT 1656 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c if (macphy_crvalue & BIT(3)) { BIT 1773 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c if (tmp_u1b & BIT(4)) { BIT 1780 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c if (tmp_u1b & BIT(5)) { BIT 2058 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c REG_MAC_PINMUX_CFG) & ~(BIT(3))); BIT 2060 drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; BIT 36 drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c BIT(7) | BIT(5) | BIT(6)); BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c BIT(7) | BIT(5)); BIT 44 drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5)); BIT 71 drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c (ledcfg | BIT(1) | BIT(5) | BIT(6))); BIT 74 drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c (ledcfg | BIT(3) | BIT(5) | BIT(6))); BIT 78 drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3))); BIT 45 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1), BIT 46 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(10) | BIT(9), BIT 47 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(18) | BIT(17) | BIT(16) | BIT(1), BIT 48 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(2) | BIT(1), BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) BIT 189 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c dbi_direct = BIT(3); BIT 191 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c dbi_direct = BIT(3) | BIT(2); BIT 217 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c dbi_direct = BIT(3); BIT 220 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c dbi_direct = BIT(3) | BIT(2); BIT 272 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(8)); BIT 275 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(8)); BIT 737 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c regval | BIT(13) | BIT(0) | BIT(1)); BIT 749 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); BIT 976 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | BIT 977 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(11), 3); BIT 992 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | BIT 993 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(11), 0); BIT 994 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), BIT 1056 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c value8 |= BIT(1); BIT 1062 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c value8 &= (~BIT(1)); BIT 1082 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); BIT 1086 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | BIT 1087 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(14), 2); BIT 1089 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | BIT 1090 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(14), 1); BIT 1111 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); BIT 1241 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c u4tmp2 &= ~(BIT(7) | BIT(6)); BIT 1331 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(17))); BIT 1436 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && BIT 1442 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) && BIT 1461 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27); BIT 1464 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c TXOKBIT = BIT(31); BIT 1465 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c RXOKBIT = BIT(30); BIT 1561 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && BIT 1566 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) && BIT 1629 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c if (!(regeac & BIT(31)) && BIT 1634 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c if (!(regeac & BIT(30)) && BIT 1728 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c (~BIT(3)))); BIT 1729 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); BIT 1798 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c RFPGA0_XA_HSSIPARAMETER1, BIT(8)); BIT 1804 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); BIT 1974 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c RFPGA0_XA_HSSIPARAMETER1, BIT(8)); BIT 1978 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); BIT 2156 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), BIT 2174 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), BIT 2214 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), BIT 2228 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), BIT 2561 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(17), 0x0); BIT 2568 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c while ((!(u4tmp & BIT(11))) && timecount <= timeout) { BIT 2617 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(17), 0x1); BIT 2799 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c [rfpath] | (BIT(18)); BIT 2803 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c [rfpath] & (~BIT(18)); BIT 2805 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c (BIT(16) | BIT(8)); BIT 2808 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ~(BIT(8) | BIT(16) | BIT(18)); BIT 2861 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) BIT 2863 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) BIT 3279 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c value8 |= BIT(1); BIT 3283 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c value8 &= (~BIT(1)); BIT 3302 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c if ((value8 & BIT(7)) == 0) { BIT 3355 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); BIT 3356 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); BIT 3358 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); BIT 3359 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); BIT 3362 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); BIT 3364 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); BIT 3374 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(10) | BIT(6) | BIT(5), BIT 3375 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | BIT 3376 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c (rtlefuse->eeprom_c9 & BIT(1)) | BIT 3377 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(1)) << 4)); BIT 3379 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(10) | BIT(6) | BIT(5), BIT 3380 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | BIT 3381 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | BIT 3382 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(0)) << 5)); BIT 3383 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); BIT 3386 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(26) | BIT(22) | BIT(21) | BIT(10) | BIT 3387 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(6) | BIT(5), BIT 3388 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | BIT 3389 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c (rtlefuse->eeprom_c9 & BIT(1)) | BIT 3390 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(1)) << 4) | BIT 3391 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_c9 & BIT(7)) << 9) | BIT 3392 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_c9 & BIT(5)) << 12) | BIT 3393 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(3)) << 18)); BIT 3395 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(10) | BIT(6) | BIT(5), BIT 3396 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | BIT 3397 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | BIT 3398 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(0)) << 5)); BIT 3400 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(10) | BIT(6) | BIT(5), BIT 3401 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) | BIT 3402 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) | BIT 3403 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(2)) << 3)); BIT 3405 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(31) | BIT(15), 0); BIT 3410 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); BIT 3411 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); BIT 3413 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); BIT 3414 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); BIT 3417 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); BIT 3419 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); BIT 3437 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(10) | BIT(6) | BIT(5), BIT 3438 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c (rtlefuse->eeprom_cc & BIT(5))); BIT 3439 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), BIT 3440 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); BIT 3441 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), BIT 3442 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c (rtlefuse->eeprom_cc & BIT(4)) >> 4); BIT 3445 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(26) | BIT(22) | BIT(21) | BIT(10) | BIT 3446 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(6) | BIT(5), BIT 3447 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c (rtlefuse->eeprom_cc & BIT(5)) | BIT 3448 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(7)) << 14)); BIT 3449 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), BIT 3450 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); BIT 3451 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), BIT 3452 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(6)) >> 6)); BIT 3454 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(31) | BIT(15), BIT 3455 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(4)) >> 4) | BIT 3456 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c ((rtlefuse->eeprom_cc & BIT(6)) << 10)); BIT 3463 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | BIT 3464 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(26) | BIT(24), 0x00); BIT 3474 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) | BIT 3475 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(18), 0); BIT 3481 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT 3482 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(16) | BIT(18), BIT 3483 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c (BIT(16) | BIT(8)) >> 8); BIT 3495 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT 3496 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(13), 0x3); BIT 3505 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(3)) | BIT(12) | BIT(13), BIT 3506 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c BIT(3)); BIT 3515 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); BIT 3560 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c u1btmp |= BIT(7); BIT 68 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MAC0_ON BIT(7) BIT 69 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MAC1_ON BIT(0) BIT 70 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MAC0_READY BIT(0) BIT 71 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MAC1_READY BIT(0) BIT 417 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_1M BIT(0) BIT 418 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_2M BIT(1) BIT 419 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_5_5M BIT(2) BIT 420 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_11M BIT(3) BIT 422 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_6M BIT(4) BIT 423 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_9M BIT(5) BIT 424 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_12M BIT(6) BIT 425 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_18M BIT(7) BIT 426 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_24M BIT(8) BIT 427 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_36M BIT(9) BIT 428 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_48M BIT(10) BIT 429 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_54M BIT(11) BIT 431 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS0 BIT(12) BIT 432 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS1 BIT(13) BIT 433 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS2 BIT(14) BIT 434 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS3 BIT(15) BIT 435 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS4 BIT(16) BIT 436 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS5 BIT(17) BIT 437 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS6 BIT(18) BIT 438 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS7 BIT(19) BIT 440 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS8 BIT(20) BIT 441 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS9 BIT(21) BIT 442 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS10 BIT(22) BIT 443 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS11 BIT(23) BIT 444 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS12 BIT(24) BIT 445 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS13 BIT(25) BIT 446 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS14 BIT(26) BIT 447 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RATE_MCS15 BIT(27) BIT 465 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define BW_OPMODE_20MHZ BIT(2) BIT 466 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define BW_OPMODE_5G BIT(1) BIT 467 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define BW_OPMODE_11J BIT(0) BIT 473 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define CAM_VALID BIT(15) BIT 475 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define CAM_USEDK BIT(5) BIT 488 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define CAM_WRITE BIT(16) BIT 490 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define CAM_POLLINIG BIT(31) BIT 503 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDMAINT6 BIT(31) BIT 504 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDMAINT5 BIT(30) BIT 505 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDMAINT4 BIT(29) BIT 506 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDMAINT3 BIT(28) BIT 507 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDMAINT2 BIT(27) BIT 508 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDMAINT1 BIT(26) BIT 509 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDOK8 BIT(25) BIT 510 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDOK7 BIT(24) BIT 511 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDOK6 BIT(23) BIT 512 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDOK5 BIT(22) BIT 513 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDOK4 BIT(21) BIT 514 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDOK3 BIT(20) BIT 515 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDOK2 BIT(19) BIT 516 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNDOK1 BIT(18) BIT 517 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_TIMEOUT2 BIT(17) BIT 518 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_TIMEOUT1 BIT(16) BIT 519 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_TXFOVW BIT(15) BIT 520 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_PSTIMEOUT BIT(14) BIT 521 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BCNINT BIT(13) BIT 522 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_RXFOVW BIT(12) BIT 523 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_RDU BIT(11) BIT 524 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_ATIMEND BIT(10) BIT 525 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BDOK BIT(9) BIT 526 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_HIGHDOK BIT(8) BIT 527 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_TBDOK BIT(7) BIT 528 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_MGNTDOK BIT(6) BIT 529 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_TBDER BIT(5) BIT 530 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BKDOK BIT(4) BIT 531 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_BEDOK BIT(3) BIT 532 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_VIDOK BIT(2) BIT 533 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_VODOK BIT(1) BIT 534 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_ROK BIT(0) BIT 536 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_TXERR BIT(11) BIT 537 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_RXERR BIT(10) BIT 538 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_C2HCMD BIT(9) BIT 539 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_CPWM BIT(8) BIT 540 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_OCPINT BIT(1) BIT 541 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IMR_WLANOFF BIT(0) BIT 679 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_APPFCS BIT(31) BIT 680 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_APP_MIC BIT(30) BIT 681 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_APP_ICV BIT(29) BIT 682 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_APP_PHYST_RXFF BIT(28) BIT 683 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_APP_BA_SSN BIT(27) BIT 684 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_ENMBID BIT(24) BIT 685 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_LSIGEN BIT(23) BIT 686 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_MFBEN BIT(22) BIT 687 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_HTC_LOC_CTRL BIT(14) BIT 688 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_AMF BIT(13) BIT 689 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_ACF BIT(12) BIT 690 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_ADF BIT(11) BIT 691 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_AICV BIT(9) BIT 692 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_ACRC32 BIT(8) BIT 693 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_CBSSID_BCN BIT(7) BIT 694 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_CBSSID_DATA BIT(6) BIT 695 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_APWRMGT BIT(5) BIT 696 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_ADD3 BIT(4) BIT 697 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_AB BIT(3) BIT 698 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_AM BIT(2) BIT 699 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_APM BIT(1) BIT 700 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RCR_AAP BIT(0) BIT 712 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SW18_FPWM BIT(3) BIT 716 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ISO_MD2PP BIT(0) BIT 717 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ISO_UA2USB BIT(1) BIT 718 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ISO_UD2CORE BIT(2) BIT 719 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ISO_PA2PCIE BIT(3) BIT 720 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ISO_PD2CORE BIT(4) BIT 721 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ISO_IP2MAC BIT(5) BIT 722 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ISO_DIOP BIT(6) BIT 723 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ISO_DIOE BIT(7) BIT 724 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ISO_EB2CORE BIT(8) BIT 725 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ISO_DIOR BIT(9) BIT 727 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PWC_EV25V BIT(14) BIT 728 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PWC_EV12V BIT(15) BIT 732 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_BBRSTB BIT(0) BIT 733 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_BB_GLB_RSTN BIT(1) BIT 734 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_USBA BIT(2) BIT 735 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_UPLL BIT(3) BIT 736 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_USBD BIT(4) BIT 737 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_DIO_PCIE BIT(5) BIT 738 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_PCIEA BIT(6) BIT 739 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_PPLL BIT(7) BIT 740 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_PCIED BIT(8) BIT 741 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_DIOE BIT(9) BIT 742 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_CPUEN BIT(10) BIT 743 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_DCORE BIT(11) BIT 744 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_ELDR BIT(12) BIT 745 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_DIO_RF BIT(13) BIT 746 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_HWPDN BIT(14) BIT 747 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FEN_MREGEN BIT(15) BIT 750 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PFM_LDALL BIT(0) BIT 751 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PFM_ALDN BIT(1) BIT 752 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PFM_LDKP BIT(2) BIT 753 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PFM_WOWL BIT(3) BIT 754 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ENPDN BIT(4) BIT 755 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PDN_PL BIT(5) BIT 756 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APFM_ONMAC BIT(8) BIT 757 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APFM_OFF BIT(9) BIT 758 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APFM_RSM BIT(10) BIT 759 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define AFSM_HSUS BIT(11) BIT 760 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define AFSM_PCIE BIT(12) BIT 761 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APDM_MAC BIT(13) BIT 762 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APDM_HOST BIT(14) BIT 763 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APDM_HPDN BIT(15) BIT 764 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RDY_MACON BIT(16) BIT 765 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SUS_HOST BIT(17) BIT 766 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ROP_ALD BIT(20) BIT 767 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ROP_PWR BIT(21) BIT 768 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ROP_SPS BIT(22) BIT 769 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SOP_MRST BIT(25) BIT 770 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SOP_FUSE BIT(26) BIT 771 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SOP_ABG BIT(27) BIT 772 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SOP_AMB BIT(28) BIT 773 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SOP_RCK BIT(29) BIT 774 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SOP_A8M BIT(30) BIT 775 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define XOP_BTCK BIT(31) BIT 778 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ANAD16V_EN BIT(0) BIT 779 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ANA8M BIT(1) BIT 780 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MACSLP BIT(4) BIT 781 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LOADER_CLK_EN BIT(5) BIT 782 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define _80M_SSC_DIS BIT(7) BIT 783 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define _80M_SSC_EN_HO BIT(8) BIT 784 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PHY_SSC_RSTB BIT(9) BIT 785 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SEC_CLK_EN BIT(10) BIT 786 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MAC_CLK_EN BIT(11) BIT 787 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SYS_CLK_EN BIT(12) BIT 788 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RING_CLK_EN BIT(13) BIT 792 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define BOOT_FROM_EEPROM BIT(4) BIT 793 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define EEPROM_EN BIT(5) BIT 796 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define AFE_BGEN BIT(0) BIT 797 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define AFE_MBEN BIT(1) BIT 798 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MAC_ID_EN BIT(7) BIT 801 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define WLOCK_ALL BIT(0) BIT 802 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define WLOCK_00 BIT(1) BIT 803 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define WLOCK_04 BIT(2) BIT 804 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define WLOCK_08 BIT(3) BIT 805 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define WLOCK_40 BIT(4) BIT 806 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define R_DIS_PRST_0 BIT(5) BIT 807 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define R_DIS_PRST_1 BIT(6) BIT 808 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LOCK_ALL_EN BIT(7) BIT 811 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RF_EN BIT(0) BIT 812 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RF_RSTB BIT(1) BIT 813 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RF_SDMRSTB BIT(2) BIT 818 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LDA15_EN BIT(0) BIT 819 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LDA15_STBY BIT(1) BIT 820 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LDA15_OBUF BIT(2) BIT 821 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LDA15_REG_VOS BIT(3) BIT 827 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LDV12_EN BIT(0) BIT 828 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LDV12_SDBY BIT(1) BIT 829 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LPLDO_HSM BIT(2) BIT 830 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LPLDO_LSM_DIS BIT(3) BIT 835 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define XTAL_EN BIT(0) BIT 836 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define XTAL_BSEL BIT(1) BIT 839 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define XTAL_GATE_USB BIT(8) BIT 841 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define XTAL_GATE_AFE BIT(11) BIT 843 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define XTAL_RF_GATE BIT(14) BIT 845 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define XTAL_GATE_DIG BIT(17) BIT 847 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define XTAL_BT_GATE BIT(20) BIT 852 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define CKDLY_AFE BIT(26) BIT 853 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define CKDLY_USB BIT(27) BIT 854 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define CKDLY_DIG BIT(28) BIT 855 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define CKDLY_BT BIT(29) BIT 859 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APLL_EN BIT(0) BIT 860 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APLL_320_EN BIT(1) BIT 861 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APLL_FREF_SEL BIT(2) BIT 862 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APLL_EDGE_SEL BIT(3) BIT 863 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APLL_WDOGB BIT(4) BIT 864 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APLL_LPFEN BIT(5) BIT 874 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APLL_320EN BIT(14) BIT 875 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APLL_80EN BIT(15) BIT 876 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define APLL_1MEN BIT(24) BIT 880 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ALD_EN BIT(18) BIT 881 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define EF_PD BIT(19) BIT 882 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define EF_FLAG BIT(31) BIT 885 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define EF_TRPT BIT(7) BIT 886 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define LDOE25_EN BIT(31) BIT 889 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MCUFWDL_EN BIT(0) BIT 890 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MCUFWDL_RDY BIT(1) BIT 891 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define FWDL_CHKSUM_RPT BIT(2) BIT 892 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MACINI_RDY BIT(3) BIT 893 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define BBINI_RDY BIT(4) BIT 894 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define RFINI_RDY BIT(5) BIT 895 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define WINTINI_RDY BIT(6) BIT 896 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define MAC1_WINTINI_RDY BIT(11) BIT 897 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define CPRST BIT(23) BIT 900 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define XCLK_VLD BIT(0) BIT 901 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ACLK_VLD BIT(1) BIT 902 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define UCLK_VLD BIT(2) BIT 903 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PCLK_VLD BIT(3) BIT 904 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PCIRSTB BIT(4) BIT 905 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define V15_VLD BIT(5) BIT 906 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define TRP_B15V_EN BIT(7) BIT 907 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SIC_IDLE BIT(8) BIT 908 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define BD_MAC2 BIT(9) BIT 909 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define BD_MAC1 BIT(10) BIT 910 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define IC_MACPHY_MODE BIT(11) BIT 911 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PAD_HWPD_IDN BIT(22) BIT 912 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define TRP_VAUX_EN BIT(23) BIT 913 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define TRP_BT_EN BIT(24) BIT 914 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define BD_PKG_SEL BIT(25) BIT 915 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define BD_HCI_SEL BIT(26) BIT 916 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define TYPE_ID BIT(27) BIT 946 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ACMHW_HWEN BIT(0) BIT 947 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ACMHW_BEQEN BIT(1) BIT 948 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ACMHW_VIQEN BIT(2) BIT 949 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ACMHW_VOQEN BIT(3) BIT 956 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define TSFRST BIT(0) BIT 957 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define DIS_GCLK BIT(1) BIT 958 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PAD_SEL BIT(2) BIT 959 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PWR_ST BIT(6) BIT 960 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define PWRBIT_OW_EN BIT(7) BIT 961 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ACRC BIT(8) BIT 962 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define CFENDFORM BIT(9) BIT 963 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define ICV BIT(10) BIT 966 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SCR_TXUSEDK BIT(0) BIT 967 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SCR_RXUSEDK BIT(1) BIT 968 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SCR_TXENCENABLE BIT(2) BIT 969 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SCR_RXENCENABLE BIT(3) BIT 970 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SCR_SKBYA2 BIT(4) BIT 971 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SCR_NOSKMC BIT(5) BIT 972 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SCR_TXBCUSEDK BIT(6) BIT 973 drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h #define SCR_RXBCUSEDK BIT(7) BIT 23 drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT 24 drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c BIT(11), 0x01); BIT 36 drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11), BIT 387 drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c u8 direct = bmac0 ? BIT(3) | BIT(2) : BIT(3); BIT 402 drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c BIT(29) | BIT(16) | BIT(17), direct); BIT 418 drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c u8 direct = bmac0 ? BIT(3) | BIT(2) : BIT(3); BIT 90 drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); BIT 104 drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c BIT(9)); BIT 847 drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4)); BIT 850 drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c BIT(0) << (hw_queue)); BIT 139 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); BIT 140 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); BIT 168 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(12), 1); BIT 169 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(14), 1); BIT 193 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 1); BIT 194 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 0); BIT 195 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 1); BIT 196 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 0); BIT 198 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0); BIT 199 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 0); BIT 201 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0); BIT 202 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2); BIT 204 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0); BIT 205 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2); BIT 677 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, DM_REG_L1SBD_PD_CH_11N, BIT(8) | BIT(7), BIT 800 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11), BIT 880 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11), BIT 886 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11), BIT 1035 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11)); BIT 158 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.h #define HAL_DM_DIG_DISABLE BIT(0) BIT 159 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.h #define HAL_DM_HIPWR_DISABLE BIT(1) BIT 140 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.c if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) { BIT 161 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.c if (((val_hmetfr >> boxnum) & BIT(0)) == 0) BIT 381 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); BIT 384 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); BIT 389 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0))); BIT 392 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp | BIT(2))); BIT 452 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.c if ((rlbm == 2) && (byte5 & BIT(4))) { BIT 831 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4)); BIT 863 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.c bool collision_state = cmd_buf[3] & BIT(0); BIT 37 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.h #define FW_PS_RF_ON BIT(2) BIT 38 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.h #define FW_PS_REGISTER_ACTIVE BIT(3) BIT 40 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.h #define FW_PS_ACK BIT(6) BIT 41 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.h #define FW_PS_TOGGLE BIT(7) BIT 45 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.h #define FW_PS_CLOCK_OFF BIT(0) /* 32k */ BIT 41 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6))); BIT 44 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp &= ~(BIT(0)); BIT 54 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6)); BIT 57 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp |= BIT(0); BIT 63 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); BIT 68 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0); BIT 338 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0)); BIT 345 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 346 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 352 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6))); BIT 354 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (tmp_reg422 & BIT(6)) BIT 361 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c bcnvalid_reg | BIT(0)); BIT 368 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c while ((txbc_reg & BIT(4)) && count < 20) { BIT 374 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c txbc_reg | BIT(4)); BIT 379 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c while (!(bcnvalid_reg & BIT(0)) && count < 20) { BIT 386 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (bcnvalid_reg & BIT(0)) BIT 387 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0)); BIT 390 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); BIT 392 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (!(bcnvalid_reg & BIT(0))) BIT 397 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 398 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 404 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0))); BIT 426 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1)); BIT 575 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); BIT 592 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (rpwm_val & BIT(7)) { BIT 596 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c ((*(u8 *)val) | BIT(7))); BIT 646 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 653 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 700 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0)); BIT 702 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c while (u8tmp & BIT(0)) { BIT 743 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (dwordtmp & BIT(24)) { BIT 747 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6)); BIT 790 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3)); BIT 792 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4))); BIT 1038 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp32 | BIT(13)); BIT 1066 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp32 | BIT(31)); BIT 1091 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp32 | BIT(11) | BIT(12)); BIT 1131 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1)); BIT 1145 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (!(tmp & BIT(2))) { BIT 1147 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp | BIT(2)); BIT 1155 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if ((tmp & BIT(0)) || (tmp & BIT(1))) { BIT 1182 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp &= ~(BIT(1) | BIT(0)); BIT 1185 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp |= BIT(2); BIT 1193 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (tmp & BIT(2)) { BIT 1197 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); BIT 1216 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp &= ~(BIT(0)); BIT 1223 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp |= BIT(0); BIT 1242 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp |= BIT(1); BIT 1258 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c (tmp & (~BIT(2)))); BIT 1268 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c tmp &= ~(BIT(2)); BIT 1290 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) { BIT 1354 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c BIT(10) | BIT(11); BIT 1402 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (!(tmp_u1b & BIT(0))) { BIT 1407 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) { BIT 1533 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 1536 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 1623 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready) BIT 1628 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); BIT 1639 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); BIT 1641 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0))); BIT 1703 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtlpci->reg_bcn_ctrl_val |= BIT(3); BIT 1862 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr2g->bw20_diff[rf][i] & BIT(3)) BIT 1871 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr2g->ofdm_diff[rf][i] & BIT(3)) BIT 1882 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr2g->bw40_diff[rf][i] & BIT(3)) BIT 1891 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr2g->bw20_diff[rf][i] & BIT(3)) BIT 1901 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr2g->ofdm_diff[rf][i] & BIT(3)) BIT 1910 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr2g->cck_diff[rf][i] & BIT(3)) BIT 1933 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr5g->bw20_diff[rf][i] & BIT(3)) BIT 1942 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr5g->ofdm_diff[rf][i] & BIT(3)) BIT 1952 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr5g->bw40_diff[rf][i] & BIT(3)) BIT 1961 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr5g->bw20_diff[rf][i] & BIT(3)) BIT 1986 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c else if (pwr5g->ofdm_diff[rf][i] & BIT(3)) BIT 1996 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr5g->bw80_diff[rf][i] & BIT(3)) BIT 2005 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (pwr5g->bw160_diff[rf][i] & BIT(3)) BIT 2134 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */ BIT 2197 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (tmp_u1b & BIT(4)) { BIT 2204 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if (tmp_u1b & BIT(5)) { BIT 2381 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 30 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.c ledcfg &= ~BIT(13); BIT 31 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.c ledcfg |= BIT(21); BIT 32 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.c ledcfg &= ~BIT(29); BIT 62 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.c ledcfg |= ~BIT(21); BIT 63 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.c ledcfg &= ~BIT(29); BIT 168 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c BIT(8)); BIT 171 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c BIT(8)); BIT 234 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c regval | BIT(13) | BIT(0) | BIT(1)); BIT 244 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); BIT 1707 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c (BIT(31) | BIT(30)), 0); BIT 1717 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), BIT 1974 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c if (!(reg_eac & BIT(28)) && BIT 2018 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c if (!(reg_eac & BIT(31)) && BIT 2076 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c if (!(reg_eac & BIT(28)) && BIT 2135 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c if (!(reg_eac & BIT(27)) && BIT 2191 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c if (!(reg_eac & BIT(31)) && BIT 2249 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c if (!(reg_eac & BIT(30)) && BIT 2277 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), BIT 2287 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), BIT 2322 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), BIT 2332 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), BIT 2529 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); BIT 2534 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01); BIT 2535 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01); BIT 2536 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01); BIT 2537 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01); BIT 2736 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7)); BIT 2737 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); BIT 2742 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c BIT(5) | BIT(6), 0x1); BIT 2745 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c BIT(5) | BIT(6), 0x2); BIT 2747 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); BIT 2756 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c BIT(14) | BIT(13) | BIT(12), 0); BIT 2758 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c BIT(5) | BIT(4) | BIT(3), 0); BIT 2760 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); BIT 2763 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c BIT(14) | BIT(13) | BIT(12), 1); BIT 2765 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c BIT(5) | BIT(4) | BIT(3), 1); BIT 2767 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); BIT 47 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \ BIT 50 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \ BIT 53 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \ BIT 56 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)}, \ BIT 59 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 62 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 65 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0}, BIT 76 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \ BIT 79 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \ BIT 82 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0}, BIT 90 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\ BIT 94 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \ BIT 97 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\ BIT 100 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 103 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0}, BIT 111 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \ BIT 114 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \ BIT 117 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, BIT 128 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \ BIT 131 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \ BIT 135 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \ BIT 138 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \ BIT 141 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 144 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0}, BIT 152 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \ BIT 155 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \ BIT 158 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 161 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \ BIT 164 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, BIT 172 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \ BIT 175 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)}, BIT 183 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, BIT 209 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \ BIT 215 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \ BIT 221 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \ BIT 227 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)}, BIT 247 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0}, \ BIT 250 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0}, \ BIT 253 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \ BIT 259 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\ BIT 382 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CMDEEPROM_EN BIT(5) BIT 383 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CMDEEPROM_SEL BIT(4) BIT 384 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CMD9346CR_9356SEL BIT(4) BIT 389 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define GPIOSEL_ENBT BIT(5) BIT 407 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_1M BIT(0) BIT 408 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_2M BIT(1) BIT 409 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_5_5M BIT(2) BIT 410 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_11M BIT(3) BIT 411 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_6M BIT(4) BIT 412 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_9M BIT(5) BIT 413 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_12M BIT(6) BIT 414 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_18M BIT(7) BIT 415 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_24M BIT(8) BIT 416 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_36M BIT(9) BIT 417 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_48M BIT(10) BIT 418 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_54M BIT(11) BIT 419 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_MCS0 BIT(12) BIT 420 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_MCS1 BIT(13) BIT 421 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_MCS2 BIT(14) BIT 422 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_MCS3 BIT(15) BIT 423 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_MCS4 BIT(16) BIT 424 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_MCS5 BIT(17) BIT 425 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_MCS6 BIT(18) BIT 426 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RRSR_MCS7 BIT(19) BIT 427 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BRSR_ACKSHORTPMB BIT(23) BIT 458 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_1M BIT(0) BIT 459 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_2M BIT(1) BIT 460 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_5_5M BIT(2) BIT 461 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_11M BIT(3) BIT 462 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_6M BIT(4) BIT 463 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_9M BIT(5) BIT 464 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_12M BIT(6) BIT 465 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_18M BIT(7) BIT 466 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_24M BIT(8) BIT 467 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_36M BIT(9) BIT 468 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_48M BIT(10) BIT 469 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_54M BIT(11) BIT 470 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS0 BIT(12) BIT 471 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS1 BIT(13) BIT 472 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS2 BIT(14) BIT 473 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS3 BIT(15) BIT 474 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS4 BIT(16) BIT 475 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS5 BIT(17) BIT 476 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS6 BIT(18) BIT 477 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS7 BIT(19) BIT 478 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS8 BIT(20) BIT 479 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS9 BIT(21) BIT 480 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS10 BIT(22) BIT 481 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS11 BIT(23) BIT 482 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS12 BIT(24) BIT 483 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS13 BIT(25) BIT 484 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS14 BIT(26) BIT 485 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RATE_MCS15 BIT(27) BIT 497 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BW_OPMODE_20MHZ BIT(2) BIT 498 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BW_OPMODE_5G BIT(1) BIT 499 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CAM_VALID BIT(15) BIT 501 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CAM_USEDK BIT(5) BIT 512 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CAM_WRITE BIT(16) BIT 514 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CAM_POLLINIG BIT(31) BIT 525 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_TIMER2 BIT(31) BIT 526 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_TIMER1 BIT(30) BIT 527 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_PSTIMEOUT BIT(29) BIT 528 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_GTINT4 BIT(28) BIT 529 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_GTINT3 BIT(27) BIT 530 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_TBDER BIT(26) BIT 531 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_TBDOK BIT(25) BIT 532 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_TSF_BIT32_TOGGLE BIT(24) BIT 533 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDMAINT0 BIT(20) BIT 534 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDOK0 BIT(16) BIT 535 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDMAINT_E BIT(14) BIT 536 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_ATIMEND BIT(12) BIT 537 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_HISR1_IND_INT BIT(11) BIT 538 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_C2HCMD BIT(10) BIT 539 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_CPWM2 BIT(9) BIT 540 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_CPWM BIT(8) BIT 541 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_HIGHDOK BIT(7) BIT 542 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_MGNTDOK BIT(6) BIT 543 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BKDOK BIT(5) BIT 544 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BEDOK BIT(4) BIT 545 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_VIDOK BIT(3) BIT 546 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_VODOK BIT(2) BIT 547 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_RDU BIT(1) BIT 548 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_ROK BIT(0) BIT 551 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_MCUERR BIT(28) BIT 552 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDMAINT7 BIT(27) BIT 553 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDMAINT6 BIT(26) BIT 554 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDMAINT5 BIT(25) BIT 555 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDMAINT4 BIT(24) BIT 556 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDMAINT3 BIT(23) BIT 557 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDMAINT2 BIT(22) BIT 558 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDMAINT1 BIT(21) BIT 559 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDOK7 BIT(20) BIT 560 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDOK6 BIT(19) BIT 561 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDOK5 BIT(18) BIT 562 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDOK4 BIT(17) BIT 563 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDOK3 BIT(16) BIT 564 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDOK2 BIT(15) BIT 565 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_BCNDOK1 BIT(14) BIT 566 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_ATIMEND_E BIT(13) BIT 567 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_TXERR BIT(11) BIT 568 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_RXERR BIT(10) BIT 569 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_TXFOVW BIT(9) BIT 570 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IMR_RXFOVW BIT(8) BIT 657 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define STOPBECON BIT(6) BIT 658 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define STOPHIGHT BIT(5) BIT 659 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define STOPMGT BIT(4) BIT 660 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define STOPVO BIT(3) BIT 661 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define STOPVI BIT(2) BIT 662 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define STOPBE BIT(1) BIT 663 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define STOPBK BIT(0) BIT 665 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_APPFCS BIT(31) BIT 666 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_APP_MIC BIT(30) BIT 667 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_APP_ICV BIT(29) BIT 668 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_APP_PHYST_RXFF BIT(28) BIT 669 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_APP_BA_SSN BIT(27) BIT 670 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_ENMBID BIT(24) BIT 671 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_LSIGEN BIT(23) BIT 672 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_MFBEN BIT(22) BIT 673 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_HTC_LOC_CTRL BIT(14) BIT 674 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_AMF BIT(13) BIT 675 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_ACF BIT(12) BIT 676 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_ADF BIT(11) BIT 677 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_AICV BIT(9) BIT 678 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_ACRC32 BIT(8) BIT 679 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_CBSSID_BCN BIT(7) BIT 680 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_CBSSID_DATA BIT(6) BIT 682 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_APWRMGT BIT(5) BIT 683 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_ADD3 BIT(4) BIT 684 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_AB BIT(3) BIT 685 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_AM BIT(2) BIT 686 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_APM BIT(1) BIT 687 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RCR_AAP BIT(0) BIT 709 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SW18_FPWM BIT(3) BIT 711 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ISO_MD2PP BIT(0) BIT 712 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ISO_UA2USB BIT(1) BIT 713 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ISO_UD2CORE BIT(2) BIT 714 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ISO_PA2PCIE BIT(3) BIT 715 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ISO_PD2CORE BIT(4) BIT 716 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ISO_IP2MAC BIT(5) BIT 717 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ISO_DIOP BIT(6) BIT 718 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ISO_DIOE BIT(7) BIT 719 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ISO_EB2CORE BIT(8) BIT 720 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ISO_DIOR BIT(9) BIT 722 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PWC_EV25V BIT(14) BIT 723 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PWC_EV12V BIT(15) BIT 725 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_BBRSTB BIT(0) BIT 726 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_BB_GLB_RSTN BIT(1) BIT 727 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_USBA BIT(2) BIT 728 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_UPLL BIT(3) BIT 729 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_USBD BIT(4) BIT 730 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_DIO_PCIE BIT(5) BIT 731 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_PCIEA BIT(6) BIT 732 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_PPLL BIT(7) BIT 733 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_PCIED BIT(8) BIT 734 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_DIOE BIT(9) BIT 735 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_CPUEN BIT(10) BIT 736 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_DCORE BIT(11) BIT 737 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_ELDR BIT(12) BIT 738 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_DIO_RF BIT(13) BIT 739 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_HWPDN BIT(14) BIT 740 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FEN_MREGEN BIT(15) BIT 742 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PFM_LDALL BIT(0) BIT 743 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PFM_ALDN BIT(1) BIT 744 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PFM_LDKP BIT(2) BIT 745 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PFM_WOWL BIT(3) BIT 746 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ENPDN BIT(4) BIT 747 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PDN_PL BIT(5) BIT 748 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APFM_ONMAC BIT(8) BIT 749 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APFM_OFF BIT(9) BIT 750 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APFM_RSM BIT(10) BIT 751 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define AFSM_HSUS BIT(11) BIT 752 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define AFSM_PCIE BIT(12) BIT 753 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APDM_MAC BIT(13) BIT 754 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APDM_HOST BIT(14) BIT 755 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APDM_HPDN BIT(15) BIT 756 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RDY_MACON BIT(16) BIT 757 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SUS_HOST BIT(17) BIT 758 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ROP_ALD BIT(20) BIT 759 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ROP_PWR BIT(21) BIT 760 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ROP_SPS BIT(22) BIT 761 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SOP_MRST BIT(25) BIT 762 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SOP_FUSE BIT(26) BIT 763 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SOP_ABG BIT(27) BIT 764 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SOP_AMB BIT(28) BIT 765 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SOP_RCK BIT(29) BIT 766 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SOP_A8M BIT(30) BIT 767 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define XOP_BTCK BIT(31) BIT 769 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ANAD16V_EN BIT(0) BIT 770 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ANA8M BIT(1) BIT 771 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define MACSLP BIT(4) BIT 772 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LOADER_CLK_EN BIT(5) BIT 773 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define _80M_SSC_DIS BIT(7) BIT 774 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define _80M_SSC_EN_HO BIT(8) BIT 775 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PHY_SSC_RSTB BIT(9) BIT 776 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SEC_CLK_EN BIT(10) BIT 777 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define MAC_CLK_EN BIT(11) BIT 778 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SYS_CLK_EN BIT(12) BIT 779 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RING_CLK_EN BIT(13) BIT 781 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BOOT_FROM_EEPROM BIT(4) BIT 782 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define EEPROM_EN BIT(5) BIT 784 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define AFE_BGEN BIT(0) BIT 785 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define AFE_MBEN BIT(1) BIT 786 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define MAC_ID_EN BIT(7) BIT 788 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WLOCK_ALL BIT(0) BIT 789 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WLOCK_00 BIT(1) BIT 790 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WLOCK_04 BIT(2) BIT 791 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WLOCK_08 BIT(3) BIT 792 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WLOCK_40 BIT(4) BIT 793 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define R_DIS_PRST_0 BIT(5) BIT 794 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define R_DIS_PRST_1 BIT(6) BIT 795 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LOCK_ALL_EN BIT(7) BIT 797 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RF_EN BIT(0) BIT 798 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RF_RSTB BIT(1) BIT 799 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RF_SDMRSTB BIT(2) BIT 801 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LDA15_EN BIT(0) BIT 802 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LDA15_STBY BIT(1) BIT 803 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LDA15_OBUF BIT(2) BIT 804 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LDA15_REG_VOS BIT(3) BIT 807 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LDV12_EN BIT(0) BIT 808 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LDV12_SDBY BIT(1) BIT 809 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LPLDO_HSM BIT(2) BIT 810 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LPLDO_LSM_DIS BIT(3) BIT 813 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define XTAL_EN BIT(0) BIT 814 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define XTAL_BSEL BIT(1) BIT 817 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define XTAL_GATE_USB BIT(8) BIT 819 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define XTAL_GATE_AFE BIT(11) BIT 821 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define XTAL_RF_GATE BIT(14) BIT 823 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define XTAL_GATE_DIG BIT(17) BIT 825 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define XTAL_BT_GATE BIT(20) BIT 829 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CKDLY_AFE BIT(26) BIT 830 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CKDLY_USB BIT(27) BIT 831 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CKDLY_DIG BIT(28) BIT 832 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CKDLY_BT BIT(29) BIT 834 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APLL_EN BIT(0) BIT 835 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APLL_320_EN BIT(1) BIT 836 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APLL_FREF_SEL BIT(2) BIT 837 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APLL_EDGE_SEL BIT(3) BIT 838 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APLL_WDOGB BIT(4) BIT 839 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APLL_LPFEN BIT(5) BIT 849 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APLL_320EN BIT(14) BIT 850 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APLL_80EN BIT(15) BIT 851 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APLL_1MEN BIT(24) BIT 853 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ALD_EN BIT(18) BIT 854 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define EF_PD BIT(19) BIT 855 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define EF_FLAG BIT(31) BIT 857 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define EF_TRPT BIT(7) BIT 858 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LDOE25_EN BIT(31) BIT 860 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RSM_EN BIT(0) BIT 861 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TIMER_EN BIT(4) BIT 863 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TRSW0EN BIT(2) BIT 864 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TRSW1EN BIT(3) BIT 865 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define EROM_EN BIT(4) BIT 866 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ENBT BIT(5) BIT 867 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ENUART BIT(8) BIT 868 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define UART_910 BIT(9) BIT 869 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ENPMAC BIT(10) BIT 870 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SIC_SWRST BIT(11) BIT 871 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ENSIC BIT(12) BIT 872 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SIC_23 BIT(13) BIT 873 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ENHDP BIT(14) BIT 874 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SIC_LBK BIT(15) BIT 876 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LED0PL BIT(4) BIT 877 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LED1PL BIT(12) BIT 878 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LED0DIS BIT(7) BIT 880 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define MCUFWDL_EN BIT(0) BIT 881 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define MCUFWDL_RDY BIT(1) BIT 882 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define FWDL_CHKSUM_RPT BIT(2) BIT 883 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define MACINI_RDY BIT(3) BIT 884 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BBINI_RDY BIT(4) BIT 885 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RFINI_RDY BIT(5) BIT 886 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WINTINI_RDY BIT(6) BIT 887 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CPRST BIT(23) BIT 889 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define XCLK_VLD BIT(0) BIT 890 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACLK_VLD BIT(1) BIT 891 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define UCLK_VLD BIT(2) BIT 892 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PCLK_VLD BIT(3) BIT 893 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PCIRSTB BIT(4) BIT 894 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define V15_VLD BIT(5) BIT 895 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TRP_B15V_EN BIT(7) BIT 896 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SIC_IDLE BIT(8) BIT 897 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BD_MAC2 BIT(9) BIT 898 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BD_MAC1 BIT(10) BIT 899 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define IC_MACPHY_MODE BIT(11) BIT 900 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define VENDOR_ID BIT(19) BIT 901 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PAD_HWPD_IDN BIT(22) BIT 902 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TRP_VAUX_EN BIT(23) BIT 903 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TRP_BT_EN BIT(24) BIT 904 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BD_PKG_SEL BIT(25) BIT 905 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BD_HCI_SEL BIT(26) BIT 906 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TYPE_ID BIT(27) BIT 913 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HCI_TXDMA_EN BIT(0) BIT 914 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HCI_RXDMA_EN BIT(1) BIT 915 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TXDMA_EN BIT(2) BIT 916 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RXDMA_EN BIT(3) BIT 917 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PROTOCOL_EN BIT(4) BIT 918 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SCHEDULE_EN BIT(5) BIT 919 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define MACTXEN BIT(6) BIT 920 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define MACRXEN BIT(7) BIT 921 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ENSWBCN BIT(8) BIT 922 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ENSEC BIT(9) BIT 952 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RXDMA_ARBBW_EN BIT(0) BIT 953 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RXSHFT_EN BIT(1) BIT 954 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RXDMA_AGG_EN BIT(2) BIT 955 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define QS_VO_QUEUE BIT(8) BIT 956 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define QS_VI_QUEUE BIT(9) BIT 957 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define QS_BE_QUEUE BIT(10) BIT 958 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define QS_BK_QUEUE BIT(11) BIT 959 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define QS_MANAGER_QUEUE BIT(12) BIT 960 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define QS_HIGH_QUEUE BIT(13) BIT 962 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HQSEL_VOQ BIT(0) BIT 963 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HQSEL_VIQ BIT(1) BIT 964 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HQSEL_BEQ BIT(2) BIT 965 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HQSEL_BKQ BIT(3) BIT 966 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HQSEL_MGTQ BIT(4) BIT 967 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HQSEL_HIQ BIT(5) BIT 989 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) BIT 990 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BB_WRITE_EN BIT(30) BIT 991 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BB_READ_EN BIT(31) BIT 998 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HPQ_PUBLIC_DIS BIT(24) BIT 999 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LPQ_PUBLIC_DIS BIT(25) BIT 1000 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LD_RQPN BIT(31) BIT 1002 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BCN_VALID BIT(16) BIT 1009 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define DROP_DATA_EN BIT(9) BIT 1011 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define EN_AMPDU_RTY_NEW BIT(7) BIT 1028 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define USE_SHORT_G1 BIT(20) BIT 1083 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define DIS_EDCA_CNT_DWN BIT(11) BIT 1085 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define EN_MBSSID BIT(1) BIT 1086 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define EN_TXBCN_RPT BIT(2) BIT 1087 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define EN_BCN_FUNCTION BIT(3) BIT 1089 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TSFTR_RST BIT(0) BIT 1090 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TSFTR1_RST BIT(1) BIT 1092 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define STOP_BCNQ BIT(6) BIT 1094 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) BIT 1095 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define DIS_TSF_UDT0_TEST_CHIP BIT(5) BIT 1097 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACMHW_HWEN BIT(0) BIT 1098 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACMHW_BEQEN BIT(1) BIT 1099 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACMHW_VIQEN BIT(2) BIT 1100 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACMHW_VOQEN BIT(3) BIT 1101 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACMHW_BEQSTATUS BIT(4) BIT 1102 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACMHW_VIQSTATUS BIT(5) BIT 1103 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACMHW_VOQSTATUS BIT(6) BIT 1105 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APSDOFF BIT(6) BIT 1106 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APSDOFF_STATUS BIT(7) BIT 1108 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BW_20MHZ BIT(2) BIT 1114 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define TSFRST BIT(0) BIT 1115 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define DIS_GCLK BIT(1) BIT 1116 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PAD_SEL BIT(2) BIT 1117 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PWR_ST BIT(6) BIT 1118 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define PWRBIT_OW_EN BIT(7) BIT 1119 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACRC BIT(8) BIT 1120 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CFENDFORM BIT(9) BIT 1121 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ICV BIT(10) BIT 1123 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define AAP BIT(0) BIT 1124 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APM BIT(1) BIT 1125 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define AM BIT(2) BIT 1126 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define AB BIT(3) BIT 1127 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ADD3 BIT(4) BIT 1128 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APWRMGT BIT(5) BIT 1129 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CBSSID BIT(6) BIT 1130 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CBSSID_DATA BIT(6) BIT 1131 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define CBSSID_BCN BIT(7) BIT 1132 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACRC32 BIT(8) BIT 1133 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define AICV BIT(9) BIT 1134 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ADF BIT(11) BIT 1135 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ACF BIT(12) BIT 1136 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define AMF BIT(13) BIT 1137 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HTC_LOC_CTRL BIT(14) BIT 1138 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define UC_DATA_EN BIT(16) BIT 1139 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define BM_DATA_EN BIT(17) BIT 1140 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define MFBEN BIT(22) BIT 1141 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define LSIGEN BIT(23) BIT 1142 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define ENMBID BIT(24) BIT 1143 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APP_BASSN BIT(27) BIT 1144 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APP_PHYSTS BIT(28) BIT 1145 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APP_ICV BIT(29) BIT 1146 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APP_MIC BIT(30) BIT 1147 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define APP_FCS BIT(31) BIT 1168 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define RXERR_RPT_RST BIT(27) BIT 1171 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SCR_TXUSEDK BIT(0) BIT 1172 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SCR_RXUSEDK BIT(1) BIT 1173 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SCR_TXENCENABLE BIT(2) BIT 1174 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SCR_RXDECENABLE BIT(3) BIT 1175 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SCR_SKBYA2 BIT(4) BIT 1176 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SCR_NOSKMC BIT(5) BIT 1177 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SCR_TXBCUSEDK BIT(6) BIT 1178 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define SCR_RXBCUSEDK BIT(7) BIT 1182 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define USB_SPEED_MASK BIT(5) BIT 1190 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define USB_AGG_EN BIT(3) BIT 1207 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) BIT 2200 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) BIT 2201 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) BIT 2202 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HAL92C_WOL_DISASSOC_EVENT BIT(2) BIT 2203 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HAL92C_WOL_DEAUTH_EVENT BIT(3) BIT 2204 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4) BIT 2206 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WOL_REASON_PTK_UPDATE BIT(0) BIT 2207 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WOL_REASON_GTK_UPDATE BIT(1) BIT 2208 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WOL_REASON_DISASSOC BIT(2) BIT 2209 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WOL_REASON_DEAUTH BIT(3) BIT 2210 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/reg.h #define WOL_REASON_FW_DISCONNECT BIT(4) BIT 21 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/rf.c 0xfffff3ff) | BIT(10) | BIT(11)); BIT 29 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/rf.c 0xfffff3ff) | BIT(10)); BIT 82 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c rtlpci->transmit_config = CFENDFORM | BIT(15); BIT 62 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c BIT(9)); BIT 358 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c wake_match = BIT(2); BIT 360 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c wake_match = BIT(1); BIT 362 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c wake_match = BIT(0); BIT 29 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(24)); BIT 34 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(25)); BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(26)); BIT 44 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(27)); BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(28)); BIT 54 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 59 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*(__pdesc), BIT(31)); BIT 89 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 2), __val, BIT(12)); BIT 94 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 2), __val, BIT(13)); BIT 99 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 2), __val, BIT(17)); BIT 109 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(8)); BIT 114 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(10)); BIT 119 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(11)); BIT 124 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(12)); BIT 129 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(13)); BIT 134 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(15)); BIT 176 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 5), __val, BIT(12)); BIT 256 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits((__pdesc + 4 * __offset), __val, BIT(31)); BIT 300 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 329 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits(__status, __val, BIT(15)); BIT 334 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits(__status, __val, BIT(16)); BIT 344 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*(__status), BIT(15)); BIT 349 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*(__status), BIT(16)); BIT 380 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*__pdesc, BIT(14)); BIT 385 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*__pdesc, BIT(15)); BIT 400 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*__pdesc, BIT(26)); BIT 405 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*__pdesc, BIT(27)); BIT 410 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*__pdesc, BIT(31)); BIT 415 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h le32p_replace_bits(__pdesc, __val, BIT(30)); BIT 425 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*(__pdesc + 1), BIT(15)); BIT 430 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*(__pdesc + 2), BIT(28)); BIT 440 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(29)); BIT 445 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(30)); BIT 450 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h return le32_get_bits(*(__pdesc + 3), BIT(31)); BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8192se/dm.h #define HAL_DM_DIG_DISABLE BIT(0) /* Disable Dig */ BIT 50 drivers/net/wireless/realtek/rtlwifi/rtl8192se/dm.h #define HAL_DM_HIPWR_DISABLE BIT(1) /* Disable High Power */ BIT 31 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_DIG_ENABLE_CTL BIT(0) BIT 32 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_HIGH_PWR_ENABLE_CTL BIT(1) BIT 33 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_SS_CTL BIT(2) BIT 34 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_RA_INIT_CTL BIT(3) BIT 35 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_RA_BG_CTL BIT(4) BIT 36 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_RA_N_CTL BIT(5) BIT 37 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_PWR_TRK_CTL BIT(6) BIT 38 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_IQK_CTL BIT(7) BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_FA_CTL BIT(8) BIT 40 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_DRIVER_CTRL_DM_CTL BIT(9) BIT 41 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_PAPE_CTL_BY_SW_HW BIT(10) BIT 459 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c bresult = ((tmpvalue & BIT(7)) == (data & BIT(7))); BIT 461 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if ((data & (BIT(6) | BIT(7))) == false) { BIT 469 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if ((tmpvalue & BIT(6))) BIT 545 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0)); BIT 550 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if (tmpu1b & BIT(7)) { BIT 551 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c tmpu1b &= ~(BIT(6) | BIT(7)); BIT 580 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c tmpu1b &= ~(BIT(3)); BIT 593 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); BIT 603 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); BIT 607 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11))); BIT 611 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13))); BIT 619 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); BIT 623 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT 624 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c BIT(4) | BIT(6))); BIT 626 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); BIT 631 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); BIT 639 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11))); BIT 643 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11))); BIT 646 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7))); BIT 649 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15))); BIT 653 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2)))); BIT 656 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6))); BIT 789 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6)); BIT 858 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13)); BIT 860 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8))); BIT 1054 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3))); BIT 1059 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4)); BIT 1060 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c tmp_byte = tmp_byte | BIT(5); BIT 1180 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8))); BIT 1181 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_dword(rtlpriv, TCR, temp | BIT(8)); BIT 1270 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c result = ((tmp & BIT(7)) == (data & BIT(7))); BIT 1272 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if ((data & (BIT(6) | BIT(7))) == false) { BIT 1280 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if ((tmp & BIT(6))) BIT 1311 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c u1btmp |= BIT(0); BIT 1329 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c u1btmp &= ~(BIT(0)); BIT 1339 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if (u1btmp & BIT(7)) { BIT 1340 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c u1btmp &= ~(BIT(6) | BIT(7)); BIT 1396 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if (tmpu1b & BIT(7)) { BIT 1397 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c tmpu1b &= ~(BIT(6) | BIT(7)); BIT 1428 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c tmpu1b &= ~(BIT(3)); BIT 1441 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); BIT 1451 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); BIT 1455 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11))); BIT 1460 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13))); BIT 1466 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); BIT 1469 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); BIT 1477 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11))); BIT 1481 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11))); BIT 1483 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15))); BIT 1487 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2)))); BIT 1490 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6))); BIT 1965 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if (!(tempval & BIT(0))) { BIT 1989 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if (tmp_u1b & BIT(4)) { BIT 1997 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c if (tmp_u1b & BIT(5)) { BIT 71 drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.c rtl_write_byte(rtlpriv, LEDCFG, (ledcfg | BIT(1))); BIT 73 drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.c rtl_write_byte(rtlpriv, LEDCFG, (ledcfg | BIT(3))); BIT 77 drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.c rtl_write_byte(rtlpriv, LEDCFG, (ledcfg | BIT(3))); BIT 111 drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c BIT(8)); BIT 114 drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c BIT(8)); BIT 485 drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c u1btmp |= BIT(0); BIT 1570 drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c while ((regu1 & BIT(5)) && (delay > 0)) { BIT 302 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RXDMA_AGG_EN BIT(7) BIT 308 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ISO_MD2PP BIT(0) BIT 309 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ISO_PA2PCIE BIT(3) BIT 310 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ISO_PLL2MD BIT(4) BIT 311 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ISO_PWC_DV2RP BIT(11) BIT 312 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ISO_PWC_RV2RP BIT(12) BIT 315 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define FEN_MREGEN BIT(15) BIT 316 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define FEN_DCORE BIT(11) BIT 317 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define FEN_CPUEN BIT(10) BIT 319 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define PAD_HWPD_IDN BIT(22) BIT 321 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SYS_CLKSEL_80M BIT(0) BIT 322 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SYS_PS_CLKSEL BIT(1) BIT 323 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SYS_CPU_CLKSEL BIT(2) BIT 324 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SYS_MAC_CLK_EN BIT(11) BIT 325 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SYS_SWHW_SEL BIT(14) BIT 326 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SYS_FWHW_SEL BIT(15) BIT 328 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CMDEEPROM_EN BIT(5) BIT 329 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CMDEERPOMSEL BIT(4) BIT 330 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CMD9346CR_9356SEL BIT(4) BIT 332 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define AFE_MBEN BIT(1) BIT 333 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define AFE_BGEN BIT(0) BIT 335 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SPS1_SWEN BIT(1) BIT 336 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SPS1_LDEN BIT(0) BIT 338 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RF_EN BIT(0) BIT 339 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RF_RSTB BIT(1) BIT 340 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RF_SDMRSTB BIT(2) BIT 342 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define LDA15_EN BIT(0) BIT 344 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define LDV12_EN BIT(0) BIT 345 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define LDV12_SDBY BIT(1) BIT 347 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define XTAL_GATE_AFE BIT(10) BIT 349 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define APLL_EN BIT(0) BIT 351 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define AFR_CARDBEN BIT(0) BIT 352 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define AFR_CLKRUN_SEL BIT(1) BIT 353 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define AFR_FUNCREGEN BIT(2) BIT 355 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define APSDOFF_STATUS BIT(15) BIT 356 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define APSDOFF BIT(14) BIT 357 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define BBRSTN BIT(13) BIT 358 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define BB_GLB_RSTN BIT(12) BIT 359 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SCHEDULE_EN BIT(10) BIT 360 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define MACRXEN BIT(9) BIT 361 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define MACTXEN BIT(8) BIT 362 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define DDMA_EN BIT(7) BIT 363 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define FW2HW_EN BIT(6) BIT 364 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RXDMA_EN BIT(5) BIT 365 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TXDMA_EN BIT(4) BIT 366 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define HCI_RXDMA_EN BIT(3) BIT 367 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define HCI_TXDMA_EN BIT(2) BIT 369 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define STOPHCCA BIT(6) BIT 370 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define STOPHIGH BIT(5) BIT 371 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define STOPMGT BIT(4) BIT 372 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define STOPVO BIT(3) BIT 373 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define STOPVI BIT(2) BIT 374 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define STOPBE BIT(1) BIT 375 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define STOPBK BIT(0) BIT 378 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define LBK_MAC_LB (BIT(0) | BIT(1) | BIT(3)) BIT 379 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define LBK_MAC_DLB (BIT(0) | BIT(1)) BIT 380 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define LBK_DMA_LB (BIT(0) | BIT(1) | BIT(2)) BIT 382 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCP_OFDL_EN BIT(25) BIT 383 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define HWPC_TX_EN BIT(24) BIT 384 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TXDMAPRE2FULL BIT(23) BIT 385 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define DISCW BIT(20) BIT 386 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCRICV BIT(19) BIT 387 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define cfendform BIT(17) BIT 388 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCRCRC BIT(16) BIT 389 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define FAKE_IMEM_EN BIT(15) BIT 390 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TSFRST BIT(9) BIT 391 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TSFEN BIT(8) BIT 392 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define FWALLRDY (BIT(0) | BIT(1) | BIT(2) | \ BIT 393 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h BIT(3) | BIT(4) | BIT(5) | \ BIT 394 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h BIT(6) | BIT(7)) BIT 395 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define FWRDY BIT(7) BIT 396 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define BASECHG BIT(6) BIT 397 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMEM BIT(5) BIT 398 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define DMEM_CODE_DONE BIT(4) BIT 399 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define EXT_IMEM_CHK_RPT BIT(3) BIT 400 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define EXT_IMEM_CODE_DONE BIT(2) BIT 401 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMEM_CHK_RPT BIT(1) BIT 402 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMEM_CODE_DONE BIT(0) BIT 403 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define EMEM_CODE_DONE BIT(2) BIT 404 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define EMEM_CHK_RPT BIT(3) BIT 405 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMEM_RDY BIT(5) BIT 414 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCR_TSFEN BIT(8) BIT 415 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCR_TSFRST BIT(9) BIT 416 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCR_FAKE_IMEM_EN BIT(15) BIT 417 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCR_CRC BIT(16) BIT 418 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCR_ICV BIT(19) BIT 419 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCR_DISCW BIT(20) BIT 420 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCR_HWPC_TX_EN BIT(24) BIT 421 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCR_TCP_OFDL_EN BIT(25) BIT 425 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_APPFCS BIT(31) BIT 426 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_DIS_ENC_2BYTE BIT(30) BIT 427 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_DIS_AES_2BYTE BIT(29) BIT 428 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_HTC_LOC_CTRL BIT(28) BIT 429 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_ENMBID BIT(27) BIT 430 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_RX_TCPOFDL_EN BIT(26) BIT 431 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_APP_PHYST_RXFF BIT(25) BIT 432 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_APP_PHYST_STAFF BIT(24) BIT 433 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_CBSSID BIT(23) BIT 434 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_APWRMGT BIT(22) BIT 435 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_ADD3 BIT(21) BIT 436 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_AMF BIT(20) BIT 437 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_ACF BIT(19) BIT 438 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_ADF BIT(18) BIT 439 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_APP_MIC BIT(17) BIT 440 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_APP_ICV BIT(16) BIT 441 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_RXFTH BIT(13) BIT 442 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_AICV BIT(12) BIT 443 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_RXDESC_LK_EN BIT(11) BIT 444 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_APP_BA_SSN BIT(6) BIT 445 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_ACRC32 BIT(5) BIT 446 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_RXSHFT_EN BIT(4) BIT 447 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_AB BIT(3) BIT 448 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_AM BIT(2) BIT 449 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_APM BIT(1) BIT 450 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_AAP BIT(0) BIT 466 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ENUART BIT(7) BIT 467 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ENJTAG BIT(3) BIT 468 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define BTMODE (BIT(2) | BIT(1)) BIT 469 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ENBT BIT(0) BIT 471 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ENMBID BIT(7) BIT 472 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define BCNUM (BIT(6) | BIT(5) | BIT(4)) BIT 480 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ENSWBCN BIT(15) BIT 492 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_1M BIT(0) BIT 493 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_2M BIT(1) BIT 494 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_5_5M BIT(2) BIT 495 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_11M BIT(3) BIT 496 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_6M BIT(4) BIT 497 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_9M BIT(5) BIT 498 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_12M BIT(6) BIT 499 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_18M BIT(7) BIT 500 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_24M BIT(8) BIT 501 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_36M BIT(9) BIT 502 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_48M BIT(10) BIT 503 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_54M BIT(11) BIT 504 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_MCS0 BIT(12) BIT 505 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_MCS1 BIT(13) BIT 506 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_MCS2 BIT(14) BIT 507 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_MCS3 BIT(15) BIT 508 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_MCS4 BIT(16) BIT 509 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_MCS5 BIT(17) BIT 510 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_MCS6 BIT(18) BIT 511 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RRSR_MCS7 BIT(19) BIT 512 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define BRSR_ACKSHORTPMB BIT(23) BIT 563 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ACMHW_HWEN BIT(0) BIT 564 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ACMHW_BEQEN BIT(1) BIT 565 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ACMHW_VIQEN BIT(2) BIT 566 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ACMHW_VOQEN BIT(3) BIT 567 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ACMHW_BEQSTATUS BIT(4) BIT 568 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ACMHW_VIQSTATUS BIT(5) BIT 569 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define ACMHW_VOQSTATUS BIT(6) BIT 574 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define NAV_UPPER_EN BIT(16) BIT 578 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define BW_OPMODE_20MHZ BIT(2) BIT 579 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define BW_OPMODE_5G BIT(1) BIT 580 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define BW_OPMODE_11J BIT(0) BIT 582 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RXERR_RPT_RST BIT(27) BIT 598 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SCR_TXUSEDK BIT(0) BIT 599 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SCR_RXUSEDK BIT(1) BIT 600 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SCR_TXENCENABLE BIT(2) BIT 601 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SCR_RXENCENABLE BIT(3) BIT 602 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SCR_SKBYA2 BIT(4) BIT 603 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define SCR_NOSKMC BIT(5) BIT 605 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CAM_VALID BIT(15) BIT 607 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CAM_USEDK BIT(5) BIT 618 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CAM_WRITE BIT(16) BIT 620 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CAM_POLLINIG BIT(31) BIT 622 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define WOW_PMEN BIT(0) BIT 623 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define WOW_WOMEN BIT(1) BIT 624 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define WOW_MAGIC BIT(2) BIT 625 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define WOW_UWF BIT(3) BIT 627 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define GPIOMUX_EN BIT(3) BIT 632 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1))) BIT 634 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define HST_RDBUSY BIT(0) BIT 635 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CPU_WTBUSY BIT(1) BIT 638 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_CPUERR BIT(5) BIT 639 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_ATIMEND BIT(4) BIT 640 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_TBDOK BIT(3) BIT 641 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_TBDER BIT(2) BIT 642 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDMAINT8 BIT(1) BIT 643 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDMAINT7 BIT(0) BIT 644 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDMAINT6 BIT(31) BIT 645 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDMAINT5 BIT(30) BIT 646 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDMAINT4 BIT(29) BIT 647 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDMAINT3 BIT(28) BIT 648 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDMAINT2 BIT(27) BIT 649 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDMAINT1 BIT(26) BIT 650 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDOK8 BIT(25) BIT 651 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDOK7 BIT(24) BIT 652 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDOK6 BIT(23) BIT 653 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDOK5 BIT(22) BIT 654 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDOK4 BIT(21) BIT 655 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDOK3 BIT(20) BIT 656 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDOK2 BIT(19) BIT 657 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNDOK1 BIT(18) BIT 658 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_TIMEOUT2 BIT(17) BIT 659 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_TIMEOUT1 BIT(16) BIT 660 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_TXFOVW BIT(15) BIT 661 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_PSTIMEOUT BIT(14) BIT 662 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BCNINT BIT(13) BIT 663 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_RXFOVW BIT(12) BIT 664 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_RDU BIT(11) BIT 665 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_RXCMDOK BIT(10) BIT 666 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BDOK BIT(9) BIT 667 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_HIGHDOK BIT(8) BIT 668 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_COMDOK BIT(7) BIT 669 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_MGNTDOK BIT(6) BIT 670 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_HCCADOK BIT(5) BIT 671 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BKDOK BIT(4) BIT 672 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_BEDOK BIT(3) BIT 673 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_VIDOK BIT(2) BIT 674 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_VODOK BIT(1) BIT 675 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define IMR_ROK BIT(0) BIT 677 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_BKQ BIT(0) BIT 678 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_BEQ BIT(1) BIT 679 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_VIQ BIT(2) BIT 680 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_VOQ BIT(3) BIT 681 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_BQ BIT(4) BIT 682 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_CQ BIT(5) BIT 683 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_MQ BIT(6) BIT 684 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_HQ BIT(7) BIT 685 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_HCCAQ BIT(8) BIT 686 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_STOPBK BIT(9) BIT 687 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_STOPBE BIT(10) BIT 688 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_STOPVI BIT(11) BIT 689 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_STOPVO BIT(12) BIT 690 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_STOPMGT BIT(13) BIT 691 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_STOPHIGH BIT(14) BIT 692 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TPPOLL_STOPHCCA BIT(15) BIT 695 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CCX_CMD_CLM_ENABLE BIT(0) BIT 696 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CCX_CMD_NHM_ENABLE BIT(1) BIT 697 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CCX_CMD_FUNCTION_ENABLE BIT(8) BIT 698 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CCX_CMD_IGNORE_CCA BIT(9) BIT 699 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CCX_CMD_IGNORE_TXON BIT(10) BIT 700 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CCX_CLM_RESULT_READY BIT(16) BIT 701 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define CCX_NHM_RESULT_READY BIT(16) BIT 820 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_9356SEL BIT(6) BIT 824 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define TCR_SAT BIT(24) BIT 827 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define RCR_ONLYERLPKT BIT(31) BIT 855 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define HAL_8192S_HW_GPIO_OFF_BIT BIT(3) BIT 857 drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h #define HAL_8192S_HW_GPIO_WPS_BIT BIT(4) BIT 632 drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c rtl_write_word(rtlpriv, TP_POLL, BIT(0) << (hw_queue)); BIT 17 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define CHIP_8723 BIT(0) BIT 18 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define NORMAL_CHIP BIT(3) BIT 19 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6))) BIT 20 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define RF_TYPE_1T2R BIT(4) BIT 21 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define RF_TYPE_2T2R BIT(5) BIT 22 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define CHIP_VENDOR_UMC BIT(7) BIT 23 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define B_CUT_VERSION BIT(12) BIT 24 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define C_CUT_VERSION BIT(13) BIT 25 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define D_CUT_VERSION ((BIT(12)|BIT(13))) BIT 26 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define E_CUT_VERSION BIT(14) BIT 27 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) BIT 30 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) BIT 31 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define CHIP_TYPE_MASK BIT(3) BIT 32 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) BIT 33 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define MANUFACTUER_MASK BIT(7) BIT 34 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) BIT 35 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) BIT 180 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); BIT 761 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c MASKDWORD) & BIT(3)) >> 3; BIT 794 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c BIT(5), 0x1); BIT 797 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0); BIT 803 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); BIT 804 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); BIT 808 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), BIT 813 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); BIT 815 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c BIT(5), 0x0); BIT 7 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.h #define HAL_DM_DIG_DISABLE BIT(0) BIT 8 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.h #define HAL_DM_HIPWR_DISABLE BIT(1) BIT 23 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/fw.c if (((val_hmetfr >> boxnum) & BIT(0)) == 0 && val_mcutst_1 == 0) BIT 145 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/fw.c boxcontent[0] &= ~(BIT(7)); BIT 155 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/fw.c boxcontent[0] &= ~(BIT(7)); BIT 165 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/fw.c boxcontent[0] &= ~(BIT(7)); BIT 175 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/fw.c boxcontent[0] |= (BIT(7)); BIT 192 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/fw.c boxcontent[0] |= (BIT(7)); BIT 552 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/fw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4)); BIT 25 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BT30 BIT(0) BIT 26 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_HT20 BIT(1) BIT 27 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_HT40 BIT(2) BIT 28 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_LEGACY BIT(3) BIT 30 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_RSSI_LOW BIT(4) BIT 31 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5) BIT 32 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6) BIT 33 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_DEC_BT_POWER BIT(7) BIT 35 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_IDLE BIT(8) BIT 36 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_UPLINK BIT(9) BIT 37 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_DOWNLINK BIT(10) BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BT_INQ_PAGE BIT(11) BIT 40 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BT_IDLE BIT(12) BIT 41 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BT_UPLINK BIT(13) BIT 42 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BT_DOWNLINK BIT(14) BIT 44 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_HOLD_FOR_BT_OPERATION BIT(15) BIT 45 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BT_RSSI_LOW BIT(19) BIT 47 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_PROFILE_HID BIT(20) BIT 48 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_PROFILE_A2DP BIT(21) BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_PROFILE_PAN BIT(22) BIT 50 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_PROFILE_SCO BIT(23) BIT 52 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_RSSI_1_LOW BIT(24) BIT 53 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_RSSI_1_MEDIUM BIT(25) BIT 54 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_WIFI_RSSI_1_HIGH BIT(26) BIT 56 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BTINFO_COMMON BIT(30) BIT 57 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BTINFO_B_HID_SCOESCO BIT(31) BIT 58 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BTINFO_B_FTP_A2DP BIT(29) BIT 60 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BT_CNT_LEVEL_0 BIT(0) BIT 61 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BT_CNT_LEVEL_1 BIT(1) BIT 62 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BT_CNT_LEVEL_2 BIT(2) BIT 63 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BT_COEX_STATE_BT_CNT_LEVEL_3 BIT(3) BIT 102 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BTINFO_B_FTP BIT(7) BIT 103 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BTINFO_B_A2DP BIT(6) BIT 104 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BTINFO_B_HID BIT(5) BIT 105 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BTINFO_B_SCO_BUSY BIT(4) BIT 106 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BTINFO_B_ACL_BUSY BIT(3) BIT 107 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BTINFO_B_INQ_PAGE BIT(2) BIT 108 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BTINFO_B_SCO_ESCO BIT(1) BIT 109 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.h #define BTINFO_B_CONNECTION BIT(0) BIT 205 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c tmp_u1 |= BIT(0); BIT 209 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c tmp_u1 &= ~BIT(2); BIT 214 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c tmp_u1 |= BIT(2); BIT 383 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(1); BIT 401 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(0); BIT 405 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(1); /* Dac Swing default enable */ BIT 429 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter1[0] |= BIT(0); BIT 433 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(0); /* function enable */ BIT 437 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(1); BIT 452 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(2); BIT 461 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(4); BIT 491 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(0); /* function enable */ BIT 524 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(0); /* function enable */ BIT 528 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(1); BIT 543 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[1] |= BIT(0); BIT 582 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(0); BIT 1514 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c h2c_parameter[0] |= BIT(0); BIT 1673 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.c if (bt_info & BIT(2)) BIT 45 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); BIT 48 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c tmp1byte &= ~(BIT(0)); BIT 58 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); BIT 61 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c tmp1byte |= BIT(1); BIT 67 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1)); BIT 72 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0); BIT 375 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); BIT 395 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c if (rpwm_val & BIT(7)) { BIT 400 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c ((*(u8 *)val) | BIT(7))); BIT 428 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c (tmp_regcr | BIT(0))); BIT 430 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 431 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 436 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c if (tmp_reg422 & BIT(6)) BIT 439 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c tmp_reg422 & (~BIT(6))); BIT 443 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 444 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 453 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c (tmp_regcr & ~(BIT(0)))); BIT 479 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 486 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 637 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7)); BIT 683 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4)); BIT 687 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7)); BIT 762 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); BIT 766 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c } while ((retry < 200) && (bytetmp & BIT(7))); BIT 983 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); BIT 1010 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c if (!(tmp_u1b & BIT(0))) { BIT 1015 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c if (!(tmp_u1b & BIT(4))) { BIT 1183 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 1186 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 1270 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && BIT 1277 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); BIT 1289 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); BIT 1291 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); BIT 1533 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) BIT 1536 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) BIT 1813 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c if (tmp_u1b & BIT(4)) { BIT 1820 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c if (tmp_u1b & BIT(5)) { BIT 2104 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1))); BIT 2109 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; BIT 2111 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; BIT 2361 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c if (tmpu_32 & BIT(18)) BIT 30 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c ledcfg &= ~BIT(6); BIT 32 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5)); BIT 63 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3))); BIT 68 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c ledcfg &= ~BIT(6); BIT 70 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c (ledcfg | BIT(3) | BIT(5))); BIT 76 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg|BIT(3)); BIT 151 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b|BIT(1))); BIT 164 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+1, (tmpu1b & (~BIT(6)))); BIT 168 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, (tmpu1b & (~BIT(4)))); BIT 777 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); BIT 786 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0); BIT 788 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), BIT 1042 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c if (!(reg_eac & BIT(28)) && BIT 1049 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c if (!(reg_eac & BIT(27)) && BIT 1070 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c if (!(reg_eac & BIT(31)) && BIT 1076 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c if (!(reg_eac & BIT(30)) && BIT 1169 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c BIT(8)); BIT 1314 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01); BIT 1315 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); BIT 1320 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c BIT(5) | BIT(6), 0x1); BIT 1323 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c BIT(5) | BIT(6), 0x2); BIT 46 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\ BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\ BIT 52 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\ BIT 55 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\ BIT 58 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\ BIT 61 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\ BIT 63 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, BIT 73 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\ BIT 75 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ BIT 77 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, BIT 85 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h BIT(4)|BIT(3), (BIT(4)|BIT(3))},\ BIT 91 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h BIT(3)|BIT(4), BIT(3)}, \ BIT 95 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(3)|BIT(4), \ BIT 96 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h BIT(3)|BIT(4)}, \ BIT 100 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 104 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_POLLING, BIT(1), 0}, BIT 112 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\ BIT 115 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\ BIT 118 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, BIT 127 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \ BIT 131 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(2), BIT(2)}, \ BIT 135 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 139 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_POLLING, BIT(1), 0}, BIT 148 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(0), 0}, \ BIT 152 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_POLLING, BIT(1), BIT(1)},\ BIT 156 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\ BIT 167 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\ BIT 170 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/ BIT 177 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/ BIT 208 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(0), 0},\ BIT 214 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \ BIT 220 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \ BIT 224 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(5), BIT(5)},\ BIT 244 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(4), 0}, \ BIT 248 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_POLLING, BIT(7), 0}, \ BIT 252 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\ BIT 256 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(1), BIT(1)},\ BIT 264 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\ BIT 320 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CMDEEPROM_EN BIT(5) BIT 321 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CMDEEPROM_SEL BIT(4) BIT 322 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CMD9346CR_9356SEL BIT(4) BIT 327 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define GPIOSEL_ENBT BIT(5) BIT 345 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_1M BIT(0) BIT 346 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_2M BIT(1) BIT 347 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_5_5M BIT(2) BIT 348 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_11M BIT(3) BIT 349 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_6M BIT(4) BIT 350 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_9M BIT(5) BIT 351 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_12M BIT(6) BIT 352 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_18M BIT(7) BIT 353 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_24M BIT(8) BIT 354 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_36M BIT(9) BIT 355 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_48M BIT(10) BIT 356 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_54M BIT(11) BIT 357 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_MCS0 BIT(12) BIT 358 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_MCS1 BIT(13) BIT 359 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_MCS2 BIT(14) BIT 360 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_MCS3 BIT(15) BIT 361 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_MCS4 BIT(16) BIT 362 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_MCS5 BIT(17) BIT 363 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_MCS6 BIT(18) BIT 364 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RRSR_MCS7 BIT(19) BIT 365 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BRSR_ACKSHORTPMB BIT(23) BIT 396 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_1M BIT(0) BIT 397 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_2M BIT(1) BIT 398 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_5_5M BIT(2) BIT 399 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_11M BIT(3) BIT 400 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_6M BIT(4) BIT 401 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_9M BIT(5) BIT 402 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_12M BIT(6) BIT 403 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_18M BIT(7) BIT 404 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_24M BIT(8) BIT 405 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_36M BIT(9) BIT 406 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_48M BIT(10) BIT 407 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_54M BIT(11) BIT 408 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS0 BIT(12) BIT 409 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS1 BIT(13) BIT 410 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS2 BIT(14) BIT 411 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS3 BIT(15) BIT 412 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS4 BIT(16) BIT 413 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS5 BIT(17) BIT 414 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS6 BIT(18) BIT 415 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS7 BIT(19) BIT 416 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS8 BIT(20) BIT 417 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS9 BIT(21) BIT 418 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS10 BIT(22) BIT 419 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS11 BIT(23) BIT 420 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS12 BIT(24) BIT 421 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS13 BIT(25) BIT 422 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS14 BIT(26) BIT 423 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RATE_MCS15 BIT(27) BIT 435 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BW_OPMODE_20MHZ BIT(2) BIT 436 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BW_OPMODE_5G BIT(1) BIT 437 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BW_OPMODE_11J BIT(0) BIT 439 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CAM_VALID BIT(15) BIT 441 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CAM_USEDK BIT(5) BIT 452 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CAM_WRITE BIT(16) BIT 454 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CAM_POLLINIG BIT(31) BIT 460 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WOW_PMEN BIT(0) BIT 461 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WOW_WOMEN BIT(1) BIT 462 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WOW_MAGIC BIT(2) BIT 463 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WOW_UWF BIT(3) BIT 466 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDMAINT6 BIT(31) BIT 467 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDMAINT5 BIT(30) BIT 468 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDMAINT4 BIT(29) BIT 469 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDMAINT3 BIT(28) BIT 470 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDMAINT2 BIT(27) BIT 471 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDMAINT1 BIT(26) BIT 472 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDOK8 BIT(25) BIT 473 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDOK7 BIT(24) BIT 474 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDOK6 BIT(23) BIT 475 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDOK5 BIT(22) BIT 476 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDOK4 BIT(21) BIT 477 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDOK3 BIT(20) BIT 478 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDOK2 BIT(19) BIT 479 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNDOK1 BIT(18) BIT 480 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_TIMEOUT2 BIT(17) BIT 481 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_TIMEOUT1 BIT(16) BIT 482 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_TXFOVW BIT(15) BIT 483 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_PSTIMEOUT BIT(14) BIT 484 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BCNINT BIT(13) BIT 485 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_RXFOVW BIT(12) BIT 486 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_RDU BIT(11) BIT 487 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_ATIMEND BIT(10) BIT 488 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BDOK BIT(9) BIT 489 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_HIGHDOK BIT(8) BIT 490 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_TBDOK BIT(7) BIT 491 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_MGNTDOK BIT(6) BIT 492 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_TBDER BIT(5) BIT 493 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BKDOK BIT(4) BIT 494 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_BEDOK BIT(3) BIT 495 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_VIDOK BIT(2) BIT 496 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_VODOK BIT(1) BIT 497 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_ROK BIT(0) BIT 499 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_TXERR BIT(11) BIT 500 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_RXERR BIT(10) BIT 501 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_CPWM BIT(8) BIT 502 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_OCPINT BIT(1) BIT 503 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IMR_WLANOFF BIT(0) BIT 507 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_TIMEOUT2 BIT(31) BIT 508 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_TIMEOUT1 BIT(30) BIT 509 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_PSTIMEOUT BIT(29) BIT 510 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_GTINT4 BIT(28) BIT 511 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_GTINT3 BIT(27) BIT 512 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_TXBCNERR BIT(26) BIT 513 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_TXBCNOK BIT(25) BIT 514 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_TSF_BIT32_TOGGLE BIT(24) BIT 515 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDMAINT3 BIT(23) BIT 516 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDMAINT2 BIT(22) BIT 517 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDMAINT1 BIT(21) BIT 518 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDMAINT0 BIT(20) BIT 519 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDOK3 BIT(19) BIT 520 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDOK2 BIT(18) BIT 521 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDOK1 BIT(17) BIT 522 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDOK0 BIT(16) BIT 523 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_HSISR_IND_ON BIT(15) BIT 524 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDMAINT_E BIT(14) BIT 525 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_ATIMEND_E BIT(13) BIT 526 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_ATIM_CTW_END BIT(12) BIT 527 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_HISRE_IND BIT(11) BIT 528 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_C2HCMD BIT(10) BIT 529 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_CPWM2 BIT(9) BIT 530 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_CPWM BIT(8) BIT 531 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_HIGHDOK BIT(7) BIT 532 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_MGNTDOK BIT(6) BIT 533 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BKDOK BIT(5) BIT 534 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BEDOK BIT(4) BIT 535 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_VIDOK BIT(3) BIT 536 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_VODOK BIT(2) BIT 537 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_RDU BIT(1) BIT 538 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_ROK BIT(0) BIT 541 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDMAINT7 BIT(23) BIT 542 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDMAINT6 BIT(22) BIT 543 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDMAINT5 BIT(21) BIT 544 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDMAINT4 BIT(20) BIT 545 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDOK7 BIT(19) BIT 546 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDOK6 BIT(18) BIT 547 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDOK5 BIT(17) BIT 548 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_BCNDOK4 BIT(16) BIT 550 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_TXERR BIT(11) BIT 551 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_RXERR BIT(10) BIT 552 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_TXFOVW BIT(9) BIT 553 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_RXFOVW BIT(8) BIT 555 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHIMR_OCPINT BIT(1) BIT 658 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define STOPBECON BIT(6) BIT 659 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define STOPHIGHT BIT(5) BIT 660 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define STOPMGT BIT(4) BIT 661 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define STOPVO BIT(3) BIT 662 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define STOPVI BIT(2) BIT 663 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define STOPBE BIT(1) BIT 664 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define STOPBK BIT(0) BIT 666 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_APPFCS BIT(31) BIT 667 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_APP_MIC BIT(30) BIT 668 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_APP_ICV BIT(29) BIT 669 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_APP_PHYST_RXFF BIT(28) BIT 670 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_APP_BA_SSN BIT(27) BIT 671 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_ENMBID BIT(24) BIT 672 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_LSIGEN BIT(23) BIT 673 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_MFBEN BIT(22) BIT 674 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_HTC_LOC_CTRL BIT(14) BIT 675 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_AMF BIT(13) BIT 676 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_ACF BIT(12) BIT 677 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_ADF BIT(11) BIT 678 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_AICV BIT(9) BIT 679 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_ACRC32 BIT(8) BIT 680 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_CBSSID_BCN BIT(7) BIT 681 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_CBSSID_DATA BIT(6) BIT 683 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_APWRMGT BIT(5) BIT 684 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_ADD3 BIT(4) BIT 685 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_AB BIT(3) BIT 686 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_AM BIT(2) BIT 687 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_APM BIT(1) BIT 688 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RCR_AAP BIT(0) BIT 710 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SW18_FPWM BIT(3) BIT 712 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ISO_MD2PP BIT(0) BIT 713 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ISO_UA2USB BIT(1) BIT 714 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ISO_UD2CORE BIT(2) BIT 715 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ISO_PA2PCIE BIT(3) BIT 716 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ISO_PD2CORE BIT(4) BIT 717 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ISO_IP2MAC BIT(5) BIT 718 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ISO_DIOP BIT(6) BIT 719 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ISO_DIOE BIT(7) BIT 720 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ISO_EB2CORE BIT(8) BIT 721 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ISO_DIOR BIT(9) BIT 723 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PWC_EV25V BIT(14) BIT 724 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PWC_EV12V BIT(15) BIT 726 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_BBRSTB BIT(0) BIT 727 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_BB_GLB_RSTN BIT(1) BIT 728 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_USBA BIT(2) BIT 729 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_UPLL BIT(3) BIT 730 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_USBD BIT(4) BIT 731 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_DIO_PCIE BIT(5) BIT 732 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_PCIEA BIT(6) BIT 733 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_PPLL BIT(7) BIT 734 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_PCIED BIT(8) BIT 735 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_DIOE BIT(9) BIT 736 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_CPUEN BIT(10) BIT 737 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_DCORE BIT(11) BIT 738 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_ELDR BIT(12) BIT 739 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_DIO_RF BIT(13) BIT 740 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_HWPDN BIT(14) BIT 741 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FEN_MREGEN BIT(15) BIT 743 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PFM_LDALL BIT(0) BIT 744 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PFM_ALDN BIT(1) BIT 745 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PFM_LDKP BIT(2) BIT 746 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PFM_WOWL BIT(3) BIT 747 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ENPDN BIT(4) BIT 748 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PDN_PL BIT(5) BIT 749 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APFM_ONMAC BIT(8) BIT 750 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APFM_OFF BIT(9) BIT 751 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APFM_RSM BIT(10) BIT 752 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define AFSM_HSUS BIT(11) BIT 753 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define AFSM_PCIE BIT(12) BIT 754 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APDM_MAC BIT(13) BIT 755 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APDM_HOST BIT(14) BIT 756 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APDM_HPDN BIT(15) BIT 757 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RDY_MACON BIT(16) BIT 758 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SUS_HOST BIT(17) BIT 759 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ROP_ALD BIT(20) BIT 760 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ROP_PWR BIT(21) BIT 761 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ROP_SPS BIT(22) BIT 762 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SOP_MRST BIT(25) BIT 763 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SOP_FUSE BIT(26) BIT 764 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SOP_ABG BIT(27) BIT 765 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SOP_AMB BIT(28) BIT 766 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SOP_RCK BIT(29) BIT 767 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SOP_A8M BIT(30) BIT 768 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define XOP_BTCK BIT(31) BIT 770 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ANAD16V_EN BIT(0) BIT 771 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ANA8M BIT(1) BIT 772 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define MACSLP BIT(4) BIT 773 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LOADER_CLK_EN BIT(5) BIT 774 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define _80M_SSC_DIS BIT(7) BIT 775 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define _80M_SSC_EN_HO BIT(8) BIT 776 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PHY_SSC_RSTB BIT(9) BIT 777 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SEC_CLK_EN BIT(10) BIT 778 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define MAC_CLK_EN BIT(11) BIT 779 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SYS_CLK_EN BIT(12) BIT 780 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RING_CLK_EN BIT(13) BIT 782 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BOOT_FROM_EEPROM BIT(4) BIT 783 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define EEPROM_EN BIT(5) BIT 785 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define AFE_BGEN BIT(0) BIT 786 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define AFE_MBEN BIT(1) BIT 787 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define MAC_ID_EN BIT(7) BIT 789 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WLOCK_ALL BIT(0) BIT 790 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WLOCK_00 BIT(1) BIT 791 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WLOCK_04 BIT(2) BIT 792 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WLOCK_08 BIT(3) BIT 793 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WLOCK_40 BIT(4) BIT 794 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define R_DIS_PRST_0 BIT(5) BIT 795 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define R_DIS_PRST_1 BIT(6) BIT 796 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LOCK_ALL_EN BIT(7) BIT 798 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RF_EN BIT(0) BIT 799 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RF_RSTB BIT(1) BIT 800 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RF_SDMRSTB BIT(2) BIT 802 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LDA15_EN BIT(0) BIT 803 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LDA15_STBY BIT(1) BIT 804 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LDA15_OBUF BIT(2) BIT 805 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LDA15_REG_VOS BIT(3) BIT 808 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LDV12_EN BIT(0) BIT 809 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LDV12_SDBY BIT(1) BIT 810 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LPLDO_HSM BIT(2) BIT 811 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LPLDO_LSM_DIS BIT(3) BIT 814 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define XTAL_EN BIT(0) BIT 815 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define XTAL_BSEL BIT(1) BIT 818 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define XTAL_GATE_USB BIT(8) BIT 820 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define XTAL_GATE_AFE BIT(11) BIT 822 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define XTAL_RF_GATE BIT(14) BIT 824 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define XTAL_GATE_DIG BIT(17) BIT 826 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define XTAL_BT_GATE BIT(20) BIT 830 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CKDLY_AFE BIT(26) BIT 831 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CKDLY_USB BIT(27) BIT 832 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CKDLY_DIG BIT(28) BIT 833 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CKDLY_BT BIT(29) BIT 835 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APLL_EN BIT(0) BIT 836 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APLL_320_EN BIT(1) BIT 837 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APLL_FREF_SEL BIT(2) BIT 838 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APLL_EDGE_SEL BIT(3) BIT 839 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APLL_WDOGB BIT(4) BIT 840 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APLL_LPFEN BIT(5) BIT 850 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APLL_320EN BIT(14) BIT 851 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APLL_80EN BIT(15) BIT 852 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APLL_1MEN BIT(24) BIT 854 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ALD_EN BIT(18) BIT 855 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define EF_PD BIT(19) BIT 856 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define EF_FLAG BIT(31) BIT 858 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define EF_TRPT BIT(7) BIT 859 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LDOE25_EN BIT(31) BIT 861 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RSM_EN BIT(0) BIT 862 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TIMER_EN BIT(4) BIT 864 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TRSW0EN BIT(2) BIT 865 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TRSW1EN BIT(3) BIT 866 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define EROM_EN BIT(4) BIT 867 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ENBT BIT(5) BIT 868 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ENUART BIT(8) BIT 869 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define UART_910 BIT(9) BIT 870 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ENPMAC BIT(10) BIT 871 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SIC_SWRST BIT(11) BIT 872 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ENSIC BIT(12) BIT 873 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SIC_23 BIT(13) BIT 874 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ENHDP BIT(14) BIT 875 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SIC_LBK BIT(15) BIT 877 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LED0PL BIT(4) BIT 878 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LED1PL BIT(12) BIT 879 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LED0DIS BIT(7) BIT 881 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define MCUFWDL_EN BIT(0) BIT 882 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define MCUFWDL_RDY BIT(1) BIT 883 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define FWDL_CHKSUM_RPT BIT(2) BIT 884 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define MACINI_RDY BIT(3) BIT 885 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BBINI_RDY BIT(4) BIT 886 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RFINI_RDY BIT(5) BIT 887 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WINTINI_RDY BIT(6) BIT 888 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CPRST BIT(23) BIT 890 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define XCLK_VLD BIT(0) BIT 891 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACLK_VLD BIT(1) BIT 892 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define UCLK_VLD BIT(2) BIT 893 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PCLK_VLD BIT(3) BIT 894 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PCIRSTB BIT(4) BIT 895 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define V15_VLD BIT(5) BIT 896 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TRP_B15V_EN BIT(7) BIT 897 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SIC_IDLE BIT(8) BIT 898 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BD_MAC2 BIT(9) BIT 899 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BD_MAC1 BIT(10) BIT 900 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define IC_MACPHY_MODE BIT(11) BIT 901 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BT_FUNC BIT(16) BIT 902 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define VENDOR_ID BIT(19) BIT 903 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PAD_HWPD_IDN BIT(22) BIT 904 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TRP_VAUX_EN BIT(23) BIT 905 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TRP_BT_EN BIT(24) BIT 906 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BD_PKG_SEL BIT(25) BIT 907 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BD_HCI_SEL BIT(26) BIT 908 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TYPE_ID BIT(27) BIT 915 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HCI_TXDMA_EN BIT(0) BIT 916 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HCI_RXDMA_EN BIT(1) BIT 917 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TXDMA_EN BIT(2) BIT 918 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RXDMA_EN BIT(3) BIT 919 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PROTOCOL_EN BIT(4) BIT 920 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SCHEDULE_EN BIT(5) BIT 921 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define MACTXEN BIT(6) BIT 922 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define MACRXEN BIT(7) BIT 923 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ENSWBCN BIT(8) BIT 924 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ENSEC BIT(9) BIT 954 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RXDMA_ARBBW_EN BIT(0) BIT 955 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RXSHFT_EN BIT(1) BIT 956 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RXDMA_AGG_EN BIT(2) BIT 957 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define QS_VO_QUEUE BIT(8) BIT 958 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define QS_VI_QUEUE BIT(9) BIT 959 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define QS_BE_QUEUE BIT(10) BIT 960 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define QS_BK_QUEUE BIT(11) BIT 961 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define QS_MANAGER_QUEUE BIT(12) BIT 962 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define QS_HIGH_QUEUE BIT(13) BIT 964 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HQSEL_VOQ BIT(0) BIT 965 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HQSEL_VIQ BIT(1) BIT 966 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HQSEL_BEQ BIT(2) BIT 967 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HQSEL_BKQ BIT(3) BIT 968 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HQSEL_MGTQ BIT(4) BIT 969 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HQSEL_HIQ BIT(5) BIT 991 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) BIT 992 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BB_WRITE_EN BIT(30) BIT 993 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BB_READ_EN BIT(31) BIT 1000 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HPQ_PUBLIC_DIS BIT(24) BIT 1001 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LPQ_PUBLIC_DIS BIT(25) BIT 1002 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LD_RQPN BIT(31) BIT 1004 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BCN_VALID BIT(16) BIT 1011 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define DROP_DATA_EN BIT(9) BIT 1013 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define EN_AMPDU_RTY_NEW BIT(7) BIT 1030 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define USE_SHORT_G1 BIT(20) BIT 1085 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define DIS_EDCA_CNT_DWN BIT(11) BIT 1087 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define EN_MBSSID BIT(1) BIT 1088 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define EN_TXBCN_RPT BIT(2) BIT 1089 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define EN_BCN_FUNCTION BIT(3) BIT 1091 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TSFTR_RST BIT(0) BIT 1092 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TSFTR1_RST BIT(1) BIT 1094 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define STOP_BCNQ BIT(6) BIT 1096 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) BIT 1097 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define DIS_TSF_UDT0_TEST_CHIP BIT(5) BIT 1099 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACMHW_HWEN BIT(0) BIT 1100 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACMHW_BEQEN BIT(1) BIT 1101 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACMHW_VIQEN BIT(2) BIT 1102 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACMHW_VOQEN BIT(3) BIT 1103 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACMHW_BEQSTATUS BIT(4) BIT 1104 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACMHW_VIQSTATUS BIT(5) BIT 1105 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACMHW_VOQSTATUS BIT(6) BIT 1107 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APSDOFF BIT(6) BIT 1108 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APSDOFF_STATUS BIT(7) BIT 1110 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BW_20MHZ BIT(2) BIT 1116 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define TSFRST BIT(0) BIT 1117 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define DIS_GCLK BIT(1) BIT 1118 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PAD_SEL BIT(2) BIT 1119 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PWR_ST BIT(6) BIT 1120 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define PWRBIT_OW_EN BIT(7) BIT 1121 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACRC BIT(8) BIT 1122 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CFENDFORM BIT(9) BIT 1123 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ICV BIT(10) BIT 1125 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define AAP BIT(0) BIT 1126 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APM BIT(1) BIT 1127 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define AM BIT(2) BIT 1128 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define AB BIT(3) BIT 1129 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ADD3 BIT(4) BIT 1130 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APWRMGT BIT(5) BIT 1131 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CBSSID BIT(6) BIT 1132 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CBSSID_DATA BIT(6) BIT 1133 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define CBSSID_BCN BIT(7) BIT 1134 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACRC32 BIT(8) BIT 1135 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define AICV BIT(9) BIT 1136 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ADF BIT(11) BIT 1137 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ACF BIT(12) BIT 1138 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define AMF BIT(13) BIT 1139 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HTC_LOC_CTRL BIT(14) BIT 1140 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define UC_DATA_EN BIT(16) BIT 1141 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define BM_DATA_EN BIT(17) BIT 1142 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define MFBEN BIT(22) BIT 1143 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define LSIGEN BIT(23) BIT 1144 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define ENMBID BIT(24) BIT 1145 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APP_BASSN BIT(27) BIT 1146 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APP_PHYSTS BIT(28) BIT 1147 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APP_ICV BIT(29) BIT 1148 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APP_MIC BIT(30) BIT 1149 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define APP_FCS BIT(31) BIT 1170 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define RXERR_RPT_RST BIT(27) BIT 1173 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SCR_TXUSEDK BIT(0) BIT 1174 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SCR_RXUSEDK BIT(1) BIT 1175 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SCR_TXENCENABLE BIT(2) BIT 1176 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SCR_RXDECENABLE BIT(3) BIT 1177 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SCR_SKBYA2 BIT(4) BIT 1178 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SCR_NOSKMC BIT(5) BIT 1179 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SCR_TXBCUSEDK BIT(6) BIT 1180 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define SCR_RXBCUSEDK BIT(7) BIT 1184 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define USB_SPEED_MASK BIT(5) BIT 1192 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define USB_AGG_EN BIT(3) BIT 1209 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) BIT 2094 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WL_HWPDN_EN BIT(0) BIT 2096 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/reg.h #define WL_HWPDN_SL BIT(1) BIT 86 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); BIT 61 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c BIT(9)); BIT 690 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4)); BIT 693 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c BIT(0) << (hw_queue)); BIT 29 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(24)); BIT 34 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(25)); BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(26)); BIT 44 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(27)); BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(28)); BIT 54 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 59 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*__pdesc, BIT(31)); BIT 69 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 1), __val, BIT(5)); BIT 74 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 1), __val, BIT(7)); BIT 94 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 2), __val, BIT(17)); BIT 115 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(31)); BIT 130 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(8)); BIT 135 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(10)); BIT 140 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(11)); BIT 145 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(12)); BIT 150 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(13)); BIT 160 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(25)); BIT 165 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(26)); BIT 170 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 4), __val, BIT(27)); BIT 190 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits((__pdesc + 5), __val, BIT(6)); BIT 235 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*__pdesc, BIT(14)); BIT 240 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*__pdesc, BIT(15)); BIT 255 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*__pdesc, BIT(26)); BIT 260 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*__pdesc, BIT(27)); BIT 265 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*__pdesc, BIT(31)); BIT 275 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(30)); BIT 280 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 285 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*(__pdesc + 1), BIT(14)); BIT 290 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*(__pdesc + 1), BIT(15)); BIT 300 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*(__pdesc + 3), BIT(6)); BIT 305 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*(__pdesc + 3), BIT(8)); BIT 310 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h return le32_get_bits(*(__pdesc + 3), BIT(9)); BIT 13 drivers/net/wireless/realtek/rtlwifi/rtl8723be/def.h #define CHIP_8723B (BIT(1) | BIT(2)) BIT 14 drivers/net/wireless/realtek/rtlwifi/rtl8723be/def.h #define NORMAL_CHIP BIT(3) BIT 15 drivers/net/wireless/realtek/rtlwifi/rtl8723be/def.h #define CHIP_VENDOR_SMIC BIT(8) BIT 17 drivers/net/wireless/realtek/rtlwifi/rtl8723be/def.h #define EXT_VENDOR_ID (BIT(18) | BIT(19)) BIT 516 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); BIT 517 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); BIT 541 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(12), 1); BIT 542 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(14), 1); BIT 565 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 1); BIT 566 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 0); BIT 567 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 1); BIT 568 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 0); BIT 570 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0); BIT 571 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 0); BIT 573 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0); BIT 574 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2); BIT 576 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0); BIT 577 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2); BIT 628 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), BIT 640 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 0x00); BIT 891 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) | BIT(16), BIT 1118 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11), BIT 1196 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11), BIT 1202 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.c rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11), BIT 152 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.h #define HAL_DM_DIG_DISABLE BIT(0) BIT 153 drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.h #define HAL_DM_HIPWR_DISABLE BIT(1) BIT 21 drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.c if (((val_hmetfr >> boxnum) & BIT(0)) == 0) BIT 270 drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.c if ((rlbm == 2) && (byte5 & BIT(4))) { BIT 657 drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4)); BIT 22 drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.h #define FW_PS_RF_ON BIT(2) BIT 23 drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.h #define FW_PS_REGISTER_ACTIVE BIT(3) BIT 25 drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.h #define FW_PS_ACK BIT(6) BIT 26 drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.h #define FW_PS_TOGGLE BIT(7) BIT 30 drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.h #define FW_PS_CLOCK_OFF BIT(0) /* 32k*/ BIT 69 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); BIT 72 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp1byte &= ~(BIT(0)); BIT 82 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); BIT 85 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp1byte |= BIT(1); BIT 91 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1)); BIT 96 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0); BIT 349 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c (tmp_regcr | BIT(0))); BIT 351 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 352 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 355 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6))); BIT 356 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (tmp_reg422 & BIT(6)) BIT 362 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c (bcnvalid_reg | BIT(0))); BIT 368 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c while (!(bcnvalid_reg & BIT(0)) && count < 20) { BIT 375 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); BIT 377 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (bcnvalid_reg & BIT(0)) BIT 378 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0)); BIT 380 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 381 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 387 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0)))); BIT 617 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); BIT 634 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (rpwm_val & BIT(7)) { BIT 638 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c ((*(u8 *)val) | BIT(7))); BIT 687 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 694 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 817 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); BIT 833 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3)); BIT 835 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); BIT 849 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (bytetmp & BIT(0)) { BIT 851 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6)); BIT 855 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3)); BIT 857 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4))); BIT 871 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6)); BIT 918 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */ BIT 919 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */ BIT 920 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */; BIT 921 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */; BIT 922 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */; BIT 923 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */; BIT 925 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */; BIT 928 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2))); BIT 1015 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12)); BIT 1035 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6)); BIT 1036 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); BIT 1040 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); BIT 1055 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5)); BIT 1056 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); BIT 1060 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); BIT 1109 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7) | BIT 1116 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4)); BIT 1167 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && BIT 1174 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); BIT 1186 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); BIT 1188 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); BIT 1201 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (!(tmp & BIT(2))) { BIT 1202 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2))); BIT 1210 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if ((tmp & BIT(0)) || (tmp & BIT(1))) { BIT 1238 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp &= ~(BIT(1) | BIT(0)); BIT 1241 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp |= BIT(2); BIT 1249 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (tmp & BIT(2)) { BIT 1253 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); BIT 1272 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp &= ~(BIT(0)); BIT 1279 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp |= BIT(0); BIT 1298 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp |= BIT(1); BIT 1314 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c (tmp & (~BIT(2)))); BIT 1324 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp &= ~(BIT(2)); BIT 1404 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11)); BIT 1439 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (tmp_u1b & BIT(2)) { BIT 1441 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c tmp_u1b &= (~BIT(2)); BIT 1568 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 1571 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 1802 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (pw2g->bw20_diff[path][cnt] & BIT(3)) BIT 1813 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (pw2g->ofdm_diff[path][cnt] & BIT(3)) BIT 1825 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (pw2g->bw40_diff[path][cnt] & BIT(3)) BIT 1835 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (pw2g->bw20_diff[path][cnt] & BIT(3)) BIT 1846 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (pw2g->ofdm_diff[path][cnt] & BIT(3)) BIT 1856 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (pw2g->cck_diff[path][cnt] & BIT(3)) BIT 1880 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (pw5g->bw20_diff[path][cnt] & BIT(3)) BIT 1890 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (pw5g->ofdm_diff[path][cnt] & BIT(3)) BIT 1901 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (pw5g->bw40_diff[path][cnt] & BIT(3)) BIT 1910 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (pw5g->bw20_diff[path][cnt] & BIT(3)) BIT 1935 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c else if (pw5g->ofdm_diff[path][cnt] & BIT(3)) BIT 2099 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */ BIT 2261 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (tmp_u1b & BIT(4)) { BIT 2268 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (tmp_u1b & BIT(5)) { BIT 2442 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 2493 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1))); BIT 2498 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; BIT 2500 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; BIT 2672 drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c if (tmpu_32 & BIT(18)) BIT 30 drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c ledcfg &= ~BIT(6); BIT 31 drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5)); BIT 62 drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3))); BIT 67 drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c ledcfg &= ~BIT(6); BIT 69 drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c (ledcfg | BIT(3) | BIT(5))); BIT 75 drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg|BIT(3)); BIT 108 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c regval | BIT(13) | BIT(0) | BIT(1)); BIT 115 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); BIT 142 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0)); BIT 144 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c u8 board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */ BIT 145 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c ((rtlhal->board_type & BIT(3)) >> 3) << 1 | /* _GPA */ BIT 146 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c ((rtlhal->board_type & BIT(7)) >> 7) << 2 | /* _ALNA */ BIT 147 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c ((rtlhal->board_type & BIT(6)) >> 6) << 3 | /* _APA */ BIT 148 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c ((rtlhal->board_type & BIT(2)) >> 2) << 4; /* _BT */ BIT 198 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if ((cond1 & BIT(0)) != 0) /*GLNA*/ BIT 200 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if ((cond1 & BIT(1)) != 0) /*GPA*/ BIT 202 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if ((cond1 & BIT(2)) != 0) /*ALNA*/ BIT 204 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if ((cond1 & BIT(3)) != 0) /*APA*/ BIT 554 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ BIT 555 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (v1 & BIT(31)) {/* positive condition*/ BIT 556 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); BIT 576 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c } else if (v1 & BIT(30)) { /*negative condition*/ BIT 1238 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), BIT 1496 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (!(reg_eac & BIT(28)) && BIT 1508 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (!(reg_eac & BIT(28)) && BIT 1575 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (!(reg_eac & BIT(28)) && BIT 1587 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (!(reg_eac & BIT(28)) && BIT 1654 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (!(reg_eac & BIT(27)) && BIT 1658 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c else if (!(reg_eac & BIT(27)) && BIT 1716 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (!(reg_eac & BIT(28)) && BIT 1728 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (!(reg_eac & BIT(28)) && BIT 1794 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (!(reg_eac & BIT(28)) && BIT 1806 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (!(reg_eac & BIT(28)) && BIT 1869 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if (!(reg_eac & BIT(27)) && BIT 1873 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c else if (!(reg_eac & BIT(27)) && BIT 1903 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), BIT 1913 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), BIT 2046 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c BIT(8)); BIT 46 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 50 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ BIT 58 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \ BIT 61 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \ BIT 64 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \ BIT 67 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ BIT 70 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \ BIT 73 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 76 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \ BIT 79 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \ BIT 82 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 84 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \ BIT 87 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \ BIT 90 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ BIT 93 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ BIT 96 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ BIT 99 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 102 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ BIT 105 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \ BIT 108 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, BIT 120 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ BIT 123 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ BIT 126 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ BIT 129 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \ BIT 132 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \ BIT 136 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_CMD_WRITE, BIT(5), BIT(5)}, \ BIT 140 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_CMD_WRITE, BIT(0), 0}, BIT 148 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \ BIT 152 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ BIT 155 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ BIT 161 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\ BIT 164 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 167 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, BIT 175 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \ BIT 178 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ BIT 181 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ BIT 184 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ BIT 187 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, BIT 199 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \ BIT 202 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \ BIT 205 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \ BIT 208 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ BIT 211 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 214 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, BIT 222 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \ BIT 225 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ BIT 228 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ BIT 231 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ BIT 234 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \ BIT 237 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ BIT 248 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ BIT 255 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ BIT 258 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, BIT 266 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, BIT 292 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ BIT 298 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ BIT 304 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ BIT 310 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, BIT 330 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ BIT 333 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \ BIT 336 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \ BIT 339 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ BIT 345 drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \ BIT 367 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CMDEEPROM_EN BIT(5) BIT 368 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CMDEEPROM_SEL BIT(4) BIT 369 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CMD9346CR_9356SEL BIT(4) BIT 374 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define GPIOSEL_ENBT BIT(5) BIT 382 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HSIMR_GPIO12_0_INT_EN BIT(0) BIT 383 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HSIMR_SPS_OCP_INT_EN BIT(5) BIT 384 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HSIMR_RON_INT_EN BIT(6) BIT 385 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HSIMR_PDN_INT_EN BIT(7) BIT 386 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HSIMR_GPIO9_INT_EN BIT(25) BIT 389 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HSISR_GPIO12_0_INT BIT(0) BIT 390 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HSISR_SPS_OCP_INT BIT(5) BIT 391 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HSISR_RON_INT_EN BIT(6) BIT 392 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HSISR_PDNINT BIT(7) BIT 393 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HSISR_GPIO9_INT BIT(25) BIT 406 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_1M BIT(0) BIT 407 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_2M BIT(1) BIT 408 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_5_5M BIT(2) BIT 409 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_11M BIT(3) BIT 410 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_6M BIT(4) BIT 411 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_9M BIT(5) BIT 412 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_12M BIT(6) BIT 413 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_18M BIT(7) BIT 414 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_24M BIT(8) BIT 415 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_36M BIT(9) BIT 416 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_48M BIT(10) BIT 417 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_54M BIT(11) BIT 418 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_MCS0 BIT(12) BIT 419 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_MCS1 BIT(13) BIT 420 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_MCS2 BIT(14) BIT 421 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_MCS3 BIT(15) BIT 422 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_MCS4 BIT(16) BIT 423 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_MCS5 BIT(17) BIT 424 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_MCS6 BIT(18) BIT 425 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RRSR_MCS7 BIT(19) BIT 426 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BRSR_ACKSHORTPMB BIT(23) BIT 457 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_1M BIT(0) BIT 458 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_2M BIT(1) BIT 459 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_5_5M BIT(2) BIT 460 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_11M BIT(3) BIT 461 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_6M BIT(4) BIT 462 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_9M BIT(5) BIT 463 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_12M BIT(6) BIT 464 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_18M BIT(7) BIT 465 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_24M BIT(8) BIT 466 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_36M BIT(9) BIT 467 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_48M BIT(10) BIT 468 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_54M BIT(11) BIT 469 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS0 BIT(12) BIT 470 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS1 BIT(13) BIT 471 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS2 BIT(14) BIT 472 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS3 BIT(15) BIT 473 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS4 BIT(16) BIT 474 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS5 BIT(17) BIT 475 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS6 BIT(18) BIT 476 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS7 BIT(19) BIT 477 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS8 BIT(20) BIT 478 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS9 BIT(21) BIT 479 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS10 BIT(22) BIT 480 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS11 BIT(23) BIT 481 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS12 BIT(24) BIT 482 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS13 BIT(25) BIT 483 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS14 BIT(26) BIT 484 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RATE_MCS15 BIT(27) BIT 496 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BW_OPMODE_20MHZ BIT(2) BIT 497 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BW_OPMODE_5G BIT(1) BIT 498 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BW_OPMODE_11J BIT(0) BIT 500 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CAM_VALID BIT(15) BIT 502 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CAM_USEDK BIT(5) BIT 513 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CAM_WRITE BIT(16) BIT 515 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CAM_POLLINIG BIT(31) BIT 521 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WOW_PMEN BIT(0) BIT 522 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WOW_WOMEN BIT(1) BIT 523 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WOW_MAGIC BIT(2) BIT 524 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WOW_UWF BIT(3) BIT 532 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_TXCCK BIT(30) /* TXRPT interrupt when BIT 535 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_PSTIMEOUT BIT(29) /* Power Save Time Out Interrupt */ BIT 536 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_GTINT4 BIT(28) /* When GTIMER4 expires, BIT 539 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_GTINT3 BIT(27) /* When GTIMER3 expires, BIT 542 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_TBDER BIT(26) /* Transmit Beacon0 Error */ BIT 543 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_TBDOK BIT(25) /* Transmit Beacon0 OK */ BIT 544 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle BIT 547 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ BIT 548 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDOK0 BIT(16) /* Beacon Queue DMA OK0 */ BIT 549 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & HSISR is BIT 552 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt BIT 555 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_ATIMEND BIT(12) /* CTWidnow End or ATIM Window End */ BIT 556 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_HISR1_IND_INT BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is BIT 559 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_C2HCMD BIT(10) /* CPU to Host Command INT Status, BIT 562 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_CPWM2 BIT(9) /* CPU power Mode exchange INT Status, BIT 565 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_CPWM BIT(8) /* CPU power Mode exchange INT Status, BIT 568 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_HIGHDOK BIT(7) /* High Queue DMA OK */ BIT 569 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK */ BIT 570 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BKDOK BIT(5) /* AC_BK DMA OK */ BIT 571 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BEDOK BIT(4) /* AC_BE DMA OK */ BIT 572 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_VIDOK BIT(3) /* AC_VI DMA OK */ BIT 573 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_VODOK BIT(2) /* AC_VO DMA OK */ BIT 574 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_RDU BIT(1) /* Rx Descriptor Unavailable */ BIT 575 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_ROK BIT(0) /* Receive DMA OK */ BIT 578 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ BIT 579 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ BIT 580 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ BIT 581 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ BIT 582 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ BIT 583 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ BIT 584 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ BIT 585 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrup 7 */ BIT 586 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrup 6 */ BIT 587 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrup 5 */ BIT 588 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrup 4 */ BIT 589 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrup 3 */ BIT 590 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrup 2 */ BIT 591 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrup 1 */ BIT 592 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_ATIMEND_E BIT(13) /* ATIM Window End Extension for Win7 */ BIT 593 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_TXERR BIT(11) /* Tx Error Flag Interrupt Status, BIT 596 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_RXERR BIT(10) /* Rx Error Flag INT Status, BIT 599 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_TXFOVW BIT(9) /* Transmit FIFO Overflow */ BIT 600 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IMR_RXFOVW BIT(8) /* Receive FIFO Overflow */ BIT 690 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define STOPBECON BIT(6) BIT 691 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define STOPHIGHT BIT(5) BIT 692 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define STOPMGT BIT(4) BIT 693 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define STOPVO BIT(3) BIT 694 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define STOPVI BIT(2) BIT 695 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define STOPBE BIT(1) BIT 696 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define STOPBK BIT(0) BIT 698 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_APPFCS BIT(31) BIT 699 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_APP_MIC BIT(30) BIT 700 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_APP_ICV BIT(29) BIT 701 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_APP_PHYST_RXFF BIT(28) BIT 702 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_APP_BA_SSN BIT(27) BIT 703 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_ENMBID BIT(24) BIT 704 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_LSIGEN BIT(23) BIT 705 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_MFBEN BIT(22) BIT 706 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_HTC_LOC_CTRL BIT(14) BIT 707 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_AMF BIT(13) BIT 708 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_ACF BIT(12) BIT 709 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_ADF BIT(11) BIT 710 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_AICV BIT(9) BIT 711 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_ACRC32 BIT(8) BIT 712 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_CBSSID_BCN BIT(7) BIT 713 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_CBSSID_DATA BIT(6) BIT 715 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_APWRMGT BIT(5) BIT 716 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_ADD3 BIT(4) BIT 717 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_AB BIT(3) BIT 718 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_AM BIT(2) BIT 719 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_APM BIT(1) BIT 720 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RCR_AAP BIT(0) BIT 742 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SW18_FPWM BIT(3) BIT 744 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ISO_MD2PP BIT(0) BIT 745 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ISO_UA2USB BIT(1) BIT 746 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ISO_UD2CORE BIT(2) BIT 747 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ISO_PA2PCIE BIT(3) BIT 748 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ISO_PD2CORE BIT(4) BIT 749 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ISO_IP2MAC BIT(5) BIT 750 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ISO_DIOP BIT(6) BIT 751 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ISO_DIOE BIT(7) BIT 752 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ISO_EB2CORE BIT(8) BIT 753 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ISO_DIOR BIT(9) BIT 755 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PWC_EV25V BIT(14) BIT 756 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PWC_EV12V BIT(15) BIT 758 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_BBRSTB BIT(0) BIT 759 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_BB_GLB_RSTN BIT(1) BIT 760 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_USBA BIT(2) BIT 761 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_UPLL BIT(3) BIT 762 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_USBD BIT(4) BIT 763 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_DIO_PCIE BIT(5) BIT 764 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_PCIEA BIT(6) BIT 765 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_PPLL BIT(7) BIT 766 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_PCIED BIT(8) BIT 767 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_DIOE BIT(9) BIT 768 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_CPUEN BIT(10) BIT 769 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_DCORE BIT(11) BIT 770 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_ELDR BIT(12) BIT 771 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_DIO_RF BIT(13) BIT 772 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_HWPDN BIT(14) BIT 773 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FEN_MREGEN BIT(15) BIT 775 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PFM_LDALL BIT(0) BIT 776 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PFM_ALDN BIT(1) BIT 777 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PFM_LDKP BIT(2) BIT 778 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PFM_WOWL BIT(3) BIT 779 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ENPDN BIT(4) BIT 780 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PDN_PL BIT(5) BIT 781 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APFM_ONMAC BIT(8) BIT 782 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APFM_OFF BIT(9) BIT 783 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APFM_RSM BIT(10) BIT 784 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define AFSM_HSUS BIT(11) BIT 785 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define AFSM_PCIE BIT(12) BIT 786 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APDM_MAC BIT(13) BIT 787 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APDM_HOST BIT(14) BIT 788 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APDM_HPDN BIT(15) BIT 789 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RDY_MACON BIT(16) BIT 790 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SUS_HOST BIT(17) BIT 791 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ROP_ALD BIT(20) BIT 792 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ROP_PWR BIT(21) BIT 793 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ROP_SPS BIT(22) BIT 794 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SOP_MRST BIT(25) BIT 795 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SOP_FUSE BIT(26) BIT 796 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SOP_ABG BIT(27) BIT 797 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SOP_AMB BIT(28) BIT 798 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SOP_RCK BIT(29) BIT 799 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SOP_A8M BIT(30) BIT 800 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define XOP_BTCK BIT(31) BIT 802 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ANAD16V_EN BIT(0) BIT 803 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ANA8M BIT(1) BIT 804 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define MACSLP BIT(4) BIT 805 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LOADER_CLK_EN BIT(5) BIT 806 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define _80M_SSC_DIS BIT(7) BIT 807 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define _80M_SSC_EN_HO BIT(8) BIT 808 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PHY_SSC_RSTB BIT(9) BIT 809 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SEC_CLK_EN BIT(10) BIT 810 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define MAC_CLK_EN BIT(11) BIT 811 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SYS_CLK_EN BIT(12) BIT 812 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RING_CLK_EN BIT(13) BIT 814 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BOOT_FROM_EEPROM BIT(4) BIT 815 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define EEPROM_EN BIT(5) BIT 817 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define AFE_BGEN BIT(0) BIT 818 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define AFE_MBEN BIT(1) BIT 819 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define MAC_ID_EN BIT(7) BIT 821 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WLOCK_ALL BIT(0) BIT 822 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WLOCK_00 BIT(1) BIT 823 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WLOCK_04 BIT(2) BIT 824 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WLOCK_08 BIT(3) BIT 825 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WLOCK_40 BIT(4) BIT 826 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define R_DIS_PRST_0 BIT(5) BIT 827 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define R_DIS_PRST_1 BIT(6) BIT 828 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LOCK_ALL_EN BIT(7) BIT 830 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RF_EN BIT(0) BIT 831 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RF_RSTB BIT(1) BIT 832 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RF_SDMRSTB BIT(2) BIT 834 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LDA15_EN BIT(0) BIT 835 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LDA15_STBY BIT(1) BIT 836 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LDA15_OBUF BIT(2) BIT 837 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LDA15_REG_VOS BIT(3) BIT 840 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LDV12_EN BIT(0) BIT 841 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LDV12_SDBY BIT(1) BIT 842 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LPLDO_HSM BIT(2) BIT 843 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LPLDO_LSM_DIS BIT(3) BIT 846 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define XTAL_EN BIT(0) BIT 847 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define XTAL_BSEL BIT(1) BIT 850 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define XTAL_GATE_USB BIT(8) BIT 852 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define XTAL_GATE_AFE BIT(11) BIT 854 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define XTAL_RF_GATE BIT(14) BIT 856 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define XTAL_GATE_DIG BIT(17) BIT 858 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define XTAL_BT_GATE BIT(20) BIT 862 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CKDLY_AFE BIT(26) BIT 863 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CKDLY_USB BIT(27) BIT 864 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CKDLY_DIG BIT(28) BIT 865 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CKDLY_BT BIT(29) BIT 867 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APLL_EN BIT(0) BIT 868 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APLL_320_EN BIT(1) BIT 869 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APLL_FREF_SEL BIT(2) BIT 870 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APLL_EDGE_SEL BIT(3) BIT 871 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APLL_WDOGB BIT(4) BIT 872 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APLL_LPFEN BIT(5) BIT 882 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APLL_320EN BIT(14) BIT 883 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APLL_80EN BIT(15) BIT 884 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APLL_1MEN BIT(24) BIT 886 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ALD_EN BIT(18) BIT 887 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define EF_PD BIT(19) BIT 888 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define EF_FLAG BIT(31) BIT 890 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define EF_TRPT BIT(7) BIT 891 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LDOE25_EN BIT(31) BIT 893 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RSM_EN BIT(0) BIT 894 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TIMER_EN BIT(4) BIT 896 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TRSW0EN BIT(2) BIT 897 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TRSW1EN BIT(3) BIT 898 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define EROM_EN BIT(4) BIT 899 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ENBT BIT(5) BIT 900 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ENUART BIT(8) BIT 901 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define UART_910 BIT(9) BIT 902 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ENPMAC BIT(10) BIT 903 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SIC_SWRST BIT(11) BIT 904 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ENSIC BIT(12) BIT 905 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SIC_23 BIT(13) BIT 906 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ENHDP BIT(14) BIT 907 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SIC_LBK BIT(15) BIT 909 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LED0PL BIT(4) BIT 910 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LED1PL BIT(12) BIT 911 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LED0DIS BIT(7) BIT 913 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define MCUFWDL_EN BIT(0) BIT 914 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define MCUFWDL_RDY BIT(1) BIT 915 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define FWDL_CHKSUM_RPT BIT(2) BIT 916 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define MACINI_RDY BIT(3) BIT 917 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BBINI_RDY BIT(4) BIT 918 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RFINI_RDY BIT(5) BIT 919 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WINTINI_RDY BIT(6) BIT 920 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CPRST BIT(23) BIT 922 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define XCLK_VLD BIT(0) BIT 923 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACLK_VLD BIT(1) BIT 924 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define UCLK_VLD BIT(2) BIT 925 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PCLK_VLD BIT(3) BIT 926 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PCIRSTB BIT(4) BIT 927 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define V15_VLD BIT(5) BIT 928 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TRP_B15V_EN BIT(7) BIT 929 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SIC_IDLE BIT(8) BIT 930 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BD_MAC2 BIT(9) BIT 931 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BD_MAC1 BIT(10) BIT 932 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IC_MACPHY_MODE BIT(11) BIT 933 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define VENDOR_ID BIT(19) BIT 934 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PAD_HWPD_IDN BIT(22) BIT 935 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TRP_VAUX_EN BIT(23) BIT 936 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TRP_BT_EN BIT(24) BIT 937 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BD_PKG_SEL BIT(25) BIT 938 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BD_HCI_SEL BIT(26) BIT 939 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TYPE_ID BIT(27) BIT 946 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HCI_TXDMA_EN BIT(0) BIT 947 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HCI_RXDMA_EN BIT(1) BIT 948 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TXDMA_EN BIT(2) BIT 949 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RXDMA_EN BIT(3) BIT 950 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PROTOCOL_EN BIT(4) BIT 951 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SCHEDULE_EN BIT(5) BIT 952 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define MACTXEN BIT(6) BIT 953 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define MACRXEN BIT(7) BIT 954 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ENSWBCN BIT(8) BIT 955 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ENSEC BIT(9) BIT 985 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RXDMA_ARBBW_EN BIT(0) BIT 986 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RXSHFT_EN BIT(1) BIT 987 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RXDMA_AGG_EN BIT(2) BIT 988 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define QS_VO_QUEUE BIT(8) BIT 989 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define QS_VI_QUEUE BIT(9) BIT 990 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define QS_BE_QUEUE BIT(10) BIT 991 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define QS_BK_QUEUE BIT(11) BIT 992 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define QS_MANAGER_QUEUE BIT(12) BIT 993 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define QS_HIGH_QUEUE BIT(13) BIT 995 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HQSEL_VOQ BIT(0) BIT 996 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HQSEL_VIQ BIT(1) BIT 997 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HQSEL_BEQ BIT(2) BIT 998 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HQSEL_BKQ BIT(3) BIT 999 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HQSEL_MGTQ BIT(4) BIT 1000 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HQSEL_HIQ BIT(5) BIT 1022 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) BIT 1023 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BB_WRITE_EN BIT(30) BIT 1024 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BB_READ_EN BIT(31) BIT 1031 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HPQ_PUBLIC_DIS BIT(24) BIT 1032 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LPQ_PUBLIC_DIS BIT(25) BIT 1033 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LD_RQPN BIT(31) BIT 1035 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BCN_VALID BIT(16) BIT 1042 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define DROP_DATA_EN BIT(9) BIT 1044 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define EN_AMPDU_RTY_NEW BIT(7) BIT 1061 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define USE_SHORT_G1 BIT(20) BIT 1116 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define DIS_EDCA_CNT_DWN BIT(11) BIT 1118 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define EN_MBSSID BIT(1) BIT 1119 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define EN_TXBCN_RPT BIT(2) BIT 1120 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define EN_BCN_FUNCTION BIT(3) BIT 1122 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TSFTR_RST BIT(0) BIT 1123 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TSFTR1_RST BIT(1) BIT 1125 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define STOP_BCNQ BIT(6) BIT 1127 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) BIT 1128 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define DIS_TSF_UDT0_TEST_CHIP BIT(5) BIT 1130 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACMHW_HWEN BIT(0) BIT 1131 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACMHW_BEQEN BIT(1) BIT 1132 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACMHW_VIQEN BIT(2) BIT 1133 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACMHW_VOQEN BIT(3) BIT 1134 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACMHW_BEQSTATUS BIT(4) BIT 1135 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACMHW_VIQSTATUS BIT(5) BIT 1136 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACMHW_VOQSTATUS BIT(6) BIT 1138 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APSDOFF BIT(6) BIT 1139 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APSDOFF_STATUS BIT(7) BIT 1141 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BW_20MHZ BIT(2) BIT 1147 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TSFRST BIT(0) BIT 1148 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define DIS_GCLK BIT(1) BIT 1149 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PAD_SEL BIT(2) BIT 1150 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PWR_ST BIT(6) BIT 1151 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PWRBIT_OW_EN BIT(7) BIT 1152 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACRC BIT(8) BIT 1153 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CFENDFORM BIT(9) BIT 1154 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ICV BIT(10) BIT 1156 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define AAP BIT(0) BIT 1157 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APM BIT(1) BIT 1158 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define AM BIT(2) BIT 1159 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define AB BIT(3) BIT 1160 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ADD3 BIT(4) BIT 1161 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APWRMGT BIT(5) BIT 1162 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CBSSID BIT(6) BIT 1163 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CBSSID_DATA BIT(6) BIT 1164 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define CBSSID_BCN BIT(7) BIT 1165 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACRC32 BIT(8) BIT 1166 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define AICV BIT(9) BIT 1167 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ADF BIT(11) BIT 1168 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACF BIT(12) BIT 1169 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define AMF BIT(13) BIT 1170 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HTC_LOC_CTRL BIT(14) BIT 1171 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define UC_DATA_EN BIT(16) BIT 1172 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BM_DATA_EN BIT(17) BIT 1173 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define MFBEN BIT(22) BIT 1174 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define LSIGEN BIT(23) BIT 1175 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ENMBID BIT(24) BIT 1176 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APP_BASSN BIT(27) BIT 1177 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APP_PHYSTS BIT(28) BIT 1178 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APP_ICV BIT(29) BIT 1179 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APP_MIC BIT(30) BIT 1180 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define APP_FCS BIT(31) BIT 1201 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define RXERR_RPT_RST BIT(27) BIT 1204 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SCR_TXUSEDK BIT(0) BIT 1205 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SCR_RXUSEDK BIT(1) BIT 1206 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SCR_TXENCENABLE BIT(2) BIT 1207 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SCR_RXDECENABLE BIT(3) BIT 1208 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SCR_SKBYA2 BIT(4) BIT 1209 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SCR_NOSKMC BIT(5) BIT 1210 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SCR_TXBCUSEDK BIT(6) BIT 1211 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SCR_RXBCUSEDK BIT(7) BIT 1213 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define XCLK_VLD BIT(0) BIT 1214 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define ACLK_VLD BIT(1) BIT 1215 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define UCLK_VLD BIT(2) BIT 1216 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PCLK_VLD BIT(3) BIT 1217 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PCIRSTB BIT(4) BIT 1218 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define V15_VLD BIT(5) BIT 1219 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TRP_B15V_EN BIT(7) BIT 1220 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define SIC_IDLE BIT(8) BIT 1221 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BD_MAC2 BIT(9) BIT 1222 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BD_MAC1 BIT(10) BIT 1223 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define IC_MACPHY_MODE BIT(11) BIT 1224 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BT_FUNC BIT(16) BIT 1225 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define VENDOR_ID BIT(19) BIT 1226 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define PAD_HWPD_IDN BIT(22) BIT 1227 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TRP_VAUX_EN BIT(23) BIT 1228 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TRP_BT_EN BIT(24) BIT 1229 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BD_PKG_SEL BIT(25) BIT 1230 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define BD_HCI_SEL BIT(26) BIT 1231 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define TYPE_ID BIT(27) BIT 1235 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define USB_SPEED_MASK BIT(5) BIT 1243 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define USB_AGG_EN BIT(3) BIT 1260 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) BIT 2253 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) BIT 2254 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) BIT 2255 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HAL92C_WOL_DISASSOC_EVENT BIT(2) BIT 2256 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HAL92C_WOL_DEAUTH_EVENT BIT(3) BIT 2257 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4) BIT 2259 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WOL_REASON_PTK_UPDATE BIT(0) BIT 2260 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WOL_REASON_GTK_UPDATE BIT(1) BIT 2261 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WOL_REASON_DISASSOC BIT(2) BIT 2262 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WOL_REASON_DEAUTH BIT(3) BIT 2263 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WOL_REASON_FW_DISCONNECT BIT(4) BIT 2270 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WL_HWPDN_EN BIT(0) /* Enable GPIO[9] as WiFi HW PDn source*/ BIT 2271 drivers/net/wireless/realtek/rtlwifi/rtl8723be/reg.h #define WL_HWPDN_SL BIT(1) /* WiFi HW PDn polarity control*/ BIT 21 drivers/net/wireless/realtek/rtlwifi/rtl8723be/rf.c 0xfffff3ff) | BIT(10) | BIT(11)); BIT 27 drivers/net/wireless/realtek/rtlwifi/rtl8723be/rf.c 0xfffff3ff) | BIT(10)); BIT 82 drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25); BIT 63 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c BIT(9)); BIT 335 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c wake_match = BIT(2); BIT 337 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c wake_match = BIT(1); BIT 339 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c wake_match = BIT(0); BIT 742 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4)); BIT 745 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c BIT(0) << (hw_queue)); BIT 29 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits(__pdesc, __val, BIT(24)); BIT 34 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits(__pdesc, __val, BIT(25)); BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits(__pdesc, __val, BIT(26)); BIT 44 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits(__pdesc, __val, BIT(27)); BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits(__pdesc, __val, BIT(28)); BIT 54 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 59 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*__pdesc, BIT(31)); BIT 89 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 2), __val, BIT(12)); BIT 94 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 2), __val, BIT(13)); BIT 99 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 2), __val, BIT(17)); BIT 114 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(8)); BIT 119 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(10)); BIT 124 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(11)); BIT 129 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(12)); BIT 134 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(13)); BIT 139 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 3), __val, BIT(15)); BIT 174 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 5), __val, BIT(4)); BIT 184 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 5), __val, BIT(12)); BIT 199 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits((__pdesc + 8), __val, BIT(15)); BIT 229 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*__pdesc, BIT(14)); BIT 234 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*__pdesc, BIT(15)); BIT 249 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*__pdesc, BIT(26)); BIT 254 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*__pdesc, BIT(27)); BIT 259 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*__pdesc, BIT(31)); BIT 269 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits(__pdesc, __val, BIT(30)); BIT 274 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 284 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*(__pdesc + 1), BIT(15)); BIT 289 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*(__pdesc + 2), BIT(28)); BIT 299 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*(__pdesc + 3), BIT(6)); BIT 304 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*(__pdesc + 3), BIT(29)); BIT 309 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*(__pdesc + 3), BIT(30)); BIT 314 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*(__pdesc + 3), BIT(31)); BIT 319 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h return le32_get_bits(*(__pdesc + 4), BIT(0)); BIT 79 drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.c while (u1b_tmp & BIT(2)) { BIT 89 drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.c u1b_tmp&(~BIT(2))); BIT 100 drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); BIT 103 drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); BIT 107 drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0))); BIT 110 drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp | BIT(2))); BIT 200 drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.c if (rtl_read_byte(rtlpriv, REG_MCUFWDL)&BIT(7)) { BIT 14 drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.h #define MCUFWDL_RDY BIT(1) BIT 15 drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.h #define FWDL_CHKSUM_RPT BIT(2) BIT 16 drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.h #define WINTINI_RDY BIT(6) BIT 100 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c BIT(8)); BIT 103 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c BIT(8)); BIT 299 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), BIT 309 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), BIT 404 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c (u8) (macbackup[i] & (~BIT(3)))); BIT 405 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); BIT 112 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define CHIP_8812 BIT(2) BIT 113 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define CHIP_8821 (BIT(0)|BIT(2)) BIT 115 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define CHIP_8821A (BIT(0)|BIT(2)) BIT 116 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define NORMAL_CHIP BIT(3) BIT 117 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6))) BIT 118 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define RF_TYPE_1T2R BIT(4) BIT 119 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define RF_TYPE_2T2R BIT(5) BIT 120 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define CHIP_VENDOR_UMC BIT(7) BIT 121 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define B_CUT_VERSION BIT(12) BIT 122 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define C_CUT_VERSION BIT(13) BIT 123 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define D_CUT_VERSION ((BIT(12)|BIT(13))) BIT 124 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define E_CUT_VERSION BIT(14) BIT 125 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) BIT 155 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) BIT 156 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define CHIP_TYPE_MASK BIT(3) BIT 157 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) BIT 158 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define MANUFACTUER_MASK BIT(7) BIT 159 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) BIT 160 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) BIT 204 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */ BIT 205 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ BIT 206 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ BIT 207 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h ODM_BOARD_EXT_PA = BIT(3), /* 1 = existing 2G ext-PA */ BIT 208 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h ODM_BOARD_EXT_LNA = BIT(4), /* 1 = existing 2G ext-LNA */ BIT 209 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h ODM_BOARD_EXT_TRSW = BIT(5), /* 1 = existing ext-TRSW */ BIT 210 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h ODM_BOARD_EXT_PA_5G = BIT(6), /* 1 = existing 5G ext-PA */ BIT 211 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h ODM_BOARD_EXT_LNA_5G = BIT(7), /* 1 = existing 5G ext-LNA */ BIT 534 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11)); BIT 550 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c if (tmp & BIT(0)) BIT 552 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c if (tmp & BIT(1)) BIT 1021 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c cck_enable = rtl_get_bbreg(hw, ODM_REG_BB_RX_PATH_11AC, BIT(28)); BIT 1029 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c rtl_set_bbreg(hw, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1); BIT 1030 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c rtl_set_bbreg(hw, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0); BIT 1032 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c rtl_set_bbreg(hw, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0); BIT 1033 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c rtl_set_bbreg(hw, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1); BIT 1050 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c BIT(17) | BIT(16), 0x03); BIT 2497 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER_88E, BIT(17)|BIT(16), BIT 2789 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.c rtl_set_bbreg(hw, RFC_AREA, BIT(14), ATC_STATUS_ON); BIT 156 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.h #define HAL_DM_DIG_DISABLE BIT(0) BIT 157 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.h #define HAL_DM_HIPWR_DISABLE BIT(1) BIT 172 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) { BIT 228 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c if (((val_hmetfr >> boxnum) & BIT(0)) == 0) BIT 440 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3)))); BIT 443 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(0)))); BIT 447 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); BIT 452 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3))); BIT 455 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(0))); BIT 459 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp | BIT(2))); BIT 519 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c if ((rlbm == 2) && (byte5 & BIT(4))) { BIT 1861 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4)); BIT 47 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_GO_ON BIT(0) BIT 48 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_TX_NULL BIT(1) BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_RF_ON BIT(2) BIT 50 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_REGISTER_ACTIVE BIT(3) BIT 52 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_DPS BIT(0) BIT 54 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_RF_OFF BIT(1) BIT 55 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_ALL_ON BIT(2) BIT 56 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_ST_ACTIVE BIT(3) BIT 57 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_ISR_ENABLE BIT(4) BIT 58 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_IMR_ENABLE BIT(5) BIT 60 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_ACK BIT(6) BIT 61 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_TOGGLE BIT(7) BIT 66 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.h #define FW_PS_CLOCK_OFF BIT(0) BIT 65 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); BIT 68 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp1byte &= ~(BIT(0)); BIT 78 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); BIT 81 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp1byte |= BIT(0); BIT 87 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1)); BIT 92 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0); BIT 298 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0))); BIT 300 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 301 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 305 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp_reg422 & (~BIT(6))); BIT 306 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (tmp_reg422 & BIT(6)) BIT 312 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c (bcnvalid_reg | BIT(0))); BIT 324 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c while (!(bcnvalid_reg & BIT(0)) && count < 20) { BIT 330 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); BIT 332 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (!(bcnvalid_reg & BIT(0))) BIT 335 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) { BIT 336 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0)); BIT 342 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c bcnvalid_reg | BIT(0)); BIT 357 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c while (!(bcnvalid_reg & BIT(0)) && count < 20) { BIT 365 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); BIT 367 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (!(bcnvalid_reg & BIT(0))) BIT 373 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (bcnvalid_reg & BIT(0)) BIT 374 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0)); BIT 376 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 377 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 384 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0)))); BIT 531 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c reg_tmp |= BIT(1); BIT 535 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c reg_tmp &= (~BIT(1)); BIT 599 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c ampdu_len |= BIT(31); BIT 676 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); BIT 693 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (rpwm_val & BIT(7)) { BIT 698 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c ((*(u8 *)val) | BIT(7))); BIT 748 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); BIT 755 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 905 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); BIT 928 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); BIT 942 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (bytetmp & BIT(0)) { BIT 944 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c bytetmp |= BIT(6); BIT 950 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c bytetmp &= ~BIT(4); BIT 965 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6)); BIT 1059 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6)); BIT 1060 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); BIT 1064 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); BIT 1078 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5)); BIT 1079 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); BIT 1083 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); BIT 1117 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12)); BIT 1146 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) | BIT 1150 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4)); BIT 1154 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4)); BIT 1185 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1)); BIT 1223 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (!(tmp & BIT(2))) { BIT 1224 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2))); BIT 1231 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if ((tmp & BIT(0)) || (tmp & BIT(1))) { BIT 1254 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp &= ~(BIT(1)); BIT 1259 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp |= BIT(2); BIT 1267 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (tmp & BIT(2)) { BIT 1271 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); BIT 1286 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp &= ~(BIT(0)); BIT 1291 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp |= BIT(0); BIT 1309 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp |= BIT(1); BIT 1324 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp & (~BIT(2))); BIT 1334 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp &= ~(BIT(2)); BIT 1536 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); BIT 1541 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c } while (!(tmp & BIT(1)) && count < 100); BIT 1550 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp &= ~(BIT(0)); BIT 1562 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp &= ~(BIT(1)); BIT 1568 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5))); BIT 1573 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1))); BIT 1584 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0))); BIT 1621 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2))); BIT 1661 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (!(tmp & (BIT(2) | BIT(3)))) { BIT 1668 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4))); BIT 1671 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5)); BIT 1685 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (!(tmp & BIT(2))) { BIT 1698 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4))); BIT 1701 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0)))); BIT 1702 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0))); BIT 1742 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (tmp & BIT(1)) { BIT 1744 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); BIT 1760 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0)))); BIT 1809 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && BIT 1816 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); BIT 1834 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); BIT 1836 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); BIT 1978 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (tmp_u1b & BIT(2)) { BIT 1980 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c tmp_u1b &= ~BIT(2); BIT 2173 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); BIT 2176 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); BIT 2316 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pmcs_reg & BIT(7)) { BIT 2318 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c pmcs_reg = pmcs_reg | BIT(7); BIT 2405 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2)); BIT 2409 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c while (!(tmp & BIT(1)) && (count++ < 100)) { BIT 2424 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3)); BIT 2457 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); BIT 2493 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlpci->reg_bcn_ctrl_val |= BIT(3); BIT 2656 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3)) BIT 2660 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3)) BIT 2667 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo24g->bw40_diff[rfpath][txcount] & BIT(3)) BIT 2671 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3)) BIT 2677 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3)) BIT 2681 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo24g->cck_diff[rfpath][txcount] & BIT(3)) BIT 2700 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3)) BIT 2704 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3)) BIT 2710 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo5g->bw40_diff[rfpath][txcount] & BIT(3)) BIT 2714 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3)) BIT 2731 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3)) BIT 2737 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo5g->bw80_diff[rfpath][txcount] & BIT(3)) BIT 2741 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (pwrinfo5g->bw160_diff[rfpath][txcount] & BIT(3)) BIT 2917 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) && BIT 2918 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c (rtlhal->pa_type_2g & BIT(4))) ? BIT 2920 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) && BIT 2921 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c (rtlhal->lna_type_2g & BIT(3))) ? BIT 2930 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) && BIT 2931 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c (rtlhal->pa_type_5g & BIT(0))) ? BIT 2933 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) && BIT 2934 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c (rtlhal->lna_type_5g & BIT(3))) ? BIT 2950 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 ext_type_pa_2g_a = (hwinfo[0XBD] & BIT(2)) >> 2; /* 0XBD[2] */ BIT 2951 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 ext_type_pa_2g_b = (hwinfo[0XBD] & BIT(6)) >> 6; /* 0XBD[6] */ BIT 2952 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 ext_type_pa_5g_a = (hwinfo[0XBF] & BIT(2)) >> 2; /* 0XBF[2] */ BIT 2953 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 ext_type_pa_5g_b = (hwinfo[0XBF] & BIT(6)) >> 6; /* 0XBF[6] */ BIT 2955 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 ext_type_lna_2g_a = (hwinfo[0XBD] & (BIT(1) | BIT(0))) >> 0; BIT 2957 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 ext_type_lna_2g_b = (hwinfo[0XBD] & (BIT(5) | BIT(4))) >> 4; BIT 2959 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 ext_type_lna_5g_a = (hwinfo[0XBF] & (BIT(1) | BIT(0))) >> 0; BIT 2961 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c u8 ext_type_lna_5g_b = (hwinfo[0XBF] & (BIT(5) | BIT(4))) >> 4; BIT 2966 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4))) BIT 2970 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0))) BIT 2974 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3))) BIT 2978 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3))) BIT 2995 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0; BIT 2996 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0; BIT 3004 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0; BIT 3005 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0; BIT 3021 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) { BIT 3088 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (tmpu_32 & BIT(18)) BIT 3271 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (tmp_u1b & BIT(4)) { BIT 3279 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c if (tmp_u1b & BIT(5)) { BIT 3703 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); BIT 3775 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c REG_GPIO_IO_SEL_2) & ~(BIT(1))); BIT 3780 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; BIT 3782 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; BIT 4028 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c cam = BIT(31) | rtl_pattern->crc; BIT 4031 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c cam |= BIT(24); BIT 4033 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c cam |= BIT(25); BIT 4035 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c cam |= BIT(26); BIT 31 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c ledcfg &= ~BIT(6); BIT 33 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5)); BIT 72 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c ledcfg |= BIT(5); /*Set 0x4c[21]*/ BIT 73 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c ledcfg &= ~(BIT(7) | BIT(6) | BIT(3) | BIT(2) | BIT(1) | BIT(0)); BIT 96 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3))); BIT 101 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c ledcfg &= ~BIT(6); BIT 103 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c (ledcfg | BIT(3) | BIT(5))); BIT 109 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg|BIT(3)); BIT 146 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c rtl_write_byte(rtlpriv, ledreg, (ledcfg | BIT(3))); BIT 67 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); BIT 71 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); BIT 76 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); BIT 740 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0)); BIT 742 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c u8 board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */ BIT 743 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c ((rtlhal->board_type & BIT(3)) >> 3) << 1 | /* _GPA */ BIT 744 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c ((rtlhal->board_type & BIT(7)) >> 7) << 2 | /* _ALNA */ BIT 745 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c ((rtlhal->board_type & BIT(6)) >> 6) << 3 | /* _APA */ BIT 746 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c ((rtlhal->board_type & BIT(2)) >> 2) << 4; /* _BT */ BIT 796 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if ((cond1 & BIT(0)) != 0) /*GLNA*/ BIT 798 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if ((cond1 & BIT(1)) != 0) /*GPA*/ BIT 800 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if ((cond1 & BIT(2)) != 0) /*ALNA*/ BIT 802 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if ((cond1 & BIT(3)) != 0) /*APA*/ BIT 1866 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ BIT 1867 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if (v1 & BIT(31)) {/* positive condition*/ BIT 1868 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); BIT 1888 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c } else if (v1 & BIT(30)) { /*negative condition*/ BIT 3354 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c tmp = reg_rf_mode_bw | BIT(7); BIT 3358 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c tmp = reg_rf_mode_bw | BIT(8); BIT 3427 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); BIT 3436 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); BIT 3440 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if (rtlphy->reg_837 & BIT(2)) BIT 3461 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); BIT 3465 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if (rtlphy->reg_837 & BIT(2)) BIT 3547 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c BIT(18)|BIT(17)|BIT(16)|BIT(9)|BIT(8), data); BIT 3645 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ BIT 3659 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ BIT 3673 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ BIT 3690 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ BIT 3692 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0); BIT 3704 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); BIT 3729 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 3773 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ BIT 3792 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7); BIT 3805 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1); BIT 3810 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ BIT 3827 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 3841 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ BIT 3844 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 3855 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1); BIT 3860 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ BIT 3874 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); BIT 3877 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0); BIT 3878 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0); BIT 3879 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); BIT 3888 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c tx_dt[cal] = (tx_dt[cal] >> 1)+(tx_dt[cal] & BIT(0)); BIT 3891 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); BIT 3908 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); BIT 3919 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); BIT 3962 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); BIT 3973 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); BIT 4003 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); /* TX VDF Disable */ BIT 4007 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 4023 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ BIT 4029 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0); BIT 4036 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0); BIT 4050 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rx_dt[cal] = (rx_dt[cal] >> 1)+(rx_dt[cal] & BIT(0)); BIT 4072 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); BIT 4083 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); BIT 4117 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 4129 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x978, BIT(31), 0x1); BIT 4130 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0); BIT 4135 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ BIT 4136 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1); BIT 4137 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0); BIT 4143 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1); /* RX VDF Enable */ BIT 4156 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); BIT 4167 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11)); BIT 4197 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); /* TX VDF Enable */ BIT 4202 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 4215 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ BIT 4231 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); BIT 4242 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); BIT 4274 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 4286 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x978, BIT(31), 0x1); BIT 4287 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0); BIT 4292 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ BIT 4311 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); BIT 4322 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11)); BIT 4352 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 4444 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 4466 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 4470 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ BIT 4491 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ BIT 4546 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1); BIT 4548 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2); BIT 378 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CMDEEPROM_EN BIT(5) BIT 379 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CMDEEPROM_SEL BIT(4) BIT 380 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CMD9346CR_9356SEL BIT(4) BIT 385 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define GPIOSEL_ENBT BIT(5) BIT 393 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HSIMR_GPIO12_0_INT_EN BIT(0) BIT 394 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HSIMR_SPS_OCP_INT_EN BIT(5) BIT 395 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HSIMR_RON_INT_EN BIT(6) BIT 396 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HSIMR_PDN_INT_EN BIT(7) BIT 397 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HSIMR_GPIO9_INT_EN BIT(25) BIT 400 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HSISR_GPIO12_0_INT BIT(0) BIT 401 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HSISR_SPS_OCP_INT BIT(5) BIT 402 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HSISR_RON_INT_EN BIT(6) BIT 403 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HSISR_PDNINT BIT(7) BIT 404 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HSISR_GPIO9_INT BIT(25) BIT 418 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_1M BIT(0) BIT 419 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_2M BIT(1) BIT 420 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_5_5M BIT(2) BIT 421 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_11M BIT(3) BIT 422 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_6M BIT(4) BIT 423 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_9M BIT(5) BIT 424 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_12M BIT(6) BIT 425 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_18M BIT(7) BIT 426 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_24M BIT(8) BIT 427 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_36M BIT(9) BIT 428 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_48M BIT(10) BIT 429 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_54M BIT(11) BIT 430 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_MCS0 BIT(12) BIT 431 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_MCS1 BIT(13) BIT 432 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_MCS2 BIT(14) BIT 433 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_MCS3 BIT(15) BIT 434 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_MCS4 BIT(16) BIT 435 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_MCS5 BIT(17) BIT 436 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_MCS6 BIT(18) BIT 437 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RRSR_MCS7 BIT(19) BIT 438 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BRSR_ACKSHORTPMB BIT(23) BIT 469 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_1M BIT(0) BIT 470 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_2M BIT(1) BIT 471 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_5_5M BIT(2) BIT 472 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_11M BIT(3) BIT 473 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_6M BIT(4) BIT 474 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_9M BIT(5) BIT 475 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_12M BIT(6) BIT 476 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_18M BIT(7) BIT 477 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_24M BIT(8) BIT 478 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_36M BIT(9) BIT 479 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_48M BIT(10) BIT 480 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_54M BIT(11) BIT 481 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS0 BIT(12) BIT 482 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS1 BIT(13) BIT 483 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS2 BIT(14) BIT 484 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS3 BIT(15) BIT 485 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS4 BIT(16) BIT 486 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS5 BIT(17) BIT 487 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS6 BIT(18) BIT 488 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS7 BIT(19) BIT 489 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS8 BIT(20) BIT 490 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS9 BIT(21) BIT 491 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS10 BIT(22) BIT 492 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS11 BIT(23) BIT 493 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS12 BIT(24) BIT 494 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS13 BIT(25) BIT 495 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS14 BIT(26) BIT 496 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RATE_MCS15 BIT(27) BIT 508 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BW_OPMODE_20MHZ BIT(2) BIT 509 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BW_OPMODE_5G BIT(1) BIT 510 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BW_OPMODE_11J BIT(0) BIT 512 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CAM_VALID BIT(15) BIT 514 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CAM_USEDK BIT(5) BIT 525 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CAM_WRITE BIT(16) BIT 527 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CAM_POLLINIG BIT(31) BIT 533 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WOW_PMEN BIT(0) BIT 534 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WOW_WOMEN BIT(1) BIT 535 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WOW_MAGIC BIT(2) BIT 536 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WOW_UWF BIT(3) BIT 544 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_TXCCK BIT(30) BIT 546 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_PSTIMEOUT BIT(29) BIT 548 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_GTINT4 BIT(28) BIT 550 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_GTINT3 BIT(27) BIT 552 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_TBDER BIT(26) BIT 554 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_TBDOK BIT(25) BIT 556 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_TSF_BIT32_TOGGLE BIT(24) BIT 558 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDMAINT0 BIT(20) BIT 560 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDOK0 BIT(16) BIT 562 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_HSISR_IND_ON_INT BIT(15) BIT 564 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDMAINT_E BIT(14) BIT 566 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_ATIMEND BIT(12) BIT 568 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_HISR1_IND_INT BIT(11) BIT 570 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_C2HCMD BIT(10) BIT 572 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_CPWM2 BIT(9) BIT 574 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_CPWM BIT(8) BIT 576 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_HIGHDOK BIT(7) BIT 578 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_MGNTDOK BIT(6) BIT 580 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BKDOK BIT(5) BIT 582 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BEDOK BIT(4) BIT 584 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_VIDOK BIT(3) BIT 586 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_VODOK BIT(2) BIT 588 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_RDU BIT(1) BIT 589 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_ROK BIT(0) /* Receive DMA OK */ BIT 593 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDMAINT7 BIT(27) BIT 595 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDMAINT6 BIT(26) BIT 597 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDMAINT5 BIT(25) BIT 599 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDMAINT4 BIT(24) BIT 601 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDMAINT3 BIT(23) BIT 603 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDMAINT2 BIT(22) BIT 605 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDMAINT1 BIT(21) BIT 607 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDOK7 BIT(20) BIT 609 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDOK6 BIT(19) BIT 611 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDOK5 BIT(18) BIT 613 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDOK4 BIT(17) BIT 615 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDOK3 BIT(16) BIT 617 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDOK2 BIT(15) BIT 619 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_BCNDOK1 BIT(14) BIT 621 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_ATIMEND_E BIT(13) BIT 623 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_TXERR BIT(11) BIT 625 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_RXERR BIT(10) BIT 627 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_TXFOVW BIT(9) BIT 629 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IMR_RXFOVW BIT(8) BIT 718 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define STOPBECON BIT(6) BIT 719 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define STOPHIGHT BIT(5) BIT 720 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define STOPMGT BIT(4) BIT 721 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define STOPVO BIT(3) BIT 722 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define STOPVI BIT(2) BIT 723 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define STOPBE BIT(1) BIT 724 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define STOPBK BIT(0) BIT 726 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_APPFCS BIT(31) BIT 727 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_APP_MIC BIT(30) BIT 728 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_APP_ICV BIT(29) BIT 729 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_APP_PHYST_RXFF BIT(28) BIT 730 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_APP_BA_SSN BIT(27) BIT 731 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_NONQOS_VHT BIT(26) BIT 732 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_ENMBID BIT(24) BIT 733 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_LSIGEN BIT(23) BIT 734 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_MFBEN BIT(22) BIT 735 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_HTC_LOC_CTRL BIT(14) BIT 736 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_AMF BIT(13) BIT 737 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_ACF BIT(12) BIT 738 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_ADF BIT(11) BIT 739 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_AICV BIT(9) BIT 740 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_ACRC32 BIT(8) BIT 741 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_CBSSID_BCN BIT(7) BIT 742 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_CBSSID_DATA BIT(6) BIT 744 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_APWRMGT BIT(5) BIT 745 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_ADD3 BIT(4) BIT 746 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_AB BIT(3) BIT 747 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_AM BIT(2) BIT 748 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_APM BIT(1) BIT 749 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RCR_AAP BIT(0) BIT 771 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SW18_FPWM BIT(3) BIT 773 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ISO_MD2PP BIT(0) BIT 774 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ISO_UA2USB BIT(1) BIT 775 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ISO_UD2CORE BIT(2) BIT 776 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ISO_PA2PCIE BIT(3) BIT 777 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ISO_PD2CORE BIT(4) BIT 778 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ISO_IP2MAC BIT(5) BIT 779 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ISO_DIOP BIT(6) BIT 780 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ISO_DIOE BIT(7) BIT 781 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ISO_EB2CORE BIT(8) BIT 782 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ISO_DIOR BIT(9) BIT 784 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PWC_EV25V BIT(14) BIT 785 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PWC_EV12V BIT(15) BIT 787 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_BBRSTB BIT(0) BIT 788 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_BB_GLB_RSTN BIT(1) BIT 789 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_USBA BIT(2) BIT 790 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_UPLL BIT(3) BIT 791 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_USBD BIT(4) BIT 792 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_DIO_PCIE BIT(5) BIT 793 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_PCIEA BIT(6) BIT 794 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_PPLL BIT(7) BIT 795 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_PCIED BIT(8) BIT 796 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_DIOE BIT(9) BIT 797 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_CPUEN BIT(10) BIT 798 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_DCORE BIT(11) BIT 799 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_ELDR BIT(12) BIT 800 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_DIO_RF BIT(13) BIT 801 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_HWPDN BIT(14) BIT 802 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FEN_MREGEN BIT(15) BIT 804 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PFM_LDALL BIT(0) BIT 805 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PFM_ALDN BIT(1) BIT 806 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PFM_LDKP BIT(2) BIT 807 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PFM_WOWL BIT(3) BIT 808 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ENPDN BIT(4) BIT 809 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PDN_PL BIT(5) BIT 810 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APFM_ONMAC BIT(8) BIT 811 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APFM_OFF BIT(9) BIT 812 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APFM_RSM BIT(10) BIT 813 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define AFSM_HSUS BIT(11) BIT 814 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define AFSM_PCIE BIT(12) BIT 815 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APDM_MAC BIT(13) BIT 816 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APDM_HOST BIT(14) BIT 817 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APDM_HPDN BIT(15) BIT 818 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RDY_MACON BIT(16) BIT 819 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SUS_HOST BIT(17) BIT 820 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ROP_ALD BIT(20) BIT 821 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ROP_PWR BIT(21) BIT 822 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ROP_SPS BIT(22) BIT 823 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SOP_MRST BIT(25) BIT 824 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SOP_FUSE BIT(26) BIT 825 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SOP_ABG BIT(27) BIT 826 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SOP_AMB BIT(28) BIT 827 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SOP_RCK BIT(29) BIT 828 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SOP_A8M BIT(30) BIT 829 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define XOP_BTCK BIT(31) BIT 831 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ANAD16V_EN BIT(0) BIT 832 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ANA8M BIT(1) BIT 833 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define MACSLP BIT(4) BIT 834 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LOADER_CLK_EN BIT(5) BIT 835 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define _80M_SSC_DIS BIT(7) BIT 836 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define _80M_SSC_EN_HO BIT(8) BIT 837 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PHY_SSC_RSTB BIT(9) BIT 838 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SEC_CLK_EN BIT(10) BIT 839 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define MAC_CLK_EN BIT(11) BIT 840 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SYS_CLK_EN BIT(12) BIT 841 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RING_CLK_EN BIT(13) BIT 843 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BOOT_FROM_EEPROM BIT(4) BIT 844 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define EEPROM_EN BIT(5) BIT 846 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define AFE_BGEN BIT(0) BIT 847 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define AFE_MBEN BIT(1) BIT 848 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define MAC_ID_EN BIT(7) BIT 850 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WLOCK_ALL BIT(0) BIT 851 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WLOCK_00 BIT(1) BIT 852 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WLOCK_04 BIT(2) BIT 853 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WLOCK_08 BIT(3) BIT 854 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WLOCK_40 BIT(4) BIT 855 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define R_DIS_PRST_0 BIT(5) BIT 856 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define R_DIS_PRST_1 BIT(6) BIT 857 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LOCK_ALL_EN BIT(7) BIT 859 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RF_EN BIT(0) BIT 860 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RF_RSTB BIT(1) BIT 861 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RF_SDMRSTB BIT(2) BIT 863 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LDA15_EN BIT(0) BIT 864 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LDA15_STBY BIT(1) BIT 865 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LDA15_OBUF BIT(2) BIT 866 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LDA15_REG_VOS BIT(3) BIT 869 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LDV12_EN BIT(0) BIT 870 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LDV12_SDBY BIT(1) BIT 871 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LPLDO_HSM BIT(2) BIT 872 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LPLDO_LSM_DIS BIT(3) BIT 875 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define XTAL_EN BIT(0) BIT 876 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define XTAL_BSEL BIT(1) BIT 879 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define XTAL_GATE_USB BIT(8) BIT 881 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define XTAL_GATE_AFE BIT(11) BIT 883 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define XTAL_RF_GATE BIT(14) BIT 885 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define XTAL_GATE_DIG BIT(17) BIT 887 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define XTAL_BT_GATE BIT(20) BIT 891 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CKDLY_AFE BIT(26) BIT 892 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CKDLY_USB BIT(27) BIT 893 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CKDLY_DIG BIT(28) BIT 894 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CKDLY_BT BIT(29) BIT 896 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APLL_EN BIT(0) BIT 897 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APLL_320_EN BIT(1) BIT 898 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APLL_FREF_SEL BIT(2) BIT 899 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APLL_EDGE_SEL BIT(3) BIT 900 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APLL_WDOGB BIT(4) BIT 901 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APLL_LPFEN BIT(5) BIT 911 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APLL_320EN BIT(14) BIT 912 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APLL_80EN BIT(15) BIT 913 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APLL_1MEN BIT(24) BIT 915 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ALD_EN BIT(18) BIT 916 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define EF_PD BIT(19) BIT 917 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define EF_FLAG BIT(31) BIT 919 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define EF_TRPT BIT(7) BIT 920 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LDOE25_EN BIT(31) BIT 922 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RSM_EN BIT(0) BIT 923 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TIMER_EN BIT(4) BIT 925 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TRSW0EN BIT(2) BIT 926 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TRSW1EN BIT(3) BIT 927 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define EROM_EN BIT(4) BIT 928 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ENBT BIT(5) BIT 929 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ENUART BIT(8) BIT 930 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define UART_910 BIT(9) BIT 931 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ENPMAC BIT(10) BIT 932 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SIC_SWRST BIT(11) BIT 933 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ENSIC BIT(12) BIT 934 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SIC_23 BIT(13) BIT 935 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ENHDP BIT(14) BIT 936 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SIC_LBK BIT(15) BIT 938 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LED0PL BIT(4) BIT 939 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LED1PL BIT(12) BIT 940 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LED0DIS BIT(7) BIT 942 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define MCUFWDL_EN BIT(0) BIT 943 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define MCUFWDL_RDY BIT(1) BIT 944 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define FWDL_CHKSUM_RPT BIT(2) BIT 945 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define MACINI_RDY BIT(3) BIT 946 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BBINI_RDY BIT(4) BIT 947 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RFINI_RDY BIT(5) BIT 948 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WINTINI_RDY BIT(6) BIT 949 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CPRST BIT(23) BIT 951 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define XCLK_VLD BIT(0) BIT 952 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACLK_VLD BIT(1) BIT 953 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define UCLK_VLD BIT(2) BIT 954 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PCLK_VLD BIT(3) BIT 955 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PCIRSTB BIT(4) BIT 956 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define V15_VLD BIT(5) BIT 957 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TRP_B15V_EN BIT(7) BIT 958 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SIC_IDLE BIT(8) BIT 959 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BD_MAC2 BIT(9) BIT 960 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BD_MAC1 BIT(10) BIT 961 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IC_MACPHY_MODE BIT(11) BIT 962 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define VENDOR_ID BIT(19) BIT 963 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PAD_HWPD_IDN BIT(22) BIT 964 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TRP_VAUX_EN BIT(23) BIT 965 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TRP_BT_EN BIT(24) BIT 966 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BD_PKG_SEL BIT(25) BIT 967 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BD_HCI_SEL BIT(26) BIT 968 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TYPE_ID BIT(27) BIT 975 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HCI_TXDMA_EN BIT(0) BIT 976 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HCI_RXDMA_EN BIT(1) BIT 977 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TXDMA_EN BIT(2) BIT 978 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RXDMA_EN BIT(3) BIT 979 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PROTOCOL_EN BIT(4) BIT 980 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SCHEDULE_EN BIT(5) BIT 981 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define MACTXEN BIT(6) BIT 982 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define MACRXEN BIT(7) BIT 983 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ENSWBCN BIT(8) BIT 984 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ENSEC BIT(9) BIT 1014 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RXDMA_ARBBW_EN BIT(0) BIT 1015 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RXSHFT_EN BIT(1) BIT 1016 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RXDMA_AGG_EN BIT(2) BIT 1017 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define QS_VO_QUEUE BIT(8) BIT 1018 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define QS_VI_QUEUE BIT(9) BIT 1019 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define QS_BE_QUEUE BIT(10) BIT 1020 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define QS_BK_QUEUE BIT(11) BIT 1021 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define QS_MANAGER_QUEUE BIT(12) BIT 1022 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define QS_HIGH_QUEUE BIT(13) BIT 1024 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HQSEL_VOQ BIT(0) BIT 1025 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HQSEL_VIQ BIT(1) BIT 1026 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HQSEL_BEQ BIT(2) BIT 1027 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HQSEL_BKQ BIT(3) BIT 1028 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HQSEL_MGTQ BIT(4) BIT 1029 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HQSEL_HIQ BIT(5) BIT 1051 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) BIT 1052 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BB_WRITE_EN BIT(30) BIT 1053 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BB_READ_EN BIT(31) BIT 1060 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HPQ_PUBLIC_DIS BIT(24) BIT 1061 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LPQ_PUBLIC_DIS BIT(25) BIT 1062 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LD_RQPN BIT(31) BIT 1064 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BCN_VALID BIT(16) BIT 1071 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define DROP_DATA_EN BIT(9) BIT 1073 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define EN_AMPDU_RTY_NEW BIT(7) BIT 1090 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define USE_SHORT_G1 BIT(20) BIT 1145 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define DIS_EDCA_CNT_DWN BIT(11) BIT 1147 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define EN_MBSSID BIT(1) BIT 1148 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define EN_TXBCN_RPT BIT(2) BIT 1149 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define EN_BCN_FUNCTION BIT(3) BIT 1151 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TSFTR_RST BIT(0) BIT 1152 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TSFTR1_RST BIT(1) BIT 1154 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define STOP_BCNQ BIT(6) BIT 1156 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) BIT 1157 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define DIS_TSF_UDT0_TEST_CHIP BIT(5) BIT 1159 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACMHW_HWEN BIT(0) BIT 1160 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACMHW_BEQEN BIT(1) BIT 1161 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACMHW_VIQEN BIT(2) BIT 1162 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACMHW_VOQEN BIT(3) BIT 1163 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACMHW_BEQSTATUS BIT(4) BIT 1164 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACMHW_VIQSTATUS BIT(5) BIT 1165 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACMHW_VOQSTATUS BIT(6) BIT 1167 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APSDOFF BIT(6) BIT 1168 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APSDOFF_STATUS BIT(7) BIT 1170 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BW_20MHZ BIT(2) BIT 1176 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TSFRST BIT(0) BIT 1177 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define DIS_GCLK BIT(1) BIT 1178 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PAD_SEL BIT(2) BIT 1179 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PWR_ST BIT(6) BIT 1180 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PWRBIT_OW_EN BIT(7) BIT 1181 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACRC BIT(8) BIT 1182 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CFENDFORM BIT(9) BIT 1183 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ICV BIT(10) BIT 1185 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define AAP BIT(0) BIT 1186 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APM BIT(1) BIT 1187 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define AM BIT(2) BIT 1188 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define AB BIT(3) BIT 1189 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ADD3 BIT(4) BIT 1190 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APWRMGT BIT(5) BIT 1191 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CBSSID BIT(6) BIT 1192 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CBSSID_DATA BIT(6) BIT 1193 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define CBSSID_BCN BIT(7) BIT 1194 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACRC32 BIT(8) BIT 1195 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define AICV BIT(9) BIT 1196 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ADF BIT(11) BIT 1197 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACF BIT(12) BIT 1198 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define AMF BIT(13) BIT 1199 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HTC_LOC_CTRL BIT(14) BIT 1200 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define UC_DATA_EN BIT(16) BIT 1201 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BM_DATA_EN BIT(17) BIT 1202 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define MFBEN BIT(22) BIT 1203 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define LSIGEN BIT(23) BIT 1204 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ENMBID BIT(24) BIT 1205 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APP_BASSN BIT(27) BIT 1206 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APP_PHYSTS BIT(28) BIT 1207 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APP_ICV BIT(29) BIT 1208 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APP_MIC BIT(30) BIT 1209 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define APP_FCS BIT(31) BIT 1230 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define RXERR_RPT_RST BIT(27) BIT 1233 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SCR_TXUSEDK BIT(0) BIT 1234 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SCR_RXUSEDK BIT(1) BIT 1235 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SCR_TXENCENABLE BIT(2) BIT 1236 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SCR_RXDECENABLE BIT(3) BIT 1237 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SCR_SKBYA2 BIT(4) BIT 1238 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SCR_NOSKMC BIT(5) BIT 1239 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SCR_TXBCUSEDK BIT(6) BIT 1240 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SCR_RXBCUSEDK BIT(7) BIT 1242 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define XCLK_VLD BIT(0) BIT 1243 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define ACLK_VLD BIT(1) BIT 1244 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define UCLK_VLD BIT(2) BIT 1245 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PCLK_VLD BIT(3) BIT 1246 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PCIRSTB BIT(4) BIT 1247 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define V15_VLD BIT(5) BIT 1248 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TRP_B15V_EN BIT(7) BIT 1249 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define SIC_IDLE BIT(8) BIT 1250 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BD_MAC2 BIT(9) BIT 1251 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BD_MAC1 BIT(10) BIT 1252 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define IC_MACPHY_MODE BIT(11) BIT 1253 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BT_FUNC BIT(16) BIT 1254 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define VENDOR_ID BIT(19) BIT 1255 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define PAD_HWPD_IDN BIT(22) BIT 1256 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TRP_VAUX_EN BIT(23) BIT 1257 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TRP_BT_EN BIT(24) BIT 1258 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BD_PKG_SEL BIT(25) BIT 1259 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BD_HCI_SEL BIT(26) BIT 1260 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define TYPE_ID BIT(27) BIT 1264 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define USB_SPEED_MASK BIT(5) BIT 1272 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define USB_AGG_EN BIT(3) BIT 1289 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) BIT 2372 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WL_HWPDN_EN BIT(0) BIT 2374 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WL_HWPDN_SL BIT(1) BIT 2376 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WL_FUNC_EN BIT(2) BIT 2378 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define WL_HWROF_EN BIT(3) BIT 2380 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BT_HWPDN_EN BIT(16) BIT 2382 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BT_HWPDN_SL BIT(17) BIT 2384 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BT_FUNC_EN BIT(18) BIT 2386 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define BT_HWROF_EN BIT(19) BIT 2388 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define GPS_HWPDN_EN BIT(20) BIT 2390 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define GPS_HWPDN_SL BIT(21) BIT 2392 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h #define GPS_FUNC_EN BIT(22) BIT 17 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rf.c rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3); BIT 18 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rf.c rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3); BIT 21 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rf.c rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1); BIT 22 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rf.c rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1); BIT 25 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rf.c rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0); BIT 26 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rf.c rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0); BIT 84 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25); BIT 36 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c ret_val = ret_val | BIT(12); BIT 477 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c wake_match = BIT(2); BIT 479 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c wake_match = BIT(1); BIT 481 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c wake_match = BIT(0); BIT 984 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4)); BIT 987 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c BIT(0) << (hw_queue)); BIT 29 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(24)); BIT 34 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(25)); BIT 39 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(26)); BIT 44 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(27)); BIT 49 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(28)); BIT 54 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 59 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc), BIT(31)); BIT 89 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 2, __val, BIT(12)); BIT 94 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 2, __val, BIT(13)); BIT 99 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 2, __val, BIT(17)); BIT 114 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 3, __val, BIT(8)); BIT 119 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 3, __val, BIT(10)); BIT 124 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 3, __val, BIT(11)); BIT 129 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 3, __val, BIT(12)); BIT 134 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 3, __val, BIT(13)); BIT 139 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 3, __val, BIT(15)); BIT 179 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 5, __val, BIT(4)); BIT 189 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 5, __val, BIT(12)); BIT 204 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc + 8, __val, BIT(15)); BIT 234 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc), BIT(14)); BIT 239 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc), BIT(15)); BIT 254 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc), BIT(26)); BIT 259 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc), BIT(27)); BIT 264 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc), BIT(31)); BIT 274 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(30)); BIT 279 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h le32p_replace_bits(__pdesc, __val, BIT(31)); BIT 289 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc + 1), BIT(15)); BIT 294 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc + 1), BIT(28)); BIT 304 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc + 3), BIT(29)); BIT 309 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc + 3), BIT(30)); BIT 314 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc + 3), BIT(31)); BIT 319 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h return le32_get_bits(*(__pdesc + 4), BIT(0)); BIT 52 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RF_CHANGE_BY_IPS BIT(28) BIT 53 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RF_CHANGE_BY_PS BIT(29) BIT 54 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RF_CHANGE_BY_HW BIT(30) BIT 55 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RF_CHANGE_BY_SW BIT(31) BIT 219 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WAKE_ON_MAGIC_PACKET BIT(0) BIT 220 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WAKE_ON_PATTERN_MATCH BIT(1) BIT 222 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_PTK_UPDATE BIT(0) BIT 223 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_GTK_UPDATE BIT(1) BIT 224 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_DISASSOC BIT(2) BIT 225 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_DEAUTH BIT(3) BIT 226 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_AP_LOST BIT(4) BIT 227 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_MAGIC_PKT BIT(5) BIT 228 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_UNICAST_PKT BIT(6) BIT 229 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_PATTERN_PKT BIT(7) BIT 230 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_RTD3_SSID_MATCH BIT(8) BIT 231 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) BIT 232 drivers/net/wireless/realtek/rtlwifi/wifi.h #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) BIT 298 drivers/net/wireless/realtek/rtlwifi/wifi.h RF_MASK_A = BIT(0), BIT 299 drivers/net/wireless/realtek/rtlwifi/wifi.h RF_MASK_B = BIT(1), BIT 300 drivers/net/wireless/realtek/rtlwifi/wifi.h RF_MASK_C = BIT(2), BIT 301 drivers/net/wireless/realtek/rtlwifi/wifi.h RF_MASK_D = BIT(3), BIT 982 drivers/net/wireless/realtek/rtlwifi/wifi.h RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */ BIT 983 drivers/net/wireless/realtek/rtlwifi/wifi.h RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */ BIT 984 drivers/net/wireless/realtek/rtlwifi/wifi.h RTL_SPEC_EXT_C2H = BIT(2), /* extend FW C2H (e.g. TX REPORT) */ BIT 3033 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ BIT 3034 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ BIT 3035 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ BIT 3037 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) BIT 3038 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ BIT 3039 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ BIT 3041 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) BIT 3043 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RT_PS_LEVEL_ASPM BIT(7) BIT 3045 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RT_RF_LPS_DISALBE_2R BIT(30) BIT 3046 drivers/net/wireless/realtek/rtlwifi/wifi.h #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ BIT 3066 drivers/net/wireless/realtek/rtlwifi/wifi.h #define LDPC_HT_ENABLE_RX BIT(0) BIT 3067 drivers/net/wireless/realtek/rtlwifi/wifi.h #define LDPC_HT_ENABLE_TX BIT(1) BIT 3068 drivers/net/wireless/realtek/rtlwifi/wifi.h #define LDPC_HT_TEST_TX_ENABLE BIT(2) BIT 3069 drivers/net/wireless/realtek/rtlwifi/wifi.h #define LDPC_HT_CAP_TX BIT(3) BIT 3071 drivers/net/wireless/realtek/rtlwifi/wifi.h #define STBC_HT_ENABLE_RX BIT(0) BIT 3072 drivers/net/wireless/realtek/rtlwifi/wifi.h #define STBC_HT_ENABLE_TX BIT(1) BIT 3073 drivers/net/wireless/realtek/rtlwifi/wifi.h #define STBC_HT_TEST_TX_ENABLE BIT(2) BIT 3074 drivers/net/wireless/realtek/rtlwifi/wifi.h #define STBC_HT_CAP_TX BIT(3) BIT 3076 drivers/net/wireless/realtek/rtlwifi/wifi.h #define LDPC_VHT_ENABLE_RX BIT(0) BIT 3077 drivers/net/wireless/realtek/rtlwifi/wifi.h #define LDPC_VHT_ENABLE_TX BIT(1) BIT 3078 drivers/net/wireless/realtek/rtlwifi/wifi.h #define LDPC_VHT_TEST_TX_ENABLE BIT(2) BIT 3079 drivers/net/wireless/realtek/rtlwifi/wifi.h #define LDPC_VHT_CAP_TX BIT(3) BIT 3081 drivers/net/wireless/realtek/rtlwifi/wifi.h #define STBC_VHT_ENABLE_RX BIT(0) BIT 3082 drivers/net/wireless/realtek/rtlwifi/wifi.h #define STBC_VHT_ENABLE_TX BIT(1) BIT 3083 drivers/net/wireless/realtek/rtlwifi/wifi.h #define STBC_VHT_TEST_TX_ENABLE BIT(2) BIT 3084 drivers/net/wireless/realtek/rtlwifi/wifi.h #define STBC_VHT_CAP_TX BIT(3) BIT 250 drivers/net/wireless/realtek/rtw88/coex.c rtw_write8_mask(rtwdev, addr, BIT(bitmap), data); BIT 853 drivers/net/wireless/realtek/rtw88/coex.c if (ap_enable && (byte1 & BIT(4) && !(byte1 & BIT(5)))) { BIT 854 drivers/net/wireless/realtek/rtw88/coex.c byte1 &= ~BIT(4); BIT 855 drivers/net/wireless/realtek/rtw88/coex.c byte1 |= BIT(5); BIT 857 drivers/net/wireless/realtek/rtw88/coex.c byte5 |= BIT(5); BIT 858 drivers/net/wireless/realtek/rtw88/coex.c byte5 &= ~BIT(6); BIT 862 drivers/net/wireless/realtek/rtw88/coex.c } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { BIT 2063 drivers/net/wireless/realtek/rtw88/coex.c rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT(0) | BIT(1)); BIT 2335 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_inq_page = ((coex_stat->bt_info_lb2 & BIT(2)) == BIT(2)); BIT 2336 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_acl_busy = ((coex_stat->bt_info_lb2 & BIT(3)) == BIT(3)); BIT 2341 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_fix_2M = ((coex_stat->bt_info_lb3 & BIT(4)) == BIT(4)); BIT 2342 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_inq = ((coex_stat->bt_info_lb3 & BIT(5)) == BIT(5)); BIT 2346 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_page = ((coex_stat->bt_info_lb3 & BIT(7)) == BIT(7)); BIT 2371 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_ble_exist = ((coex_stat->bt_info_hb1 & BIT(0)) == BIT(0)); BIT 2372 drivers/net/wireless/realtek/rtw88/coex.c if (coex_stat->bt_info_hb1 & BIT(1)) BIT 2375 drivers/net/wireless/realtek/rtw88/coex.c if (coex_stat->bt_info_hb1 & BIT(2)) { BIT 2388 drivers/net/wireless/realtek/rtw88/coex.c if (coex_stat->bt_info_hb1 & BIT(3)) BIT 2391 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_ble_voice = ((coex_stat->bt_info_hb1 & BIT(4)) == BIT(4)); BIT 2392 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_ble_scan_en = ((coex_stat->bt_info_hb1 & BIT(5)) == BIT(5)); BIT 2393 drivers/net/wireless/realtek/rtw88/coex.c if (coex_stat->bt_info_hb1 & BIT(6)) BIT 2396 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_multi_link = ((coex_stat->bt_info_hb1 & BIT(7)) == BIT(7)); BIT 2398 drivers/net/wireless/realtek/rtw88/coex.c if ((coex_stat->bt_info_hb1 & BIT(1))) { BIT 2407 drivers/net/wireless/realtek/rtw88/coex.c if ((coex_stat->bt_info_hb1 & BIT(3)) && BIT 2408 drivers/net/wireless/realtek/rtw88/coex.c (!(coex_stat->bt_info_hb1 & BIT(2)))) BIT 2411 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_opp_exist = ((coex_stat->bt_info_hb2 & BIT(0)) == BIT(0)); BIT 2412 drivers/net/wireless/realtek/rtw88/coex.c if (coex_stat->bt_info_hb2 & BIT(1)) BIT 2415 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_a2dp_active = (coex_stat->bt_info_hb2 & BIT(2)) == BIT(2); BIT 2416 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_slave = ((coex_stat->bt_info_hb2 & BIT(3)) == BIT(3)); BIT 2429 drivers/net/wireless/realtek/rtw88/coex.c coex_stat->bt_a2dp_sink = ((coex_stat->bt_info_hb3 & BIT(7)) == BIT(7)); BIT 9 drivers/net/wireless/realtek/rtw88/coex.h #define BPM_HFP BIT(0) BIT 10 drivers/net/wireless/realtek/rtw88/coex.h #define BPM_HID BIT(1) BIT 11 drivers/net/wireless/realtek/rtw88/coex.h #define BPM_A2DP BIT(2) BIT 12 drivers/net/wireless/realtek/rtw88/coex.h #define BPM_PAN BIT(3) BIT 31 drivers/net/wireless/realtek/rtw88/coex.h #define TDMA_4SLOT BIT(8) BIT 147 drivers/net/wireless/realtek/rtw88/coex.h COEX_SCBD_ACTIVE = BIT(0), BIT 148 drivers/net/wireless/realtek/rtw88/coex.h COEX_SCBD_ONOFF = BIT(1), BIT 149 drivers/net/wireless/realtek/rtw88/coex.h COEX_SCBD_SCAN = BIT(2), BIT 150 drivers/net/wireless/realtek/rtw88/coex.h COEX_SCBD_UNDERTEST = BIT(3), BIT 151 drivers/net/wireless/realtek/rtw88/coex.h COEX_SCBD_RXGAIN = BIT(4), BIT 152 drivers/net/wireless/realtek/rtw88/coex.h COEX_SCBD_BT_RFK = BIT(5), BIT 153 drivers/net/wireless/realtek/rtw88/coex.h COEX_SCBD_WLBUSY = BIT(6), BIT 154 drivers/net/wireless/realtek/rtw88/coex.h COEX_SCBD_EXTFEM = BIT(8), BIT 155 drivers/net/wireless/realtek/rtw88/coex.h COEX_SCBD_TDMA = BIT(9), BIT 156 drivers/net/wireless/realtek/rtw88/coex.h COEX_SCBD_FIX2M = BIT(10), BIT 21 drivers/net/wireless/realtek/rtw88/efuse.c (((word_en) & BIT(i)) != 0x0) BIT 779 drivers/net/wireless/realtek/rtw88/fw.c rtw_write8(rtwdev, REG_RCR, rcr | BIT(3)); BIT 141 drivers/net/wireless/realtek/rtw88/fw.h le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) BIT 143 drivers/net/wireless/realtek/rtw88/fw.h le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) BIT 164 drivers/net/wireless/realtek/rtw88/fw.h le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) BIT 185 drivers/net/wireless/realtek/rtw88/fw.h le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) BIT 193 drivers/net/wireless/realtek/rtw88/fw.h le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) BIT 197 drivers/net/wireless/realtek/rtw88/fw.h le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) BIT 199 drivers/net/wireless/realtek/rtw88/fw.h le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) BIT 203 drivers/net/wireless/realtek/rtw88/fw.h le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) BIT 213 drivers/net/wireless/realtek/rtw88/fw.h le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) BIT 233 drivers/net/wireless/realtek/rtw88/fw.h le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) BIT 124 drivers/net/wireless/realtek/rtw88/mac.c value |= BIT(3); BIT 126 drivers/net/wireless/realtek/rtw88/mac.c value &= ~BIT(3); BIT 197 drivers/net/wireless/realtek/rtw88/mac.c intf_mask = BIT(2); BIT 200 drivers/net/wireless/realtek/rtw88/mac.c intf_mask = BIT(1); BIT 239 drivers/net/wireless/realtek/rtw88/mac.c (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0))) BIT 322 drivers/net/wireless/realtek/rtw88/mac.c emem_size = ((*(data + FW_HDR_MEM_USAGE)) & BIT(4)) ? BIT 600 drivers/net/wireless/realtek/rtw88/mac.c emem_size = ((*(data + FW_HDR_MEM_USAGE)) & BIT(4)) ? BIT 612 drivers/net/wireless/realtek/rtw88/mac.c addr &= ~BIT(31); BIT 619 drivers/net/wireless/realtek/rtw88/mac.c addr &= ~BIT(31); BIT 627 drivers/net/wireless/realtek/rtw88/mac.c addr &= ~BIT(31); BIT 945 drivers/net/wireless/realtek/rtw88/mac.c rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9)); BIT 369 drivers/net/wireless/realtek/rtw88/main.c bw |= BIT(RTW_CHANNEL_WIDTH_80); BIT 372 drivers/net/wireless/realtek/rtw88/main.c bw |= BIT(RTW_CHANNEL_WIDTH_40); BIT 375 drivers/net/wireless/realtek/rtw88/main.c bw |= BIT(RTW_CHANNEL_WIDTH_20); BIT 775 drivers/net/wireless/realtek/rtw88/main.c if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) BIT 1077 drivers/net/wireless/realtek/rtw88/main.c if (efuse->bt_setting & BIT(0)) BIT 1083 drivers/net/wireless/realtek/rtw88/main.c efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; BIT 1084 drivers/net/wireless/realtek/rtw88/main.c efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; BIT 1085 drivers/net/wireless/realtek/rtw88/main.c efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; BIT 1086 drivers/net/wireless/realtek/rtw88/main.c efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; BIT 1245 drivers/net/wireless/realtek/rtw88/main.c hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 1246 drivers/net/wireless/realtek/rtw88/main.c BIT(NL80211_IFTYPE_AP) | BIT 1247 drivers/net/wireless/realtek/rtw88/main.c BIT(NL80211_IFTYPE_ADHOC) | BIT 1248 drivers/net/wireless/realtek/rtw88/main.c BIT(NL80211_IFTYPE_MESH_POINT); BIT 105 drivers/net/wireless/realtek/rtw88/main.h BB_PATH_A = BIT(0), BIT 106 drivers/net/wireless/realtek/rtw88/main.h BB_PATH_B = BIT(1), BIT 107 drivers/net/wireless/realtek/rtw88/main.h BB_PATH_C = BIT(2), BIT 108 drivers/net/wireless/realtek/rtw88/main.h BB_PATH_D = BIT(3), BIT 144 drivers/net/wireless/realtek/rtw88/main.h #define HT_STBC_EN BIT(0) BIT 145 drivers/net/wireless/realtek/rtw88/main.h #define VHT_STBC_EN BIT(1) BIT 146 drivers/net/wireless/realtek/rtw88/main.h #define HT_LDPC_EN BIT(0) BIT 147 drivers/net/wireless/realtek/rtw88/main.h #define VHT_LDPC_EN BIT(1) BIT 444 drivers/net/wireless/realtek/rtw88/main.h PORT_SET_MAC_ADDR = BIT(0), BIT 445 drivers/net/wireless/realtek/rtw88/main.h PORT_SET_BSSID = BIT(1), BIT 446 drivers/net/wireless/realtek/rtw88/main.h PORT_SET_NET_TYPE = BIT(2), BIT 447 drivers/net/wireless/realtek/rtw88/main.h PORT_SET_AID = BIT(3), BIT 448 drivers/net/wireless/realtek/rtw88/main.h PORT_SET_BCN_CTRL = BIT(4), BIT 672 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_INTF_SDIO_MSK BIT(0) BIT 673 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_INTF_USB_MSK BIT(1) BIT 674 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_INTF_PCI_MSK BIT(2) BIT 675 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) BIT 677 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_CUT_A_MSK BIT(1) BIT 678 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_CUT_B_MSK BIT(2) BIT 679 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_CUT_C_MSK BIT(3) BIT 680 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_CUT_D_MSK BIT(4) BIT 681 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_CUT_E_MSK BIT(5) BIT 682 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_CUT_F_MSK BIT(6) BIT 683 drivers/net/wireless/realtek/rtw88/main.h #define RTW_PWR_CUT_G_MSK BIT(7) BIT 714 drivers/net/wireless/realtek/rtw88/main.h RTW_INTF_PHY_CUT_A = BIT(0), BIT 715 drivers/net/wireless/realtek/rtw88/main.h RTW_INTF_PHY_CUT_B = BIT(1), BIT 716 drivers/net/wireless/realtek/rtw88/main.h RTW_INTF_PHY_CUT_C = BIT(2), BIT 717 drivers/net/wireless/realtek/rtw88/main.h RTW_INTF_PHY_CUT_D = BIT(3), BIT 718 drivers/net/wireless/realtek/rtw88/main.h RTW_INTF_PHY_CUT_E = BIT(4), BIT 719 drivers/net/wireless/realtek/rtw88/main.h RTW_INTF_PHY_CUT_F = BIT(5), BIT 720 drivers/net/wireless/realtek/rtw88/main.h RTW_INTF_PHY_CUT_G = BIT(6), BIT 968 drivers/net/wireless/realtek/rtw88/main.h #define COEX_INFO_FTP BIT(7) BIT 969 drivers/net/wireless/realtek/rtw88/main.h #define COEX_INFO_A2DP BIT(6) BIT 970 drivers/net/wireless/realtek/rtw88/main.h #define COEX_INFO_HID BIT(5) BIT 971 drivers/net/wireless/realtek/rtw88/main.h #define COEX_INFO_SCO_BUSY BIT(4) BIT 972 drivers/net/wireless/realtek/rtw88/main.h #define COEX_INFO_ACL_BUSY BIT(3) BIT 973 drivers/net/wireless/realtek/rtw88/main.h #define COEX_INFO_INQ_PAGE BIT(2) BIT 974 drivers/net/wireless/realtek/rtw88/main.h #define COEX_INFO_SCO_ESCO BIT(1) BIT 975 drivers/net/wireless/realtek/rtw88/main.h #define COEX_INFO_CONNECTION BIT(0) BIT 1231 drivers/net/wireless/realtek/rtw88/main.h #define INTF_PCIE BIT(0) BIT 1232 drivers/net/wireless/realtek/rtw88/main.h #define INTF_USB BIT(1) BIT 1233 drivers/net/wireless/realtek/rtw88/main.h #define INTF_SDIO BIT(2) BIT 1002 drivers/net/wireless/realtek/rtw88/pci.c write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12))); BIT 1053 drivers/net/wireless/realtek/rtw88/pci.c cut = BIT(0) << rtwdev->hal.cut_version; BIT 20 drivers/net/wireless/realtek/rtw88/pci.h #define BIT_RST_TRXDMA_INTF BIT(20) BIT 21 drivers/net/wireless/realtek/rtw88/pci.h #define BIT_RX_TAG_EN BIT(15) BIT 26 drivers/net/wireless/realtek/rtw88/pci.h #define BIT_MDIO_WFLAG_V1 BIT(5) BIT 28 drivers/net/wireless/realtek/rtw88/pci.h #define BIT_PCI_BCNQ_FLAG BIT(4) BIT 60 drivers/net/wireless/realtek/rtw88/pci.h #define BIT_CLR_H2CQ_HOST_IDX BIT(16) BIT 61 drivers/net/wireless/realtek/rtw88/pci.h #define BIT_CLR_H2CQ_HW_IDX BIT(8) BIT 72 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_TIMER2 BIT(31) BIT 73 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_TIMER1 BIT(30) BIT 74 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_PSTIMEOUT BIT(29) BIT 75 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_GTINT4 BIT(28) BIT 76 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_GTINT3 BIT(27) BIT 77 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_TBDER BIT(26) BIT 78 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_TBDOK BIT(25) BIT 79 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_TSF_BIT32_TOGGLE BIT(24) BIT 80 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDMAINT0 BIT(20) BIT 81 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDOK0 BIT(16) BIT 82 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_HSISR_IND_ON_INT BIT(15) BIT 83 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDMAINT_E BIT(14) BIT 84 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_ATIMEND BIT(12) BIT 85 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_HISR1_IND_INT BIT(11) BIT 86 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_C2HCMD BIT(10) BIT 87 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_CPWM2 BIT(9) BIT 88 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_CPWM BIT(8) BIT 89 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_HIGHDOK BIT(7) BIT 90 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_MGNTDOK BIT(6) BIT 91 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BKDOK BIT(5) BIT 92 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BEDOK BIT(4) BIT 93 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_VIDOK BIT(3) BIT 94 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_VODOK BIT(2) BIT 95 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_RDU BIT(1) BIT 96 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_ROK BIT(0) BIT 98 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_TXFIFO_TH_INT BIT(30) BIT 99 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BTON_STS_UPDATE BIT(29) BIT 100 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_MCUERR BIT(28) BIT 101 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDMAINT7 BIT(27) BIT 102 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDMAINT6 BIT(26) BIT 103 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDMAINT5 BIT(25) BIT 104 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDMAINT4 BIT(24) BIT 105 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDMAINT3 BIT(23) BIT 106 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDMAINT2 BIT(22) BIT 107 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDMAINT1 BIT(21) BIT 108 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDOK7 BIT(20) BIT 109 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDOK6 BIT(19) BIT 110 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDOK5 BIT(18) BIT 111 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDOK4 BIT(17) BIT 112 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDOK3 BIT(16) BIT 113 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDOK2 BIT(15) BIT 114 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_BCNDOK1 BIT(14) BIT 115 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_ATIMEND_E BIT(13) BIT 116 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_ATIMEND BIT(12) BIT 117 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_TXERR BIT(11) BIT 118 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_RXERR BIT(10) BIT 119 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_TXFOVW BIT(9) BIT 120 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_RXFOVW BIT(8) BIT 121 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_CPU_MGQ_TXDONE BIT(5) BIT 122 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_PS_TIMER_C BIT(4) BIT 123 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_PS_TIMER_B BIT(3) BIT 124 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_PS_TIMER_A BIT(2) BIT 125 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_CPUMGQ_TX_TIMER BIT(1) BIT 127 drivers/net/wireless/realtek/rtw88/pci.h #define IMR_H2CDOK BIT(16) BIT 1425 drivers/net/wireless/realtek/rtw88/phy.c rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1); BIT 1426 drivers/net/wireless/realtek/rtw88/phy.c rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1); BIT 1427 drivers/net/wireless/realtek/rtw88/phy.c rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1); BIT 1428 drivers/net/wireless/realtek/rtw88/phy.c rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1); BIT 1429 drivers/net/wireless/realtek/rtw88/phy.c rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0); BIT 9 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_FEN_CPUEN BIT(2) BIT 10 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_FEN_BB_GLB_RST BIT(1) BIT 11 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_FEN_BB_RSTB BIT(0) BIT 14 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_CPU_CLK_EN BIT(14) BIT 19 drivers/net/wireless/realtek/rtw88/reg.h #define BITS_RFC_DIRECT (BIT(31) | BIT(30)) BIT 20 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_WLMCU_IOIF BIT(0) BIT 22 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RF_SDM_RSTB BIT(2) BIT 23 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RF_RSTB BIT(1) BIT 24 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RF_EN BIT(0) BIT 27 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_MAC_CLK_SEL (BIT(20) | BIT(21)) BIT 29 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_EF_FLAG BIT(31) BIT 36 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_MASK_EFUSE_BANK_SEL (BIT(8) | BIT(9)) BIT 39 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_FSPI_EN BIT(19) BIT 40 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BT_AOD_GPIO3 BIT(9) BIT 41 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BT_PTA_EN BIT(5) BIT 42 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_WLRFE_4_5_EN BIT(2) BIT 45 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_LNAON_SEL_EN BIT(26) BIT 46 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_PAPE_SEL_EN BIT(25) BIT 47 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DPDT_WL_SEL BIT(24) BIT 48 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DPDT_SEL_EN BIT(23) BIT 50 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_PAPE_WLBT_SEL BIT(29) BIT 51 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_LNAON_WLBT_SEL BIT(28) BIT 52 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BTGP_JTAG_EN BIT(24) BIT 53 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BTGP_SPI_EN BIT(20) BIT 54 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_LED1DIS BIT(15) BIT 55 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_SW_DPDT_SEL_DATA BIT(0) BIT 57 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BT_FUNC_EN BIT(18) BIT 58 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BT_DIG_CLK_EN BIT(8) BIT 60 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DBG_GNT_WL_BT BIT(27) BIT 61 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_LTE_MUX_CTRL_PATH BIT(26) BIT 65 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_ANA_PORT_EN BIT(22) BIT 66 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_MAC_PORT_EN BIT(21) BIT 67 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BOOT_FSPI_EN BIT(20) BIT 68 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_FW_INIT_RDY BIT(15) BIT 69 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_FW_DW_RDY BIT(14) BIT 70 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RPWM_TOGGLE BIT(7) BIT 71 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DMEM_CHKSUM_OK BIT(6) BIT 72 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DMEM_DW_OK BIT(5) BIT 73 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_IMEM_CHKSUM_OK BIT(4) BIT 74 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_IMEM_DW_OK BIT(3) BIT 75 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2) BIT 76 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_MCUFWDL_EN BIT(0) BIT 77 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_CHECK_SUM_OK (BIT(4) | BIT(6)) BIT 85 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BT_INT_EN BIT(15) BIT 87 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RTL_ID BIT(23) BIT 88 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RF_TYPE_ID BIT(27) BIT 105 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_WLRF1_BBRF_EN (BIT(24) | BIT(25) | BIT(26)) BIT 107 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_32K_CAL_TMR_EN BIT(10) BIT 108 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_MAC_SEC_EN BIT(9) BIT 109 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_ENSWBCN BIT(8) BIT 110 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_MACRXEN BIT(7) BIT 111 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_MACTXEN BIT(6) BIT 112 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_SCHEDULE_EN BIT(5) BIT 113 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_PROTOCOL_EN BIT(4) BIT 114 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXDMA_EN BIT(3) BIT 115 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_TXDMA_EN BIT(2) BIT 116 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_HCI_RXDMA_EN BIT(1) BIT 117 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_HCI_TXDMA_EN BIT(0) BIT 176 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BCN_VALID_V1 BIT(15) BIT 179 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_AUTO_INIT_LLT_V1 BIT(0) BIT 182 drivers/net/wireless/realtek/rtw88/reg.h #define BTI_PAGE_OVF BIT(2) BIT 185 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_LD_RQPN BIT(31) BIT 199 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_EN_BCNQ_DL BIT(22) BIT 200 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_EN_WR_FREE_TAIL BIT(20) BIT 203 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BA_PARSER_EN BIT(5) BIT 214 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_CHECK_CCK_EN BIT(7) BIT 218 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_EN_GNT_BT_AWAKE BIT(3) BIT 219 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_EN_EOF_V1 BIT(2) BIT 222 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_WL_RFK BIT(0) BIT 227 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_PRE_TX_CMD BIT(6) BIT 229 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_PTA_WL_TX_EN BIT(4) BIT 230 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_PTA_EDCCA_EN BIT(5) BIT 234 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BTCCA_CTRL (BIT(0) | BIT(1)) BIT 235 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_EN_PRECNT BIT(11) BIT 249 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_SIFS_BK_EN BIT(12) BIT 252 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DIS_TXOP_CFE BIT(10) BIT 253 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DIS_LSIG_CFE BIT(9) BIT 254 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DIS_STBC_CFE BIT(8) BIT 259 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DIS_TSF_UDT BIT(4) BIT 260 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_EN_BCN_FUNCTION BIT(3) BIT 268 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_EN_FREE_CNT BIT(3) BIT 269 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1)) BIT 271 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_TSFT_SEL_TIMER0 (BIT(4) | BIT(5) | BIT(6)) BIT 275 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_APP_FCS BIT(31) BIT 276 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_APP_MIC BIT(30) BIT 277 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_APP_ICV BIT(29) BIT 278 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_APP_PHYSTS BIT(28) BIT 279 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_APP_BASSN BIT(27) BIT 280 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_VHT_DACK BIT(26) BIT 281 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_TCPOFLD_EN BIT(25) BIT 282 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_ENMBID BIT(24) BIT 283 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_LSIGEN BIT(23) BIT 284 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_MFBEN BIT(22) BIT 285 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DISCHKPPDLLEN BIT(21) BIT 286 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_PKTCTL_DLEN BIT(20) BIT 287 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_TIM_PARSER_EN BIT(18) BIT 288 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_BC_MD_EN BIT(17) BIT 289 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_UC_MD_EN BIT(16) BIT 290 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXSK_PERPKT BIT(15) BIT 291 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_HTC_LOC_CTRL BIT(14) BIT 292 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RPFM_CAM_ENABLE BIT(12) BIT 293 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_TA_BCN BIT(11) BIT 294 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DISDECMYPKT BIT(10) BIT 295 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_AICV BIT(9) BIT 296 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_ACRC32 BIT(8) BIT 297 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_CBSSID_BCN BIT(7) BIT 298 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_CBSSID_DATA BIT(6) BIT 299 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_APWRMGT BIT(5) BIT 300 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_ADD3 BIT(4) BIT 301 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_AB BIT(3) BIT 302 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_AM BIT(2) BIT 303 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_APM BIT(1) BIT 304 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_AAP BIT(0) BIT 307 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_APP_PHYSTS BIT(28) BIT 316 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RFMOD (BIT(7) | BIT(8)) BIT 317 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RFMOD_80M BIT(8) BIT 318 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RFMOD_40M BIT(7) BIT 333 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_GNT_BT_POLARITY BIT(4) BIT 334 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_LTE_COEX_EN BIT(7) BIT 346 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATE6M BIT(0) BIT 347 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATE9M BIT(1) BIT 348 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATEMCS0 BIT(2) BIT 349 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATEMCS1 BIT(3) BIT 350 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATEMCS8 BIT(4) BIT 351 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATEMCS9 BIT(5) BIT 352 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATEVHT1SS_MCS0 BIT(6) BIT 353 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATEVHT1SS_MCS1 BIT(7) BIT 354 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATEVHT2SS_MCS0 BIT(8) BIT 355 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATEVHT2SS_MCS1 BIT(9) BIT 363 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RFE_BUF_EN BIT(3) BIT 367 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_WL_PLATFORM_RST BIT(16) BIT 368 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_WL_SECURITY_CLK BIT(15) BIT 369 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DDMA_EN BIT(8) BIT 381 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DDMACH0_OWN BIT(31) BIT 382 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DDMACH0_CHKSUM_EN BIT(29) BIT 383 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DDMACH0_CHKSUM_STS BIT(27) BIT 384 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) BIT 385 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DDMACH0_CHKSUM_CONT BIT(24) BIT 389 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_H2CQ_FULL BIT(31) BIT 394 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXGCK_FIFOTHR_EN BIT(28) BIT 424 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXGCK_OFDMCCA_EN BIT(16) BIT 436 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXPSF_CTRLEN BIT(12) BIT 437 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXPSF_VHTCHKEN BIT(11) BIT 438 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXPSF_HTCHKEN BIT(10) BIT 439 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXPSF_OFDMCHKEN BIT(9) BIT 440 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXPSF_CCKCHKEN BIT(8) BIT 441 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXPSF_OFDMRST BIT(7) BIT 442 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXPSF_CCKRST BIT(6) BIT 443 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXPSF_MHCHKEN BIT(5) BIT 444 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXPSF_CONT_ERRCHKEN BIT(4) BIT 445 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_RXPSF_ALL_ERRCHKEN BIT(3) BIT 460 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_DUMMY_FCS_READY_MASK_EN BIT(9) BIT 465 drivers/net/wireless/realtek/rtw88/reg.h #define LTECOEX_READY BIT(29) BIT 476 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_ANAPAR_BTPS BIT(22) BIT 301 drivers/net/wireless/realtek/rtw88/regd.c if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_80)) BIT 65 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); BIT 66 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); BIT 67 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); BIT 71 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); BIT 75 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); BIT 219 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); BIT 223 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); BIT 226 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); BIT 256 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); BIT 424 drivers/net/wireless/realtek/rtw88/rtw8822b.c #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) BIT 426 drivers/net/wireless/realtek/rtw88/rtw8822b.c #define RF18_BAND_5G (BIT(16) | BIT(8)) BIT 428 drivers/net/wireless/realtek/rtw88/rtw8822b.c #define RF18_RFSI_MASK (BIT(18) | BIT(17)) BIT 429 drivers/net/wireless/realtek/rtw88/rtw8822b.c #define RF18_RFSI_GE_CH80 (BIT(17)) BIT 430 drivers/net/wireless/realtek/rtw88/rtw8822b.c #define RF18_RFSI_GT_CH144 (BIT(18)) BIT 431 drivers/net/wireless/realtek/rtw88/rtw8822b.c #define RF18_BW_MASK (BIT(11) | BIT(10)) BIT 432 drivers/net/wireless/realtek/rtw88/rtw8822b.c #define RF18_BW_20M (BIT(11) | BIT(10)) BIT 433 drivers/net/wireless/realtek/rtw88/rtw8822b.c #define RF18_BW_40M (BIT(11)) BIT 434 drivers/net/wireless/realtek/rtw88/rtw8822b.c #define RF18_BW_80M (BIT(10)) BIT 435 drivers/net/wireless/realtek/rtw88/rtw8822b.c #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15)) BIT 482 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); BIT 484 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); BIT 490 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); BIT 491 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); BIT 519 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); BIT 520 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); BIT 521 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); BIT 524 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); BIT 525 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); BIT 526 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); BIT 529 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); BIT 530 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); BIT 531 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); BIT 543 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); BIT 544 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); BIT 545 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); BIT 560 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); BIT 561 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); BIT 562 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); BIT 592 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); BIT 596 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); BIT 598 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); BIT 605 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); BIT 613 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); BIT 617 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); BIT 623 drivers/net/wireless/realtek/rtw88/rtw8822b.c val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20)); BIT 626 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); BIT 627 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); BIT 632 drivers/net/wireless/realtek/rtw88/rtw8822b.c val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20)); BIT 635 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); BIT 636 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); BIT 687 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); BIT 688 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); BIT 689 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); BIT 714 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); BIT 715 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); BIT 726 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); BIT 727 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); BIT 728 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); BIT 730 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); BIT 731 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); BIT 732 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); BIT 938 drivers/net/wireless/realtek/rtw88/rtw8822b.c ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); BIT 950 drivers/net/wireless/realtek/rtw88/rtw8822b.c cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); BIT 972 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_set(rtwdev, 0x9a4, BIT(17)); BIT 973 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); BIT 974 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); BIT 975 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_set(rtwdev, 0xa2c, BIT(15)); BIT 976 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_set(rtwdev, 0xb58, BIT(0)); BIT 977 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write32_clr(rtwdev, 0xb58, BIT(0)); BIT 998 drivers/net/wireless/realtek/rtw88/rtw8822b.c reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); BIT 1263 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 1268 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, BIT 1273 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 1278 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, BIT 1301 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(1), 0}, BIT 1306 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 1311 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 1321 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(5), 0}, BIT 1326 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, BIT 1331 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 1336 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, BIT 1341 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 1351 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 1356 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(7), 0}, BIT 1361 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, BIT 1366 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 1371 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 1376 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_POLLING, BIT(0), 0}, BIT 1381 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, BIT 1401 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, BIT 1411 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(2), 0}, BIT 1416 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, BIT 1421 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, BIT 1434 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(2), 0}, BIT 1439 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(3), 0}, BIT 1459 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(1), 0}, BIT 1464 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 1469 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(1), 0}, BIT 1474 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 1479 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, BIT 1484 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_POLLING, BIT(1), 0}, BIT 1489 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(3), 0}, BIT 1494 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, BIT 1507 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, BIT 1517 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(5), 0}, BIT 1522 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, BIT 1527 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 1532 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(5), 0}, BIT 1537 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(4), 0}, BIT 1542 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 1547 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(1), 0}, BIT 1552 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, BIT 1557 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(2), 0}, BIT 1562 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, BIT 1567 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, BIT 1572 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, BIT 1577 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, BIT 1582 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 1587 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_POLLING, BIT(1), 0}, BIT 1592 drivers/net/wireless/realtek/rtw88/rtw8822b.c RTW_PWR_CMD_WRITE, BIT(1), 0}, BIT 10 drivers/net/wireless/realtek/rtw88/rtw8822b.h #define RCR_VHT_ACK BIT(26) BIT 133 drivers/net/wireless/realtek/rtw88/rtw8822b.h #define BIT_RX_PSEL_RST (BIT(28) | BIT(29)) BIT 363 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); BIT 392 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); BIT 442 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); BIT 623 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); BIT 699 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_clr(rtwdev, 0x1830, BIT(30)); BIT 704 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_clr(rtwdev, 0x4130, BIT(30)); BIT 709 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_set(rtwdev, 0x1830, BIT(30)); BIT 710 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_set(rtwdev, 0x4130, BIT(30)); BIT 722 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); BIT 728 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); BIT 734 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); BIT 740 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); BIT 751 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); BIT 752 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); BIT 753 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); BIT 754 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); BIT 756 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); BIT 758 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); BIT 759 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); BIT 761 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); BIT 763 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); BIT 764 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); BIT 767 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); BIT 769 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); BIT 771 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); BIT 772 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); BIT 773 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); BIT 774 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); BIT 783 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); BIT 784 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); BIT 787 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); BIT 789 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); BIT 791 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); BIT 792 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); BIT 793 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); BIT 794 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); BIT 796 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); BIT 797 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); BIT 806 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); BIT 807 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); BIT 835 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); BIT 839 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); BIT 842 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); BIT 848 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); BIT 852 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); BIT 854 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); BIT 856 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); BIT 857 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); BIT 858 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); BIT 859 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); BIT 903 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); BIT 904 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); BIT 907 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); BIT 908 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); BIT 909 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); BIT 910 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); BIT 967 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); BIT 988 drivers/net/wireless/realtek/rtw88/rtw8822c.c x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); BIT 1149 drivers/net/wireless/realtek/rtw88/rtw8822c.c value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); BIT 1267 drivers/net/wireless/realtek/rtw88/rtw8822c.c #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) BIT 1269 drivers/net/wireless/realtek/rtw88/rtw8822c.c #define RF18_BAND_5G (BIT(16) | BIT(8)) BIT 1271 drivers/net/wireless/realtek/rtw88/rtw8822c.c #define RF18_RFSI_MASK (BIT(18) | BIT(17)) BIT 1272 drivers/net/wireless/realtek/rtw88/rtw8822c.c #define RF18_RFSI_GE_CH80 (BIT(17)) BIT 1273 drivers/net/wireless/realtek/rtw88/rtw8822c.c #define RF18_RFSI_GT_CH140 (BIT(18)) BIT 1274 drivers/net/wireless/realtek/rtw88/rtw8822c.c #define RF18_BW_MASK (BIT(13) | BIT(12)) BIT 1275 drivers/net/wireless/realtek/rtw88/rtw8822c.c #define RF18_BW_20M (BIT(13) | BIT(12)) BIT 1276 drivers/net/wireless/realtek/rtw88/rtw8822c.c #define RF18_BW_40M (BIT(13)) BIT 1277 drivers/net/wireless/realtek/rtw88/rtw8822c.c #define RF18_BW_80M (BIT(12)) BIT 1344 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); BIT 1410 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); BIT 1457 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), BIT 1530 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); BIT 1531 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); BIT 1532 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); BIT 1536 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); BIT 1537 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); BIT 1538 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); BIT 1744 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); BIT 1749 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); BIT 1772 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); BIT 1950 drivers/net/wireless/realtek/rtw88/rtw8822c.c rf_0x1 |= BIT(13); BIT 1965 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1); BIT 1966 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0); BIT 1967 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1); BIT 1968 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1); BIT 1976 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); BIT 1977 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1); BIT 1979 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1); BIT 1983 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); BIT 1985 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0); BIT 1991 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x66, BIT(4), 0); BIT 1992 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x67, BIT(0), 0); BIT 1993 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x42, BIT(3), 0); BIT 1994 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x65, BIT(7), 0); BIT 1995 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write8_mask(rtwdev, 0x73, BIT(3), 0); BIT 2081 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); BIT 2148 drivers/net/wireless/realtek/rtw88/rtw8822c.c band_shift = FIELD_GET(BIT(16), reg); BIT 2172 drivers/net/wireless/realtek/rtw88/rtw8822c.c if (dc_i & BIT(11)) BIT 2174 drivers/net/wireless/realtek/rtw88/rtw8822c.c if (dc_q & BIT(11)) BIT 2268 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); BIT 2308 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); BIT 2309 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); BIT 2312 drivers/net/wireless/realtek/rtw88/rtw8822c.c if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { BIT 2355 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); BIT 2356 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); BIT 2357 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); BIT 2368 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); BIT 2376 drivers/net/wireless/realtek/rtw88/rtw8822c.c if (i_val & BIT(15)) BIT 2378 drivers/net/wireless/realtek/rtw88/rtw8822c.c if (q_val & BIT(15)) BIT 2417 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); BIT 2422 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); BIT 2652 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); BIT 2655 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); BIT 2767 drivers/net/wireless/realtek/rtw88/rtw8822c.c result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26)); BIT 2806 drivers/net/wireless/realtek/rtw88/rtw8822c.c 0x05020000 | (BIT(path) << 28)); BIT 2814 drivers/net/wireless/realtek/rtw88/rtw8822c.c 0x05020008 | (BIT(path) << 28)); BIT 2875 drivers/net/wireless/realtek/rtw88/rtw8822c.c BIT(14), 0x0); BIT 2964 drivers/net/wireless/realtek/rtw88/rtw8822c.c u32 mask = BIT(15) | BIT(14); BIT 3199 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 3204 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, BIT 3209 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, BIT 3214 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 3219 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(7), 0}, BIT 3224 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 3229 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, BIT 3242 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(5), 0}, BIT 3247 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, BIT 3252 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 3257 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, BIT 3262 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 3272 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(3), 0}, BIT 3277 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 3282 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(7), 0}, BIT 3287 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, BIT 3292 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 3297 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_POLLING, BIT(0), 0}, BIT 3302 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, BIT 3307 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(4), 0}, BIT 3312 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), BIT 3313 drivers/net/wireless/realtek/rtw88/rtw8822c.c (BIT(7) | BIT(6) | BIT(5))}, BIT 3318 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, BIT 3323 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, BIT 3328 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, BIT 3333 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, BIT 3338 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, BIT 3351 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(3), 0}, BIT 3366 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(4), 0}, BIT 3376 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(1), 0}, BIT 3381 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 3386 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(1), 0}, BIT 3391 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, BIT 3396 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_POLLING, BIT(1), 0}, BIT 3401 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, BIT 3414 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, BIT 3424 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(5), 0}, BIT 3429 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(0), 0}, BIT 3434 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, BIT 3439 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(1), 0}, BIT 3454 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, BIT 3459 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, BIT 3464 drivers/net/wireless/realtek/rtw88/rtw8822c.c RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, BIT 154 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_LDOE25_PON BIT(0) BIT 156 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BITS_RRSR_RSC (BIT(21) | BIT(22)) BIT 175 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_PT_OPT BIT(21) BIT 178 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_3WIRE_TX_EN BIT(0) BIT 179 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_3WIRE_RX_EN BIT(1) BIT 180 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_3WIRE_PI_ON BIT(28) BIT 191 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BITS_RX_IQ_WEIGHT (BIT(8) | BIT(9)) BIT 196 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_CCK_FA_RST (BIT(14) | BIT(15)) BIT 197 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_OFDM_FA_RST (BIT(12) | BIT(13)) BIT 200 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_BB_CCK_CHECK_EN BIT(18) BIT 207 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_NBI_EN BIT(30) BIT 211 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_CCK_BLK_EN BIT(1) BIT 212 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1)) BIT 215 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_COM_RX_GCK_EN BIT(31) BIT 223 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_ALL_CNT_RST BIT(25) BIT 269 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_EXT_TIA_BW BIT(1) BIT 270 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_DE_TRXBW BIT(2) BIT 271 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_DE_TX_GAIN BIT(16) BIT 272 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_RXG_GAIN BIT(18) BIT 273 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_DE_PWR_TRIM BIT(19) BIT 274 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_INNER_LB BIT(21) BIT 275 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_BYPASS_DPD BIT(25) BIT 276 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_DPD_EN BIT(31) BIT 13478 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x18a4, BIT(7), 0, BIT 13479 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x41a4, BIT(7), 0, BIT 13555 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x18a4, BIT(7), 1, BIT 13556 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x41a4, BIT(7), 1, BIT 13562 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x1e24, BIT(17), 0x1, BIT 13564 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x1864, BIT(31), 0x1, BIT 13565 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x4164, BIT(31), 0x1, BIT 13566 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x180c, BIT(27), 0x1, BIT 13567 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x410c, BIT(27), 0x1, BIT 13568 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x186c, BIT(7), 0x1, BIT 13569 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 0x416c, BIT(7), 0x1, BIT 151 drivers/net/wireless/realtek/rtw88/rx.c rx_status->chains |= BIT(path); BIT 9 drivers/net/wireless/realtek/rtw88/rx.h le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(26)) BIT 11 drivers/net/wireless/realtek/rtw88/rx.h le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(15)) BIT 13 drivers/net/wireless/realtek/rtw88/rx.h le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(14)) BIT 15 drivers/net/wireless/realtek/rtw88/rx.h le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(27)) BIT 17 drivers/net/wireless/realtek/rtw88/rx.h le32_get_bits(*((__le32 *)(rxdesc) + 0x02), BIT(28)) BIT 15 drivers/net/wireless/realtek/rtw88/sec.h #define RTW_SEC_CMD_WRITE_ENABLE BIT(16) BIT 16 drivers/net/wireless/realtek/rtw88/sec.h #define RTW_SEC_CMD_CLEAR BIT(30) BIT 17 drivers/net/wireless/realtek/rtw88/sec.h #define RTW_SEC_CMD_POLLING BIT(31) BIT 19 drivers/net/wireless/realtek/rtw88/sec.h #define RTW_SEC_TX_UNI_USE_DK BIT(0) BIT 20 drivers/net/wireless/realtek/rtw88/sec.h #define RTW_SEC_RX_UNI_USE_DK BIT(1) BIT 21 drivers/net/wireless/realtek/rtw88/sec.h #define RTW_SEC_TX_DEC_EN BIT(2) BIT 22 drivers/net/wireless/realtek/rtw88/sec.h #define RTW_SEC_RX_DEC_EN BIT(3) BIT 23 drivers/net/wireless/realtek/rtw88/sec.h #define RTW_SEC_TX_BC_USE_DK BIT(6) BIT 24 drivers/net/wireless/realtek/rtw88/sec.h #define RTW_SEC_RX_BC_USE_DK BIT(7) BIT 26 drivers/net/wireless/realtek/rtw88/sec.h #define RTW_SEC_ENGINE_EN BIT(9) BIT 72 drivers/net/wireless/realtek/rtw88/tx.c return (BIT(2) << exp) - 1; BIT 21 drivers/net/wireless/realtek/rtw88/tx.h le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(24)) BIT 27 drivers/net/wireless/realtek/rtw88/tx.h le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(10)) BIT 29 drivers/net/wireless/realtek/rtw88/tx.h le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(8)) BIT 43 drivers/net/wireless/realtek/rtw88/tx.h le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(7)) BIT 45 drivers/net/wireless/realtek/rtw88/tx.h le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(12)) BIT 47 drivers/net/wireless/realtek/rtw88/tx.h le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(26)) BIT 49 drivers/net/wireless/realtek/rtw88/tx.h le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(4)) BIT 51 drivers/net/wireless/realtek/rtw88/tx.h le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(19)) BIT 3468 drivers/net/wireless/rndis_wlan.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) BIT 3469 drivers/net/wireless/rndis_wlan.c | BIT(NL80211_IFTYPE_ADHOC); BIT 146 drivers/net/wireless/rsi/rsi_91x_mac80211.c .types = BIT(NL80211_IFTYPE_STATION), BIT 150 drivers/net/wireless/rsi/rsi_91x_mac80211.c .types = BIT(NL80211_IFTYPE_AP) | BIT 151 drivers/net/wireless/rsi/rsi_91x_mac80211.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 152 drivers/net/wireless/rsi/rsi_91x_mac80211.c BIT(NL80211_IFTYPE_P2P_GO), BIT 156 drivers/net/wireless/rsi/rsi_91x_mac80211.c .types = BIT(NL80211_IFTYPE_P2P_DEVICE), BIT 1382 drivers/net/wireless/rsi/rsi_91x_mac80211.c if (rate_bitmap & BIT(ii)) { BIT 1394 drivers/net/wireless/rsi/rsi_91x_mac80211.c if ((rate_bitmap >> 12) & BIT(ii)) { BIT 2053 drivers/net/wireless/rsi/rsi_91x_mac80211.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 2054 drivers/net/wireless/rsi/rsi_91x_mac80211.c BIT(NL80211_IFTYPE_AP) | BIT 2055 drivers/net/wireless/rsi/rsi_91x_mac80211.c BIT(NL80211_IFTYPE_P2P_DEVICE) | BIT 2056 drivers/net/wireless/rsi/rsi_91x_mac80211.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 2057 drivers/net/wireless/rsi/rsi_91x_mac80211.c BIT(NL80211_IFTYPE_P2P_GO); BIT 1192 drivers/net/wireless/rsi/rsi_91x_mgmt.c cmd_frame->desc_word[3] = cpu_to_le16(BIT(0)); BIT 1373 drivers/net/wireless/rsi/rsi_91x_mgmt.c if (rate_bitmap & BIT(ii)) { BIT 1407 drivers/net/wireless/rsi/rsi_91x_mgmt.c cpu_to_le16(rsi_mcsrates[kk] | BIT(9)); BIT 361 drivers/net/wireless/rsi/rsi_91x_sdio_ops.c isr_status ^= BIT(isr_type - 1); BIT 395 drivers/net/wireless/rsi/rsi_91x_sdio_ops.c if (buf_status & (BIT(PKT_MGMT_BUFF_FULL))) { BIT 403 drivers/net/wireless/rsi/rsi_91x_sdio_ops.c if (buf_status & (BIT(PKT_BUFF_FULL))) { BIT 411 drivers/net/wireless/rsi/rsi_91x_sdio_ops.c if (buf_status & (BIT(PKT_BUFF_SEMI_FULL))) { BIT 20 drivers/net/wireless/rsi/rsi_boot_params.h #define CRYSTAL_GOOD_TIME BIT(0) BIT 21 drivers/net/wireless/rsi/rsi_boot_params.h #define BOOTUP_MODE_INFO BIT(1) BIT 22 drivers/net/wireless/rsi/rsi_boot_params.h #define WIFI_TAPLL_CONFIGS BIT(5) BIT 23 drivers/net/wireless/rsi/rsi_boot_params.h #define WIFI_PLL960_CONFIGS BIT(6) BIT 24 drivers/net/wireless/rsi/rsi_boot_params.h #define WIFI_AFEPLL_CONFIGS BIT(7) BIT 25 drivers/net/wireless/rsi/rsi_boot_params.h #define WIFI_SWITCH_CLK_CONFIGS BIT(8) BIT 105 drivers/net/wireless/rsi/rsi_boot_params.h #define RSI_SWITCH_TASS_CLK BIT(0) BIT 106 drivers/net/wireless/rsi/rsi_boot_params.h #define RSI_SWITCH_QSPI_CLK BIT(1) BIT 107 drivers/net/wireless/rsi/rsi_boot_params.h #define RSI_SWITCH_SLP_CLK_2_32 BIT(2) BIT 108 drivers/net/wireless/rsi/rsi_boot_params.h #define RSI_SWITCH_WLAN_BBP_LMAC_CLK_REG BIT(3) BIT 109 drivers/net/wireless/rsi/rsi_boot_params.h #define RSI_SWITCH_ZBBT_BBP_LMAC_CLK_REG BIT(4) BIT 110 drivers/net/wireless/rsi/rsi_boot_params.h #define RSI_SWITCH_BBP_LMAC_CLK_REG BIT(5) BIT 111 drivers/net/wireless/rsi/rsi_boot_params.h #define RSI_MODEM_CLK_160MHZ BIT(6) BIT 173 drivers/net/wireless/rsi/rsi_boot_params.h #define BT_COEXIST BIT(0) BIT 174 drivers/net/wireless/rsi/rsi_boot_params.h #define BOOTUP_MODE (BIT(2) | BIT(1)) BIT 92 drivers/net/wireless/rsi/rsi_hal.h #define RSI_RESTART_WDT BIT(11) BIT 93 drivers/net/wireless/rsi/rsi_hal.h #define RSI_BYPASS_ULP_ON_WDT BIT(1) BIT 107 drivers/net/wireless/rsi/rsi_hal.h #define RSI_GSPI_DMA_MODE BIT(13) BIT 109 drivers/net/wireless/rsi/rsi_hal.h #define RSI_GSPI_2_ULP BIT(12) BIT 110 drivers/net/wireless/rsi/rsi_hal.h #define RSI_GSPI_TRIG BIT(7) BIT 111 drivers/net/wireless/rsi/rsi_hal.h #define RSI_GSPI_READ BIT(6) BIT 112 drivers/net/wireless/rsi/rsi_hal.h #define RSI_GSPI_RF_SPI_ACTIVE BIT(8) BIT 140 drivers/net/wireless/rsi/rsi_hal.h #define RAM_384K_ACCESS_FROM_TA (BIT(2) | BIT(3) | BIT(4) | BIT(5) | \ BIT 141 drivers/net/wireless/rsi/rsi_hal.h BIT(20) | BIT(21) | BIT(22) | \ BIT 142 drivers/net/wireless/rsi/rsi_hal.h BIT(23) | BIT(24) | BIT(25)) BIT 158 drivers/net/wireless/rsi/rsi_hal.h #define RSI_BL_CTRL_SPI_32BIT_MODE BIT(27) BIT 159 drivers/net/wireless/rsi/rsi_hal.h #define RSI_BL_CTRL_REL_TA_SOFTRESET BIT(28) BIT 160 drivers/net/wireless/rsi/rsi_hal.h #define RSI_BL_CTRL_START_FROM_ROM_PC BIT(29) BIT 161 drivers/net/wireless/rsi/rsi_hal.h #define RSI_BL_CTRL_SPI_8BIT_MODE BIT(30) BIT 162 drivers/net/wireless/rsi/rsi_hal.h #define RSI_BL_CTRL_LAST_ENTRY BIT(31) BIT 36 drivers/net/wireless/rsi/rsi_main.h #define ERR_ZONE BIT(0) /* For Error Msgs */ BIT 37 drivers/net/wireless/rsi/rsi_main.h #define INFO_ZONE BIT(1) /* For General Status Msgs */ BIT 38 drivers/net/wireless/rsi/rsi_main.h #define INIT_ZONE BIT(2) /* For Driver Init Seq Msgs */ BIT 39 drivers/net/wireless/rsi/rsi_main.h #define MGMT_TX_ZONE BIT(3) /* For TX Mgmt Path Msgs */ BIT 40 drivers/net/wireless/rsi/rsi_main.h #define MGMT_RX_ZONE BIT(4) /* For RX Mgmt Path Msgs */ BIT 41 drivers/net/wireless/rsi/rsi_main.h #define DATA_TX_ZONE BIT(5) /* For TX Data Path Msgs */ BIT 42 drivers/net/wireless/rsi/rsi_main.h #define DATA_RX_ZONE BIT(6) /* For RX Data Path Msgs */ BIT 43 drivers/net/wireless/rsi/rsi_main.h #define FSM_ZONE BIT(7) /* For State Machine Msgs */ BIT 44 drivers/net/wireless/rsi/rsi_main.h #define ISR_ZONE BIT(8) /* For Interrupt Msgs */ BIT 111 drivers/net/wireless/rsi/rsi_main.h #define RSI_WOW_ENABLED BIT(0) BIT 112 drivers/net/wireless/rsi/rsi_main.h #define RSI_WOW_NO_CONNECTION BIT(1) BIT 29 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_11G_MODE BIT(7) BIT 50 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_UNICAST_MAGIC_PKT BIT(0) BIT 51 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_BROADCAST_MAGICPKT BIT(1) BIT 52 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_EAPOL_PKT BIT(2) BIT 53 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DISCONNECT_PKT BIT(3) BIT 54 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_HW_BMISS_PKT BIT(4) BIT 55 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_INSERT_SEQ_IN_FW BIT(2) BIT 81 drivers/net/wireless/rsi/rsi_mgmt.h #define RF_RESET_ENABLE BIT(3) BIT 82 drivers/net/wireless/rsi/rsi_mgmt.h #define RATE_INFO_ENABLE BIT(0) BIT 83 drivers/net/wireless/rsi/rsi_mgmt.h #define MORE_DATA_PRESENT BIT(1) BIT 84 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_BROADCAST_PKT BIT(9) BIT 85 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DESC_REQUIRE_CFM_TO_HOST BIT(2) BIT 86 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_ADD_DELTA_TSF_VAP_ID BIT(3) BIT 87 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_FETCH_RETRY_CNT_FRM_HST BIT(4) BIT 88 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_QOS_ENABLE BIT(12) BIT 89 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_REKEY_PURPOSE BIT(13) BIT 90 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_ENCRYPT_PKT BIT(15) BIT 91 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_SET_PS_ENABLE BIT(12) BIT 93 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_CMDDESC_40MHZ BIT(4) BIT 94 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_CMDDESC_UPPER_20_ENABLE BIT(5) BIT 95 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_CMDDESC_LOWER_20_ENABLE BIT(6) BIT 96 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_CMDDESC_FULL_40_ENABLE (BIT(5) | BIT(6)) BIT 103 drivers/net/wireless/rsi/rsi_mgmt.h #define ENABLE_SHORTGI_RATE BIT(9) BIT 182 drivers/net/wireless/rsi/rsi_mgmt.h #define PROMISCOUS_MODE BIT(0) BIT 183 drivers/net/wireless/rsi/rsi_mgmt.h #define ALLOW_DATA_ASSOC_PEER BIT(1) BIT 184 drivers/net/wireless/rsi/rsi_mgmt.h #define ALLOW_MGMT_ASSOC_PEER BIT(2) BIT 185 drivers/net/wireless/rsi/rsi_mgmt.h #define ALLOW_CTRL_ASSOC_PEER BIT(3) BIT 186 drivers/net/wireless/rsi/rsi_mgmt.h #define DISALLOW_BEACONS BIT(4) BIT 187 drivers/net/wireless/rsi/rsi_mgmt.h #define ALLOW_CONN_PEER_MGMT_WHILE_BUF_FULL BIT(5) BIT 188 drivers/net/wireless/rsi/rsi_mgmt.h #define DISALLOW_BROADCAST_DATA BIT(6) BIT 191 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_CHAN_RADAR BIT(7) BIT 195 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_PS_DISABLE_IND BIT(15) BIT 211 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DATA_DESC_MAC_BBP_INFO BIT(0) BIT 212 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DATA_DESC_NO_ACK_IND BIT(9) BIT 213 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DATA_DESC_QOS_EN BIT(12) BIT 215 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DATA_DESC_DTIM_BEACON_GATED_FRAME BIT(10) BIT 216 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DATA_DESC_BEACON_FRAME BIT(11) BIT 217 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DATA_DESC_DTIM_BEACON (BIT(10) | BIT(11)) BIT 218 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DATA_DESC_INSERT_TSF BIT(15) BIT 219 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DATA_DESC_INSERT_SEQ_NO BIT(2) BIT 222 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_WOW_ANY BIT(1) BIT 223 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_WOW_GTK_REKEY BIT(3) BIT 224 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_WOW_MAGIC_PKT BIT(4) BIT 225 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_WOW_DISCONNECT BIT(5) BIT 305 drivers/net/wireless/rsi/rsi_mgmt.h #define PWR_SAVE_WAKEUP_IND BIT(0) BIT 306 drivers/net/wireless/rsi/rsi_mgmt.h #define TCP_CHECK_SUM_OFFLOAD BIT(1) BIT 307 drivers/net/wireless/rsi/rsi_mgmt.h #define CONFIRM_REQUIRED_TO_HOST BIT(2) BIT 308 drivers/net/wireless/rsi/rsi_mgmt.h #define ADD_DELTA_TSF BIT(3) BIT 309 drivers/net/wireless/rsi/rsi_mgmt.h #define FETCH_RETRY_CNT_FROM_HOST_DESC BIT(4) BIT 310 drivers/net/wireless/rsi/rsi_mgmt.h #define EOSP_INDICATION BIT(5) BIT 311 drivers/net/wireless/rsi/rsi_mgmt.h #define REQUIRE_TSF_SYNC_CONFIRM BIT(6) BIT 312 drivers/net/wireless/rsi/rsi_mgmt.h #define ENCAP_MGMT_PKT BIT(7) BIT 313 drivers/net/wireless/rsi/rsi_mgmt.h #define DESC_IMMEDIATE_WAKEUP BIT(15) BIT 375 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_AGGR_PARAMS_START BIT(4) BIT 376 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_AGGR_PARAMS_RX_AGGR BIT(5) BIT 460 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_KEY_TYPE_BROADCAST BIT(1) BIT 461 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_WEP_KEY BIT(2) BIT 462 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_WEP_KEY_104 BIT(3) BIT 463 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_CIPHER_WPA BIT(4) BIT 464 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_CIPHER_TKIP BIT(5) BIT 465 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_KEY_MODE_AP BIT(7) BIT 466 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_PROTECT_DATA_FRAMES BIT(13) BIT 493 drivers/net/wireless/rsi/rsi_mgmt.h #define QUIET_INFO_VALID BIT(0) BIT 494 drivers/net/wireless/rsi/rsi_mgmt.h #define QUIET_ENABLE BIT(1) BIT 535 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_MOTION_SENSOR_ULP_WAKEUP BIT(0) BIT 536 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_SLEEP_IND_FROM_DEVICE BIT(1) BIT 537 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_2_ULP BIT(2) BIT 538 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_PUSH_BUTTON_ULP_WAKEUP BIT(3) BIT 541 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_0_PSPI_CSN_0 BIT(0) BIT 542 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_1_PSPI_CSN_1 BIT(1) BIT 543 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_2_HOST_WAKEUP_INTR BIT(2) BIT 544 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_3_PSPI_DATA_0 BIT(3) BIT 545 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_4_PSPI_DATA_1 BIT(4) BIT 546 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_5_PSPI_DATA_2 BIT(5) BIT 547 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_6_PSPI_DATA_3 BIT(6) BIT 548 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_7_I2C_SCL BIT(7) BIT 549 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_8_I2C_SDA BIT(8) BIT 550 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_9_UART1_RX BIT(9) BIT 551 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_10_UART1_TX BIT(10) BIT 552 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_11_UART1_RTS_I2S_CLK BIT(11) BIT 553 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_12_UART1_CTS_I2S_WS BIT(12) BIT 554 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_13_DBG_UART_RX_I2S_DIN BIT(13) BIT 555 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_14_DBG_UART_RX_I2S_DOUT BIT(14) BIT 556 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_15_LP_WAKEUP_BOOT_BYPASS BIT(15) BIT 557 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_16_LED_0 BIT(16) BIT 558 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_17_BTCOEX_WLAN_ACT_EXT_ANT_SEL BIT(17) BIT 559 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_18_BTCOEX_BT_PRIO_EXT_ANT_SEL BIT(18) BIT 560 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_19_BTCOEX_BT_ACT_EXT_ON_OFF BIT(19) BIT 561 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_20_RF_RESET BIT(20) BIT 562 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_GPIO_21_SLEEP_IND_FROM_DEVICE BIT(21) BIT 641 drivers/net/wireless/rsi/rsi_mgmt.h #define HOST_BG_SCAN_TRIG BIT(4) BIT 667 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DUTY_CYCLING BIT(0) BIT 668 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_END_OF_FRAME BIT(1) BIT 669 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_SIFS_TX_ENABLE BIT(2) BIT 670 drivers/net/wireless/rsi/rsi_mgmt.h #define RSI_DPD BIT(3) BIT 92 drivers/net/wireless/rsi/rsi_sdio.h #define TA_SOFT_RST_SET BIT(0) BIT 128 drivers/net/wireless/st/cw1200/cw1200_sdio.c cccr |= BIT(0); BIT 131 drivers/net/wireless/st/cw1200/cw1200_sdio.c cccr |= BIT(self->func->num); BIT 94 drivers/net/wireless/st/cw1200/debug.c seq_printf(seq, "%s ", (map & BIT(i)) ? "**" : ".."); BIT 122 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONT_WUP_BIT (BIT(12)) BIT 123 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONT_RDY_BIT (BIT(13)) BIT 124 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONT_IRQ_ENABLE (BIT(14)) BIT 125 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONT_RDY_ENABLE (BIT(15)) BIT 126 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONT_IRQ_RDY_ENABLE (BIT(14)|BIT(15)) BIT 129 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_FRAME_BIT (BIT(2)) BIT 130 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_WORD_MODE_BITS (BIT(3)|BIT(4)) BIT 131 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_WORD_MODE_1 (BIT(3)) BIT 132 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_WORD_MODE_2 (BIT(4)) BIT 133 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_ERROR_0_BIT (BIT(5)) BIT 134 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_ERROR_1_BIT (BIT(6)) BIT 135 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_ERROR_2_BIT (BIT(7)) BIT 137 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_CSN_FRAME_BIT (BIT(7)) BIT 138 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_ERROR_3_BIT (BIT(8)) BIT 139 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_ERROR_4_BIT (BIT(9)) BIT 141 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_ACCESS_MODE_BIT (BIT(10)) BIT 143 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_AHB_PRFETCH_BIT (BIT(11)) BIT 144 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_CPU_CLK_DIS_BIT (BIT(12)) BIT 146 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_PRFETCH_BIT (BIT(13)) BIT 148 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_CPU_RESET_BIT (BIT(14)) BIT 149 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONFIG_CLEAR_INT_BIT (BIT(15)) BIT 152 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONF_IRQ_ENABLE (BIT(16)) BIT 153 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONF_RDY_ENABLE (BIT(17)) BIT 154 drivers/net/wireless/st/cw1200/hwio.h #define ST90TDS_CONF_IRQ_RDY_ENABLE (BIT(16)|BIT(17)) BIT 287 drivers/net/wireless/st/cw1200/main.c hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 288 drivers/net/wireless/st/cw1200/main.c BIT(NL80211_IFTYPE_ADHOC) | BIT 289 drivers/net/wireless/st/cw1200/main.c BIT(NL80211_IFTYPE_AP) | BIT 290 drivers/net/wireless/st/cw1200/main.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 291 drivers/net/wireless/st/cw1200/main.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 292 drivers/net/wireless/st/cw1200/main.c BIT(NL80211_IFTYPE_P2P_GO); BIT 342 drivers/net/wireless/st/cw1200/queue.c if (link_id_map & BIT(item->txpriv.link_id)) { BIT 566 drivers/net/wireless/st/cw1200/queue.c if (link_id_map & BIT(i)) { BIT 269 drivers/net/wireless/st/cw1200/sta.c if (priv->link_id_map & BIT(i)) { BIT 272 drivers/net/wireless/st/cw1200/sta.c priv->link_id_map &= ~BIT(i); BIT 1562 drivers/net/wireless/st/cw1200/sta.c priv->sta_asleep_mask |= BIT(sta_priv->link_id); BIT 1603 drivers/net/wireless/st/cw1200/sta.c bit = BIT(link_id); BIT 418 drivers/net/wireless/st/cw1200/txrx.c if (rates & BIT(i)) BIT 419 drivers/net/wireless/st/cw1200/txrx.c ret |= BIT(priv->rates[i].hw_value); BIT 469 drivers/net/wireless/st/cw1200/txrx.c if (t->sta && (t->sta->uapsd_queues & BIT(t->queue))) BIT 479 drivers/net/wireless/st/cw1200/txrx.c u32 mask = ~BIT(t->txpriv.raw_link_id); BIT 825 drivers/net/wireless/st/cw1200/txrx.c pspoll_mask = BIT(sta_priv->link_id); BIT 1237 drivers/net/wireless/st/cw1200/txrx.c priv->key_map |= BIT(idx); BIT 1244 drivers/net/wireless/st/cw1200/txrx.c BUG_ON(!(priv->key_map & BIT(idx))); BIT 1246 drivers/net/wireless/st/cw1200/txrx.c priv->key_map &= ~BIT(idx); BIT 1259 drivers/net/wireless/st/cw1200/txrx.c if (priv->key_map & BIT(idx)) { BIT 1397 drivers/net/wireless/st/cw1200/txrx.c mask = BIT(i + 1); BIT 1482 drivers/net/wireless/st/cw1200/wsm.c } else if (!(BIT(txpriv->raw_link_id) & BIT 1483 drivers/net/wireless/st/cw1200/wsm.c (BIT(0) | priv->link_id_map))) { BIT 1581 drivers/net/wireless/st/cw1200/wsm.c static const int urgent = BIT(CW1200_LINK_ID_AFTER_DTIM) | BIT 1582 drivers/net/wireless/st/cw1200/wsm.c BIT(CW1200_LINK_ID_UAPSD); BIT 1631 drivers/net/wireless/st/cw1200/wsm.c tx_allowed_mask = BIT(CW1200_LINK_ID_AFTER_DTIM); BIT 1642 drivers/net/wireless/st/cw1200/wsm.c tx_allowed_mask |= BIT(CW1200_LINK_ID_UAPSD); BIT 1645 drivers/net/wireless/st/cw1200/wsm.c tx_allowed_mask &= ~BIT(CW1200_LINK_ID_AFTER_DTIM); BIT 1647 drivers/net/wireless/st/cw1200/wsm.c tx_allowed_mask |= BIT(CW1200_LINK_ID_AFTER_DTIM); BIT 1724 drivers/net/wireless/st/cw1200/wsm.c priv->pspoll_mask &= ~BIT(txpriv->raw_link_id); BIT 109 drivers/net/wireless/st/cw1200/wsm.h #define WSM_SCAN_FLAG_FORCE_BACKGROUND (BIT(0)) BIT 113 drivers/net/wireless/st/cw1200/wsm.h #define WSM_SCAN_FLAG_SPLIT_METHOD (BIT(1)) BIT 116 drivers/net/wireless/st/cw1200/wsm.h #define WSM_SCAN_FLAG_SHORT_PREAMBLE (BIT(2)) BIT 119 drivers/net/wireless/st/cw1200/wsm.h #define WSM_SCAN_FLAG_11N_GREENFIELD (BIT(3)) BIT 133 drivers/net/wireless/st/cw1200/wsm.h #define WSM_PSM_PS BIT(0) BIT 136 drivers/net/wireless/st/cw1200/wsm.h #define WSM_PSM_FAST_PS_FLAG BIT(7) BIT 139 drivers/net/wireless/st/cw1200/wsm.h #define WSM_PSM_FAST_PS (BIT(0) | BIT(7)) BIT 145 drivers/net/wireless/st/cw1200/wsm.h #define WSM_PSM_UNKNOWN BIT(1) BIT 171 drivers/net/wireless/st/cw1200/wsm.h #define WSM_HT_TX_STBC (BIT(7)) BIT 192 drivers/net/wireless/st/cw1200/wsm.h #define WSM_TX_STATUS_AGGREGATION (BIT(0)) BIT 196 drivers/net/wireless/st/cw1200/wsm.h #define WSM_TX_STATUS_REQUEUE (BIT(1)) BIT 231 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_AGGREGATE (BIT(3)) BIT 234 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_AGGREGATE_FIRST (BIT(4)) BIT 237 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_AGGREGATE_LAST (BIT(5)) BIT 240 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_DEFRAGMENTED (BIT(6)) BIT 243 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_BEACON (BIT(7)) BIT 246 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_TIM (BIT(8)) BIT 249 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_MULTICAST (BIT(9)) BIT 252 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_MATCHING_SSID (BIT(10)) BIT 255 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_MATCHING_BSSI (BIT(11)) BIT 258 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_MORE_DATA (BIT(12)) BIT 261 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_MEASUREMENT (BIT(13)) BIT 264 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_HT (BIT(14)) BIT 267 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_STBC (BIT(15)) BIT 270 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_ADDRESS1 (BIT(16)) BIT 273 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_GROUP (BIT(17)) BIT 276 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_BROADCAST (BIT(18)) BIT 279 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_GROUP_KEY (BIT(19)) BIT 285 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RX_STATUS_TSF_INCLUDED (BIT(24)) BIT 288 drivers/net/wireless/st/cw1200/wsm.h #define WSM_TX_2BYTES_SHIFT (BIT(7)) BIT 309 drivers/net/wireless/st/cw1200/wsm.h #define WSM_JOIN_FLAGS_UNSYNCRONIZED BIT(0) BIT 311 drivers/net/wireless/st/cw1200/wsm.h #define WSM_JOIN_FLAGS_P2P_GO BIT(1) BIT 316 drivers/net/wireless/st/cw1200/wsm.h #define WSM_JOIN_FLAGS_FORCE BIT(2) BIT 320 drivers/net/wireless/st/cw1200/wsm.h #define WSM_JOIN_FLAGS_PRIO BIT(3) BIT 324 drivers/net/wireless/st/cw1200/wsm.h #define WSM_JOIN_FLAGS_FORCE_WITH_COMPLETE_IND BIT(5) BIT 349 drivers/net/wireless/st/cw1200/wsm.h #define WSM_ASSOCIATION_MODE_USE_PREAMBLE_TYPE (BIT(0)) BIT 350 drivers/net/wireless/st/cw1200/wsm.h #define WSM_ASSOCIATION_MODE_USE_HT_MODE (BIT(1)) BIT 351 drivers/net/wireless/st/cw1200/wsm.h #define WSM_ASSOCIATION_MODE_USE_BASIC_RATE_SET (BIT(2)) BIT 352 drivers/net/wireless/st/cw1200/wsm.h #define WSM_ASSOCIATION_MODE_USE_MPDU_START_SPACING (BIT(3)) BIT 353 drivers/net/wireless/st/cw1200/wsm.h #define WSM_ASSOCIATION_MODE_SNOOP_ASSOC_FRAMES (BIT(4)) BIT 356 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RCPI_RSSI_THRESHOLD_ENABLE (BIT(0)) BIT 357 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RCPI_RSSI_USE_RSSI (BIT(1)) BIT 358 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RCPI_RSSI_DONT_USE_UPPER (BIT(2)) BIT 359 drivers/net/wireless/st/cw1200/wsm.h #define WSM_RCPI_RSSI_DONT_USE_LOWER (BIT(3)) BIT 362 drivers/net/wireless/st/cw1200/wsm.h #define WSM_UPDATE_IE_BEACON (BIT(0)) BIT 363 drivers/net/wireless/st/cw1200/wsm.h #define WSM_UPDATE_IE_PROBE_RESP (BIT(1)) BIT 364 drivers/net/wireless/st/cw1200/wsm.h #define WSM_UPDATE_IE_PROBE_REQ (BIT(2)) BIT 1376 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(0)); BIT 1378 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(1)); BIT 1380 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(2)); BIT 1382 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(3)); BIT 1388 drivers/net/wireless/st/cw1200/wsm.h #define WSM_BEACON_FILTER_IE_HAS_CHANGED BIT(0) BIT 1389 drivers/net/wireless/st/cw1200/wsm.h #define WSM_BEACON_FILTER_IE_NO_LONGER_PRESENT BIT(1) BIT 1390 drivers/net/wireless/st/cw1200/wsm.h #define WSM_BEACON_FILTER_IE_HAS_APPEARED BIT(2) BIT 1414 drivers/net/wireless/st/cw1200/wsm.h #define WSM_BEACON_FILTER_ENABLE BIT(0) /* Enable/disable beacon filtering */ BIT 1415 drivers/net/wireless/st/cw1200/wsm.h #define WSM_BEACON_FILTER_AUTO_ERP BIT(1) /* If 1 FW will handle ERP IE changes internally */ BIT 1452 drivers/net/wireless/st/cw1200/wsm.h val |= BIT(4); BIT 1454 drivers/net/wireless/st/cw1200/wsm.h val |= BIT(5); BIT 1491 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(0)); BIT 1493 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(1)); BIT 1495 drivers/net/wireless/st/cw1200/wsm.h val |= __cpu_to_le32(BIT(2)); BIT 1535 drivers/net/wireless/st/cw1200/wsm.h #define WSM_TX_RATE_POLICY_FLAG_TERMINATE_WHEN_FINISHED BIT(2) BIT 1536 drivers/net/wireless/st/cw1200/wsm.h #define WSM_TX_RATE_POLICY_FLAG_COUNT_INITIAL_TRANSMIT BIT(3) BIT 480 drivers/net/wireless/ti/wl1251/acx.h #define BEACON_RULE_PASS_ON_CHANGE BIT(0) BIT 481 drivers/net/wireless/ti/wl1251/acx.h #define BEACON_RULE_PASS_ON_APPEARANCE BIT(1) BIT 718 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_FCS BIT(2) BIT 719 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_ALL_GOOD BIT(3) BIT 720 drivers/net/wireless/ti/wl1251/acx.h #define CFG_UNI_FILTER_EN BIT(4) BIT 721 drivers/net/wireless/ti/wl1251/acx.h #define CFG_BSSID_FILTER_EN BIT(5) BIT 722 drivers/net/wireless/ti/wl1251/acx.h #define CFG_MC_FILTER_EN BIT(6) BIT 723 drivers/net/wireless/ti/wl1251/acx.h #define CFG_MC_ADDR0_EN BIT(7) BIT 724 drivers/net/wireless/ti/wl1251/acx.h #define CFG_MC_ADDR1_EN BIT(8) BIT 725 drivers/net/wireless/ti/wl1251/acx.h #define CFG_BC_REJECT_EN BIT(9) BIT 726 drivers/net/wireless/ti/wl1251/acx.h #define CFG_SSID_FILTER_EN BIT(10) BIT 727 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_INT_FCS_ERROR BIT(11) BIT 728 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_INT_ENCRYPTED BIT(12) BIT 729 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_WR_RX_STATUS BIT(13) BIT 730 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_FILTER_NULTI BIT(14) BIT 731 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_RESERVE BIT(15) BIT 732 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_TIMESTAMP_TSF BIT(16) BIT 734 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_RSV_EN BIT(0) BIT 735 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_RCTS_ACK BIT(1) BIT 736 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_PRSP_EN BIT(2) BIT 737 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_PREQ_EN BIT(3) BIT 738 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_MGMT_EN BIT(4) BIT 739 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_FCS_ERROR BIT(5) BIT 740 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_DATA_EN BIT(6) BIT 741 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_CTL_EN BIT(7) BIT 742 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_CF_EN BIT(8) BIT 743 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_BCN_EN BIT(9) BIT 744 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_AUTH_EN BIT(10) BIT 745 drivers/net/wireless/ti/wl1251/acx.h #define CFG_RX_ASSOC_EN BIT(11) BIT 747 drivers/net/wireless/ti/wl1251/acx.h #define SCAN_PASSIVE BIT(0) BIT 748 drivers/net/wireless/ti/wl1251/acx.h #define SCAN_5GHZ_BAND BIT(1) BIT 749 drivers/net/wireless/ti/wl1251/acx.h #define SCAN_TRIGGERED BIT(2) BIT 750 drivers/net/wireless/ti/wl1251/acx.h #define SCAN_PRIORITY_HIGH BIT(3) BIT 1323 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_RX0_DATA BIT(0) BIT 1326 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_TX_RESULT BIT(1) BIT 1329 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_TX_XFR BIT(2) BIT 1332 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_RX1_DATA BIT(3) BIT 1335 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_EVENT_A BIT(4) BIT 1338 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_EVENT_B BIT(5) BIT 1341 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_WAKE_ON_HOST BIT(6) BIT 1344 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_TRACE_A BIT(7) BIT 1347 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_TRACE_B BIT(8) BIT 1350 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_CMD_COMPLETE BIT(9) BIT 1353 drivers/net/wireless/ti/wl1251/acx.h #define WL1251_ACX_INTR_INIT_COMPLETE BIT(14) BIT 25 drivers/net/wireless/ti/wl1251/event.h RESERVED1_EVENT_ID = BIT(0), BIT 26 drivers/net/wireless/ti/wl1251/event.h RESERVED2_EVENT_ID = BIT(1), BIT 27 drivers/net/wireless/ti/wl1251/event.h MEASUREMENT_START_EVENT_ID = BIT(2), BIT 28 drivers/net/wireless/ti/wl1251/event.h SCAN_COMPLETE_EVENT_ID = BIT(3), BIT 29 drivers/net/wireless/ti/wl1251/event.h CALIBRATION_COMPLETE_EVENT_ID = BIT(4), BIT 30 drivers/net/wireless/ti/wl1251/event.h ROAMING_TRIGGER_LOW_RSSI_EVENT_ID = BIT(5), BIT 31 drivers/net/wireless/ti/wl1251/event.h PS_REPORT_EVENT_ID = BIT(6), BIT 32 drivers/net/wireless/ti/wl1251/event.h SYNCHRONIZATION_TIMEOUT_EVENT_ID = BIT(7), BIT 33 drivers/net/wireless/ti/wl1251/event.h HEALTH_REPORT_EVENT_ID = BIT(8), BIT 34 drivers/net/wireless/ti/wl1251/event.h ACI_DETECTION_EVENT_ID = BIT(9), BIT 35 drivers/net/wireless/ti/wl1251/event.h DEBUG_REPORT_EVENT_ID = BIT(10), BIT 36 drivers/net/wireless/ti/wl1251/event.h MAC_STATUS_EVENT_ID = BIT(11), BIT 37 drivers/net/wireless/ti/wl1251/event.h DISCONNECT_EVENT_COMPLETE_ID = BIT(12), BIT 38 drivers/net/wireless/ti/wl1251/event.h JOIN_EVENT_COMPLETE_ID = BIT(13), BIT 39 drivers/net/wireless/ti/wl1251/event.h CHANNEL_SWITCH_COMPLETE_EVENT_ID = BIT(14), BIT 40 drivers/net/wireless/ti/wl1251/event.h BSS_LOSE_EVENT_ID = BIT(15), BIT 41 drivers/net/wireless/ti/wl1251/event.h ROAMING_TRIGGER_MAX_TX_RETRY_EVENT_ID = BIT(16), BIT 42 drivers/net/wireless/ti/wl1251/event.h MEASUREMENT_COMPLETE_EVENT_ID = BIT(17), BIT 43 drivers/net/wireless/ti/wl1251/event.h AP_DISCOVERY_COMPLETE_EVENT_ID = BIT(18), BIT 44 drivers/net/wireless/ti/wl1251/event.h SCHEDULED_SCAN_COMPLETE_EVENT_ID = BIT(19), BIT 45 drivers/net/wireless/ti/wl1251/event.h PSPOLL_DELIVERY_FAILURE_EVENT_ID = BIT(20), BIT 46 drivers/net/wireless/ti/wl1251/event.h RESET_BSS_EVENT_ID = BIT(21), BIT 47 drivers/net/wireless/ti/wl1251/event.h REGAINED_BSS_EVENT_ID = BIT(22), BIT 48 drivers/net/wireless/ti/wl1251/event.h ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID = BIT(23), BIT 49 drivers/net/wireless/ti/wl1251/event.h ROAMING_TRIGGER_LOW_SNR_EVENT_ID = BIT(24), BIT 50 drivers/net/wireless/ti/wl1251/event.h ROAMING_TRIGGER_REGAINED_SNR_EVENT_ID = BIT(25), BIT 52 drivers/net/wireless/ti/wl1251/event.h DBG_EVENT_ID = BIT(26), BIT 53 drivers/net/wireless/ti/wl1251/event.h BT_PTA_SENSE_EVENT_ID = BIT(27), BIT 54 drivers/net/wireless/ti/wl1251/event.h BT_PTA_PREDICTION_EVENT_ID = BIT(28), BIT 55 drivers/net/wireless/ti/wl1251/event.h BT_PTA_AVALANCHE_EVENT_ID = BIT(29), BIT 57 drivers/net/wireless/ti/wl1251/event.h PLT_RX_CALIBRATION_COMPLETE_EVENT_ID = BIT(30), BIT 1520 drivers/net/wireless/ti/wl1251/main.c wl->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 1521 drivers/net/wireless/ti/wl1251/main.c BIT(NL80211_IFTYPE_ADHOC); BIT 239 drivers/net/wireless/ti/wl1251/reg.h #define ACX_SLV_SOFT_RESET_BIT BIT(0) BIT 240 drivers/net/wireless/ti/wl1251/reg.h #define ACX_REG_EEPROM_START_BIT BIT(0) BIT 548 drivers/net/wireless/ti/wl1251/reg.h #define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */ BIT 549 drivers/net/wireless/ti/wl1251/reg.h #define OFDM_RATE_BIT BIT(6) BIT 550 drivers/net/wireless/ti/wl1251/reg.h #define PBCC_RATE_BIT BIT(7) BIT 596 drivers/net/wireless/ti/wl1251/reg.h #define INTR_TRIG_CMD BIT(0) BIT 604 drivers/net/wireless/ti/wl1251/reg.h #define INTR_TRIG_EVENT_ACK BIT(1) BIT 611 drivers/net/wireless/ti/wl1251/reg.h #define INTR_TRIG_TX_PROC0 BIT(2) BIT 618 drivers/net/wireless/ti/wl1251/reg.h #define INTR_TRIG_RX_PROC0 BIT(3) BIT 620 drivers/net/wireless/ti/wl1251/reg.h #define INTR_TRIG_DEBUG_ACK BIT(4) BIT 622 drivers/net/wireless/ti/wl1251/reg.h #define INTR_TRIG_STATE_CHANGED BIT(5) BIT 632 drivers/net/wireless/ti/wl1251/reg.h #define INTR_TRIG_RX_PROC1 BIT(17) BIT 639 drivers/net/wireless/ti/wl1251/reg.h #define INTR_TRIG_TX_PROC1 BIT(18) BIT 39 drivers/net/wireless/ti/wl1251/rx.h #define SHORT_PREAMBLE_BIT BIT(0) BIT 40 drivers/net/wireless/ti/wl1251/rx.h #define OFDM_RATE_BIT BIT(6) BIT 41 drivers/net/wireless/ti/wl1251/rx.h #define PBCC_RATE_BIT BIT(7) BIT 147 drivers/net/wireless/ti/wl1251/tx.h TX_DMA_ERROR = BIT(7), BIT 148 drivers/net/wireless/ti/wl1251/tx.h TX_DISABLED = BIT(6), BIT 149 drivers/net/wireless/ti/wl1251/tx.h TX_RETRY_EXCEEDED = BIT(5), BIT 150 drivers/net/wireless/ti/wl1251/tx.h TX_TIMEOUT = BIT(4), BIT 151 drivers/net/wireless/ti/wl1251/tx.h TX_KEY_NOT_FOUND = BIT(3), BIT 152 drivers/net/wireless/ti/wl1251/tx.h TX_ENCRYPT_FAIL = BIT(2), BIT 153 drivers/net/wireless/ti/wl1251/tx.h TX_UNAVAILABLE_PRIORITY = BIT(1), BIT 22 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_IRQ = BIT(0), BIT 23 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_SPI = BIT(1), BIT 24 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_BOOT = BIT(2), BIT 25 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_MAILBOX = BIT(3), BIT 26 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_NETLINK = BIT(4), BIT 27 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_EVENT = BIT(5), BIT 28 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_TX = BIT(6), BIT 29 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_RX = BIT(7), BIT 30 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_SCAN = BIT(8), BIT 31 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_CRYPT = BIT(9), BIT 32 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_PSM = BIT(10), BIT 33 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_MAC80211 = BIT(11), BIT 34 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_CMD = BIT(12), BIT 35 drivers/net/wireless/ti/wl1251/wl1251.h DEBUG_ACX = BIT(13), BIT 76 drivers/net/wireless/ti/wl12xx/event.c BIT(mbox->role_id), BIT 14 drivers/net/wireless/ti/wl12xx/event.h MEASUREMENT_START_EVENT_ID = BIT(8), BIT 15 drivers/net/wireless/ti/wl12xx/event.h MEASUREMENT_COMPLETE_EVENT_ID = BIT(9), BIT 16 drivers/net/wireless/ti/wl12xx/event.h SCAN_COMPLETE_EVENT_ID = BIT(10), BIT 17 drivers/net/wireless/ti/wl12xx/event.h WFD_DISCOVERY_COMPLETE_EVENT_ID = BIT(11), BIT 18 drivers/net/wireless/ti/wl12xx/event.h AP_DISCOVERY_COMPLETE_EVENT_ID = BIT(12), BIT 19 drivers/net/wireless/ti/wl12xx/event.h RESERVED1 = BIT(13), BIT 20 drivers/net/wireless/ti/wl12xx/event.h PSPOLL_DELIVERY_FAILURE_EVENT_ID = BIT(14), BIT 21 drivers/net/wireless/ti/wl12xx/event.h ROLE_STOP_COMPLETE_EVENT_ID = BIT(15), BIT 22 drivers/net/wireless/ti/wl12xx/event.h RADAR_DETECTED_EVENT_ID = BIT(16), BIT 23 drivers/net/wireless/ti/wl12xx/event.h CHANNEL_SWITCH_COMPLETE_EVENT_ID = BIT(17), BIT 24 drivers/net/wireless/ti/wl12xx/event.h BSS_LOSE_EVENT_ID = BIT(18), BIT 25 drivers/net/wireless/ti/wl12xx/event.h REGAINED_BSS_EVENT_ID = BIT(19), BIT 26 drivers/net/wireless/ti/wl12xx/event.h MAX_TX_RETRY_EVENT_ID = BIT(20), BIT 27 drivers/net/wireless/ti/wl12xx/event.h DUMMY_PACKET_EVENT_ID = BIT(21), BIT 28 drivers/net/wireless/ti/wl12xx/event.h SOFT_GEMINI_SENSE_EVENT_ID = BIT(22), BIT 29 drivers/net/wireless/ti/wl12xx/event.h CHANGE_AUTO_MODE_TIMEOUT_EVENT_ID = BIT(23), BIT 30 drivers/net/wireless/ti/wl12xx/event.h SOFT_GEMINI_AVALANCHE_EVENT_ID = BIT(24), BIT 31 drivers/net/wireless/ti/wl12xx/event.h PLT_RX_CALIBRATION_COMPLETE_EVENT_ID = BIT(25), BIT 32 drivers/net/wireless/ti/wl12xx/event.h INACTIVE_STA_EVENT_ID = BIT(26), BIT 33 drivers/net/wireless/ti/wl12xx/event.h PEER_REMOVE_COMPLETE_EVENT_ID = BIT(27), BIT 34 drivers/net/wireless/ti/wl12xx/event.h PERIODIC_SCAN_COMPLETE_EVENT_ID = BIT(28), BIT 35 drivers/net/wireless/ti/wl12xx/event.h PERIODIC_SCAN_REPORT_EVENT_ID = BIT(29), BIT 36 drivers/net/wireless/ti/wl12xx/event.h BA_SESSION_RX_CONSTRAINT_EVENT_ID = BIT(30), BIT 37 drivers/net/wireless/ti/wl12xx/event.h REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID = BIT(31), BIT 800 drivers/net/wireless/ti/wl12xx/main.c spare_reg |= (BIT(3) | BIT(5) | BIT(6)); BIT 881 drivers/net/wireless/ti/wl12xx/main.c spare_reg |= BIT(2); BIT 1739 drivers/net/wireless/ti/wl12xx/main.c .types = BIT(NL80211_IFTYPE_STATION), BIT 1743 drivers/net/wireless/ti/wl12xx/main.c .types = BIT(NL80211_IFTYPE_AP) | BIT 1744 drivers/net/wireless/ti/wl12xx/main.c BIT(NL80211_IFTYPE_P2P_GO) | BIT 1745 drivers/net/wireless/ti/wl12xx/main.c BIT(NL80211_IFTYPE_P2P_CLIENT), BIT 238 drivers/net/wireless/ti/wl12xx/reg.h #define ACX_REG_EEPROM_START_BIT BIT(1) BIT 369 drivers/net/wireless/ti/wl12xx/reg.h #define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */ BIT 370 drivers/net/wireless/ti/wl12xx/reg.h #define OFDM_RATE_BIT BIT(6) BIT 371 drivers/net/wireless/ti/wl12xx/reg.h #define PBCC_RATE_BIT BIT(7) BIT 405 drivers/net/wireless/ti/wl12xx/reg.h #define OCP_READY_MASK BIT(18) BIT 406 drivers/net/wireless/ti/wl12xx/reg.h #define OCP_STATUS_MASK (BIT(16) | BIT(17)) BIT 417 drivers/net/wireless/ti/wl12xx/reg.h #define POLARITY_LOW BIT(1) BIT 418 drivers/net/wireless/ti/wl12xx/reg.h #define NO_PULL (BIT(14) | BIT(15)) BIT 430 drivers/net/wireless/ti/wl12xx/reg.h #define MCS_PLL_CLK_SEL_FREF BIT(0) BIT 432 drivers/net/wireless/ti/wl12xx/reg.h #define WL_CLK_REQ_TYPE_FREF BIT(3) BIT 433 drivers/net/wireless/ti/wl12xx/reg.h #define WL_CLK_REQ_TYPE_PG2 (BIT(3) | BIT(2)) BIT 435 drivers/net/wireless/ti/wl12xx/reg.h #define PRCM_CM_EN_MUX_WLAN_FREF BIT(4) BIT 440 drivers/net/wireless/ti/wl12xx/reg.h #define TCXO_DET_FAILED BIT(4) BIT 444 drivers/net/wireless/ti/wl12xx/reg.h #define FREF_CLK_DETECT_FAIL BIT(4) BIT 448 drivers/net/wireless/ti/wl12xx/reg.h #define WL_SPARE_VAL BIT(2) BIT 450 drivers/net/wireless/ti/wl12xx/reg.h #define WL_SPARE_MASK_8526 (BIT(6) | BIT(5) | BIT(3)) BIT 460 drivers/net/wireless/ti/wl12xx/reg.h #define MCS_PLL_ENABLE_HP (BIT(0) | BIT(1)) BIT 485 drivers/net/wireless/ti/wl12xx/reg.h #define WL12XX_INTR_TRIG_CMD BIT(0) BIT 493 drivers/net/wireless/ti/wl12xx/reg.h #define WL12XX_INTR_TRIG_EVENT_ACK BIT(1) BIT 14 drivers/net/wireless/ti/wl18xx/event.h SCAN_COMPLETE_EVENT_ID = BIT(8), BIT 15 drivers/net/wireless/ti/wl18xx/event.h RADAR_DETECTED_EVENT_ID = BIT(9), BIT 16 drivers/net/wireless/ti/wl18xx/event.h CHANNEL_SWITCH_COMPLETE_EVENT_ID = BIT(10), BIT 17 drivers/net/wireless/ti/wl18xx/event.h BSS_LOSS_EVENT_ID = BIT(11), BIT 18 drivers/net/wireless/ti/wl18xx/event.h MAX_TX_FAILURE_EVENT_ID = BIT(12), BIT 19 drivers/net/wireless/ti/wl18xx/event.h DUMMY_PACKET_EVENT_ID = BIT(13), BIT 20 drivers/net/wireless/ti/wl18xx/event.h INACTIVE_STA_EVENT_ID = BIT(14), BIT 21 drivers/net/wireless/ti/wl18xx/event.h PEER_REMOVE_COMPLETE_EVENT_ID = BIT(15), BIT 22 drivers/net/wireless/ti/wl18xx/event.h PERIODIC_SCAN_COMPLETE_EVENT_ID = BIT(16), BIT 23 drivers/net/wireless/ti/wl18xx/event.h BA_SESSION_RX_CONSTRAINT_EVENT_ID = BIT(17), BIT 24 drivers/net/wireless/ti/wl18xx/event.h REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID = BIT(18), BIT 25 drivers/net/wireless/ti/wl18xx/event.h DFS_CHANNELS_CONFIG_COMPLETE_EVENT = BIT(19), BIT 26 drivers/net/wireless/ti/wl18xx/event.h PERIODIC_SCAN_REPORT_EVENT_ID = BIT(20), BIT 27 drivers/net/wireless/ti/wl18xx/event.h RX_BA_WIN_SIZE_CHANGE_EVENT_ID = BIT(21), BIT 28 drivers/net/wireless/ti/wl18xx/event.h SMART_CONFIG_SYNC_EVENT_ID = BIT(22), BIT 29 drivers/net/wireless/ti/wl18xx/event.h SMART_CONFIG_DECODE_EVENT_ID = BIT(23), BIT 30 drivers/net/wireless/ti/wl18xx/event.h TIME_SYNC_EVENT_ID = BIT(24), BIT 31 drivers/net/wireless/ti/wl18xx/event.h FW_LOGGER_INDICATION = BIT(25), BIT 933 drivers/net/wireless/ti/wl18xx/main.c irq_invert |= BIT(1); BIT 1816 drivers/net/wireless/ti/wl18xx/main.c .types = BIT(NL80211_IFTYPE_STATION), BIT 1820 drivers/net/wireless/ti/wl18xx/main.c .types = BIT(NL80211_IFTYPE_AP) BIT 1821 drivers/net/wireless/ti/wl18xx/main.c | BIT(NL80211_IFTYPE_P2P_GO) BIT 1822 drivers/net/wireless/ti/wl18xx/main.c | BIT(NL80211_IFTYPE_P2P_CLIENT) BIT 1824 drivers/net/wireless/ti/wl18xx/main.c | BIT(NL80211_IFTYPE_MESH_POINT) BIT 1829 drivers/net/wireless/ti/wl18xx/main.c .types = BIT(NL80211_IFTYPE_P2P_DEVICE), BIT 1836 drivers/net/wireless/ti/wl18xx/main.c .types = BIT(NL80211_IFTYPE_AP), BIT 1841 drivers/net/wireless/ti/wl18xx/main.c .types = BIT(NL80211_IFTYPE_MESH_POINT), BIT 1846 drivers/net/wireless/ti/wl18xx/main.c .types = BIT(NL80211_IFTYPE_P2P_DEVICE), BIT 1863 drivers/net/wireless/ti/wl18xx/main.c .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) | BIT 1864 drivers/net/wireless/ti/wl18xx/main.c BIT(NL80211_CHAN_HT20) | BIT 1865 drivers/net/wireless/ti/wl18xx/main.c BIT(NL80211_CHAN_HT40MINUS) | BIT 1866 drivers/net/wireless/ti/wl18xx/main.c BIT(NL80211_CHAN_HT40PLUS), BIT 167 drivers/net/wireless/ti/wl18xx/reg.h #define WL18XX_INTR_TRIG_CMD BIT(28) BIT 175 drivers/net/wireless/ti/wl18xx/reg.h #define WL18XX_INTR_TRIG_EVENT_ACK BIT(29) BIT 77 drivers/net/wireless/ti/wl18xx/tx.c tx_success = !(tx_stat_byte & BIT(WL18XX_TX_STATUS_STAT_BIT_IDX)); BIT 22 drivers/net/wireless/ti/wl18xx/tx.h #define WL18XX_TX_CTRL_NOT_PADDED BIT(7) BIT 28 drivers/net/wireless/ti/wl18xx/tx.h #define CONF_TX_RATE_USE_WIDE_CHAN BIT(31) BIT 1429 drivers/net/wireless/ti/wlcore/acx.c BIT(CMD_STATUS_NO_RX_BA_SESSION)); BIT 1504 drivers/net/wireless/ti/wlcore/acx.c if (!(conf_queues & BIT(i))) BIT 1509 drivers/net/wireless/ti/wlcore/acx.c rx_streaming->enable = enable_queues & BIT(i); BIT 23 drivers/net/wireless/ti/wlcore/acx.h #define WL1271_ACX_INTR_WATCHDOG BIT(0) BIT 25 drivers/net/wireless/ti/wlcore/acx.h #define WL1271_ACX_INTR_INIT_COMPLETE BIT(1) BIT 27 drivers/net/wireless/ti/wlcore/acx.h #define WL1271_ACX_INTR_EVENT_A BIT(2) BIT 29 drivers/net/wireless/ti/wlcore/acx.h #define WL1271_ACX_INTR_EVENT_B BIT(3) BIT 31 drivers/net/wireless/ti/wlcore/acx.h #define WL1271_ACX_INTR_CMD_COMPLETE BIT(4) BIT 33 drivers/net/wireless/ti/wlcore/acx.h #define WL1271_ACX_INTR_HW_AVAILABLE BIT(5) BIT 35 drivers/net/wireless/ti/wlcore/acx.h #define WL1271_ACX_INTR_DATA BIT(6) BIT 37 drivers/net/wireless/ti/wlcore/acx.h #define WL1271_ACX_INTR_TRACE_A BIT(7) BIT 39 drivers/net/wireless/ti/wlcore/acx.h #define WL1271_ACX_INTR_TRACE_B BIT(8) BIT 41 drivers/net/wireless/ti/wlcore/acx.h #define WL1271_ACX_SW_INTR_WATCHDOG BIT(9) BIT 334 drivers/net/wireless/ti/wlcore/acx.h #define SCAN_PASSIVE BIT(0) BIT 335 drivers/net/wireless/ti/wlcore/acx.h #define SCAN_5GHZ_BAND BIT(1) BIT 336 drivers/net/wireless/ti/wlcore/acx.h #define SCAN_TRIGGERED BIT(2) BIT 337 drivers/net/wireless/ti/wlcore/acx.h #define SCAN_PRIORITY_HIGH BIT(3) BIT 543 drivers/net/wireless/ti/wlcore/acx.h #define ACX_ARP_FILTER_ARP_FILTERING BIT(0) BIT 544 drivers/net/wireless/ti/wlcore/acx.h #define ACX_ARP_FILTER_AUTO_ARP BIT(1) BIT 595 drivers/net/wireless/ti/wlcore/acx.h #define HOST_IF_CFG_RX_FIFO_ENABLE BIT(0) BIT 596 drivers/net/wireless/ti/wlcore/acx.h #define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1) BIT 597 drivers/net/wireless/ti/wlcore/acx.h #define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3) BIT 598 drivers/net/wireless/ti/wlcore/acx.h #define HOST_IF_CFG_RX_PAD_TO_SDIO_BLK BIT(4) BIT 599 drivers/net/wireless/ti/wlcore/acx.h #define HOST_IF_CFG_ADD_RX_ALIGNMENT BIT(6) BIT 657 drivers/net/wireless/ti/wlcore/acx.h #define WL12XX_HT_CAP_HT_OPERATION BIT(16) BIT 131 drivers/net/wireless/ti/wlcore/cmd.c valid_rets |= BIT(CMD_STATUS_SUCCESS); BIT 1550 drivers/net/wireless/ti/wlcore/cmd.c if (sta->wme && (sta->uapsd_queues & BIT(i))) BIT 14 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_1MBPS = BIT(0), BIT 15 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_2MBPS = BIT(1), BIT 16 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_5_5MBPS = BIT(2), BIT 17 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_6MBPS = BIT(3), BIT 18 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_9MBPS = BIT(4), BIT 19 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_11MBPS = BIT(5), BIT 20 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_12MBPS = BIT(6), BIT 21 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_18MBPS = BIT(7), BIT 22 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_22MBPS = BIT(8), BIT 23 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_24MBPS = BIT(9), BIT 24 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_36MBPS = BIT(10), BIT 25 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_48MBPS = BIT(11), BIT 26 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_54MBPS = BIT(12), BIT 27 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_0 = BIT(13), BIT 28 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_1 = BIT(14), BIT 29 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_2 = BIT(15), BIT 30 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_3 = BIT(16), BIT 31 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_4 = BIT(17), BIT 32 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_5 = BIT(18), BIT 33 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_6 = BIT(19), BIT 34 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_7 = BIT(20), BIT 35 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_8 = BIT(21), BIT 36 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_9 = BIT(22), BIT 37 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_10 = BIT(23), BIT 38 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_11 = BIT(24), BIT 39 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_12 = BIT(25), BIT 40 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_13 = BIT(26), BIT 41 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_14 = BIT(27), BIT 42 drivers/net/wireless/ti/wlcore/conf.h CONF_HW_BIT_RATE_MCS_15 = BIT(28), BIT 488 drivers/net/wireless/ti/wlcore/conf.h #define CONF_BCN_RULE_PASS_ON_CHANGE BIT(0) BIT 489 drivers/net/wireless/ti/wlcore/conf.h #define CONF_BCN_RULE_PASS_ON_APPEARANCE BIT(1) BIT 22 drivers/net/wireless/ti/wlcore/debug.h DEBUG_IRQ = BIT(0), BIT 23 drivers/net/wireless/ti/wlcore/debug.h DEBUG_SPI = BIT(1), BIT 24 drivers/net/wireless/ti/wlcore/debug.h DEBUG_BOOT = BIT(2), BIT 25 drivers/net/wireless/ti/wlcore/debug.h DEBUG_MAILBOX = BIT(3), BIT 26 drivers/net/wireless/ti/wlcore/debug.h DEBUG_TESTMODE = BIT(4), BIT 27 drivers/net/wireless/ti/wlcore/debug.h DEBUG_EVENT = BIT(5), BIT 28 drivers/net/wireless/ti/wlcore/debug.h DEBUG_TX = BIT(6), BIT 29 drivers/net/wireless/ti/wlcore/debug.h DEBUG_RX = BIT(7), BIT 30 drivers/net/wireless/ti/wlcore/debug.h DEBUG_SCAN = BIT(8), BIT 31 drivers/net/wireless/ti/wlcore/debug.h DEBUG_CRYPT = BIT(9), BIT 32 drivers/net/wireless/ti/wlcore/debug.h DEBUG_PSM = BIT(10), BIT 33 drivers/net/wireless/ti/wlcore/debug.h DEBUG_MAC80211 = BIT(11), BIT 34 drivers/net/wireless/ti/wlcore/debug.h DEBUG_CMD = BIT(12), BIT 35 drivers/net/wireless/ti/wlcore/debug.h DEBUG_ACX = BIT(13), BIT 36 drivers/net/wireless/ti/wlcore/debug.h DEBUG_SDIO = BIT(14), BIT 37 drivers/net/wireless/ti/wlcore/debug.h DEBUG_FILTERS = BIT(15), BIT 38 drivers/net/wireless/ti/wlcore/debug.h DEBUG_ADHOC = BIT(16), BIT 39 drivers/net/wireless/ti/wlcore/debug.h DEBUG_AP = BIT(17), BIT 40 drivers/net/wireless/ti/wlcore/debug.h DEBUG_PROBE = BIT(18), BIT 41 drivers/net/wireless/ti/wlcore/debug.h DEBUG_IO = BIT(19), BIT 27 drivers/net/wireless/ti/wlcore/event.h RSSI_SNR_TRIGGER_0_EVENT_ID = BIT(0), BIT 28 drivers/net/wireless/ti/wlcore/event.h RSSI_SNR_TRIGGER_1_EVENT_ID = BIT(1), BIT 29 drivers/net/wireless/ti/wlcore/event.h RSSI_SNR_TRIGGER_2_EVENT_ID = BIT(2), BIT 30 drivers/net/wireless/ti/wlcore/event.h RSSI_SNR_TRIGGER_3_EVENT_ID = BIT(3), BIT 31 drivers/net/wireless/ti/wlcore/event.h RSSI_SNR_TRIGGER_4_EVENT_ID = BIT(4), BIT 32 drivers/net/wireless/ti/wlcore/event.h RSSI_SNR_TRIGGER_5_EVENT_ID = BIT(5), BIT 33 drivers/net/wireless/ti/wlcore/event.h RSSI_SNR_TRIGGER_6_EVENT_ID = BIT(6), BIT 34 drivers/net/wireless/ti/wlcore/event.h RSSI_SNR_TRIGGER_7_EVENT_ID = BIT(7), BIT 14 drivers/net/wireless/ti/wlcore/ini.h #define SCRATCH_ENABLE_LPD BIT(25) BIT 5384 drivers/net/wireless/ti/wlcore/main.c if (*ba_bitmap & BIT(tid)) { BIT 5396 drivers/net/wireless/ti/wlcore/main.c *ba_bitmap |= BIT(tid); BIT 5402 drivers/net/wireless/ti/wlcore/main.c if (!(*ba_bitmap & BIT(tid))) { BIT 5417 drivers/net/wireless/ti/wlcore/main.c *ba_bitmap &= ~BIT(tid); BIT 6096 drivers/net/wireless/ti/wlcore/main.c wl->addresses[idx].addr[0] |= BIT(1); BIT 6243 drivers/net/wireless/ti/wlcore/main.c wl->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 6244 drivers/net/wireless/ti/wlcore/main.c BIT(NL80211_IFTYPE_AP) | BIT 6245 drivers/net/wireless/ti/wlcore/main.c BIT(NL80211_IFTYPE_P2P_DEVICE) | BIT 6246 drivers/net/wireless/ti/wlcore/main.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 6248 drivers/net/wireless/ti/wlcore/main.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 6250 drivers/net/wireless/ti/wlcore/main.c BIT(NL80211_IFTYPE_P2P_GO); BIT 69 drivers/net/wireless/ti/wlcore/rx.c status->signal = ((desc->rssi & RSSI_LEVEL_BITMASK) | BIT(7)); BIT 20 drivers/net/wireless/ti/wlcore/rx.h #define ANT_DIVERSITY_BITMASK BIT(7) BIT 22 drivers/net/wireless/ti/wlcore/rx.h #define SHORT_PREAMBLE_BIT BIT(0) BIT 23 drivers/net/wireless/ti/wlcore/rx.h #define OFDM_RATE_BIT BIT(6) BIT 24 drivers/net/wireless/ti/wlcore/rx.h #define PBCC_RATE_BIT BIT(7) BIT 60 drivers/net/wireless/ti/wlcore/rx.h #define WL1271_RX_DESC_STBC BIT(2) BIT 61 drivers/net/wireless/ti/wlcore/rx.h #define WL1271_RX_DESC_A_MPDU BIT(3) BIT 62 drivers/net/wireless/ti/wlcore/rx.h #define WL1271_RX_DESC_HT BIT(4) BIT 89 drivers/net/wireless/ti/wlcore/rx.h #define RX_BUF_UNALIGNED_PAYLOAD BIT(20) BIT 92 drivers/net/wireless/ti/wlcore/rx.h #define RX_BUF_PADDED_PAYLOAD BIT(30) BIT 93 drivers/net/wireless/ti/wlcore/scan.h #define SCAN_CHANNEL_FLAGS_DFS BIT(0) /* channel is passive until an BIT 95 drivers/net/wireless/ti/wlcore/scan.h #define SCAN_CHANNEL_FLAGS_DFS_ENABLED BIT(1) BIT 1193 drivers/net/wireless/ti/wlcore/tx.c return BIT(__ffs(rate_set)); BIT 17 drivers/net/wireless/ti/wlcore/tx.h #define TX_HW_ATTR_SAVE_RETRIES BIT(0) BIT 18 drivers/net/wireless/ti/wlcore/tx.h #define TX_HW_ATTR_HEADER_PAD BIT(1) BIT 19 drivers/net/wireless/ti/wlcore/tx.h #define TX_HW_ATTR_SESSION_COUNTER (BIT(2) | BIT(3) | BIT(4)) BIT 20 drivers/net/wireless/ti/wlcore/tx.h #define TX_HW_ATTR_RATE_POLICY (BIT(5) | BIT(6) | BIT(7) | \ BIT 21 drivers/net/wireless/ti/wlcore/tx.h BIT(8) | BIT(9)) BIT 22 drivers/net/wireless/ti/wlcore/tx.h #define TX_HW_ATTR_LAST_WORD_PAD (BIT(10) | BIT(11)) BIT 23 drivers/net/wireless/ti/wlcore/tx.h #define TX_HW_ATTR_TX_CMPLT_REQ BIT(12) BIT 24 drivers/net/wireless/ti/wlcore/tx.h #define TX_HW_ATTR_TX_DUMMY_REQ BIT(13) BIT 25 drivers/net/wireless/ti/wlcore/tx.h #define TX_HW_ATTR_HOST_ENCRYPT BIT(14) BIT 26 drivers/net/wireless/ti/wlcore/tx.h #define TX_HW_ATTR_EAPOL_FRAME BIT(15) BIT 548 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0) BIT 551 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_START_STA_FAILS BIT(1) BIT 554 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2) BIT 557 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3) BIT 560 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4) BIT 563 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_LEGACY_NVS BIT(5) BIT 566 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7) BIT 569 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8) BIT 572 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9) BIT 575 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10) BIT 578 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11) BIT 581 drivers/net/wireless/ti/wlcore/wlcore.h #define WLCORE_QUIRK_AP_ZERO_SESSION_ID BIT(12) BIT 606 drivers/net/wireless/ti/wlcore/wlcore.h #define INTR_TRIG_TX_PROC0 BIT(2) BIT 613 drivers/net/wireless/ti/wlcore/wlcore.h #define INTR_TRIG_RX_PROC0 BIT(3) BIT 615 drivers/net/wireless/ti/wlcore/wlcore.h #define INTR_TRIG_DEBUG_ACK BIT(4) BIT 617 drivers/net/wireless/ti/wlcore/wlcore.h #define INTR_TRIG_STATE_CHANGED BIT(5) BIT 626 drivers/net/wireless/ti/wlcore/wlcore.h #define INTR_TRIG_RX_PROC1 BIT(17) BIT 633 drivers/net/wireless/ti/wlcore/wlcore.h #define INTR_TRIG_TX_PROC1 BIT(18) BIT 635 drivers/net/wireless/ti/wlcore/wlcore.h #define ACX_SLV_SOFT_RESET_BIT BIT(1) BIT 294 drivers/net/wireless/ti/wlcore/wlcore_i.h #define WL1271_RX_FILTER_FLAG_MASK BIT(0) BIT 296 drivers/net/wireless/ti/wlcore/wlcore_i.h #define WL1271_RX_FILTER_FLAG_ETHERNET_HEADER BIT(1) BIT 363 drivers/net/wireless/virt_wifi.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); BIT 1392 drivers/net/wireless/zydas/zd1211rw/zd_mac.c BIT(NL80211_IFTYPE_MESH_POINT) | BIT 1393 drivers/net/wireless/zydas/zd1211rw/zd_mac.c BIT(NL80211_IFTYPE_STATION) | BIT 1394 drivers/net/wireless/zydas/zd1211rw/zd_mac.c BIT(NL80211_IFTYPE_ADHOC) | BIT 1395 drivers/net/wireless/zydas/zd1211rw/zd_mac.c BIT(NL80211_IFTYPE_AP); BIT 148 drivers/nfc/trf7970a.c #define TRF7970A_QUIRK_IRQ_STATUS_READ BIT(0) BIT 149 drivers/nfc/trf7970a.c #define TRF7970A_QUIRK_EN2_MUST_STAY_LOW BIT(1) BIT 174 drivers/nfc/trf7970a.c #define TRF7970A_CMD_BIT_CTRL BIT(7) BIT 175 drivers/nfc/trf7970a.c #define TRF7970A_CMD_BIT_RW BIT(6) BIT 176 drivers/nfc/trf7970a.c #define TRF7970A_CMD_BIT_CONTINUOUS BIT(5) BIT 213 drivers/nfc/trf7970a.c #define TRF7970A_CHIP_STATUS_VRS5_3 BIT(0) BIT 214 drivers/nfc/trf7970a.c #define TRF7970A_CHIP_STATUS_REC_ON BIT(1) BIT 215 drivers/nfc/trf7970a.c #define TRF7970A_CHIP_STATUS_AGC_ON BIT(2) BIT 216 drivers/nfc/trf7970a.c #define TRF7970A_CHIP_STATUS_PM_ON BIT(3) BIT 217 drivers/nfc/trf7970a.c #define TRF7970A_CHIP_STATUS_RF_PWR BIT(4) BIT 218 drivers/nfc/trf7970a.c #define TRF7970A_CHIP_STATUS_RF_ON BIT(5) BIT 219 drivers/nfc/trf7970a.c #define TRF7970A_CHIP_STATUS_DIRECT BIT(6) BIT 220 drivers/nfc/trf7970a.c #define TRF7970A_CHIP_STATUS_STBY BIT(7) BIT 246 drivers/nfc/trf7970a.c #define TRF7970A_ISO_CTRL_NFC_CE BIT(2) BIT 247 drivers/nfc/trf7970a.c #define TRF7970A_ISO_CTRL_NFC_ACTIVE BIT(3) BIT 248 drivers/nfc/trf7970a.c #define TRF7970A_ISO_CTRL_NFC_INITIATOR BIT(4) BIT 249 drivers/nfc/trf7970a.c #define TRF7970A_ISO_CTRL_NFC_NFC_CE_MODE BIT(5) BIT 250 drivers/nfc/trf7970a.c #define TRF7970A_ISO_CTRL_RFID BIT(5) BIT 251 drivers/nfc/trf7970a.c #define TRF7970A_ISO_CTRL_DIR_MODE BIT(6) BIT 252 drivers/nfc/trf7970a.c #define TRF7970A_ISO_CTRL_RX_CRC_N BIT(7) /* true == No CRC */ BIT 266 drivers/nfc/trf7970a.c #define TRF7970A_MODULATOR_EN_ANA BIT(3) BIT 272 drivers/nfc/trf7970a.c #define TRF7970A_MODULATOR_EN_OOK BIT(6) BIT 273 drivers/nfc/trf7970a.c #define TRF7970A_MODULATOR_27MHZ BIT(7) BIT 275 drivers/nfc/trf7970a.c #define TRF7970A_RX_SPECIAL_SETTINGS_NO_LIM BIT(0) BIT 276 drivers/nfc/trf7970a.c #define TRF7970A_RX_SPECIAL_SETTINGS_AGCR BIT(1) BIT 281 drivers/nfc/trf7970a.c #define TRF7970A_RX_SPECIAL_SETTINGS_HBT BIT(4) BIT 282 drivers/nfc/trf7970a.c #define TRF7970A_RX_SPECIAL_SETTINGS_M848 BIT(5) BIT 283 drivers/nfc/trf7970a.c #define TRF7970A_RX_SPECIAL_SETTINGS_C424 BIT(6) BIT 284 drivers/nfc/trf7970a.c #define TRF7970A_RX_SPECIAL_SETTINGS_C212 BIT(7) BIT 287 drivers/nfc/trf7970a.c #define TRF7970A_REG_IO_CTRL_IO_LOW BIT(5) BIT 288 drivers/nfc/trf7970a.c #define TRF7970A_REG_IO_CTRL_EN_EXT_PA BIT(6) BIT 289 drivers/nfc/trf7970a.c #define TRF7970A_REG_IO_CTRL_AUTO_REG BIT(7) BIT 292 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_NORESP BIT(0) /* ISO15693 only */ BIT 293 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_NFC_COL_ERROR BIT(0) BIT 294 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_COL BIT(1) BIT 295 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_FRAMING_EOF_ERROR BIT(2) BIT 296 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_NFC_RF BIT(2) BIT 297 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_PARITY_ERROR BIT(3) BIT 298 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_NFC_SDD BIT(3) BIT 299 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_CRC_ERROR BIT(4) BIT 300 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_NFC_PROTO_ERROR BIT(4) BIT 301 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_FIFO BIT(5) BIT 302 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_SRX BIT(6) BIT 303 drivers/nfc/trf7970a.c #define TRF7970A_IRQ_STATUS_TX BIT(7) BIT 311 drivers/nfc/trf7970a.c #define TRF7970A_RSSI_OSC_STATUS_RSSI_MASK (BIT(2) | BIT(1) | BIT(0)) BIT 312 drivers/nfc/trf7970a.c #define TRF7970A_RSSI_OSC_STATUS_RSSI_X_MASK (BIT(5) | BIT(4) | BIT(3)) BIT 313 drivers/nfc/trf7970a.c #define TRF7970A_RSSI_OSC_STATUS_RSSI_OSC_OK BIT(6) BIT 315 drivers/nfc/trf7970a.c #define TRF7970A_SPECIAL_FCN_REG1_COL_7_6 BIT(0) BIT 316 drivers/nfc/trf7970a.c #define TRF7970A_SPECIAL_FCN_REG1_14_ANTICOLL BIT(1) BIT 317 drivers/nfc/trf7970a.c #define TRF7970A_SPECIAL_FCN_REG1_4_BIT_RX BIT(2) BIT 318 drivers/nfc/trf7970a.c #define TRF7970A_SPECIAL_FCN_REG1_SP_DIR_MODE BIT(3) BIT 319 drivers/nfc/trf7970a.c #define TRF7970A_SPECIAL_FCN_REG1_NEXT_SLOT_37US BIT(4) BIT 320 drivers/nfc/trf7970a.c #define TRF7970A_SPECIAL_FCN_REG1_PAR43 BIT(5) BIT 332 drivers/nfc/trf7970a.c #define TRF7970A_NFC_LOW_FIELD_LEVEL_CLEX_DIS BIT(7) BIT 335 drivers/nfc/trf7970a.c #define TRF7970A_NFC_TARGET_LEVEL_HI_RF BIT(3) BIT 336 drivers/nfc/trf7970a.c #define TRF7970A_NFC_TARGET_LEVEL_SDD_EN BIT(5) BIT 341 drivers/nfc/trf7970a.c #define TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_106 BIT(0) BIT 342 drivers/nfc/trf7970a.c #define TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_212 BIT(1) BIT 343 drivers/nfc/trf7970a.c #define TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_424 (BIT(0) | BIT(1)) BIT 344 drivers/nfc/trf7970a.c #define TRF79070A_NFC_TARGET_PROTOCOL_PAS_14443B BIT(2) BIT 345 drivers/nfc/trf7970a.c #define TRF79070A_NFC_TARGET_PROTOCOL_PAS_106 BIT(3) BIT 346 drivers/nfc/trf7970a.c #define TRF79070A_NFC_TARGET_PROTOCOL_FELICA BIT(4) BIT 347 drivers/nfc/trf7970a.c #define TRF79070A_NFC_TARGET_PROTOCOL_RF_L BIT(6) BIT 348 drivers/nfc/trf7970a.c #define TRF79070A_NFC_TARGET_PROTOCOL_RF_H BIT(7) BIT 374 drivers/nfc/trf7970a.c #define TRF7970A_FIFO_STATUS_OVERFLOW BIT(7) BIT 396 drivers/nfc/trf7970a.c #define ISO15693_REQ_FLAG_SUB_CARRIER BIT(0) BIT 397 drivers/nfc/trf7970a.c #define ISO15693_REQ_FLAG_DATA_RATE BIT(1) BIT 398 drivers/nfc/trf7970a.c #define ISO15693_REQ_FLAG_INVENTORY BIT(2) BIT 399 drivers/nfc/trf7970a.c #define ISO15693_REQ_FLAG_PROTOCOL_EXT BIT(3) BIT 400 drivers/nfc/trf7970a.c #define ISO15693_REQ_FLAG_SELECT BIT(4) BIT 401 drivers/nfc/trf7970a.c #define ISO15693_REQ_FLAG_AFI BIT(4) BIT 402 drivers/nfc/trf7970a.c #define ISO15693_REQ_FLAG_ADDRESS BIT(5) BIT 403 drivers/nfc/trf7970a.c #define ISO15693_REQ_FLAG_NB_SLOTS BIT(5) BIT 404 drivers/nfc/trf7970a.c #define ISO15693_REQ_FLAG_OPTION BIT(6) BIT 103 drivers/ntb/hw/amd/ntb_hw_amd.h PMM_REG_CTL = BIT(21), BIT 104 drivers/ntb/hw/amd/ntb_hw_amd.h SMM_REG_CTL = BIT(20), BIT 105 drivers/ntb/hw/amd/ntb_hw_amd.h SMM_REG_ACC_PATH = BIT(18), BIT 106 drivers/ntb/hw/amd/ntb_hw_amd.h PMM_REG_ACC_PATH = BIT(17), BIT 107 drivers/ntb/hw/amd/ntb_hw_amd.h NTB_CLK_EN = BIT(16), BIT 121 drivers/ntb/hw/amd/ntb_hw_amd.h AMD_SIDE_MASK = BIT(0), BIT 122 drivers/ntb/hw/amd/ntb_hw_amd.h AMD_SIDE_READY = BIT(1), BIT 144 drivers/ntb/hw/amd/ntb_hw_amd.h AMD_PEER_FLUSH_EVENT = BIT(0), BIT 145 drivers/ntb/hw/amd/ntb_hw_amd.h AMD_PEER_RESET_EVENT = BIT(1), BIT 146 drivers/ntb/hw/amd/ntb_hw_amd.h AMD_PEER_D3_EVENT = BIT(2), BIT 147 drivers/ntb/hw/amd/ntb_hw_amd.h AMD_PEER_PMETO_EVENT = BIT(3), BIT 148 drivers/ntb/hw/amd/ntb_hw_amd.h AMD_PEER_D0_EVENT = BIT(4), BIT 149 drivers/ntb/hw/amd/ntb_hw_amd.h AMD_LINK_UP_EVENT = BIT(5), BIT 150 drivers/ntb/hw/amd/ntb_hw_amd.h AMD_LINK_DOWN_EVENT = BIT(6), BIT 644 drivers/ntb/hw/idt/ntb_hw_idt.c port_mask = ~BIT(ndev->port); BIT 645 drivers/ntb/hw/idt/ntb_hw_idt.c part_mask = ~BIT(ndev->part); BIT 647 drivers/ntb/hw/idt/ntb_hw_idt.c port_mask &= ~BIT(ndev->peers[pidx].port); BIT 648 drivers/ntb/hw/idt/ntb_hw_idt.c part_mask &= ~BIT(ndev->peers[pidx].part); BIT 77 drivers/ntb/hw/intel/ntb_hw_intel.h #define NTB_CTL_CFG_LOCK BIT(0) BIT 78 drivers/ntb/hw/intel/ntb_hw_intel.h #define NTB_CTL_DISABLE BIT(1) BIT 79 drivers/ntb/hw/intel/ntb_hw_intel.h #define NTB_CTL_S2P_BAR2_SNOOP BIT(2) BIT 80 drivers/ntb/hw/intel/ntb_hw_intel.h #define NTB_CTL_P2S_BAR2_SNOOP BIT(4) BIT 81 drivers/ntb/hw/intel/ntb_hw_intel.h #define NTB_CTL_S2P_BAR4_SNOOP BIT(6) BIT 82 drivers/ntb/hw/intel/ntb_hw_intel.h #define NTB_CTL_P2S_BAR4_SNOOP BIT(8) BIT 83 drivers/ntb/hw/intel/ntb_hw_intel.h #define NTB_CTL_S2P_BAR5_SNOOP BIT(12) BIT 84 drivers/ntb/hw/intel/ntb_hw_intel.h #define NTB_CTL_P2S_BAR5_SNOOP BIT(14) BIT 247 drivers/ntb/ntb_transport.c DESC_DONE_FLAG = BIT(0), BIT 248 drivers/ntb/ntb_transport.c LINK_DOWN_FLAG = BIT(1), BIT 1137 drivers/ntb/ntb_transport.c ntb_peer_spad_write(nt->ndev, PIDX, QP_LINKS, val | BIT(qp->qp_num)); BIT 1143 drivers/ntb/ntb_transport.c if (val & BIT(qp->qp_num)) { BIT 2344 drivers/ntb/ntb_transport.c ntb_peer_spad_write(qp->ndev, PIDX, QP_LINKS, val & ~BIT(qp->qp_num)); BIT 101 drivers/ntb/test/ntb_msi_test.c ntb_peer_db_set(nm->ntb, BIT(ntb_port_number(nm->ntb))); BIT 118 drivers/ntb/test/ntb_msi_test.c ntb_peer_db_set(nm->ntb, BIT(ntb_port_number(nm->ntb))); BIT 160 drivers/ntb/test/ntb_msi_test.c if (!(peer_mask & BIT(peer))) BIT 500 drivers/ntb/test/ntb_tool.c if (ntb_link_is_up(tc->ntb, NULL, NULL) & BIT(peer->pidx)) BIT 657 drivers/nvdimm/region_devs.c if ((nd_region->flags & (BIT(ND_REGION_PERSIST_CACHE) BIT 658 drivers/nvdimm/region_devs.c | BIT(ND_REGION_PERSIST_MEMCTRL))) == 0) BIT 41 drivers/nvmem/bcm-ocotp.c #define OTPC_STAT_CMD_DONE BIT(1) BIT 42 drivers/nvmem/bcm-ocotp.c #define OTPC_STAT_PROG_OK BIT(2) BIT 56 drivers/nvmem/bcm-ocotp.c #define OTPC_CMD_MASK (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1) BIT 57 drivers/nvmem/bcm-ocotp.c #define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1) BIT 281 drivers/nvmem/bcm-ocotp.c BIT(OTPC_MODE_REG_OTPC_MODE), BIT 30 drivers/nvmem/lpc18xx_eeprom.c #define LPC18XX_EEPROM_INTSTAT_END_OF_PROG BIT(2) BIT 33 drivers/nvmem/lpc18xx_eeprom.c #define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST BIT(2) BIT 23 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL1_PD_ENABLE BIT(27) BIT 24 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY BIT(26) BIT 25 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL1_AUTO_RD_START BIT(25) BIT 26 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE BIT(24) BIT 28 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL1_AUTO_WR_BUSY BIT(14) BIT 29 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL1_AUTO_WR_START BIT(13) BIT 30 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL1_AUTO_WR_ENABLE BIT(12) BIT 31 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET BIT(11) BIT 37 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE BIT(10) BIT 23 drivers/nvmem/mxs-ocotp.c #define BM_OCOTP_CTRL_RD_BANK_OPEN BIT(12) BIT 24 drivers/nvmem/mxs-ocotp.c #define BM_OCOTP_CTRL_ERROR BIT(9) BIT 25 drivers/nvmem/mxs-ocotp.c #define BM_OCOTP_CTRL_BUSY BIT(8) BIT 33 drivers/nvmem/nvmem.h #define FLAG_COMPAT BIT(0) BIT 22 drivers/nvmem/rockchip-efuse.c #define RK3288_PGENB BIT(3) BIT 23 drivers/nvmem/rockchip-efuse.c #define RK3288_LOAD BIT(2) BIT 24 drivers/nvmem/rockchip-efuse.c #define RK3288_STROBE BIT(1) BIT 25 drivers/nvmem/rockchip-efuse.c #define RK3288_CSB BIT(0) BIT 31 drivers/nvmem/rockchip-efuse.c #define RK3328_INT_FINISH BIT(0) BIT 32 drivers/nvmem/rockchip-efuse.c #define RK3328_AUTO_ENB BIT(0) BIT 33 drivers/nvmem/rockchip-efuse.c #define RK3328_AUTO_RD BIT(1) BIT 38 drivers/nvmem/rockchip-efuse.c #define RK3399_STROBSFTSEL BIT(9) BIT 39 drivers/nvmem/rockchip-efuse.c #define RK3399_RSB BIT(7) BIT 40 drivers/nvmem/rockchip-efuse.c #define RK3399_PD BIT(5) BIT 41 drivers/nvmem/rockchip-efuse.c #define RK3399_PGENB BIT(3) BIT 42 drivers/nvmem/rockchip-efuse.c #define RK3399_LOAD BIT(2) BIT 43 drivers/nvmem/rockchip-efuse.c #define RK3399_STROBE BIT(1) BIT 44 drivers/nvmem/rockchip-efuse.c #define RK3399_CSB BIT(0) BIT 13 drivers/nvmem/sc27xx-efuse.c #define SC27XX_EFUSE_EN BIT(6) BIT 30 drivers/nvmem/sc27xx-efuse.c #define SC27XX_EFUSE_PG_START BIT(0) BIT 31 drivers/nvmem/sc27xx-efuse.c #define SC27XX_EFUSE_RD_START BIT(1) BIT 32 drivers/nvmem/sc27xx-efuse.c #define SC27XX_EFUSE_CLR_RDDONE BIT(2) BIT 35 drivers/nvmem/sc27xx-efuse.c #define SC27XX_EFUSE_PGM_BUSY BIT(0) BIT 36 drivers/nvmem/sc27xx-efuse.c #define SC27XX_EFUSE_READ_BUSY BIT(1) BIT 37 drivers/nvmem/sc27xx-efuse.c #define SC27XX_EFUSE_STANDBY BIT(2) BIT 38 drivers/nvmem/sc27xx-efuse.c #define SC27XX_EFUSE_GLOBAL_PROT BIT(3) BIT 39 drivers/nvmem/sc27xx-efuse.c #define SC27XX_EFUSE_RD_DONE BIT(4) BIT 21 drivers/nvmem/snvs_lpgpr.c #define IMX_GPR_SL BIT(5) BIT 22 drivers/nvmem/snvs_lpgpr.c #define IMX_GPR_HL BIT(5) BIT 27 drivers/nvmem/sunxi_sid.c #define SUN8I_SID_READ BIT(1) BIT 37 drivers/nvmem/vf610-ocotp.c #define OCOTP_CTRL_RELOAD_SHADOWS BIT(10) BIT 38 drivers/nvmem/vf610-ocotp.c #define OCOTP_CTRL_ERR BIT(9) BIT 39 drivers/nvmem/vf610-ocotp.c #define OCOTP_CTRL_BUSY BIT(8) BIT 56 drivers/opp/ti-opp-supply.c #define OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE BIT(1) BIT 57 drivers/opp/ti-opp-supply.c #define OPPDM_HAS_NO_ABB BIT(2) BIT 38 drivers/pci/controller/dwc/pci-dra7xx.c #define ERR_SYS BIT(0) BIT 39 drivers/pci/controller/dwc/pci-dra7xx.c #define ERR_FATAL BIT(1) BIT 40 drivers/pci/controller/dwc/pci-dra7xx.c #define ERR_NONFATAL BIT(2) BIT 41 drivers/pci/controller/dwc/pci-dra7xx.c #define ERR_COR BIT(3) BIT 42 drivers/pci/controller/dwc/pci-dra7xx.c #define ERR_AXI BIT(4) BIT 43 drivers/pci/controller/dwc/pci-dra7xx.c #define ERR_ECRC BIT(5) BIT 44 drivers/pci/controller/dwc/pci-dra7xx.c #define PME_TURN_OFF BIT(8) BIT 45 drivers/pci/controller/dwc/pci-dra7xx.c #define PME_TO_ACK BIT(9) BIT 46 drivers/pci/controller/dwc/pci-dra7xx.c #define PM_PME BIT(10) BIT 47 drivers/pci/controller/dwc/pci-dra7xx.c #define LINK_REQ_RST BIT(11) BIT 48 drivers/pci/controller/dwc/pci-dra7xx.c #define LINK_UP_EVT BIT(12) BIT 49 drivers/pci/controller/dwc/pci-dra7xx.c #define CFG_BME_EVT BIT(13) BIT 50 drivers/pci/controller/dwc/pci-dra7xx.c #define CFG_MSE_EVT BIT(14) BIT 57 drivers/pci/controller/dwc/pci-dra7xx.c #define INTA BIT(0) BIT 58 drivers/pci/controller/dwc/pci-dra7xx.c #define INTB BIT(1) BIT 59 drivers/pci/controller/dwc/pci-dra7xx.c #define INTC BIT(2) BIT 60 drivers/pci/controller/dwc/pci-dra7xx.c #define INTD BIT(3) BIT 61 drivers/pci/controller/dwc/pci-dra7xx.c #define MSI BIT(4) BIT 73 drivers/pci/controller/dwc/pci-dra7xx.c #define LINK_UP BIT(16) BIT 82 drivers/pci/controller/dwc/pci-dra7xx.c #define MSI_REQ_GRANT BIT(0) BIT 85 drivers/pci/controller/dwc/pci-dra7xx.c #define PCIE_1LANE_2LANE_SELECTION BIT(13) BIT 86 drivers/pci/controller/dwc/pci-dra7xx.c #define PCIE_B1C0_MODE_SEL BIT(2) BIT 87 drivers/pci/controller/dwc/pci-dra7xx.c #define PCIE_B0_B1_TSYNCEN BIT(0) BIT 557 drivers/pci/controller/dwc/pci-dra7xx.c .b1co_mode_sel_mask = BIT(2), BIT 567 drivers/pci/controller/dwc/pci-dra7xx.c .b1co_mode_sel_mask = BIT(2), BIT 32 drivers/pci/controller/dwc/pci-exynos.c #define IRQ_INTA_ASSERT BIT(0) BIT 33 drivers/pci/controller/dwc/pci-exynos.c #define IRQ_INTB_ASSERT BIT(2) BIT 34 drivers/pci/controller/dwc/pci-exynos.c #define IRQ_INTC_ASSERT BIT(4) BIT 35 drivers/pci/controller/dwc/pci-exynos.c #define IRQ_INTD_ASSERT BIT(6) BIT 40 drivers/pci/controller/dwc/pci-exynos.c #define IRQ_MSI_ENABLE BIT(2) BIT 44 drivers/pci/controller/dwc/pci-exynos.c #define PCIE_CORE_RESET_ENABLE BIT(0) BIT 53 drivers/pci/controller/dwc/pci-exynos.c #define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) BIT 37 drivers/pci/controller/dwc/pci-imx6.c #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) BIT 38 drivers/pci/controller/dwc/pci-imx6.c #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) BIT 39 drivers/pci/controller/dwc/pci-imx6.c #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) BIT 53 drivers/pci/controller/dwc/pci-imx6.c #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) BIT 54 drivers/pci/controller/dwc/pci-imx6.c #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) BIT 55 drivers/pci/controller/dwc/pci-imx6.c #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) BIT 111 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_CTRL_CAP_ADR BIT(16) BIT 112 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_CTRL_CAP_DAT BIT(17) BIT 113 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_CTRL_WR BIT(18) BIT 114 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_CTRL_RD BIT(19) BIT 117 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_STAT_ACK BIT(16) BIT 123 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_ATEOVRD_EN BIT(2) BIT 130 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9) BIT 141 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2) BIT 142 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5) BIT 143 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7) BIT 146 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6) BIT 147 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3) BIT 153 drivers/pci/controller/dwc/pci-imx6.c #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) BIT 154 drivers/pci/controller/dwc/pci-imx6.c #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) BIT 39 drivers/pci/controller/dwc/pci-keystone.c #define LTSSM_EN_VAL BIT(0) BIT 40 drivers/pci/controller/dwc/pci-keystone.c #define OB_XLAT_EN_VAL BIT(1) BIT 41 drivers/pci/controller/dwc/pci-keystone.c #define DBI_CS2 BIT(5) BIT 47 drivers/pci/controller/dwc/pci-keystone.c #define CFG_TYPE1 BIT(24) BIT 52 drivers/pci/controller/dwc/pci-keystone.c #define OB_ENABLEN BIT(0) BIT 59 drivers/pci/controller/dwc/pci-keystone.c #define INT_ENABLE BIT(0) BIT 72 drivers/pci/controller/dwc/pci-keystone.c #define INTx_EN BIT(0) BIT 76 drivers/pci/controller/dwc/pci-keystone.c #define ERR_AER BIT(5) /* ECRC error */ BIT 77 drivers/pci/controller/dwc/pci-keystone.c #define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ BIT 78 drivers/pci/controller/dwc/pci-keystone.c #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ BIT 79 drivers/pci/controller/dwc/pci-keystone.c #define ERR_CORR BIT(3) /* Correctable error */ BIT 80 drivers/pci/controller/dwc/pci-keystone.c #define ERR_NONFATAL BIT(2) /* Non-fatal error */ BIT 81 drivers/pci/controller/dwc/pci-keystone.c #define ERR_FATAL BIT(1) /* Fatal error */ BIT 82 drivers/pci/controller/dwc/pci-keystone.c #define ERR_SYS BIT(0) /* System error */ BIT 101 drivers/pci/controller/dwc/pci-keystone.c #define KS_PCIE_SYSCLOCKOUTEN BIT(0) BIT 166 drivers/pci/controller/dwc/pci-keystone.c BIT(bit_pos)); BIT 214 drivers/pci/controller/dwc/pci-keystone.c BIT(bit_pos)); BIT 238 drivers/pci/controller/dwc/pci-keystone.c BIT(bit_pos)); BIT 268 drivers/pci/controller/dwc/pci-keystone.c if (BIT(0) & pending) { BIT 603 drivers/pci/controller/dwc/pci-keystone.c if (!(reg & BIT(pos))) BIT 27 drivers/pci/controller/dwc/pci-meson.c #define FAST_LINK_MODE BIT(7) BIT 29 drivers/pci/controller/dwc/pci-meson.c #define LINK_CAPABLE_X1 BIT(16) BIT 33 drivers/pci/controller/dwc/pci-meson.c #define NUM_OF_LANES_X1 BIT(8) BIT 34 drivers/pci/controller/dwc/pci-meson.c #define DIRECT_SPEED_CHANGE BIT(17) BIT 38 drivers/pci/controller/dwc/pci-meson.c #define PCI_IO_EN BIT(0) BIT 39 drivers/pci/controller/dwc/pci-meson.c #define PCI_MEM_SPACE_EN BIT(1) BIT 40 drivers/pci/controller/dwc/pci-meson.c #define PCI_BUS_MASTER_EN BIT(2) BIT 54 drivers/pci/controller/dwc/pci-meson.c #define APP_LTSSM_ENABLE BIT(7) BIT 41 drivers/pci/controller/dwc/pcie-armada8k.c #define PCIE_APP_LTSSM_EN BIT(2) BIT 47 drivers/pci/controller/dwc/pcie-armada8k.c #define PCIE_GLB_STS_RDLH_LINK_UP BIT(1) BIT 48 drivers/pci/controller/dwc/pcie-armada8k.c #define PCIE_GLB_STS_PHY_LINK_UP BIT(9) BIT 52 drivers/pci/controller/dwc/pcie-armada8k.c #define PCIE_INT_A_ASSERT_MASK BIT(9) BIT 53 drivers/pci/controller/dwc/pcie-armada8k.c #define PCIE_INT_B_ASSERT_MASK BIT(10) BIT 54 drivers/pci/controller/dwc/pcie-armada8k.c #define PCIE_INT_C_ASSERT_MASK BIT(11) BIT 55 drivers/pci/controller/dwc/pcie-armada8k.c #define PCIE_INT_D_ASSERT_MASK BIT(12) BIT 59 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_DBG_OEN BIT(24) BIT 60 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_CORE_RESET_REQ BIT(21) BIT 61 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_LTSSM_ENABLE BIT(20) BIT 63 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_CLKREQ_B BIT(11) BIT 64 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_REFCLK_ENABLE BIT(10) BIT 65 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_PLL_ENABLE BIT(9) BIT 66 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_PCLK_ENABLE BIT(8) BIT 67 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_RISRCREN BIT(4) BIT 68 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_MODE_TX_DRV_EN BIT(3) BIT 69 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_CISRREN BIT(2) BIT 70 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_MACRO_ENABLE BIT(0) BIT 72 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_REFCLKSEL BIT(23) BIT 73 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIECFG_NOC_RESET BIT(3) BIT 77 drivers/pci/controller/dwc/pcie-artpec6.c #define PCIESTAT_EXTREFCLK BIT(3) BIT 80 drivers/pci/controller/dwc/pcie-artpec6.c #define NOCCFG_ENABLE_CLK_PCIE BIT(4) BIT 81 drivers/pci/controller/dwc/pcie-artpec6.c #define NOCCFG_POWER_PCIE_IDLEACK BIT(3) BIT 82 drivers/pci/controller/dwc/pcie-artpec6.c #define NOCCFG_POWER_PCIE_IDLE BIT(2) BIT 83 drivers/pci/controller/dwc/pcie-artpec6.c #define NOCCFG_POWER_PCIE_IDLEREQ BIT(1) BIT 86 drivers/pci/controller/dwc/pcie-artpec6.c #define PHY_COSPLLLOCK BIT(0) BIT 89 drivers/pci/controller/dwc/pcie-artpec6.c #define PHY_TX_ASIC_OUT_TX_ACK BIT(0) BIT 92 drivers/pci/controller/dwc/pcie-artpec6.c #define PHY_RX_ASIC_OUT_ACK BIT(0) BIT 159 drivers/pci/controller/dwc/pcie-designware-host.c pp->irq_mask[ctrl] |= BIT(bit); BIT 178 drivers/pci/controller/dwc/pcie-designware-host.c pp->irq_mask[ctrl] &= ~BIT(bit); BIT 194 drivers/pci/controller/dwc/pcie-designware-host.c dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit)); BIT 45 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_PORT_DEBUG1_LINK_UP BIT(4) BIT 46 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29) BIT 49 drivers/pci/controller/dwc/pcie-designware.h #define PORT_LOGIC_SPEED_CHANGE BIT(17) BIT 64 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_ATU_REGION_INBOUND BIT(31) BIT 75 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_ATU_ENABLE BIT(31) BIT 76 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) BIT 87 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_DBI_RO_WR_EN BIT(0) BIT 90 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_PL_CHK_REG_CHK_REG_START BIT(0) BIT 91 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1) BIT 92 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16) BIT 93 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17) BIT 94 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18) BIT 123 drivers/pci/controller/dwc/pcie-designware.h (((region) << 9) | BIT(8)) BIT 39 drivers/pci/controller/dwc/pcie-histb.c #define PCIE_RDLH_LINK_UP BIT(5) BIT 40 drivers/pci/controller/dwc/pcie-histb.c #define PCIE_XMLH_LINK_UP BIT(15) BIT 41 drivers/pci/controller/dwc/pcie-histb.c #define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) BIT 42 drivers/pci/controller/dwc/pcie-histb.c #define PCIE_APP_LTSSM_ENABLE BIT(11) BIT 46 drivers/pci/controller/dwc/pcie-histb.c #define PCIE_WM_LEGACY BIT(1) BIT 47 drivers/pci/controller/dwc/pcie-histb.c #define PCIE_WM_RC BIT(30) BIT 33 drivers/pci/controller/dwc/pcie-qcom.c #define MST_WAKEUP_EN BIT(13) BIT 34 drivers/pci/controller/dwc/pcie-qcom.c #define SLV_WAKEUP_EN BIT(12) BIT 35 drivers/pci/controller/dwc/pcie-qcom.c #define MSTR_ACLK_CGC_DIS BIT(10) BIT 36 drivers/pci/controller/dwc/pcie-qcom.c #define SLV_ACLK_CGC_DIS BIT(9) BIT 37 drivers/pci/controller/dwc/pcie-qcom.c #define CORE_CLK_CGC_DIS BIT(6) BIT 38 drivers/pci/controller/dwc/pcie-qcom.c #define AUX_PWR_DET BIT(4) BIT 39 drivers/pci/controller/dwc/pcie-qcom.c #define L23_CLK_RMV_DIS BIT(2) BIT 40 drivers/pci/controller/dwc/pcie-qcom.c #define L1_CLK_RMV_DIS BIT(1) BIT 59 drivers/pci/controller/dwc/pcie-qcom.c #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) BIT 65 drivers/pci/controller/dwc/pcie-qcom.c #define CFG_BRIDGE_SB_INIT BIT(0) BIT 69 drivers/pci/controller/dwc/pcie-qcom.c #define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11)) BIT 319 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(0); BIT 324 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(16); BIT 466 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(31); BIT 491 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(8); BIT 588 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(0); BIT 596 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(29); BIT 600 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(4); BIT 604 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(31); BIT 869 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(0); BIT 877 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(29); BIT 881 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(4); BIT 885 drivers/pci/controller/dwc/pcie-qcom.c val |= BIT(31); BIT 1028 drivers/pci/controller/dwc/pcie-qcom.c val &= ~BIT(0); BIT 38 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_PINMUX_PEX_RST BIT(0) BIT 39 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2) BIT 40 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) BIT 41 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) BIT 42 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) BIT 43 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_PINMUX_CLKREQ_OUT_OVRD_EN BIT(9) BIT 44 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_PINMUX_CLKREQ_OUT_OVRD BIT(10) BIT 47 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) BIT 48 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_CTRL_LTSSM_EN BIT(7) BIT 49 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_CTRL_HW_HOT_RST_EN BIT(20) BIT 55 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L0_0_LINK_STATE_INT_EN BIT(0) BIT 56 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L0_0_MSI_RCV_INT_EN BIT(4) BIT 57 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L0_0_INT_INT_EN BIT(8) BIT 58 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN BIT(19) BIT 59 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L0_0_SYS_INTR_EN BIT(30) BIT 60 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN BIT(31) BIT 63 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_STATUS_L0_LINK_STATE_INT BIT(0) BIT 64 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_STATUS_L0_INT_INT BIT(8) BIT 65 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_STATUS_L0_CDM_REG_CHK_INT BIT(18) BIT 68 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1) BIT 71 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1) BIT 80 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2) BIT 81 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3) BIT 82 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L1_8_INTX_EN BIT(11) BIT 83 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15) BIT 87 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS BIT(2) BIT 88 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS BIT(3) BIT 99 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMPLT BIT(2) BIT 100 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1) BIT 101 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0) BIT 104 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT BIT(2) BIT 105 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR BIT(1) BIT 106 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0) BIT 111 drivers/pci/controller/dwc/pcie-tegra194.c #define LTR_MSG_REQ BIT(15) BIT 115 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_LTR_MSG_2_LTR_MSG_REQ_STATE BIT(3) BIT 118 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_LINK_STATUS_RDLH_LINK_UP BIT(0) BIT 121 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21) BIT 128 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_PM_XMT_TURNOFF_STATE BIT(0) BIT 142 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_CFG_MISC_SLV_EP_MODE BIT(14) BIT 148 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_CFG_SLCG_OVERRIDE_SLCG_EN_MASTER BIT(0) BIT 151 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N BIT(0) BIT 153 drivers/pci/controller/dwc/pcie-tegra194.c #define IO_BASE_IO_DECODE BIT(0) BIT 154 drivers/pci/controller/dwc/pcie-tegra194.c #define IO_BASE_IO_DECODE_BIT8 BIT(8) BIT 156 drivers/pci/controller/dwc/pcie-tegra194.c #define CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE BIT(0) BIT 157 drivers/pci/controller/dwc/pcie-tegra194.c #define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16) BIT 176 drivers/pci/controller/dwc/pcie-tegra194.c #define ENTER_ASPM BIT(30) BIT 186 drivers/pci/controller/dwc/pcie-tegra194.c #define PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE BIT(17) BIT 198 drivers/pci/controller/dwc/pcie-tegra194.c #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) BIT 199 drivers/pci/controller/dwc/pcie-tegra194.c #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) BIT 26 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_PERST_PLDN_REGEN BIT(12) BIT 27 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_PERST_NOE_REGEN BIT(11) BIT 28 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_PERST_OUT_REGEN BIT(8) BIT 29 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_PERST_PLDN_REGVAL BIT(4) BIT 30 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_PERST_NOE_REGVAL BIT(3) BIT 31 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_PERST_OUT_REGVAL BIT(0) BIT 34 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_PCLK_ALIVE BIT(15) BIT 37 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_APP_LTSSM_ENABLE BIT(0) BIT 40 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_SYS_AUX_PWR_DET BIT(8) BIT 44 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_CFG_BW_MGT_STATUS BIT(4) BIT 45 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3) BIT 46 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2) BIT 47 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_CFG_PME_MSI_STATUS BIT(1) BIT 57 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_RDLH_LINK_UP BIT(1) BIT 58 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_XMLH_LINK_UP BIT(0) BIT 179 drivers/pci/controller/dwc/pcie-uniphier.c val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT); BIT 192 drivers/pci/controller/dwc/pcie-uniphier.c val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); BIT 205 drivers/pci/controller/dwc/pcie-uniphier.c val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); BIT 28 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) BIT 29 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) BIT 30 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) BIT 40 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) BIT 41 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_LINK_TRAINING BIT(5) BIT 44 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) BIT 45 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) BIT 46 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) BIT 47 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) BIT 56 drivers/pci/controller/pci-aardvark.c #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) BIT 64 drivers/pci/controller/pci-aardvark.c #define PIO_NON_POSTED_REQ BIT(0) BIT 90 drivers/pci/controller/pci-aardvark.c #define LINK_TRAINING_EN BIT(6) BIT 91 drivers/pci/controller/pci-aardvark.c #define LEGACY_INTA BIT(28) BIT 92 drivers/pci/controller/pci-aardvark.c #define LEGACY_INTB BIT(29) BIT 93 drivers/pci/controller/pci-aardvark.c #define LEGACY_INTC BIT(30) BIT 94 drivers/pci/controller/pci-aardvark.c #define LEGACY_INTD BIT(31) BIT 96 drivers/pci/controller/pci-aardvark.c #define HOT_RESET_GEN BIT(0) BIT 99 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) BIT 100 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) BIT 101 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) BIT 102 drivers/pci/controller/pci-aardvark.c #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) BIT 105 drivers/pci/controller/pci-aardvark.c #define PCIE_MSG_PM_PME_MASK BIT(7) BIT 107 drivers/pci/controller/pci-aardvark.c #define PCIE_ISR0_MSI_INT_PENDING BIT(24) BIT 108 drivers/pci/controller/pci-aardvark.c #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) BIT 109 drivers/pci/controller/pci-aardvark.c #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) BIT 113 drivers/pci/controller/pci-aardvark.c #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) BIT 114 drivers/pci/controller/pci-aardvark.c #define PCIE_ISR1_FLUSH BIT(5) BIT 115 drivers/pci/controller/pci-aardvark.c #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) BIT 143 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_CMDQ_INT BIT(0) BIT 144 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_MSI_STATUS_INT BIT(1) BIT 145 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_CMD_SENT_DONE BIT(3) BIT 146 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_DMA_INT BIT(4) BIT 147 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_IB_DXFERDONE BIT(5) BIT 148 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_OB_DXFERDONE BIT(6) BIT 149 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_OB_RXFERDONE BIT(7) BIT 150 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_COMPQ_INT BIT(12) BIT 151 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) BIT 152 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) BIT 153 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_CORE_INT BIT(16) BIT 154 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_CORE_INT_PIO BIT(17) BIT 155 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_DPMU_INT BIT(18) BIT 156 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_PCIE_MIS_INT BIT(19) BIT 157 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_MSI_INT1_DET BIT(20) BIT 158 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_MSI_INT2_DET BIT(21) BIT 159 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_RC_DBELL_DET BIT(22) BIT 160 drivers/pci/controller/pci-aardvark.c #define PCIE_IRQ_EP_STATUS BIT(23) BIT 879 drivers/pci/controller/pci-aardvark.c if (!(BIT(msi_idx) & msi_status)) BIT 882 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); BIT 53 drivers/pci/controller/pci-ftpci100.c #define PCI_STATUS_66MHZ_CAPABLE BIT(21) BIT 57 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_INTMASK_CMDERR BIT(27) BIT 58 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_INTMASK_PARERR BIT(26) BIT 61 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_INTMASK_MABRT_RX BIT(21) BIT 62 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_INTMASK_TABRT_RX BIT(20) BIT 63 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_INTMASK_TABRT_TX BIT(19) BIT 64 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_INTMASK_RETRY4 BIT(18) BIT 65 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_INTMASK_SERR_RX BIT(17) BIT 66 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_INTMASK_PERR_RX BIT(16) BIT 68 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_MSTPRI_REQ6 BIT(14) BIT 69 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_MSTPRI_REQ5 BIT(13) BIT 70 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_MSTPRI_REQ4 BIT(12) BIT 71 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_MSTPRI_REQ3 BIT(11) BIT 72 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_MSTPRI_REQ2 BIT(10) BIT 73 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_MSTPRI_REQ1 BIT(9) BIT 74 drivers/pci/controller/pci-ftpci100.c #define PCI_CTRL2_MSTPRI_REQ0 BIT(8) BIT 107 drivers/pci/controller/pci-ftpci100.c #define PCI_CONF_ENABLE BIT(31) BIT 277 drivers/pci/controller/pci-ftpci100.c reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT); BIT 288 drivers/pci/controller/pci-ftpci100.c | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT)); BIT 299 drivers/pci/controller/pci-ftpci100.c reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT); BIT 315 drivers/pci/controller/pci-ftpci100.c if ((irq_stat & BIT(i)) == 0) BIT 62 drivers/pci/controller/pci-mvebu.c #define PCIE_STAT_LINK_DOWN BIT(0) BIT 65 drivers/pci/controller/pci-mvebu.c #define PCIE_DEBUG_SOFT_RESET BIT(20) BIT 92 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_STAT_PAR_ERR BIT(15) BIT 93 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_STAT_SYS_ERR BIT(14) BIT 94 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_STAT_M_ABORT_ERR BIT(13) BIT 95 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_STAT_T_ABORT_ERR BIT(12) BIT 98 drivers/pci/controller/pci-v3-semi.c #define V3_LB_ISTAT_MAILBOX BIT(7) BIT 99 drivers/pci/controller/pci-v3-semi.c #define V3_LB_ISTAT_PCI_RD BIT(6) BIT 100 drivers/pci/controller/pci-v3-semi.c #define V3_LB_ISTAT_PCI_WR BIT(5) BIT 101 drivers/pci/controller/pci-v3-semi.c #define V3_LB_ISTAT_PCI_INT BIT(4) BIT 102 drivers/pci/controller/pci-v3-semi.c #define V3_LB_ISTAT_PCI_PERR BIT(3) BIT 103 drivers/pci/controller/pci-v3-semi.c #define V3_LB_ISTAT_I2O_QWR BIT(2) BIT 104 drivers/pci/controller/pci-v3-semi.c #define V3_LB_ISTAT_DMA1 BIT(1) BIT 105 drivers/pci/controller/pci-v3-semi.c #define V3_LB_ISTAT_DMA0 BIT(0) BIT 108 drivers/pci/controller/pci-v3-semi.c #define V3_COMMAND_M_FBB_EN BIT(9) BIT 109 drivers/pci/controller/pci-v3-semi.c #define V3_COMMAND_M_SERR_EN BIT(8) BIT 110 drivers/pci/controller/pci-v3-semi.c #define V3_COMMAND_M_PAR_EN BIT(6) BIT 111 drivers/pci/controller/pci-v3-semi.c #define V3_COMMAND_M_MASTER_EN BIT(2) BIT 112 drivers/pci/controller/pci-v3-semi.c #define V3_COMMAND_M_MEM_EN BIT(1) BIT 113 drivers/pci/controller/pci-v3-semi.c #define V3_COMMAND_M_IO_EN BIT(0) BIT 116 drivers/pci/controller/pci-v3-semi.c #define V3_SYSTEM_M_RST_OUT BIT(15) BIT 117 drivers/pci/controller/pci-v3-semi.c #define V3_SYSTEM_M_LOCK BIT(14) BIT 121 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_CFG_M_I2O_EN BIT(15) BIT 122 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_CFG_M_IO_REG_DIS BIT(14) BIT 123 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_CFG_M_IO_DIS BIT(13) BIT 124 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_CFG_M_EN3V BIT(12) BIT 125 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_CFG_M_RETRY_EN BIT(10) BIT 126 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_CFG_M_AD_LOW1 BIT(9) BIT 127 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_CFG_M_AD_LOW0 BIT(8) BIT 139 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_BASE_M_PREFETCH BIT(3) BIT 141 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_BASE_M_IO BIT(0) BIT 145 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_MAP_M_RD_POST_INH BIT(15) BIT 149 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_MAP_M_REG_EN BIT(1) BIT 150 drivers/pci/controller/pci-v3-semi.c #define V3_PCI_MAP_M_ENABLE BIT(0) BIT 156 drivers/pci/controller/pci-v3-semi.c #define V3_LB_BASE_PREFETCH BIT(3) BIT 157 drivers/pci/controller/pci-v3-semi.c #define V3_LB_BASE_ENABLE BIT(0) BIT 177 drivers/pci/controller/pci-v3-semi.c #define V3_LB_MAP_AD_LOW_EN BIT(0) BIT 190 drivers/pci/controller/pci-v3-semi.c #define V3_LB_BASE2_ENABLE BIT(0) BIT 200 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_LOCAL BIT(12) BIT 201 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_LB_RD1_FLUSH_EOB BIT(10) BIT 202 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 BIT(11) BIT 203 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_LB_RD1_FLUSH_ANY (BIT(10)|BIT(11)) BIT 204 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_LB_RD0_FLUSH_EOB BIT(8) BIT 205 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 BIT(9) BIT 206 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_LB_RD0_FLUSH_ANY (BIT(8)|BIT(9)) BIT 207 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_PCI BIT(4) BIT 208 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB BIT(2) BIT 209 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 BIT(3) BIT 210 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY (BIT(2)|BIT(3)) BIT 211 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB BIT(0) BIT 212 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1 BIT(1) BIT 213 drivers/pci/controller/pci-v3-semi.c #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY (BIT(0)|BIT(1)) BIT 217 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_TO_256_CYCLES BIT(13) BIT 218 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_TO_512_CYCLES BIT(14) BIT 219 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_TO_1024_CYCLES (BIT(13)|BIT(14)) BIT 220 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_RST BIT(12) BIT 221 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_PPC_RDY BIT(11) BIT 222 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_LB_INT BIT(10) BIT 223 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_ERR_EN BIT(9) BIT 224 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_RDY_EN BIT(8) BIT 225 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_BE_IMODE BIT(7) BIT 226 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_BE_OMODE BIT(6) BIT 227 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_ENDIAN BIT(5) BIT 228 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_PARK_EN BIT(4) BIT 229 drivers/pci/controller/pci-v3-semi.c #define V3_LB_CFG_LB_FBB_DIS BIT(2) BIT 233 drivers/pci/controller/pci-v3-semi.c #define INTEGRATOR_SC_PCI_ENABLE BIT(0) BIT 234 drivers/pci/controller/pci-v3-semi.c #define INTEGRATOR_SC_PCI_INTCLR BIT(1) BIT 342 drivers/pci/controller/pci-v3-semi.c mapaddress |= BIT(slot - 5); BIT 347 drivers/pci/controller/pci-v3-semi.c address |= BIT(slot + 11); BIT 278 drivers/pci/controller/pcie-cadence-ep.c ep->irq_pending |= BIT(intx); BIT 281 drivers/pci/controller/pcie-cadence-ep.c ep->irq_pending &= ~BIT(intx); BIT 394 drivers/pci/controller/pcie-cadence-ep.c cfg = BIT(0); BIT 396 drivers/pci/controller/pcie-cadence-ep.c cfg |= BIT(epf->func_no); BIT 491 drivers/pci/controller/pcie-cadence-ep.c cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0)); BIT 74 drivers/pci/controller/pcie-cadence.h #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) BIT 76 drivers/pci/controller/pcie-cadence.h #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) BIT 77 drivers/pci/controller/pcie-cadence.h #define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) BIT 79 drivers/pci/controller/pcie-cadence.h #define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) BIT 80 drivers/pci/controller/pcie-cadence.h #define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) BIT 137 drivers/pci/controller/pcie-cadence.h #define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) BIT 191 drivers/pci/controller/pcie-cadence.h #define CDNS_PCIE_MSG_NO_DATA BIT(16) BIT 17 drivers/pci/controller/pcie-iproc-msi.c #define IPROC_MSI_INTR_EN BIT(IPROC_MSI_INTR_EN_SHIFT) BIT 19 drivers/pci/controller/pcie-iproc-msi.c #define IPROC_MSI_INT_N_EVENT BIT(IPROC_MSI_INT_N_EVENT_SHIFT) BIT 21 drivers/pci/controller/pcie-iproc-msi.c #define IPROC_MSI_EQ_EN BIT(IPROC_MSI_EQ_EN_SHIFT) BIT 414 drivers/pci/controller/pcie-iproc-msi.c val |= BIT(eq); BIT 427 drivers/pci/controller/pcie-iproc-msi.c val &= ~BIT(eq); BIT 27 drivers/pci/controller/pcie-iproc.c #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT) BIT 29 drivers/pci/controller/pcie-iproc.c #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT) BIT 31 drivers/pci/controller/pcie-iproc.c #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT) BIT 35 drivers/pci/controller/pcie-iproc.c #define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT) BIT 38 drivers/pci/controller/pcie-iproc.c #define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT) BIT 56 drivers/pci/controller/pcie-iproc.c #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT) BIT 58 drivers/pci/controller/pcie-iproc.c #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT) BIT 61 drivers/pci/controller/pcie-iproc.c #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT) BIT 80 drivers/pci/controller/pcie-iproc.c #define OARR_VALID BIT(OARR_VALID_SHIFT) BIT 90 drivers/pci/controller/pcie-iproc.c #define IMAP_VALID BIT(IMAP_VALID_SHIFT) BIT 1058 drivers/pci/controller/pcie-iproc.c return !!(val & (BIT(ib_map->nr_sizes) - 1)); BIT 1092 drivers/pci/controller/pcie-iproc.c writel(lower_32_bits(pci_addr) | BIT(size_idx), BIT 41 drivers/pci/controller/pcie-mediatek.c #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) BIT 42 drivers/pci/controller/pcie-mediatek.c #define PCIE_PORT_PERST(x) BIT(1 + (x)) BIT 43 drivers/pci/controller/pcie-mediatek.c #define PCIE_PORT_LINKUP BIT(0) BIT 46 drivers/pci/controller/pcie-mediatek.c #define PCIE_BAR_ENABLE BIT(0) BIT 47 drivers/pci/controller/pcie-mediatek.c #define PCIE_REVISION_ID BIT(0) BIT 69 drivers/pci/controller/pcie-mediatek.c #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8) BIT 70 drivers/pci/controller/pcie-mediatek.c #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8) BIT 83 drivers/pci/controller/pcie-mediatek.c #define MSI_STATUS BIT(23) BIT 86 drivers/pci/controller/pcie-mediatek.c #define MSI_MASK BIT(23) BIT 93 drivers/pci/controller/pcie-mediatek.c #define WIN_ENABLE BIT(7) BIT 108 drivers/pci/controller/pcie-mediatek.c #define APP_CFG_REQ BIT(0) BIT 131 drivers/pci/controller/pcie-mediatek.c #define PCIE_PHY_RSTB BIT(0) BIT 132 drivers/pci/controller/pcie-mediatek.c #define PCIE_PIPE_SRSTB BIT(1) BIT 133 drivers/pci/controller/pcie-mediatek.c #define PCIE_MAC_SRSTB BIT(2) BIT 134 drivers/pci/controller/pcie-mediatek.c #define PCIE_CRSTB BIT(3) BIT 135 drivers/pci/controller/pcie-mediatek.c #define PCIE_PERSTB BIT(8) BIT 138 drivers/pci/controller/pcie-mediatek.c #define PCIE_PORT_LINKUP_V2 BIT(10) BIT 37 drivers/pci/controller/pcie-rcar.c #define CONFIG_SEND_ENABLE BIT(31) BIT 39 drivers/pci/controller/pcie-rcar.c #define TYPE1 BIT(8) BIT 44 drivers/pci/controller/pcie-rcar.c #define PHYRDY BIT(0) BIT 49 drivers/pci/controller/pcie-rcar.c #define DL_DOWN BIT(3) BIT 50 drivers/pci/controller/pcie-rcar.c #define CFINIT BIT(0) BIT 52 drivers/pci/controller/pcie-rcar.c #define DATA_LINK_ACTIVE BIT(0) BIT 54 drivers/pci/controller/pcie-rcar.c #define UNSUPPORTED_REQUEST BIT(4) BIT 57 drivers/pci/controller/pcie-rcar.c #define MSIFE BIT(0) BIT 67 drivers/pci/controller/pcie-rcar.c #define LAM_PREFETCH BIT(3) BIT 68 drivers/pci/controller/pcie-rcar.c #define LAM_64BIT BIT(2) BIT 69 drivers/pci/controller/pcie-rcar.c #define LAR_ENABLE BIT(1) BIT 76 drivers/pci/controller/pcie-rcar.c #define PAR_ENABLE BIT(31) BIT 77 drivers/pci/controller/pcie-rcar.c #define IO_SPACE BIT(8) BIT 89 drivers/pci/controller/pcie-rcar.c #define SPCHGFIN BIT(4) BIT 90 drivers/pci/controller/pcie-rcar.c #define SPCHGFAIL BIT(6) BIT 91 drivers/pci/controller/pcie-rcar.c #define SPCHGSUC BIT(7) BIT 97 drivers/pci/controller/pcie-rcar.c #define SPEED_CHANGE BIT(24) BIT 98 drivers/pci/controller/pcie-rcar.c #define SCRAMBLE_DISABLE BIT(27) BIT 99 drivers/pci/controller/pcie-rcar.c #define LTSMDIS BIT(31) BIT 104 drivers/pci/controller/pcie-rcar.c #define SPCNGRSN BIT(31) BIT 108 drivers/pci/controller/pcie-rcar.c #define WRITE_CMD BIT(16) BIT 109 drivers/pci/controller/pcie-rcar.c #define PHY_ACK BIT(24) BIT 367 drivers/pci/controller/pcie-rockchip-ep.c ep->irq_pending |= BIT(intx); BIT 370 drivers/pci/controller/pcie-rockchip-ep.c ep->irq_pending &= ~BIT(intx); BIT 496 drivers/pci/controller/pcie-rockchip-ep.c cfg = BIT(0); BIT 498 drivers/pci/controller/pcie-rockchip-ep.c cfg |= BIT(epf->func_no); BIT 615 drivers/pci/controller/pcie-rockchip-ep.c rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); BIT 370 drivers/pci/controller/pcie-rockchip-host.c if (!(rockchip->lanes_map & BIT(i))) { BIT 533 drivers/pci/controller/pcie-rockchip-host.c reg &= ~BIT(hwirq); BIT 346 drivers/pci/controller/pcie-rockchip.c if (rockchip->lanes_map & BIT(i)) BIT 51 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15) BIT 52 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_MSG BIT(14) BIT 53 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_HOT_RST BIT(13) BIT 54 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_DPA BIT(12) BIT 55 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_FATAL_ERR BIT(11) BIT 56 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10) BIT 57 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_CORR_ERR BIT(9) BIT 58 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_INTD BIT(8) BIT 59 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_INTC BIT(7) BIT 60 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_INTB BIT(6) BIT 61 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_INTA BIT(5) BIT 62 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_LOCAL BIT(4) BIT 63 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_UDMA BIT(3) BIT 64 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_PHY BIT(2) BIT 65 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_HOT_PLUG BIT(1) BIT 66 drivers/pci/controller/pcie-rockchip.h #define PCIE_CLIENT_INT_PWR_STCG BIT(0) BIT 96 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_LANE_MAP_REVERSE BIT(16) BIT 98 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_PRFPE BIT(0) BIT 99 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_CRFPE BIT(1) BIT 100 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_RRPE BIT(2) BIT 101 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_PRFO BIT(3) BIT 102 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_CRFO BIT(4) BIT 103 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_RT BIT(5) BIT 104 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_RTR BIT(6) BIT 105 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_PE BIT(7) BIT 106 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_MTR BIT(8) BIT 107 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_UCR BIT(9) BIT 108 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_FCE BIT(10) BIT 109 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_CT BIT(11) BIT 110 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_UTC BIT(18) BIT 111 drivers/pci/controller/pcie-rockchip.h #define PCIE_CORE_INT_MMVC BIT(19) BIT 145 drivers/pci/controller/pcie-rockchip.h #define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) BIT 166 drivers/pci/controller/pcie-rockchip.h #define AXI_REGION_SIZE BIT(20) BIT 221 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_MSG_NO_DATA BIT(16) BIT 224 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19) BIT 230 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16) BIT 231 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24) BIT 250 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) BIT 52 drivers/pci/controller/pcie-tango.c u32 bit = BIT(d->hwirq % 32); BIT 62 drivers/pci/controller/pcie-tango.c u32 bit = BIT(d->hwirq % 32); BIT 48 drivers/pci/controller/pcie-xilinx-nwl.c #define SET_ISUB_CONTROL BIT(0) BIT 60 drivers/pci/controller/pcie-xilinx-nwl.c #define CFG_ENABLE_PM_MSG_FWD BIT(1) BIT 61 drivers/pci/controller/pcie-xilinx-nwl.c #define CFG_ENABLE_INT_MSG_FWD BIT(2) BIT 62 drivers/pci/controller/pcie-xilinx-nwl.c #define CFG_ENABLE_ERR_MSG_FWD BIT(3) BIT 68 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0) BIT 69 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_RXMSG_OVER BIT(1) BIT 70 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_SLAVE_ERR BIT(4) BIT 71 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_MASTER_ERR BIT(5) BIT 72 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_I_ADDR_ERR BIT(6) BIT 73 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_E_ADDR_ERR BIT(7) BIT 74 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_FATAL_AER BIT(16) BIT 75 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_NON_FATAL_AER BIT(17) BIT 76 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_CORR_AER BIT(18) BIT 77 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_UR_DETECT BIT(20) BIT 78 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) BIT 79 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_FATAL_DEV BIT(23) BIT 80 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MISC_SR_LINK_DOWN BIT(24) BIT 81 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) BIT 82 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) BIT 101 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_LEG_SR_INTA BIT(0) BIT 102 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_LEG_SR_INTB BIT(1) BIT 103 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_LEG_SR_INTC BIT(2) BIT 104 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_LEG_SR_INTD BIT(3) BIT 112 drivers/pci/controller/pcie-xilinx-nwl.c #define MSII_PRESENT BIT(0) BIT 113 drivers/pci/controller/pcie-xilinx-nwl.c #define MSII_ENABLE BIT(0) BIT 114 drivers/pci/controller/pcie-xilinx-nwl.c #define MSII_STATUS_ENABLE BIT(15) BIT 117 drivers/pci/controller/pcie-xilinx-nwl.c #define BRCFG_INTERRUPT_MASK BIT(0) BIT 118 drivers/pci/controller/pcie-xilinx-nwl.c #define BREG_PRESENT BIT(0) BIT 119 drivers/pci/controller/pcie-xilinx-nwl.c #define BREG_ENABLE BIT(0) BIT 120 drivers/pci/controller/pcie-xilinx-nwl.c #define BREG_ENABLE_FORCE BIT(1) BIT 123 drivers/pci/controller/pcie-xilinx-nwl.c #define E_ECAM_PRESENT BIT(0) BIT 124 drivers/pci/controller/pcie-xilinx-nwl.c #define E_ECAM_CR_ENABLE BIT(0) BIT 137 drivers/pci/controller/pcie-xilinx-nwl.c #define PCIE_PHY_LINKUP_BIT BIT(0) BIT 138 drivers/pci/controller/pcie-xilinx-nwl.c #define PHY_RDY_LINKUP_BIT BIT(1) BIT 41 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_LINK_DOWN BIT(0) BIT 42 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_ECRC_ERR BIT(1) BIT 43 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_STR_ERR BIT(2) BIT 44 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_HOT_RESET BIT(3) BIT 45 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_CFG_TIMEOUT BIT(8) BIT 46 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_CORRECTABLE BIT(9) BIT 47 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_NONFATAL BIT(10) BIT 48 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_FATAL BIT(11) BIT 49 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_INTX BIT(16) BIT 50 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_MSI BIT(17) BIT 51 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_SLV_UNSUPP BIT(20) BIT 52 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_SLV_UNEXP BIT(21) BIT 53 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_SLV_COMPL BIT(22) BIT 54 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_SLV_ERRP BIT(23) BIT 55 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_SLV_CMPABT BIT(24) BIT 56 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_SLV_ILLBUR BIT(25) BIT 57 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_MST_DECERR BIT(26) BIT 58 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_MST_SLVERR BIT(27) BIT 59 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_INTR_MST_ERRP BIT(28) BIT 65 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_RPEFR_ERR_VALID BIT(18) BIT 70 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_RPIFR1_INTR_VALID BIT(31) BIT 71 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_RPIFR1_MSI_INTR BIT(30) BIT 84 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_REG_RPSC_BEN BIT(0) BIT 87 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) BIT 25 drivers/pci/endpoint/functions/pci-epf-test.c #define COMMAND_RAISE_LEGACY_IRQ BIT(0) BIT 26 drivers/pci/endpoint/functions/pci-epf-test.c #define COMMAND_RAISE_MSI_IRQ BIT(1) BIT 27 drivers/pci/endpoint/functions/pci-epf-test.c #define COMMAND_RAISE_MSIX_IRQ BIT(2) BIT 28 drivers/pci/endpoint/functions/pci-epf-test.c #define COMMAND_READ BIT(3) BIT 29 drivers/pci/endpoint/functions/pci-epf-test.c #define COMMAND_WRITE BIT(4) BIT 30 drivers/pci/endpoint/functions/pci-epf-test.c #define COMMAND_COPY BIT(5) BIT 32 drivers/pci/endpoint/functions/pci-epf-test.c #define STATUS_READ_SUCCESS BIT(0) BIT 33 drivers/pci/endpoint/functions/pci-epf-test.c #define STATUS_READ_FAIL BIT(1) BIT 34 drivers/pci/endpoint/functions/pci-epf-test.c #define STATUS_WRITE_SUCCESS BIT(2) BIT 35 drivers/pci/endpoint/functions/pci-epf-test.c #define STATUS_WRITE_FAIL BIT(3) BIT 36 drivers/pci/endpoint/functions/pci-epf-test.c #define STATUS_COPY_SUCCESS BIT(4) BIT 37 drivers/pci/endpoint/functions/pci-epf-test.c #define STATUS_COPY_FAIL BIT(5) BIT 38 drivers/pci/endpoint/functions/pci-epf-test.c #define STATUS_IRQ_RAISED BIT(6) BIT 39 drivers/pci/endpoint/functions/pci-epf-test.c #define STATUS_SRC_ADDR_INVALID BIT(7) BIT 40 drivers/pci/endpoint/functions/pci-epf-test.c #define STATUS_DST_ADDR_INVALID BIT(8) BIT 428 drivers/pci/pci-acpi.c HPX_TYPE_ENDPOINT = BIT(0), BIT 429 drivers/pci/pci-acpi.c HPX_TYPE_LEG_END = BIT(1), BIT 430 drivers/pci/pci-acpi.c HPX_TYPE_RC_END = BIT(2), BIT 431 drivers/pci/pci-acpi.c HPX_TYPE_RC_EC = BIT(3), BIT 432 drivers/pci/pci-acpi.c HPX_TYPE_ROOT_PORT = BIT(4), BIT 433 drivers/pci/pci-acpi.c HPX_TYPE_UPSTREAM = BIT(5), BIT 434 drivers/pci/pci-acpi.c HPX_TYPE_DOWNSTREAM = BIT(6), BIT 435 drivers/pci/pci-acpi.c HPX_TYPE_PCI_BRIDGE = BIT(7), BIT 436 drivers/pci/pci-acpi.c HPX_TYPE_PCIE_BRIDGE = BIT(8), BIT 461 drivers/pci/pci-acpi.c HPX_FN_NORMAL = BIT(0), BIT 462 drivers/pci/pci-acpi.c HPX_FN_SRIOV_PHYS = BIT(1), BIT 463 drivers/pci/pci-acpi.c HPX_FN_SRIOV_VIRT = BIT(2), BIT 480 drivers/pci/pci-acpi.c if ((hpx3_cap_id & BIT(4)) && cap_ver >= pcie_cap_id) BIT 52 drivers/pci/pci-bridge-emul.c .rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16), BIT 110 drivers/pci/pci-bridge-emul.c .rsvd = ((BIT(6) | GENMASK(4, 0)) << 16), BIT 147 drivers/pci/pci-bridge-emul.c .rw = GENMASK(31, 11) | BIT(0), BIT 165 drivers/pci/pci-bridge-emul.c BIT(8) | BIT(9) | BIT(11)) << 16)), BIT 170 drivers/pci/pci-bridge-emul.c .w1c = BIT(10) << 16, BIT 172 drivers/pci/pci-bridge-emul.c .rsvd = (GENMASK(15, 12) | BIT(4)) << 16, BIT 204 drivers/pci/pci-bridge-emul.c .ro = lower_32_bits(~BIT(23)), BIT 205 drivers/pci/pci-bridge-emul.c .rsvd = BIT(23), BIT 218 drivers/pci/pci-bridge-emul.c .rsvd = GENMASK(15, 12) | BIT(2), BIT 123 drivers/pci/pci-bridge-emul.h PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR = BIT(0), BIT 5285 drivers/pci/quirks.c if (val & BIT(25)) BIT 5289 drivers/pci/quirks.c pci_write_config_dword(gpu, 0x488, val | BIT(25)); BIT 428 drivers/pci/setup-res.c if (!(sizes & BIT(size))) BIT 124 drivers/pcmcia/ricoh.h #define RL5C47X_MISC3_CB_CLKRUN_DIS BIT(1) BIT 1176 drivers/perf/arm-ccn.c int overflowed = pmovsr & BIT(idx); BIT 42 drivers/perf/arm_dsu_pmu.c #define CLUSTERPMCR_E BIT(0) BIT 43 drivers/perf/arm_dsu_pmu.c #define CLUSTERPMCR_P BIT(1) BIT 44 drivers/perf/arm_dsu_pmu.c #define CLUSTERPMCR_C BIT(2) BIT 70 drivers/perf/arm_smmuv3_pmu.c #define SMMU_PMCG_CFGR_SID_FILTER_TYPE BIT(23) BIT 71 drivers/perf/arm_smmuv3_pmu.c #define SMMU_PMCG_CFGR_MSI BIT(21) BIT 72 drivers/perf/arm_smmuv3_pmu.c #define SMMU_PMCG_CFGR_RELOC_CTRS BIT(20) BIT 76 drivers/perf/arm_smmuv3_pmu.c #define SMMU_PMCG_CR_ENABLE BIT(0) BIT 80 drivers/perf/arm_smmuv3_pmu.c #define SMMU_PMCG_IRQ_CTRL_IRQEN BIT(0) BIT 97 drivers/perf/arm_smmuv3_pmu.c #define SMMU_PMCG_EVCNTR_RDONLY BIT(0) BIT 152 drivers/perf/arm_smmuv3_pmu.c if (smmu_pmu->counter_mask & BIT(32)) BIT 162 drivers/perf/arm_smmuv3_pmu.c if (smmu_pmu->counter_mask & BIT(32)) BIT 172 drivers/perf/arm_smmuv3_pmu.c writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0); BIT 177 drivers/perf/arm_smmuv3_pmu.c writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0); BIT 182 drivers/perf/arm_smmuv3_pmu.c writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0); BIT 188 drivers/perf/arm_smmuv3_pmu.c writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0); BIT 272 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT); BIT 275 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); BIT 278 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT); BIT 323 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSFCR_EL1_FT_SHIFT); BIT 326 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSFCR_EL1_FE_SHIFT); BIT 329 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSFCR_EL1_FL_SHIFT); BIT 496 drivers/perf/arm_spe_pmu.c limit |= BIT(SYS_PMBLIMITR_EL1_E_SHIFT); BIT 555 drivers/perf/arm_spe_pmu.c if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT))) BIT 562 drivers/perf/arm_spe_pmu.c if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT)) BIT 567 drivers/perf/arm_spe_pmu.c if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT)) BIT 690 drivers/perf/arm_spe_pmu.c if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) && BIT 694 drivers/perf/arm_spe_pmu.c if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) && BIT 698 drivers/perf/arm_spe_pmu.c if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) && BIT 704 drivers/perf/arm_spe_pmu.c (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | BIT 705 drivers/perf/arm_spe_pmu.c BIT(SYS_PMSCR_EL1_CX_SHIFT) | BIT 706 drivers/perf/arm_spe_pmu.c BIT(SYS_PMSCR_EL1_PCT_SHIFT)))) BIT 943 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) { BIT 960 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT)) BIT 963 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT)) BIT 966 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT)) BIT 969 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT)) BIT 972 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT)) BIT 975 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT)) BIT 200 drivers/perf/qcom_l2_pmu.c return BIT(L2CYCLE_CTR_BIT); BIT 202 drivers/perf/qcom_l2_pmu.c return BIT(idx); BIT 977 drivers/perf/qcom_l2_pmu.c BIT(L2CYCLE_CTR_BIT); BIT 28 drivers/perf/xgene_pmu.c #define CSW_CSWCR_DUALMCB_MASK BIT(0) BIT 32 drivers/perf/xgene_pmu.c #define MCBADDRMR_DUALMCU_MODE_MASK BIT(2) BIT 39 drivers/perf/xgene_pmu.c #define PCPPMU_INT_MCU BIT(0) BIT 40 drivers/perf/xgene_pmu.c #define PCPPMU_INT_MCB BIT(1) BIT 41 drivers/perf/xgene_pmu.c #define PCPPMU_INT_L3C BIT(2) BIT 42 drivers/perf/xgene_pmu.c #define PCPPMU_INT_IOB BIT(3) BIT 56 drivers/perf/xgene_pmu.c #define PMU_PMCR_E BIT(0) BIT 57 drivers/perf/xgene_pmu.c #define PMU_PMCR_P BIT(1) BIT 1219 drivers/perf/xgene_pmu.c int overflowed = pmovsr & BIT(idx); BIT 47 drivers/phy/allwinner/phy-sun4i-usb.c #define PHYCTL_DATA BIT(7) BIT 49 drivers/phy/allwinner/phy-sun4i-usb.c #define OTGCTL_ROUTE_MUSB BIT(0) BIT 51 drivers/phy/allwinner/phy-sun4i-usb.c #define SUNXI_AHB_ICHR8_EN BIT(10) BIT 52 drivers/phy/allwinner/phy-sun4i-usb.c #define SUNXI_AHB_INCR4_BURST_EN BIT(9) BIT 53 drivers/phy/allwinner/phy-sun4i-usb.c #define SUNXI_AHB_INCRX_ALIGN_EN BIT(8) BIT 54 drivers/phy/allwinner/phy-sun4i-usb.c #define SUNXI_ULPI_BYPASS_EN BIT(0) BIT 82 drivers/phy/allwinner/phy-sun4i-usb.c #define PHY_CTL_VBUSVLDEXT BIT(5) BIT 83 drivers/phy/allwinner/phy-sun4i-usb.c #define PHY_CTL_SIDDQ BIT(3) BIT 86 drivers/phy/allwinner/phy-sun4i-usb.c #define SUNXI_EHCI_HS_FORCE BIT(20) BIT 87 drivers/phy/allwinner/phy-sun4i-usb.c #define SUNXI_HSIC_CONNECT_DET BIT(17) BIT 88 drivers/phy/allwinner/phy-sun4i-usb.c #define SUNXI_HSIC_CONNECT_INT BIT(16) BIT 89 drivers/phy/allwinner/phy-sun4i-usb.c #define SUNXI_HSIC BIT(1) BIT 194 drivers/phy/allwinner/phy-sun4i-usb.c u32 temp, usbc_bit = BIT(phy->index * 2); BIT 652 drivers/phy/allwinner/phy-sun4i-usb.c if (data->cfg->missing_phys & BIT(args->args[0])) BIT 750 drivers/phy/allwinner/phy-sun4i-usb.c if (data->cfg->missing_phys & BIT(i)) BIT 972 drivers/phy/allwinner/phy-sun4i-usb.c .missing_phys = BIT(1) | BIT(2), BIT 22 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_GCTL_EN BIT(0) BIT 25 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28) BIT 48 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA0_REG_PWS BIT(31) BIT 49 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA0_REG_DMPC BIT(28) BIT 55 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31) BIT 62 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA2_EN_CK_CPU BIT(4) BIT 63 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA2_REG_ENIB BIT(1) BIT 68 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA3_EN_VTTC BIT(27) BIT 69 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA3_EN_DIV BIT(26) BIT 70 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA3_EN_LDOC BIT(25) BIT 71 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA3_EN_LDOD BIT(24) BIT 72 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA3_EN_LDOR BIT(18) BIT 75 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA4_REG_DMPLVC BIT(24) BIT 23 drivers/phy/allwinner/phy-sun9i-usb.c #define SUNXI_AHB_INCR16_BURST_EN BIT(11) BIT 24 drivers/phy/allwinner/phy-sun9i-usb.c #define SUNXI_AHB_INCR8_BURST_EN BIT(10) BIT 25 drivers/phy/allwinner/phy-sun9i-usb.c #define SUNXI_AHB_INCR4_BURST_EN BIT(9) BIT 26 drivers/phy/allwinner/phy-sun9i-usb.c #define SUNXI_AHB_INCRX_ALIGN_EN BIT(8) BIT 27 drivers/phy/allwinner/phy-sun9i-usb.c #define SUNXI_ULPI_BYPASS_EN BIT(0) BIT 30 drivers/phy/allwinner/phy-sun9i-usb.c #define SUNXI_EHCI_HS_FORCE BIT(20) BIT 31 drivers/phy/allwinner/phy-sun9i-usb.c #define SUNXI_HSIC_CONNECT_DET BIT(17) BIT 32 drivers/phy/allwinner/phy-sun9i-usb.c #define SUNXI_HSIC_CONNECT_INT BIT(16) BIT 33 drivers/phy/allwinner/phy-sun9i-usb.c #define SUNXI_HSIC BIT(1) BIT 35 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R4_I_C2L_CAL_EN BIT(24) BIT 36 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R4_I_C2L_CAL_RESET_N BIT(25) BIT 37 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R4_I_C2L_CAL_DONE BIT(26) BIT 38 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R4_TEST_BYPASS_MODE_EN BIT(27) BIT 52 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_LOAD_STAT BIT(14) BIT 53 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_UPDATE_PMA_SIGNALS BIT(15) BIT 55 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT BIT(21) BIT 56 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL BIT(22) BIT 57 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN BIT(23) BIT 58 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_I_C2L_HS_EN BIT(24) BIT 59 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_I_C2L_FS_EN BIT(25) BIT 60 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_I_C2L_LS_EN BIT(26) BIT 61 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_I_C2L_HS_OE BIT(27) BIT 62 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_I_C2L_FS_OE BIT(28) BIT 63 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_I_C2L_HS_RX_EN BIT(29) BIT 64 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R13_I_C2L_FSLS_RX_EN BIT(30) BIT 67 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R14_I_RDP_EN BIT(0) BIT 68 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R14_I_RPU_SW1_EN BIT(1) BIT 70 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R14_PG_RSTN BIT(4) BIT 71 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R14_I_C2L_DATA_16_8 BIT(5) BIT 72 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R14_I_C2L_ASSERT_SINGLE_EN_ZERO BIT(6) BIT 80 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R16_MPLL_TDC_MODE BIT(20) BIT 81 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R16_MPLL_SDM_EN BIT(21) BIT 82 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R16_MPLL_LOAD BIT(22) BIT 83 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R16_MPLL_DCO_SDM_EN BIT(23) BIT 85 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R16_MPLL_LOCK_F BIT(26) BIT 86 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R16_MPLL_FAST_LOCK BIT(27) BIT 87 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R16_MPLL_EN BIT(28) BIT 88 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R16_MPLL_RESET BIT(29) BIT 89 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R16_MPLL_LOCK BIT(30) BIT 90 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R16_MPLL_LOCK_DIG BIT(31) BIT 94 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R17_MPLL_FIX_EN BIT(16) BIT 97 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R17_MPLL_FILTER_MODE BIT(23) BIT 105 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R18_MPLL_DCO_M_EN BIT(12) BIT 106 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R18_MPLL_DCO_CLK_SEL BIT(13) BIT 114 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R18_MPLL_ACG_RANGE BIT(31) BIT 118 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R20_USB2_IDDET_EN BIT(0) BIT 120 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R20_USB2_OTG_VBUSDET_EN BIT(4) BIT 121 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R20_USB2_AMON_EN BIT(5) BIT 122 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R20_USB2_CAL_CODE_R5 BIT(6) BIT 123 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R20_BYPASS_OTG_DET BIT(7) BIT 124 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R20_USB2_DMON_EN BIT(8) BIT 126 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R20_USB2_EDGE_DRV_EN BIT(13) BIT 129 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R20_USB2_BGR_START BIT(21) BIT 132 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R20_BYPASS_CAL_DONE_R5 BIT(31) BIT 135 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R21_USB2_BGR_FORCE BIT(0) BIT 136 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R21_USB2_CAL_ACK_EN BIT(1) BIT 137 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R21_USB2_OTG_ACA_EN BIT(2) BIT 138 drivers/phy/amlogic/phy-meson-g12a-usb2.c #define PHY_CTRL_R21_USB2_TX_STRG_PD BIT(3) BIT 32 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c #define PHY_R1_PHY_REF_CLKDIV2 BIT(24) BIT 42 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c #define PHY_R4_PHY_CR_WRITE BIT(0) BIT 43 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c #define PHY_R4_PHY_CR_READ BIT(1) BIT 45 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c #define PHY_R4_PHY_CR_CAP_DATA BIT(18) BIT 46 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c #define PHY_R4_PHY_CR_CAP_ADDR BIT(19) BIT 50 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c #define PHY_R5_PHY_CR_ACK BIT(16) BIT 51 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c #define PHY_R5_PHY_BS_OUT BIT(17) BIT 212 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c ret = regmap_update_bits(priv->regmap_cr, 0x102d, BIT(7), BIT(7)); BIT 231 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c data &= ~BIT(6); BIT 232 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c data |= BIT(7); BIT 253 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c data |= (0x7f | BIT(14)); BIT 20 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_BYPASS_SEL BIT(0) BIT 21 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_BYPASS_DM_EN BIT(1) BIT 22 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_BYPASS_DP_EN BIT(2) BIT 23 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_TXBITSTUFF_ENH BIT(3) BIT 24 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_TXBITSTUFF_EN BIT(4) BIT 25 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_DM_PULLDOWN BIT(5) BIT 26 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_DP_PULLDOWN BIT(6) BIT 27 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) BIT 28 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_DP_VBUS_VLD_EXT BIT(8) BIT 29 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_ADP_PRB_EN BIT(9) BIT 30 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_ADP_DISCHARGE BIT(10) BIT 31 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_ADP_CHARGE BIT(11) BIT 32 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_DRV_VBUS BIT(12) BIT 33 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_ID_PULLUP BIT(13) BIT 34 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_LOOPBACK_EN_B BIT(14) BIT 35 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_OTG_DISABLE BIT(15) BIT 36 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_COMMON_ONN BIT(16) BIT 39 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_POWER_ON_RESET BIT(22) BIT 41 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_ID_SET_ID_DQ BIT(25) BIT 42 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_ATE_RESET BIT(26) BIT 43 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_FSV_MINUS BIT(27) BIT 44 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_FSV_PLUS BIT(28) BIT 45 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_BYPASS_DM_DATA BIT(29) BIT 46 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R0_BYPASS_DP_DATA BIT(30) BIT 49 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R1_BURN_IN_TEST BIT(0) BIT 50 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R1_ACA_ENABLE BIT(1) BIT 51 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R1_DCD_ENABLE BIT(2) BIT 52 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R1_VDAT_SRC_EN_B BIT(3) BIT 53 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R1_VDAT_DET_EN_B BIT(4) BIT 54 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R1_CHARGES_SEL BIT(5) BIT 55 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) BIT 70 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_TESTDATA_OUT_SEL BIT(12) BIT 71 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_TESTCLK BIT(13) BIT 73 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_ACA_PIN_RANGE_C BIT(18) BIT 74 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_ACA_PIN_RANGE_B BIT(19) BIT 75 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_ACA_PIN_RANGE_A BIT(20) BIT 76 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_ACA_PIN_GND BIT(21) BIT 77 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_ACA_PIN_FLOAT BIT(22) BIT 78 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_CHARGE_DETECT BIT(23) BIT 79 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_DEVICE_SESSION_VALID BIT(24) BIT 80 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_ADP_PROBE BIT(25) BIT 81 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_ADP_SENSE BIT(26) BIT 82 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_SESSION_END BIT(27) BIT 83 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_VBUS_VALID BIT(28) BIT 84 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_B_VALID BIT(29) BIT 85 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_A_VALID BIT(30) BIT 86 drivers/phy/amlogic/phy-meson-gxl-usb2.c #define U2P_R2_ID_DIG BIT(31) BIT 20 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R0_P30_PHY_RESET BIT(6) BIT 21 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7) BIT 22 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8) BIT 25 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) BIT 26 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) BIT 29 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R0_U2D_ACT BIT(31) BIT 32 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R1_U3H_BIGENDIAN_GS BIT(0) BIT 33 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R1_U3H_PME_ENABLE BIT(1) BIT 37 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16) BIT 38 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17) BIT 39 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18) BIT 45 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R2_P30_CR_READ BIT(16) BIT 46 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R2_P30_CR_WRITE BIT(17) BIT 47 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R2_P30_CR_CAP_ADDR BIT(18) BIT 48 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R2_P30_CR_CAP_DATA BIT(19) BIT 53 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R3_P30_SSC_ENABLE BIT(0) BIT 56 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R3_P30_REF_SSP_EN BIT(13) BIT 62 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R4_P21_PORT_RESET_0 BIT(0) BIT 63 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R4_P21_SLEEP_M0 BIT(1) BIT 65 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R4_P21_ONLY BIT(4) BIT 68 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R5_ID_DIG_SYNC BIT(0) BIT 69 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R5_ID_DIG_REG BIT(1) BIT 71 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R5_ID_DIG_EN_0 BIT(4) BIT 72 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R5_ID_DIG_EN_1 BIT(5) BIT 73 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R5_ID_DIG_CURR BIT(6) BIT 74 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R5_ID_DIG_IRQ BIT(7) BIT 81 drivers/phy/amlogic/phy-meson-gxl-usb3.c #define USB_R6_P30_CR_ACK BIT(16) BIT 19 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CONFIG_CLK_EN BIT(0) BIT 22 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CONFIG_CLK_32k_ALTSEL BIT(15) BIT 23 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CONFIG_TEST_TRIG BIT(31) BIT 26 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_SOFT_PRST BIT(0) BIT 27 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_SOFT_HRESET BIT(1) BIT 29 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_CLK_DET_RST BIT(4) BIT 30 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_INTR_SEL BIT(5) BIT 31 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_CLK_DETECTED BIT(8) BIT 32 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_SOF_SENT_RCVD_TGL BIT(9) BIT 33 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_SOF_TOGGLE_OUT BIT(10) BIT 34 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_POWER_ON_RESET BIT(15) BIT 35 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_SLEEPM BIT(16) BIT 36 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_TX_BITSTUFF_ENN_H BIT(17) BIT 37 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_TX_BITSTUFF_ENN BIT(18) BIT 38 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_COMMON_ON BIT(19) BIT 43 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_CTRL_PORT_RESET BIT(25) BIT 50 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_VBUS_VLD_EXT_SEL BIT(0) BIT 51 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_VBUS_VLD_EXT BIT(1) BIT 52 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_OTG_DISABLE BIT(2) BIT 53 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ID_PULLUP BIT(3) BIT 54 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_DRV_VBUS BIT(4) BIT 55 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ADP_PRB_EN BIT(5) BIT 56 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ADP_DISCHARGE BIT(6) BIT 57 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ADP_CHARGE BIT(7) BIT 58 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_SESS_END BIT(8) BIT 59 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_DEVICE_SESS_VLD BIT(9) BIT 60 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_B_VALID BIT(10) BIT 61 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_A_VALID BIT(11) BIT 62 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ID_DIG BIT(12) BIT 63 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_VBUS_VALID BIT(13) BIT 64 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ADP_PROBE BIT(14) BIT 65 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ADP_SENSE BIT(15) BIT 66 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ACA_ENABLE BIT(16) BIT 67 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_DCD_ENABLE BIT(17) BIT 68 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_VDAT_DET_EN_B BIT(18) BIT 69 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_VDAT_SRC_EN_B BIT(19) BIT 70 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_CHARGE_SEL BIT(20) BIT 71 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_CHARGE_DETECT BIT(21) BIT 72 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ACA_PIN_RANGE_C BIT(22) BIT 73 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ACA_PIN_RANGE_B BIT(23) BIT 74 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ACA_PIN_RANGE_A BIT(24) BIT 75 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ACA_PIN_GND BIT(25) BIT 76 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_ADP_BC_ACA_PIN_FLOAT BIT(26) BIT 84 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_TEST_DATA_OUT_SEL BIT(12) BIT 85 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_TEST_CLK BIT(13) BIT 88 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_TEST_DISABLE_ID_PULLUP BIT(20) BIT 95 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_TUNE_TX_PREEMP_PULSE_TUNE BIT(10) BIT 101 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_TUNE_HOST_DM_PULLDOWN BIT(26) BIT 102 drivers/phy/amlogic/phy-meson8b-usb2.c #define REG_TUNE_HOST_DP_PULLDOWN BIT(27) BIT 84 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c val &= ~BIT(shift); BIT 93 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c val |= BIT(shift); BIT 19 drivers/phy/broadcom/phy-bcm-kona-usb2.c #define OTGCTL_OTGSTAT2 BIT(31) BIT 20 drivers/phy/broadcom/phy-bcm-kona-usb2.c #define OTGCTL_OTGSTAT1 BIT(30) BIT 21 drivers/phy/broadcom/phy-bcm-kona-usb2.c #define OTGCTL_PRST_N_SW BIT(11) BIT 22 drivers/phy/broadcom/phy-bcm-kona-usb2.c #define OTGCTL_HRESET_N BIT(10) BIT 23 drivers/phy/broadcom/phy-bcm-kona-usb2.c #define OTGCTL_UTMI_LINE_STATE1 BIT(9) BIT 24 drivers/phy/broadcom/phy-bcm-kona-usb2.c #define OTGCTL_UTMI_LINE_STATE0 BIT(8) BIT 27 drivers/phy/broadcom/phy-bcm-kona-usb2.c #define P1CTL_SOFT_RESET BIT(1) BIT 28 drivers/phy/broadcom/phy-bcm-kona-usb2.c #define P1CTL_NON_DRIVING BIT(0) BIT 38 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define ICFG_DEV_BIT BIT(2) BIT 39 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define IDM_RST_BIT BIT(0) BIT 40 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define AFE_CORERDY_VDDC BIT(18) BIT 41 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define PHY_PLL_RESETB BIT(15) BIT 42 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define PHY_RESETB BIT(14) BIT 43 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define PHY_PLL_LOCK BIT(0) BIT 45 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define DRD_DEV_MODE BIT(20) BIT 46 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define OHCI_OVRCUR_POL BIT(11) BIT 47 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define ICFG_OFF_MODE BIT(6) BIT 53 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define DRD_HOST_MODE (BIT(2) | BIT(3)) BIT 54 drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c #define DRD_DEVICE_MODE (BIT(4) | BIT(5)) BIT 169 drivers/phy/broadcom/phy-bcm-sr-usb.c BIT(u3pll_ctrl[SSPLL_SUSPEND_EN])); BIT 171 drivers/phy/broadcom/phy-bcm-sr-usb.c BIT(u3pll_ctrl[PLL_SEQ_START])); BIT 173 drivers/phy/broadcom/phy-bcm-sr-usb.c BIT(u3pll_ctrl[PLL_RESETB])); BIT 179 drivers/phy/broadcom/phy-bcm-sr-usb.c BIT(u3pll_ctrl[PLL_LOCK])); BIT 203 drivers/phy/broadcom/phy-bcm-sr-usb.c BIT(u2phy_ctrl[CORERDY])); BIT 209 drivers/phy/broadcom/phy-bcm-sr-usb.c BIT(u2pll_ctrl[PLL_RESETB])); BIT 211 drivers/phy/broadcom/phy-bcm-sr-usb.c BIT(u2phy_ctrl[PHY_RESETB])); BIT 223 drivers/phy/broadcom/phy-bcm-sr-usb.c BIT(u2pll_ctrl[PLL_LOCK])); BIT 238 drivers/phy/broadcom/phy-bcm-sr-usb.c BIT(u2phy_ctrl[CORERDY])); BIT 240 drivers/phy/broadcom/phy-bcm-sr-usb.c BIT(u2phy_ctrl[CORERDY])); BIT 81 drivers/phy/broadcom/phy-brcm-sata.c BLOCK0_XGXSSTATUS_PLL_LOCK = BIT(12), BIT 88 drivers/phy/broadcom/phy-brcm-sata.c PLLCONTROL_0_FREQ_DET_RESTART = BIT(13), BIT 89 drivers/phy/broadcom/phy-brcm-sata.c PLLCONTROL_0_FREQ_MONITOR = BIT(12), BIT 90 drivers/phy/broadcom/phy-brcm-sata.c PLLCONTROL_0_SEQ_START = BIT(15), BIT 110 drivers/phy/broadcom/phy-brcm-sata.c TX_ACTRL0_TXPOL_FLIP = BIT(6), BIT 114 drivers/phy/broadcom/phy-brcm-sata.c AEQ_CONTROL1_ENABLE = BIT(2), BIT 115 drivers/phy/broadcom/phy-brcm-sata.c AEQ_CONTROL1_FREEZE = BIT(3), BIT 117 drivers/phy/broadcom/phy-brcm-sata.c AEQ_FRC_EQ_FORCE = BIT(0), BIT 118 drivers/phy/broadcom/phy-brcm-sata.c AEQ_FRC_EQ_FORCE_VAL = BIT(1), BIT 146 drivers/phy/broadcom/phy-brcm-sata.c TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0), BIT 147 drivers/phy/broadcom/phy-brcm-sata.c TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1), BIT 160 drivers/phy/broadcom/phy-brcm-sata.c PHY_CTRL_1_RESET = BIT(0), BIT 573 drivers/phy/broadcom/phy-brcm-sata.c u32 tmp = BIT(8); BIT 151 drivers/phy/broadcom/phy-brcm-usb-init.c #define MDIO_USB3 BIT(31) BIT 30 drivers/phy/cadence/cdns-dphy.c #define DPHY_CMN_SSM_EN BIT(0) BIT 31 drivers/phy/cadence/cdns-dphy.c #define DPHY_CMN_TX_MODE_EN BIT(9) BIT 40 drivers/phy/cadence/cdns-dphy.c #define DPHY_CMN_FBDIV_FROM_REG (BIT(10) | BIT(21)) BIT 43 drivers/phy/cadence/cdns-dphy.c #define DPHY_CMN_IPDIV_FROM_REG BIT(0) BIT 45 drivers/phy/cadence/cdns-dphy.c #define DPHY_CMN_OPDIV_FROM_REG BIT(6) BIT 49 drivers/phy/cadence/cdns-dphy.c #define DPHY_PSM_CFG_FROM_REG BIT(0) BIT 12 drivers/phy/freescale/phy-fsl-imx8mq-usb.c #define PHY_CTRL0_REF_SSP_EN BIT(2) BIT 15 drivers/phy/freescale/phy-fsl-imx8mq-usb.c #define PHY_CTRL1_RESET BIT(0) BIT 16 drivers/phy/freescale/phy-fsl-imx8mq-usb.c #define PHY_CTRL1_COMMONONN BIT(1) BIT 17 drivers/phy/freescale/phy-fsl-imx8mq-usb.c #define PHY_CTRL1_ATERESET BIT(3) BIT 18 drivers/phy/freescale/phy-fsl-imx8mq-usb.c #define PHY_CTRL1_VDATSRCENB0 BIT(19) BIT 19 drivers/phy/freescale/phy-fsl-imx8mq-usb.c #define PHY_CTRL1_VDATDETENB0 BIT(20) BIT 22 drivers/phy/freescale/phy-fsl-imx8mq-usb.c #define PHY_CTRL2_TXENABLEN0 BIT(8) BIT 20 drivers/phy/hisilicon/phy-hi3660-usb3.c #define GT_CLK_USB3OTG_REF BIT(0) BIT 21 drivers/phy/hisilicon/phy-hi3660-usb3.c #define GT_ACLK_USB3OTG BIT(1) BIT 25 drivers/phy/hisilicon/phy-hi3660-usb3.c #define IP_RST_USB3OTGPHY_POR BIT(3) BIT 26 drivers/phy/hisilicon/phy-hi3660-usb3.c #define IP_RST_USB3OTG BIT(5) BIT 29 drivers/phy/hisilicon/phy-hi3660-usb3.c #define USB_REFCLK_ISO_EN BIT(25) BIT 33 drivers/phy/hisilicon/phy-hi3660-usb3.c #define USB_TCXO_EN BIT(1) BIT 36 drivers/phy/hisilicon/phy-hi3660-usb3.c #define SC_CLK_USB3PHY_3MUX1_SEL BIT(25) BIT 39 drivers/phy/hisilicon/phy-hi3660-usb3.c #define SC_USB3PHY_ABB_GT_EN BIT(15) BIT 42 drivers/phy/hisilicon/phy-hi3660-usb3.c #define USBOTG3CTRL2_POWERDOWN_HSP BIT(0) BIT 43 drivers/phy/hisilicon/phy-hi3660-usb3.c #define USBOTG3CTRL2_POWERDOWN_SSP BIT(1) BIT 46 drivers/phy/hisilicon/phy-hi3660-usb3.c #define USBOTG3_CTRL3_VBUSVLDEXT BIT(6) BIT 47 drivers/phy/hisilicon/phy-hi3660-usb3.c #define USBOTG3_CTRL3_VBUSVLDEXTSEL BIT(5) BIT 52 drivers/phy/hisilicon/phy-hi3660-usb3.c #define REF_SSP_EN BIT(16) BIT 15 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL4_PICO_SIDDQ BIT(6) BIT 16 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL4_PICO_OGDISABLE BIT(8) BIT 17 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL4_PICO_VBUSVLDEXT BIT(10) BIT 18 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL4_PICO_VBUSVLDEXTSEL BIT(11) BIT 19 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL4_OTG_PHY_SEL BIT(21) BIT 23 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL5_USBOTG_RES_SEL BIT(3) BIT 24 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL5_PICOPHY_ACAENB BIT(4) BIT 25 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL5_PICOPHY_BC_MODE BIT(5) BIT 26 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL5_PICOPHY_CHRGSEL BIT(6) BIT 27 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL5_PICOPHY_VDATSRCEND BIT(7) BIT 28 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL5_PICOPHY_VDATDETENB BIT(8) BIT 29 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL5_PICOPHY_DCDENB BIT(9) BIT 30 drivers/phy/hisilicon/phy-hi6220-usb.c #define CTRL5_PICOPHY_IDDIG BIT(10) BIT 36 drivers/phy/hisilicon/phy-hi6220-usb.c #define RST0_USBOTG_BUS BIT(4) BIT 37 drivers/phy/hisilicon/phy-hi6220-usb.c #define RST0_POR_PICOPHY BIT(5) BIT 38 drivers/phy/hisilicon/phy-hi6220-usb.c #define RST0_USBOTG BIT(6) BIT 39 drivers/phy/hisilicon/phy-hi6220-usb.c #define RST0_USBOTG_32K BIT(7) BIT 26 drivers/phy/hisilicon/phy-hisi-inno-usb2.c #define PHY_TEST_WREN BIT(21) BIT 27 drivers/phy/hisilicon/phy-hisi-inno-usb2.c #define PHY_TEST_CLK BIT(22) /* rising edge active */ BIT 28 drivers/phy/hisilicon/phy-hisi-inno-usb2.c #define PHY_TEST_RST BIT(23) /* low active */ BIT 29 drivers/phy/hisilicon/phy-hisi-inno-usb2.c #define PHY_CLK_ENABLE BIT(2) BIT 27 drivers/phy/hisilicon/phy-histb-combphy.c #define COMBPHY_BYPASS_CODEC BIT(31) BIT 28 drivers/phy/hisilicon/phy-histb-combphy.c #define COMBPHY_TEST_WRITE BIT(24) BIT 33 drivers/phy/hisilicon/phy-histb-combphy.c #define COMBPHY_CLKREF_OUT_OEN BIT(0) BIT 20 drivers/phy/hisilicon/phy-hix5hd2-sata.c #define PHY_RESET BIT(0) BIT 21 drivers/phy/hisilicon/phy-hix5hd2-sata.c #define REF_SSP_EN BIT(9) BIT 22 drivers/phy/hisilicon/phy-hix5hd2-sata.c #define SSC_EN BIT(10) BIT 23 drivers/phy/hisilicon/phy-hix5hd2-sata.c #define REF_USE_PAD BIT(23) BIT 30 drivers/phy/hisilicon/phy-hix5hd2-sata.c #define SPEED_CTRL BIT(20) BIT 77 drivers/phy/hisilicon/phy-hix5hd2-sata.c BIT(data[1]), BIT(data[1])); BIT 23 drivers/phy/lantiq/phy-lantiq-rcu-usb2.c #define RCU_CFG1_TX_PEE BIT(0) BIT 106 drivers/phy/lantiq/phy-lantiq-rcu-usb2.c BIT(priv->reg_bits->hostmode), 0); BIT 110 drivers/phy/lantiq/phy-lantiq-rcu-usb2.c BIT(priv->reg_bits->slave_endianness), 0); BIT 112 drivers/phy/lantiq/phy-lantiq-rcu-usb2.c BIT(priv->reg_bits->host_endianness), BIT 113 drivers/phy/lantiq/phy-lantiq-rcu-usb2.c BIT(priv->reg_bits->host_endianness)); BIT 33 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_PLL_CTRL2_CONST_SDM_EN BIT(8) BIT 34 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_PLL_CTRL2_PLL_SDM_EN BIT(9) BIT 37 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN BIT(1) BIT 47 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN BIT(14) BIT 55 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_TX1_CTRL1_FORCE_EN BIT(3) BIT 56 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_TX1_CTRL1_LOAD_EN BIT(4) BIT 67 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_TX2_CTRL1_LOAD_EN BIT(4) BIT 77 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_RX1_CTRL1_LOAD_EN BIT(1) BIT 22 drivers/phy/marvell/phy-armada375-usb2.c #define USB2_PHY_CONFIG_DISABLE BIT(0) BIT 27 drivers/phy/marvell/phy-armada38x-comphy.c #define COMPHY_STAT1_PLL_RDY_TX BIT(3) BIT 28 drivers/phy/marvell/phy-armada38x-comphy.c #define COMPHY_STAT1_PLL_RDY_RX BIT(2) BIT 25 drivers/phy/marvell/phy-berlin-sata.c #define POWER_DOWN_PHY0 BIT(6) BIT 26 drivers/phy/marvell/phy-berlin-sata.c #define POWER_DOWN_PHY1 BIT(14) BIT 27 drivers/phy/marvell/phy-berlin-sata.c #define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16) BIT 28 drivers/phy/marvell/phy-berlin-sata.c #define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19) BIT 34 drivers/phy/marvell/phy-berlin-sata.c #define REF_FREF_SEL_25 BIT(0) BIT 38 drivers/phy/marvell/phy-berlin-sata.c #define USE_MAX_PLL_RATE BIT(12) BIT 29 drivers/phy/marvell/phy-berlin-usb.c #define CLK_STABLE BIT(0) BIT 30 drivers/phy/marvell/phy-berlin-usb.c #define PLL_CTRL_PIN BIT(1) BIT 31 drivers/phy/marvell/phy-berlin-usb.c #define PLL_CTRL_REG BIT(2) BIT 32 drivers/phy/marvell/phy-berlin-usb.c #define PLL_ON BIT(3) BIT 34 drivers/phy/marvell/phy-berlin-usb.c #define PHASE_OFF_TOL_250 BIT(5) BIT 36 drivers/phy/marvell/phy-berlin-usb.c #define KVC0_REG_CTRL BIT(9) BIT 39 drivers/phy/marvell/phy-berlin-usb.c #define CLK_BLK_EN BIT(13) BIT 42 drivers/phy/marvell/phy-berlin-usb.c #define EXT_HS_RCAL_EN BIT(3) BIT 43 drivers/phy/marvell/phy-berlin-usb.c #define EXT_FS_RCAL_EN BIT(4) BIT 50 drivers/phy/marvell/phy-berlin-usb.c #define TX_VDD15_15 BIT(4) BIT 54 drivers/phy/marvell/phy-berlin-usb.c #define TX_VDD12_11 BIT(6) BIT 57 drivers/phy/marvell/phy-berlin-usb.c #define LOW_VDD_EN BIT(8) BIT 64 drivers/phy/marvell/phy-berlin-usb.c #define IMP_CAL_FS_HS_DLY_1 BIT(6) BIT 72 drivers/phy/marvell/phy-berlin-usb.c #define PHASE_FREEZE_DLY_4_CL BIT(0) BIT 74 drivers/phy/marvell/phy-berlin-usb.c #define ACK_LENGTH_12_CL BIT(2) BIT 78 drivers/phy/marvell/phy-berlin-usb.c #define SQ_LENGTH_6 BIT(4) BIT 82 drivers/phy/marvell/phy-berlin-usb.c #define DISCON_THRESHOLD_270 BIT(6) BIT 88 drivers/phy/marvell/phy-berlin-usb.c #define INTPL_CUR_20 BIT(14) BIT 93 drivers/phy/marvell/phy-berlin-usb.c #define ANA_PWR_UP BIT(1) BIT 94 drivers/phy/marvell/phy-berlin-usb.c #define ANA_PWR_DOWN BIT(2) BIT 97 drivers/phy/marvell/phy-berlin-usb.c #define R_ROTATE_0 BIT(10) BIT 98 drivers/phy/marvell/phy-berlin-usb.c #define MODE_TEST_EN BIT(11) BIT 31 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PLL_READY BIT(31) BIT 33 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PHY_PLLCAL_DONE BIT(31) BIT 34 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PHY_IMPCAL_DONE BIT(23) BIT 36 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define USB2PHY_SQCAL_DONE BIT(31) BIT 38 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PHY_PU_OTG BIT(4) BIT 40 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PHY_CDP_EN BIT(2) BIT 41 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PHY_DCP_EN BIT(3) BIT 42 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PHY_PD_EN BIT(4) BIT 43 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PHY_PU_CHRG_DTC BIT(5) BIT 44 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PHY_CDP_DM_AUTO BIT(7) BIT 45 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PHY_ENSWITCH_DP BIT(12) BIT 46 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define PHY_ENSWITCH_DM BIT(13) BIT 50 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define RB_USB2PHY_PU BIT(0) BIT 51 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define USB2_DP_PULLDN_DEV_MODE BIT(5) BIT 52 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define USB2_DM_PULLDN_DEV_MODE BIT(6) BIT 53 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define RB_USB2PHY_SUSPM(usb32) (usb32 ? BIT(14) : BIT(7)) BIT 21 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1) BIT 24 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_CFG0_PU_RX BIT(11) BIT 25 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_CFG0_PU_TX BIT(12) BIT 26 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_CFG0_HALF_BUS BIT(14) BIT 27 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE BIT(15) BIT 29 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_CFG1_RESET BIT(3) BIT 30 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4) BIT 31 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_CFG1_CORE_RESET BIT(5) BIT 32 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_CFG1_RF_RESET BIT(6) BIT 34 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4) BIT 36 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2) BIT 37 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY BIT(3) BIT 38 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4) BIT 44 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_IMP_CAL_TX_EXT_EN BIT(15) BIT 46 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL BIT(15) BIT 48 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_COEF_DFE_EN BIT(14) BIT 49 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_COEF_DFE_CTRL BIT(15) BIT 58 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_GEN1_S1_RX_DFE_EN BIT(10) BIT 62 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4) BIT 66 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_VDD_CAL0_CONT_MODE BIT(15) BIT 70 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5) BIT 71 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL BIT(10) BIT 73 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL BIT(11) BIT 74 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_RX_CTRL1_CLK8T_EN BIT(12) BIT 76 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SPEED_DIV_TX_FORCE BIT(7) BIT 79 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_SP_CALIB_SAMPLER_EN BIT(12) BIT 84 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN BIT(2) BIT 88 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN BIT(12) BIT 90 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_DME_ETH_MODE BIT(7) BIT 92 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_TRAINING0_P2P_HOLD BIT(15) BIT 96 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN BIT(8) BIT 97 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11 BIT(9) BIT 99 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_GEN1_S3_FBCK_SEL BIT(9) BIT 109 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_CONF1_PWRUP BIT(1) BIT 110 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */ BIT 112 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_CONF6_40B BIT(18) BIT 118 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SD1_CTRL1_RXAUI1_EN BIT(26) BIT 119 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define MVEBU_COMPHY_SD1_CTRL1_RXAUI0_EN BIT(27) BIT 21 drivers/phy/marvell/phy-mvebu-sata.c #define MODE_2_FORCE_PU_TX BIT(0) BIT 22 drivers/phy/marvell/phy-mvebu-sata.c #define MODE_2_FORCE_PU_RX BIT(1) BIT 23 drivers/phy/marvell/phy-mvebu-sata.c #define MODE_2_PU_PLL BIT(2) BIT 24 drivers/phy/marvell/phy-mvebu-sata.c #define MODE_2_PU_IVREF BIT(3) BIT 26 drivers/phy/marvell/phy-mvebu-sata.c #define CTRL_PHY_SHUTDOWN BIT(9) BIT 31 drivers/phy/marvell/phy-pxa-28nm-hsic.c #define PHY_28NM_HSIC_S2H_PU_PLL BIT(10) BIT 32 drivers/phy/marvell/phy-pxa-28nm-hsic.c #define PHY_28NM_HSIC_H2S_PLL_LOCK BIT(15) BIT 33 drivers/phy/marvell/phy-pxa-28nm-hsic.c #define PHY_28NM_HSIC_S2H_HSIC_EN BIT(7) BIT 34 drivers/phy/marvell/phy-pxa-28nm-hsic.c #define S2H_DRV_SE0_4RESUME BIT(14) BIT 35 drivers/phy/marvell/phy-pxa-28nm-hsic.c #define PHY_28NM_HSIC_H2S_IMPCAL_DONE BIT(27) BIT 37 drivers/phy/marvell/phy-pxa-28nm-hsic.c #define PHY_28NM_HSIC_CONNECT_INT BIT(1) BIT 38 drivers/phy/marvell/phy-pxa-28nm-hsic.c #define PHY_28NM_HSIC_HS_READY_INT BIT(2) BIT 44 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_PLL_READY BIT(31) BIT 59 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_PLL_PU_BY_REG BIT(1) BIT 61 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_PLL_PU_PLL BIT(0) BIT 64 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_PLL_PLLCAL_DONE BIT(31) BIT 66 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_PLL_IMPCAL_DONE BIT(23) BIT 81 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_TX_PU_BY_REG BIT(25) BIT 83 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_TX_PU_ANA BIT(24) BIT 93 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_RX_SQCAL_DONE BIT(31) BIT 96 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_DIG_BITSTAFFING_ERR BIT(31) BIT 97 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_DIG_SYNC_ERR BIT(30) BIT 108 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_PLL_LOCK_BYPASS BIT(7) BIT 111 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_OTG_CONTROL_BY_PIN BIT(5) BIT 112 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_OTG_PU_OTG BIT(4) BIT 129 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_CTRL3_OVERWRITE BIT(0) BIT 130 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_CTRL3_VBUS_VALID BIT(4) BIT 131 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_CTRL3_AVALID BIT(5) BIT 132 drivers/phy/marvell/phy-pxa-28nm-usb2.c #define PHY_28NM_CTRL3_BVALID BIT(6) BIT 42 drivers/phy/mediatek/phy-mtk-tphy.c #define PA0_RG_U2PLL_FORCE_ON BIT(15) BIT 43 drivers/phy/mediatek/phy-mtk-tphy.c #define PA0_RG_USB20_INTR_EN BIT(5) BIT 52 drivers/phy/mediatek/phy-mtk-tphy.c #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) BIT 55 drivers/phy/mediatek/phy-mtk-tphy.c #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) BIT 58 drivers/phy/mediatek/phy-mtk-tphy.c #define PA5_RG_U2_HS_100U_U3_EN BIT(11) BIT 61 drivers/phy/mediatek/phy-mtk-tphy.c #define PA6_RG_U2_BC11_SW_EN BIT(23) BIT 62 drivers/phy/mediatek/phy-mtk-tphy.c #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) BIT 67 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_USB20_GPIO_CTL BIT(9) BIT 68 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_USB20_GPIO_MODE BIT(8) BIT 72 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) BIT 75 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_FORCE_UART_EN BIT(26) BIT 76 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_FORCE_DATAIN BIT(23) BIT 77 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_FORCE_DM_PULLDOWN BIT(21) BIT 78 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_FORCE_DP_PULLDOWN BIT(20) BIT 79 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_FORCE_XCVRSEL BIT(19) BIT 80 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_FORCE_SUSPENDM BIT(18) BIT 81 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_FORCE_TERMSEL BIT(17) BIT 84 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_DMPULLDOWN BIT(7) BIT 85 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_DPPULLDOWN BIT(6) BIT 88 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_SUSPENDM BIT(3) BIT 89 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_TERMSEL BIT(2) BIT 97 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_UART_EN BIT(16) BIT 98 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_FORCE_IDDIG BIT(9) BIT 99 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_VBUSVALID BIT(5) BIT 100 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_SESSEND BIT(4) BIT 101 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_AVALID BIT(2) BIT 102 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_IDDIG BIT(1) BIT 105 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_CHGDT_EN BIT(0) BIT 108 drivers/phy/mediatek/phy-mtk-tphy.c #define P3C_REG_IP_SW_RST BIT(31) BIT 109 drivers/phy/mediatek/phy-mtk-tphy.c #define P3C_MCU_BUS_CK_GATE_EN BIT(30) BIT 110 drivers/phy/mediatek/phy-mtk-tphy.c #define P3C_FORCE_IP_SW_RST BIT(29) BIT 113 drivers/phy/mediatek/phy-mtk-tphy.c #define P3C_RG_SWRST_U3_PHYD BIT(25) BIT 114 drivers/phy/mediatek/phy-mtk-tphy.c #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) BIT 186 drivers/phy/mediatek/phy-mtk-tphy.c #define XC3_RG_U3_XTAL_RX_PWD BIT(9) BIT 187 drivers/phy/mediatek/phy-mtk-tphy.c #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) BIT 192 drivers/phy/mediatek/phy-mtk-tphy.c #define P2F_RG_FREQDET_EN BIT(24) BIT 199 drivers/phy/mediatek/phy-mtk-tphy.c #define P2F_USB_FM_VALID BIT(0) BIT 200 drivers/phy/mediatek/phy-mtk-tphy.c #define P2F_RG_FRCK_EN BIT(8) BIT 16 drivers/phy/mediatek/phy-mtk-ufs.c #define FRC_PLL_ISO_EN BIT(8) BIT 17 drivers/phy/mediatek/phy-mtk-ufs.c #define PLL_ISO_EN BIT(9) BIT 18 drivers/phy/mediatek/phy-mtk-ufs.c #define FRC_FRC_PWR_ON BIT(10) BIT 19 drivers/phy/mediatek/phy-mtk-ufs.c #define PLL_PWR_ON BIT(11) BIT 22 drivers/phy/mediatek/phy-mtk-ufs.c #define FSM_DIFZ_FRC BIT(18) BIT 25 drivers/phy/mediatek/phy-mtk-ufs.c #define FRC_RX_SQ_EN BIT(0) BIT 26 drivers/phy/mediatek/phy-mtk-ufs.c #define RX_SQ_EN BIT(1) BIT 29 drivers/phy/mediatek/phy-mtk-ufs.c #define FRC_CDR_PWR_ON BIT(17) BIT 30 drivers/phy/mediatek/phy-mtk-ufs.c #define CDR_PWR_ON BIT(18) BIT 31 drivers/phy/mediatek/phy-mtk-ufs.c #define FRC_CDR_ISO_EN BIT(19) BIT 32 drivers/phy/mediatek/phy-mtk-ufs.c #define CDR_ISO_EN BIT(20) BIT 37 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2F_RG_FREQDET_EN BIT(24) BIT 44 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2F_RG_FRCK_EN BIT(8) BIT 45 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2F_USB_FM_VALID BIT(0) BIT 48 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2A0_RG_INTR_EN BIT(5) BIT 59 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2A5_RG_HSTX_SRCAL_EN BIT(15) BIT 64 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2A6_RG_BC11_SW_EN BIT(23) BIT 65 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2A6_RG_OTG_VBUSCMP_EN BIT(20) BIT 68 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2D_FORCE_IDDIG BIT(9) BIT 69 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2D_RG_VBUSVALID BIT(5) BIT 70 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2D_RG_SESSEND BIT(4) BIT 71 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2D_RG_AVALID BIT(2) BIT 72 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2D_RG_IDDIG BIT(1) BIT 41 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_IDPULSE BIT(15) BIT 42 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_ID100KPU BIT(14) BIT 43 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_IDPUCNTRL BIT(13) BIT 44 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_IDPU BIT(12) BIT 45 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_IDPD BIT(11) BIT 46 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_VBUSCHRGTMR3 BIT(10) BIT 47 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_VBUSCHRGTMR2 BIT(9) BIT 48 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_VBUSCHRGTMR1 BIT(8) BIT 49 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_VBUSCHRGTMR0 BIT(7) BIT 50 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_VBUSPU BIT(6) BIT 51 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_VBUSPD BIT(5) BIT 52 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_DMPD BIT(4) BIT 53 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_DPPD BIT(3) BIT 54 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_DM1K5PU BIT(2) BIT 55 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_DP1K5PU BIT(1) BIT 56 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_DP150KPU BIT(0) BIT 59 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_ZHSDRV1 BIT(15) BIT 60 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_ZHSDRV0 BIT(14) BIT 61 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_DPLLCLKREQ BIT(13) BIT 62 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_SE0CONN BIT(12) BIT 63 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_UARTTXTRI BIT(11) BIT 64 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_UARTSWAP BIT(10) BIT 65 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_UARTMUX1 BIT(9) BIT 66 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_UARTMUX0 BIT(8) BIT 67 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_ULPISTPLOW BIT(7) BIT 68 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_TXENPOL BIT(6) BIT 69 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_USBXCVREN BIT(5) BIT 70 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_USBCNTRL BIT(4) BIT 71 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_USBSUSPEND BIT(3) BIT 72 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_EMUMODE2 BIT(2) BIT 73 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_EMUMODE1 BIT(1) BIT 74 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_EMUMODE0 BIT(0) BIT 77 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_SPARE_898_15 BIT(15) BIT 78 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_IHSTX03 BIT(14) BIT 79 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_IHSTX02 BIT(13) BIT 80 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_IHSTX01 BIT(12) BIT 81 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_IHSTX0 BIT(11) BIT 82 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_IDPU_SPI BIT(10) BIT 83 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_UNUSED_898_9 BIT(9) BIT 84 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_VBUSSTBY_EN BIT(8) BIT 85 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_VBUSEN_SPI BIT(7) BIT 86 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_VBUSPU_SPI BIT(6) BIT 87 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_VBUSPD_SPI BIT(5) BIT 88 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_DMPD_SPI BIT(4) BIT 89 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_DPPD_SPI BIT(3) BIT 90 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_SUSPEND_SPI BIT(2) BIT 91 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_PU_SPI BIT(1) BIT 92 drivers/phy/motorola/phy-cpcap-usb.c #define CPCAP_BIT_ULPI_SPI_SEL BIT(0) BIT 184 drivers/phy/motorola/phy-cpcap-usb.c s->id_ground = val & BIT(15); BIT 185 drivers/phy/motorola/phy-cpcap-usb.c s->id_float = val & BIT(14); BIT 186 drivers/phy/motorola/phy-cpcap-usb.c s->vbusov = val & BIT(11); BIT 192 drivers/phy/motorola/phy-cpcap-usb.c s->vbusvld = val & BIT(3); BIT 193 drivers/phy/motorola/phy-cpcap-usb.c s->sessvld = val & BIT(2); BIT 194 drivers/phy/motorola/phy-cpcap-usb.c s->sessend = val & BIT(1); BIT 195 drivers/phy/motorola/phy-cpcap-usb.c s->se1 = val & BIT(0); BIT 201 drivers/phy/motorola/phy-cpcap-usb.c s->dm = val & BIT(1); BIT 202 drivers/phy/motorola/phy-cpcap-usb.c s->dp = val & BIT(0); BIT 41 drivers/phy/mscc/phy-ocelot-serdes.c HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(BIT(macro))); BIT 273 drivers/phy/mscc/phy-ocelot-serdes.c HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(BIT(macro))); BIT 19 drivers/phy/phy-lpc18xx-usb-otg.c #define LPC18XX_CREG_CREG0_USB0PHY BIT(5) BIT 30 drivers/phy/phy-pistachio-usb.c #define USB_PHY_STATUS_RX_PHY_CLK BIT(9) BIT 31 drivers/phy/phy-pistachio-usb.c #define USB_PHY_STATUS_RX_UTMI_CLK BIT(8) BIT 32 drivers/phy/phy-pistachio-usb.c #define USB_PHY_STATUS_VBUS_FAULT BIT(7) BIT 60 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c #define UNIPHY_PLL_LOCK BIT(0) BIT 61 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c #define SATA_PHY_TX_CAL BIT(0) BIT 62 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c #define SATA_PHY_RX_CAL BIT(0) BIT 76 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~BIT(1); BIT 83 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~BIT(0); BIT 88 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= BIT(0); BIT 95 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= BIT(0); BIT 139 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~BIT(1); BIT 144 drivers/phy/qualcomm/phy-qcom-pcie2.c val &= ~BIT(0); BIT 164 drivers/phy/qualcomm/phy-qcom-pcie2.c !(val & BIT(0)), 1000, 10); BIT 178 drivers/phy/qualcomm/phy-qcom-pcie2.c val |= BIT(0); BIT 28 drivers/phy/qualcomm/phy-qcom-qmp.c #define SW_RESET BIT(0) BIT 30 drivers/phy/qualcomm/phy-qcom-qmp.c #define SW_PWRDN BIT(0) BIT 31 drivers/phy/qualcomm/phy-qcom-qmp.c #define REFCLK_DRV_DSBL BIT(1) BIT 33 drivers/phy/qualcomm/phy-qcom-qmp.c #define SERDES_START BIT(0) BIT 34 drivers/phy/qualcomm/phy-qcom-qmp.c #define PCS_START BIT(1) BIT 35 drivers/phy/qualcomm/phy-qcom-qmp.c #define PLL_READY_GATE_EN BIT(3) BIT 37 drivers/phy/qualcomm/phy-qcom-qmp.c #define PHYSTATUS BIT(6) BIT 39 drivers/phy/qualcomm/phy-qcom-qmp.c #define PCS_READY BIT(0) BIT 43 drivers/phy/qualcomm/phy-qcom-qmp.c #define SW_DPPHY_RESET BIT(0) BIT 45 drivers/phy/qualcomm/phy-qcom-qmp.c #define SW_DPPHY_RESET_MUX BIT(1) BIT 47 drivers/phy/qualcomm/phy-qcom-qmp.c #define SW_USB3PHY_RESET BIT(2) BIT 49 drivers/phy/qualcomm/phy-qcom-qmp.c #define SW_USB3PHY_RESET_MUX BIT(3) BIT 52 drivers/phy/qualcomm/phy-qcom-qmp.c #define USB3_MODE BIT(0) /* enables USB3 mode */ BIT 53 drivers/phy/qualcomm/phy-qcom-qmp.c #define DP_MODE BIT(1) /* enables DP mode */ BIT 56 drivers/phy/qualcomm/phy-qcom-qmp.c #define ARCVR_DTCT_EN BIT(0) BIT 57 drivers/phy/qualcomm/phy-qcom-qmp.c #define ALFPS_DTCT_EN BIT(1) BIT 58 drivers/phy/qualcomm/phy-qcom-qmp.c #define ARCVR_DTCT_EVENT_SEL BIT(4) BIT 61 drivers/phy/qualcomm/phy-qcom-qmp.c #define IRQ_CLEAR BIT(0) BIT 64 drivers/phy/qualcomm/phy-qcom-qmp.c #define RCVR_DETECT BIT(0) BIT 67 drivers/phy/qualcomm/phy-qcom-qmp.c #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ BIT 26 drivers/phy/qualcomm/phy-qcom-qusb2.c #define CLK_REF_SEL BIT(7) BIT 35 drivers/phy/qualcomm/phy-qcom-qusb2.c #define PLL_LOCKED BIT(5) BIT 38 drivers/phy/qualcomm/phy-qcom-qusb2.c #define CORE_READY_STATUS BIT(0) BIT 41 drivers/phy/qualcomm/phy-qcom-qusb2.c #define CLAMP_N_EN BIT(5) BIT 42 drivers/phy/qualcomm/phy-qcom-qusb2.c #define FREEZIO_N BIT(1) BIT 43 drivers/phy/qualcomm/phy-qcom-qusb2.c #define POWER_DOWN BIT(0) BIT 46 drivers/phy/qualcomm/phy-qcom-qusb2.c #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) BIT 47 drivers/phy/qualcomm/phy-qcom-qusb2.c #define PWR_CTRL1_CLAMP_N_EN BIT(1) BIT 49 drivers/phy/qualcomm/phy-qcom-qusb2.c #define QUSB2PHY_REFCLK_ENABLE BIT(0) BIT 51 drivers/phy/qualcomm/phy-qcom-qusb2.c #define PHY_CLK_SCHEME_SEL BIT(0) BIT 54 drivers/phy/qualcomm/phy-qcom-qusb2.c #define DMSE_INTR_HIGH_SEL BIT(4) BIT 55 drivers/phy/qualcomm/phy-qcom-qusb2.c #define DPSE_INTR_HIGH_SEL BIT(3) BIT 56 drivers/phy/qualcomm/phy-qcom-qusb2.c #define CHG_DET_INTR_EN BIT(2) BIT 57 drivers/phy/qualcomm/phy-qcom-qusb2.c #define DMSE_INTR_EN BIT(1) BIT 58 drivers/phy/qualcomm/phy-qcom-qusb2.c #define DPSE_INTR_EN BIT(0) BIT 61 drivers/phy/qualcomm/phy-qcom-qusb2.c #define CORE_PLL_EN_FROM_RESET BIT(4) BIT 62 drivers/phy/qualcomm/phy-qcom-qusb2.c #define CORE_RESET BIT(5) BIT 63 drivers/phy/qualcomm/phy-qcom-qusb2.c #define CORE_RESET_MUX BIT(6) BIT 72 drivers/phy/qualcomm/phy-qcom-qusb2.c #define PREEMPH_WIDTH_HALF_BIT BIT(2) BIT 246 drivers/phy/qualcomm/phy-qcom-qusb2.c .autoresume_en = BIT(3), BIT 257 drivers/phy/qualcomm/phy-qcom-qusb2.c .autoresume_en = BIT(0), BIT 270 drivers/phy/qualcomm/phy-qcom-qusb2.c .autoresume_en = BIT(0), BIT 82 drivers/phy/qualcomm/phy-qcom-ufs-i.h #define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE BIT(0) BIT 17 drivers/phy/qualcomm/phy-qcom-usb-hs.c # define ULPI_PWR_OTG_COMP_DISABLE BIT(0) BIT 20 drivers/phy/qualcomm/phy-qcom-usb-hs.c # define ULPI_MISC_A_VBUSVLDEXTSEL BIT(1) BIT 21 drivers/phy/qualcomm/phy-qcom-usb-hs.c # define ULPI_MISC_A_VBUSVLDEXT BIT(0) BIT 40 drivers/phy/ralink/phy-ralink-usb.c #define RT_RSTCTRL_UDEV BIT(25) BIT 41 drivers/phy/ralink/phy-ralink-usb.c #define RT_RSTCTRL_UHST BIT(22) BIT 42 drivers/phy/ralink/phy-ralink-usb.c #define RT_SYSCFG1_USB0_HOST_MODE BIT(10) BIT 44 drivers/phy/ralink/phy-ralink-usb.c #define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25) BIT 45 drivers/phy/ralink/phy-ralink-usb.c #define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22) BIT 46 drivers/phy/ralink/phy-ralink-usb.c #define RT_CLKCFG1_UPHY1_CLK_EN BIT(20) BIT 47 drivers/phy/ralink/phy-ralink-usb.c #define RT_CLKCFG1_UPHY0_CLK_EN BIT(18) BIT 49 drivers/phy/ralink/phy-ralink-usb.c #define USB_PHY_UTMI_8B60M BIT(1) BIT 50 drivers/phy/ralink/phy-ralink-usb.c #define UDEV_WAKEUP BIT(0) BIT 20 drivers/phy/renesas/phy-rcar-gen3-pcie.c #define PHY_CTRL_PHY_PWDN BIT(2) BIT 41 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_INT_ENABLE_UCOM_INTEN BIT(3) BIT 42 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_INT_ENABLE_USBH_INTB_EN BIT(2) /* For EHCI */ BIT 43 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_INT_ENABLE_USBH_INTA_EN BIT(1) /* For OHCI */ BIT 46 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_USBCTR_DIRPD BIT(2) BIT 47 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_USBCTR_PLL_RST BIT(1) BIT 56 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */ BIT 59 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_OBINT_SESSVLDCHG BIT(12) BIT 60 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_OBINT_IDDIGCHG BIT(11) BIT 65 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_VBCTRL_OCCLREN BIT(16) BIT 66 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_VBCTRL_DRVVBUSSEL BIT(8) BIT 69 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_LINECTRL1_DPRPD_EN BIT(19) BIT 70 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_LINECTRL1_DP_RPD BIT(18) BIT 71 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_LINECTRL1_DMRPD_EN BIT(17) BIT 72 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_LINECTRL1_DM_RPD BIT(16) BIT 73 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_LINECTRL1_OPMODE_NODRV BIT(6) BIT 76 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_ADPCTRL_OTGSESSVLD BIT(20) BIT 77 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_ADPCTRL_IDDIG BIT(19) BIT 78 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */ BIT 79 drivers/phy/renesas/phy-rcar-gen3-usb2.c #define USB2_ADPCTRL_DRVVBUS BIT(4) BIT 31 drivers/phy/renesas/phy-rcar-gen3-usb3.c #define CLKSET1_PHYRESET BIT(4) /* 1: reset */ BIT 32 drivers/phy/renesas/phy-rcar-gen3-usb3.c #define CLKSET1_REF_CLKDIV BIT(3) /* 1: USB_EXTAL */ BIT 33 drivers/phy/renesas/phy-rcar-gen3-usb3.c #define CLKSET1_PRIVATE_2_1 BIT(1) /* Write B'01 */ BIT 34 drivers/phy/renesas/phy-rcar-gen3-usb3.c #define CLKSET1_REF_CLK_SEL BIT(0) /* 1: USB3S0_CLK_P */ BIT 37 drivers/phy/renesas/phy-rcar-gen3-usb3.c #define SSC_SET_SSC_EN BIT(12) BIT 44 drivers/phy/renesas/phy-rcar-gen3-usb3.c #define PHY_ENABLE_RESET_EN BIT(4) BIT 47 drivers/phy/renesas/phy-rcar-gen3-usb3.c #define VBUS_EN_VBUS_EN BIT(1) BIT 19 drivers/phy/rockchip/phy-rockchip-dp.c #define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20) BIT 20 drivers/phy/rockchip/phy-rockchip-dp.c #define GRF_EDP_REF_CLK_SEL_INTER BIT(4) BIT 22 drivers/phy/rockchip/phy-rockchip-dp.c #define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21) BIT 24 drivers/phy/rockchip/phy-rockchip-dp.c #define GRF_EDP_PHY_SIDDQ_OFF BIT(5) BIT 27 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_REFCLK_SEL_PCLK BIT(0) BIT 29 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_BYPASS_RXSENSE_EN BIT(2) BIT 30 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_BYPASS_PWRON_EN BIT(1) BIT 31 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_BYPASS_PLLPD_EN BIT(0) BIT 33 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_BYPASS_PDATA_EN BIT(4) BIT 34 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PDATAEN_DISABLE BIT(0) BIT 36 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_BYPASS_AUTO_TERM_RES_CAL BIT(7) BIT 41 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_CTRL_MANUAL BIT(0) BIT 43 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_POWER_DOWN BIT(5) BIT 44 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_POWER_DOWN BIT(4) BIT 45 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_RXSENSE_CLK_CH_ENABLE BIT(3) BIT 46 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_RXSENSE_DATA_CH2_ENABLE BIT(2) BIT 47 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_RXSENSE_DATA_CH1_ENABLE BIT(1) BIT 48 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_RXSENSE_DATA_CH0_ENABLE BIT(0) BIT 50 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_BANDGAP_ENABLE BIT(4) BIT 53 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_FB_DIV_8_MASK BIT(7) BIT 55 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PCLK_VCO_DIV_5_MASK BIT(5) BIT 80 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_LOCK_STATUS BIT(0) BIT 88 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_FB_DIV_8_MASK BIT(7) BIT 92 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_LOCK_STATUS BIT(0) BIT 115 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_BYPASS_RXSENSE_EN BIT(2) BIT 116 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_BYPASS_POWERON_EN BIT(1) BIT 117 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_BYPASS_PLLPD_EN BIT(0) BIT 119 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_INT_POL_HIGH BIT(7) BIT 120 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_BYPASS_PDATA_EN BIT(4) BIT 121 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PDATA_EN BIT(0) BIT 129 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_INT_AGND_LOW_PULSE_LOCKED BIT(3) BIT 130 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_INT_RXSENSE_LOW_PULSE_LOCKED BIT(2) BIT 131 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_INT_VSS_AGND_ESD_DET BIT(1) BIT 132 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_INT_AGND_VSS_ESD_DET BIT(0) BIT 134 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PCLK_VCO_DIV_5_MASK BIT(1) BIT 136 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_POWER_DOWN BIT(0) BIT 142 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_SPREAD_SPECTRUM_MOD_DOWN BIT(7) BIT 143 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_SPREAD_SPECTRUM_MOD_DISABLE BIT(6) BIT 169 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_LOCK_STATUS BIT(0) BIT 172 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_POST_PLL_REFCLK_SEL_TMDS BIT(1) BIT 173 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_POST_PLL_POWER_DOWN BIT(0) BIT 185 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_POST_PLL_LOCK_STATUS BIT(0) BIT 187 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_BANDGAP_ENABLE BIT(2) BIT 189 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_CLK_DRIVER_EN BIT(3) BIT 190 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_D2_DRIVER_EN BIT(2) BIT 191 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_D1_DRIVER_EN BIT(1) BIT 192 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_D0_DRIVER_EN BIT(0) BIT 198 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_BYPASS_TERM_RESISTOR_CALIB BIT(7) BIT 215 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_TERM_RESIST_75 BIT(5) BIT 216 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_TERM_RESIST_150 BIT(4) BIT 217 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_TERM_RESIST_300 BIT(3) BIT 218 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_TERM_RESIST_600 BIT(2) BIT 219 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_TERM_RESIST_1000 BIT(1) BIT 220 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_TERM_RESIST_2000 BIT(0) BIT 42 drivers/phy/rockchip/phy-rockchip-pcie.c #define PHY_CFG_SEPE_RATE BIT(3) BIT 43 drivers/phy/rockchip/phy-rockchip-pcie.c #define PHY_CFG_PLL_100M BIT(3) BIT 44 drivers/phy/rockchip/phy-rockchip-pcie.c #define PHY_PLL_LOCKED BIT(9) BIT 45 drivers/phy/rockchip/phy-rockchip-pcie.c #define PHY_PLL_OUTPUT BIT(10) BIT 103 drivers/phy/rockchip/phy-rockchip-typec.c #define CMN_TXPXCAL_START BIT(15) BIT 104 drivers/phy/rockchip/phy-rockchip-typec.c #define CMN_TXPXCAL_DONE BIT(14) BIT 105 drivers/phy/rockchip/phy-rockchip-typec.c #define CMN_TXPXCAL_NO_RESPONSE BIT(13) BIT 106 drivers/phy/rockchip/phy-rockchip-typec.c #define CMN_TXPXCAL_CURRENT_RESPONSE BIT(12) BIT 190 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DP_AUX_EN BIT(15) BIT 191 drivers/phy/rockchip/phy-rockchip-typec.c #define AUXDA_SE_EN BIT(14) BIT 192 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_CAL_LATCH_EN BIT(13) BIT 193 drivers/phy/rockchip/phy-rockchip-typec.c #define AUXDA_POLARITY BIT(12) BIT 194 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_POWER_ISOLATION_EN BIT(11) BIT 195 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_POWER_EN_PH_2_N BIT(10) BIT 196 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_POWER_EN_PH_1_N BIT(9) BIT 197 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_BGREF_EN BIT(8) BIT 198 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_LDO_EN BIT(7) BIT 199 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DECAP_EN_DEL BIT(6) BIT 200 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DECAP_EN BIT(5) BIT 201 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_UPHY_SUPPLY_EN_DEL BIT(4) BIT 202 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_UPHY_SUPPLY_EN BIT(3) BIT 203 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_LOW_LEAKAGE_EN BIT(2) BIT 204 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_IDLE_LOWI_EN BIT(1) BIT 205 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_CMN_MODE_EN BIT(0) BIT 209 drivers/phy/rockchip/phy-rockchip-typec.c #define AUXDA_DEBOUNCING_CLK BIT(15) BIT 210 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_LPBK_RECOVERED_CLK_EN BIT(14) BIT 211 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_LPBK_ISI_GEN_EN BIT(13) BIT 212 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_LPBK_SERIAL_EN BIT(12) BIT 213 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_LPBK_LINE_EN BIT(11) BIT 214 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_LDO_REDC_SINKIQ BIT(10) BIT 215 drivers/phy/rockchip/phy-rockchip-typec.c #define XCVR_DECAP_EN_DEL BIT(9) BIT 216 drivers/phy/rockchip/phy-rockchip-typec.c #define XCVR_DECAP_EN BIT(8) BIT 217 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_MPHY_ENABLE_HS_NT BIT(7) BIT 218 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_MPHY_SA_MODE BIT(6) BIT 219 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_LDO_RBYR_FB_EN BIT(5) BIT 220 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_RST_PULL_DOWN BIT(4) BIT 221 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_LDO_BG_FB_EN BIT(3) BIT 222 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_LDO_BG_REF_EN BIT(2) BIT 223 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_PREDRV_EN_DEL BIT(1) BIT 224 drivers/phy/rockchip/phy-rockchip-typec.c #define TXDA_DRV_PREDRV_EN BIT(0) BIT 228 drivers/phy/rockchip/phy-rockchip-typec.c #define TX_HIGH_Z BIT(6) BIT 231 drivers/phy/rockchip/phy-rockchip-typec.c #define LOW_POWER_SWING_EN BIT(2) BIT 232 drivers/phy/rockchip/phy-rockchip-typec.c #define TX_FCM_DRV_MAIN_EN BIT(1) BIT 233 drivers/phy/rockchip/phy-rockchip-typec.c #define TX_FCM_FULL_MARGIN BIT(0) BIT 237 drivers/phy/rockchip/phy-rockchip-typec.c #define TX_HIGH_Z_TM_EN BIT(15) BIT 320 drivers/phy/rockchip/phy-rockchip-typec.c #define CMN_READY BIT(0) BIT 322 drivers/phy/rockchip/phy-rockchip-typec.c #define DP_PLL_CLOCK_ENABLE BIT(2) BIT 323 drivers/phy/rockchip/phy-rockchip-typec.c #define DP_PLL_ENABLE BIT(0) BIT 328 drivers/phy/rockchip/phy-rockchip-typec.c #define DP_MODE_A0 BIT(4) BIT 329 drivers/phy/rockchip/phy-rockchip-typec.c #define DP_MODE_A2 BIT(6) BIT 339 drivers/phy/rockchip/phy-rockchip-typec.c #define MODE_UFP_USB BIT(0) BIT 340 drivers/phy/rockchip/phy-rockchip-typec.c #define MODE_DFP_USB BIT(1) BIT 341 drivers/phy/rockchip/phy-rockchip-typec.c #define MODE_DFP_DP BIT(2) BIT 900 drivers/phy/rockchip/phy-rockchip-typec.c if (!(val & BIT(reg->enable_bit))) { BIT 32 drivers/phy/rockchip/phy-rockchip-usb.c #define UOC_CON0_SIDDQ BIT(13) BIT 33 drivers/phy/rockchip/phy-rockchip-usb.c #define UOC_CON0_DISABLE BIT(4) BIT 34 drivers/phy/rockchip/phy-rockchip-usb.c #define UOC_CON0_COMMON_ON_N BIT(0) BIT 37 drivers/phy/rockchip/phy-rockchip-usb.c #define UOC_CON2_SOFT_CON_SEL BIT(2) BIT 41 drivers/phy/rockchip/phy-rockchip-usb.c #define UOC_CON3_UTMI_TERMSEL_FULLSPEED BIT(5) BIT 46 drivers/phy/rockchip/phy-rockchip-usb.c #define UOC_CON3_UTMI_SUSPENDN BIT(0) BIT 367 drivers/phy/rockchip/phy-rockchip-usb.c #define RK3188_UOC0_CON0_BYPASSSEL BIT(9) BIT 368 drivers/phy/rockchip/phy-rockchip-usb.c #define RK3188_UOC0_CON0_BYPASSDMEN BIT(8) BIT 406 drivers/phy/rockchip/phy-rockchip-usb.c #define RK3288_UOC0_CON3_BYPASSDMEN BIT(6) BIT 407 drivers/phy/rockchip/phy-rockchip-usb.c #define RK3288_UOC0_CON3_BYPASSSEL BIT(7) BIT 174 drivers/phy/samsung/phy-exynos-mipi-video.c .resetn_val = BIT(0), BIT 183 drivers/phy/samsung/phy-exynos-mipi-video.c .resetn_val = BIT(0), BIT 192 drivers/phy/samsung/phy-exynos-mipi-video.c .resetn_val = BIT(1), BIT 201 drivers/phy/samsung/phy-exynos-mipi-video.c .resetn_val = BIT(1), BIT 210 drivers/phy/samsung/phy-exynos-mipi-video.c .resetn_val = BIT(0), BIT 39 drivers/phy/samsung/phy-exynos-pcie.c #define PCIE_PHY_COMMON_PD_CMN BIT(3) BIT 44 drivers/phy/samsung/phy-exynos-pcie.c #define PCIE_PHY_TRSV0_PD_TSV BIT(7) BIT 49 drivers/phy/samsung/phy-exynos-pcie.c #define PCIE_PHY_TRSV1_PD_TSV BIT(7) BIT 54 drivers/phy/samsung/phy-exynos-pcie.c #define PCIE_PHY_TRSV2_PD_TSV BIT(7) BIT 59 drivers/phy/samsung/phy-exynos-pcie.c #define PCIE_PHY_TRSV3_PD_TSV BIT(7) BIT 20 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_PHY0_SUSPEND BIT(0) BIT 21 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_PHY0_PWR BIT(3) BIT 22 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR BIT(4) BIT 23 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_PHY0_SLEEP BIT(5) BIT 30 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_PHY1_SUSPEND BIT(6) BIT 31 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_PHY1_PWR BIT(7) BIT 32 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_PHY1_SLEEP BIT(8) BIT 38 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND BIT(9) BIT 39 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_HSIC0_SLEEP BIT(10) BIT 44 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND BIT(11) BIT 45 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYPWR_HSIC1_SLEEP BIT(12) BIT 59 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP BIT(2) BIT 60 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYCLK_PHY0_COMMON_ON BIT(4) BIT 61 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_UPHYCLK_PHY1_COMMON_ON BIT(7) BIT 66 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_URSTCON_PHY0 BIT(0) BIT 67 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_URSTCON_OTG_HLINK BIT(1) BIT 68 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_URSTCON_OTG_PHYLINK BIT(2) BIT 69 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_URSTCON_PHY1_ALL BIT(3) BIT 70 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_URSTCON_PHY1_P0 BIT(4) BIT 71 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_URSTCON_PHY1_P1P2 BIT(5) BIT 72 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_URSTCON_HOST_LINK_ALL BIT(6) BIT 73 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_URSTCON_HOST_LINK_P0 BIT(7) BIT 74 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_URSTCON_HOST_LINK_P1 BIT(8) BIT 75 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_URSTCON_HOST_LINK_P2 BIT(9) BIT 79 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_USB_ISOL_DEVICE BIT(0) BIT 81 drivers/phy/samsung/phy-exynos4210-usb2.c #define EXYNOS_4210_USB_ISOL_HOST BIT(0) BIT 20 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0) BIT 21 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_PHY0_PWR BIT(3) BIT 22 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR BIT(4) BIT 23 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_PHY0_SLEEP BIT(5) BIT 30 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND BIT(6) BIT 31 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_PHY1_PWR BIT(7) BIT 32 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_PHY1_SLEEP BIT(8) BIT 38 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND BIT(9) BIT 39 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_HSIC0_PWR BIT(10) BIT 40 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP BIT(11) BIT 46 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND BIT(12) BIT 47 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_HSIC1_PWR BIT(13) BIT 48 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP BIT(14) BIT 69 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYCLK_PHY0_ID_PULLUP BIT(3) BIT 70 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYCLK_PHY0_COMMON_ON BIT(4) BIT 71 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON BIT(7) BIT 84 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_PHY0 BIT(0) BIT 85 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_OTG_HLINK BIT(1) BIT 86 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_OTG_PHYLINK BIT(2) BIT 87 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_HOST_PHY BIT(3) BIT 98 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_PHY1 BIT(4) BIT 99 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_HSIC0 BIT(6) BIT 100 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_HSIC1 BIT(5) BIT 101 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_HOST_LINK_ALL BIT(7) BIT 102 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_HOST_LINK_P0 BIT(10) BIT 103 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_HOST_LINK_P1 BIT(9) BIT 104 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_URSTCON_HOST_LINK_P2 BIT(8) BIT 108 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_USB_ISOL_OTG BIT(0) BIT 110 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_USB_ISOL_HSIC0 BIT(0) BIT 112 drivers/phy/samsung/phy-exynos4x12-usb2.c #define EXYNOS_4x12_USB_ISOL_HSIC1 BIT(0) BIT 41 drivers/phy/samsung/phy-exynos5-usbdrd.c #define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27) BIT 45 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYUTMI_OTGDISABLE BIT(6) BIT 46 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYUTMI_FORCESUSPEND BIT(1) BIT 47 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYUTMI_FORCESLEEP BIT(0) BIT 53 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYCLKRST_EN_UTMISUSPEND BIT(31) BIT 61 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYCLKRST_SSC_EN BIT(20) BIT 62 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYCLKRST_REF_SSP_EN BIT(19) BIT 63 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYCLKRST_REF_CLKDIV2 BIT(18) BIT 80 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYCLKRST_RETENABLEN BIT(4) BIT 86 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYCLKRST_PORTRESET BIT(1) BIT 87 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYCLKRST_COMMONONN BIT(0) BIT 90 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYREG0_SSC_REF_CLK_SEL BIT(21) BIT 91 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYREG0_SSC_RANGE BIT(20) BIT 92 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYREG0_CR_WRITE BIT(19) BIT 93 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYREG0_CR_READ BIT(18) BIT 95 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYREG0_CR_CAP_DATA BIT(1) BIT 96 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYREG0_CR_CAP_ADDR BIT(0) BIT 100 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYREG1_CR_ACK BIT(0) BIT 104 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYPARAM0_REF_USE_PAD BIT(31) BIT 117 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYTEST_POWERDOWN_SSP BIT(3) BIT 118 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYTEST_POWERDOWN_HSP BIT(2) BIT 124 drivers/phy/samsung/phy-exynos5-usbdrd.c #define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2) BIT 25 drivers/phy/samsung/phy-exynos5250-sata.c #define EXYNOS5_SATAPHY_PMU_ENABLE BIT(0) BIT 27 drivers/phy/samsung/phy-exynos5250-sata.c #define RESET_GLOBAL_RST_N BIT(0) BIT 28 drivers/phy/samsung/phy-exynos5250-sata.c #define RESET_CMN_RST_N BIT(1) BIT 29 drivers/phy/samsung/phy-exynos5250-sata.c #define RESET_CMN_BLOCK_RST_N BIT(2) BIT 30 drivers/phy/samsung/phy-exynos5250-sata.c #define RESET_CMN_I2C_RST_N BIT(3) BIT 31 drivers/phy/samsung/phy-exynos5250-sata.c #define RESET_TX_RX_PIPE_RST_N BIT(4) BIT 32 drivers/phy/samsung/phy-exynos5250-sata.c #define RESET_TX_RX_BLOCK_RST_N BIT(5) BIT 33 drivers/phy/samsung/phy-exynos5250-sata.c #define RESET_TX_RX_I2C_RST_N (BIT(6) | BIT(7)) BIT 36 drivers/phy/samsung/phy-exynos5250-sata.c #define SATA_SPD_GEN3 BIT(1) BIT 38 drivers/phy/samsung/phy-exynos5250-sata.c #define CTRL0_P0_PHY_CALIBRATED_SEL BIT(9) BIT 39 drivers/phy/samsung/phy-exynos5250-sata.c #define CTRL0_P0_PHY_CALIBRATED BIT(8) BIT 41 drivers/phy/samsung/phy-exynos5250-sata.c #define PHCTRLM_REF_RATE BIT(1) BIT 42 drivers/phy/samsung/phy-exynos5250-sata.c #define PHCTRLM_HIGH_SPEED BIT(0) BIT 44 drivers/phy/samsung/phy-exynos5250-sata.c #define PHSTATM_PLL_LOCKED BIT(0) BIT 31 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL BIT(31) BIT 38 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNIN BIT(11) BIT 39 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE BIT(10) BIT 40 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N BIT(9) BIT 45 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ BIT(6) BIT 46 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP BIT(5) BIT 47 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND BIT(4) BIT 48 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_WORDINTERFACE BIT(3) BIT 49 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST BIT(2) BIT 50 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST BIT(1) BIT 51 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST BIT(0) BIT 65 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HSICPHYCTRLX_SIDDQ BIT(6) BIT 66 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HSICPHYCTRLX_FORCESLEEP BIT(5) BIT 67 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HSICPHYCTRLX_FORCESUSPEND BIT(4) BIT 68 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HSICPHYCTRLX_WORDINTERFACE BIT(3) BIT 69 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HSICPHYCTRLX_UTMISWRST BIT(2) BIT 70 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HSICPHYCTRLX_PHYSWRST BIT(0) BIT 74 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN BIT(29) BIT 75 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTEHCICTRL_ENAINCR4 BIT(28) BIT 76 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTEHCICTRL_ENAINCR8 BIT(27) BIT 77 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTEHCICTRL_ENAINCR16 BIT(26) BIT 78 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTEHCICTRL_AUTOPPDONOVRCUREN BIT(25) BIT 91 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTEHCICTRL_SIMULATIONMODE BIT(0) BIT 98 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVALEN BIT(0) BIT 102 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET BIT(14) BIT 103 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG BIT(13) BIT 104 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USBOTGSYS_PHY_SW_RST BIT(12) BIT 108 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USBOTGSYS_ID_PULLUP BIT(8) BIT 109 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USBOTGSYS_COMMON_ON BIT(7) BIT 113 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USBOTGSYS_FORCE_SLEEP BIT(3) BIT 114 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USBOTGSYS_OTGDISABLE BIT(2) BIT 115 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG BIT(1) BIT 116 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND BIT(0) BIT 120 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USB_ISOL_OTG BIT(0) BIT 122 drivers/phy/samsung/phy-exynos5250-usb2.c #define EXYNOS_5250_USB_ISOL_HOST BIT(0) BIT 19 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_UPHYPWR_PHY0_SUSPEND BIT(0) BIT 20 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_UPHYPWR_PHY0_PWR BIT(3) BIT 21 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_UPHYPWR_PHY0_OTG_PWR BIT(4) BIT 27 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_UPHYPWR_PHY1_SUSPEND BIT(6) BIT 28 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_UPHYPWR_PHY1_PWR BIT(7) BIT 41 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_UPHYCLK_PHY0_ID_PULLUP BIT(2) BIT 42 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_UPHYCLK_PHY0_COMMON_ON BIT(4) BIT 43 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_UPHYCLK_PHY1_COMMON_ON BIT(7) BIT 48 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_URSTCON_PHY0 BIT(0) BIT 49 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_URSTCON_OTG_HLINK BIT(1) BIT 50 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_URSTCON_OTG_PHYLINK BIT(2) BIT 51 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_URSTCON_PHY1_ALL BIT(3) BIT 52 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_URSTCON_HOST_LINK_ALL BIT(4) BIT 56 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_USB_ISOL_DEVICE BIT(0) BIT 57 drivers/phy/samsung/phy-s5pv210-usb2.c #define S5PV210_USB_ISOL_HOST BIT(1) BIT 26 drivers/phy/socionext/phy-uniphier-pcie.c #define TESTI_WR_EN BIT(0) BIT 29 drivers/phy/socionext/phy-uniphier-pcie.c #define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */ BIT 30 drivers/phy/socionext/phy-uniphier-pcie.c #define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */ BIT 34 drivers/phy/socionext/phy-uniphier-pcie.c #define SG_USBPCIESEL_PCIE BIT(0) BIT 37 drivers/phy/socionext/phy-uniphier-pcie.c #define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */ BIT 37 drivers/phy/socionext/phy-uniphier-usb3hs.c #define HSPHY_CFG1_DAT_EN BIT(29) BIT 38 drivers/phy/socionext/phy-uniphier-usb3hs.c #define HSPHY_CFG1_ADR_EN BIT(28) BIT 28 drivers/phy/socionext/phy-uniphier-usb3ss.c #define TESTI_WR_EN BIT(0) BIT 28 drivers/phy/st/phy-miphy28lp.c #define RST_APPLI_SW BIT(0) BIT 29 drivers/phy/st/phy-miphy28lp.c #define RST_CONF_SW BIT(1) BIT 30 drivers/phy/st/phy-miphy28lp.c #define RST_MACRO_SW BIT(2) BIT 33 drivers/phy/st/phy-miphy28lp.c #define RST_PLL_SW BIT(0) BIT 34 drivers/phy/st/phy-miphy28lp.c #define RST_COMP_SW BIT(2) BIT 37 drivers/phy/st/phy-miphy28lp.c #define PHY_RDY BIT(0) BIT 38 drivers/phy/st/phy-miphy28lp.c #define HFC_RDY BIT(1) BIT 39 drivers/phy/st/phy-miphy28lp.c #define HFC_PLL BIT(2) BIT 42 drivers/phy/st/phy-miphy28lp.c #define TERM_EN_SW BIT(2) BIT 43 drivers/phy/st/phy-miphy28lp.c #define DIS_LINK_RST BIT(3) BIT 44 drivers/phy/st/phy-miphy28lp.c #define AUTO_RST_RX BIT(4) BIT 45 drivers/phy/st/phy-miphy28lp.c #define PX_RX_POL BIT(5) BIT 48 drivers/phy/st/phy-miphy28lp.c #define TX_SEL BIT(6) BIT 49 drivers/phy/st/phy-miphy28lp.c #define SSC_SEL BIT(4) BIT 50 drivers/phy/st/phy-miphy28lp.c #define GENSEL_SEL BIT(0) BIT 54 drivers/phy/st/phy-miphy28lp.c #define SSC_EN_SW BIT(2) BIT 80 drivers/phy/st/phy-miphy28lp.c #define COMP_START BIT(6) BIT 83 drivers/phy/st/phy-miphy28lp.c #define COMP_DONE BIT(7) BIT 101 drivers/phy/st/phy-miphy28lp.c #define TX_SLEW_CAL_MAN_EN BIT(0) BIT 116 drivers/phy/st/phy-miphy28lp.c #define VGA_GAIN BIT(0) BIT 117 drivers/phy/st/phy-miphy28lp.c #define EQ_DC_GAIN BIT(2) BIT 118 drivers/phy/st/phy-miphy28lp.c #define EQ_BOOST_GAIN BIT(3) BIT 130 drivers/phy/st/phy-miphy28lp.c #define VGA_OFFSET_POLARITY BIT(4) BIT 131 drivers/phy/st/phy-miphy28lp.c #define OFFSET_COMPENSATION_EN BIT(6) BIT 144 drivers/phy/st/phy-miphy28lp.c #define EN_ULTRA_LOW_POWER BIT(0) BIT 145 drivers/phy/st/phy-miphy28lp.c #define EN_FIRST_HALF BIT(1) BIT 146 drivers/phy/st/phy-miphy28lp.c #define EN_SECOND_HALF BIT(2) BIT 147 drivers/phy/st/phy-miphy28lp.c #define EN_DIGIT_SIGNAL_CHECK BIT(3) BIT 157 drivers/phy/st/phy-miphy28lp.c #define SET_NEW_CHANGE BIT(1) BIT 163 drivers/phy/st/phy-miphy28lp.c #define START_ACT_FILT BIT(6) BIT 175 drivers/phy/st/phy-miphy28lp.c #define MIPHY_OSC_FORCE_EXT BIT(3) BIT 176 drivers/phy/st/phy-miphy28lp.c #define MIPHY_OSC_RDY BIT(5) BIT 180 drivers/phy/st/phy-miphy28lp.c #define MIPHY_CTRL_SYNC_D_EN BIT(2) BIT 25 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31) BIT 26 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30) BIT 27 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29) BIT 28 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27) BIT 29 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26) BIT 30 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25) BIT 31 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24) BIT 32 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23) BIT 33 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22) BIT 34 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21) BIT 35 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20) BIT 36 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19) BIT 37 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18) BIT 38 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17) BIT 39 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16) BIT 40 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11) BIT 41 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10) BIT 42 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9) BIT 43 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8) BIT 44 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7) BIT 45 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6) BIT 46 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5) BIT 47 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4) BIT 48 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3) BIT 49 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2) BIT 50 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1) BIT 51 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0) BIT 53 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29))) BIT 55 drivers/phy/st/phy-spear1310-miphy.c BIT((x + 29))) BIT 70 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31) BIT 71 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28) BIT 73 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15) BIT 74 drivers/phy/st/phy-spear1310-miphy.c #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12) BIT 23 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_PCM_CFG_SATA_POWER_EN BIT(11) BIT 28 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_PERIP1_SW_RSATA BIT(12) BIT 35 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT BIT(11) BIT 36 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_PCIE_CFG_POWERUP_RESET BIT(10) BIT 37 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_PCIE_CFG_CORE_CLK_EN BIT(9) BIT 38 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_PCIE_CFG_AUX_CLK_EN BIT(8) BIT 39 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_SATA_CFG_TX_CLK_EN BIT(4) BIT 40 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_SATA_CFG_RX_CLK_EN BIT(3) BIT 41 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_SATA_CFG_POWERUP_RESET BIT(2) BIT 42 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_SATA_CFG_PM_CLK_EN BIT(1) BIT 58 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_MIPHY_OSC_BYPASS_EXT BIT(31) BIT 59 drivers/phy/st/phy-spear1340-miphy.c #define SPEAR1340_MIPHY_CLK_REF_DIV2 BIT(27) BIT 25 drivers/phy/st/phy-stm32-usbphyc.c #define PLLEN BIT(26) BIT 26 drivers/phy/st/phy-stm32-usbphyc.c #define PLLSTRB BIT(27) BIT 27 drivers/phy/st/phy-stm32-usbphyc.c #define PLLSTRBYP BIT(28) BIT 28 drivers/phy/st/phy-stm32-usbphyc.c #define PLLFRACCTL BIT(29) BIT 29 drivers/phy/st/phy-stm32-usbphyc.c #define PLLDITHEN0 BIT(30) BIT 30 drivers/phy/st/phy-stm32-usbphyc.c #define PLLDITHEN1 BIT(31) BIT 33 drivers/phy/st/phy-stm32-usbphyc.c #define SWITHOST BIT(0) BIT 18 drivers/phy/tegra/phy-tegra194-p2u.c #define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0) BIT 19 drivers/phy/tegra/phy-tegra194-p2u.c #define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1) BIT 21 drivers/phy/tegra/phy-tegra194-p2u.c #define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN BIT(1) BIT 50 drivers/phy/tegra/xusb-tegra186.c #define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x) BIT 51 drivers/phy/tegra/xusb-tegra186.c #define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7) BIT 52 drivers/phy/tegra/xusb-tegra186.c #define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14) BIT 53 drivers/phy/tegra/xusb-tegra186.c #define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21) BIT 54 drivers/phy/tegra/xusb-tegra186.c #define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28) BIT 55 drivers/phy/tegra/xusb-tegra186.c #define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30) BIT 63 drivers/phy/tegra/xusb-tegra186.c #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3) BIT 64 drivers/phy/tegra/xusb-tegra186.c #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3) BIT 65 drivers/phy/tegra/xusb-tegra186.c #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3) BIT 69 drivers/phy/tegra/xusb-tegra186.c #define TERM_SEL BIT(25) BIT 70 drivers/phy/tegra/xusb-tegra186.c #define USB2_OTG_PD BIT(26) BIT 71 drivers/phy/tegra/xusb-tegra186.c #define USB2_OTG_PD2 BIT(27) BIT 72 drivers/phy/tegra/xusb-tegra186.c #define USB2_OTG_PD2_OVRD_EN BIT(28) BIT 73 drivers/phy/tegra/xusb-tegra186.c #define USB2_OTG_PD_ZI BIT(29) BIT 76 drivers/phy/tegra/xusb-tegra186.c #define USB2_OTG_PD_DR BIT(2) BIT 81 drivers/phy/tegra/xusb-tegra186.c #define BIAS_PAD_PD BIT(11) BIT 87 drivers/phy/tegra/xusb-tegra186.c #define USB2_PD_TRK BIT(26) BIT 90 drivers/phy/tegra/xusb-tegra186.c #define HSIC_PD_TX_DATA0 BIT(1) BIT 91 drivers/phy/tegra/xusb-tegra186.c #define HSIC_PD_TX_STROBE BIT(3) BIT 92 drivers/phy/tegra/xusb-tegra186.c #define HSIC_PD_RX_DATA0 BIT(4) BIT 93 drivers/phy/tegra/xusb-tegra186.c #define HSIC_PD_RX_STROBE BIT(6) BIT 94 drivers/phy/tegra/xusb-tegra186.c #define HSIC_PD_ZI_DATA0 BIT(7) BIT 95 drivers/phy/tegra/xusb-tegra186.c #define HSIC_PD_ZI_STROBE BIT(9) BIT 96 drivers/phy/tegra/xusb-tegra186.c #define HSIC_RPD_DATA0 BIT(13) BIT 97 drivers/phy/tegra/xusb-tegra186.c #define HSIC_RPD_STROBE BIT(15) BIT 98 drivers/phy/tegra/xusb-tegra186.c #define HSIC_RPU_DATA0 BIT(16) BIT 99 drivers/phy/tegra/xusb-tegra186.c #define HSIC_RPU_STROBE BIT(18) BIT 104 drivers/phy/tegra/xusb-tegra186.c #define HSIC_PD_TRK BIT(19) BIT 107 drivers/phy/tegra/xusb-tegra186.c #define VBUS_OVERRIDE BIT(14) BIT 189 drivers/phy/tegra/xusb-tegra210.c #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18) BIT 190 drivers/phy/tegra/xusb-tegra210.c #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13) BIT 44 drivers/phy/ti/phy-dm816x-usb.c #define DM816X_USB_CTRL_PHYCLKSRC BIT(8) /* 1 = PLL ref clock */ BIT 45 drivers/phy/ti/phy-dm816x-usb.c #define DM816X_USB_CTRL_PHYSLEEP1 BIT(1) /* Enable the first phy */ BIT 46 drivers/phy/ti/phy-dm816x-usb.c #define DM816X_USB_CTRL_PHYSLEEP0 BIT(0) /* Enable the second phy */ BIT 127 drivers/phy/ti/phy-dm816x-usb.c mask = BIT(phy->instance); BIT 128 drivers/phy/ti/phy-dm816x-usb.c val = ~BIT(phy->instance); BIT 155 drivers/phy/ti/phy-dm816x-usb.c mask = BIT(phy->instance); BIT 156 drivers/phy/ti/phy-dm816x-usb.c val = BIT(phy->instance); BIT 106 drivers/phy/ti/phy-gmii-sel.c if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE) && BIT 114 drivers/phy/ti/phy-gmii-sel.c if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) && BIT 141 drivers/phy/ti/phy-gmii-sel.c .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) | BIT 142 drivers/phy/ti/phy-gmii-sel.c BIT(PHY_GMII_SEL_RMII_IO_CLK_EN), BIT 169 drivers/phy/ti/phy-gmii-sel.c .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE), BIT 209 drivers/phy/ti/phy-gmii-sel.c if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) && BIT 218 drivers/phy/ti/phy-gmii-sel.c if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN)) BIT 29 drivers/phy/ti/phy-omap-usb2.c #define AM654_USB2_OTG_PD BIT(8) BIT 30 drivers/phy/ti/phy-omap-usb2.c #define AM654_USB2_VBUS_DET_EN BIT(5) BIT 31 drivers/phy/ti/phy-omap-usb2.c #define AM654_USB2_VBUSVALID_DET_EN BIT(4) BIT 42 drivers/phy/ti/phy-ti-pipe3.c #define PLL_LDOPWDN BIT(15) BIT 43 drivers/phy/ti/phy-ti-pipe3.c #define PLL_TICOPWDN BIT(16) BIT 47 drivers/phy/ti/phy-ti-pipe3.c #define SATA_PLL_SOFT_RESET BIT(18) BIT 64 drivers/phy/ti/phy-ti-pipe3.c #define INTERFACE_MODE_USBSS BIT(4) BIT 65 drivers/phy/ti/phy-ti-pipe3.c #define INTERFACE_MODE_SATA_1P5 BIT(3) BIT 66 drivers/phy/ti/phy-ti-pipe3.c #define INTERFACE_MODE_SATA_3P0 BIT(2) BIT 67 drivers/phy/ti/phy-ti-pipe3.c #define INTERFACE_MODE_PCIE BIT(0) BIT 84 drivers/phy/ti/phy-ti-pipe3.c #define MEM_OVRD_HS_RATE BIT(26) BIT 86 drivers/phy/ti/phy-ti-pipe3.c #define MEM_CDR_FASTLOCK BIT(23) BIT 96 drivers/phy/ti/phy-ti-pipe3.c #define MEM_CDR_THR_MODE BIT(12) BIT 98 drivers/phy/ti/phy-ti-pipe3.c #define MEM_CDR_2NDO_SDM_MODE BIT(11) BIT 108 drivers/phy/ti/phy-ti-pipe3.c #define MEM_OVRD_EQLEV BIT(2) BIT 110 drivers/phy/ti/phy-ti-pipe3.c #define MEM_OVRD_EQFTC BIT(1) BIT 290 drivers/phy/ti/phy-twl4030-usb.c else if (status & (BIT(7) | BIT(2))) { BIT 291 drivers/phy/ti/phy-twl4030-usb.c if (status & BIT(7)) { BIT 293 drivers/phy/ti/phy-twl4030-usb.c status &= ~BIT(7); BIT 298 drivers/phy/ti/phy-twl4030-usb.c if (status & BIT(2)) BIT 300 drivers/phy/ti/phy-twl4030-usb.c else if (status & BIT(7)) BIT 524 drivers/pinctrl/actions/pinctrl-owl.c val |= BIT(pin); BIT 526 drivers/pinctrl/actions/pinctrl-owl.c val &= ~BIT(pin); BIT 595 drivers/pinctrl/actions/pinctrl-owl.c return !!(val & BIT(offset)); BIT 766 drivers/pinctrl/actions/pinctrl-owl.c value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M)) BIT 2574 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c !(desc->mask & (BIT(21) | BIT(22)))) BIT 59 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 } BIT 2748 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c !(desc->mask & (BIT(21) | BIT(22)))) BIT 495 drivers/pinctrl/aspeed/pinctrl-aspeed.c (val & BIT(pconf->bit)) >> pconf->bit); BIT 546 drivers/pinctrl/aspeed/pinctrl-aspeed.c BIT(pconf->bit), val); BIT 258 drivers/pinctrl/bcm/pinctrl-bcm2835.c bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); BIT 419 drivers/pinctrl/bcm/pinctrl-bcm2835.c value |= BIT(GPIO_REG_SHIFT(offset)); BIT 421 drivers/pinctrl/bcm/pinctrl-bcm2835.c value &= ~(BIT(GPIO_REG_SHIFT(offset))); BIT 930 drivers/pinctrl/bcm/pinctrl-bcm2835.c bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); BIT 1133 drivers/pinctrl/bcm/pinctrl-bcm2835.c bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); BIT 148 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val |= BIT(shift); BIT 150 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val &= ~BIT(shift); BIT 160 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c return !!(readl(chip->base + offset) & BIT(shift)); BIT 185 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + BIT 204 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c u32 val = BIT(shift); BIT 360 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c return !(readl(chip->base + offset) & BIT(shift)); BIT 382 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c return !!(readl(chip->base + offset) & BIT(shift)); BIT 483 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_1 &= ~BIT(shift); BIT 484 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_2 &= ~BIT(shift); BIT 486 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_1 |= BIT(shift); BIT 487 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_2 &= ~BIT(shift); BIT 489 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_1 &= ~BIT(shift); BIT 490 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_2 |= BIT(shift); BIT 525 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift); BIT 526 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift); BIT 572 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val &= ~BIT(shift); BIT 601 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val = readl(base + offset) & BIT(shift); BIT 785 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH); BIT 19 drivers/pinctrl/bcm/pinctrl-ns.c #define FLAG_BCM4708 BIT(1) BIT 20 drivers/pinctrl/bcm/pinctrl-ns.c #define FLAG_BCM4709 BIT(2) BIT 21 drivers/pinctrl/bcm/pinctrl-ns.c #define FLAG_BCM53012 BIT(3) BIT 232 drivers/pinctrl/bcm/pinctrl-ns.c unset |= BIT(pin_number); BIT 117 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val |= BIT(gpio); BIT 119 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val &= ~BIT(gpio); BIT 132 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c return !!(readl(chip->io_ctrl + reg) & BIT(gpio)); BIT 134 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c return !!(readl(chip->base + reg) & BIT(gpio)); BIT 163 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c writel(BIT(bit), chip->base + NSP_GPIO_EVENT); BIT 176 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c u32 val = BIT(gpio); BIT 322 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio)); BIT 409 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val &= ~BIT(shift); BIT 433 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val = readl(chip->io_ctrl + offset) & BIT(shift); BIT 491 drivers/pinctrl/bcm/pinctrl-nsp-mux.c if ((val & BIT(pin)) != (*gpio_select << pin)) { BIT 492 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val &= ~BIT(pin); BIT 1082 drivers/pinctrl/cirrus/pinctrl-lochnagar.c BIT(pin->shift), value << pin->shift); BIT 124 drivers/pinctrl/freescale/pinctrl-imx.h #define SHARE_MUX_CONF_REG BIT(0) BIT 125 drivers/pinctrl/freescale/pinctrl-imx.h #define ZERO_OFFSET_VALID BIT(1) BIT 126 drivers/pinctrl/freescale/pinctrl-imx.h #define IMX_USE_SCU BIT(2) BIT 141 drivers/pinctrl/freescale/pinctrl-imx.h #define BM_PAD_CTL_GP_ENABLE BIT(30) BIT 142 drivers/pinctrl/freescale/pinctrl-imx.h #define BM_PAD_CTL_IFMUX_ENABLE BIT(31) BIT 53 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_FUNCTION(val) (BIT(0) & val) BIT 54 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1) BIT 55 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2) BIT 56 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4) BIT 57 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8) BIT 58 drivers/pinctrl/freescale/pinctrl-imx1-core.c #define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10) BIT 142 drivers/pinctrl/freescale/pinctrl-imx1-core.c return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset; BIT 151 drivers/pinctrl/freescale/pinctrl-imx1-core.c return !!(readl(reg) & BIT(offset)); BIT 257 drivers/pinctrl/freescale/pinctrl-imx7ulp.c #define BM_OBE_ENABLED BIT(17) BIT 258 drivers/pinctrl/freescale/pinctrl-imx7ulp.c #define BM_IBE_ENABLED BIT(16) BIT 38 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_IODEN BIT(31) BIT 39 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_DIRECT_IRQ_EN BIT(27) BIT 41 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_TRIG_NEG BIT(26) BIT 42 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_TRIG_POS BIT(25) BIT 43 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_TRIG_LVL BIT(24) BIT 44 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_DEBOUNCE_EN BIT(20) BIT 45 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_GLITCH_FILTER_EN BIT(19) BIT 46 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_GLITCH_F_SLOW_CLK BIT(17) BIT 47 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_GLITCH_F_FAST_CLK BIT(16) BIT 62 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ BIT 63 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ BIT 64 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_LEVEL BIT(0) BIT 1316 drivers/pinctrl/intel/pinctrl-baytrail.c writel(BIT(offset % 32), reg); BIT 39 drivers/pinctrl/intel/pinctrl-cherryview.c #define CHV_PADCTRL0_TERM_UP BIT(23) BIT 47 drivers/pinctrl/intel/pinctrl-cherryview.c #define CHV_PADCTRL0_GPIOEN BIT(15) BIT 54 drivers/pinctrl/intel/pinctrl-cherryview.c #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) BIT 55 drivers/pinctrl/intel/pinctrl-cherryview.c #define CHV_PADCTRL0_GPIORXSTATE BIT(0) BIT 58 drivers/pinctrl/intel/pinctrl-cherryview.c #define CHV_PADCTRL1_CFGLOCK BIT(31) BIT 62 drivers/pinctrl/intel/pinctrl-cherryview.c #define CHV_PADCTRL1_ODEN BIT(3) BIT 1328 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); BIT 1349 drivers/pinctrl/intel/pinctrl-cherryview.c value &= ~BIT(intr_line); BIT 1351 drivers/pinctrl/intel/pinctrl-cherryview.c value |= BIT(intr_line); BIT 47 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_PREGFRXSEL BIT(24) BIT 48 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_RXINV BIT(23) BIT 49 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_GPIROUTIOXAPIC BIT(20) BIT 50 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_GPIROUTSCI BIT(19) BIT 51 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_GPIROUTSMI BIT(18) BIT 52 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_GPIROUTNMI BIT(17) BIT 56 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_GPIORXDIS BIT(9) BIT 57 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_GPIOTXDIS BIT(8) BIT 58 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_GPIORXSTATE BIT(1) BIT 59 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_GPIOTXSTATE BIT(0) BIT 62 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG1_TERM_UP BIT(13) BIT 71 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG2_DEBEN BIT(0) BIT 223 drivers/pinctrl/intel/pinctrl-intel.c return !(readl(hostown) & BIT(gpp_offset)); BIT 272 drivers/pinctrl/intel/pinctrl-intel.c if (value & BIT(gpp_offset)) BIT 277 drivers/pinctrl/intel/pinctrl-intel.c if (value & BIT(gpp_offset)) BIT 625 drivers/pinctrl/intel/pinctrl-intel.c arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; BIT 991 drivers/pinctrl/intel/pinctrl-intel.c writel(BIT(gpp_offset), community->regs + is_offset); BIT 1020 drivers/pinctrl/intel/pinctrl-intel.c writel(BIT(gpp_offset), is); BIT 1024 drivers/pinctrl/intel/pinctrl-intel.c value &= ~BIT(gpp_offset); BIT 1026 drivers/pinctrl/intel/pinctrl-intel.c value |= BIT(gpp_offset); BIT 1593 drivers/pinctrl/intel/pinctrl-intel.c requested |= BIT(i); BIT 121 drivers/pinctrl/intel/pinctrl-intel.h #define PINCTRL_FEATURE_DEBOUNCE BIT(0) BIT 122 drivers/pinctrl/intel/pinctrl-intel.h #define PINCTRL_FEATURE_1K_PD BIT(1) BIT 38 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_PU_EN BIT(8) BIT 39 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_PD_EN BIT(9) BIT 41 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_SLEWSEL BIT(10) BIT 42 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_OVINEN BIT(12) BIT 43 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_OVINEN_EN BIT(13) BIT 45 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_OVOUTEN BIT(14) BIT 46 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_OVOUTEN_EN BIT(15) BIT 48 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_INDATAOV_VAL BIT(16) BIT 49 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_INDATAOV_EN BIT(17) BIT 51 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_OUTDATAOV_VAL BIT(18) BIT 52 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_OUTDATAOV_EN BIT(19) BIT 54 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_OD_EN BIT(21) BIT 69 drivers/pinctrl/mediatek/mtk-eint.c unsigned int bit = BIT(eint_num % 32); BIT 88 drivers/pinctrl/mediatek/mtk-eint.c u32 mask = BIT(hwirq & 0x1f); BIT 112 drivers/pinctrl/mediatek/mtk-eint.c u32 mask = BIT(d->hwirq & 0x1f); BIT 124 drivers/pinctrl/mediatek/mtk-eint.c u32 mask = BIT(d->hwirq & 0x1f); BIT 139 drivers/pinctrl/mediatek/mtk-eint.c unsigned int bit = BIT(eint_num % 32); BIT 149 drivers/pinctrl/mediatek/mtk-eint.c u32 mask = BIT(d->hwirq & 0x1f); BIT 159 drivers/pinctrl/mediatek/mtk-eint.c u32 mask = BIT(d->hwirq & 0x1f); BIT 204 drivers/pinctrl/mediatek/mtk-eint.c eint->wake_mask[reg] |= BIT(shift); BIT 206 drivers/pinctrl/mediatek/mtk-eint.c eint->wake_mask[reg] &= ~BIT(shift); BIT 325 drivers/pinctrl/mediatek/mtk-eint.c status &= ~BIT(offset); BIT 333 drivers/pinctrl/mediatek/mtk-eint.c if (eint->wake_mask[mask_offset] & BIT(offset) && BIT 334 drivers/pinctrl/mediatek/mtk-eint.c !(eint->cur_mask[mask_offset] & BIT(offset))) { BIT 335 drivers/pinctrl/mediatek/mtk-eint.c writel_relaxed(BIT(offset), reg - BIT 346 drivers/pinctrl/mediatek/mtk-eint.c writel(BIT(offset), reg - eint->regs->stat + BIT 364 drivers/pinctrl/mediatek/mtk-eint.c writel(BIT(offset), reg - BIT 490 drivers/pinctrl/mediatek/pinctrl-mt2701.c mask = BIT(mt2701_spec_pinmux[i].bit); BIT 156 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1, BIT 168 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c >> pf->bitpos) & (BIT(nbits_l) - 1); BIT 170 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c & (BIT(nbits_h) - 1); BIT 77 drivers/pinctrl/mediatek/pinctrl-mtk-common.c bit = BIT(offset & 0xf); BIT 99 drivers/pinctrl/mediatek/pinctrl-mtk-common.c bit = BIT(offset & 0xf); BIT 138 drivers/pinctrl/mediatek/pinctrl-mtk-common.c bit = BIT(pin & 0xf); BIT 175 drivers/pinctrl/mediatek/pinctrl-mtk-common.c bit = BIT(ies_smt_infos[i].bit); BIT 214 drivers/pinctrl/mediatek/pinctrl-mtk-common.c mask = BIT(bits) - 1; BIT 255 drivers/pinctrl/mediatek/pinctrl-mtk-common.c bit_pupd = BIT(spec_pupd_pin->pupd_bit); BIT 258 drivers/pinctrl/mediatek/pinctrl-mtk-common.c bit_r0 = BIT(spec_pupd_pin->r0_bit); BIT 259 drivers/pinctrl/mediatek/pinctrl-mtk-common.c bit_r1 = BIT(spec_pupd_pin->r1_bit); BIT 314 drivers/pinctrl/mediatek/pinctrl-mtk-common.c bit = BIT(pin & 0xf); BIT 801 drivers/pinctrl/mediatek/pinctrl-mtk-common.c bit = BIT(offset & 0xf); BIT 820 drivers/pinctrl/mediatek/pinctrl-mtk-common.c bit = BIT(offset & 0xf); BIT 185 drivers/pinctrl/meson/pinctrl-meson.c return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT 186 drivers/pinctrl/meson/pinctrl-meson.c arg ? BIT(bit) : 0); BIT 206 drivers/pinctrl/meson/pinctrl-meson.c return BIT(bit) & val ? 1 : 0; BIT 265 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); BIT 285 drivers/pinctrl/meson/pinctrl-meson.c val = BIT(bit); BIT 287 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); BIT 292 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); BIT 409 drivers/pinctrl/meson/pinctrl-meson.c if (!(val & BIT(bit))) { BIT 418 drivers/pinctrl/meson/pinctrl-meson.c if (val & BIT(bit)) BIT 583 drivers/pinctrl/meson/pinctrl-meson.c return !!(val & BIT(bit)); BIT 50 drivers/pinctrl/meson/pinctrl-meson8-pmx.c BIT(pmx_data->bit), 0); BIT 79 drivers/pinctrl/meson/pinctrl-meson8-pmx.c BIT(pmx_data->bit), BIT 80 drivers/pinctrl/meson/pinctrl-meson8-pmx.c BIT(pmx_data->bit)); BIT 166 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"), BIT 167 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"), BIT 168 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), BIT 169 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"), BIT 170 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"), BIT 171 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"), BIT 172 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"), BIT 173 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), BIT 174 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), BIT 175 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), BIT 176 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"), BIT 177 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"), BIT 178 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"), BIT 179 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"), BIT 180 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), BIT 181 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), BIT 182 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), BIT 183 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), BIT 184 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), BIT 186 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"), BIT 187 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"), BIT 188 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"), BIT 189 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"), BIT 194 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), BIT 195 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), BIT 196 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), BIT 197 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), BIT 198 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), BIT 199 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), BIT 200 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), BIT 201 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), BIT 202 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), BIT 203 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), BIT 204 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), BIT 205 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), BIT 390 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = BIT(offset); BIT 403 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = BIT(offset); BIT 417 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = BIT(offset); BIT 438 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = BIT(offset); BIT 453 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = BIT(offset); BIT 565 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val |= (BIT(d->hwirq % GPIO_PER_REG)); BIT 567 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val &= ~(BIT(d->hwirq % GPIO_PER_REG)); BIT 586 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val &= ~(BIT(d->hwirq % GPIO_PER_REG)); BIT 589 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val |= (BIT(d->hwirq % GPIO_PER_REG)); BIT 598 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c if (in_val & BIT(d->hwirq % GPIO_PER_REG)) BIT 599 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */ BIT 601 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */ BIT 712 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c d->mask = BIT(d->hwirq % GPIO_PER_REG); BIT 1062 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 irq_bit = BIT(i % GPIO_PER_REG); BIT 21 drivers/pinctrl/mvebu/pinctrl-armada-38x.c V_88F6810 = BIT(0), BIT 22 drivers/pinctrl/mvebu/pinctrl-armada-38x.c V_88F6820 = BIT(1), BIT 23 drivers/pinctrl/mvebu/pinctrl-armada-38x.c V_88F6828 = BIT(2), BIT 21 drivers/pinctrl/mvebu/pinctrl-armada-39x.c V_88F6920 = BIT(0), BIT 22 drivers/pinctrl/mvebu/pinctrl-armada-39x.c V_88F6925 = BIT(1), BIT 23 drivers/pinctrl/mvebu/pinctrl-armada-39x.c V_88F6928 = BIT(2), BIT 32 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c V_ARMADA_7K = BIT(0), BIT 33 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c V_ARMADA_8K_CPM = BIT(1), BIT 34 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c V_ARMADA_8K_CPS = BIT(2), BIT 35 drivers/pinctrl/mvebu/pinctrl-armada-cp110.c V_CP115_STANDALONE = BIT(3), BIT 31 drivers/pinctrl/mvebu/pinctrl-armada-xp.c V_MV78230 = BIT(0), BIT 32 drivers/pinctrl/mvebu/pinctrl-armada-xp.c V_MV78260 = BIT(1), BIT 33 drivers/pinctrl/mvebu/pinctrl-armada-xp.c V_MV78460 = BIT(2), BIT 36 drivers/pinctrl/mvebu/pinctrl-armada-xp.c V_98DX3236 = BIT(3), BIT 37 drivers/pinctrl/mvebu/pinctrl-armada-xp.c V_98DX3336 = BIT(4), BIT 38 drivers/pinctrl/mvebu/pinctrl-armada-xp.c V_98DX4251 = BIT(5), BIT 30 drivers/pinctrl/mvebu/pinctrl-dove.c #define AU0_AC97_SEL BIT(16) BIT 33 drivers/pinctrl/mvebu/pinctrl-dove.c #define SPI_GPIO_SEL BIT(5) BIT 34 drivers/pinctrl/mvebu/pinctrl-dove.c #define UART1_GPIO_SEL BIT(4) BIT 35 drivers/pinctrl/mvebu/pinctrl-dove.c #define AU1_GPIO_SEL BIT(3) BIT 36 drivers/pinctrl/mvebu/pinctrl-dove.c #define CAM_GPIO_SEL BIT(2) BIT 37 drivers/pinctrl/mvebu/pinctrl-dove.c #define SD1_GPIO_SEL BIT(1) BIT 38 drivers/pinctrl/mvebu/pinctrl-dove.c #define SD0_GPIO_SEL BIT(0) BIT 46 drivers/pinctrl/mvebu/pinctrl-dove.c #define TWSI_ENABLE_OPTION1 BIT(7) BIT 48 drivers/pinctrl/mvebu/pinctrl-dove.c #define TWSI_ENABLE_OPTION2 BIT(20) BIT 49 drivers/pinctrl/mvebu/pinctrl-dove.c #define TWSI_ENABLE_OPTION3 BIT(21) BIT 50 drivers/pinctrl/mvebu/pinctrl-dove.c #define TWSI_OPTION3_GPIO BIT(22) BIT 52 drivers/pinctrl/mvebu/pinctrl-dove.c #define SSP_ON_AU1 BIT(0) BIT 54 drivers/pinctrl/mvebu/pinctrl-dove.c #define AU1_SPDIFO_GPIO_EN BIT(1) BIT 55 drivers/pinctrl/mvebu/pinctrl-dove.c #define NAND_GPIO_EN BIT(0) BIT 57 drivers/pinctrl/mvebu/pinctrl-dove.c #define CONFIG_PMU BIT(4) BIT 71 drivers/pinctrl/mvebu/pinctrl-dove.c if ((pmu & BIT(pid)) == 0) BIT 90 drivers/pinctrl/mvebu/pinctrl-dove.c writel(pmu & ~BIT(pid), data->base + PMU_MPP_GENERAL_CTRL); BIT 94 drivers/pinctrl/mvebu/pinctrl-dove.c writel(pmu | BIT(pid), data->base + PMU_MPP_GENERAL_CTRL); BIT 226 drivers/pinctrl/mvebu/pinctrl-dove.c *config |= BIT(3); BIT 228 drivers/pinctrl/mvebu/pinctrl-dove.c *config |= BIT(2); BIT 230 drivers/pinctrl/mvebu/pinctrl-dove.c *config |= BIT(1); BIT 232 drivers/pinctrl/mvebu/pinctrl-dove.c *config |= BIT(0); BIT 235 drivers/pinctrl/mvebu/pinctrl-dove.c if ((*config & BIT(3)) == 0) BIT 236 drivers/pinctrl/mvebu/pinctrl-dove.c *config &= ~(BIT(2) | BIT(0)); BIT 238 drivers/pinctrl/mvebu/pinctrl-dove.c if ((*config & BIT(1)) == 0) BIT 239 drivers/pinctrl/mvebu/pinctrl-dove.c *config &= ~BIT(0); BIT 249 drivers/pinctrl/mvebu/pinctrl-dove.c if (config & BIT(3)) BIT 255 drivers/pinctrl/mvebu/pinctrl-dove.c (config & BIT(2)) ? SSP_ON_AU1 : 0); BIT 258 drivers/pinctrl/mvebu/pinctrl-dove.c (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0); BIT 261 drivers/pinctrl/mvebu/pinctrl-dove.c (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0); BIT 107 drivers/pinctrl/nomadik/pinctrl-abx500.c *bit = !!(val & BIT(pos)); BIT 121 drivers/pinctrl/nomadik/pinctrl-abx500.c AB8500_MISC, reg, BIT(pos), val << pos); BIT 300 drivers/pinctrl/nomadik/pinctrl-abx500.c !!(af.alta_val & BIT(0))); BIT 308 drivers/pinctrl/nomadik/pinctrl-abx500.c !!(af.alta_val & BIT(1))); BIT 321 drivers/pinctrl/nomadik/pinctrl-abx500.c af.alt_bit1, !!(af.altb_val & BIT(0))); BIT 329 drivers/pinctrl/nomadik/pinctrl-abx500.c !!(af.altb_val & BIT(1))); BIT 339 drivers/pinctrl/nomadik/pinctrl-abx500.c af.alt_bit2, !!(af.altc_val & BIT(0))); BIT 344 drivers/pinctrl/nomadik/pinctrl-abx500.c af.alt_bit2, !!(af.altc_val & BIT(1))); BIT 294 drivers/pinctrl/nomadik/pinctrl-nomadik.c afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset); BIT 295 drivers/pinctrl/nomadik/pinctrl-nomadik.c bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset); BIT 297 drivers/pinctrl/nomadik/pinctrl-nomadik.c afunc |= BIT(offset); BIT 299 drivers/pinctrl/nomadik/pinctrl-nomadik.c bfunc |= BIT(offset); BIT 311 drivers/pinctrl/nomadik/pinctrl-nomadik.c slpm |= BIT(offset); BIT 313 drivers/pinctrl/nomadik/pinctrl-nomadik.c slpm &= ~BIT(offset); BIT 324 drivers/pinctrl/nomadik/pinctrl-nomadik.c pdis |= BIT(offset); BIT 325 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->pull_up &= ~BIT(offset); BIT 327 drivers/pinctrl/nomadik/pinctrl-nomadik.c pdis &= ~BIT(offset); BIT 333 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->pull_up |= BIT(offset); BIT 334 drivers/pinctrl/nomadik/pinctrl-nomadik.c writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); BIT 336 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->pull_up &= ~BIT(offset); BIT 337 drivers/pinctrl/nomadik/pinctrl-nomadik.c writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); BIT 344 drivers/pinctrl/nomadik/pinctrl-nomadik.c bool enabled = nmk_chip->lowemi & BIT(offset); BIT 350 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->lowemi |= BIT(offset); BIT 352 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->lowemi &= ~BIT(offset); BIT 361 drivers/pinctrl/nomadik/pinctrl-nomadik.c writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); BIT 368 drivers/pinctrl/nomadik/pinctrl-nomadik.c writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); BIT 370 drivers/pinctrl/nomadik/pinctrl-nomadik.c writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); BIT 376 drivers/pinctrl/nomadik/pinctrl-nomadik.c writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS); BIT 388 drivers/pinctrl/nomadik/pinctrl-nomadik.c u32 bit = BIT(offset); BIT 410 drivers/pinctrl/nomadik/pinctrl-nomadik.c u32 falling = nmk_chip->fimsc & BIT(offset); BIT 411 drivers/pinctrl/nomadik/pinctrl-nomadik.c u32 rising = nmk_chip->rimsc & BIT(offset); BIT 423 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->rimsc &= ~BIT(offset); BIT 429 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->fimsc &= ~BIT(offset); BIT 487 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (readl(npct->prcm_base + reg) & BIT(bit)) { BIT 488 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); BIT 516 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (readl(npct->prcm_base + reg) & BIT(bit)) { BIT 517 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); BIT 529 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); BIT 603 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (readl(npct->prcm_base + reg) & BIT(bit)) BIT 618 drivers/pinctrl/nomadik/pinctrl-nomadik.c writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); BIT 649 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (nmk_chip->edge_rising & BIT(offset)) { BIT 651 drivers/pinctrl/nomadik/pinctrl-nomadik.c *rimscval |= BIT(offset); BIT 653 drivers/pinctrl/nomadik/pinctrl-nomadik.c *rimscval &= ~BIT(offset); BIT 656 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (nmk_chip->edge_falling & BIT(offset)) { BIT 658 drivers/pinctrl/nomadik/pinctrl-nomadik.c *fimscval |= BIT(offset); BIT 660 drivers/pinctrl/nomadik/pinctrl-nomadik.c *fimscval &= ~BIT(offset); BIT 696 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (!(nmk_chip->real_wake & BIT(d->hwirq))) BIT 733 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->real_wake |= BIT(d->hwirq); BIT 735 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->real_wake &= ~BIT(d->hwirq); BIT 768 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->edge_rising &= ~BIT(d->hwirq); BIT 770 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->edge_rising |= BIT(d->hwirq); BIT 772 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->edge_falling &= ~BIT(d->hwirq); BIT 774 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->edge_falling |= BIT(d->hwirq); BIT 816 drivers/pinctrl/nomadik/pinctrl-nomadik.c status &= ~BIT(bit); BIT 853 drivers/pinctrl/nomadik/pinctrl-nomadik.c dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); BIT 866 drivers/pinctrl/nomadik/pinctrl-nomadik.c writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); BIT 880 drivers/pinctrl/nomadik/pinctrl-nomadik.c value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); BIT 920 drivers/pinctrl/nomadik/pinctrl-nomadik.c afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset); BIT 921 drivers/pinctrl/nomadik/pinctrl-nomadik.c bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset); BIT 957 drivers/pinctrl/nomadik/pinctrl-nomadik.c is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); BIT 958 drivers/pinctrl/nomadik/pinctrl-nomadik.c pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset)); BIT 959 drivers/pinctrl/nomadik/pinctrl-nomadik.c data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); BIT 995 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (nmk_chip->edge_rising & BIT(offset)) BIT 997 drivers/pinctrl/nomadik/pinctrl-nomadik.c else if (nmk_chip->edge_falling & BIT(offset)) BIT 1608 drivers/pinctrl/nomadik/pinctrl-nomadik.c slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); BIT 37 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c #define SRCNT_ESPI BIT(3) BIT 242 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c unsigned int gpio = BIT(d->hwirq); BIT 293 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); BIT 305 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); BIT 317 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); BIT 1423 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c BIT(cfg->bit0), BIT 1425 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c BIT(cfg->bit0) : 0); BIT 1428 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c BIT(cfg->bit1), BIT 1430 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c BIT(cfg->bit1) : 0); BIT 1433 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c BIT(cfg->bit2), BIT 1435 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c BIT(cfg->bit2) : 0); BIT 1446 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c unsigned long pinmask = BIT(gpio); BIT 1465 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = BIT(pin % bank->gc.ngpio); BIT 1508 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c unsigned long pinmask = BIT(gpio); BIT 1533 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = BIT(pin % bank->gc.ngpio); BIT 1692 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = BIT(offset % bank->gc.ngpio); BIT 1723 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c unsigned long pinmask = BIT(gpio); BIT 1785 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = BIT(pin % bank->gc.ngpio); BIT 49 drivers/pinctrl/pinctrl-amd.c return !(pin_reg & BIT(OUTPUT_ENABLE_OFF)); BIT 60 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); BIT 76 drivers/pinctrl/pinctrl-amd.c pin_reg |= BIT(OUTPUT_ENABLE_OFF); BIT 78 drivers/pinctrl/pinctrl-amd.c pin_reg |= BIT(OUTPUT_VALUE_OFF); BIT 80 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(OUTPUT_VALUE_OFF); BIT 97 drivers/pinctrl/pinctrl-amd.c return !!(pin_reg & BIT(PIN_STS_OFF)); BIT 109 drivers/pinctrl/pinctrl-amd.c pin_reg |= BIT(OUTPUT_VALUE_OFF); BIT 111 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(OUTPUT_VALUE_OFF); BIT 143 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); BIT 144 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(DB_TMR_LARGE_OFF); BIT 148 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); BIT 149 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(DB_TMR_LARGE_OFF); BIT 153 drivers/pinctrl/pinctrl-amd.c pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); BIT 154 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(DB_TMR_LARGE_OFF); BIT 158 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); BIT 159 drivers/pinctrl/pinctrl-amd.c pin_reg |= BIT(DB_TMR_LARGE_OFF); BIT 163 drivers/pinctrl/pinctrl-amd.c pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); BIT 164 drivers/pinctrl/pinctrl-amd.c pin_reg |= BIT(DB_TMR_LARGE_OFF); BIT 170 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); BIT 171 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(DB_TMR_LARGE_OFF); BIT 245 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { BIT 254 drivers/pinctrl/pinctrl-amd.c else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && BIT 260 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(LEVEL_TRIG_OFF)) BIT 272 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(INTERRUPT_MASK_OFF)) BIT 279 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) BIT 284 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) BIT 289 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) BIT 294 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { BIT 296 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(PULL_UP_SEL_OFF)) BIT 305 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) BIT 310 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { BIT 313 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(OUTPUT_VALUE_OFF)) BIT 321 drivers/pinctrl/pinctrl-amd.c if (pin_reg & BIT(PIN_STS_OFF)) BIT 350 drivers/pinctrl/pinctrl-amd.c pin_reg |= BIT(INTERRUPT_ENABLE_OFF); BIT 351 drivers/pinctrl/pinctrl-amd.c pin_reg |= BIT(INTERRUPT_MASK_OFF); BIT 365 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); BIT 366 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(INTERRUPT_MASK_OFF); BIT 380 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(INTERRUPT_MASK_OFF); BIT 394 drivers/pinctrl/pinctrl-amd.c pin_reg |= BIT(INTERRUPT_MASK_OFF); BIT 435 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(LEVEL_TRIG_OFF); BIT 443 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(LEVEL_TRIG_OFF); BIT 451 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(LEVEL_TRIG_OFF); BIT 500 drivers/pinctrl/pinctrl-amd.c mask = BIT(INTERRUPT_ENABLE_OFF); BIT 503 drivers/pinctrl/pinctrl-amd.c pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); BIT 534 drivers/pinctrl/pinctrl-amd.c #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) BIT 566 drivers/pinctrl/pinctrl-amd.c !(regval & BIT(INTERRUPT_MASK_OFF))) BIT 583 drivers/pinctrl/pinctrl-amd.c regval &= ~BIT(INTERRUPT_ENABLE_OFF); BIT 660 drivers/pinctrl/pinctrl-amd.c arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); BIT 664 drivers/pinctrl/pinctrl-amd.c arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); BIT 706 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); BIT 707 drivers/pinctrl/pinctrl-amd.c pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; BIT 711 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(PULL_UP_SEL_OFF); BIT 712 drivers/pinctrl/pinctrl-amd.c pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; BIT 713 drivers/pinctrl/pinctrl-amd.c pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); BIT 714 drivers/pinctrl/pinctrl-amd.c pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; BIT 54 drivers/pinctrl/pinctrl-as3722.c #define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP) BIT 55 drivers/pinctrl/pinctrl-as3722.c #define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN) BIT 56 drivers/pinctrl/pinctrl-as3722.c #define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE) BIT 57 drivers/pinctrl/pinctrl-as3722.c #define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN) BIT 36 drivers/pinctrl/pinctrl-at91-pio4.c #define ATMEL_PIO_DIR_MASK BIT(8) BIT 37 drivers/pinctrl/pinctrl-at91-pio4.c #define ATMEL_PIO_PUEN_MASK BIT(9) BIT 38 drivers/pinctrl/pinctrl-at91-pio4.c #define ATMEL_PIO_PDEN_MASK BIT(10) BIT 39 drivers/pinctrl/pinctrl-at91-pio4.c #define ATMEL_PIO_IFEN_MASK BIT(12) BIT 40 drivers/pinctrl/pinctrl-at91-pio4.c #define ATMEL_PIO_IFSCEN_MASK BIT(13) BIT 41 drivers/pinctrl/pinctrl-at91-pio4.c #define ATMEL_PIO_OPD_MASK BIT(14) BIT 42 drivers/pinctrl/pinctrl-at91-pio4.c #define ATMEL_PIO_SCHMITT_MASK BIT(15) BIT 173 drivers/pinctrl/pinctrl-at91-pio4.c BIT(pin->line)); BIT 214 drivers/pinctrl/pinctrl-at91-pio4.c BIT(pin->line)); BIT 223 drivers/pinctrl/pinctrl-at91-pio4.c BIT(pin->line)); BIT 238 drivers/pinctrl/pinctrl-at91-pio4.c atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); BIT 240 drivers/pinctrl/pinctrl-at91-pio4.c atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); BIT 312 drivers/pinctrl/pinctrl-at91-pio4.c BIT(pin->line)); BIT 328 drivers/pinctrl/pinctrl-at91-pio4.c return !!(reg & BIT(pin->line)); BIT 340 drivers/pinctrl/pinctrl-at91-pio4.c BIT(pin->line)); BIT 343 drivers/pinctrl/pinctrl-at91-pio4.c BIT(pin->line)); BIT 358 drivers/pinctrl/pinctrl-at91-pio4.c BIT(pin->line)); BIT 380 drivers/pinctrl/pinctrl-at91-pio4.c writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); BIT 396 drivers/pinctrl/pinctrl-at91-pio4.c writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); BIT 879 drivers/pinctrl/pinctrl-at91-pio4.c ATMEL_PIO_MSKR, BIT(j)); BIT 901 drivers/pinctrl/pinctrl-at91-pio4.c ATMEL_PIO_MSKR, BIT(j)); BIT 593 drivers/pinctrl/pinctrl-at91.c if (tmp & BIT(pin)) BIT 603 drivers/pinctrl/pinctrl-at91.c if ((tmp & BIT(pin))) BIT 660 drivers/pinctrl/pinctrl-at91.c tmp &= ~BIT(pin); BIT 662 drivers/pinctrl/pinctrl-at91.c tmp |= BIT(pin); BIT 678 drivers/pinctrl/pinctrl-at91.c tmp &= ~BIT(pin); BIT 680 drivers/pinctrl/pinctrl-at91.c tmp |= BIT(pin); BIT 1457 drivers/pinctrl/pinctrl-at91.c #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) BIT 38 drivers/pinctrl/pinctrl-axp209.c #define AXP20X_MUX_GPIO_IN BIT(1) BIT 39 drivers/pinctrl/pinctrl-axp209.c #define AXP20X_MUX_ADC BIT(2) BIT 41 drivers/pinctrl/pinctrl-axp209.c #define AXP813_MUX_ADC (BIT(2) | BIT(0)) BIT 84 drivers/pinctrl/pinctrl-axp209.c .ldo_mask = BIT(0) | BIT(1), BIT 85 drivers/pinctrl/pinctrl-axp209.c .adc_mask = BIT(0) | BIT(1), BIT 93 drivers/pinctrl/pinctrl-axp209.c .ldo_mask = BIT(0) | BIT(1), BIT 94 drivers/pinctrl/pinctrl-axp209.c .adc_mask = BIT(0), BIT 128 drivers/pinctrl/pinctrl-axp209.c return !!(val & BIT(offset + pctl->desc->gpio_status_offset)); BIT 243 drivers/pinctrl/pinctrl-axp209.c if (!(BIT(group) & mask)) BIT 1164 drivers/pinctrl/pinctrl-bm1880.c arg = !!(regval & BIT(bit_offset)); BIT 1168 drivers/pinctrl/pinctrl-bm1880.c arg = !!(regval & BIT(bit_offset)); BIT 1172 drivers/pinctrl/pinctrl-bm1880.c arg = !!(regval & BIT(bit_offset)); BIT 1176 drivers/pinctrl/pinctrl-bm1880.c arg = !!(regval & BIT(bit_offset)); BIT 1180 drivers/pinctrl/pinctrl-bm1880.c arg = !!(regval & BIT(bit_offset)); BIT 1185 drivers/pinctrl/pinctrl-bm1880.c !!(regval & BIT(bit_offset))); BIT 1219 drivers/pinctrl/pinctrl-bm1880.c regval |= BIT(bit_offset); BIT 1223 drivers/pinctrl/pinctrl-bm1880.c regval |= BIT(bit_offset); BIT 1227 drivers/pinctrl/pinctrl-bm1880.c regval |= BIT(bit_offset); BIT 1232 drivers/pinctrl/pinctrl-bm1880.c regval |= BIT(bit_offset); BIT 1234 drivers/pinctrl/pinctrl-bm1880.c regval &= ~BIT(bit_offset); BIT 1239 drivers/pinctrl/pinctrl-bm1880.c regval |= BIT(bit_offset); BIT 1241 drivers/pinctrl/pinctrl-bm1880.c regval &= ~BIT(bit_offset); BIT 74 drivers/pinctrl/pinctrl-da850-pupd.c arg = !!(~val & BIT(selector)); BIT 89 drivers/pinctrl/pinctrl-da850-pupd.c arg = !!(val & BIT(selector)); BIT 118 drivers/pinctrl/pinctrl-da850-pupd.c ena &= ~BIT(selector); BIT 121 drivers/pinctrl/pinctrl-da850-pupd.c ena |= BIT(selector); BIT 122 drivers/pinctrl/pinctrl-da850-pupd.c sel |= BIT(selector); BIT 125 drivers/pinctrl/pinctrl-da850-pupd.c ena |= BIT(selector); BIT 126 drivers/pinctrl/pinctrl-da850-pupd.c sel &= ~BIT(selector); BIT 177 drivers/pinctrl/pinctrl-digicolor.c drive &= ~BIT(bit_off); BIT 199 drivers/pinctrl/pinctrl-digicolor.c drive |= BIT(bit_off); BIT 215 drivers/pinctrl/pinctrl-digicolor.c return !!(input & BIT(bit_off)); BIT 229 drivers/pinctrl/pinctrl-digicolor.c output |= BIT(bit_off); BIT 231 drivers/pinctrl/pinctrl-digicolor.c output &= ~BIT(bit_off); BIT 313 drivers/pinctrl/pinctrl-falcon.c pad_w32(mem, BIT(PORT_PIN(pin)), reg); BIT 314 drivers/pinctrl/pinctrl-falcon.c if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin)))) BIT 86 drivers/pinctrl/pinctrl-gemini.c #define GLOBAL_STATUS_FLPIN BIT(20) BIT 106 drivers/pinctrl/pinctrl-gemini.c #define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28) BIT 108 drivers/pinctrl/pinctrl-gemini.c #define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27) BIT 111 drivers/pinctrl/pinctrl-gemini.c #define TVC_CLK_PAD_ENABLE BIT(20) BIT 112 drivers/pinctrl/pinctrl-gemini.c #define PCI_CLK_PAD_ENABLE BIT(17) BIT 113 drivers/pinctrl/pinctrl-gemini.c #define LPC_CLK_PAD_ENABLE BIT(16) BIT 114 drivers/pinctrl/pinctrl-gemini.c #define TVC_PADS_ENABLE BIT(9) BIT 115 drivers/pinctrl/pinctrl-gemini.c #define SSP_PADS_ENABLE BIT(8) BIT 116 drivers/pinctrl/pinctrl-gemini.c #define LCD_PADS_ENABLE BIT(7) BIT 117 drivers/pinctrl/pinctrl-gemini.c #define LPC_PADS_ENABLE BIT(6) BIT 118 drivers/pinctrl/pinctrl-gemini.c #define PCI_PADS_ENABLE BIT(5) BIT 119 drivers/pinctrl/pinctrl-gemini.c #define IDE_PADS_ENABLE BIT(4) BIT 120 drivers/pinctrl/pinctrl-gemini.c #define DRAM_PADS_POWERDOWN BIT(3) BIT 121 drivers/pinctrl/pinctrl-gemini.c #define NAND_PADS_DISABLE BIT(2) BIT 122 drivers/pinctrl/pinctrl-gemini.c #define PFLASH_PADS_DISABLE BIT(1) BIT 123 drivers/pinctrl/pinctrl-gemini.c #define SFLASH_PADS_DISABLE BIT(0) BIT 124 drivers/pinctrl/pinctrl-gemini.c #define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27)) BIT 2233 drivers/pinctrl/pinctrl-gemini.c if (after & BIT(i)) { BIT 2255 drivers/pinctrl/pinctrl-gemini.c if (!(after & BIT(i))) { BIT 2589 drivers/pinctrl/pinctrl-gemini.c (val & BIT(i)) ? "enabled" : "disabled"); BIT 1350 drivers/pinctrl/pinctrl-ingenic.c regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); BIT 1361 drivers/pinctrl/pinctrl-ingenic.c regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset)); BIT 1375 drivers/pinctrl/pinctrl-ingenic.c return !!(val & BIT(offset)); BIT 1610 drivers/pinctrl/pinctrl-ingenic.c (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); BIT 1619 drivers/pinctrl/pinctrl-ingenic.c (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); BIT 1637 drivers/pinctrl/pinctrl-ingenic.c return val & BIT(idx); BIT 1778 drivers/pinctrl/pinctrl-ingenic.c if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx))) BIT 1783 drivers/pinctrl/pinctrl-ingenic.c if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx))) BIT 1832 drivers/pinctrl/pinctrl-ingenic.c if (!(jzpc->info->pull_ups[offt] & BIT(idx))) BIT 1840 drivers/pinctrl/pinctrl-ingenic.c if (!(jzpc->info->pull_downs[offt] & BIT(idx))) BIT 28 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_REG_ENAIO2_DAC BIT(0) BIT 32 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_PIN_EPD BIT(3) BIT 33 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_PIN_EPUN BIT(4) BIT 34 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_PIN_EHS BIT(5) BIT 35 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_PIN_EZI BIT(6) BIT 36 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_PIN_ZIF BIT(7) BIT 40 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_USB1_EPD BIT(2) BIT 41 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_USB1_EPWR BIT(4) BIT 43 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_I2C0_EFP BIT(0) BIT 44 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_I2C0_EHD BIT(2) BIT 45 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_I2C0_EZI BIT(3) BIT 46 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_SCU_I2C0_ZIF BIT(7) BIT 204 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC18XX_ANALOG_PIN BIT(7) BIT 255 drivers/pinctrl/pinctrl-max77620.c BIT(group), val); BIT 296 drivers/pinctrl/pinctrl-max77620.c if (val & BIT(pin)) BIT 306 drivers/pinctrl/pinctrl-max77620.c if (val & BIT(pin)) BIT 500 drivers/pinctrl/pinctrl-max77620.c BIT(pin) : 0; BIT 502 drivers/pinctrl/pinctrl-max77620.c BIT(pin) : 0; BIT 506 drivers/pinctrl/pinctrl-max77620.c BIT(pin), pu_val); BIT 515 drivers/pinctrl/pinctrl-max77620.c BIT(pin), pd_val); BIT 191 drivers/pinctrl/pinctrl-mcp23s08.c u16 mask = BIT(pin); BIT 267 drivers/pinctrl/pinctrl-mcp23s08.c status = (data & BIT(pin)) ? 1 : 0; BIT 426 drivers/pinctrl/pinctrl-mcp23s08.c unsigned mask = BIT(offset); BIT 437 drivers/pinctrl/pinctrl-mcp23s08.c unsigned mask = BIT(offset); BIT 507 drivers/pinctrl/pinctrl-mcp23s08.c intf_set = intf & BIT(i); BIT 516 drivers/pinctrl/pinctrl-mcp23s08.c (intcap & BIT(i))) != BIT 517 drivers/pinctrl/pinctrl-mcp23s08.c (intcap_mask & (BIT(i) & gpio_orig)); BIT 518 drivers/pinctrl/pinctrl-mcp23s08.c gpio_set = BIT(i) & gpio; BIT 519 drivers/pinctrl/pinctrl-mcp23s08.c gpio_bit_changed = (BIT(i) & gpio_orig) != BIT 520 drivers/pinctrl/pinctrl-mcp23s08.c (BIT(i) & gpio); BIT 521 drivers/pinctrl/pinctrl-mcp23s08.c defval_changed = (BIT(i) & intcon) && BIT 522 drivers/pinctrl/pinctrl-mcp23s08.c ((BIT(i) & gpio) != BIT 523 drivers/pinctrl/pinctrl-mcp23s08.c (BIT(i) & defval)); BIT 526 drivers/pinctrl/pinctrl-mcp23s08.c (BIT(i) & mcp->irq_rise) && gpio_set) || BIT 528 drivers/pinctrl/pinctrl-mcp23s08.c (BIT(i) & mcp->irq_fall) && !gpio_set) || BIT 569 drivers/pinctrl/pinctrl-mcp23s08.c mcp->irq_rise |= BIT(pos); BIT 570 drivers/pinctrl/pinctrl-mcp23s08.c mcp->irq_fall |= BIT(pos); BIT 573 drivers/pinctrl/pinctrl-mcp23s08.c mcp->irq_rise |= BIT(pos); BIT 574 drivers/pinctrl/pinctrl-mcp23s08.c mcp->irq_fall &= ~BIT(pos); BIT 577 drivers/pinctrl/pinctrl-mcp23s08.c mcp->irq_rise &= ~BIT(pos); BIT 578 drivers/pinctrl/pinctrl-mcp23s08.c mcp->irq_fall |= BIT(pos); BIT 1028 drivers/pinctrl/pinctrl-mcp23s08.c if (pdata->spi_present_mask & BIT(addr)) BIT 1043 drivers/pinctrl/pinctrl-mcp23s08.c if (!(pdata->spi_present_mask & BIT(addr))) BIT 421 drivers/pinctrl/pinctrl-ocelot.c BIT(p), f << p); BIT 423 drivers/pinctrl/pinctrl-ocelot.c BIT(p), f << (p - 1)); BIT 437 drivers/pinctrl/pinctrl-ocelot.c regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), BIT 438 drivers/pinctrl/pinctrl-ocelot.c input ? 0 : BIT(p)); BIT 451 drivers/pinctrl/pinctrl-ocelot.c BIT(p), 0); BIT 453 drivers/pinctrl/pinctrl-ocelot.c BIT(p), 0); BIT 583 drivers/pinctrl/pinctrl-ocelot.c return !!(val & BIT(offset % 32)); BIT 593 drivers/pinctrl/pinctrl-ocelot.c BIT(offset % 32)); BIT 596 drivers/pinctrl/pinctrl-ocelot.c BIT(offset % 32)); BIT 607 drivers/pinctrl/pinctrl-ocelot.c return !(val & BIT(offset % 32)); BIT 620 drivers/pinctrl/pinctrl-ocelot.c unsigned int pin = BIT(offset % 32); BIT 650 drivers/pinctrl/pinctrl-ocelot.c BIT(gpio % 32), 0); BIT 660 drivers/pinctrl/pinctrl-ocelot.c BIT(gpio % 32), BIT(gpio % 32)); BIT 670 drivers/pinctrl/pinctrl-ocelot.c BIT(gpio % 32), BIT(gpio % 32)); BIT 595 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pg->pin); BIT 646 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pg->pin); BIT 698 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset - bank->gpio_chip.base); BIT 729 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset - bank->gpio_chip.base); BIT 757 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); BIT 766 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); BIT 776 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); BIT 785 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); BIT 797 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); BIT 843 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pin - bank->gpio_chip.base); BIT 875 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pin - bank->gpio_chip.base); BIT 907 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); BIT 944 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); BIT 985 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(data->hwirq); BIT 995 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(data->hwirq); BIT 1011 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(data->hwirq); BIT 1803 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset - bank->gpio_chip.base); BIT 1817 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset); BIT 1828 drivers/pinctrl/pinctrl-pic32.c return !!(readl(bank->reg_base + PORT_REG) & BIT(offset)); BIT 1835 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset); BIT 1847 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset); BIT 1884 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(pin - bank->gpio_chip.base); BIT 1928 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset); BIT 1993 drivers/pinctrl/pinctrl-pic32.c return !!(readl(bank->reg_base + TRIS_REG) & BIT(offset)); BIT 2007 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG)); BIT 2014 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG)); BIT 2030 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(data->hwirq); BIT 2039 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); BIT 2047 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); BIT 2055 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); BIT 2077 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(pin); BIT 27 drivers/pinctrl/pinctrl-pistachio.c #define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32) BIT 45 drivers/pinctrl/pinctrl-pistachio.c #define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32) BIT 1169 drivers/pinctrl/pinctrl-pistachio.c return !(gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset)); BIT 1177 drivers/pinctrl/pinctrl-pistachio.c if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset)) BIT 1182 drivers/pinctrl/pinctrl-pistachio.c return !!(gpio_readl(bank, reg) & BIT(offset)); BIT 121 drivers/pinctrl/pinctrl-rk805.c #define RK805_GPIO0_VAL_MSK BIT(0) BIT 122 drivers/pinctrl/pinctrl-rk805.c #define RK805_GPIO1_VAL_MSK BIT(1) BIT 68 drivers/pinctrl/pinctrl-rockchip.c #define IOMUX_GPIO_ONLY BIT(0) BIT 69 drivers/pinctrl/pinctrl-rockchip.c #define IOMUX_WIDTH_4BIT BIT(1) BIT 70 drivers/pinctrl/pinctrl-rockchip.c #define IOMUX_SOURCE_PMU BIT(2) BIT 71 drivers/pinctrl/pinctrl-rockchip.c #define IOMUX_UNROUTED BIT(3) BIT 72 drivers/pinctrl/pinctrl-rockchip.c #define IOMUX_WIDTH_3BIT BIT(4) BIT 711 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 7), BIT 718 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 7) | BIT(7), BIT 725 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 8), BIT 732 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 8) | BIT(8), BIT 739 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 10), BIT 746 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 10) | BIT(10), BIT 753 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 9), BIT 760 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 9) | BIT(9), BIT 771 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 3) | BIT(16 + 4), BIT 778 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), BIT 785 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), BIT 792 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 5), BIT 799 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 5) | BIT(5), BIT 806 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 6), BIT 813 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 6) | BIT(6), BIT 825 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 11), BIT 833 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 11) | BIT(11), BIT 844 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16), BIT 851 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16) | BIT(0), BIT 858 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 1), BIT 865 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 1) | BIT(1), BIT 872 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 2), BIT 879 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 2) | BIT(2), BIT 886 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 3), BIT 893 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 3) | BIT(3), BIT 900 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 4), BIT 907 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 4) | BIT(4), BIT 914 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 5), BIT 921 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 5) | BIT(5), BIT 928 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 7), BIT 935 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 7) | BIT(7), BIT 942 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 8), BIT 949 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 8) | BIT(8), BIT 956 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 11), BIT 963 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 11) | BIT(11), BIT 974 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 12) | BIT(12), BIT 981 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 12), BIT 992 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16) | BIT(16 + 1), BIT 999 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16) | BIT(16 + 1) | BIT(0), BIT 1006 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 2) | BIT(2), BIT 1013 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 10) | BIT(10), BIT 1020 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 3), BIT 1027 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 3) | BIT(3), BIT 1034 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), BIT 1041 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 6), BIT 1048 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 6) | BIT(6), BIT 1055 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 7) | BIT(7), BIT 1062 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 8) | BIT(8), BIT 1069 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 9) | BIT(9), BIT 1080 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 10) | BIT(16 + 11), BIT 1087 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), BIT 1094 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), BIT 1101 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 14), BIT 1108 drivers/pinctrl/pinctrl-rockchip.c .route_val = BIT(16 + 14) | BIT(14), BIT 1178 drivers/pinctrl/pinctrl-rockchip.c if (bank->recalced_mask & BIT(pin)) BIT 1266 drivers/pinctrl/pinctrl-rockchip.c if (bank->recalced_mask & BIT(pin)) BIT 1269 drivers/pinctrl/pinctrl-rockchip.c if (bank->route_mask & BIT(pin)) { BIT 1901 drivers/pinctrl/pinctrl-rockchip.c rmask = BIT(15) | BIT(31); BIT 1902 drivers/pinctrl/pinctrl-rockchip.c data |= BIT(31); BIT 1982 drivers/pinctrl/pinctrl-rockchip.c return !(data & BIT(bit)) BIT 2024 drivers/pinctrl/pinctrl-rockchip.c data = BIT(bit + 16); BIT 2026 drivers/pinctrl/pinctrl-rockchip.c data |= BIT(bit); BIT 2127 drivers/pinctrl/pinctrl-rockchip.c data = BIT(bit + 16) | (enable << bit); BIT 2128 drivers/pinctrl/pinctrl-rockchip.c rmask = BIT(bit + 16) | BIT(bit); BIT 2214 drivers/pinctrl/pinctrl-rockchip.c return !(data & BIT(offset)); BIT 2242 drivers/pinctrl/pinctrl-rockchip.c data |= BIT(pin); BIT 2244 drivers/pinctrl/pinctrl-rockchip.c data &= ~BIT(pin); BIT 2701 drivers/pinctrl/pinctrl-rockchip.c data &= ~BIT(offset); BIT 2703 drivers/pinctrl/pinctrl-rockchip.c data |= BIT(offset); BIT 2762 drivers/pinctrl/pinctrl-rockchip.c data |= BIT(offset); BIT 2764 drivers/pinctrl/pinctrl-rockchip.c data &= ~BIT(offset); BIT 2851 drivers/pinctrl/pinctrl-rockchip.c pend &= ~BIT(irq); BIT 2865 drivers/pinctrl/pinctrl-rockchip.c if (bank->toggle_edge_mode & BIT(irq)) { BIT 2875 drivers/pinctrl/pinctrl-rockchip.c if (data & BIT(irq)) BIT 2876 drivers/pinctrl/pinctrl-rockchip.c polarity &= ~BIT(irq); BIT 2878 drivers/pinctrl/pinctrl-rockchip.c polarity |= BIT(irq); BIT 2887 drivers/pinctrl/pinctrl-rockchip.c } while ((data & BIT(irq)) != (data_old & BIT(irq))); BIT 2900 drivers/pinctrl/pinctrl-rockchip.c u32 mask = BIT(d->hwirq); BIT 3336 drivers/pinctrl/pinctrl-rockchip.c bank->recalced_mask |= BIT(pin); BIT 3346 drivers/pinctrl/pinctrl-rockchip.c bank->route_mask |= BIT(pin); BIT 3355 drivers/pinctrl/pinctrl-rockchip.c #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) BIT 65 drivers/pinctrl/pinctrl-rza1.c #define MUX_FUNC_PFC_MASK BIT(0) BIT 66 drivers/pinctrl/pinctrl-rza1.c #define MUX_FUNC_PFCE_MASK BIT(1) BIT 67 drivers/pinctrl/pinctrl-rza1.c #define MUX_FUNC_PFCEA_MASK BIT(2) BIT 70 drivers/pinctrl/pinctrl-rza1.c #define MUX_FLAGS_BIDIR BIT(0) BIT 71 drivers/pinctrl/pinctrl-rza1.c #define MUX_FLAGS_SWIO_INPUT BIT(1) BIT 72 drivers/pinctrl/pinctrl-rza1.c #define MUX_FLAGS_SWIO_OUTPUT BIT(2) BIT 580 drivers/pinctrl/pinctrl-rza1.c val |= BIT(bit); BIT 582 drivers/pinctrl/pinctrl-rza1.c val &= ~BIT(bit); BIT 592 drivers/pinctrl/pinctrl-rza1.c return ioread16(mem) & BIT(bit); BIT 68 drivers/pinctrl/pinctrl-rza2.c #define PWPR_B0WI BIT(7) /* Bit Write Disable */ BIT 69 drivers/pinctrl/pinctrl-rza2.c #define PWPR_PFSWE BIT(6) /* PFS Register Write Enable */ BIT 70 drivers/pinctrl/pinctrl-rza2.c #define PFS_ISEL BIT(6) /* Interrupt Select */ BIT 87 drivers/pinctrl/pinctrl-rza2.c reg8 &= ~BIT(pin); BIT 103 drivers/pinctrl/pinctrl-rza2.c reg8 |= BIT(pin); BIT 168 drivers/pinctrl/pinctrl-rza2.c return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin)); BIT 182 drivers/pinctrl/pinctrl-rza2.c new_value |= BIT(pin); BIT 184 drivers/pinctrl/pinctrl-rza2.c new_value &= ~BIT(pin); BIT 80 drivers/pinctrl/pinctrl-st.c #define RT_D_CFG_CLKNOTDATA_MASK BIT(2) BIT 84 drivers/pinctrl/pinctrl-st.c #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) BIT 86 drivers/pinctrl/pinctrl-st.c #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) BIT 88 drivers/pinctrl/pinctrl-st.c #define RT_D_CFG_INVERTCLK_MASK BIT(9) BIT 90 drivers/pinctrl/pinctrl-st.c #define RT_D_CFG_RETIME_MASK BIT(10) BIT 136 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_OE BIT(27) BIT 143 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_PU BIT(26) BIT 150 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_OD BIT(25) BIT 156 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_RT BIT(23) BIT 162 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_RT_INVERTCLK BIT(22) BIT 170 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_RT_CLKNOTDATA BIT(21) BIT 178 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) BIT 186 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_RT_CLK BIT(18) BIT 296 drivers/pinctrl/pinctrl-st.c #define ST_IRQ_EDGE_FALLING BIT(0) BIT 297 drivers/pinctrl/pinctrl-st.c #define ST_IRQ_EDGE_RISING BIT(1) BIT 298 drivers/pinctrl/pinctrl-st.c #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) BIT 390 drivers/pinctrl/pinctrl-st.c unsigned long mask = BIT(pin); BIT 510 drivers/pinctrl/pinctrl-st.c val |= BIT(pin); BIT 512 drivers/pinctrl/pinctrl-st.c val &= ~BIT(pin); BIT 581 drivers/pinctrl/pinctrl-st.c if (oe_value & BIT(pin)) BIT 587 drivers/pinctrl/pinctrl-st.c if (pu_value & BIT(pin)) BIT 593 drivers/pinctrl/pinctrl-st.c if (od_value & BIT(pin)) BIT 606 drivers/pinctrl/pinctrl-st.c if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) BIT 609 drivers/pinctrl/pinctrl-st.c if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) BIT 612 drivers/pinctrl/pinctrl-st.c if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) BIT 615 drivers/pinctrl/pinctrl-st.c if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) BIT 618 drivers/pinctrl/pinctrl-st.c if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) BIT 623 drivers/pinctrl/pinctrl-st.c delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | BIT 624 drivers/pinctrl/pinctrl-st.c (((delay0 & BIT(pin)) ? 1 : 0)); BIT 669 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_SET_POUT); BIT 671 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); BIT 697 drivers/pinctrl/pinctrl-st.c if (direction & BIT(i)) BIT 698 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); BIT 700 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); BIT 708 drivers/pinctrl/pinctrl-st.c return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); BIT 945 drivers/pinctrl/pinctrl-st.c if ((BIT(pin) & pc->rt_pin_mask)) BIT 956 drivers/pinctrl/pinctrl-st.c if ((BIT(pin) & pc->rt_pin_mask)) BIT 1095 drivers/pinctrl/pinctrl-st.c if (BIT(j) & pin_mask) { BIT 1282 drivers/pinctrl/pinctrl-st.c writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); BIT 1290 drivers/pinctrl/pinctrl-st.c writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); BIT 1348 drivers/pinctrl/pinctrl-st.c val &= ~BIT(pin); BIT 1407 drivers/pinctrl/pinctrl-st.c writel(BIT(n), BIT 47 drivers/pinctrl/pinctrl-stmfx.c #define get_mask(offset) (BIT(get_shift(offset))) BIT 400 drivers/pinctrl/pinctrl-sx150x.c return !!(value & BIT(offset)); BIT 416 drivers/pinctrl/pinctrl-sx150x.c return !!(value & BIT(offset)); BIT 423 drivers/pinctrl/pinctrl-sx150x.c BIT(offset), value ? BIT(offset) : 0); BIT 465 drivers/pinctrl/pinctrl-sx150x.c BIT(offset), BIT(offset)); BIT 483 drivers/pinctrl/pinctrl-sx150x.c BIT(offset), 0); BIT 492 drivers/pinctrl/pinctrl-sx150x.c pctl->irq.masked |= BIT(n); BIT 501 drivers/pinctrl/pinctrl-sx150x.c pctl->irq.masked &= ~BIT(n); BIT 622 drivers/pinctrl/pinctrl-sx150x.c data &= BIT(pin); BIT 637 drivers/pinctrl/pinctrl-sx150x.c data &= BIT(pin); BIT 655 drivers/pinctrl/pinctrl-sx150x.c data &= BIT(pin); BIT 673 drivers/pinctrl/pinctrl-sx150x.c data &= BIT(pin); BIT 740 drivers/pinctrl/pinctrl-sx150x.c BIT(pin), 0); BIT 746 drivers/pinctrl/pinctrl-sx150x.c BIT(pin), 0); BIT 755 drivers/pinctrl/pinctrl-sx150x.c BIT(pin), BIT(pin)); BIT 764 drivers/pinctrl/pinctrl-sx150x.c BIT(pin), BIT(pin)); BIT 777 drivers/pinctrl/pinctrl-sx150x.c BIT(pin), BIT(pin)); BIT 790 drivers/pinctrl/pinctrl-sx150x.c BIT(pin), 0); BIT 59 drivers/pinctrl/pinctrl-xway.c #define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p))) BIT 60 drivers/pinctrl/pinctrl-xway.c #define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r) BIT 61 drivers/pinctrl/pinctrl-xway.c #define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r) BIT 945 drivers/pinctrl/pinctrl-zynq.c #define ZYNQ_PINCONF_TRISTATE BIT(0) BIT 946 drivers/pinctrl/pinctrl-zynq.c #define ZYNQ_PINCONF_SPEED BIT(8) BIT 947 drivers/pinctrl/pinctrl-zynq.c #define ZYNQ_PINCONF_PULLUP BIT(12) BIT 948 drivers/pinctrl/pinctrl-zynq.c #define ZYNQ_PINCONF_DISABLE_RECVR BIT(13) BIT 99 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = (val & ~BIT(pin % 32)) | (input ? 0 : BIT(pin % 32)); BIT 168 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = (val & ~BIT(pin % 32)) | ((df->muxval & 1) ? BIT(pin % 32) : 0); BIT 195 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = readl_relaxed(pgsr) & BIT(pin % 32); BIT 232 drivers/pinctrl/pxa/pinctrl-pxa2xx.c val = (val & ~BIT(pin % 32)) | (is_set ? BIT(pin % 32) : 0); BIT 314 drivers/pinctrl/qcom/pinctrl-msm.c arg = !!(val & BIT(g->in_bit)); BIT 389 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->out_bit); BIT 391 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->out_bit); BIT 443 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->oe_bit); BIT 464 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->out_bit); BIT 466 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->out_bit); BIT 470 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->oe_bit); BIT 489 drivers/pinctrl/qcom/pinctrl-msm.c return val & BIT(g->oe_bit) ? 0 : 1; BIT 501 drivers/pinctrl/qcom/pinctrl-msm.c return !!(val & BIT(g->in_bit)); BIT 517 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->out_bit); BIT 519 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->out_bit); BIT 563 drivers/pinctrl/qcom/pinctrl-msm.c is_out = !!(ctl_reg & BIT(g->oe_bit)); BIT 569 drivers/pinctrl/qcom/pinctrl-msm.c val = !!(io_reg & BIT(g->out_bit)); BIT 571 drivers/pinctrl/qcom/pinctrl-msm.c val = !!(io_reg & BIT(g->in_bit)); BIT 687 drivers/pinctrl/qcom/pinctrl-msm.c val = msm_readl_io(pctrl, g) & BIT(g->in_bit); BIT 690 drivers/pinctrl/qcom/pinctrl-msm.c pol ^= BIT(g->intr_polarity_bit); BIT 693 drivers/pinctrl/qcom/pinctrl-msm.c val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); BIT 736 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->intr_raw_status_bit); BIT 738 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->intr_enable_bit); BIT 765 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->intr_status_bit); BIT 770 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_raw_status_bit); BIT 771 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_enable_bit); BIT 804 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_status_bit); BIT 806 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~BIT(g->intr_status_bit); BIT 847 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_raw_status_bit); BIT 854 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); BIT 858 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); BIT 862 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); BIT 867 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); BIT 875 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_detection_bit); BIT 876 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); BIT 879 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_detection_bit); BIT 882 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_detection_bit); BIT 883 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); BIT 888 drivers/pinctrl/qcom/pinctrl-msm.c val |= BIT(g->intr_polarity_bit); BIT 979 drivers/pinctrl/qcom/pinctrl-msm.c if (val & BIT(g->intr_status_bit)) { BIT 565 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c val = BIT(pad->dtest_buffer - 1); BIT 26 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c #define PM8XXX_GPIO_MODE_ENABLED BIT(0) BIT 46 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c #define PM8XXX_BANK_WRITE BIT(7) BIT 338 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(2); BIT 340 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(3); BIT 344 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(2); BIT 346 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(3); BIT 357 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(2); BIT 359 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(3); BIT 363 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(3); BIT 367 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(0) | BIT(1); BIT 372 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(0) | BIT(1); BIT 376 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(0); BIT 384 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(3); BIT 388 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(1); BIT 392 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c banks |= BIT(1); BIT 402 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (banks & BIT(0)) { BIT 408 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (banks & BIT(1)) { BIT 415 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (banks & BIT(2)) { BIT 420 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (banks & BIT(3)) { BIT 426 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (banks & BIT(4)) { BIT 431 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c if (banks & BIT(5)) { BIT 434 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= BIT(3); BIT 654 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->open_drain = !!(val & BIT(1)); BIT 655 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->output_value = val & BIT(0); BIT 672 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->disable = val & BIT(0); BIT 684 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin->inverted = !(val & BIT(3)); BIT 198 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c ctrl |= BIT(1); BIT 209 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c ctrl |= BIT(1); BIT 225 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c ctrl |= BIT(1); BIT 679 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c pin->output_value = !!(ctrl & BIT(0)); BIT 680 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c pin->paired = !!(ctrl & BIT(1)); BIT 711 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c pin->output_value = !!(ctrl & BIT(0)); BIT 712 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c pin->paired = !!(ctrl & BIT(1)); BIT 717 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c pin->output_value = !!(ctrl & BIT(0)); BIT 718 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c pin->paired = !!(ctrl & BIT(1)); BIT 159 drivers/pinctrl/sh-pfc/gpio.c reg->shadow |= BIT(pos); BIT 161 drivers/pinctrl/sh-pfc/gpio.c reg->shadow &= ~BIT(pos); BIT 3132 drivers/pinctrl/sh-pfc/pfc-r8a7778.c if (ioread32(addr) & BIT(bit)) BIT 3152 drivers/pinctrl/sh-pfc/pfc-r8a7778.c value = ioread32(addr) & ~BIT(bit); BIT 3154 drivers/pinctrl/sh-pfc/pfc-r8a7778.c value |= BIT(bit); BIT 5833 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) BIT 5835 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) BIT 5852 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); BIT 5854 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c enable |= BIT(bit); BIT 5856 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); BIT 5858 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c updown |= BIT(bit); BIT 6185 drivers/pinctrl/sh-pfc/pfc-r8a7795.c if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) BIT 6187 drivers/pinctrl/sh-pfc/pfc-r8a7795.c else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) BIT 6204 drivers/pinctrl/sh-pfc/pfc-r8a7795.c enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); BIT 6206 drivers/pinctrl/sh-pfc/pfc-r8a7795.c enable |= BIT(bit); BIT 6208 drivers/pinctrl/sh-pfc/pfc-r8a7795.c updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); BIT 6210 drivers/pinctrl/sh-pfc/pfc-r8a7795.c updown |= BIT(bit); BIT 6151 drivers/pinctrl/sh-pfc/pfc-r8a7796.c if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) BIT 6153 drivers/pinctrl/sh-pfc/pfc-r8a7796.c else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) BIT 6170 drivers/pinctrl/sh-pfc/pfc-r8a7796.c enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); BIT 6172 drivers/pinctrl/sh-pfc/pfc-r8a7796.c enable |= BIT(bit); BIT 6174 drivers/pinctrl/sh-pfc/pfc-r8a7796.c updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); BIT 6176 drivers/pinctrl/sh-pfc/pfc-r8a7796.c updown |= BIT(bit); BIT 6391 drivers/pinctrl/sh-pfc/pfc-r8a77965.c if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) BIT 6393 drivers/pinctrl/sh-pfc/pfc-r8a77965.c else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) BIT 6410 drivers/pinctrl/sh-pfc/pfc-r8a77965.c enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); BIT 6412 drivers/pinctrl/sh-pfc/pfc-r8a77965.c enable |= BIT(bit); BIT 6414 drivers/pinctrl/sh-pfc/pfc-r8a77965.c updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); BIT 6416 drivers/pinctrl/sh-pfc/pfc-r8a77965.c updown |= BIT(bit); BIT 5238 drivers/pinctrl/sh-pfc/pfc-r8a77990.c if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) BIT 5240 drivers/pinctrl/sh-pfc/pfc-r8a77990.c else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) BIT 5257 drivers/pinctrl/sh-pfc/pfc-r8a77990.c enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); BIT 5259 drivers/pinctrl/sh-pfc/pfc-r8a77990.c enable |= BIT(bit); BIT 5261 drivers/pinctrl/sh-pfc/pfc-r8a77990.c updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); BIT 5263 drivers/pinctrl/sh-pfc/pfc-r8a77990.c updown |= BIT(bit); BIT 4242 drivers/pinctrl/sh-pfc/pfc-sh73a0.c value |= BIT(28); BIT 4244 drivers/pinctrl/sh-pfc/pfc-sh73a0.c value &= ~BIT(28); BIT 4274 drivers/pinctrl/sh-pfc/pfc-sh73a0.c return !!(value & BIT(28)); BIT 654 drivers/pinctrl/sh-pfc/pinctrl.c arg = (val & BIT(bit)) ? 3300 : 1800; BIT 724 drivers/pinctrl/sh-pfc/pinctrl.c val |= BIT(bit); BIT 726 drivers/pinctrl/sh-pfc/pinctrl.c val &= ~BIT(bit); BIT 133 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30) | BIT(31), BIT 136 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT 137 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT 138 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT 139 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(20) | BIT(21) | BIT(22) | BIT(31), BIT 147 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(4), BIT 157 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT 158 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT 159 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT 160 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(20) | BIT(21) | BIT(22) | BIT(31), BIT 163 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30) | BIT(31), BIT 166 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(16) | BIT(17), BIT 174 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(4) | BIT(15), BIT 184 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT 185 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT 186 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT 187 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(20) | BIT(21) | BIT(22) | BIT(31), BIT 190 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30) | BIT(31), BIT 193 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT 194 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(21) | BIT(22) | BIT(23), BIT 202 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(4) | BIT(15), BIT 213 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT 214 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT 215 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(17) | BIT(18) | BIT(19) | BIT 216 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(20) | BIT(21) | BIT(22) | BIT(31), BIT 219 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30) | BIT(31), BIT 222 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(8), BIT 230 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(4), BIT 231 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(4), BIT 240 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(12), BIT 243 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(23), BIT 246 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(4) | BIT(5), BIT 254 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(9), BIT 255 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(9), BIT 263 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(4) | BIT(5), BIT 277 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(15) | BIT(17), BIT 291 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(10) | BIT(14), BIT 294 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(16) | BIT(18), BIT 302 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(10), BIT 303 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(10), BIT 311 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(16) | BIT(18), BIT 325 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30) | BIT(31), BIT 328 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), BIT 336 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(7), BIT 345 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30), BIT 348 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(0) | BIT(2) | BIT(3), BIT 356 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(7), BIT 357 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(7), BIT 365 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(10), BIT 373 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(3), BIT 382 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(10), BIT 390 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(3), BIT 391 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(3), BIT 399 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(19), BIT 407 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(2), BIT 408 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(2), BIT 416 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), BIT 431 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3) | BIT(4), BIT 446 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), BIT 454 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(1) | BIT(9), BIT 455 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(1) | BIT(9), BIT 463 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), BIT 477 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), BIT 485 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(16), BIT 494 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3), BIT 502 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(5), BIT 503 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(5), BIT 511 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(24) | BIT(25) | BIT(26), BIT 519 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(13), BIT 528 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(24) | BIT(25) | BIT(26), BIT 536 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(13), BIT 537 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(13), BIT 545 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), BIT 553 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(1) | BIT(2) | BIT(9), BIT 562 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), BIT 570 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(1) | BIT(2) | BIT(6), BIT 579 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23), BIT 587 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(1) | BIT(2) | BIT(9), BIT 596 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(20) | BIT(21), BIT 609 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(15), BIT 612 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), BIT 620 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(16), BIT 621 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(16), BIT 629 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(12) | BIT(13), BIT 637 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(16), BIT 638 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(16), BIT 646 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), BIT 649 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(0) | BIT(1), BIT 657 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(5) | BIT(19), BIT 666 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(1), BIT 674 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(5) | BIT(19), BIT 675 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(19), BIT 683 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(27) | BIT(28) | BIT(29), BIT 691 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(11), BIT 700 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(27) | BIT(28), BIT 708 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(11), BIT 717 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(14), BIT 731 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9) BIT 732 drivers/pinctrl/sirf/pinctrl-atlas6.c | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) | BIT 733 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(29), BIT 741 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(18), BIT 742 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(18), BIT 751 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) BIT 752 drivers/pinctrl/sirf/pinctrl-atlas6.c | BIT(21) | BIT(22) | BIT(23), BIT 755 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(23) | BIT(24) | BIT(25), BIT 763 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(15), BIT 764 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(15), BIT 773 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(26) | BIT(27), BIT 787 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(13) | BIT(15), BIT 795 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(16), BIT 804 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(4), BIT 812 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(12), BIT 821 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(5), BIT 835 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(6), BIT 849 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(7), BIT 863 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(14), BIT 877 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(8), BIT 885 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(4), BIT 894 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) BIT 895 drivers/pinctrl/sirf/pinctrl-atlas6.c | BIT(9) | BIT(24) | BIT(25) | BIT(26) | BIT 896 drivers/pinctrl/sirf/pinctrl-atlas6.c BIT(27) | BIT(28) | BIT(29), BIT 903 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(18), BIT 913 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(28), BIT 921 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(11), BIT 922 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ BIT 930 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(2), BIT 931 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcval = BIT(2), BIT 939 drivers/pinctrl/sirf/pinctrl-atlas6.c .funcmask = BIT(2), BIT 948 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(9) | BIT(10) | BIT(11), BIT 57 drivers/pinctrl/sirf/pinctrl-atlas7.c #define DS3 BIT(3) BIT 58 drivers/pinctrl/sirf/pinctrl-atlas7.c #define DS2 BIT(2) BIT 59 drivers/pinctrl/sirf/pinctrl-atlas7.c #define DS1 BIT(1) BIT 60 drivers/pinctrl/sirf/pinctrl-atlas7.c #define DS0 BIT(0) BIT 101 drivers/pinctrl/sirf/pinctrl-atlas7.c #define PUN BIT(1) BIT 102 drivers/pinctrl/sirf/pinctrl-atlas7.c #define PD BIT(0) BIT 103 drivers/pinctrl/sirf/pinctrl-atlas7.c #define PE BIT(0) BIT 329 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0) BIT 330 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1) BIT 331 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2) BIT 332 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3) BIT 333 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4) BIT 334 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5) BIT 335 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6) BIT 336 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7) BIT 137 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 138 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT 139 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT 140 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(17) | BIT(18), BIT 143 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(31), BIT 151 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(4), BIT 161 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 162 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT 163 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT 164 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(17) | BIT(18), BIT 167 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(31), BIT 170 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(16) | BIT(17), BIT 178 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(4), BIT 188 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 189 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT 190 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT 191 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(17) | BIT(18), BIT 194 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(31), BIT 197 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT 198 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(21) | BIT(22) | BIT(23), BIT 206 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(4), BIT 217 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 218 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT 219 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT 220 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(17) | BIT(18), BIT 223 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(31), BIT 226 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(23), BIT 234 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(4), BIT 235 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(4), BIT 244 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(4) | BIT(5), BIT 247 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(23) | BIT(28), BIT 255 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(9), BIT 256 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(9), BIT 264 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(4) | BIT(5), BIT 278 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(15) | BIT(17), BIT 292 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27), BIT 300 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(10), BIT 301 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(10), BIT 309 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(16) | BIT(18), BIT 323 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(30) | BIT(31), BIT 326 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), BIT 334 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(7), BIT 343 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), BIT 351 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(7), BIT 352 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(7), BIT 360 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9), BIT 374 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(10), BIT 382 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(3), BIT 391 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(10), BIT 399 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(3), BIT 400 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(3), BIT 408 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(19), BIT 416 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(2), BIT 417 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(2), BIT 425 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), BIT 440 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(11) | BIT(12) | BIT(14), BIT 455 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14) BIT 456 drivers/pinctrl/sirf/pinctrl-prima2.c | BIT(23) | BIT(28), BIT 464 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(1) | BIT(9), BIT 465 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(1) | BIT(9), BIT 473 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), BIT 481 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(8), BIT 490 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), BIT 498 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(8), BIT 499 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(8), BIT 507 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(27) | BIT(28) | BIT(29), BIT 521 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(24) | BIT(25) | BIT(26), BIT 529 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(12) | BIT(13) | BIT(14), BIT 530 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(12), BIT 538 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(24) | BIT(25) | BIT(26), BIT 546 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(13) | BIT(14), BIT 547 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(13) | BIT(14), BIT 555 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), BIT 563 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9), BIT 572 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), BIT 580 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(1) | BIT(2) | BIT(6), BIT 589 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23), BIT 597 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(1) | BIT(2) | BIT(9), BIT 606 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(20) | BIT(21), BIT 620 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28), BIT 628 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11), BIT 637 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(25) | BIT(26), BIT 651 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(29) | BIT(30) | BIT(31), BIT 654 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1), BIT 662 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(13) | BIT(14), BIT 671 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(30) | BIT(31), BIT 685 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), BIT 693 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(5), BIT 702 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(5), BIT 711 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(2) | BIT(3), BIT 719 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(5), BIT 720 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(5), BIT 728 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(14), BIT 742 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) BIT 743 drivers/pinctrl/sirf/pinctrl-prima2.c | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT 744 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(25), BIT 752 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(0), BIT 762 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(26) | BIT(27), BIT 776 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(13) | BIT(15), BIT 790 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) BIT 791 drivers/pinctrl/sirf/pinctrl-prima2.c | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT 792 drivers/pinctrl/sirf/pinctrl-prima2.c BIT(25), BIT 795 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(12), BIT 803 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(0), BIT 804 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(0), BIT 813 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(4), BIT 821 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(12), BIT 830 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(5), BIT 844 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(6), BIT 858 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(7), BIT 872 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(8), BIT 886 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(22), BIT 893 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(6), BIT 894 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */ BIT 902 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(27), BIT 910 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(11), BIT 911 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ BIT 919 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(2), BIT 920 drivers/pinctrl/sirf/pinctrl-prima2.c .funcval = BIT(2), BIT 928 drivers/pinctrl/sirf/pinctrl-prima2.c .funcmask = BIT(2), BIT 937 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(9) | BIT(10) | BIT(11), BIT 34 drivers/pinctrl/sprd/pinctrl-sprd.c #define PIN_FUNC_MASK (BIT(4) | BIT(5)) BIT 36 drivers/pinctrl/sprd/pinctrl-sprd.c #define PIN_FUNC_SEL_2 BIT(4) BIT 37 drivers/pinctrl/sprd/pinctrl-sprd.c #define PIN_FUNC_SEL_3 BIT(5) BIT 40 drivers/pinctrl/sprd/pinctrl-sprd.c #define AP_SLEEP_MODE BIT(13) BIT 41 drivers/pinctrl/sprd/pinctrl-sprd.c #define PUBCP_SLEEP_MODE BIT(14) BIT 42 drivers/pinctrl/sprd/pinctrl-sprd.c #define TGLDSP_SLEEP_MODE BIT(15) BIT 43 drivers/pinctrl/sprd/pinctrl-sprd.c #define AGDSP_SLEEP_MODE BIT(16) BIT 47 drivers/pinctrl/sprd/pinctrl-sprd.c #define SLEEP_INPUT BIT(1) BIT 51 drivers/pinctrl/sprd/pinctrl-sprd.c #define SLEEP_OUTPUT BIT(0) BIT 58 drivers/pinctrl/sprd/pinctrl-sprd.c #define SLEEP_PULL_DOWN BIT(2) BIT 62 drivers/pinctrl/sprd/pinctrl-sprd.c #define PULL_DOWN BIT(6) BIT 66 drivers/pinctrl/sprd/pinctrl-sprd.c #define SLEEP_PULL_UP BIT(3) BIT 70 drivers/pinctrl/sprd/pinctrl-sprd.c #define PULL_UP_20K (BIT(12) | BIT(7)) BIT 71 drivers/pinctrl/sprd/pinctrl-sprd.c #define PULL_UP_4_7K BIT(12) BIT 75 drivers/pinctrl/sprd/pinctrl-sprd.c #define INPUT_SCHMITT BIT(11) BIT 80 drivers/pinctrl/sprd/pinctrl-sprd.c AP_SLEEP = BIT(0), BIT 81 drivers/pinctrl/sprd/pinctrl-sprd.c PUBCP_SLEEP = BIT(1), BIT 82 drivers/pinctrl/sprd/pinctrl-sprd.c TGLDSP_SLEEP = BIT(2), BIT 83 drivers/pinctrl/sprd/pinctrl-sprd.c AGDSP_SLEEP = BIT(3), BIT 509 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(19); BIT 512 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(20); BIT 515 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(19) | BIT(20); BIT 518 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(21); BIT 521 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(21) | BIT(19); BIT 524 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(21) | BIT(20); BIT 527 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(19) | BIT(20) | BIT(21); BIT 530 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22); BIT 533 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(19); BIT 536 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(20); BIT 539 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(20) | BIT(19); BIT 542 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(21); BIT 545 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(21) | BIT(19); BIT 548 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(21) | BIT(20); BIT 551 drivers/pinctrl/sprd/pinctrl-sprd.c val |= BIT(22) | BIT(21) | BIT(20) | BIT(19); BIT 154 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); BIT 170 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); BIT 200 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); BIT 233 drivers/pinctrl/stm32/pinctrl-stm32.c ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); BIT 380 drivers/pinctrl/stm32/pinctrl-stm32.c if (pctl->irqmux_map & BIT(irq_data->hwirq)) { BIT 388 drivers/pinctrl/stm32/pinctrl-stm32.c pctl->irqmux_map |= BIT(irq_data->hwirq); BIT 409 drivers/pinctrl/stm32/pinctrl-stm32.c pctl->irqmux_map &= ~BIT(irq_data->hwirq); BIT 830 drivers/pinctrl/stm32/pinctrl-stm32.c val &= ~BIT(offset); BIT 856 drivers/pinctrl/stm32/pinctrl-stm32.c val &= BIT(offset); BIT 983 drivers/pinctrl/stm32/pinctrl-stm32.c BIT(offset)); BIT 986 drivers/pinctrl/stm32/pinctrl-stm32.c BIT(offset)); BIT 1517 drivers/pinctrl/stm32/pinctrl-stm32.c val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); BIT 1522 drivers/pinctrl/stm32/pinctrl-stm32.c val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); BIT 22 drivers/pinctrl/stm32/pinctrl-stm32.h #define STM32MP_PKG_AA BIT(0) BIT 23 drivers/pinctrl/stm32/pinctrl-stm32.h #define STM32MP_PKG_AB BIT(1) BIT 24 drivers/pinctrl/stm32/pinctrl-stm32.h #define STM32MP_PKG_AC BIT(2) BIT 25 drivers/pinctrl/stm32/pinctrl-stm32.h #define STM32MP_PKG_AD BIT(3) BIT 875 drivers/pinctrl/sunxi/pinctrl-sunxi.c regval |= BIT(index); BIT 877 drivers/pinctrl/sunxi/pinctrl-sunxi.c regval &= ~(BIT(index)); BIT 89 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define PINCTRL_SUN5I_A10S BIT(1) BIT 90 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define PINCTRL_SUN5I_A13 BIT(2) BIT 91 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define PINCTRL_SUN5I_GR8 BIT(3) BIT 92 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define PINCTRL_SUN6I_A31 BIT(4) BIT 93 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define PINCTRL_SUN6I_A31S BIT(5) BIT 94 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define PINCTRL_SUN4I_A10 BIT(6) BIT 95 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define PINCTRL_SUN7I_A20 BIT(7) BIT 96 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define PINCTRL_SUN8I_R40 BIT(8) BIT 97 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define PINCTRL_SUN8I_V3 BIT(9) BIT 98 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define PINCTRL_SUN8I_V3S BIT(10) BIT 347 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c if (value & BIT(lane->iddq)) BIT 391 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c regval &= ~BIT(lane->iddq); BIT 393 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c regval |= BIT(lane->iddq); BIT 495 drivers/pinctrl/tegra/pinctrl-tegra.c if ((val & BIT(bit)) && !arg) { BIT 1319 drivers/pinctrl/tegra/pinctrl-tegra210.c .parked_bitmask = BIT(5), \ BIT 298 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c mask = BIT(iectrl % 32); BIT 478 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c mask = BIT(iectrl % 32); BIT 148 drivers/pinctrl/uniphier/pinctrl-uniphier.h #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1) BIT 149 drivers/pinctrl/uniphier/pinctrl-uniphier.h #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0) BIT 105 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_setbits(data, reg_en, BIT(bit)); BIT 106 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_clearbits(data, reg_dir, BIT(bit)); BIT 110 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_setbits(data, reg_en, BIT(bit)); BIT 111 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_setbits(data, reg_dir, BIT(bit)); BIT 119 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_clearbits(data, reg_en, BIT(bit)); BIT 448 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_clearbits(data, reg_pull_en, BIT(bit)); BIT 451 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_clearbits(data, reg_pull_cfg, BIT(bit)); BIT 452 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_setbits(data, reg_pull_en, BIT(bit)); BIT 455 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_setbits(data, reg_pull_cfg, BIT(bit)); BIT 456 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_setbits(data, reg_pull_en, BIT(bit)); BIT 490 drivers/pinctrl/vt8500/pinctrl-wmt.c return !(val & BIT(bit)); BIT 505 drivers/pinctrl/vt8500/pinctrl-wmt.c return !!(readl_relaxed(data->base + reg_data_in) & BIT(bit)); BIT 522 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_setbits(data, reg_data_out, BIT(bit)); BIT 524 drivers/pinctrl/vt8500/pinctrl-wmt.c wmt_clearbits(data, reg_data_out, BIT(bit)); BIT 22 drivers/pinctrl/zte/pinctrl-zx.c #define ZX_PULL_DOWN BIT(0) BIT 23 drivers/pinctrl/zte/pinctrl-zx.c #define ZX_PULL_UP BIT(1) BIT 24 drivers/pinctrl/zte/pinctrl-zx.c #define ZX_INPUT_ENABLE BIT(3) BIT 28 drivers/pinctrl/zte/pinctrl-zx.c #define ZX_SLEW BIT(8) BIT 92 drivers/pinctrl/zte/pinctrl-zx.h #define AON_MUX_FLAG BIT(7) BIT 42 drivers/platform/chrome/wilco_ec/mailbox.c #define EC_CMDR_DATA BIT(0) /* Data ready for host to read */ BIT 43 drivers/platform/chrome/wilco_ec/mailbox.c #define EC_CMDR_PENDING BIT(1) /* Write pending to EC */ BIT 44 drivers/platform/chrome/wilco_ec/mailbox.c #define EC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ BIT 45 drivers/platform/chrome/wilco_ec/mailbox.c #define EC_CMDR_CMD BIT(3) /* Last host write was a command */ BIT 847 drivers/platform/mellanox/mlxbf-tmfifo.c if (vring->index & BIT(0)) { BIT 287 drivers/platform/mellanox/mlxreg-hotplug.c if (regval & BIT(bit)) { BIT 528 drivers/platform/mellanox/mlxreg-hotplug.c item->mask &= ~BIT(j); BIT 65 drivers/platform/x86/asus-wmi.c #define ASUS_WMI_FNLOCK_BIOS_DISABLED BIT(0) BIT 18 drivers/platform/x86/dcdbas.h #define HC_ACTION_HOST_CONTROL_POWEROFF BIT(1) BIT 19 drivers/platform/x86/dcdbas.h #define HC_ACTION_HOST_CONTROL_POWERCYCLE BIT(2) BIT 506 drivers/platform/x86/dell-laptop.c if (ret == 0 && (hwswitch & BIT(hwswitch_bit)) && BIT 507 drivers/platform/x86/dell-laptop.c (status & BIT(0)) && !(status & BIT(16))) BIT 518 drivers/platform/x86/dell-laptop.c if (status & BIT(0)) { BIT 527 drivers/platform/x86/dell-laptop.c rfkill_set_sw_state(rfkill, !!(status & BIT(radio + 16))); BIT 534 drivers/platform/x86/dell-laptop.c if (hwswitch & (BIT(radio - 1))) BIT 535 drivers/platform/x86/dell-laptop.c rfkill_set_hw_state(rfkill, !(status & BIT(16))); BIT 550 drivers/platform/x86/dell-laptop.c if (ret != 0 || !(status & BIT(0))) { BIT 594 drivers/platform/x86/dell-laptop.c status & BIT(0)); BIT 596 drivers/platform/x86/dell-laptop.c (status & BIT(1)) >> 1); BIT 598 drivers/platform/x86/dell-laptop.c (status & BIT(2)) >> 2); BIT 600 drivers/platform/x86/dell-laptop.c (status & BIT(3)) >> 3); BIT 602 drivers/platform/x86/dell-laptop.c (status & BIT(4)) >> 4); BIT 604 drivers/platform/x86/dell-laptop.c (status & BIT(5)) >> 5); BIT 606 drivers/platform/x86/dell-laptop.c (status & BIT(6)) >> 6); BIT 608 drivers/platform/x86/dell-laptop.c (status & BIT(7)) >> 7); BIT 610 drivers/platform/x86/dell-laptop.c (status & BIT(8)) >> 8); BIT 612 drivers/platform/x86/dell-laptop.c (status & BIT(9)) >> 9); BIT 614 drivers/platform/x86/dell-laptop.c (status & BIT(10)) >> 10); BIT 616 drivers/platform/x86/dell-laptop.c (status & BIT(11)) >> 11); BIT 618 drivers/platform/x86/dell-laptop.c (status & BIT(12)) >> 12); BIT 621 drivers/platform/x86/dell-laptop.c (status & BIT(16)) >> 16); BIT 623 drivers/platform/x86/dell-laptop.c (status & BIT(17)) >> 17); BIT 625 drivers/platform/x86/dell-laptop.c (status & BIT(18)) >> 18); BIT 627 drivers/platform/x86/dell-laptop.c (status & BIT(19)) >> 19); BIT 629 drivers/platform/x86/dell-laptop.c (status & BIT(20)) >> 20); BIT 631 drivers/platform/x86/dell-laptop.c (status & BIT(21)) >> 21); BIT 636 drivers/platform/x86/dell-laptop.c hwswitch_state & BIT(0)); BIT 638 drivers/platform/x86/dell-laptop.c (hwswitch_state & BIT(1)) >> 1); BIT 640 drivers/platform/x86/dell-laptop.c (hwswitch_state & BIT(2)) >> 2); BIT 642 drivers/platform/x86/dell-laptop.c (hwswitch_state & BIT(3)) >> 3); BIT 644 drivers/platform/x86/dell-laptop.c (hwswitch_state & BIT(4)) >> 4); BIT 646 drivers/platform/x86/dell-laptop.c (hwswitch_state & BIT(7)) >> 7); BIT 648 drivers/platform/x86/dell-laptop.c (hwswitch_state & BIT(8)) >> 8); BIT 650 drivers/platform/x86/dell-laptop.c (hwswitch_state & BIT(15)) >> 15); BIT 673 drivers/platform/x86/dell-laptop.c if (ret == 0 && (status & BIT(0))) BIT 757 drivers/platform/x86/dell-laptop.c if (!(status & BIT(0)) && !force_rfkill) BIT 1227 drivers/platform/x86/dell-laptop.c if (units & BIT(0)) BIT 1229 drivers/platform/x86/dell-laptop.c if (units & BIT(1)) BIT 1231 drivers/platform/x86/dell-laptop.c if (units & BIT(2)) BIT 1233 drivers/platform/x86/dell-laptop.c if (units & BIT(3)) BIT 1326 drivers/platform/x86/dell-laptop.c input1 = BIT(state->mode_bit) & 0xFFFF; BIT 1456 drivers/platform/x86/dell-laptop.c kbd_info.modes &= ~BIT(KBD_MODE_BIT_ON); BIT 1466 drivers/platform/x86/dell-laptop.c ffs(kbd_info.modes & ~BIT(KBD_MODE_BIT_OFF)); BIT 1471 drivers/platform/x86/dell-laptop.c if (kbd_info.modes & (BIT(KBD_MODE_BIT_ALS) | BIT 1472 drivers/platform/x86/dell-laptop.c BIT(KBD_MODE_BIT_TRIGGER_ALS))) BIT 1476 drivers/platform/x86/dell-laptop.c BIT(KBD_MODE_BIT_TRIGGER_ALS) | BIT(KBD_MODE_BIT_TRIGGER) | BIT 1477 drivers/platform/x86/dell-laptop.c BIT(KBD_MODE_BIT_TRIGGER_25) | BIT(KBD_MODE_BIT_TRIGGER_50) | BIT 1478 drivers/platform/x86/dell-laptop.c BIT(KBD_MODE_BIT_TRIGGER_75) | BIT(KBD_MODE_BIT_TRIGGER_100) BIT 1484 drivers/platform/x86/dell-laptop.c if (kbd_is_level_mode_bit(i) && (BIT(i) & kbd_info.modes)) BIT 1494 drivers/platform/x86/dell-laptop.c if (BIT(i) & kbd_info.modes) { BIT 1512 drivers/platform/x86/dell-laptop.c kbd_token_bits |= BIT(i); BIT 1728 drivers/platform/x86/dell-laptop.c if (!(kbd_info.triggers & BIT(i))) BIT 1735 drivers/platform/x86/dell-laptop.c triggers_enabled && (state.triggers & BIT(i))) { BIT 1740 drivers/platform/x86/dell-laptop.c (!triggers_enabled || !(state.triggers & BIT(i)))) { BIT 1756 drivers/platform/x86/dell-laptop.c new_state.triggers |= BIT(trigger_bit); BIT 1758 drivers/platform/x86/dell-laptop.c new_state.triggers &= ~BIT(trigger_bit); BIT 1765 drivers/platform/x86/dell-laptop.c new_state.triggers &= ~BIT(2); BIT 1778 drivers/platform/x86/dell-laptop.c if (!(kbd_info.modes & BIT(new_state.mode_bit))) { BIT 1811 drivers/platform/x86/dell-laptop.c if (!(kbd_info.triggers & BIT(i))) BIT 1816 drivers/platform/x86/dell-laptop.c (state.triggers & BIT(i))) BIT 1876 drivers/platform/x86/dell-laptop.c if (!(kbd_info.modes & BIT(new_state.mode_bit))) { BIT 176 drivers/platform/x86/dell-rbtn.c rbtn_data->input_dev->evbit[0] = BIT(EV_KEY); BIT 69 drivers/platform/x86/fujitsu-laptop.c #define FUNC_FLAGS BIT(12) BIT 70 drivers/platform/x86/fujitsu-laptop.c #define FUNC_LEDS (BIT(12) | BIT(0)) BIT 71 drivers/platform/x86/fujitsu-laptop.c #define FUNC_BUTTONS (BIT(12) | BIT(1)) BIT 72 drivers/platform/x86/fujitsu-laptop.c #define FUNC_BACKLIGHT (BIT(12) | BIT(2)) BIT 78 drivers/platform/x86/fujitsu-laptop.c #define FLAG_RFKILL BIT(5) BIT 79 drivers/platform/x86/fujitsu-laptop.c #define FLAG_LID BIT(8) BIT 80 drivers/platform/x86/fujitsu-laptop.c #define FLAG_DOCK BIT(9) BIT 81 drivers/platform/x86/fujitsu-laptop.c #define FLAG_TOUCHPAD_TOGGLE BIT(26) BIT 82 drivers/platform/x86/fujitsu-laptop.c #define FLAG_MICMUTE BIT(29) BIT 86 drivers/platform/x86/fujitsu-laptop.c #define FUNC_LED_OFF BIT(0) BIT 87 drivers/platform/x86/fujitsu-laptop.c #define FUNC_LED_ON (BIT(0) | BIT(16) | BIT(17)) BIT 88 drivers/platform/x86/fujitsu-laptop.c #define LOGOLAMP_POWERON BIT(13) BIT 89 drivers/platform/x86/fujitsu-laptop.c #define LOGOLAMP_ALWAYS BIT(14) BIT 90 drivers/platform/x86/fujitsu-laptop.c #define KEYBOARD_LAMPS BIT(8) BIT 91 drivers/platform/x86/fujitsu-laptop.c #define RADIO_LED_ON BIT(5) BIT 92 drivers/platform/x86/fujitsu-laptop.c #define ECO_LED BIT(16) BIT 93 drivers/platform/x86/fujitsu-laptop.c #define ECO_LED_ON BIT(19) BIT 96 drivers/platform/x86/fujitsu-laptop.c #define BACKLIGHT_PARAM_POWER BIT(2) BIT 97 drivers/platform/x86/fujitsu-laptop.c #define BACKLIGHT_OFF (BIT(0) | BIT(1)) BIT 735 drivers/platform/x86/fujitsu-laptop.c if (priv->flags_supported & BIT(17)) { BIT 754 drivers/platform/x86/fujitsu-laptop.c if ((call_fext_func(device, FUNC_LEDS, 0x0, 0x0, 0x0) & BIT(14)) && BIT 935 drivers/platform/x86/fujitsu-laptop.c sparse_keymap_report_event(priv->input, BIT(i), 1, true); BIT 292 drivers/platform/x86/fujitsu-tablet.c pressed = keymask & changed & BIT(i); BIT 40 drivers/platform/x86/hp-wireless.c hpwl_input_dev->evbit[0] = BIT(EV_KEY); BIT 324 drivers/platform/x86/hp-wmi.c int query = BIT(r + 8) | ((!blocked) << r); BIT 21 drivers/platform/x86/intel_bxtwc_tmu.c #define BXTWC_MIRQLVL1_MTMU BIT(1) BIT 22 drivers/platform/x86/intel_bxtwc_tmu.c #define BXTWC_TMU_WK_ALRM BIT(1) BIT 23 drivers/platform/x86/intel_bxtwc_tmu.c #define BXTWC_TMU_SYS_ALRM BIT(2) BIT 18 drivers/platform/x86/intel_chtdc_ti_pwrbtn.c #define SIRQ_PWRBTN_REL BIT(0) BIT 49 drivers/platform/x86/intel_int0002_vgpio.c #define GPE0A_PME_B0_STS_BIT BIT(13) BIT 50 drivers/platform/x86/intel_int0002_vgpio.c #define GPE0A_PME_B0_EN_BIT BIT(13) BIT 20 drivers/platform/x86/intel_mrfld_pwrbtn.c #define BCOVE_PBSTATUS_PBLVL BIT(4) /* 1 - release, 0 - press */ BIT 164 drivers/platform/x86/intel_pmc_core.c {"PMC", BIT(0)}, BIT 165 drivers/platform/x86/intel_pmc_core.c {"OPI-DMI", BIT(1)}, BIT 166 drivers/platform/x86/intel_pmc_core.c {"SPI/eSPI", BIT(2)}, BIT 167 drivers/platform/x86/intel_pmc_core.c {"XHCI", BIT(3)}, BIT 168 drivers/platform/x86/intel_pmc_core.c {"SPA", BIT(4)}, BIT 169 drivers/platform/x86/intel_pmc_core.c {"SPB", BIT(5)}, BIT 170 drivers/platform/x86/intel_pmc_core.c {"SPC", BIT(6)}, BIT 171 drivers/platform/x86/intel_pmc_core.c {"GBE", BIT(7)}, BIT 173 drivers/platform/x86/intel_pmc_core.c {"SATA", BIT(0)}, BIT 174 drivers/platform/x86/intel_pmc_core.c {"HDA_PGD0", BIT(1)}, BIT 175 drivers/platform/x86/intel_pmc_core.c {"HDA_PGD1", BIT(2)}, BIT 176 drivers/platform/x86/intel_pmc_core.c {"HDA_PGD2", BIT(3)}, BIT 177 drivers/platform/x86/intel_pmc_core.c {"HDA_PGD3", BIT(4)}, BIT 178 drivers/platform/x86/intel_pmc_core.c {"SPD", BIT(5)}, BIT 179 drivers/platform/x86/intel_pmc_core.c {"LPSS", BIT(6)}, BIT 180 drivers/platform/x86/intel_pmc_core.c {"LPC", BIT(7)}, BIT 182 drivers/platform/x86/intel_pmc_core.c {"SMB", BIT(0)}, BIT 183 drivers/platform/x86/intel_pmc_core.c {"ISH", BIT(1)}, BIT 184 drivers/platform/x86/intel_pmc_core.c {"P2SB", BIT(2)}, BIT 185 drivers/platform/x86/intel_pmc_core.c {"NPK_VNN", BIT(3)}, BIT 186 drivers/platform/x86/intel_pmc_core.c {"SDX", BIT(4)}, BIT 187 drivers/platform/x86/intel_pmc_core.c {"SPE", BIT(5)}, BIT 188 drivers/platform/x86/intel_pmc_core.c {"Fuse", BIT(6)}, BIT 190 drivers/platform/x86/intel_pmc_core.c {"SBR8", BIT(7)}, BIT 192 drivers/platform/x86/intel_pmc_core.c {"CSME_FSC", BIT(0)}, BIT 193 drivers/platform/x86/intel_pmc_core.c {"USB3_OTG", BIT(1)}, BIT 194 drivers/platform/x86/intel_pmc_core.c {"EXI", BIT(2)}, BIT 195 drivers/platform/x86/intel_pmc_core.c {"CSE", BIT(3)}, BIT 196 drivers/platform/x86/intel_pmc_core.c {"CSME_KVM", BIT(4)}, BIT 197 drivers/platform/x86/intel_pmc_core.c {"CSME_PMT", BIT(5)}, BIT 198 drivers/platform/x86/intel_pmc_core.c {"CSME_CLINK", BIT(6)}, BIT 199 drivers/platform/x86/intel_pmc_core.c {"CSME_PTIO", BIT(7)}, BIT 201 drivers/platform/x86/intel_pmc_core.c {"CSME_USBR", BIT(0)}, BIT 202 drivers/platform/x86/intel_pmc_core.c {"CSME_SUSRAM", BIT(1)}, BIT 203 drivers/platform/x86/intel_pmc_core.c {"CSME_SMT1", BIT(2)}, BIT 204 drivers/platform/x86/intel_pmc_core.c {"CSME_SMT4", BIT(3)}, BIT 205 drivers/platform/x86/intel_pmc_core.c {"CSME_SMS2", BIT(4)}, BIT 206 drivers/platform/x86/intel_pmc_core.c {"CSME_SMS1", BIT(5)}, BIT 207 drivers/platform/x86/intel_pmc_core.c {"CSME_RTC", BIT(6)}, BIT 208 drivers/platform/x86/intel_pmc_core.c {"CSME_PSF", BIT(7)}, BIT 210 drivers/platform/x86/intel_pmc_core.c {"SBR0", BIT(0)}, BIT 211 drivers/platform/x86/intel_pmc_core.c {"SBR1", BIT(1)}, BIT 212 drivers/platform/x86/intel_pmc_core.c {"SBR2", BIT(2)}, BIT 213 drivers/platform/x86/intel_pmc_core.c {"SBR3", BIT(3)}, BIT 214 drivers/platform/x86/intel_pmc_core.c {"SBR4", BIT(4)}, BIT 215 drivers/platform/x86/intel_pmc_core.c {"SBR5", BIT(5)}, BIT 216 drivers/platform/x86/intel_pmc_core.c {"CSME_PECI", BIT(6)}, BIT 217 drivers/platform/x86/intel_pmc_core.c {"PSF1", BIT(7)}, BIT 219 drivers/platform/x86/intel_pmc_core.c {"PSF2", BIT(0)}, BIT 220 drivers/platform/x86/intel_pmc_core.c {"PSF3", BIT(1)}, BIT 221 drivers/platform/x86/intel_pmc_core.c {"PSF4", BIT(2)}, BIT 222 drivers/platform/x86/intel_pmc_core.c {"CNVI", BIT(3)}, BIT 223 drivers/platform/x86/intel_pmc_core.c {"UFS0", BIT(4)}, BIT 224 drivers/platform/x86/intel_pmc_core.c {"EMMC", BIT(5)}, BIT 225 drivers/platform/x86/intel_pmc_core.c {"SPF", BIT(6)}, BIT 226 drivers/platform/x86/intel_pmc_core.c {"SBR6", BIT(7)}, BIT 228 drivers/platform/x86/intel_pmc_core.c {"SBR7", BIT(0)}, BIT 229 drivers/platform/x86/intel_pmc_core.c {"NPK_AON", BIT(1)}, BIT 230 drivers/platform/x86/intel_pmc_core.c {"HDA_PGD4", BIT(2)}, BIT 231 drivers/platform/x86/intel_pmc_core.c {"HDA_PGD5", BIT(3)}, BIT 232 drivers/platform/x86/intel_pmc_core.c {"HDA_PGD6", BIT(4)}, BIT 234 drivers/platform/x86/intel_pmc_core.c {"PSF6", BIT(5)}, BIT 235 drivers/platform/x86/intel_pmc_core.c {"PSF7", BIT(6)}, BIT 236 drivers/platform/x86/intel_pmc_core.c {"PSF8", BIT(7)}, BIT 239 drivers/platform/x86/intel_pmc_core.c {"RES_65", BIT(0)}, BIT 240 drivers/platform/x86/intel_pmc_core.c {"RES_66", BIT(1)}, BIT 241 drivers/platform/x86/intel_pmc_core.c {"RES_67", BIT(2)}, BIT 242 drivers/platform/x86/intel_pmc_core.c {"TAM", BIT(3)}, BIT 243 drivers/platform/x86/intel_pmc_core.c {"GBETSN", BIT(4)}, BIT 244 drivers/platform/x86/intel_pmc_core.c {"TBTLSX", BIT(5)}, BIT 245 drivers/platform/x86/intel_pmc_core.c {"RES_71", BIT(6)}, BIT 246 drivers/platform/x86/intel_pmc_core.c {"RES_72", BIT(7)}, BIT 251 drivers/platform/x86/intel_pmc_core.c {"AUDIO_D3", BIT(0)}, BIT 252 drivers/platform/x86/intel_pmc_core.c {"OTG_D3", BIT(1)}, BIT 253 drivers/platform/x86/intel_pmc_core.c {"XHCI_D3", BIT(2)}, BIT 254 drivers/platform/x86/intel_pmc_core.c {"LPIO_D3", BIT(3)}, BIT 255 drivers/platform/x86/intel_pmc_core.c {"SDX_D3", BIT(4)}, BIT 256 drivers/platform/x86/intel_pmc_core.c {"SATA_D3", BIT(5)}, BIT 257 drivers/platform/x86/intel_pmc_core.c {"UFS0_D3", BIT(6)}, BIT 258 drivers/platform/x86/intel_pmc_core.c {"UFS1_D3", BIT(7)}, BIT 259 drivers/platform/x86/intel_pmc_core.c {"EMMC_D3", BIT(8)}, BIT 264 drivers/platform/x86/intel_pmc_core.c {"SDIO_PLL_OFF", BIT(0)}, BIT 265 drivers/platform/x86/intel_pmc_core.c {"USB2_PLL_OFF", BIT(1)}, BIT 266 drivers/platform/x86/intel_pmc_core.c {"AUDIO_PLL_OFF", BIT(2)}, BIT 267 drivers/platform/x86/intel_pmc_core.c {"OC_PLL_OFF", BIT(3)}, BIT 268 drivers/platform/x86/intel_pmc_core.c {"MAIN_PLL_OFF", BIT(4)}, BIT 269 drivers/platform/x86/intel_pmc_core.c {"XOSC_OFF", BIT(5)}, BIT 270 drivers/platform/x86/intel_pmc_core.c {"LPC_CLKS_GATED", BIT(6)}, BIT 271 drivers/platform/x86/intel_pmc_core.c {"PCIE_CLKREQS_IDLE", BIT(7)}, BIT 272 drivers/platform/x86/intel_pmc_core.c {"AUDIO_ROSC_OFF", BIT(8)}, BIT 273 drivers/platform/x86/intel_pmc_core.c {"HPET_XOSC_CLK_REQ", BIT(9)}, BIT 274 drivers/platform/x86/intel_pmc_core.c {"PMC_ROSC_SLOW_CLK", BIT(10)}, BIT 275 drivers/platform/x86/intel_pmc_core.c {"AON2_ROSC_GATED", BIT(11)}, BIT 276 drivers/platform/x86/intel_pmc_core.c {"CLKACKS_DEASSERTED", BIT(12)}, BIT 281 drivers/platform/x86/intel_pmc_core.c {"MPHY_CORE_GATED", BIT(0)}, BIT 282 drivers/platform/x86/intel_pmc_core.c {"CSME_GATED", BIT(1)}, BIT 283 drivers/platform/x86/intel_pmc_core.c {"USB2_SUS_GATED", BIT(2)}, BIT 284 drivers/platform/x86/intel_pmc_core.c {"DYN_FLEX_IO_IDLE", BIT(3)}, BIT 285 drivers/platform/x86/intel_pmc_core.c {"GBE_NO_LINK", BIT(4)}, BIT 286 drivers/platform/x86/intel_pmc_core.c {"THERM_SEN_DISABLED", BIT(5)}, BIT 287 drivers/platform/x86/intel_pmc_core.c {"PCIE_LOW_POWER", BIT(6)}, BIT 288 drivers/platform/x86/intel_pmc_core.c {"ISH_VNNAON_REQ_ACT", BIT(7)}, BIT 289 drivers/platform/x86/intel_pmc_core.c {"ISH_VNN_REQ_ACT", BIT(8)}, BIT 290 drivers/platform/x86/intel_pmc_core.c {"CNV_VNNAON_REQ_ACT", BIT(9)}, BIT 291 drivers/platform/x86/intel_pmc_core.c {"CNV_VNN_REQ_ACT", BIT(10)}, BIT 292 drivers/platform/x86/intel_pmc_core.c {"NPK_VNNON_REQ_ACT", BIT(11)}, BIT 293 drivers/platform/x86/intel_pmc_core.c {"PMSYNC_STATE_IDLE", BIT(12)}, BIT 294 drivers/platform/x86/intel_pmc_core.c {"ALST_GT_THRES", BIT(13)}, BIT 295 drivers/platform/x86/intel_pmc_core.c {"PMC_ARC_PG_READY", BIT(14)}, BIT 409 drivers/platform/x86/intel_pmc_core.c return value & BIT(pmcdev->map->pm_read_disable_bit); BIT 451 drivers/platform/x86/intel_pmc_core.c return value & BIT(SPT_PMC_MSG_FULL_STS_BIT); BIT 72 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_PMC BIT(0) BIT 73 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_OPI BIT(1) BIT 74 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_SPI BIT(2) BIT 75 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_XHCI BIT(3) BIT 76 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_SPA BIT(4) BIT 77 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_SPB BIT(5) BIT 78 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_SPC BIT(6) BIT 79 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_GBE BIT(7) BIT 81 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_SATA BIT(0) BIT 82 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_HDA_PGD0 BIT(1) BIT 83 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_HDA_PGD1 BIT(2) BIT 84 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_HDA_PGD2 BIT(3) BIT 85 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_HDA_PGD3 BIT(4) BIT 86 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_RSVD_0B BIT(5) BIT 87 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_LPSS BIT(6) BIT 88 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_LPC BIT(7) BIT 90 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_SMB BIT(0) BIT 91 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_ISH BIT(1) BIT 92 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_P2SB BIT(2) BIT 93 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_DFX BIT(3) BIT 94 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_SCC BIT(4) BIT 95 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_RSVD_0C BIT(5) BIT 96 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_FUSE BIT(6) BIT 97 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CAMREA BIT(7) BIT 99 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_RSVD_0D BIT(0) BIT 100 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_USB3_OTG BIT(1) BIT 101 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_EXI BIT(2) BIT 102 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSE BIT(3) BIT 103 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_KVM BIT(4) BIT 104 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_PMT BIT(5) BIT 105 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_CLINK BIT(6) BIT 106 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_PTIO BIT(7) BIT 108 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_USBR BIT(0) BIT 109 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_SUSRAM BIT(1) BIT 110 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_SMT BIT(2) BIT 111 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_RSVD_1A BIT(3) BIT 112 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_SMS2 BIT(4) BIT 113 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_SMS1 BIT(5) BIT 114 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_RTC BIT(6) BIT 115 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_CSME_PSF BIT(7) BIT 117 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE0 BIT(0) BIT 118 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE1 BIT(1) BIT 119 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE2 BIT(2) BIT 120 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE3 BIT(3) BIT 121 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE4 BIT(4) BIT 122 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE5 BIT(5) BIT 123 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE6 BIT(6) BIT 124 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE7 BIT(7) BIT 126 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE8 BIT(0) BIT 127 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE9 BIT(1) BIT 128 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE10 BIT(2) BIT 129 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE11 BIT(3) BIT 130 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE12 BIT(4) BIT 131 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE13 BIT(5) BIT 132 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE14 BIT(6) BIT 133 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_LANE15 BIT(7) BIT 135 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0) BIT 136 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1) BIT 137 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2) BIT 138 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3) BIT 140 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_VRIC1_SLPS0LVEN BIT(13) BIT 141 drivers/platform/x86/intel_pmc_core.h #define SPT_PMC_VRIC1_XTALSDQDIS BIT(22) BIT 151 drivers/platform/x86/intel_pmc_core.h #define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31) BIT 182 drivers/platform/x86/intel_pmc_core.h #define LTR_REQ_SNOOP BIT(15) BIT 183 drivers/platform/x86/intel_pmc_core.h #define LTR_REQ_NONSNOOP BIT(31) BIT 44 drivers/platform/x86/intel_pmc_ipc.c #define IPC_CMD_MSI BIT(8) BIT 48 drivers/platform/x86/intel_pmc_ipc.c #define IPC_STATUS_IRQ BIT(2) BIT 49 drivers/platform/x86/intel_pmc_ipc.c #define IPC_STATUS_ERR BIT(1) BIT 50 drivers/platform/x86/intel_pmc_ipc.c #define IPC_STATUS_BUSY BIT(0) BIT 27 drivers/platform/x86/intel_punit_ipc.c #define CMD_RUN BIT(31) BIT 99 drivers/platform/x86/intel_scu_ipc.c #define IPC_STATUS_IRQ BIT(2) BIT 168 drivers/platform/x86/intel_scu_ipc.c while ((status & BIT(0)) && --loop_count) { BIT 173 drivers/platform/x86/intel_scu_ipc.c if (status & BIT(0)) { BIT 178 drivers/platform/x86/intel_scu_ipc.c if (status & BIT(1)) BIT 195 drivers/platform/x86/intel_scu_ipc.c if (status & BIT(1)) BIT 29 drivers/platform/x86/intel_telemetry_pltdrv.c #define TELEM_SAMPLE_PERIOD_INVALID(x) ((x) & (BIT(7))) BIT 62 drivers/platform/x86/intel_telemetry_pltdrv.c #define TELEM_DISABLE(x) ((x) &= ~(BIT(31))) BIT 63 drivers/platform/x86/intel_telemetry_pltdrv.c #define TELEM_CLEAR_EVENTS(x) ((x) |= (BIT(30))) BIT 64 drivers/platform/x86/intel_telemetry_pltdrv.c #define TELEM_ENABLE_SRAM_EVT_TRACE(x) ((x) &= ~(BIT(30) | BIT(24))) BIT 65 drivers/platform/x86/intel_telemetry_pltdrv.c #define TELEM_ENABLE_PERIODIC(x) ((x) |= (BIT(23) | BIT(31) | BIT(7))) BIT 67 drivers/platform/x86/intel_telemetry_pltdrv.c #define TELEM_CLEAR_VERBOSITY_BITS(x) ((x) &= ~(BIT(27) | BIT(28))) BIT 110 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) BIT 112 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) BIT 148 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1)) BIT 153 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) BIT 154 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7)) BIT 284 drivers/platform/x86/mlx-platform.c .mask = BIT(0), BIT 291 drivers/platform/x86/mlx-platform.c .mask = BIT(1), BIT 301 drivers/platform/x86/mlx-platform.c .mask = BIT(0), BIT 308 drivers/platform/x86/mlx-platform.c .mask = BIT(1), BIT 318 drivers/platform/x86/mlx-platform.c .mask = BIT(0), BIT 325 drivers/platform/x86/mlx-platform.c .mask = BIT(1), BIT 332 drivers/platform/x86/mlx-platform.c .mask = BIT(2), BIT 339 drivers/platform/x86/mlx-platform.c .mask = BIT(3), BIT 407 drivers/platform/x86/mlx-platform.c .mask = BIT(0), BIT 413 drivers/platform/x86/mlx-platform.c .mask = BIT(1), BIT 455 drivers/platform/x86/mlx-platform.c .mask = BIT(0), BIT 462 drivers/platform/x86/mlx-platform.c .mask = BIT(1), BIT 472 drivers/platform/x86/mlx-platform.c .mask = BIT(0), BIT 479 drivers/platform/x86/mlx-platform.c .mask = BIT(1), BIT 489 drivers/platform/x86/mlx-platform.c .mask = BIT(0), BIT 495 drivers/platform/x86/mlx-platform.c .mask = BIT(1), BIT 501 drivers/platform/x86/mlx-platform.c .mask = BIT(2), BIT 507 drivers/platform/x86/mlx-platform.c .mask = BIT(3), BIT 566 drivers/platform/x86/mlx-platform.c .mask = BIT(0), BIT 572 drivers/platform/x86/mlx-platform.c .mask = BIT(1), BIT 613 drivers/platform/x86/mlx-platform.c .mask = BIT(0), BIT 620 drivers/platform/x86/mlx-platform.c .mask = BIT(1), BIT 630 drivers/platform/x86/mlx-platform.c .mask = BIT(0), BIT 632 drivers/platform/x86/mlx-platform.c .bit = BIT(0), BIT 638 drivers/platform/x86/mlx-platform.c .mask = BIT(1), BIT 640 drivers/platform/x86/mlx-platform.c .bit = BIT(1), BIT 646 drivers/platform/x86/mlx-platform.c .mask = BIT(2), BIT 648 drivers/platform/x86/mlx-platform.c .bit = BIT(2), BIT 654 drivers/platform/x86/mlx-platform.c .mask = BIT(3), BIT 656 drivers/platform/x86/mlx-platform.c .bit = BIT(3), BIT 662 drivers/platform/x86/mlx-platform.c .mask = BIT(4), BIT 664 drivers/platform/x86/mlx-platform.c .bit = BIT(4), BIT 670 drivers/platform/x86/mlx-platform.c .mask = BIT(5), BIT 672 drivers/platform/x86/mlx-platform.c .bit = BIT(5), BIT 876 drivers/platform/x86/mlx-platform.c .bit = BIT(0), BIT 883 drivers/platform/x86/mlx-platform.c .bit = BIT(0), BIT 890 drivers/platform/x86/mlx-platform.c .bit = BIT(1), BIT 897 drivers/platform/x86/mlx-platform.c .bit = BIT(1), BIT 904 drivers/platform/x86/mlx-platform.c .bit = BIT(2), BIT 911 drivers/platform/x86/mlx-platform.c .bit = BIT(2), BIT 918 drivers/platform/x86/mlx-platform.c .bit = BIT(3), BIT 925 drivers/platform/x86/mlx-platform.c .bit = BIT(3), BIT 932 drivers/platform/x86/mlx-platform.c .bit = BIT(4), BIT 939 drivers/platform/x86/mlx-platform.c .bit = BIT(4), BIT 946 drivers/platform/x86/mlx-platform.c .bit = BIT(5), BIT 953 drivers/platform/x86/mlx-platform.c .bit = BIT(5), BIT 984 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), BIT 990 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), BIT 996 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), BIT 1002 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), BIT 1008 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(4), BIT 1014 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(5), BIT 1020 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), BIT 1026 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(7), BIT 1032 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), BIT 1038 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), BIT 1044 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), BIT 1050 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), BIT 1056 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), BIT 1090 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), BIT 1096 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), BIT 1102 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), BIT 1108 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), BIT 1114 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(4), BIT 1120 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(5), BIT 1126 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), BIT 1132 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), BIT 1138 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), BIT 1144 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), BIT 1150 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), BIT 1156 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), BIT 1202 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), BIT 1208 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), BIT 1214 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), BIT 1220 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(4), BIT 1226 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(5), BIT 1232 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), BIT 1238 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(7), BIT 1244 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), BIT 1250 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), BIT 1256 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), BIT 1262 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), BIT 1268 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), BIT 1274 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(5), BIT 1280 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), BIT 1286 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), BIT 1292 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), BIT 1298 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), BIT 1304 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(4), BIT 1338 drivers/platform/x86/mlx-platform.c .bit = BIT(0), BIT 1345 drivers/platform/x86/mlx-platform.c .bit = BIT(1), BIT 1352 drivers/platform/x86/mlx-platform.c .bit = BIT(2), BIT 1359 drivers/platform/x86/mlx-platform.c .bit = BIT(3), BIT 1366 drivers/platform/x86/mlx-platform.c .bit = BIT(4), BIT 1373 drivers/platform/x86/mlx-platform.c .bit = BIT(5), BIT 1380 drivers/platform/x86/mlx-platform.c .bit = BIT(6), BIT 1387 drivers/platform/x86/mlx-platform.c .bit = BIT(7), BIT 1394 drivers/platform/x86/mlx-platform.c .bit = BIT(0), BIT 1401 drivers/platform/x86/mlx-platform.c .bit = BIT(1), BIT 1408 drivers/platform/x86/mlx-platform.c .bit = BIT(2), BIT 1415 drivers/platform/x86/mlx-platform.c .bit = BIT(3), BIT 1453 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), BIT 1524 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), BIT 5376 drivers/platform/x86/thinkpad_acpi.c return status & BIT(9); BIT 9337 drivers/platform/x86/thinkpad_acpi.c METHOD_ERR = BIT(31), BIT 9461 drivers/platform/x86/thinkpad_acpi.c if (ret & BIT(9)) BIT 9464 drivers/platform/x86/thinkpad_acpi.c if (ret & BIT(8)) BIT 9480 drivers/platform/x86/thinkpad_acpi.c if (ret & BIT(8)) BIT 2485 drivers/platform/x86/toshiba_acpi.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ BIT 35 drivers/power/avs/rockchip-io-domain.c #define PX30_IO_VSEL_VCCIO6_SRC BIT(0) BIT 39 drivers/power/avs/rockchip-io-domain.c #define RK3288_SOC_CON2_FLASH0 BIT(7) BIT 43 drivers/power/avs/rockchip-io-domain.c #define RK3328_SOC_CON4_VCCIO2 BIT(7) BIT 47 drivers/power/avs/rockchip-io-domain.c #define RK3368_SOC_CON15_FLASH0 BIT(14) BIT 51 drivers/power/avs/rockchip-io-domain.c #define RK3399_PMUGRF_CON0_VSEL BIT(8) BIT 91 drivers/power/avs/rockchip-io-domain.c val |= (BIT(supply->idx) << 16); BIT 24 drivers/power/reset/at91-poweroff.c #define AT91_SHDW_SHDW BIT(0) /* Shut Down command */ BIT 32 drivers/power/reset/at91-poweroff.c #define AT91_SHDW_RTTWKEN BIT(16) /* Real Time Timer Wake-up Enable */ BIT 33 drivers/power/reset/at91-poweroff.c #define AT91_SHDW_RTCWKEN BIT(17) /* Real Time Clock Wake-up Enable */ BIT 36 drivers/power/reset/at91-poweroff.c #define AT91_SHDW_WAKEUP0 BIT(0) /* Wake-up 0 Status */ BIT 37 drivers/power/reset/at91-poweroff.c #define AT91_SHDW_RTTWK BIT(16) /* Real-time Timer Wake-up */ BIT 38 drivers/power/reset/at91-poweroff.c #define AT91_SHDW_RTCWK BIT(17) /* Real-time Clock Wake-up [SAM9RL] */ BIT 25 drivers/power/reset/at91-reset.c #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */ BIT 26 drivers/power/reset/at91-reset.c #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */ BIT 27 drivers/power/reset/at91-reset.c #define AT91_RSTC_EXTRST BIT(3) /* External Reset */ BIT 31 drivers/power/reset/at91-reset.c #define AT91_RSTC_URSTS BIT(0) /* User Reset Status */ BIT 33 drivers/power/reset/at91-reset.c #define AT91_RSTC_NRSTL BIT(16) /* NRST Pin Level */ BIT 34 drivers/power/reset/at91-reset.c #define AT91_RSTC_SRCMP BIT(17) /* Software Reset Command in Progress */ BIT 37 drivers/power/reset/at91-reset.c #define AT91_RSTC_URSTEN BIT(0) /* User Reset Enable */ BIT 38 drivers/power/reset/at91-reset.c #define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */ BIT 35 drivers/power/reset/at91-sama5d2_shdwc.c #define AT91_SHDW_SHDW BIT(0) /* Shut Down command */ BIT 87 drivers/power/reset/brcmstb-reboot.c .rst_src_en_mask = BIT(0), BIT 88 drivers/power/reset/brcmstb-reboot.c .sw_mstr_rst_mask = BIT(0), BIT 92 drivers/power/reset/brcmstb-reboot.c .rst_src_en_mask = BIT(3), BIT 93 drivers/power/reset/brcmstb-reboot.c .sw_mstr_rst_mask = BIT(31), BIT 23 drivers/power/reset/gemini-poweroff.c #define GEMINI_CTRL_SHUTDOWN BIT(0) BIT 24 drivers/power/reset/gemini-poweroff.c #define GEMINI_CTRL_ENABLE BIT(1) BIT 25 drivers/power/reset/gemini-poweroff.c #define GEMINI_CTRL_IRQ_CLR BIT(2) BIT 27 drivers/power/reset/gemini-poweroff.c #define GEMINI_STAT_CIR BIT(4) BIT 28 drivers/power/reset/gemini-poweroff.c #define GEMINI_STAT_RTC BIT(5) BIT 29 drivers/power/reset/gemini-poweroff.c #define GEMINI_STAT_POWERBUTTON BIT(6) BIT 24 drivers/power/reset/keystone-reset.c #define RSCTRL_RESET_MASK BIT(16) BIT 25 drivers/power/reset/ocelot-reset.c #define CORE_RST_PROTECT BIT(2) BIT 27 drivers/power/reset/ocelot-reset.c #define SOFT_CHIP_RST BIT(0) BIT 15 drivers/power/reset/sc27xx-poweroff.c #define SC27XX_PWR_OFF_EN BIT(0) BIT 34 drivers/power/reset/st-poweroff.c .mask_rst = BIT(0), BIT 36 drivers/power/reset/st-poweroff.c .mask_rst_msk = BIT(0) BIT 49 drivers/power/supply/act8945a_charger.c #define APCH_STATUS_CHGDAT BIT(0) BIT 50 drivers/power/supply/act8945a_charger.c #define APCH_STATUS_INDAT BIT(1) BIT 51 drivers/power/supply/act8945a_charger.c #define APCH_STATUS_TEMPDAT BIT(2) BIT 52 drivers/power/supply/act8945a_charger.c #define APCH_STATUS_TIMRDAT BIT(3) BIT 53 drivers/power/supply/act8945a_charger.c #define APCH_STATUS_CHGSTAT BIT(4) BIT 54 drivers/power/supply/act8945a_charger.c #define APCH_STATUS_INSTAT BIT(5) BIT 55 drivers/power/supply/act8945a_charger.c #define APCH_STATUS_TEMPSTAT BIT(6) BIT 56 drivers/power/supply/act8945a_charger.c #define APCH_STATUS_TIMRSTAT BIT(7) BIT 58 drivers/power/supply/act8945a_charger.c #define APCH_CTRL_CHGEOCOUT BIT(0) BIT 59 drivers/power/supply/act8945a_charger.c #define APCH_CTRL_INDIS BIT(1) BIT 60 drivers/power/supply/act8945a_charger.c #define APCH_CTRL_TEMPOUT BIT(2) BIT 61 drivers/power/supply/act8945a_charger.c #define APCH_CTRL_TIMRPRE BIT(3) BIT 62 drivers/power/supply/act8945a_charger.c #define APCH_CTRL_CHGEOCIN BIT(4) BIT 63 drivers/power/supply/act8945a_charger.c #define APCH_CTRL_INCON BIT(5) BIT 64 drivers/power/supply/act8945a_charger.c #define APCH_CTRL_TEMPIN BIT(6) BIT 65 drivers/power/supply/act8945a_charger.c #define APCH_CTRL_TIMRTOT BIT(7) BIT 55 drivers/power/supply/adp5061.c #define ADP5061_VOLTAGE_TH_DIS_RCH_MSK BIT(7) BIT 23 drivers/power/supply/axp20x_ac_power.c #define AXP20X_PWR_STATUS_ACIN_PRESENT BIT(7) BIT 24 drivers/power/supply/axp20x_ac_power.c #define AXP20X_PWR_STATUS_ACIN_AVAIL BIT(6) BIT 26 drivers/power/supply/axp20x_ac_power.c #define AXP813_ACIN_PATH_SEL BIT(7) BIT 35 drivers/power/supply/axp20x_battery.c #define AXP20X_PWR_STATUS_BAT_CHARGING BIT(2) BIT 37 drivers/power/supply/axp20x_battery.c #define AXP20X_PWR_OP_BATT_PRESENT BIT(5) BIT 38 drivers/power/supply/axp20x_battery.c #define AXP20X_PWR_OP_BATT_ACTIVATED BIT(3) BIT 41 drivers/power/supply/axp20x_battery.c #define AXP22X_FG_VALID BIT(7) BIT 27 drivers/power/supply/axp20x_usb_power.c #define AXP20X_PWR_STATUS_VBUS_PRESENT BIT(5) BIT 28 drivers/power/supply/axp20x_usb_power.c #define AXP20X_PWR_STATUS_VBUS_USED BIT(4) BIT 30 drivers/power/supply/axp20x_usb_power.c #define AXP20X_USB_STATUS_VBUS_VALID BIT(2) BIT 46 drivers/power/supply/axp20x_usb_power.c #define AXP20X_ADC_EN1_VBUS_CURR BIT(2) BIT 47 drivers/power/supply/axp20x_usb_power.c #define AXP20X_ADC_EN1_VBUS_VOLT BIT(3) BIT 49 drivers/power/supply/axp20x_usb_power.c #define AXP20X_VBUS_MON_VBUS_VALID BIT(3) BIT 26 drivers/power/supply/axp288_charger.c #define PS_STAT_VBUS_TRIGGER BIT(0) BIT 27 drivers/power/supply/axp288_charger.c #define PS_STAT_BAT_CHRG_DIR BIT(2) BIT 28 drivers/power/supply/axp288_charger.c #define PS_STAT_VBAT_ABOVE_VHOLD BIT(3) BIT 29 drivers/power/supply/axp288_charger.c #define PS_STAT_VBUS_VALID BIT(4) BIT 30 drivers/power/supply/axp288_charger.c #define PS_STAT_VBUS_PRESENT BIT(5) BIT 32 drivers/power/supply/axp288_charger.c #define CHRG_STAT_BAT_SAFE_MODE BIT(3) BIT 33 drivers/power/supply/axp288_charger.c #define CHRG_STAT_BAT_VALID BIT(4) BIT 34 drivers/power/supply/axp288_charger.c #define CHRG_STAT_BAT_PRESENT BIT(5) BIT 35 drivers/power/supply/axp288_charger.c #define CHRG_STAT_CHARGING BIT(6) BIT 36 drivers/power/supply/axp288_charger.c #define CHRG_STAT_PMIC_OTP BIT(7) BIT 49 drivers/power/supply/axp288_charger.c #define VBUS_ISPOUT_VBUS_PATH_DIS BIT(7) BIT 55 drivers/power/supply/axp288_charger.c #define CHRG_CCCV_ITERM_20P BIT(4) /* 20% of CC */ BIT 62 drivers/power/supply/axp288_charger.c #define CHRG_CCCV_CHG_EN BIT(7) BIT 68 drivers/power/supply/axp288_charger.c #define CNTL2_CHGLED_TYPEB BIT(4) BIT 69 drivers/power/supply/axp288_charger.c #define CNTL2_CHG_OUT_TURNON BIT(5) BIT 75 drivers/power/supply/axp288_charger.c #define CHRG_ILIM_TEMP_LOOP_EN BIT(3) BIT 91 drivers/power/supply/axp288_charger.c #define FG_CNTL_OCV_ADJ_EN BIT(3) BIT 43 drivers/power/supply/bq2415x_charger.c #define BQ2415X_RESET_STATUS BIT(6) BIT 44 drivers/power/supply/bq2415x_charger.c #define BQ2415X_RESET_CONTROL (BIT(4)|BIT(5)) BIT 45 drivers/power/supply/bq2415x_charger.c #define BQ2415X_RESET_VOLTAGE (BIT(1)|BIT(3)) BIT 46 drivers/power/supply/bq2415x_charger.c #define BQ2415X_RESET_CURRENT (BIT(0)|BIT(3)|BIT(7)) BIT 52 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_STAT (BIT(4)|BIT(5)) BIT 55 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_FAULT (BIT(0)|BIT(1)|BIT(2)) BIT 59 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_LIMIT (BIT(6)|BIT(7)) BIT 61 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_VLOWV (BIT(4)|BIT(5)) BIT 69 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_VO (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) BIT 75 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_VENDER (BIT(5)|BIT(6)|BIT(7)) BIT 77 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_PN (BIT(3)|BIT(4)) BIT 79 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_REVISION (BIT(0)|BIT(1)|BIT(2)) BIT 83 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_RESET BIT(7) BIT 84 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_VI_CHRG (BIT(4)|BIT(5)|BIT(6)) BIT 87 drivers/power/supply/bq2415x_charger.c #define BQ2415X_MASK_VI_TERM (BIT(0)|BIT(1)|BIT(2)) BIT 236 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_read_mask(bq, reg, BIT(bit), bit); BIT 295 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_write_mask(bq, reg, val, BIT(bit), bit); BIT 26 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7) BIT 28 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_ISC_VINDPM_MASK (BIT(6) | BIT(5) | BIT(4) | \ BIT 29 drivers/power/supply/bq24190_charger.c BIT(3)) BIT 31 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_ISC_IINLIM_MASK (BIT(2) | BIT(1) | BIT(0)) BIT 35 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_POC_RESET_MASK BIT(7) BIT 37 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_POC_WDT_RESET_MASK BIT(6) BIT 39 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_POC_CHG_CONFIG_MASK (BIT(5) | BIT(4)) BIT 44 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_POC_SYS_MIN_MASK (BIT(3) | BIT(2) | BIT(1)) BIT 48 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_POC_BOOST_LIM_MASK BIT(0) BIT 52 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CCC_ICHG_MASK (BIT(7) | BIT(6) | BIT(5) | \ BIT 53 drivers/power/supply/bq24190_charger.c BIT(4) | BIT(3) | BIT(2)) BIT 55 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CCC_FORCE_20PCT_MASK BIT(0) BIT 59 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_PCTCC_IPRECHG_MASK (BIT(7) | BIT(6) | BIT(5) | \ BIT 60 drivers/power/supply/bq24190_charger.c BIT(4)) BIT 64 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_PCTCC_ITERM_MASK (BIT(3) | BIT(2) | BIT(1) | \ BIT 65 drivers/power/supply/bq24190_charger.c BIT(0)) BIT 71 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CVC_VREG_MASK (BIT(7) | BIT(6) | BIT(5) | \ BIT 72 drivers/power/supply/bq24190_charger.c BIT(4) | BIT(3) | BIT(2)) BIT 74 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CVC_BATLOWV_MASK BIT(1) BIT 76 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CVC_VRECHG_MASK BIT(0) BIT 80 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CTTC_EN_TERM_MASK BIT(7) BIT 82 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CTTC_TERM_STAT_MASK BIT(6) BIT 84 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CTTC_WATCHDOG_MASK (BIT(5) | BIT(4)) BIT 86 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CTTC_EN_TIMER_MASK BIT(3) BIT 88 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CTTC_CHG_TIMER_MASK (BIT(2) | BIT(1)) BIT 90 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_CTTC_JEITA_ISET_MASK BIT(0) BIT 94 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_ICTRC_BAT_COMP_MASK (BIT(7) | BIT(6) | BIT(5)) BIT 96 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_ICTRC_VCLAMP_MASK (BIT(4) | BIT(3) | BIT(2)) BIT 98 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_ICTRC_TREG_MASK (BIT(1) | BIT(0)) BIT 102 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_MOC_DPDM_EN_MASK BIT(7) BIT 104 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_MOC_TMR2X_EN_MASK BIT(6) BIT 106 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_MOC_BATFET_DISABLE_MASK BIT(5) BIT 108 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_MOC_JEITA_VSET_MASK BIT(4) BIT 110 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_MOC_INT_MASK_MASK (BIT(1) | BIT(0)) BIT 114 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_SS_VBUS_STAT_MASK (BIT(7) | BIT(6)) BIT 116 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_SS_CHRG_STAT_MASK (BIT(5) | BIT(4)) BIT 118 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_SS_DPM_STAT_MASK BIT(3) BIT 120 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_SS_PG_STAT_MASK BIT(2) BIT 122 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_SS_THERM_STAT_MASK BIT(1) BIT 124 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_SS_VSYS_STAT_MASK BIT(0) BIT 128 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_F_WATCHDOG_FAULT_MASK BIT(7) BIT 130 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_F_BOOST_FAULT_MASK BIT(6) BIT 132 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_F_CHRG_FAULT_MASK (BIT(5) | BIT(4)) BIT 134 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_F_BAT_FAULT_MASK BIT(3) BIT 136 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_F_NTC_FAULT_MASK (BIT(2) | BIT(1) | BIT(0)) BIT 140 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_VPRS_PN_MASK (BIT(5) | BIT(4) | BIT(3)) BIT 145 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_VPRS_TS_PROFILE_MASK BIT(2) BIT 147 drivers/power/supply/bq24190_charger.c #define BQ24190_REG_VPRS_DEV_REG_MASK (BIT(1) | BIT(0)) BIT 65 drivers/power/supply/bq27xxx_battery.c #define BQ27XXX_FLAG_DSC BIT(0) BIT 66 drivers/power/supply/bq27xxx_battery.c #define BQ27XXX_FLAG_SOCF BIT(1) /* State-of-Charge threshold final */ BIT 67 drivers/power/supply/bq27xxx_battery.c #define BQ27XXX_FLAG_SOC1 BIT(2) /* State-of-Charge threshold 1 */ BIT 68 drivers/power/supply/bq27xxx_battery.c #define BQ27XXX_FLAG_CFGUP BIT(4) BIT 69 drivers/power/supply/bq27xxx_battery.c #define BQ27XXX_FLAG_FC BIT(9) BIT 70 drivers/power/supply/bq27xxx_battery.c #define BQ27XXX_FLAG_OTD BIT(14) BIT 71 drivers/power/supply/bq27xxx_battery.c #define BQ27XXX_FLAG_OTC BIT(15) BIT 72 drivers/power/supply/bq27xxx_battery.c #define BQ27XXX_FLAG_UT BIT(14) BIT 73 drivers/power/supply/bq27xxx_battery.c #define BQ27XXX_FLAG_OT BIT(15) BIT 76 drivers/power/supply/bq27xxx_battery.c #define BQ27000_FLAG_EDVF BIT(0) /* Final End-of-Discharge-Voltage flag */ BIT 77 drivers/power/supply/bq27xxx_battery.c #define BQ27000_FLAG_EDV1 BIT(1) /* First End-of-Discharge-Voltage flag */ BIT 78 drivers/power/supply/bq27xxx_battery.c #define BQ27000_FLAG_CI BIT(4) /* Capacity Inaccurate flag */ BIT 79 drivers/power/supply/bq27xxx_battery.c #define BQ27000_FLAG_FC BIT(5) BIT 80 drivers/power/supply/bq27xxx_battery.c #define BQ27000_FLAG_CHGS BIT(7) /* Charge state flag */ BIT 44 drivers/power/supply/cpcap-battery.c #define CPCAP_REG_BPEOL_BIT_EOL9 BIT(9) /* Set for EOL irq */ BIT 45 drivers/power/supply/cpcap-battery.c #define CPCAP_REG_BPEOL_BIT_EOL8 BIT(8) /* Set for EOL irq */ BIT 46 drivers/power/supply/cpcap-battery.c #define CPCAP_REG_BPEOL_BIT_UNKNOWN7 BIT(7) BIT 47 drivers/power/supply/cpcap-battery.c #define CPCAP_REG_BPEOL_BIT_UNKNOWN6 BIT(6) BIT 48 drivers/power/supply/cpcap-battery.c #define CPCAP_REG_BPEOL_BIT_UNKNOWN5 BIT(5) BIT 49 drivers/power/supply/cpcap-battery.c #define CPCAP_REG_BPEOL_BIT_EOL_MULTI BIT(4) /* Set for multiple EOL irqs */ BIT 50 drivers/power/supply/cpcap-battery.c #define CPCAP_REG_BPEOL_BIT_UNKNOWN3 BIT(3) BIT 51 drivers/power/supply/cpcap-battery.c #define CPCAP_REG_BPEOL_BIT_UNKNOWN2 BIT(2) BIT 52 drivers/power/supply/cpcap-battery.c #define CPCAP_REG_BPEOL_BIT_BATTDETEN BIT(1) /* Enable battery detect */ BIT 53 drivers/power/supply/cpcap-battery.c #define CPCAP_REG_BPEOL_BIT_EOLSEL BIT(0) /* BPDET = 0, EOL = 1 */ BIT 41 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_UNUSED_641_15 BIT(15) /* 641 = register number */ BIT 42 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_UNUSED_641_14 BIT(14) /* 641 = register number */ BIT 43 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_CHRG_LED_EN BIT(13) /* Charger LED */ BIT 44 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_RVRSMODE BIT(12) /* USB VBUS output enable */ BIT 45 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_ICHRG_TR1 BIT(11) /* Trickle charge current */ BIT 46 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_ICHRG_TR0 BIT(10) BIT 47 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_FET_OVRD BIT(9) /* 0 = hardware, 1 = FET_CTRL */ BIT 48 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_FET_CTRL BIT(8) /* BPFET 1 if FET_OVRD set */ BIT 49 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_VCHRG3 BIT(7) /* Charge voltage bits */ BIT 50 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_VCHRG2 BIT(6) BIT 51 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_VCHRG1 BIT(5) BIT 52 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_VCHRG0 BIT(4) BIT 53 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_ICHRG3 BIT(3) /* Charge current bits */ BIT 54 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_ICHRG2 BIT(2) BIT 55 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_ICHRG1 BIT(1) BIT 56 drivers/power/supply/cpcap-charger.c #define CPCAP_REG_CRM_ICHRG0 BIT(0) BIT 112 drivers/power/supply/cpcap-charger.c #define CPCAP_BIT_VBUS_SWITCH BIT(0) /* VBUS boost to 5V */ BIT 415 drivers/power/supply/cpcap-charger.c s->chrg_det = val & BIT(13); BIT 416 drivers/power/supply/cpcap-charger.c s->rvrs_chrg = val & BIT(12); BIT 417 drivers/power/supply/cpcap-charger.c s->vbusov = val & BIT(11); BIT 423 drivers/power/supply/cpcap-charger.c s->chrg_se1b = val & BIT(13); BIT 424 drivers/power/supply/cpcap-charger.c s->rvrs_mode = val & BIT(6); BIT 425 drivers/power/supply/cpcap-charger.c s->chrgcurr1 = val & BIT(4); BIT 426 drivers/power/supply/cpcap-charger.c s->vbusvld = val & BIT(3); BIT 432 drivers/power/supply/cpcap-charger.c s->battdetb = val & BIT(6); BIT 31 drivers/power/supply/lp8727_charger.c #define LP8727_CP_EN BIT(0) BIT 32 drivers/power/supply/lp8727_charger.c #define LP8727_ADC_EN BIT(1) BIT 33 drivers/power/supply/lp8727_charger.c #define LP8727_ID200_EN BIT(4) BIT 36 drivers/power/supply/lp8727_charger.c #define LP8727_CHGDET_EN BIT(1) BIT 37 drivers/power/supply/lp8727_charger.c #define LP8727_INT_EN BIT(6) BIT 47 drivers/power/supply/lp8727_charger.c #define LP8727_VBUS BIT(4) BIT 51 drivers/power/supply/lp8727_charger.c #define LP8727_CHPORT BIT(6) BIT 52 drivers/power/supply/lp8727_charger.c #define LP8727_DCPORT BIT(7) BIT 32 drivers/power/supply/lp8788-charger.c #define LP8788_NO_BATT_M BIT(6) BIT 33 drivers/power/supply/lp8788-charger.c #define LP8788_BAD_BATT_M BIT(7) BIT 40 drivers/power/supply/lp8788-charger.c #define LP8788_CHG_EOC_MODE_M BIT(0) BIT 59 drivers/power/supply/ltc2941-battery-gauge.c #define LTC2941_REG_STATUS_CHIP_ID BIT(7) BIT 61 drivers/power/supply/ltc2941-battery-gauge.c #define LTC2942_REG_CONTROL_MODE_SCAN (BIT(7) | BIT(6)) BIT 62 drivers/power/supply/ltc2941-battery-gauge.c #define LTC2943_REG_CONTROL_MODE_SCAN BIT(7) BIT 63 drivers/power/supply/ltc2941-battery-gauge.c #define LTC294X_REG_CONTROL_PRESCALER_MASK (BIT(5) | BIT(4) | BIT(3)) BIT 64 drivers/power/supply/ltc2941-battery-gauge.c #define LTC294X_REG_CONTROL_SHUTDOWN_MASK (BIT(0)) BIT 68 drivers/power/supply/ltc2941-battery-gauge.c #define LTC294X_REG_CONTROL_ADC_DISABLE(x) ((x) & ~(BIT(7) | BIT(6))) BIT 40 drivers/power/supply/max14656_charger_detector.c #define INT_EN_REG_MASK BIT(4) BIT 41 drivers/power/supply/max14656_charger_detector.c #define CHG_TYPE_INT_MASK BIT(0) BIT 42 drivers/power/supply/max14656_charger_detector.c #define STATUS1_VB_VALID_MASK BIT(4) BIT 44 drivers/power/supply/max14656_charger_detector.c #define INT1_DCD_TIMEOUT_MASK BIT(7) BIT 46 drivers/power/supply/max14656_charger_detector.c #define CONTROL1_INT_EN BIT(4) BIT 47 drivers/power/supply/max14656_charger_detector.c #define CONTROL1_INT_ACTIVE_HIGH BIT(5) BIT 48 drivers/power/supply/max14656_charger_detector.c #define CONTROL1_EDGE BIT(7) BIT 50 drivers/power/supply/max14656_charger_detector.c #define CONTROL2_ADC_EN BIT(0) BIT 16 drivers/power/supply/max77650-charger.c #define MAX77650_CHARGER_ENABLED BIT(0) BIT 18 drivers/power/supply/max77650-charger.c #define MAX77650_CHARGER_CHG_EN_MASK BIT(0) BIT 59 drivers/power/supply/max77650-charger.c #define MAX77650_CHARGER_CHG_MASK BIT(1) BIT 39 drivers/power/supply/qcom_smbb.c #define CTRL_EN BIT(7) BIT 42 drivers/power/supply/qcom_smbb.c #define IBAT_TERM_CHG_IEOC BIT(7) BIT 43 drivers/power/supply/qcom_smbb.c #define IBAT_TERM_CHG_IEOC_BMS BIT(7) BIT 47 drivers/power/supply/qcom_smbb.c #define TCHG_MAX_EN BIT(7) BIT 50 drivers/power/supply/qcom_smbb.c #define WDOG_EN BIT(7) BIT 53 drivers/power/supply/qcom_smbb.c #define BUCK_REG_MODE BIT(0) BIT 54 drivers/power/supply/qcom_smbb.c #define BUCK_REG_MODE_VBAT BIT(0) BIT 58 drivers/power/supply/qcom_smbb.c #define PRES_STATUS_BAT_PRES BIT(7) BIT 60 drivers/power/supply/qcom_smbb.c #define TEMP_STATUS_OK BIT(7) BIT 61 drivers/power/supply/qcom_smbb.c #define TEMP_STATUS_HOT BIT(6) BIT 63 drivers/power/supply/qcom_smbb.c #define BTC_CTRL_COMP_EN BIT(7) BIT 64 drivers/power/supply/qcom_smbb.c #define BTC_CTRL_COLD_EXT BIT(1) BIT 65 drivers/power/supply/qcom_smbb.c #define BTC_CTRL_HOT_EXT_N BIT(0) BIT 69 drivers/power/supply/qcom_smbb.c #define OTG_CTL_EN BIT(0) BIT 71 drivers/power/supply/qcom_smbb.c #define ENUM_TIMER_STOP BIT(0) BIT 75 drivers/power/supply/qcom_smbb.c #define REV_BST_CHG_GONE BIT(7) BIT 81 drivers/power/supply/qcom_smbb.c #define BOOT_DONE BIT(7) BIT 83 drivers/power/supply/qcom_smbb.c #define STATUS_USBIN_VALID BIT(0) /* USB connection is valid */ BIT 84 drivers/power/supply/qcom_smbb.c #define STATUS_DCIN_VALID BIT(1) /* DC connection is valid */ BIT 85 drivers/power/supply/qcom_smbb.c #define STATUS_BAT_HOT BIT(2) /* Battery temp 1=Hot, 0=Cold */ BIT 86 drivers/power/supply/qcom_smbb.c #define STATUS_BAT_OK BIT(3) /* Battery temp OK */ BIT 87 drivers/power/supply/qcom_smbb.c #define STATUS_BAT_PRESENT BIT(4) /* Battery is present */ BIT 88 drivers/power/supply/qcom_smbb.c #define STATUS_CHG_DONE BIT(5) /* Charge cycle is complete */ BIT 89 drivers/power/supply/qcom_smbb.c #define STATUS_CHG_TRKL BIT(6) /* Trickle charging */ BIT 90 drivers/power/supply/qcom_smbb.c #define STATUS_CHG_FAST BIT(7) /* Fast charging */ BIT 91 drivers/power/supply/qcom_smbb.c #define STATUS_CHG_GONE BIT(8) /* No charger is connected */ BIT 733 drivers/power/supply/qcom_smbb.c { SMBB_CHG_CFG, 0xff, 0x00, BIT(3) }, BIT 989 drivers/power/supply/qcom_smbb.c if (r->rev_mask & BIT(chg->revision)) BIT 166 drivers/power/supply/rt9455_charger.c #define GET_MASK(fid) (BIT(rt9455_reg_fields[fid].msb + 1) - \ BIT 167 drivers/power/supply/rt9455_charger.c BIT(rt9455_reg_fields[fid].lsb)) BIT 152 drivers/power/supply/sbs-battery.c #define SBS_FLAGS_TI_BQ20Z75 BIT(0) BIT 28 drivers/power/supply/sbs-charger.c #define SBS_CHARGER_STATUS_CHARGE_INHIBITED BIT(1) BIT 29 drivers/power/supply/sbs-charger.c #define SBS_CHARGER_STATUS_RES_COLD BIT(9) BIT 30 drivers/power/supply/sbs-charger.c #define SBS_CHARGER_STATUS_RES_HOT BIT(10) BIT 31 drivers/power/supply/sbs-charger.c #define SBS_CHARGER_STATUS_BATTERY_PRESENT BIT(14) BIT 32 drivers/power/supply/sbs-charger.c #define SBS_CHARGER_STATUS_AC_PRESENT BIT(15) BIT 34 drivers/power/supply/sbs-manager.c #define SBSM_BIT_AC_PRESENT BIT(0) BIT 35 drivers/power/supply/sbs-manager.c #define SBSM_BIT_TURBO BIT(7) BIT 183 drivers/power/supply/sbs-manager.c reg = BIT(SBSM_SMB_BAT_OFFSET + chan); BIT 202 drivers/power/supply/sbs-manager.c return ret & BIT(off); BIT 260 drivers/power/supply/sbs-manager.c if (irq_bat & BIT(i)) { BIT 355 drivers/power/supply/sbs-manager.c if (data->supported_bats & BIT(i)) { BIT 14 drivers/power/supply/sc2731_charger.c #define SC2731_CHARGE_FULL BIT(4) BIT 16 drivers/power/supply/sc2731_charger.c #define SC2731_CHARGE_EN BIT(5) BIT 36 drivers/power/supply/sc2731_charger.c #define SC2731_CC_EN BIT(13) BIT 37 drivers/power/supply/sc2731_charger.c #define SC2731_CHARGER_PD BIT(0) BIT 19 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_EN BIT(7) BIT 20 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_RTC_EN BIT(6) BIT 46 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_WRITE_SELCLB_EN BIT(0) BIT 52 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_LOW_OVERLOAD_INT BIT(0) BIT 53 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_CLBCNT_DELTA_INT BIT(2) BIT 43 drivers/power/supply/smb347-charger.c #define CFG_STAT_DISABLED BIT(5) BIT 44 drivers/power/supply/smb347-charger.c #define CFG_STAT_ACTIVE_HIGH BIT(7) BIT 49 drivers/power/supply/smb347-charger.c #define CFG_PIN_EN_APSD_IRQ BIT(1) BIT 50 drivers/power/supply/smb347-charger.c #define CFG_PIN_EN_CHARGER_ERROR BIT(2) BIT 56 drivers/power/supply/smb347-charger.c #define CFG_THERM_MONITOR_DISABLED BIT(4) BIT 58 drivers/power/supply/smb347-charger.c #define CFG_SYSOK_SUSPEND_HARD_LIMIT_DISABLED BIT(2) BIT 77 drivers/power/supply/smb347-charger.c #define CFG_FAULT_IRQ_DCIN_UV BIT(2) BIT 79 drivers/power/supply/smb347-charger.c #define CFG_STATUS_IRQ_TERMINATION_OR_TAPER BIT(4) BIT 80 drivers/power/supply/smb347-charger.c #define CFG_STATUS_IRQ_CHARGE_TIMEOUT BIT(7) BIT 85 drivers/power/supply/smb347-charger.c #define CMD_A_CHG_ENABLED BIT(1) BIT 86 drivers/power/supply/smb347-charger.c #define CMD_A_SUSPEND_ENABLED BIT(2) BIT 87 drivers/power/supply/smb347-charger.c #define CMD_A_ALLOW_WRITE BIT(7) BIT 94 drivers/power/supply/smb347-charger.c #define IRQSTAT_C_TERMINATION_STAT BIT(0) BIT 95 drivers/power/supply/smb347-charger.c #define IRQSTAT_C_TERMINATION_IRQ BIT(1) BIT 96 drivers/power/supply/smb347-charger.c #define IRQSTAT_C_TAPER_IRQ BIT(3) BIT 98 drivers/power/supply/smb347-charger.c #define IRQSTAT_D_CHARGE_TIMEOUT_STAT BIT(2) BIT 99 drivers/power/supply/smb347-charger.c #define IRQSTAT_D_CHARGE_TIMEOUT_IRQ BIT(3) BIT 101 drivers/power/supply/smb347-charger.c #define IRQSTAT_E_USBIN_UV_STAT BIT(0) BIT 102 drivers/power/supply/smb347-charger.c #define IRQSTAT_E_USBIN_UV_IRQ BIT(1) BIT 103 drivers/power/supply/smb347-charger.c #define IRQSTAT_E_DCIN_UV_STAT BIT(4) BIT 104 drivers/power/supply/smb347-charger.c #define IRQSTAT_E_DCIN_UV_IRQ BIT(5) BIT 112 drivers/power/supply/smb347-charger.c #define STAT_C_CHG_ENABLED BIT(0) BIT 113 drivers/power/supply/smb347-charger.c #define STAT_C_HOLDOFF_STAT BIT(3) BIT 116 drivers/power/supply/smb347-charger.c #define STAT_C_CHG_TERM BIT(5) BIT 117 drivers/power/supply/smb347-charger.c #define STAT_C_CHARGER_ERROR BIT(6) BIT 23 drivers/power/supply/tps65090-charger.c #define TPS65090_CHARGER_ENABLE BIT(0) BIT 24 drivers/power/supply/tps65090-charger.c #define TPS65090_VACG BIT(1) BIT 25 drivers/power/supply/tps65090-charger.c #define TPS65090_NOITERM BIT(5) BIT 43 drivers/power/supply/twl4030_charger.c #define TWL4030_BCIAUTOWEN BIT(5) BIT 44 drivers/power/supply/twl4030_charger.c #define TWL4030_CONFIG_DONE BIT(4) BIT 45 drivers/power/supply/twl4030_charger.c #define TWL4030_CVENAC BIT(2) BIT 46 drivers/power/supply/twl4030_charger.c #define TWL4030_BCIAUTOUSB BIT(1) BIT 47 drivers/power/supply/twl4030_charger.c #define TWL4030_BCIAUTOAC BIT(0) BIT 48 drivers/power/supply/twl4030_charger.c #define TWL4030_CGAIN BIT(5) BIT 49 drivers/power/supply/twl4030_charger.c #define TWL4030_USBFASTMCHG BIT(2) BIT 50 drivers/power/supply/twl4030_charger.c #define TWL4030_STS_VBUS BIT(7) BIT 51 drivers/power/supply/twl4030_charger.c #define TWL4030_STS_USB_ID BIT(2) BIT 52 drivers/power/supply/twl4030_charger.c #define TWL4030_BBCHEN BIT(4) BIT 64 drivers/power/supply/twl4030_charger.c #define TWL4030_BATSTSPCHG BIT(2) BIT 65 drivers/power/supply/twl4030_charger.c #define TWL4030_BATSTSMCHG BIT(6) BIT 68 drivers/power/supply/twl4030_charger.c #define TWL4030_WOVF BIT(0) /* Watchdog overflow */ BIT 69 drivers/power/supply/twl4030_charger.c #define TWL4030_TMOVF BIT(1) /* Timer overflow */ BIT 70 drivers/power/supply/twl4030_charger.c #define TWL4030_ICHGHIGH BIT(2) /* Battery charge current high */ BIT 71 drivers/power/supply/twl4030_charger.c #define TWL4030_ICHGLOW BIT(3) /* Battery cc. low / FSM state change */ BIT 72 drivers/power/supply/twl4030_charger.c #define TWL4030_ICHGEOC BIT(4) /* Battery current end-of-charge */ BIT 73 drivers/power/supply/twl4030_charger.c #define TWL4030_TBATOR2 BIT(5) /* Battery temperature out of range 2 */ BIT 74 drivers/power/supply/twl4030_charger.c #define TWL4030_TBATOR1 BIT(6) /* Battery temperature out of range 1 */ BIT 75 drivers/power/supply/twl4030_charger.c #define TWL4030_BATSTS BIT(7) /* Battery status */ BIT 77 drivers/power/supply/twl4030_charger.c #define TWL4030_VBATLVL BIT(0) /* VBAT level */ BIT 78 drivers/power/supply/twl4030_charger.c #define TWL4030_VBATOV BIT(1) /* VBAT overvoltage */ BIT 79 drivers/power/supply/twl4030_charger.c #define TWL4030_VBUSOV BIT(2) /* VBUS overvoltage */ BIT 80 drivers/power/supply/twl4030_charger.c #define TWL4030_ACCHGOV BIT(3) /* Ac charger overvoltage */ BIT 82 drivers/power/supply/twl4030_charger.c #define TWL4030_MSTATEC_USB BIT(4) BIT 83 drivers/power/supply/twl4030_charger.c #define TWL4030_MSTATEC_AC BIT(5) BIT 36 drivers/power/supply/ucs1002_power.c # define F_ADET_PIN BIT(4) BIT 37 drivers/power/supply/ucs1002_power.c # define F_CHG_ACT BIT(3) BIT 41 drivers/power/supply/ucs1002_power.c # define F_DISCHARGE_ERR BIT(6) BIT 42 drivers/power/supply/ucs1002_power.c # define F_RESET BIT(5) BIT 43 drivers/power/supply/ucs1002_power.c # define F_MIN_KEEP_OUT BIT(4) BIT 44 drivers/power/supply/ucs1002_power.c # define F_TSD BIT(3) BIT 45 drivers/power/supply/ucs1002_power.c # define F_OVER_VOLT BIT(2) BIT 46 drivers/power/supply/ucs1002_power.c # define F_BACK_VOLT BIT(1) BIT 47 drivers/power/supply/ucs1002_power.c # define F_OVER_ILIM BIT(0) BIT 52 drivers/power/supply/ucs1002_power.c # define F_PWR_EN_PIN BIT(6) BIT 53 drivers/power/supply/ucs1002_power.c # define F_M2_PIN BIT(5) BIT 54 drivers/power/supply/ucs1002_power.c # define F_M1_PIN BIT(4) BIT 55 drivers/power/supply/ucs1002_power.c # define F_EM_EN_PIN BIT(3) BIT 56 drivers/power/supply/ucs1002_power.c # define F_SEL_PIN BIT(2) BIT 66 drivers/power/supply/ucs1002_power.c # define F_RATION_EN BIT(3) BIT 73 drivers/power/supply/ucs1002_power.c # define F_PIN_IGNORE BIT(7) BIT 74 drivers/power/supply/ucs1002_power.c # define F_EM_EN_SET BIT(5) BIT 75 drivers/power/supply/ucs1002_power.c # define F_M2_SET BIT(4) BIT 76 drivers/power/supply/ucs1002_power.c # define F_M1_SET BIT(3) BIT 77 drivers/power/supply/ucs1002_power.c # define F_S0_SET BIT(2) BIT 78 drivers/power/supply/ucs1002_power.c # define F_PWR_EN_SET BIT(1) BIT 79 drivers/power/supply/ucs1002_power.c # define F_LATCH_SET BIT(0) BIT 36 drivers/powercap/intel_rapl_common.c #define POWER_LIMIT1_ENABLE BIT(15) BIT 37 drivers/powercap/intel_rapl_common.c #define POWER_LIMIT1_CLAMP BIT(16) BIT 43 drivers/powercap/intel_rapl_common.c #define POWER_LOW_LOCK BIT(31) BIT 66 drivers/powercap/intel_rapl_common.c #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ BIT 67 drivers/powercap/intel_rapl_common.c #define RAPL_PRIMITIVE_DUMMY BIT(2) BIT 82 drivers/powercap/intel_rapl_common.c #define DOMAIN_STATE_INACTIVE BIT(0) BIT 83 drivers/powercap/intel_rapl_common.c #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) BIT 84 drivers/powercap/intel_rapl_common.c #define DOMAIN_STATE_BIOS_LOCKED BIT(2) BIT 106 drivers/powercap/intel_rapl_common.c #define PACKAGE_PLN_INT_SAVED BIT(0) BIT 47 drivers/ptp/ptp_dte.c #define DTE_PPB_ADJ(ppb) (u32)(div64_u64((((u64)abs(ppb) * BIT(28)) +\ BIT 19 drivers/pwm/pwm-atmel-hlcdc.c #define ATMEL_HLCDC_PWMPOL BIT(4) BIT 92 drivers/pwm/pwm-bcm-iproc.c if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) BIT 97 drivers/pwm/pwm-bcm-iproc.c if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm))) BIT 22 drivers/pwm/pwm-berlin.c #define BERLIN_PWM_ENABLE BIT(0) BIT 36 drivers/pwm/pwm-berlin.c #define BERLIN_PWM_INVERT_POLARITY BIT(3) BIT 23 drivers/pwm/pwm-brcmstb.c #define CTRL_START BIT(0) BIT 24 drivers/pwm/pwm-brcmstb.c #define CTRL_OEB BIT(1) BIT 25 drivers/pwm/pwm-brcmstb.c #define CTRL_FORCE_HIGH BIT(2) BIT 26 drivers/pwm/pwm-brcmstb.c #define CTRL_OPENDRAIN BIT(3) BIT 30 drivers/pwm/pwm-brcmstb.c #define CTRL2_OUT_SELECT BIT(0) BIT 14 drivers/pwm/pwm-crc.c #define PWM_OUTPUT_ENABLE BIT(7) BIT 97 drivers/pwm/pwm-fsl-ftm.c regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), BIT 98 drivers/pwm/pwm-fsl-ftm.c BIT(pwm->hwpwm + 16)); BIT 111 drivers/pwm/pwm-fsl-ftm.c regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), BIT 222 drivers/pwm/pwm-fsl-ftm.c if (~(val | BIT(pwm->hwpwm)) & 0xFF) BIT 291 drivers/pwm/pwm-fsl-ftm.c reg_polarity = BIT(pwm->hwpwm); BIT 293 drivers/pwm/pwm-fsl-ftm.c regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity); BIT 321 drivers/pwm/pwm-fsl-ftm.c BIT(pwm->hwpwm), BIT(pwm->hwpwm)); BIT 345 drivers/pwm/pwm-fsl-ftm.c regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), BIT 24 drivers/pwm/pwm-hibvt.c #define PWM_ENABLE_MASK BIT(0) BIT 27 drivers/pwm/pwm-hibvt.c #define PWM_POLARITY_MASK BIT(1) BIT 30 drivers/pwm/pwm-hibvt.c #define PWM_KEEP_MASK BIT(2) BIT 162 drivers/pwm/pwm-img.c val |= BIT(pwm->hwpwm); BIT 178 drivers/pwm/pwm-img.c val &= ~BIT(pwm->hwpwm); BIT 339 drivers/pwm/pwm-img.c val &= ~BIT(i); BIT 391 drivers/pwm/pwm-img.c if (pwm_chip->suspend_ctrl_cfg & BIT(i)) BIT 42 drivers/pwm/pwm-imx-tpm.c #define PWM_IMX_TPM_SC_CPWMS BIT(5) BIT 44 drivers/pwm/pwm-imx-tpm.c #define PWM_IMX_TPM_CnSC_CHF BIT(7) BIT 45 drivers/pwm/pwm-imx-tpm.c #define PWM_IMX_TPM_CnSC_MSB BIT(5) BIT 46 drivers/pwm/pwm-imx-tpm.c #define PWM_IMX_TPM_CnSC_MSA BIT(4) BIT 26 drivers/pwm/pwm-imx1.c #define MX1_PWMC_EN BIT(4) BIT 32 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_STOPEN BIT(25) BIT 33 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_DOZEN BIT(24) BIT 34 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_WAITEN BIT(23) BIT 35 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_DBGEN BIT(22) BIT 36 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_BCTR BIT(21) BIT 37 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_HCTR BIT(20) BIT 52 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_SWR BIT(3) BIT 60 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_EN BIT(0) BIT 62 drivers/pwm/pwm-imx27.c #define MX3_PWMSR_FWE BIT(6) BIT 63 drivers/pwm/pwm-imx27.c #define MX3_PWMSR_CMP BIT(5) BIT 64 drivers/pwm/pwm-imx27.c #define MX3_PWMSR_ROV BIT(4) BIT 65 drivers/pwm/pwm-imx27.c #define MX3_PWMSR_FE BIT(3) BIT 31 drivers/pwm/pwm-lpc18xx-sct.c #define LPC18XX_PWM_CONFIG_UNIFY BIT(0) BIT 32 drivers/pwm/pwm-lpc18xx-sct.c #define LPC18XX_PWM_CONFIG_NORELOAD BIT(7) BIT 35 drivers/pwm/pwm-lpc18xx-sct.c #define LPC18XX_PWM_CTRL_HALT BIT(2) BIT 36 drivers/pwm/pwm-lpc18xx-sct.c #define LPC18XX_PWM_BIDIR BIT(4) BIT 260 drivers/pwm/pwm-lpc18xx-sct.c BIT(set_event)); BIT 262 drivers/pwm/pwm-lpc18xx-sct.c BIT(clear_event)); BIT 401 drivers/pwm/pwm-lpc18xx-sct.c BIT(lpc18xx_pwm->period_event)); BIT 23 drivers/pwm/pwm-lpc32xx.c #define PWM_ENABLE BIT(31) BIT 24 drivers/pwm/pwm-lpc32xx.c #define PWM_PIN_LEVEL BIT(30) BIT 24 drivers/pwm/pwm-lpss.c #define PWM_ENABLE BIT(31) BIT 25 drivers/pwm/pwm-lpss.c #define PWM_SW_UPDATE BIT(30) BIT 96 drivers/pwm/pwm-lpss.c base_unit_range = BIT(lpwm->info->base_unit_bits) - 1; BIT 170 drivers/pwm/pwm-lpss.c base_unit_range = BIT(lpwm->info->base_unit_bits); BIT 162 drivers/pwm/pwm-mediatek.c pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); BIT 182 drivers/pwm/pwm-mediatek.c value |= BIT(pwm->hwpwm); BIT 194 drivers/pwm/pwm-mediatek.c value &= ~BIT(pwm->hwpwm); BIT 52 drivers/pwm/pwm-meson.c #define MISC_B_CLK_EN BIT(23) BIT 53 drivers/pwm/pwm-meson.c #define MISC_A_CLK_EN BIT(15) BIT 60 drivers/pwm/pwm-meson.c #define MISC_B_EN BIT(1) BIT 61 drivers/pwm/pwm-meson.c #define MISC_A_EN BIT(0) BIT 253 drivers/pwm/pwm-mtk-disp.c .enable_mask = BIT(16), BIT 263 drivers/pwm/pwm-mtk-disp.c .enable_mask = BIT(0), BIT 273 drivers/pwm/pwm-mtk-disp.c .enable_mask = BIT(0), BIT 26 drivers/pwm/pwm-rcar.c #define RCAR_PWMCR_CCMD BIT(15) BIT 27 drivers/pwm/pwm-rcar.c #define RCAR_PWMCR_SYNC BIT(11) BIT 28 drivers/pwm/pwm-rcar.c #define RCAR_PWMCR_SS0 BIT(4) BIT 29 drivers/pwm/pwm-rcar.c #define RCAR_PWMCR_EN0 BIT(0) BIT 50 drivers/pwm/pwm-samsung.c #define TCON_START(chan) BIT(4 * (chan) + 0) BIT 51 drivers/pwm/pwm-samsung.c #define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1) BIT 52 drivers/pwm/pwm-samsung.c #define TCON_INVERT(chan) BIT(4 * (chan) + 2) BIT 53 drivers/pwm/pwm-samsung.c #define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3) BIT 54 drivers/pwm/pwm-samsung.c #define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2) BIT 149 drivers/pwm/pwm-samsung.c return (BIT(reg) & variant->tclk_mask) == 0; BIT 209 drivers/pwm/pwm-samsung.c pwm_samsung_set_divisor(chip, chan, BIT(div)); BIT 219 drivers/pwm/pwm-samsung.c if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { BIT 259 drivers/pwm/pwm-samsung.c our_chip->disabled_mask &= ~BIT(pwm->hwpwm); BIT 279 drivers/pwm/pwm-samsung.c our_chip->disabled_mask |= BIT(pwm->hwpwm); BIT 402 drivers/pwm/pwm-samsung.c chip->inverter_mask |= BIT(channel); BIT 405 drivers/pwm/pwm-samsung.c chip->inverter_mask &= ~BIT(channel); BIT 442 drivers/pwm/pwm-samsung.c .tclk_mask = BIT(4), BIT 449 drivers/pwm/pwm-samsung.c .tclk_mask = BIT(7) | BIT(6) | BIT(5), BIT 463 drivers/pwm/pwm-samsung.c .tclk_mask = BIT(5), BIT 497 drivers/pwm/pwm-samsung.c chip->variant.output_mask |= BIT(val); BIT 525 drivers/pwm/pwm-samsung.c chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1; BIT 562 drivers/pwm/pwm-samsung.c if (chip->variant.output_mask & BIT(chan)) BIT 614 drivers/pwm/pwm-samsung.c if (our_chip->variant.output_mask & BIT(i)) BIT 616 drivers/pwm/pwm-samsung.c our_chip->inverter_mask & BIT(i)); BIT 625 drivers/pwm/pwm-samsung.c if (our_chip->disabled_mask & BIT(i)) BIT 30 drivers/pwm/pwm-sifive.c #define PWM_SIFIVE_PWMCFG_STICKY BIT(8) BIT 31 drivers/pwm/pwm-sifive.c #define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9) BIT 32 drivers/pwm/pwm-sifive.c #define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10) BIT 33 drivers/pwm/pwm-sifive.c #define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12) BIT 34 drivers/pwm/pwm-sifive.c #define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13) BIT 35 drivers/pwm/pwm-sifive.c #define PWM_SIFIVE_PWMCFG_CENTER BIT(16) BIT 36 drivers/pwm/pwm-sifive.c #define PWM_SIFIVE_PWMCFG_GANG BIT(24) BIT 37 drivers/pwm/pwm-sifive.c #define PWM_SIFIVE_PWMCFG_IP BIT(28) BIT 22 drivers/pwm/pwm-sprd.c #define SPRD_PWM_ENABLE_BIT BIT(0) BIT 333 drivers/pwm/pwm-sti.c regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm)); BIT 19 drivers/pwm/pwm-stmpe.c #define PWMCS_EN_PWM0 BIT(0) BIT 20 drivers/pwm/pwm-stmpe.c #define PWMCS_EN_PWM1 BIT(1) BIT 21 drivers/pwm/pwm-stmpe.c #define PWMCS_EN_PWM2 BIT(2) BIT 52 drivers/pwm/pwm-stmpe.c value = ret | BIT(pwm->hwpwm); BIT 78 drivers/pwm/pwm-stmpe.c value = ret & ~BIT(pwm->hwpwm); BIT 92 drivers/pwm/pwm-stmpe.c #define LOAD BIT(14) /* Only available on 2403 */ BIT 94 drivers/pwm/pwm-stmpe.c #define RAMPDOWN BIT(7) BIT 95 drivers/pwm/pwm-stmpe.c #define PRESCALE_512 BIT(14) BIT 96 drivers/pwm/pwm-stmpe.c #define STEPTIME_1 BIT(8) BIT 97 drivers/pwm/pwm-stmpe.c #define BRANCH (BIT(15) | BIT(13)) BIT 124 drivers/pwm/pwm-stmpe.c ret = stmpe_set_altfunc(stmpe_pwm->stmpe, BIT(pin), BIT 32 drivers/pwm/pwm-sun4i.c #define PWM_EN BIT(4) BIT 33 drivers/pwm/pwm-sun4i.c #define PWM_ACT_STATE BIT(5) BIT 34 drivers/pwm/pwm-sun4i.c #define PWM_CLK_GATING BIT(6) BIT 35 drivers/pwm/pwm-sun4i.c #define PWM_MODE BIT(7) BIT 36 drivers/pwm/pwm-sun4i.c #define PWM_PULSE BIT(8) BIT 37 drivers/pwm/pwm-sun4i.c #define PWM_BYPASS BIT(9) BIT 41 drivers/pwm/pwm-sun4i.c #define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch)) BIT 23 drivers/pwm/pwm-tiecap.c #define ECCTL2_APWM_POL_LOW BIT(10) BIT 24 drivers/pwm/pwm-tiecap.c #define ECCTL2_APWM_MODE BIT(9) BIT 25 drivers/pwm/pwm-tiecap.c #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6)) BIT 26 drivers/pwm/pwm-tiecap.c #define ECCTL2_TSCTR_FREERUN BIT(4) BIT 23 drivers/pwm/pwm-tiehrpwm.c #define TBCTL_PRDLD_MASK BIT(3) BIT 25 drivers/pwm/pwm-tiehrpwm.c #define TBCTL_PRDLD_IMDT BIT(3) BIT 26 drivers/pwm/pwm-tiehrpwm.c #define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \ BIT 27 drivers/pwm/pwm-tiehrpwm.c BIT(8) | BIT(7)) BIT 28 drivers/pwm/pwm-tiehrpwm.c #define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0)) BIT 30 drivers/pwm/pwm-tiehrpwm.c #define TBCTL_CTRMODE_DOWN BIT(0) BIT 31 drivers/pwm/pwm-tiehrpwm.c #define TBCTL_CTRMODE_UPDOWN BIT(1) BIT 32 drivers/pwm/pwm-tiehrpwm.c #define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0)) BIT 51 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_CBU_MASK (BIT(9) | BIT(8)) BIT 52 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_CBU_FRCLOW BIT(8) BIT 53 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_CBU_FRCHIGH BIT(9) BIT 54 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8)) BIT 55 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_CAU_MASK (BIT(5) | BIT(4)) BIT 56 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_CAU_FRCLOW BIT(4) BIT 57 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_CAU_FRCHIGH BIT(5) BIT 58 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4)) BIT 59 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_PRD_MASK (BIT(3) | BIT(2)) BIT 60 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_PRD_FRCLOW BIT(2) BIT 61 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_PRD_FRCHIGH BIT(3) BIT 62 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2)) BIT 63 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_ZRO_MASK (BIT(1) | BIT(0)) BIT 64 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_ZRO_FRCLOW BIT(0) BIT 65 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_ZRO_FRCHIGH BIT(1) BIT 66 drivers/pwm/pwm-tiehrpwm.c #define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0)) BIT 77 drivers/pwm/pwm-tiehrpwm.c #define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6)) BIT 79 drivers/pwm/pwm-tiehrpwm.c #define AQSFRC_RLDCSF_PRD BIT(6) BIT 80 drivers/pwm/pwm-tiehrpwm.c #define AQSFRC_RLDCSF_ZROPRD BIT(7) BIT 81 drivers/pwm/pwm-tiehrpwm.c #define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6)) BIT 83 drivers/pwm/pwm-tiehrpwm.c #define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2)) BIT 85 drivers/pwm/pwm-tiehrpwm.c #define AQCSFRC_CSFB_FRCLOW BIT(2) BIT 86 drivers/pwm/pwm-tiehrpwm.c #define AQCSFRC_CSFB_FRCHIGH BIT(3) BIT 87 drivers/pwm/pwm-tiehrpwm.c #define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2)) BIT 88 drivers/pwm/pwm-tiehrpwm.c #define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0)) BIT 90 drivers/pwm/pwm-tiehrpwm.c #define AQCSFRC_CSFA_FRCLOW BIT(0) BIT 91 drivers/pwm/pwm-tiehrpwm.c #define AQCSFRC_CSFA_FRCHIGH BIT(1) BIT 92 drivers/pwm/pwm-tiehrpwm.c #define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) BIT 37 drivers/pwm/pwm-vt8500.c #define CTRL_ENABLE BIT(0) BIT 38 drivers/pwm/pwm-vt8500.c #define CTRL_INVERT BIT(1) BIT 39 drivers/pwm/pwm-vt8500.c #define CTRL_AUTOLOAD BIT(2) BIT 40 drivers/pwm/pwm-vt8500.c #define CTRL_STOP_IMM BIT(3) BIT 41 drivers/pwm/pwm-vt8500.c #define CTRL_LOAD_PRESCALE BIT(4) BIT 42 drivers/pwm/pwm-vt8500.c #define CTRL_LOAD_PERIOD BIT(5) BIT 44 drivers/pwm/pwm-vt8500.c #define STATUS_CTRL_UPDATE BIT(0) BIT 45 drivers/pwm/pwm-vt8500.c #define STATUS_SCALAR_UPDATE BIT(1) BIT 46 drivers/pwm/pwm-vt8500.c #define STATUS_PERIOD_UPDATE BIT(2) BIT 47 drivers/pwm/pwm-vt8500.c #define STATUS_DUTY_UPDATE BIT(3) BIT 21 drivers/pwm/pwm-zx.c #define ZX_PWM_POLAR BIT(1) BIT 22 drivers/pwm/pwm-zx.c #define ZX_PWM_EN BIT(0) BIT 52 drivers/rapidio/devices/rio_mport_cdev.c DBG_INIT = BIT(0), /* driver init */ BIT 53 drivers/rapidio/devices/rio_mport_cdev.c DBG_EXIT = BIT(1), /* driver exit */ BIT 54 drivers/rapidio/devices/rio_mport_cdev.c DBG_MPORT = BIT(2), /* mport add/remove */ BIT 55 drivers/rapidio/devices/rio_mport_cdev.c DBG_RDEV = BIT(3), /* RapidIO device add/remove */ BIT 56 drivers/rapidio/devices/rio_mport_cdev.c DBG_DMA = BIT(4), /* DMA transfer messages */ BIT 57 drivers/rapidio/devices/rio_mport_cdev.c DBG_MMAP = BIT(5), /* mapping messages */ BIT 58 drivers/rapidio/devices/rio_mport_cdev.c DBG_IBW = BIT(6), /* inbound window */ BIT 59 drivers/rapidio/devices/rio_mport_cdev.c DBG_EVENT = BIT(7), /* event handling messages */ BIT 60 drivers/rapidio/devices/rio_mport_cdev.c DBG_OBW = BIT(8), /* outbound window messages */ BIT 61 drivers/rapidio/devices/rio_mport_cdev.c DBG_DBELL = BIT(9), /* doorbell messages */ BIT 14 drivers/rapidio/devices/tsi721.h DBG_INIT = BIT(0), /* driver init */ BIT 15 drivers/rapidio/devices/tsi721.h DBG_EXIT = BIT(1), /* driver exit */ BIT 16 drivers/rapidio/devices/tsi721.h DBG_MPORT = BIT(2), /* mport add/remove */ BIT 17 drivers/rapidio/devices/tsi721.h DBG_MAINT = BIT(3), /* maintenance ops messages */ BIT 18 drivers/rapidio/devices/tsi721.h DBG_DMA = BIT(4), /* DMA transfer messages */ BIT 19 drivers/rapidio/devices/tsi721.h DBG_DMAV = BIT(5), /* verbose DMA transfer messages */ BIT 20 drivers/rapidio/devices/tsi721.h DBG_IBW = BIT(6), /* inbound window */ BIT 21 drivers/rapidio/devices/tsi721.h DBG_EVENT = BIT(7), /* event handling messages */ BIT 22 drivers/rapidio/devices/tsi721.h DBG_OBW = BIT(8), /* outbound window messages */ BIT 23 drivers/rapidio/devices/tsi721.h DBG_DBELL = BIT(9), /* doorbell messages */ BIT 24 drivers/rapidio/devices/tsi721.h DBG_OMSG = BIT(10), /* doorbell messages */ BIT 25 drivers/rapidio/devices/tsi721.h DBG_IMSG = BIT(11), /* doorbell messages */ BIT 37 drivers/rapidio/rio_cm.c DBG_INIT = BIT(0), /* driver init */ BIT 38 drivers/rapidio/rio_cm.c DBG_EXIT = BIT(1), /* driver exit */ BIT 39 drivers/rapidio/rio_cm.c DBG_MPORT = BIT(2), /* mport add/remove */ BIT 40 drivers/rapidio/rio_cm.c DBG_RDEV = BIT(3), /* RapidIO device add/remove */ BIT 41 drivers/rapidio/rio_cm.c DBG_CHOP = BIT(4), /* channel operations */ BIT 42 drivers/rapidio/rio_cm.c DBG_WAIT = BIT(5), /* waiting for events */ BIT 43 drivers/rapidio/rio_cm.c DBG_TX = BIT(6), /* message TX */ BIT 44 drivers/rapidio/rio_cm.c DBG_TX_EVENT = BIT(7), /* message TX event */ BIT 45 drivers/rapidio/rio_cm.c DBG_RX_DATA = BIT(8), /* inbound data messages */ BIT 46 drivers/rapidio/rio_cm.c DBG_RX_CMD = BIT(9), /* inbound REQ/ACK/NACK messages */ BIT 292 drivers/regulator/88pm8607.c PM8607_DVC(BUCK1, GO, BIT(0), SUPPLIES_EN11, 0), BIT 293 drivers/regulator/88pm8607.c PM8607_DVC(BUCK2, GO, BIT(1), SUPPLIES_EN11, 1), BIT 294 drivers/regulator/88pm8607.c PM8607_DVC(BUCK3, GO, BIT(2), SUPPLIES_EN11, 2), BIT 133 drivers/regulator/act8865-regulator.c #define ACT8600_APCH_CHG_ACIN BIT(7) BIT 134 drivers/regulator/act8865-regulator.c #define ACT8600_APCH_CHG_USB BIT(6) BIT 135 drivers/regulator/act8865-regulator.c #define ACT8600_APCH_CSTATE0 BIT(5) BIT 136 drivers/regulator/act8865-regulator.c #define ACT8600_APCH_CSTATE1 BIT(4) BIT 276 drivers/regulator/act8865-regulator.c val |= BIT(4); BIT 345 drivers/regulator/act8865-regulator.c val = BIT(5); BIT 349 drivers/regulator/act8865-regulator.c val = BIT(5); BIT 355 drivers/regulator/act8865-regulator.c return regmap_update_bits(regmap, reg, BIT(5), val); BIT 394 drivers/regulator/act8865-regulator.c if (id <= ACT8865_ID_DCDC3 && (val & BIT(5))) BIT 396 drivers/regulator/act8865-regulator.c else if (id > ACT8865_ID_DCDC3 && !(val & BIT(5))) BIT 122 drivers/regulator/act8945a-regulator.c val |= BIT(4); BIT 190 drivers/regulator/act8945a-regulator.c val = BIT(5); BIT 194 drivers/regulator/act8945a-regulator.c val = BIT(5); BIT 200 drivers/regulator/act8945a-regulator.c ret = regmap_update_bits(regmap, reg, BIT(5), val); BIT 301 drivers/regulator/anatop-regulator.c rdesc->enable_mask = BIT(enable_bit); BIT 133 drivers/regulator/as3711-regulator.c .enable_mask = BIT(_en_bit), \ BIT 63 drivers/regulator/axp20x-regulator.c #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2) BIT 65 drivers/regulator/axp20x-regulator.c #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3) BIT 94 drivers/regulator/axp20x-regulator.c #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4) BIT 156 drivers/regulator/axp20x-regulator.c #define AXP803_DCDC23_POLYPHASE_DUAL BIT(6) BIT 157 drivers/regulator/axp20x-regulator.c #define AXP803_DCDC56_POLYPHASE_DUAL BIT(5) BIT 236 drivers/regulator/axp20x-regulator.c #define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5) BIT 48 drivers/regulator/bcm590xx-regulator.c #define BCM590XX_REG_ENABLE BIT(7) BIT 49 drivers/regulator/bcm590xx-regulator.c #define BCM590XX_VBUS_ENABLE BIT(2) BIT 36 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VSDIO_SEL BIT(15) BIT 37 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VDIG_SEL BIT(14) BIT 38 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VCAM_SEL BIT(13) BIT 39 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_SW6_SEL BIT(12) BIT 40 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_SW5_SEL BIT(11) BIT 41 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_SW4_SEL BIT(10) BIT 42 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_SW3_SEL BIT(9) BIT 43 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_SW2_SEL BIT(8) BIT 44 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_SW1_SEL BIT(7) BIT 47 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VUSBINT2_SEL BIT(15) BIT 48 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VUSBINT1_SEL BIT(14) BIT 49 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VVIB_SEL BIT(13) BIT 50 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VWLAN1_SEL BIT(12) BIT 51 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VRF1_SEL BIT(11) BIT 52 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VHVIO_SEL BIT(10) BIT 53 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VDAC_SEL BIT(9) BIT 54 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VUSB_SEL BIT(8) BIT 55 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VSIM_SEL BIT(7) BIT 56 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VRFREF_SEL BIT(6) BIT 57 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VPLL_SEL BIT(5) BIT 58 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VFUSE_SEL BIT(4) BIT 59 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VCSI_SEL BIT(3) BIT 60 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_SPARE_14_2 BIT(2) BIT 61 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VWLAN2_SEL BIT(1) BIT 62 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VRF2_SEL BIT(0) BIT 65 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VAUDIO_SEL BIT(0) BIT 73 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_AUDIO_LOW_PWR BIT(6) BIT 74 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_AUD_LOWPWR_SPEED BIT(5) BIT 75 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VAUDIOPRISTBY BIT(4) BIT 76 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VAUDIO_MODE1 BIT(2) BIT 77 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_VAUDIO_MODE0 BIT(1) BIT 78 drivers/regulator/cpcap-regulator.c #define CPCAP_BIT_V_AUDIO_EN BIT(0) BIT 90 drivers/regulator/cpcap-regulator.c #define CPCAP_REG_OFF_MODE_SEC BIT(15) BIT 899 drivers/regulator/da9062-regulator.c if (BIT(regl->info->oc_event.lsb) & bits) { BIT 610 drivers/regulator/da9063-regulator.c if (BIT(regl->info->oc_event.lsb) & bits) { BIT 47 drivers/regulator/fan53555.c #define CTL_MODE_VSEL0_MODE BIT(0) BIT 48 drivers/regulator/fan53555.c #define CTL_MODE_VSEL1_MODE BIT(1) BIT 122 drivers/regulator/hi655x-regulator.c .enable_mask = BIT(cmask), \ BIT 144 drivers/regulator/hi655x-regulator.c .enable_mask = BIT(cmask), \ BIT 65 drivers/regulator/lp3972.c #define LP3972_OEN3_L1EN BIT(0) BIT 66 drivers/regulator/lp3972.c #define LP3972_OVER2_LDO2_EN BIT(2) BIT 67 drivers/regulator/lp3972.c #define LP3972_OVER2_LDO3_EN BIT(3) BIT 68 drivers/regulator/lp3972.c #define LP3972_OVER2_LDO4_EN BIT(4) BIT 69 drivers/regulator/lp3972.c #define LP3972_OVER1_S_EN BIT(2) BIT 49 drivers/regulator/lp872x.c #define LP872X_EN_LDO1_M BIT(0) BIT 50 drivers/regulator/lp872x.c #define LP872X_EN_LDO2_M BIT(1) BIT 51 drivers/regulator/lp872x.c #define LP872X_EN_LDO3_M BIT(2) BIT 52 drivers/regulator/lp872x.c #define LP872X_EN_LDO4_M BIT(3) BIT 53 drivers/regulator/lp872x.c #define LP872X_EN_LDO5_M BIT(4) BIT 57 drivers/regulator/lp872x.c #define LP8720_TIMESTEP_M BIT(0) BIT 58 drivers/regulator/lp872x.c #define LP8720_EXT_DVS_M BIT(2) BIT 60 drivers/regulator/lp872x.c #define LP8720_BUCK_FPWM_M BIT(5) BIT 61 drivers/regulator/lp872x.c #define LP8720_EN_BUCK_M BIT(5) /* Addr 08h */ BIT 62 drivers/regulator/lp872x.c #define LP8720_DVS_SEL_M BIT(7) BIT 67 drivers/regulator/lp872x.c #define LP8725_BUCK1_EN_M BIT(0) BIT 68 drivers/regulator/lp872x.c #define LP8725_DVS1_M BIT(2) BIT 69 drivers/regulator/lp872x.c #define LP8725_DVS2_M BIT(3) BIT 70 drivers/regulator/lp872x.c #define LP8725_BUCK2_EN_M BIT(4) BIT 74 drivers/regulator/lp872x.c #define LP8725_BUCK1_FPWM_M BIT(1) BIT 76 drivers/regulator/lp872x.c #define LP8725_BUCK2_FPWM_M BIT(5) BIT 77 drivers/regulator/lp872x.c #define LP8725_EN_LILO1_M BIT(5) /* Addr 0Dh */ BIT 78 drivers/regulator/lp872x.c #define LP8725_EN_LILO2_M BIT(6) BIT 91 drivers/regulator/lp872x.c #define LP8725_DEFAULT_DVS BIT(2) BIT 31 drivers/regulator/lp8755.c #define LP8755_BUCK_EN_M BIT(7) BIT 35 drivers/regulator/lp8788-buck.c #define LP8788_EN_BUCK1_M BIT(0) /* Addr 0Ch */ BIT 36 drivers/regulator/lp8788-buck.c #define LP8788_EN_BUCK2_M BIT(1) BIT 37 drivers/regulator/lp8788-buck.c #define LP8788_EN_BUCK3_M BIT(2) BIT 38 drivers/regulator/lp8788-buck.c #define LP8788_EN_BUCK4_M BIT(3) BIT 45 drivers/regulator/lp8788-buck.c #define LP8788_BUCK1_DVS_I2C BIT(2) BIT 46 drivers/regulator/lp8788-buck.c #define LP8788_BUCK2_DVS_I2C BIT(6) BIT 52 drivers/regulator/lp8788-buck.c #define LP8788_FPWM_BUCK1_M BIT(0) /* Addr 2Dh */ BIT 54 drivers/regulator/lp8788-buck.c #define LP8788_FPWM_BUCK2_M BIT(1) BIT 56 drivers/regulator/lp8788-buck.c #define LP8788_FPWM_BUCK3_M BIT(2) BIT 58 drivers/regulator/lp8788-buck.c #define LP8788_FPWM_BUCK4_M BIT(3) BIT 48 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO1_M BIT(0) /* Addr 0Dh ~ 0Fh */ BIT 49 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO2_M BIT(1) BIT 50 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO3_M BIT(2) BIT 51 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO4_M BIT(3) BIT 52 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO5_M BIT(4) BIT 53 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO6_M BIT(5) BIT 54 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO7_M BIT(6) BIT 55 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO8_M BIT(7) BIT 56 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO9_M BIT(0) BIT 57 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO10_M BIT(1) BIT 58 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO11_M BIT(2) BIT 59 drivers/regulator/lp8788-ldo.c #define LP8788_EN_DLDO12_M BIT(3) BIT 60 drivers/regulator/lp8788-ldo.c #define LP8788_EN_ALDO1_M BIT(4) BIT 61 drivers/regulator/lp8788-ldo.c #define LP8788_EN_ALDO2_M BIT(5) BIT 62 drivers/regulator/lp8788-ldo.c #define LP8788_EN_ALDO3_M BIT(6) BIT 63 drivers/regulator/lp8788-ldo.c #define LP8788_EN_ALDO4_M BIT(7) BIT 64 drivers/regulator/lp8788-ldo.c #define LP8788_EN_ALDO5_M BIT(0) BIT 65 drivers/regulator/lp8788-ldo.c #define LP8788_EN_ALDO6_M BIT(1) BIT 66 drivers/regulator/lp8788-ldo.c #define LP8788_EN_ALDO7_M BIT(2) BIT 67 drivers/regulator/lp8788-ldo.c #define LP8788_EN_ALDO8_M BIT(3) BIT 68 drivers/regulator/lp8788-ldo.c #define LP8788_EN_ALDO9_M BIT(4) BIT 69 drivers/regulator/lp8788-ldo.c #define LP8788_EN_ALDO10_M BIT(5) BIT 70 drivers/regulator/lp8788-ldo.c #define LP8788_EN_SEL_DLDO911_M BIT(0) /* Addr 10h */ BIT 71 drivers/regulator/lp8788-ldo.c #define LP8788_EN_SEL_DLDO7_M BIT(1) BIT 72 drivers/regulator/lp8788-ldo.c #define LP8788_EN_SEL_ALDO7_M BIT(2) BIT 73 drivers/regulator/lp8788-ldo.c #define LP8788_EN_SEL_ALDO5_M BIT(3) BIT 74 drivers/regulator/lp8788-ldo.c #define LP8788_EN_SEL_ALDO234_M BIT(4) BIT 75 drivers/regulator/lp8788-ldo.c #define LP8788_EN_SEL_ALDO1_M BIT(5) BIT 37 drivers/regulator/ltc3589.c #define LTC3589_IRQSTAT_PGOOD_TIMEOUT BIT(3) BIT 38 drivers/regulator/ltc3589.c #define LTC3589_IRQSTAT_UNDERVOLT_WARN BIT(4) BIT 39 drivers/regulator/ltc3589.c #define LTC3589_IRQSTAT_UNDERVOLT_FAULT BIT(5) BIT 40 drivers/regulator/ltc3589.c #define LTC3589_IRQSTAT_THERMAL_WARN BIT(6) BIT 41 drivers/regulator/ltc3589.c #define LTC3589_IRQSTAT_THERMAL_FAULT BIT(7) BIT 43 drivers/regulator/ltc3589.c #define LTC3589_OVEN_SW1 BIT(0) BIT 44 drivers/regulator/ltc3589.c #define LTC3589_OVEN_SW2 BIT(1) BIT 45 drivers/regulator/ltc3589.c #define LTC3589_OVEN_SW3 BIT(2) BIT 46 drivers/regulator/ltc3589.c #define LTC3589_OVEN_BB_OUT BIT(3) BIT 47 drivers/regulator/ltc3589.c #define LTC3589_OVEN_LDO2 BIT(4) BIT 48 drivers/regulator/ltc3589.c #define LTC3589_OVEN_LDO3 BIT(5) BIT 49 drivers/regulator/ltc3589.c #define LTC3589_OVEN_LDO4 BIT(6) BIT 50 drivers/regulator/ltc3589.c #define LTC3589_OVEN_SW_CTRL BIT(7) BIT 52 drivers/regulator/ltc3589.c #define LTC3589_VCCR_SW1_GO BIT(0) BIT 53 drivers/regulator/ltc3589.c #define LTC3589_VCCR_SW2_GO BIT(2) BIT 54 drivers/regulator/ltc3589.c #define LTC3589_VCCR_SW3_GO BIT(4) BIT 55 drivers/regulator/ltc3589.c #define LTC3589_VCCR_LDO2_GO BIT(6) BIT 45 drivers/regulator/ltc3676.c #define LTC3676_DVBxA_REF_SELECT BIT(5) BIT 46 drivers/regulator/ltc3676.c #define LTC3676_DVBxB_PGOOD_MASK BIT(5) BIT 48 drivers/regulator/ltc3676.c #define LTC3676_IRQSTAT_PGOOD_TIMEOUT BIT(3) BIT 49 drivers/regulator/ltc3676.c #define LTC3676_IRQSTAT_UNDERVOLT_WARN BIT(4) BIT 50 drivers/regulator/ltc3676.c #define LTC3676_IRQSTAT_UNDERVOLT_FAULT BIT(5) BIT 51 drivers/regulator/ltc3676.c #define LTC3676_IRQSTAT_THERMAL_WARN BIT(6) BIT 52 drivers/regulator/ltc3676.c #define LTC3676_IRQSTAT_THERMAL_FAULT BIT(7) BIT 19 drivers/regulator/max77650-regulator.c #define MAX77650_REGULATOR_DISABLED BIT(2) BIT 26 drivers/regulator/max77650-regulator.c #define MAX77650_REGULATOR_AD_MASK BIT(3) BIT 28 drivers/regulator/max77650-regulator.c #define MAX77650_REGULATOR_AD_ENABLED BIT(3) BIT 57 drivers/regulator/max8973-regulator.c #define MAX8973_VOUT_ENABLE BIT(7) BIT 64 drivers/regulator/max8973-regulator.c #define MAX8973_SNS_ENABLE BIT(7) BIT 65 drivers/regulator/max8973-regulator.c #define MAX8973_FPWM_EN_M BIT(6) BIT 66 drivers/regulator/max8973-regulator.c #define MAX8973_NFSR_ENABLE BIT(5) BIT 67 drivers/regulator/max8973-regulator.c #define MAX8973_AD_ENABLE BIT(4) BIT 68 drivers/regulator/max8973-regulator.c #define MAX8973_BIAS_ENABLE BIT(3) BIT 69 drivers/regulator/max8973-regulator.c #define MAX8973_FREQSHIFT_9PER BIT(2) BIT 78 drivers/regulator/max8973-regulator.c #define MAX8973_WDTMR_ENABLE BIT(6) BIT 79 drivers/regulator/max8973-regulator.c #define MAX8973_DISCH_ENBABLE BIT(5) BIT 80 drivers/regulator/max8973-regulator.c #define MAX8973_FT_ENABLE BIT(4) BIT 81 drivers/regulator/max8973-regulator.c #define MAX77621_T_JUNCTION_120 BIT(7) BIT 101 drivers/regulator/max8973-regulator.c #define MAX77621_CHIPID_TJINT_S BIT(0) BIT 25 drivers/regulator/mcp16502.c #define MCP16502_FLT BIT(7) BIT 26 drivers/regulator/mcp16502.c #define MCP16502_ENS BIT(0) BIT 69 drivers/regulator/mcp16502.c #define MCP16502_MODE_FPWM BIT(6) BIT 72 drivers/regulator/mcp16502.c #define MCP16502_EN BIT(7) BIT 73 drivers/regulator/mcp16502.c #define MCP16502_MODE BIT(6) BIT 55 drivers/regulator/mt6323-regulator.c .enable_mask = BIT(0), \ BIT 57 drivers/regulator/mt6323-regulator.c .qi = BIT(13), \ BIT 60 drivers/regulator/mt6323-regulator.c .vselctrl_mask = BIT(1), \ BIT 78 drivers/regulator/mt6323-regulator.c .enable_mask = BIT(enbit), \ BIT 80 drivers/regulator/mt6323-regulator.c .qi = BIT(15), \ BIT 97 drivers/regulator/mt6323-regulator.c .enable_mask = BIT(enbit), \ BIT 100 drivers/regulator/mt6323-regulator.c .qi = BIT(15), \ BIT 57 drivers/regulator/mt6358-regulator.c .enable_mask = BIT(0), \ BIT 61 drivers/regulator/mt6358-regulator.c .qi = BIT(0), \ BIT 66 drivers/regulator/mt6358-regulator.c .modeset_mask = BIT(_modeset_shift), \ BIT 86 drivers/regulator/mt6358-regulator.c .enable_mask = BIT(enbit), \ BIT 89 drivers/regulator/mt6358-regulator.c .qi = BIT(15), \ BIT 112 drivers/regulator/mt6358-regulator.c .enable_mask = BIT(0), \ BIT 118 drivers/regulator/mt6358-regulator.c .qi = BIT(0), \ BIT 133 drivers/regulator/mt6358-regulator.c .enable_mask = BIT(enbit), \ BIT 137 drivers/regulator/mt6358-regulator.c .qi = BIT(15), \ BIT 108 drivers/regulator/mt6380-regulator.c .enable_mask = BIT(enbit), \ BIT 130 drivers/regulator/mt6380-regulator.c .enable_mask = BIT(enbit), \ BIT 148 drivers/regulator/mt6380-regulator.c .enable_mask = BIT(enbit), \ BIT 57 drivers/regulator/mt6397-regulator.c .enable_mask = BIT(0), \ BIT 59 drivers/regulator/mt6397-regulator.c .qi = BIT(13), \ BIT 62 drivers/regulator/mt6397-regulator.c .vselctrl_mask = BIT(1), \ BIT 64 drivers/regulator/mt6397-regulator.c .modeset_mask = BIT(_modeset_shift), \ BIT 83 drivers/regulator/mt6397-regulator.c .enable_mask = BIT(enbit), \ BIT 85 drivers/regulator/mt6397-regulator.c .qi = BIT(15), \ BIT 99 drivers/regulator/mt6397-regulator.c .enable_mask = BIT(enbit), \ BIT 102 drivers/regulator/mt6397-regulator.c .qi = BIT(15), \ BIT 74 drivers/regulator/pbias-regulator.c .enable = BIT(1), BIT 75 drivers/regulator/pbias-regulator.c .enable_mask = BIT(1), BIT 76 drivers/regulator/pbias-regulator.c .vmode = BIT(0), BIT 85 drivers/regulator/pbias-regulator.c .enable = BIT(9), BIT 86 drivers/regulator/pbias-regulator.c .enable_mask = BIT(9), BIT 87 drivers/regulator/pbias-regulator.c .vmode = BIT(8), BIT 95 drivers/regulator/pbias-regulator.c .enable = BIT(26) | BIT(22), BIT 96 drivers/regulator/pbias-regulator.c .enable_mask = BIT(26) | BIT(25) | BIT(22), BIT 97 drivers/regulator/pbias-regulator.c .disable_val = BIT(25), BIT 98 drivers/regulator/pbias-regulator.c .vmode = BIT(21), BIT 106 drivers/regulator/pbias-regulator.c .enable = BIT(27) | BIT(26), BIT 107 drivers/regulator/pbias-regulator.c .enable_mask = BIT(27) | BIT(25) | BIT(26), BIT 108 drivers/regulator/pbias-regulator.c .disable_val = BIT(25), BIT 109 drivers/regulator/pbias-regulator.c .vmode = BIT(21), BIT 20 drivers/regulator/pfuze100-regulator.c #define PFUZE_FLAG_DISABLE_SW BIT(1) BIT 59 drivers/regulator/pfuze100-regulator.c #define PFUZE100_VGENxLPWR BIT(6) BIT 60 drivers/regulator/pfuze100-regulator.c #define PFUZE100_VGENxSTBY BIT(5) BIT 76 drivers/regulator/rc5t583-regulator.c .enable_mask = BIT(_en_bit), \ BIT 51 drivers/regulator/rk808-regulator.c #define RK808_DVS2_POL BIT(2) BIT 52 drivers/regulator/rk808-regulator.c #define RK808_DVS1_POL BIT(1) BIT 66 drivers/regulator/rk808-regulator.c #define ENABLE_MASK(id) (BIT(id) | BIT(4 + (id))) BIT 67 drivers/regulator/rk808-regulator.c #define DISABLE_VAL(id) (BIT(4 + (id))) BIT 506 drivers/regulator/rk808-regulator.c msk = BIT(id_slp % 8); BIT 769 drivers/regulator/rk808-regulator.c .enable_mask = BIT(0), BIT 785 drivers/regulator/rk808-regulator.c .enable_mask = BIT(1), BIT 797 drivers/regulator/rk808-regulator.c .enable_mask = BIT(2), BIT 803 drivers/regulator/rk808-regulator.c RK805_DCDC_EN_REG, BIT(3), 0), BIT 807 drivers/regulator/rk808-regulator.c BIT(0), 400), BIT 810 drivers/regulator/rk808-regulator.c BIT(1), 400), BIT 813 drivers/regulator/rk808-regulator.c BIT(2), 400), BIT 831 drivers/regulator/rk808-regulator.c .enable_mask = BIT(0), BIT 847 drivers/regulator/rk808-regulator.c .enable_mask = BIT(1), BIT 859 drivers/regulator/rk808-regulator.c .enable_mask = BIT(2), BIT 864 drivers/regulator/rk808-regulator.c RK808_DCDC_EN_REG, BIT(3), 0), BIT 867 drivers/regulator/rk808-regulator.c BIT(0), 400), BIT 870 drivers/regulator/rk808-regulator.c BIT(1), 400), BIT 885 drivers/regulator/rk808-regulator.c .enable_mask = BIT(2), BIT 891 drivers/regulator/rk808-regulator.c BIT(3), 400), BIT 894 drivers/regulator/rk808-regulator.c BIT(4), 400), BIT 897 drivers/regulator/rk808-regulator.c BIT(5), 400), BIT 900 drivers/regulator/rk808-regulator.c BIT(6), 400), BIT 903 drivers/regulator/rk808-regulator.c BIT(7), 400), BIT 905 drivers/regulator/rk808-regulator.c RK808_DCDC_EN_REG, BIT(5)), BIT 907 drivers/regulator/rk808-regulator.c RK808_DCDC_EN_REG, BIT(6)), BIT 1190 drivers/regulator/rk808-regulator.c .enable_mask = BIT(0), BIT 1206 drivers/regulator/rk808-regulator.c .enable_mask = BIT(1), BIT 1218 drivers/regulator/rk808-regulator.c .enable_mask = BIT(2), BIT 1223 drivers/regulator/rk808-regulator.c RK818_DCDC_EN_REG, BIT(3), 0), BIT 1226 drivers/regulator/rk808-regulator.c RK818_DCDC_EN_REG, BIT(4), 0), BIT 1229 drivers/regulator/rk808-regulator.c BIT(0), 400), BIT 1232 drivers/regulator/rk808-regulator.c BIT(1), 400), BIT 1247 drivers/regulator/rk808-regulator.c .enable_mask = BIT(2), BIT 1253 drivers/regulator/rk808-regulator.c BIT(3), 400), BIT 1256 drivers/regulator/rk808-regulator.c BIT(4), 400), BIT 1259 drivers/regulator/rk808-regulator.c BIT(5), 400), BIT 1262 drivers/regulator/rk808-regulator.c BIT(6), 400), BIT 1265 drivers/regulator/rk808-regulator.c BIT(7), 400), BIT 1268 drivers/regulator/rk808-regulator.c RK818_DCDC_EN_REG, BIT(5), 400), BIT 1270 drivers/regulator/rk808-regulator.c RK818_DCDC_EN_REG, BIT(6)), BIT 1272 drivers/regulator/rk808-regulator.c RK818_H5V_EN_REG, BIT(0)), BIT 1274 drivers/regulator/rk808-regulator.c RK818_DCDC_EN_REG, BIT(7)), BIT 45 drivers/regulator/rn5t618-regulator.c REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500), BIT 46 drivers/regulator/rn5t618-regulator.c REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500), BIT 47 drivers/regulator/rn5t618-regulator.c REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500), BIT 48 drivers/regulator/rn5t618-regulator.c REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500), BIT 50 drivers/regulator/rn5t618-regulator.c REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000), BIT 51 drivers/regulator/rn5t618-regulator.c REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000), BIT 52 drivers/regulator/rn5t618-regulator.c REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000), BIT 53 drivers/regulator/rn5t618-regulator.c REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000), BIT 54 drivers/regulator/rn5t618-regulator.c REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000), BIT 56 drivers/regulator/rn5t618-regulator.c REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1200000, 3500000, 25000), BIT 57 drivers/regulator/rn5t618-regulator.c REG(LDORTC2, LDOEN2, BIT(5), LDORTC2DAC, 0x7f, 900000, 3500000, 25000), BIT 62 drivers/regulator/rn5t618-regulator.c REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500), BIT 63 drivers/regulator/rn5t618-regulator.c REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500), BIT 64 drivers/regulator/rn5t618-regulator.c REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500), BIT 66 drivers/regulator/rn5t618-regulator.c REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000), BIT 67 drivers/regulator/rn5t618-regulator.c REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000), BIT 68 drivers/regulator/rn5t618-regulator.c REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000), BIT 69 drivers/regulator/rn5t618-regulator.c REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000), BIT 70 drivers/regulator/rn5t618-regulator.c REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000), BIT 72 drivers/regulator/rn5t618-regulator.c REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1700000, 3500000, 25000), BIT 73 drivers/regulator/rn5t618-regulator.c REG(LDORTC2, LDOEN2, BIT(5), LDORTC2DAC, 0x7f, 900000, 3500000, 25000), BIT 78 drivers/regulator/rn5t618-regulator.c REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500), BIT 79 drivers/regulator/rn5t618-regulator.c REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500), BIT 80 drivers/regulator/rn5t618-regulator.c REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500), BIT 81 drivers/regulator/rn5t618-regulator.c REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500), BIT 82 drivers/regulator/rn5t618-regulator.c REG(DCDC5, DC5CTL, BIT(0), DC5DAC, 0xff, 600000, 3500000, 12500), BIT 84 drivers/regulator/rn5t618-regulator.c REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000), BIT 85 drivers/regulator/rn5t618-regulator.c REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000), BIT 86 drivers/regulator/rn5t618-regulator.c REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 900000, 3500000, 25000), BIT 87 drivers/regulator/rn5t618-regulator.c REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000), BIT 88 drivers/regulator/rn5t618-regulator.c REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 600000, 3500000, 25000), BIT 89 drivers/regulator/rn5t618-regulator.c REG(LDO6, LDOEN1, BIT(5), LDO6DAC, 0x7f, 600000, 3500000, 25000), BIT 90 drivers/regulator/rn5t618-regulator.c REG(LDO7, LDOEN1, BIT(6), LDO7DAC, 0x7f, 900000, 3500000, 25000), BIT 91 drivers/regulator/rn5t618-regulator.c REG(LDO8, LDOEN1, BIT(7), LDO8DAC, 0x7f, 900000, 3500000, 25000), BIT 92 drivers/regulator/rn5t618-regulator.c REG(LDO9, LDOEN2, BIT(0), LDO9DAC, 0x7f, 900000, 3500000, 25000), BIT 93 drivers/regulator/rn5t618-regulator.c REG(LDO10, LDOEN2, BIT(0), LDO10DAC, 0x7f, 900000, 3500000, 25000), BIT 95 drivers/regulator/rn5t618-regulator.c REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1700000, 3500000, 25000), BIT 96 drivers/regulator/rn5t618-regulator.c REG(LDORTC2, LDOEN2, BIT(5), LDORTC2DAC, 0x7f, 900000, 3500000, 25000), BIT 41 drivers/regulator/sc2731-regulator.c #define SC2731_DCDC_CPU0_PD_MASK BIT(4) BIT 42 drivers/regulator/sc2731-regulator.c #define SC2731_DCDC_CPU1_PD_MASK BIT(3) BIT 43 drivers/regulator/sc2731-regulator.c #define SC2731_DCDC_RF_PD_MASK BIT(11) BIT 44 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMA0_PD_MASK BIT(0) BIT 45 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMA1_PD_MASK BIT(0) BIT 46 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMMOT_PD_MASK BIT(0) BIT 47 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_VLDO_PD_MASK BIT(0) BIT 48 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_EMMCCORE_PD_MASK BIT(0) BIT 49 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_SDCORE_PD_MASK BIT(0) BIT 50 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_SDIO_PD_MASK BIT(0) BIT 51 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_WIFIPA_PD_MASK BIT(0) BIT 52 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_USB33_PD_MASK BIT(0) BIT 53 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMD0_PD_MASK BIT(0) BIT 54 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMD1_PD_MASK BIT(0) BIT 55 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CON_PD_MASK BIT(0) BIT 56 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMIO_PD_MASK BIT(0) BIT 57 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_SRAM_PD_MASK BIT(0) BIT 232 drivers/regulator/slg51000-regulator.c .enable_mask = BIT(SLG51000_REGULATOR_##_id), \ BIT 15 drivers/regulator/stm32-booster.c #define STM32H7_SYSCFG_BOOSTE_MASK BIT(8) BIT 20 drivers/regulator/stm32-booster.c #define STM32MP1_SYSCFG_EN_BOOSTER_MASK BIT(8) BIT 20 drivers/regulator/stm32-pwr.c #define USB_3_3_EN BIT(24) BIT 21 drivers/regulator/stm32-pwr.c #define USB_3_3_RDY BIT(26) BIT 22 drivers/regulator/stm32-pwr.c #define REG_1_8_EN BIT(28) BIT 23 drivers/regulator/stm32-pwr.c #define REG_1_8_RDY BIT(29) BIT 24 drivers/regulator/stm32-pwr.c #define REG_1_1_EN BIT(30) BIT 25 drivers/regulator/stm32-pwr.c #define REG_1_1_RDY BIT(31) BIT 24 drivers/regulator/stm32-vrefbuf.c #define STM32_VRR BIT(3) BIT 25 drivers/regulator/stm32-vrefbuf.c #define STM32_HIZ BIT(1) BIT 26 drivers/regulator/stm32-vrefbuf.c #define STM32_ENVR BIT(0) BIT 354 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(0), BIT 356 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(0), BIT 361 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(1), BIT 363 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(1), BIT 368 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(2), BIT 370 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(2), BIT 375 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(3), BIT 377 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(3), BIT 382 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(0), BIT 384 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(0), BIT 389 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(1), BIT 391 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(1), BIT 396 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(2), BIT 398 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(2), BIT 403 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(3), BIT 405 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(3), BIT 410 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(4), BIT 412 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(4), BIT 417 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(5), BIT 419 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(5), BIT 424 drivers/regulator/stpmic1_regulator.c .mask_reset_mask = BIT(6), BIT 429 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(6), BIT 434 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(4), BIT 439 drivers/regulator/stpmic1_regulator.c .icc_mask = BIT(5), BIT 18 drivers/regulator/sy8106a-regulator.c #define SY8106A_DISABLE_REG BIT(0) BIT 23 drivers/regulator/sy8106a-regulator.c #define SY8106A_GO_BIT BIT(7) BIT 105 drivers/regulator/tps51632-regulator.c ret = regmap_write(tps->regmap, TPS51632_SLEW_REGS, BIT(bit)); BIT 52 drivers/regulator/tps62360-regulator.c #define FORCE_PWM_ENABLE BIT(7) BIT 265 drivers/regulator/tps62360-regulator.c ret = regmap_update_bits(tps->regmap, REG_RAMPCTRL, BIT(2), 0); BIT 284 drivers/regulator/tps62360-regulator.c tps->desc.ramp_delay = DIV_ROUND_UP(32000, BIT(ramp_ctrl)); BIT 498 drivers/regulator/tps62360-regulator.c st = regmap_update_bits(tps->regmap, REG_RAMPCTRL, BIT(2), BIT(2)); BIT 41 drivers/regulator/tps65023-regulator.c #define TPS65023_PGOODZ_PWRFAILZ BIT(7) BIT 42 drivers/regulator/tps65023-regulator.c #define TPS65023_PGOODZ_LOWBATTZ BIT(6) BIT 43 drivers/regulator/tps65023-regulator.c #define TPS65023_PGOODZ_VDCDC1 BIT(5) BIT 44 drivers/regulator/tps65023-regulator.c #define TPS65023_PGOODZ_VDCDC2 BIT(4) BIT 45 drivers/regulator/tps65023-regulator.c #define TPS65023_PGOODZ_VDCDC3 BIT(3) BIT 46 drivers/regulator/tps65023-regulator.c #define TPS65023_PGOODZ_LDO2 BIT(2) BIT 47 drivers/regulator/tps65023-regulator.c #define TPS65023_PGOODZ_LDO1 BIT(1) BIT 50 drivers/regulator/tps65023-regulator.c #define TPS65023_MASK_PWRFAILZ BIT(7) BIT 51 drivers/regulator/tps65023-regulator.c #define TPS65023_MASK_LOWBATTZ BIT(6) BIT 52 drivers/regulator/tps65023-regulator.c #define TPS65023_MASK_VDCDC1 BIT(5) BIT 53 drivers/regulator/tps65023-regulator.c #define TPS65023_MASK_VDCDC2 BIT(4) BIT 54 drivers/regulator/tps65023-regulator.c #define TPS65023_MASK_VDCDC3 BIT(3) BIT 55 drivers/regulator/tps65023-regulator.c #define TPS65023_MASK_LDO2 BIT(2) BIT 56 drivers/regulator/tps65023-regulator.c #define TPS65023_MASK_LDO1 BIT(1) BIT 59 drivers/regulator/tps65023-regulator.c #define TPS65023_REG_CTRL_VDCDC1_EN BIT(5) BIT 60 drivers/regulator/tps65023-regulator.c #define TPS65023_REG_CTRL_VDCDC2_EN BIT(4) BIT 61 drivers/regulator/tps65023-regulator.c #define TPS65023_REG_CTRL_VDCDC3_EN BIT(3) BIT 62 drivers/regulator/tps65023-regulator.c #define TPS65023_REG_CTRL_LDO2_EN BIT(2) BIT 63 drivers/regulator/tps65023-regulator.c #define TPS65023_REG_CTRL_LDO1_EN BIT(1) BIT 66 drivers/regulator/tps65023-regulator.c #define TPS65023_REG_CTRL2_GO BIT(7) BIT 67 drivers/regulator/tps65023-regulator.c #define TPS65023_REG_CTRL2_CORE_ADJ BIT(6) BIT 68 drivers/regulator/tps65023-regulator.c #define TPS65023_REG_CTRL2_DCDC2 BIT(2) BIT 69 drivers/regulator/tps65023-regulator.c #define TPS65023_REG_CTRL2_DCDC1 BIT(1) BIT 70 drivers/regulator/tps65023-regulator.c #define TPS65023_REG_CTRL2_DCDC3 BIT(0) BIT 127 drivers/regulator/tps65086-regulator.c BUCK_VID_MASK, TPS65086_BUCK123CTRL, BIT(0), BIT 129 drivers/regulator/tps65086-regulator.c BIT(0)), BIT 131 drivers/regulator/tps65086-regulator.c BUCK_VID_MASK, TPS65086_BUCK123CTRL, BIT(1), BIT 133 drivers/regulator/tps65086-regulator.c BIT(0)), BIT 135 drivers/regulator/tps65086-regulator.c BUCK_VID_MASK, TPS65086_BUCK123CTRL, BIT(2), BIT 137 drivers/regulator/tps65086-regulator.c BIT(0)), BIT 139 drivers/regulator/tps65086-regulator.c BUCK_VID_MASK, TPS65086_BUCK4CTRL, BIT(0), BIT 141 drivers/regulator/tps65086-regulator.c BIT(0)), BIT 143 drivers/regulator/tps65086-regulator.c BUCK_VID_MASK, TPS65086_BUCK5CTRL, BIT(0), BIT 145 drivers/regulator/tps65086-regulator.c BIT(0)), BIT 147 drivers/regulator/tps65086-regulator.c BUCK_VID_MASK, TPS65086_BUCK6CTRL, BIT(0), BIT 149 drivers/regulator/tps65086-regulator.c BIT(0)), BIT 151 drivers/regulator/tps65086-regulator.c VDOA1_VID_MASK, TPS65086_LDOA1CTRL, BIT(0), BIT 154 drivers/regulator/tps65086-regulator.c VDOA23_VID_MASK, TPS65086_LDOA2CTRL, BIT(0), BIT 157 drivers/regulator/tps65086-regulator.c VDOA23_VID_MASK, TPS65086_LDOA3CTRL, BIT(0), BIT 159 drivers/regulator/tps65086-regulator.c TPS65086_SWITCH("SWA1", "swa1", SWA1, TPS65086_SWVTT_EN, BIT(5)), BIT 160 drivers/regulator/tps65086-regulator.c TPS65086_SWITCH("SWB1", "swb1", SWB1, TPS65086_SWVTT_EN, BIT(6)), BIT 161 drivers/regulator/tps65086-regulator.c TPS65086_SWITCH("SWB2", "swb2", SWB2, TPS65086_SWVTT_EN, BIT(7)), BIT 162 drivers/regulator/tps65086-regulator.c TPS65086_SWITCH("VTT", "vtt", VTT, TPS65086_SWVTT_EN, BIT(4)), BIT 108 drivers/regulator/tps65090-regulator.c if (!(control & BIT(CTRL_TO_BIT))) BIT 113 drivers/regulator/tps65090-regulator.c if (!(control & BIT(CTRL_PG_BIT))) BIT 207 drivers/regulator/tps65090-regulator.c tps65090_REG_FIXEDV(DCDC1, "vsys1", 0x0C, BIT(CTRL_EN_BIT), 5000000, BIT 209 drivers/regulator/tps65090-regulator.c tps65090_REG_FIXEDV(DCDC2, "vsys2", 0x0D, BIT(CTRL_EN_BIT), 3300000, BIT 211 drivers/regulator/tps65090-regulator.c tps65090_REG_SWITCH(DCDC3, "vsys3", 0x0E, BIT(CTRL_EN_BIT), BIT 215 drivers/regulator/tps65090-regulator.c BIT(CTRL_EN_BIT) | BIT(CTRL_PG_BIT), BIT 218 drivers/regulator/tps65090-regulator.c BIT(CTRL_EN_BIT) | BIT(CTRL_PG_BIT), BIT 221 drivers/regulator/tps65090-regulator.c BIT(CTRL_EN_BIT) | BIT(CTRL_PG_BIT), BIT 224 drivers/regulator/tps65090-regulator.c BIT(CTRL_EN_BIT) | BIT(CTRL_PG_BIT), BIT 227 drivers/regulator/tps65090-regulator.c BIT(CTRL_EN_BIT) | BIT(CTRL_PG_BIT), BIT 230 drivers/regulator/tps65090-regulator.c BIT(CTRL_EN_BIT) | BIT(CTRL_PG_BIT), BIT 233 drivers/regulator/tps65090-regulator.c BIT(CTRL_EN_BIT) | BIT(CTRL_PG_BIT), BIT 40 drivers/regulator/tps65132-regulator.c #define TPS65132_REG_APPS_DIS_VPOS BIT(0) BIT 41 drivers/regulator/tps65132-regulator.c #define TPS65132_REG_APPS_DIS_VNEG BIT(1) BIT 49 drivers/regulator/tps6524x-regulator.c #define DCDCDCDC1_PG_MSK BIT(1) BIT 51 drivers/regulator/tps6524x-regulator.c #define DCDCDCDC2_PG_MSK BIT(3) BIT 53 drivers/regulator/tps6524x-regulator.c #define DCDCDCDC3_PG_MSK BIT(5) BIT 62 drivers/regulator/tps6524x-regulator.c #define USB_IWARN_SD BIT(6) BIT 63 drivers/regulator/tps6524x-regulator.c #define USB_FAST_LOOP BIT(7) BIT 66 drivers/regulator/tps6524x-regulator.c #define ALARM_LDO1 BIT(0) BIT 67 drivers/regulator/tps6524x-regulator.c #define ALARM_DCDC1 BIT(1) BIT 68 drivers/regulator/tps6524x-regulator.c #define ALARM_DCDC2 BIT(2) BIT 69 drivers/regulator/tps6524x-regulator.c #define ALARM_DCDC3 BIT(3) BIT 70 drivers/regulator/tps6524x-regulator.c #define ALARM_LDO2 BIT(4) BIT 71 drivers/regulator/tps6524x-regulator.c #define ALARM_USB_WARN BIT(5) BIT 72 drivers/regulator/tps6524x-regulator.c #define ALARM_USB_ALARM BIT(6) BIT 73 drivers/regulator/tps6524x-regulator.c #define ALARM_LCD BIT(9) BIT 74 drivers/regulator/tps6524x-regulator.c #define ALARM_TEMP_WARM BIT(10) BIT 75 drivers/regulator/tps6524x-regulator.c #define ALARM_TEMP_HOT BIT(11) BIT 76 drivers/regulator/tps6524x-regulator.c #define ALARM_NRST BIT(14) BIT 77 drivers/regulator/tps6524x-regulator.c #define ALARM_POWERUP BIT(15) BIT 80 drivers/regulator/tps6524x-regulator.c #define INT_LDO1 BIT(0) BIT 81 drivers/regulator/tps6524x-regulator.c #define INT_DCDC1 BIT(1) BIT 82 drivers/regulator/tps6524x-regulator.c #define INT_DCDC2 BIT(2) BIT 83 drivers/regulator/tps6524x-regulator.c #define INT_DCDC3 BIT(3) BIT 84 drivers/regulator/tps6524x-regulator.c #define INT_LDO2 BIT(4) BIT 85 drivers/regulator/tps6524x-regulator.c #define INT_USB_WARN BIT(5) BIT 86 drivers/regulator/tps6524x-regulator.c #define INT_USB_ALARM BIT(6) BIT 87 drivers/regulator/tps6524x-regulator.c #define INT_LCD BIT(9) BIT 88 drivers/regulator/tps6524x-regulator.c #define INT_TEMP_WARM BIT(10) BIT 89 drivers/regulator/tps6524x-regulator.c #define INT_TEMP_HOT BIT(11) BIT 90 drivers/regulator/tps6524x-regulator.c #define INT_GLOBAL_EN BIT(15) BIT 93 drivers/regulator/tps6524x-regulator.c #define STATUS_LDO1 BIT(0) BIT 94 drivers/regulator/tps6524x-regulator.c #define STATUS_DCDC1 BIT(1) BIT 95 drivers/regulator/tps6524x-regulator.c #define STATUS_DCDC2 BIT(2) BIT 96 drivers/regulator/tps6524x-regulator.c #define STATUS_DCDC3 BIT(3) BIT 97 drivers/regulator/tps6524x-regulator.c #define STATUS_LDO2 BIT(4) BIT 98 drivers/regulator/tps6524x-regulator.c #define STATUS_USB_WARN BIT(5) BIT 99 drivers/regulator/tps6524x-regulator.c #define STATUS_USB_ALARM BIT(6) BIT 100 drivers/regulator/tps6524x-regulator.c #define STATUS_LCD BIT(9) BIT 101 drivers/regulator/tps6524x-regulator.c #define STATUS_TEMP_WARM BIT(10) BIT 102 drivers/regulator/tps6524x-regulator.c #define STATUS_TEMP_HOT BIT(11) BIT 114 drivers/regulator/tps6524x-regulator.c #define CMD_WRITE(reg) (BIT(5) | (reg) << 6) BIT 115 drivers/regulator/tps6524x-regulator.c #define STAT_CLK BIT(3) BIT 116 drivers/regulator/tps6524x-regulator.c #define STAT_WRITE BIT(2) BIT 117 drivers/regulator/tps6524x-regulator.c #define STAT_INVALID BIT(1) BIT 118 drivers/regulator/tps6524x-regulator.c #define STAT_WP BIT(0) BIT 223 drivers/regulator/tps6586x-regulator.c ENA, 3, ENB, 3, TPS6586X_VCC2, BIT(6)), BIT 225 drivers/regulator/tps6586x-regulator.c ENC, 3, END, 3, TPS6586X_VCC1, BIT(6)), BIT 227 drivers/regulator/tps6586x-regulator.c ENA, 1, ENB, 1, TPS6586X_VCC1, BIT(2)), BIT 229 drivers/regulator/tps6586x-regulator.c ENA, 0, ENB, 0, TPS6586X_VCC1, BIT(0)), BIT 43 drivers/regulator/tps65912-regulator.c .enable_mask = BIT(7), \ BIT 24 drivers/regulator/tps80031-regulator.c #define DCDC_OFFSET_EN BIT(0) BIT 25 drivers/regulator/tps80031-regulator.c #define DCDC_EXTENDED_EN BIT(1) BIT 26 drivers/regulator/tps80031-regulator.c #define TRACK_MODE_ENABLE BIT(2) BIT 28 drivers/regulator/tps80031-regulator.c #define SMPS_MULTOFFSET_VIO BIT(1) BIT 29 drivers/regulator/tps80031-regulator.c #define SMPS_MULTOFFSET_SMPS1 BIT(3) BIT 30 drivers/regulator/tps80031-regulator.c #define SMPS_MULTOFFSET_SMPS2 BIT(4) BIT 31 drivers/regulator/tps80031-regulator.c #define SMPS_MULTOFFSET_SMPS3 BIT(6) BIT 32 drivers/regulator/tps80031-regulator.c #define SMPS_MULTOFFSET_SMPS4 BIT(0) BIT 39 drivers/regulator/tps80031-regulator.c #define MISC2_LDOUSB_IN_VSYS BIT(4) BIT 40 drivers/regulator/tps80031-regulator.c #define MISC2_LDOUSB_IN_PMID BIT(3) BIT 43 drivers/regulator/tps80031-regulator.c #define MISC2_LDO3_SEL_VIB_VAL BIT(0) BIT 46 drivers/regulator/tps80031-regulator.c #define BOOST_HW_PWR_EN BIT(5) BIT 47 drivers/regulator/tps80031-regulator.c #define BOOST_HW_PWR_EN_MASK BIT(5) BIT 49 drivers/regulator/tps80031-regulator.c #define OPA_MODE_EN BIT(6) BIT 50 drivers/regulator/tps80031-regulator.c #define OPA_MODE_EN_MASK BIT(6) BIT 624 drivers/regulator/tps80031-regulator.c ri->device_flags = smps_mult & BIT(5) ? TRACK_MODE_ENABLE : 0; BIT 109 drivers/regulator/twl-regulator.c #define P3_GRP_4030 BIT(7) /* "peripherals" */ BIT 110 drivers/regulator/twl-regulator.c #define P2_GRP_4030 BIT(6) /* secondary processor, modem, etc */ BIT 111 drivers/regulator/twl-regulator.c #define P1_GRP_4030 BIT(5) /* CPU/Linux */ BIT 113 drivers/regulator/twl-regulator.c #define P3_GRP_6030 BIT(2) /* secondary processor, modem, etc */ BIT 114 drivers/regulator/twl-regulator.c #define P2_GRP_6030 BIT(1) /* "peripherals" */ BIT 115 drivers/regulator/twl-regulator.c #define P1_GRP_6030 BIT(0) /* CPU/Linux */ BIT 127 drivers/regulator/twl-regulator.c #define PB_I2C_BUSY BIT(0) BIT 128 drivers/regulator/twl-regulator.c #define PB_I2C_BWEN BIT(1) BIT 240 drivers/regulator/twl-regulator.c return (state & BIT(3)) BIT 61 drivers/regulator/twl6030-regulator.c #define TWL6030_VREG_VOLTAGE_WR_S BIT(7) BIT 75 drivers/regulator/twl6030-regulator.c #define SMPS_OFFSET_EN BIT(0) BIT 76 drivers/regulator/twl6030-regulator.c #define SMPS_EXTENDED_EN BIT(1) BIT 77 drivers/regulator/twl6030-regulator.c #define TWL_6030_WARM_RESET BIT(3) BIT 82 drivers/regulator/twl6030-regulator.c #define SMPS_MULTOFFSET_SMPS4 BIT(0) BIT 83 drivers/regulator/twl6030-regulator.c #define SMPS_MULTOFFSET_VIO BIT(1) BIT 84 drivers/regulator/twl6030-regulator.c #define SMPS_MULTOFFSET_SMPS3 BIT(6) BIT 117 drivers/regulator/twl6030-regulator.c #define P3_GRP_6030 BIT(2) /* secondary processor, modem, etc */ BIT 118 drivers/regulator/twl6030-regulator.c #define P2_GRP_6030 BIT(1) /* "peripherals" */ BIT 119 drivers/regulator/twl6030-regulator.c #define P1_GRP_6030 BIT(0) /* CPU/Linux */ BIT 141 drivers/regulator/twl6030-regulator.c #define PB_I2C_BUSY BIT(0) BIT 142 drivers/regulator/twl6030-regulator.c #define PB_I2C_BWEN BIT(1) BIT 135 drivers/regulator/uniphier-regulator.c #define USB3VBUS_REG BIT(4) BIT 136 drivers/regulator/uniphier-regulator.c #define USB3VBUS_REG_EN BIT(3) BIT 32 drivers/remoteproc/da8xx_remoteproc.c #define SYSCFG_CHIPSIG0 BIT(0) BIT 33 drivers/remoteproc/da8xx_remoteproc.c #define SYSCFG_CHIPSIG1 BIT(1) BIT 34 drivers/remoteproc/da8xx_remoteproc.c #define SYSCFG_CHIPSIG2 BIT(2) BIT 35 drivers/remoteproc/da8xx_remoteproc.c #define SYSCFG_CHIPSIG3 BIT(3) BIT 36 drivers/remoteproc/da8xx_remoteproc.c #define SYSCFG_CHIPSIG4 BIT(4) BIT 19 drivers/remoteproc/imx_rproc.c #define IMX7D_ENABLE_M4 BIT(3) BIT 20 drivers/remoteproc/imx_rproc.c #define IMX7D_SW_M4P_RST BIT(2) BIT 21 drivers/remoteproc/imx_rproc.c #define IMX7D_SW_M4C_RST BIT(1) BIT 22 drivers/remoteproc/imx_rproc.c #define IMX7D_SW_M4C_NON_SCLR_RST BIT(0) BIT 34 drivers/remoteproc/imx_rproc.c #define IMX6SX_ENABLE_M4 BIT(22) BIT 35 drivers/remoteproc/imx_rproc.c #define IMX6SX_SW_M4P_RST BIT(12) BIT 36 drivers/remoteproc/imx_rproc.c #define IMX6SX_SW_M4C_NON_SCLR_RST BIT(4) BIT 37 drivers/remoteproc/imx_rproc.c #define IMX6SX_SW_M4C_RST BIT(3) BIT 62 drivers/remoteproc/imx_rproc.c #define ATT_OWN BIT(1) BIT 155 drivers/remoteproc/qcom_q6v5.c BIT(q6v5->stop_bit), BIT(q6v5->stop_bit)); BIT 159 drivers/remoteproc/qcom_q6v5.c qcom_smem_state_update_bits(q6v5->state, BIT(q6v5->stop_bit), 0); BIT 216 drivers/remoteproc/qcom_q6v5_adsp.c val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); BIT 74 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_STOP_CORE BIT(0) BIT 75 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_CORE_ARES BIT(1) BIT 76 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_BUS_ARES_ENABLE BIT(2) BIT 79 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_CLK_ENABLE BIT(1) BIT 82 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0) BIT 83 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1) BIT 84 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2) BIT 85 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_L2TAG_SLP_NRET_N BIT(16) BIT 86 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_ETB_SLP_NRET_N BIT(17) BIT 87 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_L2DATA_STBY_N BIT(18) BIT 88 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_SLP_RET_N BIT(19) BIT 89 drivers/remoteproc/qcom_q6v5_mss.c #define Q6SS_CLAMP_IO BIT(20) BIT 90 drivers/remoteproc/qcom_q6v5_mss.c #define QDSS_BHS_ON BIT(21) BIT 91 drivers/remoteproc/qcom_q6v5_mss.c #define QDSS_LDO_BYP BIT(22) BIT 94 drivers/remoteproc/qcom_q6v5_mss.c #define QDSP6v56_LDO_BYP BIT(25) BIT 95 drivers/remoteproc/qcom_q6v5_mss.c #define QDSP6v56_BHS_ON BIT(24) BIT 96 drivers/remoteproc/qcom_q6v5_mss.c #define QDSP6v56_CLAMP_WL BIT(21) BIT 97 drivers/remoteproc/qcom_q6v5_mss.c #define QDSP6v56_CLAMP_QMC_MEM BIT(22) BIT 368 drivers/remoteproc/qcom_q6v5_mss.c if (remote_owner && *current_perm == BIT(QCOM_SCM_VMID_MSS_MSA)) BIT 370 drivers/remoteproc/qcom_q6v5_mss.c if (!remote_owner && *current_perm == BIT(QCOM_SCM_VMID_HLOS)) BIT 479 drivers/remoteproc/qcom_q6v5_mss.c val, !(val & BIT(31)), 1, BIT 492 drivers/remoteproc/qcom_q6v5_mss.c val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); BIT 518 drivers/remoteproc/qcom_q6v5_mss.c val, !(val & BIT(31)), 1, BIT 548 drivers/remoteproc/qcom_q6v5_mss.c val |= BIT(i); BIT 683 drivers/remoteproc/qcom_q6v5_mss.c mdata_perm = BIT(QCOM_SCM_VMID_HLOS); BIT 1077 drivers/remoteproc/qcom_q6v5_mss.c unsigned long mask = BIT((unsigned long)segment->priv); BIT 1216 drivers/remoteproc/qcom_q6v5_mss.c qproc->dump_complete_mask |= BIT(i); BIT 1524 drivers/remoteproc/qcom_q6v5_mss.c qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS); BIT 1525 drivers/remoteproc/qcom_q6v5_mss.c qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS); BIT 35 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_STOP_CORE BIT(0) BIT 36 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_CORE_ARES BIT(1) BIT 37 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_BUS_ARES_ENABLE BIT(2) BIT 40 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_CLK_ENABLE BIT(1) BIT 43 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_L2DATA_STBY_N BIT(18) BIT 44 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_SLP_RET_N BIT(19) BIT 45 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_CLAMP_IO BIT(20) BIT 46 drivers/remoteproc/qcom_q6v5_wcss.c #define QDSS_BHS_ON BIT(21) BIT 49 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_LDO_BYP BIT(25) BIT 50 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_BHS_ON BIT(24) BIT 51 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_CLAMP_WL BIT(21) BIT 52 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_CLAMP_QMC_MEM BIT(22) BIT 64 drivers/remoteproc/qcom_q6v5_wcss.c #define BHS_EN_REST_ACK BIT(0) BIT 65 drivers/remoteproc/qcom_q6v5_wcss.c #define SSCAON_ENABLE BIT(13) BIT 66 drivers/remoteproc/qcom_q6v5_wcss.c #define SSCAON_BUS_EN BIT(15) BIT 114 drivers/remoteproc/qcom_q6v5_wcss.c val, !(val & BIT(31)), 1, BIT 143 drivers/remoteproc/qcom_q6v5_wcss.c val |= BIT(i); BIT 289 drivers/remoteproc/qcom_q6v5_wcss.c val |= BIT(1); BIT 350 drivers/remoteproc/qcom_q6v5_wcss.c val &= ~BIT(i); BIT 37 drivers/remoteproc/qcom_wcnss.c #define WCNSS_SPARE_NVBIN_DLND BIT(25) BIT 39 drivers/remoteproc/qcom_wcnss.c #define WCNSS_PMU_IRIS_XO_CFG BIT(3) BIT 40 drivers/remoteproc/qcom_wcnss.c #define WCNSS_PMU_IRIS_XO_EN BIT(4) BIT 41 drivers/remoteproc/qcom_wcnss.c #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5) BIT 42 drivers/remoteproc/qcom_wcnss.c #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */ BIT 44 drivers/remoteproc/qcom_wcnss.c #define WCNSS_PMU_IRIS_RESET BIT(7) BIT 45 drivers/remoteproc/qcom_wcnss.c #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */ BIT 46 drivers/remoteproc/qcom_wcnss.c #define WCNSS_PMU_IRIS_XO_READ BIT(9) BIT 47 drivers/remoteproc/qcom_wcnss.c #define WCNSS_PMU_IRIS_XO_READ_STS BIT(10) BIT 270 drivers/remoteproc/qcom_wcnss.c BIT(wcnss->stop_bit), BIT 271 drivers/remoteproc/qcom_wcnss.c BIT(wcnss->stop_bit)); BIT 279 drivers/remoteproc/qcom_wcnss.c BIT(wcnss->stop_bit), BIT 26 drivers/remoteproc/st_slim_rproc.c #define SLIM_EN_RUN BIT(0) BIT 29 drivers/remoteproc/st_slim_rproc.c #define SLIM_CLK_GATE_DIS BIT(0) BIT 30 drivers/remoteproc/st_slim_rproc.c #define SLIM_CLK_GATE_RESET BIT(2) BIT 44 drivers/remoteproc/st_slim_rproc.c #define SLIM_STBUS_SYNC_DIS BIT(0) BIT 52 drivers/reset/hisilicon/hi6220_reset.c return regmap_write(regmap, reg, BIT(offset)); BIT 64 drivers/reset/hisilicon/hi6220_reset.c return regmap_write(regmap, reg, BIT(offset)); BIT 78 drivers/reset/hisilicon/hi6220_reset.c return regmap_write(regmap, SC_MEDIA_RSTEN, BIT(idx)); BIT 87 drivers/reset/hisilicon/hi6220_reset.c return regmap_write(regmap, SC_MEDIA_RSTDIS, BIT(idx)); BIT 27 drivers/reset/hisilicon/reset-hi3660.c unsigned int mask = BIT(idx & 0x1f); BIT 36 drivers/reset/reset-ath79.c val |= BIT(id); BIT 38 drivers/reset/reset-ath79.c val &= ~BIT(id); BIT 66 drivers/reset/reset-ath79.c return !!(val & BIT(id)); BIT 34 drivers/reset/reset-axs10x.c writel(BIT(id), rst->regs_rst); BIT 41 drivers/reset/reset-berlin.c int mask = BIT(id & 0x1f); BIT 26 drivers/reset/reset-brcmstb.c #define SW_INIT_BIT(id) BIT((id) & 0x1f) BIT 31 drivers/reset/reset-hsdk.c BIT(16), /* APB_RST */ BIT 32 drivers/reset/reset-hsdk.c BIT(17), /* AXI_RST */ BIT 33 drivers/reset/reset-hsdk.c BIT(18), /* ETH_RST */ BIT 34 drivers/reset/reset-hsdk.c BIT(19), /* USB_RST */ BIT 35 drivers/reset/reset-hsdk.c BIT(20), /* SDIO_RST */ BIT 36 drivers/reset/reset-hsdk.c BIT(21), /* HDMI_RST */ BIT 37 drivers/reset/reset-hsdk.c BIT(22), /* GFX_RST */ BIT 38 drivers/reset/reset-hsdk.c BIT(25), /* DMAC_RST */ BIT 39 drivers/reset/reset-hsdk.c BIT(31), /* EBI_RST */ BIT 49 drivers/reset/reset-hsdk.c #define CGU_IP_SW_RESET_RESET BIT(0) BIT 57 drivers/reset/reset-imx7.c [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) }, BIT 58 drivers/reset/reset-imx7.c [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) }, BIT 59 drivers/reset/reset-imx7.c [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) }, BIT 60 drivers/reset/reset-imx7.c [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) }, BIT 61 drivers/reset/reset-imx7.c [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) }, BIT 62 drivers/reset/reset-imx7.c [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) }, BIT 63 drivers/reset/reset-imx7.c [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) }, BIT 64 drivers/reset/reset-imx7.c [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) }, BIT 65 drivers/reset/reset-imx7.c [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) }, BIT 66 drivers/reset/reset-imx7.c [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) }, BIT 67 drivers/reset/reset-imx7.c [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) }, BIT 68 drivers/reset/reset-imx7.c [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) }, BIT 69 drivers/reset/reset-imx7.c [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) }, BIT 70 drivers/reset/reset-imx7.c [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) }, BIT 71 drivers/reset/reset-imx7.c [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) }, BIT 72 drivers/reset/reset-imx7.c [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) }, BIT 73 drivers/reset/reset-imx7.c [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) }, BIT 74 drivers/reset/reset-imx7.c [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) }, BIT 75 drivers/reset/reset-imx7.c [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) }, BIT 76 drivers/reset/reset-imx7.c [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) }, BIT 77 drivers/reset/reset-imx7.c [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, BIT 78 drivers/reset/reset-imx7.c [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, BIT 79 drivers/reset/reset-imx7.c [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, BIT 80 drivers/reset/reset-imx7.c [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, BIT 81 drivers/reset/reset-imx7.c [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) }, BIT 82 drivers/reset/reset-imx7.c [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) }, BIT 149 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) }, BIT 150 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) }, BIT 151 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) }, BIT 152 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) }, BIT 153 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) }, BIT 154 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) }, BIT 155 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) }, BIT 156 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) }, BIT 157 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) }, BIT 158 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) }, BIT 159 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) }, BIT 160 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) }, BIT 161 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) }, BIT 162 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) }, BIT 163 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) }, BIT 164 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) }, BIT 165 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, BIT 166 drivers/reset/reset-imx7.c [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, BIT 167 drivers/reset/reset-imx7.c [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) }, BIT 168 drivers/reset/reset-imx7.c [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, BIT 169 drivers/reset/reset-imx7.c [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, BIT 170 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) }, BIT 171 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) }, BIT 172 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) }, BIT 173 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) }, BIT 174 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) }, BIT 176 drivers/reset/reset-imx7.c BIT(2) | BIT(1) }, BIT 177 drivers/reset/reset-imx7.c [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, BIT 178 drivers/reset/reset-imx7.c [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, BIT 179 drivers/reset/reset-imx7.c [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, BIT 180 drivers/reset/reset-imx7.c [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, BIT 181 drivers/reset/reset-imx7.c [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) }, BIT 182 drivers/reset/reset-imx7.c [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) }, BIT 183 drivers/reset/reset-imx7.c [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) }, BIT 185 drivers/reset/reset-imx7.c BIT(2) | BIT(1) }, BIT 186 drivers/reset/reset-imx7.c [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) }, BIT 187 drivers/reset/reset-imx7.c [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) }, BIT 188 drivers/reset/reset-imx7.c [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) }, BIT 189 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) }, BIT 190 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) }, BIT 191 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) }, BIT 192 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) }, BIT 193 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) }, BIT 194 drivers/reset/reset-imx7.c [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) }, BIT 195 drivers/reset/reset-imx7.c [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) }, BIT 196 drivers/reset/reset-imx7.c [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) }, BIT 197 drivers/reset/reset-imx7.c [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) }, BIT 198 drivers/reset/reset-imx7.c [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) }, BIT 199 drivers/reset/reset-imx7.c [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) }, BIT 200 drivers/reset/reset-imx7.c [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) }, BIT 47 drivers/reset/reset-lantiq.c return !!(val & BIT(status)); BIT 73 drivers/reset/reset-lantiq.c u32 val = assert ? BIT(set) : 0; BIT 76 drivers/reset/reset-lantiq.c ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(set), BIT 50 drivers/reset/reset-lpc18xx.c writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0); BIT 44 drivers/reset/reset-meson-audio-arb.c val &= ~BIT(arb->reset_bits[id]); BIT 46 drivers/reset/reset-meson-audio-arb.c val |= BIT(arb->reset_bits[id]); BIT 63 drivers/reset/reset-meson-audio-arb.c return !(val & BIT(arb->reset_bits[id])); BIT 145 drivers/reset/reset-meson-audio-arb.c writel(BIT(ARB_GENERAL_BIT), arb->regs); BIT 37 drivers/reset/reset-meson.c writel(BIT(offset), reg_addr); BIT 57 drivers/reset/reset-meson.c writel(reg & ~BIT(offset), reg_addr); BIT 59 drivers/reset/reset-meson.c writel(reg | BIT(offset), reg_addr); BIT 35 drivers/reset/reset-oxnas.c regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id)); BIT 37 drivers/reset/reset-oxnas.c regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id)); BIT 48 drivers/reset/reset-oxnas.c regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id)); BIT 59 drivers/reset/reset-oxnas.c regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id)); BIT 74 drivers/reset/reset-pistachio.c mask = BIT(shift); BIT 91 drivers/reset/reset-pistachio.c mask = BIT(shift); BIT 59 drivers/reset/reset-qcom-pdc.c BIT(sdm845_pdc_resets[idx].bit), BIT 60 drivers/reset/reset-qcom-pdc.c BIT(sdm845_pdc_resets[idx].bit)); BIT 69 drivers/reset/reset-qcom-pdc.c BIT(sdm845_pdc_resets[idx].bit), 0); BIT 45 drivers/reset/reset-simple.c reg |= BIT(offset); BIT 47 drivers/reset/reset-simple.c reg &= ~BIT(offset); BIT 78 drivers/reset/reset-simple.c return !(reg & BIT(offset)) ^ !data->status_active_low; BIT 40 drivers/reset/reset-stm32mp1.c writel(BIT(offset), addr); BIT 68 drivers/reset/reset-stm32mp1.c return !!(reg & BIT(offset)); BIT 89 drivers/reset/reset-ti-syscon.c mask = BIT(control->assert_bit); BIT 120 drivers/reset/reset-ti-syscon.c mask = BIT(control->deassert_bit); BIT 157 drivers/reset/reset-ti-syscon.c return !(reset_state & BIT(control->status_bit)) == BIT 20 drivers/reset/reset-uniphier.c #define UNIPHIER_RESET_ACTIVE_LOW BIT(0) BIT 265 drivers/reset/reset-uniphier.c mask = BIT(p->bit); BIT 311 drivers/reset/reset-uniphier.c asserted = !!(val & BIT(p->bit)); BIT 42 drivers/reset/reset-zynq.c BIT(offset), BIT 43 drivers/reset/reset-zynq.c BIT(offset)); BIT 59 drivers/reset/reset-zynq.c BIT(offset), BIT 60 drivers/reset/reset-zynq.c ~BIT(offset)); BIT 80 drivers/reset/reset-zynq.c return !!(reg & BIT(offset)); BIT 205 drivers/rpmsg/qcom_glink_native.c #define GLINK_FEATURE_INTENTLESS BIT(1) BIT 9 drivers/rpmsg/qcom_glink_native.h #define GLINK_FEATURE_INTENT_REUSE BIT(0) BIT 10 drivers/rpmsg/qcom_glink_native.h #define GLINK_FEATURE_MIGRATION BIT(1) BIT 11 drivers/rpmsg/qcom_glink_native.h #define GLINK_FEATURE_TRACER_PKT BIT(2) BIT 358 drivers/rpmsg/qcom_smd.c #define SMD_CHANNEL_FLAGS_STREAM BIT(8) BIT 359 drivers/rpmsg/qcom_smd.c #define SMD_CHANNEL_FLAGS_PACKET BIT(9) BIT 383 drivers/rpmsg/qcom_smd.c regmap_write(edge->ipc_regmap, edge->ipc_offset, BIT(edge->ipc_bit)); BIT 28 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */ BIT 29 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */ BIT 30 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */ BIT 31 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */ BIT 32 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */ BIT 33 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */ BIT 34 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL1_CAP BIT(7) BIT 37 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */ BIT 38 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL2_CTAIE BIT(1) /* Countdown timer A int. enable */ BIT 39 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL2_WTAIE BIT(2) /* Watchdog timer A int. enable */ BIT 40 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL2_AF BIT(3) /* Alarm interrupt status */ BIT 41 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL2_SF BIT(4) /* Second interrupt status */ BIT 42 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL2_CTBF BIT(5) /* Countdown timer B int. status */ BIT 43 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL2_CTAF BIT(6) /* Countdown timer A int. status */ BIT 44 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL2_WTAF BIT(7) /* Watchdog timer A int. status */ BIT 47 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL3_PM2 BIT(7) /* Power Management bit 2 */ BIT 48 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL3_PM1 BIT(6) /* Power Management bit 1 */ BIT 49 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL3_PM0 BIT(5) /* Power Management bit 0 */ BIT 50 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL3_BSF BIT(3) /* Battery switchover int. status */ BIT 51 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL3_BLF BIT(2) /* Battery low int. status */ BIT 52 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL3_BSIE BIT(1) /* Battery switchover int. enable */ BIT 53 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_CTRL3_BLIE BIT(0) /* Battery low int. enable */ BIT 59 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_RTC_SC_OSC BIT(7) /* Clock integrity status */ BIT 62 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_RTC_HR_PM BIT(5) /* RTC Hours PM bit */ BIT 72 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_ALRM_MN_AE BIT(7) /* Minute enable */ BIT 74 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_ALRM_HR_AE BIT(7) /* Hour enable */ BIT 76 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_ALRM_DT_AE BIT(7) /* Date (day of the month) enable */ BIT 78 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_ALRM_DW_AE BIT(7) /* Day of the week enable */ BIT 88 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIM_CLK_TAM BIT(7) /* Permanent/pulsed timer A/int. 2 */ BIT 89 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIM_CLK_TBM BIT(6) /* Permanent/pulsed timer B */ BIT 90 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */ BIT 91 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIM_CLK_COF1 BIT(4) /* Clkout Freq bit 1 */ BIT 92 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIM_CLK_COF0 BIT(3) /* Clkout Freq bit 0 */ BIT 93 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIM_CLK_TAC1 BIT(2) /* Timer A: - 01 : countdown */ BIT 94 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIM_CLK_TAC0 BIT(1) /* - 10 : timer */ BIT 95 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIM_CLK_TBC BIT(0) /* Timer B enable */ BIT 99 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2) /* Freq bit 2 */ BIT 100 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1) /* Freq bit 1 */ BIT 101 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0) /* Freq bit 0 */ BIT 108 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6) BIT 109 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5) BIT 110 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4) BIT 111 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2) BIT 112 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1) BIT 113 drivers/rtc/rtc-ab-b5ze-s3.c #define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0) BIT 19 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL1_WE BIT(0) BIT 20 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL1_TE BIT(1) BIT 21 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL1_TAR BIT(2) BIT 22 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL1_EERE BIT(3) BIT 23 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL1_SRON BIT(4) BIT 24 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL1_TD0 BIT(5) BIT 25 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL1_TD1 BIT(6) BIT 26 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL1_CLKINT BIT(7) BIT 29 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_INT_AIE BIT(0) BIT 30 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_INT_TIE BIT(1) BIT 31 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_INT_V1IE BIT(2) BIT 32 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_INT_V2IE BIT(3) BIT 33 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_INT_SRIE BIT(4) BIT 36 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_INT_FLAG_AF BIT(0) BIT 37 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_INT_FLAG_TF BIT(1) BIT 38 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_INT_FLAG_V1IF BIT(2) BIT 39 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_INT_FLAG_V2IF BIT(3) BIT 40 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_INT_FLAG_SRF BIT(4) BIT 43 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_STATUS_V1F BIT(2) BIT 44 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_STATUS_V2F BIT(3) BIT 45 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_STATUS_SR BIT(4) BIT 46 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_STATUS_PON BIT(5) BIT 47 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL_STATUS_EEBUSY BIT(7) BIT 52 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_HOURS_PM BIT(6) BIT 66 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_EEPROM_THP BIT(0) BIT 67 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_EEPROM_THE BIT(1) BIT 68 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_EEPROM_FD0 BIT(2) BIT 69 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_EEPROM_FD1 BIT(3) BIT 70 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_EEPROM_R1K BIT(4) BIT 71 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_EEPROM_R5K BIT(5) BIT 72 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_EEPROM_R20K BIT(6) BIT 73 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_EEPROM_R80K BIT(7) BIT 37 drivers/rtc/rtc-abx80x.c #define ABX8XX_STATUS_AF BIT(2) BIT 38 drivers/rtc/rtc-abx80x.c #define ABX8XX_STATUS_BLF BIT(4) BIT 39 drivers/rtc/rtc-abx80x.c #define ABX8XX_STATUS_WDT BIT(6) BIT 42 drivers/rtc/rtc-abx80x.c #define ABX8XX_CTRL_WRITE BIT(0) BIT 43 drivers/rtc/rtc-abx80x.c #define ABX8XX_CTRL_ARST BIT(2) BIT 44 drivers/rtc/rtc-abx80x.c #define ABX8XX_CTRL_12_24 BIT(6) BIT 47 drivers/rtc/rtc-abx80x.c #define ABX8XX_CTRL2_RSVD BIT(5) BIT 50 drivers/rtc/rtc-abx80x.c #define ABX8XX_IRQ_AIE BIT(2) BIT 56 drivers/rtc/rtc-abx80x.c #define ABX8XX_OSC_FOS BIT(3) BIT 57 drivers/rtc/rtc-abx80x.c #define ABX8XX_OSC_BOS BIT(4) BIT 58 drivers/rtc/rtc-abx80x.c #define ABX8XX_OSC_ACAL_512 BIT(5) BIT 59 drivers/rtc/rtc-abx80x.c #define ABX8XX_OSC_ACAL_1024 BIT(6) BIT 61 drivers/rtc/rtc-abx80x.c #define ABX8XX_OSC_OSEL BIT(7) BIT 64 drivers/rtc/rtc-abx80x.c #define ABX8XX_OSS_OF BIT(1) BIT 65 drivers/rtc/rtc-abx80x.c #define ABX8XX_OSS_OMODE BIT(4) BIT 68 drivers/rtc/rtc-abx80x.c #define ABX8XX_WDT_WDS BIT(7) BIT 82 drivers/rtc/rtc-abx80x.c #define ABX8XX_OUT_CTRL_EXDS BIT(4) BIT 808 drivers/rtc/rtc-abx80x.c BIT(2)); BIT 25 drivers/rtc/rtc-ac100.c #define AC100_RTC_CTRL_24HOUR BIT(0) BIT 34 drivers/rtc/rtc-ac100.c #define AC100_CLKOUT_EN BIT(0) BIT 44 drivers/rtc/rtc-ac100.c #define AC100_RTC_YEA_LEAP BIT(15) BIT 45 drivers/rtc/rtc-ac100.c #define AC100_RTC_UPD_TRIGGER BIT(15) BIT 48 drivers/rtc/rtc-ac100.c #define AC100_ALM_INT_ENABLE BIT(0) BIT 57 drivers/rtc/rtc-ac100.c #define AC100_ALM_ENABLE_FLAG BIT(15) BIT 58 drivers/rtc/rtc-ac100.c #define AC100_ALM_UPD_TRIGGER BIT(15) BIT 137 drivers/rtc/rtc-ac100.c (BIT(AC100_CLKOUT_DIV_WIDTH) - 1); BIT 291 drivers/rtc/rtc-ac100.c BIT(AC100_CLKOUT_MUX_SHIFT), BIT 292 drivers/rtc/rtc-ac100.c index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0); BIT 19 drivers/rtc/rtc-armada38x.c #define RTC_STATUS_ALARM1 BIT(0) BIT 20 drivers/rtc/rtc-armada38x.c #define RTC_STATUS_ALARM2 BIT(1) BIT 23 drivers/rtc/rtc-armada38x.c #define RTC_IRQ_AL_EN BIT(0) BIT 24 drivers/rtc/rtc-armada38x.c #define RTC_IRQ_FREQ_EN BIT(1) BIT 25 drivers/rtc/rtc-armada38x.c #define RTC_IRQ_FREQ_1HZ BIT(2) BIT 27 drivers/rtc/rtc-armada38x.c #define RTC_CCR_MODE BIT(15) BIT 29 drivers/rtc/rtc-armada38x.c #define RTC_NOMINAL_TIMING BIT(13) BIT 54 drivers/rtc/rtc-armada38x.c #define RTC_8K_ALARM2 BIT(0) BIT 57 drivers/rtc/rtc-armada38x.c #define SOC_RTC_ALARM1 BIT(0) BIT 58 drivers/rtc/rtc-armada38x.c #define SOC_RTC_ALARM2 BIT(1) BIT 59 drivers/rtc/rtc-armada38x.c #define SOC_RTC_ALARM1_MASK BIT(2) BIT 60 drivers/rtc/rtc-armada38x.c #define SOC_RTC_ALARM2_MASK BIT(3) BIT 17 drivers/rtc/rtc-asm9260.c #define BM_RTCALF BIT(1) BIT 18 drivers/rtc/rtc-asm9260.c #define BM_RTCCIF BIT(0) BIT 23 drivers/rtc/rtc-asm9260.c #define BM_CCALOFF BIT(4) BIT 25 drivers/rtc/rtc-asm9260.c #define BM_CTCRST BIT(1) BIT 27 drivers/rtc/rtc-asm9260.c #define BM_CLKEN BIT(0) BIT 31 drivers/rtc/rtc-asm9260.c #define BM_CIIR_IMYEAR BIT(7) BIT 32 drivers/rtc/rtc-asm9260.c #define BM_CIIR_IMMON BIT(6) BIT 33 drivers/rtc/rtc-asm9260.c #define BM_CIIR_IMDOY BIT(5) BIT 34 drivers/rtc/rtc-asm9260.c #define BM_CIIR_IMDOW BIT(4) BIT 35 drivers/rtc/rtc-asm9260.c #define BM_CIIR_IMDOM BIT(3) BIT 36 drivers/rtc/rtc-asm9260.c #define BM_CIIR_IMHOUR BIT(2) BIT 37 drivers/rtc/rtc-asm9260.c #define BM_CIIR_IMMIN BIT(1) BIT 38 drivers/rtc/rtc-asm9260.c #define BM_CIIR_IMSEC BIT(0) BIT 42 drivers/rtc/rtc-asm9260.c #define BM_AMR_IMYEAR BIT(7) BIT 43 drivers/rtc/rtc-asm9260.c #define BM_AMR_IMMON BIT(6) BIT 44 drivers/rtc/rtc-asm9260.c #define BM_AMR_IMDOY BIT(5) BIT 45 drivers/rtc/rtc-asm9260.c #define BM_AMR_IMDOW BIT(4) BIT 46 drivers/rtc/rtc-asm9260.c #define BM_AMR_IMDOM BIT(3) BIT 47 drivers/rtc/rtc-asm9260.c #define BM_AMR_IMHOUR BIT(2) BIT 48 drivers/rtc/rtc-asm9260.c #define BM_AMR_IMMIN BIT(1) BIT 49 drivers/rtc/rtc-asm9260.c #define BM_AMR_IMSEC BIT(0) BIT 86 drivers/rtc/rtc-asm9260.c #define BM_CALDIR_BACK BIT(17) BIT 19 drivers/rtc/rtc-aspeed.c #define RTC_UNLOCK BIT(1) BIT 20 drivers/rtc/rtc-aspeed.c #define RTC_ENABLE BIT(0) BIT 48 drivers/rtc/rtc-at91sam9.c #define AT91_RTT_ALMIEN BIT(16) /* Alarm Interrupt Enable */ BIT 49 drivers/rtc/rtc-at91sam9.c #define AT91_RTT_RTTINCIEN BIT(17) /* Increment Interrupt Enable */ BIT 50 drivers/rtc/rtc-at91sam9.c #define AT91_RTT_RTTRST BIT(18) /* Timer Restart */ BIT 59 drivers/rtc/rtc-at91sam9.c #define AT91_RTT_ALMS BIT(0) /* Alarm Status */ BIT 60 drivers/rtc/rtc-at91sam9.c #define AT91_RTT_RTTINC BIT(1) /* Timer Increment */ BIT 34 drivers/rtc/rtc-bq32k.c #define BQ32K_TCFE BIT(6) /* Trickle charge FET bypass */ BIT 37 drivers/rtc/rtc-cadence.c #define CDNS_RTC_CTLR_TIME BIT(0) BIT 38 drivers/rtc/rtc-cadence.c #define CDNS_RTC_CTLR_CAL BIT(1) BIT 42 drivers/rtc/rtc-cadence.c #define CDNS_RTC_STSR_VT BIT(0) BIT 43 drivers/rtc/rtc-cadence.c #define CDNS_RTC_STSR_VC BIT(1) BIT 44 drivers/rtc/rtc-cadence.c #define CDNS_RTC_STSR_VTA BIT(2) BIT 45 drivers/rtc/rtc-cadence.c #define CDNS_RTC_STSR_VCA BIT(3) BIT 50 drivers/rtc/rtc-cadence.c #define CDNS_RTC_KRTCR_KRTC BIT(0) BIT 53 drivers/rtc/rtc-cadence.c #define CDNS_RTC_AEI_HOS BIT(0) BIT 54 drivers/rtc/rtc-cadence.c #define CDNS_RTC_AEI_SEC BIT(1) BIT 55 drivers/rtc/rtc-cadence.c #define CDNS_RTC_AEI_MIN BIT(2) BIT 56 drivers/rtc/rtc-cadence.c #define CDNS_RTC_AEI_HOUR BIT(3) BIT 57 drivers/rtc/rtc-cadence.c #define CDNS_RTC_AEI_DATE BIT(4) BIT 58 drivers/rtc/rtc-cadence.c #define CDNS_RTC_AEI_MNTH BIT(5) BIT 59 drivers/rtc/rtc-cadence.c #define CDNS_RTC_AEI_ALRM BIT(6) BIT 66 drivers/rtc/rtc-cadence.c #define CDNS_RTC_TIME_PM BIT(30) BIT 67 drivers/rtc/rtc-cadence.c #define CDNS_RTC_TIME_CH BIT(31) BIT 75 drivers/rtc/rtc-cadence.c #define CDNS_RTC_CAL_CH BIT(31) BIT 38 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_BUSY BIT(31) BIT 39 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_SIZE BIT(25) BIT 40 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_DIR BIT(24) BIT 41 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_BENU_MSB BIT(23) BIT 42 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22) BIT 43 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21) BIT 44 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_BENU_LSB BIT(20) BIT 46 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_BENL_MSB BIT(19) BIT 47 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18) BIT 48 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17) BIT 49 drivers/rtc/rtc-davinci.c #define PRTCIF_CTLR_BENL_LSB BIT(16) BIT 53 drivers/rtc/rtc-davinci.c #define PRTCIF_INTEN_RTCSS BIT(1) BIT 54 drivers/rtc/rtc-davinci.c #define PRTCIF_INTEN_RTCIF BIT(0) BIT 59 drivers/rtc/rtc-davinci.c #define PRTCIF_INTFLG_RTCSS BIT(1) BIT 60 drivers/rtc/rtc-davinci.c #define PRTCIF_INTFLG_RTCIF BIT(0) BIT 86 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CTRL_WDTBUS BIT(7) BIT 87 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CTRL_WEN BIT(6) BIT 88 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CTRL_WDRT BIT(5) BIT 89 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CTRL_WDTFLG BIT(4) BIT 90 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CTRL_TE BIT(3) BIT 91 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CTRL_TIEN BIT(2) BIT 92 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CTRL_TMRFLG BIT(1) BIT 93 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CTRL_TMMD BIT(0) BIT 96 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CCTRL_CALBUSY BIT(7) BIT 97 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CCTRL_DAEN BIT(5) BIT 98 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CCTRL_HAEN BIT(4) BIT 99 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CCTRL_MAEN BIT(3) BIT 100 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CCTRL_ALMFLG BIT(2) BIT 101 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CCTRL_AIEN BIT(1) BIT 102 drivers/rtc/rtc-davinci.c #define PRTCSS_RTC_CCTRL_CAEN BIT(0) BIT 26 drivers/rtc/rtc-digicolor.c #define DC_RTC_GO_BUSY BIT(7) BIT 118 drivers/rtc/rtc-ds1307.c #define RX8130_REG_EXTENSION_WADA BIT(3) BIT 120 drivers/rtc/rtc-ds1307.c #define RX8130_REG_FLAG_VLF BIT(1) BIT 121 drivers/rtc/rtc-ds1307.c #define RX8130_REG_FLAG_AF BIT(3) BIT 123 drivers/rtc/rtc-ds1307.c #define RX8130_REG_CONTROL0_AIE BIT(3) BIT 132 drivers/rtc/rtc-ds1307.c # define MCP794XX_BIT_ALMX_IF BIT(3) BIT 133 drivers/rtc/rtc-ds1307.c # define MCP794XX_BIT_ALMX_C0 BIT(4) BIT 134 drivers/rtc/rtc-ds1307.c # define MCP794XX_BIT_ALMX_C1 BIT(5) BIT 135 drivers/rtc/rtc-ds1307.c # define MCP794XX_BIT_ALMX_C2 BIT(6) BIT 136 drivers/rtc/rtc-ds1307.c # define MCP794XX_BIT_ALMX_POL BIT(7) BIT 142 drivers/rtc/rtc-ds1307.c # define M41TXX_BIT_OUT BIT(7) BIT 143 drivers/rtc/rtc-ds1307.c # define M41TXX_BIT_FT BIT(6) BIT 144 drivers/rtc/rtc-ds1307.c # define M41TXX_BIT_CALIB_SIGN BIT(5) BIT 18 drivers/rtc/rtc-ep93xx.c #define EP93XX_RTC_STATUS_INTR BIT(0) BIT 21 drivers/rtc/rtc-ep93xx.c #define EP93XX_RTC_CONTROL_MIE BIT(0) BIT 19 drivers/rtc/rtc-hym8563.c #define HYM8563_CTL1_TEST BIT(7) BIT 20 drivers/rtc/rtc-hym8563.c #define HYM8563_CTL1_STOP BIT(5) BIT 21 drivers/rtc/rtc-hym8563.c #define HYM8563_CTL1_TESTC BIT(3) BIT 24 drivers/rtc/rtc-hym8563.c #define HYM8563_CTL2_TI_TP BIT(4) BIT 25 drivers/rtc/rtc-hym8563.c #define HYM8563_CTL2_AF BIT(3) BIT 26 drivers/rtc/rtc-hym8563.c #define HYM8563_CTL2_TF BIT(2) BIT 27 drivers/rtc/rtc-hym8563.c #define HYM8563_CTL2_AIE BIT(1) BIT 28 drivers/rtc/rtc-hym8563.c #define HYM8563_CTL2_TIE BIT(0) BIT 31 drivers/rtc/rtc-hym8563.c #define HYM8563_SEC_VL BIT(7) BIT 47 drivers/rtc/rtc-hym8563.c #define HYM8563_MONTH_CENTURY BIT(7) BIT 58 drivers/rtc/rtc-hym8563.c #define HYM8563_ALM_BIT_DISABLE BIT(7) BIT 61 drivers/rtc/rtc-hym8563.c #define HYM8563_CLKOUT_ENABLE BIT(7) BIT 69 drivers/rtc/rtc-hym8563.c #define HYM8563_TMR_CTL_ENABLE BIT(7) BIT 20 drivers/rtc/rtc-isl12026.c # define ISL12026_REG_PWR_BSW BIT(6) BIT 21 drivers/rtc/rtc-isl12026.c # define ISL12026_REG_PWR_SBIB BIT(7) BIT 24 drivers/rtc/rtc-isl12026.c # define ISL12026_REG_HR_MIL BIT(7) /* military or 24 hour time */ BIT 26 drivers/rtc/rtc-isl12026.c # define ISL12026_REG_SR_RTCF BIT(0) BIT 27 drivers/rtc/rtc-isl12026.c # define ISL12026_REG_SR_WEL BIT(1) BIT 28 drivers/rtc/rtc-isl12026.c # define ISL12026_REG_SR_RWEL BIT(2) BIT 29 drivers/rtc/rtc-isl12026.c # define ISL12026_REG_SR_MBZ BIT(3) BIT 30 drivers/rtc/rtc-isl12026.c # define ISL12026_REG_SR_OSCF BIT(4) BIT 31 drivers/rtc/rtc-jz4740.c #define JZ_RTC_WENR_WEN BIT(31) BIT 33 drivers/rtc/rtc-jz4740.c #define JZ_RTC_CTRL_WRDY BIT(7) BIT 34 drivers/rtc/rtc-jz4740.c #define JZ_RTC_CTRL_1HZ BIT(6) BIT 35 drivers/rtc/rtc-jz4740.c #define JZ_RTC_CTRL_1HZ_IRQ BIT(5) BIT 36 drivers/rtc/rtc-jz4740.c #define JZ_RTC_CTRL_AF BIT(4) BIT 37 drivers/rtc/rtc-jz4740.c #define JZ_RTC_CTRL_AF_IRQ BIT(3) BIT 38 drivers/rtc/rtc-jz4740.c #define JZ_RTC_CTRL_AE BIT(2) BIT 39 drivers/rtc/rtc-jz4740.c #define JZ_RTC_CTRL_ENABLE BIT(0) BIT 28 drivers/rtc/rtc-lp8788.c #define LP8788_INT_RTC_ALM1_M BIT(1) /* Addr 05h */ BIT 30 drivers/rtc/rtc-lp8788.c #define LP8788_INT_RTC_ALM2_M BIT(2) /* Addr 05h */ BIT 32 drivers/rtc/rtc-lp8788.c #define LP8788_ALM_EN_M BIT(7) /* Addr 7Dh or 84h */ BIT 20 drivers/rtc/rtc-lpc24xx.c #define LPC24XX_RTCCIF BIT(0) BIT 21 drivers/rtc/rtc-lpc24xx.c #define LPC24XX_RTCALF BIT(1) BIT 24 drivers/rtc/rtc-lpc24xx.c #define LPC24XX_CLKEN BIT(0) BIT 25 drivers/rtc/rtc-lpc24xx.c #define LPC178X_CCALEN BIT(4) BIT 55 drivers/rtc/rtc-m41t80.c #define M41T80_SEC_ST BIT(7) /* ST: Stop Bit */ BIT 56 drivers/rtc/rtc-m41t80.c #define M41T80_ALMON_AFE BIT(7) /* AFE: AF Enable Bit */ BIT 57 drivers/rtc/rtc-m41t80.c #define M41T80_ALMON_SQWE BIT(6) /* SQWE: SQW Enable Bit */ BIT 58 drivers/rtc/rtc-m41t80.c #define M41T80_ALHOUR_HT BIT(6) /* HT: Halt Update Bit */ BIT 59 drivers/rtc/rtc-m41t80.c #define M41T80_FLAGS_OF BIT(2) /* OF: Oscillator Failure Bit */ BIT 60 drivers/rtc/rtc-m41t80.c #define M41T80_FLAGS_AF BIT(6) /* AF: Alarm Flag Bit */ BIT 61 drivers/rtc/rtc-m41t80.c #define M41T80_FLAGS_BATT_LOW BIT(4) /* BL: Battery Low Bit */ BIT 62 drivers/rtc/rtc-m41t80.c #define M41T80_WATCHDOG_RB2 BIT(7) /* RB: Watchdog resolution */ BIT 63 drivers/rtc/rtc-m41t80.c #define M41T80_WATCHDOG_RB1 BIT(1) /* RB: Watchdog resolution */ BIT 64 drivers/rtc/rtc-m41t80.c #define M41T80_WATCHDOG_RB0 BIT(0) /* RB: Watchdog resolution */ BIT 66 drivers/rtc/rtc-m41t80.c #define M41T80_FEATURE_HT BIT(0) /* Halt feature */ BIT 67 drivers/rtc/rtc-m41t80.c #define M41T80_FEATURE_BL BIT(1) /* Battery low indicator */ BIT 68 drivers/rtc/rtc-m41t80.c #define M41T80_FEATURE_SQ BIT(2) /* Squarewave feature */ BIT 69 drivers/rtc/rtc-m41t80.c #define M41T80_FEATURE_WD BIT(3) /* Extra watchdog resolution */ BIT 70 drivers/rtc/rtc-m41t80.c #define M41T80_FEATURE_SQ_ALT BIT(4) /* RSx bits are in reg 4 */ BIT 31 drivers/rtc/rtc-m48t86.c #define M48T86_B_SET BIT(7) BIT 32 drivers/rtc/rtc-m48t86.c #define M48T86_B_DM BIT(2) BIT 33 drivers/rtc/rtc-m48t86.c #define M48T86_B_H24 BIT(1) BIT 36 drivers/rtc/rtc-m48t86.c #define M48T86_D_VRT BIT(7) BIT 29 drivers/rtc/rtc-max77686.c #define BCD_EN_MASK BIT(BCD_EN_SHIFT) BIT 31 drivers/rtc/rtc-max77686.c #define MODEL24_MASK BIT(MODEL24_SHIFT) BIT 34 drivers/rtc/rtc-max77686.c #define RTC_UDR_MASK BIT(RTC_UDR_SHIFT) BIT 36 drivers/rtc/rtc-max77686.c #define RTC_RBUDR_MASK BIT(RTC_RBUDR_SHIFT) BIT 39 drivers/rtc/rtc-max77686.c #define HOUR_PM_MASK BIT(HOUR_PM_SHIFT) BIT 42 drivers/rtc/rtc-max77686.c #define ALARM_ENABLE_MASK BIT(ALARM_ENABLE_SHIFT) BIT 46 drivers/rtc/rtc-mcp795.c #define MCP795_ST_BIT BIT(7) BIT 47 drivers/rtc/rtc-mcp795.c #define MCP795_24_BIT BIT(6) BIT 48 drivers/rtc/rtc-mcp795.c #define MCP795_LP_BIT BIT(5) BIT 49 drivers/rtc/rtc-mcp795.c #define MCP795_EXTOSC_BIT BIT(3) BIT 50 drivers/rtc/rtc-mcp795.c #define MCP795_OSCON_BIT BIT(5) BIT 51 drivers/rtc/rtc-mcp795.c #define MCP795_ALM0_BIT BIT(4) BIT 52 drivers/rtc/rtc-mcp795.c #define MCP795_ALM1_BIT BIT(5) BIT 53 drivers/rtc/rtc-mcp795.c #define MCP795_ALM0IF_BIT BIT(3) BIT 54 drivers/rtc/rtc-mcp795.c #define MCP795_ALM0C0_BIT BIT(4) BIT 55 drivers/rtc/rtc-mcp795.c #define MCP795_ALM0C1_BIT BIT(5) BIT 56 drivers/rtc/rtc-mcp795.c #define MCP795_ALM0C2_BIT BIT(6) BIT 29 drivers/rtc/rtc-meson.c #define RTC_ADDR0_LINE_SCLK BIT(0) BIT 30 drivers/rtc/rtc-meson.c #define RTC_ADDR0_LINE_SEN BIT(1) BIT 31 drivers/rtc/rtc-meson.c #define RTC_ADDR0_LINE_SDI BIT(2) BIT 32 drivers/rtc/rtc-meson.c #define RTC_ADDR0_START_SER BIT(17) BIT 33 drivers/rtc/rtc-meson.c #define RTC_ADDR0_WAIT_SER BIT(22) BIT 37 drivers/rtc/rtc-meson.c #define RTC_ADDR1_SDO BIT(0) BIT 38 drivers/rtc/rtc-meson.c #define RTC_ADDR1_S_READY BIT(1) BIT 20 drivers/rtc/rtc-mt6397.c #define RTC_BBPU_CBUSY BIT(6) BIT 25 drivers/rtc/rtc-mt6397.c #define RTC_IRQ_STA_AL BIT(0) BIT 26 drivers/rtc/rtc-mt6397.c #define RTC_IRQ_STA_LP BIT(3) BIT 29 drivers/rtc/rtc-mt6397.c #define RTC_IRQ_EN_AL BIT(0) BIT 30 drivers/rtc/rtc-mt6397.c #define RTC_IRQ_EN_ONESHOT BIT(2) BIT 31 drivers/rtc/rtc-mt6397.c #define RTC_IRQ_EN_LP BIT(3) BIT 35 drivers/rtc/rtc-mt6397.c #define RTC_AL_MASK_DOW BIT(4) BIT 59 drivers/rtc/rtc-mt6397.c #define RTC_PDN2_PWRON_ALARM BIT(4) BIT 40 drivers/rtc/rtc-mt7622.c #define RTC_RC_STOP BIT(0) BIT 46 drivers/rtc/rtc-mt7622.c #define RTC_INT_AL_STA BIT(4) BIT 55 drivers/rtc/rtc-mt7622.c #define RTC_AL_EN BIT(0) BIT 25 drivers/rtc/rtc-mv.c #define RTC_HOURS_12H_MODE BIT(22) /* 12 hour mode */ BIT 34 drivers/rtc/rtc-mv.c #define RTC_ALARM_VALID BIT(7) BIT 18 drivers/rtc/rtc-mxc_v2.c #define SRTC_LPCR_EN_LP BIT(3) /* lp enable */ BIT 19 drivers/rtc/rtc-mxc_v2.c #define SRTC_LPCR_WAE BIT(4) /* lp wakeup alarm enable */ BIT 20 drivers/rtc/rtc-mxc_v2.c #define SRTC_LPCR_ALP BIT(7) /* lp alarm flag */ BIT 21 drivers/rtc/rtc-mxc_v2.c #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */ BIT 22 drivers/rtc/rtc-mxc_v2.c #define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */ BIT 23 drivers/rtc/rtc-mxc_v2.c #define SRTC_LPCR_IE BIT(15) /* lp init state exit bit */ BIT 25 drivers/rtc/rtc-mxc_v2.c #define SRTC_LPSR_ALP BIT(3) /* lp alarm flag */ BIT 26 drivers/rtc/rtc-mxc_v2.c #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */ BIT 27 drivers/rtc/rtc-mxc_v2.c #define SRTC_LPSR_IES BIT(15) /* lp init state exit status */ BIT 88 drivers/rtc/rtc-omap.c #define OMAP_RTC_CTRL_SPLIT BIT(7) BIT 89 drivers/rtc/rtc-omap.c #define OMAP_RTC_CTRL_DISABLE BIT(6) BIT 90 drivers/rtc/rtc-omap.c #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) BIT 91 drivers/rtc/rtc-omap.c #define OMAP_RTC_CTRL_TEST BIT(4) BIT 92 drivers/rtc/rtc-omap.c #define OMAP_RTC_CTRL_MODE_12_24 BIT(3) BIT 93 drivers/rtc/rtc-omap.c #define OMAP_RTC_CTRL_AUTO_COMP BIT(2) BIT 94 drivers/rtc/rtc-omap.c #define OMAP_RTC_CTRL_ROUND_30S BIT(1) BIT 95 drivers/rtc/rtc-omap.c #define OMAP_RTC_CTRL_STOP BIT(0) BIT 98 drivers/rtc/rtc-omap.c #define OMAP_RTC_STATUS_POWER_UP BIT(7) BIT 99 drivers/rtc/rtc-omap.c #define OMAP_RTC_STATUS_ALARM2 BIT(7) BIT 100 drivers/rtc/rtc-omap.c #define OMAP_RTC_STATUS_ALARM BIT(6) BIT 101 drivers/rtc/rtc-omap.c #define OMAP_RTC_STATUS_1D_EVENT BIT(5) BIT 102 drivers/rtc/rtc-omap.c #define OMAP_RTC_STATUS_1H_EVENT BIT(4) BIT 103 drivers/rtc/rtc-omap.c #define OMAP_RTC_STATUS_1M_EVENT BIT(3) BIT 104 drivers/rtc/rtc-omap.c #define OMAP_RTC_STATUS_1S_EVENT BIT(2) BIT 105 drivers/rtc/rtc-omap.c #define OMAP_RTC_STATUS_RUN BIT(1) BIT 106 drivers/rtc/rtc-omap.c #define OMAP_RTC_STATUS_BUSY BIT(0) BIT 109 drivers/rtc/rtc-omap.c #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4) BIT 110 drivers/rtc/rtc-omap.c #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) BIT 111 drivers/rtc/rtc-omap.c #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) BIT 114 drivers/rtc/rtc-omap.c #define OMAP_RTC_OSC_32KCLK_EN BIT(6) BIT 115 drivers/rtc/rtc-omap.c #define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3) BIT 116 drivers/rtc/rtc-omap.c #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4) BIT 119 drivers/rtc/rtc-omap.c #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) BIT 122 drivers/rtc/rtc-omap.c #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16) BIT 123 drivers/rtc/rtc-omap.c #define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x) BIT 124 drivers/rtc/rtc-omap.c #define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x) BIT 65 drivers/rtc/rtc-pcf2123.c #define CTRL1_CORR_INT BIT(1) /* Correction irq enable */ BIT 66 drivers/rtc/rtc-pcf2123.c #define CTRL1_12_HOUR BIT(2) /* 12 hour time */ BIT 67 drivers/rtc/rtc-pcf2123.c #define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */ BIT 68 drivers/rtc/rtc-pcf2123.c #define CTRL1_STOP BIT(5) /* Stop the clock */ BIT 69 drivers/rtc/rtc-pcf2123.c #define CTRL1_EXT_TEST BIT(7) /* External clock test mode */ BIT 72 drivers/rtc/rtc-pcf2123.c #define CTRL2_TIE BIT(0) /* Countdown timer irq enable */ BIT 73 drivers/rtc/rtc-pcf2123.c #define CTRL2_AIE BIT(1) /* Alarm irq enable */ BIT 74 drivers/rtc/rtc-pcf2123.c #define CTRL2_TF BIT(2) /* Countdown timer flag */ BIT 75 drivers/rtc/rtc-pcf2123.c #define CTRL2_AF BIT(3) /* Alarm flag */ BIT 76 drivers/rtc/rtc-pcf2123.c #define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */ BIT 77 drivers/rtc/rtc-pcf2123.c #define CTRL2_MSF BIT(5) /* Minute or second irq flag */ BIT 78 drivers/rtc/rtc-pcf2123.c #define CTRL2_SI BIT(6) /* Second irq enable */ BIT 79 drivers/rtc/rtc-pcf2123.c #define CTRL2_MI BIT(7) /* Minute irq enable */ BIT 82 drivers/rtc/rtc-pcf2123.c #define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */ BIT 85 drivers/rtc/rtc-pcf2123.c #define ALRM_DISABLE BIT(7) /* MN, HR, DM, or DW alarm matching */ BIT 92 drivers/rtc/rtc-pcf2123.c #define CD_TMR_TE BIT(3) /* Countdown timer enable */ BIT 96 drivers/rtc/rtc-pcf2123.c #define OFFSET_COARSE BIT(7) /* Coarse mode offset */ BIT 101 drivers/rtc/rtc-pcf2123.c #define PCF2123_WRITE BIT(4) BIT 102 drivers/rtc/rtc-pcf2123.c #define PCF2123_READ (BIT(4) | BIT(7)) BIT 28 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_CTRL1_TSF1 BIT(4) BIT 31 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_CTRL2_TSIE BIT(2) BIT 32 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_CTRL2_TSF2 BIT(5) BIT 35 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_CTRL3_BLIE BIT(0) BIT 36 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_CTRL3_BIE BIT(1) BIT 37 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_CTRL3_BLF BIT(2) BIT 38 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_CTRL3_BF BIT(3) BIT 39 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_CTRL3_BTSE BIT(4) BIT 42 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_SC_OSF BIT(7) BIT 51 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_WD_CTL_TF0 BIT(0) BIT 52 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_WD_CTL_TF1 BIT(1) BIT 53 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_WD_CTL_CD0 BIT(6) BIT 54 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_WD_CTL_CD1 BIT(7) BIT 58 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) BIT 59 drivers/rtc/rtc-pcf2127.c #define PCF2127_BIT_TS_CTRL_TSM BIT(7) BIT 34 drivers/rtc/rtc-pcf85063.c #define PCF85063_REG_CTRL1_CAP_SEL BIT(0) BIT 35 drivers/rtc/rtc-pcf85063.c #define PCF85063_REG_CTRL1_STOP BIT(5) BIT 38 drivers/rtc/rtc-pcf85063.c #define PCF85063_CTRL2_AF BIT(6) BIT 39 drivers/rtc/rtc-pcf85063.c #define PCF85063_CTRL2_AIE BIT(7) BIT 43 drivers/rtc/rtc-pcf85063.c #define PCF85063_OFFSET_MODE BIT(7) BIT 53 drivers/rtc/rtc-pcf85063.c #define PCF85063_AEN BIT(7) BIT 36 drivers/rtc/rtc-pcf8523.c #define REG_OFFSET_MODE BIT(7) BIT 71 drivers/rtc/rtc-pcf85363.c #define ALRM_SEC_A1E BIT(0) BIT 72 drivers/rtc/rtc-pcf85363.c #define ALRM_MIN_A1E BIT(1) BIT 73 drivers/rtc/rtc-pcf85363.c #define ALRM_HR_A1E BIT(2) BIT 74 drivers/rtc/rtc-pcf85363.c #define ALRM_DAY_A1E BIT(3) BIT 75 drivers/rtc/rtc-pcf85363.c #define ALRM_MON_A1E BIT(4) BIT 76 drivers/rtc/rtc-pcf85363.c #define ALRM_MIN_A2E BIT(5) BIT 77 drivers/rtc/rtc-pcf85363.c #define ALRM_HR_A2E BIT(6) BIT 78 drivers/rtc/rtc-pcf85363.c #define ALRM_DAY_A2E BIT(7) BIT 80 drivers/rtc/rtc-pcf85363.c #define INT_WDIE BIT(0) BIT 81 drivers/rtc/rtc-pcf85363.c #define INT_BSIE BIT(1) BIT 82 drivers/rtc/rtc-pcf85363.c #define INT_TSRIE BIT(2) BIT 83 drivers/rtc/rtc-pcf85363.c #define INT_A2IE BIT(3) BIT 84 drivers/rtc/rtc-pcf85363.c #define INT_A1IE BIT(4) BIT 85 drivers/rtc/rtc-pcf85363.c #define INT_OIE BIT(5) BIT 86 drivers/rtc/rtc-pcf85363.c #define INT_PIE BIT(6) BIT 87 drivers/rtc/rtc-pcf85363.c #define INT_ILP BIT(7) BIT 89 drivers/rtc/rtc-pcf85363.c #define FLAGS_TSR1F BIT(0) BIT 90 drivers/rtc/rtc-pcf85363.c #define FLAGS_TSR2F BIT(1) BIT 91 drivers/rtc/rtc-pcf85363.c #define FLAGS_TSR3F BIT(2) BIT 92 drivers/rtc/rtc-pcf85363.c #define FLAGS_BSF BIT(3) BIT 93 drivers/rtc/rtc-pcf85363.c #define FLAGS_WDF BIT(4) BIT 94 drivers/rtc/rtc-pcf85363.c #define FLAGS_A1F BIT(5) BIT 95 drivers/rtc/rtc-pcf85363.c #define FLAGS_A2F BIT(6) BIT 96 drivers/rtc/rtc-pcf85363.c #define FLAGS_PIF BIT(7) BIT 104 drivers/rtc/rtc-pcf85363.c #define STOP_EN_STOP BIT(0) BIT 48 drivers/rtc/rtc-pcf8563.c #define PCF8563_TMRC_ENABLE BIT(7) BIT 22 drivers/rtc/rtc-pic32.c #define PIC32_RTCCON_ON BIT(15) BIT 23 drivers/rtc/rtc-pic32.c #define PIC32_RTCCON_SIDL BIT(13) BIT 25 drivers/rtc/rtc-pic32.c #define PIC32_RTCCON_RTCCLKON BIT(6) BIT 26 drivers/rtc/rtc-pic32.c #define PIC32_RTCCON_RTCWREN BIT(3) BIT 27 drivers/rtc/rtc-pic32.c #define PIC32_RTCCON_RTCSYNC BIT(2) BIT 28 drivers/rtc/rtc-pic32.c #define PIC32_RTCCON_HALFSEC BIT(1) BIT 29 drivers/rtc/rtc-pic32.c #define PIC32_RTCCON_RTCOE BIT(0) BIT 32 drivers/rtc/rtc-pic32.c #define PIC32_RTCALRM_ALRMEN BIT(15) BIT 33 drivers/rtc/rtc-pic32.c #define PIC32_RTCALRM_CHIME BIT(14) BIT 34 drivers/rtc/rtc-pic32.c #define PIC32_RTCALRM_PIV BIT(13) BIT 35 drivers/rtc/rtc-pic32.c #define PIC32_RTCALRM_ALARMSYNC BIT(12) BIT 21 drivers/rtc/rtc-pm8xxx.c #define PM8xxx_RTC_ENABLE BIT(7) BIT 22 drivers/rtc/rtc-pm8xxx.c #define PM8xxx_RTC_ALARM_CLEAR BIT(0) BIT 412 drivers/rtc/rtc-pm8xxx.c .alarm_en = BIT(1), BIT 422 drivers/rtc/rtc-pm8xxx.c .alarm_en = BIT(1), BIT 432 drivers/rtc/rtc-pm8xxx.c .alarm_en = BIT(7), BIT 25 drivers/rtc/rtc-r7301.c #define RTC7301_AE BIT(3) BIT 40 drivers/rtc/rtc-r7301.c #define RTC7301_ALARM_CONTROL_AIE BIT(0) BIT 41 drivers/rtc/rtc-r7301.c #define RTC7301_ALARM_CONTROL_AF BIT(1) BIT 43 drivers/rtc/rtc-r7301.c #define RTC7301_TIMER_CONTROL_TIE BIT(0) BIT 44 drivers/rtc/rtc-r7301.c #define RTC7301_TIMER_CONTROL_TF BIT(1) BIT 46 drivers/rtc/rtc-r7301.c #define RTC7301_CONTROL_BUSY BIT(0) BIT 47 drivers/rtc/rtc-r7301.c #define RTC7301_CONTROL_STOP BIT(1) BIT 48 drivers/rtc/rtc-r7301.c #define RTC7301_CONTROL_BANK_SEL_0 BIT(2) BIT 49 drivers/rtc/rtc-r7301.c #define RTC7301_CONTROL_BANK_SEL_1 BIT(3) BIT 124 drivers/rtc/rtc-r7301.c if (bank & BIT(0)) BIT 126 drivers/rtc/rtc-r7301.c if (bank & BIT(1)) BIT 33 drivers/rtc/rtc-rc5t583.c #define SET_YAL BIT(5) BIT 36 drivers/rtc/rtc-rc5t583.c #define GET_YAL_STATUS BIT(3) BIT 20 drivers/rtc/rtc-rk808.c #define BIT_RTC_CTRL_REG_STOP_RTC_M BIT(0) BIT 27 drivers/rtc/rtc-rk808.c #define BIT_RTC_CTRL_REG_RTC_GET_TIME BIT(6) BIT 28 drivers/rtc/rtc-rk808.c #define BIT_RTC_CTRL_REG_RTC_READSEL_M BIT(7) BIT 29 drivers/rtc/rtc-rk808.c #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M BIT(3) BIT 37 drivers/rtc/rtc-rtd119x.c #define RTD_RTCACR_RTCPWR BIT(7) BIT 41 drivers/rtc/rtc-rtd119x.c #define RTD_RTCCR_RTCRST BIT(6) BIT 46 drivers/rtc/rtc-rv3028.c #define RV3028_STATUS_PORF BIT(0) BIT 47 drivers/rtc/rtc-rv3028.c #define RV3028_STATUS_EVF BIT(1) BIT 48 drivers/rtc/rtc-rv3028.c #define RV3028_STATUS_AF BIT(2) BIT 49 drivers/rtc/rtc-rv3028.c #define RV3028_STATUS_TF BIT(3) BIT 50 drivers/rtc/rtc-rv3028.c #define RV3028_STATUS_UF BIT(4) BIT 51 drivers/rtc/rtc-rv3028.c #define RV3028_STATUS_BSF BIT(5) BIT 52 drivers/rtc/rtc-rv3028.c #define RV3028_STATUS_CLKF BIT(6) BIT 53 drivers/rtc/rtc-rv3028.c #define RV3028_STATUS_EEBUSY BIT(7) BIT 55 drivers/rtc/rtc-rv3028.c #define RV3028_CTRL1_EERD BIT(3) BIT 56 drivers/rtc/rtc-rv3028.c #define RV3028_CTRL1_WADA BIT(5) BIT 58 drivers/rtc/rtc-rv3028.c #define RV3028_CTRL2_RESET BIT(0) BIT 59 drivers/rtc/rtc-rv3028.c #define RV3028_CTRL2_12_24 BIT(1) BIT 60 drivers/rtc/rtc-rv3028.c #define RV3028_CTRL2_EIE BIT(2) BIT 61 drivers/rtc/rtc-rv3028.c #define RV3028_CTRL2_AIE BIT(3) BIT 62 drivers/rtc/rtc-rv3028.c #define RV3028_CTRL2_TIE BIT(4) BIT 63 drivers/rtc/rtc-rv3028.c #define RV3028_CTRL2_UIE BIT(5) BIT 64 drivers/rtc/rtc-rv3028.c #define RV3028_CTRL2_TSE BIT(7) BIT 66 drivers/rtc/rtc-rv3028.c #define RV3028_EVT_CTRL_TSR BIT(2) BIT 74 drivers/rtc/rtc-rv3028.c #define RV3028_BACKUP_TCE BIT(5) BIT 407 drivers/rtc/rtc-rv3028.c return regmap_update_bits(rv3028->regmap, RV3028_BACKUP, BIT(7), BIT 25 drivers/rtc/rtc-rv3029c2.c #define RV3029_ONOFF_CTRL_WE BIT(0) BIT 26 drivers/rtc/rtc-rv3029c2.c #define RV3029_ONOFF_CTRL_TE BIT(1) BIT 27 drivers/rtc/rtc-rv3029c2.c #define RV3029_ONOFF_CTRL_TAR BIT(2) BIT 28 drivers/rtc/rtc-rv3029c2.c #define RV3029_ONOFF_CTRL_EERE BIT(3) BIT 29 drivers/rtc/rtc-rv3029c2.c #define RV3029_ONOFF_CTRL_SRON BIT(4) BIT 30 drivers/rtc/rtc-rv3029c2.c #define RV3029_ONOFF_CTRL_TD0 BIT(5) BIT 31 drivers/rtc/rtc-rv3029c2.c #define RV3029_ONOFF_CTRL_TD1 BIT(6) BIT 32 drivers/rtc/rtc-rv3029c2.c #define RV3029_ONOFF_CTRL_CLKINT BIT(7) BIT 34 drivers/rtc/rtc-rv3029c2.c #define RV3029_IRQ_CTRL_AIE BIT(0) BIT 35 drivers/rtc/rtc-rv3029c2.c #define RV3029_IRQ_CTRL_TIE BIT(1) BIT 36 drivers/rtc/rtc-rv3029c2.c #define RV3029_IRQ_CTRL_V1IE BIT(2) BIT 37 drivers/rtc/rtc-rv3029c2.c #define RV3029_IRQ_CTRL_V2IE BIT(3) BIT 38 drivers/rtc/rtc-rv3029c2.c #define RV3029_IRQ_CTRL_SRIE BIT(4) BIT 40 drivers/rtc/rtc-rv3029c2.c #define RV3029_IRQ_FLAGS_AF BIT(0) BIT 41 drivers/rtc/rtc-rv3029c2.c #define RV3029_IRQ_FLAGS_TF BIT(1) BIT 42 drivers/rtc/rtc-rv3029c2.c #define RV3029_IRQ_FLAGS_V1IF BIT(2) BIT 43 drivers/rtc/rtc-rv3029c2.c #define RV3029_IRQ_FLAGS_V2IF BIT(3) BIT 44 drivers/rtc/rtc-rv3029c2.c #define RV3029_IRQ_FLAGS_SRF BIT(4) BIT 46 drivers/rtc/rtc-rv3029c2.c #define RV3029_STATUS_VLOW1 BIT(2) BIT 47 drivers/rtc/rtc-rv3029c2.c #define RV3029_STATUS_VLOW2 BIT(3) BIT 48 drivers/rtc/rtc-rv3029c2.c #define RV3029_STATUS_SR BIT(4) BIT 49 drivers/rtc/rtc-rv3029c2.c #define RV3029_STATUS_PON BIT(5) BIT 50 drivers/rtc/rtc-rv3029c2.c #define RV3029_STATUS_EEBUSY BIT(7) BIT 52 drivers/rtc/rtc-rv3029c2.c #define RV3029_RST_CTRL_SYSR BIT(4) BIT 59 drivers/rtc/rtc-rv3029c2.c #define RV3029_REG_HR_12_24 BIT(6) /* 24h/12h mode */ BIT 60 drivers/rtc/rtc-rv3029c2.c #define RV3029_REG_HR_PM BIT(5) /* PM/AM bit in 12h mode */ BIT 75 drivers/rtc/rtc-rv3029c2.c #define RV3029_A_AE_X BIT(7) BIT 92 drivers/rtc/rtc-rv3029c2.c #define RV3029_EECTRL_THP BIT(0) /* temp scan interval */ BIT 93 drivers/rtc/rtc-rv3029c2.c #define RV3029_EECTRL_THE BIT(1) /* thermometer enable */ BIT 94 drivers/rtc/rtc-rv3029c2.c #define RV3029_EECTRL_FD0 BIT(2) /* CLKOUT */ BIT 95 drivers/rtc/rtc-rv3029c2.c #define RV3029_EECTRL_FD1 BIT(3) /* CLKOUT */ BIT 96 drivers/rtc/rtc-rv3029c2.c #define RV3029_TRICKLE_1K BIT(4) /* 1.5K resistance */ BIT 97 drivers/rtc/rtc-rv3029c2.c #define RV3029_TRICKLE_5K BIT(5) /* 5K resistance */ BIT 98 drivers/rtc/rtc-rv3029c2.c #define RV3029_TRICKLE_20K BIT(6) /* 20K resistance */ BIT 99 drivers/rtc/rtc-rv3029c2.c #define RV3029_TRICKLE_80K BIT(7) /* 80K resistance */ BIT 106 drivers/rtc/rtc-rv3029c2.c #define RV3029_CONTROL_E2P_XOFFS_SIGN BIT(7) /* Sign: 1->pos, 0->neg */ BIT 37 drivers/rtc/rtc-rv8803.c #define RV8803_EXT_WADA BIT(6) BIT 39 drivers/rtc/rtc-rv8803.c #define RV8803_FLAG_V1F BIT(0) BIT 40 drivers/rtc/rtc-rv8803.c #define RV8803_FLAG_V2F BIT(1) BIT 41 drivers/rtc/rtc-rv8803.c #define RV8803_FLAG_AF BIT(3) BIT 42 drivers/rtc/rtc-rv8803.c #define RV8803_FLAG_TF BIT(4) BIT 43 drivers/rtc/rtc-rv8803.c #define RV8803_FLAG_UF BIT(5) BIT 45 drivers/rtc/rtc-rv8803.c #define RV8803_CTRL_RESET BIT(0) BIT 47 drivers/rtc/rtc-rv8803.c #define RV8803_CTRL_EIE BIT(2) BIT 48 drivers/rtc/rtc-rv8803.c #define RV8803_CTRL_AIE BIT(3) BIT 49 drivers/rtc/rtc-rv8803.c #define RV8803_CTRL_TIE BIT(4) BIT 50 drivers/rtc/rtc-rv8803.c #define RV8803_CTRL_UIE BIT(5) BIT 53 drivers/rtc/rtc-rv8803.c #define RX8900_FLAG_SWOFF BIT(2) BIT 54 drivers/rtc/rtc-rv8803.c #define RX8900_FLAG_VDETOFF BIT(3) BIT 65 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_ALARM_EN BIT(7) BIT 68 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_EXT_TSEL0 BIT(0) BIT 69 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_EXT_TSEL1 BIT(1) BIT 70 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_EXT_TSEL2 BIT(2) BIT 71 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_EXT_WADA BIT(3) BIT 72 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_EXT_TE BIT(4) BIT 73 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_EXT_USEL BIT(5) BIT 74 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_EXT_FSEL0 BIT(6) BIT 75 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_EXT_FSEL1 BIT(7) BIT 78 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_FLAG_VLF BIT(1) BIT 79 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_FLAG_AF BIT(3) BIT 80 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_FLAG_TF BIT(4) BIT 81 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_FLAG_UF BIT(5) BIT 84 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_CTRL_TBKE BIT(0) BIT 85 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_CTRL_TBKON BIT(1) BIT 86 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_CTRL_TSTP BIT(2) BIT 87 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_CTRL_AIE BIT(3) BIT 88 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_CTRL_TIE BIT(4) BIT 89 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_CTRL_UIE BIT(5) BIT 90 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_CTRL_STOP BIT(6) BIT 91 drivers/rtc/rtc-rx6110.c #define RX6110_BIT_CTRL_TEST BIT(7) BIT 132 drivers/rtc/rtc-rx6110.c data[RTC_WDAY] = BIT(bin2bcd(tm->tm_wday)); BIT 37 drivers/rtc/rtc-rx8010.c #define RX8010_EXT_WADA BIT(3) BIT 39 drivers/rtc/rtc-rx8010.c #define RX8010_FLAG_VLF BIT(1) BIT 40 drivers/rtc/rtc-rx8010.c #define RX8010_FLAG_AF BIT(3) BIT 41 drivers/rtc/rtc-rx8010.c #define RX8010_FLAG_TF BIT(4) BIT 42 drivers/rtc/rtc-rx8010.c #define RX8010_FLAG_UF BIT(5) BIT 44 drivers/rtc/rtc-rx8010.c #define RX8010_CTRL_AIE BIT(3) BIT 45 drivers/rtc/rtc-rx8010.c #define RX8010_CTRL_UIE BIT(5) BIT 46 drivers/rtc/rtc-rx8010.c #define RX8010_CTRL_STOP BIT(6) BIT 47 drivers/rtc/rtc-rx8010.c #define RX8010_CTRL_TEST BIT(7) BIT 49 drivers/rtc/rtc-rx8010.c #define RX8010_ALARM_AE BIT(7) BIT 46 drivers/rtc/rtc-rx8025.c #define RX8025_BIT_CTRL1_TEST BIT(3) BIT 47 drivers/rtc/rtc-rx8025.c #define RX8025_BIT_CTRL1_1224 BIT(5) BIT 48 drivers/rtc/rtc-rx8025.c #define RX8025_BIT_CTRL1_DALE BIT(6) BIT 49 drivers/rtc/rtc-rx8025.c #define RX8025_BIT_CTRL1_WALE BIT(7) BIT 51 drivers/rtc/rtc-rx8025.c #define RX8025_BIT_CTRL2_DAFG BIT(0) BIT 52 drivers/rtc/rtc-rx8025.c #define RX8025_BIT_CTRL2_WAFG BIT(1) BIT 53 drivers/rtc/rtc-rx8025.c #define RX8025_BIT_CTRL2_CTFG BIT(2) BIT 54 drivers/rtc/rtc-rx8025.c #define RX8025_BIT_CTRL2_PON BIT(4) BIT 55 drivers/rtc/rtc-rx8025.c #define RX8025_BIT_CTRL2_XST BIT(5) BIT 56 drivers/rtc/rtc-rx8025.c #define RX8025_BIT_CTRL2_VDET BIT(6) BIT 35 drivers/rtc/rtc-s35390a.c #define S35390A_FLAG_POC BIT(0) BIT 36 drivers/rtc/rtc-s35390a.c #define S35390A_FLAG_BLD BIT(1) BIT 37 drivers/rtc/rtc-s35390a.c #define S35390A_FLAG_INT2 BIT(2) BIT 38 drivers/rtc/rtc-s35390a.c #define S35390A_FLAG_24H BIT(6) BIT 39 drivers/rtc/rtc-s35390a.c #define S35390A_FLAG_RESET BIT(7) BIT 42 drivers/rtc/rtc-s35390a.c #define S35390A_FLAG_TEST BIT(0) BIT 47 drivers/rtc/rtc-s35390a.c #define S35390A_INT2_MODE_ALARM BIT(1) /* INT2AE */ BIT 48 drivers/rtc/rtc-s35390a.c #define S35390A_INT2_MODE_PMIN_EDG BIT(2) /* INT2ME */ BIT 49 drivers/rtc/rtc-s35390a.c #define S35390A_INT2_MODE_FREQ BIT(3) /* INT2FE */ BIT 50 drivers/rtc/rtc-s35390a.c #define S35390A_INT2_MODE_PMIN (BIT(3) | BIT(2)) /* INT2FE | INT2ME */ BIT 34 drivers/rtc/rtc-sa1100.c #define RTSR_HZE BIT(3) /* HZ interrupt enable */ BIT 35 drivers/rtc/rtc-sa1100.c #define RTSR_ALE BIT(2) /* RTC alarm interrupt enable */ BIT 36 drivers/rtc/rtc-sa1100.c #define RTSR_HZ BIT(1) /* HZ rising-edge detected */ BIT 37 drivers/rtc/rtc-sa1100.c #define RTSR_AL BIT(0) /* RTC alarm detected */ BIT 46 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_SEC_EN BIT(0) BIT 47 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_MIN_EN BIT(1) BIT 48 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_HOUR_EN BIT(2) BIT 49 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_DAY_EN BIT(3) BIT 50 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_ALARM_EN BIT(4) BIT 51 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_HRS_FORMAT_EN BIT(5) BIT 52 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_AUXALM_EN BIT(6) BIT 53 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_SPG_UPD_EN BIT(7) BIT 54 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_SEC_UPD_EN BIT(8) BIT 55 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_MIN_UPD_EN BIT(9) BIT 56 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_HOUR_UPD_EN BIT(10) BIT 57 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_DAY_UPD_EN BIT(11) BIT 58 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_ALMSEC_UPD_EN BIT(12) BIT 59 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_ALMMIN_UPD_EN BIT(13) BIT 60 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_ALMHOUR_UPD_EN BIT(14) BIT 61 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_ALMDAY_UPD_EN BIT(15) BIT 90 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_POWEROFF_ALM_FLAG BIT(8) BIT 39 drivers/rtc/rtc-stm32.c #define STM32_RTC_CR_FMT BIT(6) BIT 40 drivers/rtc/rtc-stm32.c #define STM32_RTC_CR_ALRAE BIT(8) BIT 41 drivers/rtc/rtc-stm32.c #define STM32_RTC_CR_ALRAIE BIT(12) BIT 44 drivers/rtc/rtc-stm32.c #define STM32_RTC_ISR_ALRAWF BIT(0) BIT 45 drivers/rtc/rtc-stm32.c #define STM32_RTC_ISR_INITS BIT(4) BIT 46 drivers/rtc/rtc-stm32.c #define STM32_RTC_ISR_RSF BIT(5) BIT 47 drivers/rtc/rtc-stm32.c #define STM32_RTC_ISR_INITF BIT(6) BIT 48 drivers/rtc/rtc-stm32.c #define STM32_RTC_ISR_INIT BIT(7) BIT 49 drivers/rtc/rtc-stm32.c #define STM32_RTC_ISR_ALRAF BIT(8) BIT 60 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_SEC_MASK BIT(7) BIT 63 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_MIN_MASK BIT(15) BIT 66 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_PM BIT(22) BIT 67 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_HOUR_MASK BIT(23) BIT 70 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_WDSEL BIT(30) BIT 73 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_DATE_MASK BIT(31) BIT 76 drivers/rtc/rtc-stm32.c #define STM32_RTC_SR_ALRA BIT(0) BIT 35 drivers/rtc/rtc-sun6i.c #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) BIT 36 drivers/rtc/rtc-sun6i.c #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) BIT 37 drivers/rtc/rtc-sun6i.c #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) BIT 38 drivers/rtc/rtc-sun6i.c #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) BIT 39 drivers/rtc/rtc-sun6i.c #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) BIT 40 drivers/rtc/rtc-sun6i.c #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) BIT 53 drivers/rtc/rtc-sun6i.c #define SUN6I_ALRM_EN_CNT_EN BIT(0) BIT 55 drivers/rtc/rtc-sun6i.c #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) BIT 57 drivers/rtc/rtc-sun6i.c #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) BIT 63 drivers/rtc/rtc-sun6i.c #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) BIT 67 drivers/rtc/rtc-sun6i.c #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) BIT 24 drivers/rtc/rtc-sunxi.c #define SUNXI_LOSC_CTRL_RTC_HMS_ACC BIT(8) BIT 25 drivers/rtc/rtc-sunxi.c #define SUNXI_LOSC_CTRL_RTC_YMD_ACC BIT(7) BIT 34 drivers/rtc/rtc-sunxi.c #define SUNXI_ALRM_EN_CNT_EN BIT(8) BIT 37 drivers/rtc/rtc-sunxi.c #define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) BIT 40 drivers/rtc/rtc-sunxi.c #define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) BIT 35 drivers/rtc/rtc-tps6586x.c #define POR_RESET_N BIT(7) BIT 36 drivers/rtc/rtc-tps6586x.c #define OSC_SRC_SEL BIT(6) BIT 37 drivers/rtc/rtc-tps6586x.c #define RTC_ENABLE BIT(5) /* enables alarm */ BIT 38 drivers/rtc/rtc-tps6586x.c #define RTC_BUF_ENABLE BIT(4) /* 32 KHz buffer enable */ BIT 39 drivers/rtc/rtc-tps6586x.c #define PRE_BYPASS BIT(3) /* 0=1KHz or 1=32KHz updates */ BIT 40 drivers/rtc/rtc-tps6586x.c #define CL_SEL_MASK (BIT(2)|BIT(1)) BIT 25 drivers/rtc/rtc-xgene.c #define RTC_CCR_IE BIT(0) BIT 26 drivers/rtc/rtc-xgene.c #define RTC_CCR_MASK BIT(1) BIT 27 drivers/rtc/rtc-xgene.c #define RTC_CCR_EN BIT(2) BIT 28 drivers/rtc/rtc-xgene.c #define RTC_CCR_WEN BIT(3) BIT 30 drivers/rtc/rtc-xgene.c #define RTC_STAT_BIT BIT(0) BIT 31 drivers/rtc/rtc-zynqmp.c #define RTC_FR_EN BIT(20) BIT 34 drivers/rtc/rtc-zynqmp.c #define RTC_INT_SEC BIT(0) BIT 35 drivers/rtc/rtc-zynqmp.c #define RTC_INT_ALRM BIT(1) BIT 36 drivers/rtc/rtc-zynqmp.c #define RTC_OSC_EN BIT(24) BIT 37 drivers/rtc/rtc-zynqmp.c #define RTC_BATT_EN BIT(31) BIT 2051 drivers/s390/net/qeth_l2_main.c vnicc = BIT(i); BIT 2075 drivers/s390/net/qeth_l2_main.c vnicc = BIT(i); BIT 189 drivers/scsi/FlashPoint.c #define TAR_SYNC_MASK (BIT(7)+BIT(6)) BIT 190 drivers/scsi/FlashPoint.c #define SYNC_TRYING BIT(6) BIT 191 drivers/scsi/FlashPoint.c #define SYNC_SUPPORTED (BIT(7)+BIT(6)) BIT 193 drivers/scsi/FlashPoint.c #define TAR_WIDE_MASK (BIT(5)+BIT(4)) BIT 194 drivers/scsi/FlashPoint.c #define WIDE_ENABLED BIT(4) BIT 195 drivers/scsi/FlashPoint.c #define WIDE_NEGOCIATED BIT(5) BIT 197 drivers/scsi/FlashPoint.c #define TAR_TAG_Q_MASK (BIT(3)+BIT(2)) BIT 198 drivers/scsi/FlashPoint.c #define TAG_Q_TRYING BIT(2) BIT 199 drivers/scsi/FlashPoint.c #define TAG_Q_REJECT BIT(3) BIT 201 drivers/scsi/FlashPoint.c #define TAR_ALLOW_DISC BIT(0) BIT 203 drivers/scsi/FlashPoint.c #define EE_SYNC_MASK (BIT(0)+BIT(1)) BIT 204 drivers/scsi/FlashPoint.c #define EE_SYNC_5MB BIT(0) BIT 205 drivers/scsi/FlashPoint.c #define EE_SYNC_10MB BIT(1) BIT 206 drivers/scsi/FlashPoint.c #define EE_SYNC_20MB (BIT(0)+BIT(1)) BIT 208 drivers/scsi/FlashPoint.c #define EE_WIDE_SCSI BIT(7) BIT 377 drivers/scsi/FlashPoint.c #define SCAM_ENABLED BIT(2) BIT 378 drivers/scsi/FlashPoint.c #define SCAM_LEVEL2 BIT(3) BIT 380 drivers/scsi/FlashPoint.c #define RENEGO_ENA BIT(10) BIT 381 drivers/scsi/FlashPoint.c #define CONNIO_ENA BIT(11) BIT 382 drivers/scsi/FlashPoint.c #define GREEN_PC_ENA BIT(12) BIT 389 drivers/scsi/FlashPoint.c #define WIDE_NEGO_BIT BIT(7) BIT 390 drivers/scsi/FlashPoint.c #define DISC_ENABLE_BIT BIT(6) BIT 410 drivers/scsi/FlashPoint.c #define SCCB_MGR_ACTIVE BIT(0) BIT 411 drivers/scsi/FlashPoint.c #define TICKLE_ME BIT(1) BIT 412 drivers/scsi/FlashPoint.c #define SCCB_MGR_PRESENT BIT(3) BIT 413 drivers/scsi/FlashPoint.c #define BIOS_IN_USE BIT(4) BIT 417 drivers/scsi/FlashPoint.c #define STOP_CLK BIT(0) /*Turn off BusMaster Clock */ BIT 418 drivers/scsi/FlashPoint.c #define DRVR_RST BIT(1) /*Firmware Reset to 80C15 chip */ BIT 419 drivers/scsi/FlashPoint.c #define HALT_MACH BIT(3) /*Halt State Machine */ BIT 420 drivers/scsi/FlashPoint.c #define HARD_ABORT BIT(4) /*Hard Abort */ BIT 430 drivers/scsi/FlashPoint.c #define INT_CMD_COMPL BIT(0) /* DMA command complete */ BIT 431 drivers/scsi/FlashPoint.c #define INT_EXT_STATUS BIT(1) /* Extended Status Set */ BIT 444 drivers/scsi/FlashPoint.c #define DISABLE_INT BIT(7) /*Do not interrupt at end of cmd. */ BIT 454 drivers/scsi/FlashPoint.c #define EXT_ARB_ACK BIT(7) BIT 455 drivers/scsi/FlashPoint.c #define SCSI_TERM_ENA_H BIT(6) /* SCSI high byte terminator */ BIT 456 drivers/scsi/FlashPoint.c #define SEE_MS BIT(5) BIT 457 drivers/scsi/FlashPoint.c #define SEE_CS BIT(3) BIT 458 drivers/scsi/FlashPoint.c #define SEE_CLK BIT(2) BIT 459 drivers/scsi/FlashPoint.c #define SEE_DO BIT(1) BIT 460 drivers/scsi/FlashPoint.c #define SEE_DI BIT(0) BIT 471 drivers/scsi/FlashPoint.c #define SCSI_TERM_ENA_L BIT(0) /*Enable/Disable external terminators */ BIT 472 drivers/scsi/FlashPoint.c #define FLUSH_XFER_CNTR BIT(1) /*Flush transfer counter */ BIT 473 drivers/scsi/FlashPoint.c #define FORCE1_XFER BIT(5) /*Always xfer one byte in byte mode */ BIT 474 drivers/scsi/FlashPoint.c #define FAST_SINGLE BIT(6) /*?? */ BIT 481 drivers/scsi/FlashPoint.c #define SCATTER_EN BIT(0) BIT 482 drivers/scsi/FlashPoint.c #define SGRAM_ARAM BIT(1) BIT 483 drivers/scsi/FlashPoint.c #define G_INT_DISABLE BIT(3) /* Enable/Disable all Interrupts */ BIT 484 drivers/scsi/FlashPoint.c #define NARROW_SCSI_CARD BIT(4) /* NARROW/WIDE SCSI config pin */ BIT 488 drivers/scsi/FlashPoint.c #define REC_MASTER_ABORT BIT(5) /*received Master abort */ BIT 497 drivers/scsi/FlashPoint.c #define BM_FORCE_OFF BIT(0) /*Bus Master is forced to get off */ BIT 498 drivers/scsi/FlashPoint.c #define PCI_TGT_ABORT BIT(0) /*PCI bus master transaction aborted */ BIT 499 drivers/scsi/FlashPoint.c #define PCI_DEV_TMOUT BIT(1) /*PCI Device Time out */ BIT 500 drivers/scsi/FlashPoint.c #define CMD_ABORTED BIT(4) /*Command aborted */ BIT 501 drivers/scsi/FlashPoint.c #define BM_PARITY_ERR BIT(5) /*parity error on data received */ BIT 502 drivers/scsi/FlashPoint.c #define PIO_OVERRUN BIT(6) /*Slave data overrun */ BIT 503 drivers/scsi/FlashPoint.c #define BM_CMD_BUSY BIT(7) /*Bus master transfer command busy */ BIT 509 drivers/scsi/FlashPoint.c #define EXT_STATUS_ON BIT(1) /*Extended status is valid */ BIT 510 drivers/scsi/FlashPoint.c #define SCSI_INTERRUPT BIT(2) /*Global indication of a SCSI int. */ BIT 511 drivers/scsi/FlashPoint.c #define INT_ASSERTED BIT(5) /* */ BIT 517 drivers/scsi/FlashPoint.c #define RESET BIT(7) BIT 518 drivers/scsi/FlashPoint.c #define PROG_HLT BIT(6) BIT 519 drivers/scsi/FlashPoint.c #define PARITY BIT(5) BIT 520 drivers/scsi/FlashPoint.c #define FIFO BIT(4) BIT 521 drivers/scsi/FlashPoint.c #define SEL BIT(3) BIT 522 drivers/scsi/FlashPoint.c #define SCAM_SEL BIT(2) BIT 523 drivers/scsi/FlashPoint.c #define RSEL BIT(1) BIT 524 drivers/scsi/FlashPoint.c #define TIMEOUT BIT(0) BIT 525 drivers/scsi/FlashPoint.c #define BUS_FREE BIT(15) BIT 526 drivers/scsi/FlashPoint.c #define XFER_CNT_0 BIT(14) BIT 527 drivers/scsi/FlashPoint.c #define PHASE BIT(13) BIT 528 drivers/scsi/FlashPoint.c #define IUNKWN BIT(12) BIT 529 drivers/scsi/FlashPoint.c #define ICMD_COMP BIT(11) BIT 530 drivers/scsi/FlashPoint.c #define ITICKLE BIT(10) BIT 531 drivers/scsi/FlashPoint.c #define IDO_STRT BIT(9) BIT 532 drivers/scsi/FlashPoint.c #define ITAR_DISC BIT(8) BIT 533 drivers/scsi/FlashPoint.c #define AUTO_INT (BIT(12)+BIT(11)+BIT(10)+BIT(9)+BIT(8)) BIT 541 drivers/scsi/FlashPoint.c #define SCSI_SEL BIT(7) BIT 542 drivers/scsi/FlashPoint.c #define SCSI_BSY BIT(6) BIT 543 drivers/scsi/FlashPoint.c #define SCSI_REQ BIT(5) BIT 544 drivers/scsi/FlashPoint.c #define SCSI_ACK BIT(4) BIT 545 drivers/scsi/FlashPoint.c #define SCSI_ATN BIT(3) BIT 546 drivers/scsi/FlashPoint.c #define SCSI_CD BIT(2) BIT 547 drivers/scsi/FlashPoint.c #define SCSI_MSG BIT(1) BIT 548 drivers/scsi/FlashPoint.c #define SCSI_IOBIT BIT(0) BIT 550 drivers/scsi/FlashPoint.c #define S_SCSI_PHZ (BIT(2)+BIT(1)+BIT(0)) BIT 551 drivers/scsi/FlashPoint.c #define S_MSGO_PH (BIT(2)+BIT(1) ) BIT 552 drivers/scsi/FlashPoint.c #define S_MSGI_PH (BIT(2)+BIT(1)+BIT(0)) BIT 553 drivers/scsi/FlashPoint.c #define S_DATAI_PH ( BIT(0)) BIT 555 drivers/scsi/FlashPoint.c #define S_ILL_PH ( BIT(1) ) BIT 559 drivers/scsi/FlashPoint.c #define SEL_TAR BIT(6) BIT 560 drivers/scsi/FlashPoint.c #define ENA_ATN BIT(4) BIT 561 drivers/scsi/FlashPoint.c #define ENA_RESEL BIT(2) BIT 562 drivers/scsi/FlashPoint.c #define SCSI_RST BIT(1) BIT 563 drivers/scsi/FlashPoint.c #define ENA_SCAM_SEL BIT(0) BIT 567 drivers/scsi/FlashPoint.c #define SCSI_PORT BIT(7) BIT 568 drivers/scsi/FlashPoint.c #define SCSI_INBIT BIT(6) BIT 569 drivers/scsi/FlashPoint.c #define DMA_PORT BIT(5) BIT 570 drivers/scsi/FlashPoint.c #define DMA_RD BIT(4) BIT 571 drivers/scsi/FlashPoint.c #define HOST_PORT BIT(3) BIT 572 drivers/scsi/FlashPoint.c #define HOST_WRT BIT(2) BIT 573 drivers/scsi/FlashPoint.c #define SCSI_BUS_EN BIT(1) BIT 574 drivers/scsi/FlashPoint.c #define START_TO BIT(0) BIT 578 drivers/scsi/FlashPoint.c #define SCSI_INI BIT(6) BIT 579 drivers/scsi/FlashPoint.c #define SCAM_EN BIT(5) BIT 580 drivers/scsi/FlashPoint.c #define DMA_RESET BIT(3) BIT 581 drivers/scsi/FlashPoint.c #define HPSCSI_RESET BIT(2) BIT 582 drivers/scsi/FlashPoint.c #define PROG_RESET BIT(1) BIT 583 drivers/scsi/FlashPoint.c #define FIFO_CLR BIT(0) BIT 591 drivers/scsi/FlashPoint.c #define SCAM_TIMER BIT(7) BIT 592 drivers/scsi/FlashPoint.c #define SCSI_MODE8 BIT(3) BIT 593 drivers/scsi/FlashPoint.c #define SCSI_PAR_ERR BIT(0) BIT 624 drivers/scsi/FlashPoint.c #define NARROW_SCSI BIT(4) BIT 631 drivers/scsi/FlashPoint.c #define AUTO_IMMED BIT(5) BIT 632 drivers/scsi/FlashPoint.c #define SELECT BIT(6) BIT 633 drivers/scsi/FlashPoint.c #define END_DATA (BIT(7)+BIT(6)) BIT 650 drivers/scsi/FlashPoint.c #define PWR_DWN BIT(6) BIT 651 drivers/scsi/FlashPoint.c #define ACTdeassert BIT(4) BIT 652 drivers/scsi/FlashPoint.c #define CLK_40MHZ (BIT(1) + BIT(0)) BIT 662 drivers/scsi/FlashPoint.c #define FIFO_EMPTY BIT(6) BIT 666 drivers/scsi/FlashPoint.c #define CHK_SCSI_P BIT(3) BIT 667 drivers/scsi/FlashPoint.c #define HOST_MODE8 BIT(0) BIT 671 drivers/scsi/FlashPoint.c #define ID_UNLOCK BIT(3) BIT 680 drivers/scsi/FlashPoint.c #define AR3 (BIT(9) + BIT(8)) BIT 681 drivers/scsi/FlashPoint.c #define SDATA BIT(10) BIT 683 drivers/scsi/FlashPoint.c #define CRD_OP BIT(11) /* Cmp Reg. w/ Data */ BIT 685 drivers/scsi/FlashPoint.c #define CRR_OP BIT(12) /* Cmp Reg. w. Reg. */ BIT 687 drivers/scsi/FlashPoint.c #define CPE_OP (BIT(14)+BIT(11)) /* Cmp SCSI phs & Branch EQ */ BIT 689 drivers/scsi/FlashPoint.c #define CPN_OP (BIT(14)+BIT(12)) /* Cmp SCSI phs & Branch NOT EQ */ BIT 692 drivers/scsi/FlashPoint.c #define ADATA_IN BIT(8) BIT 693 drivers/scsi/FlashPoint.c #define ACOMMAND BIT(10) BIT 694 drivers/scsi/FlashPoint.c #define ASTATUS (BIT(10)+BIT(8)) BIT 695 drivers/scsi/FlashPoint.c #define AMSG_OUT (BIT(10)+BIT(9)) BIT 696 drivers/scsi/FlashPoint.c #define AMSG_IN (BIT(10)+BIT(9)+BIT(8)) BIT 698 drivers/scsi/FlashPoint.c #define BRH_OP BIT(13) /* Branch */ BIT 701 drivers/scsi/FlashPoint.c #define EQUAL BIT(8) BIT 702 drivers/scsi/FlashPoint.c #define NOT_EQ BIT(9) BIT 704 drivers/scsi/FlashPoint.c #define TCB_OP (BIT(13)+BIT(11)) /* Test condition & branch */ BIT 706 drivers/scsi/FlashPoint.c #define FIFO_0 BIT(10) BIT 708 drivers/scsi/FlashPoint.c #define MPM_OP BIT(15) /* Match phase and move data */ BIT 710 drivers/scsi/FlashPoint.c #define MRR_OP BIT(14) /* Move DReg. to Reg. */ BIT 712 drivers/scsi/FlashPoint.c #define S_IDREG (BIT(2)+BIT(1)+BIT(0)) BIT 715 drivers/scsi/FlashPoint.c #define D_AR1 BIT(0) BIT 716 drivers/scsi/FlashPoint.c #define D_BUCKET (BIT(2) + BIT(1) + BIT(0)) BIT 718 drivers/scsi/FlashPoint.c #define RAT_OP (BIT(14)+BIT(13)+BIT(11)) BIT 720 drivers/scsi/FlashPoint.c #define SSI_OP (BIT(15)+BIT(11)) BIT 1139 drivers/scsi/FlashPoint.c if (RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7)) BIT 1143 drivers/scsi/FlashPoint.c WR_HARPOON(ioport + hp_xfer_pad, (temp & ~BIT(4))); BIT 1144 drivers/scsi/FlashPoint.c if (RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7)) BIT 1146 drivers/scsi/FlashPoint.c WR_HARPOON(ioport + hp_xfer_pad, (temp | BIT(4))); BIT 1147 drivers/scsi/FlashPoint.c if (RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7)) BIT 1154 drivers/scsi/FlashPoint.c WR_HARPOON(ioport + hp_xfer_pad, (temp2 | BIT(4))); BIT 1158 drivers/scsi/FlashPoint.c if (!(RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7))) BIT 1160 drivers/scsi/FlashPoint.c WR_HARPOON(ioport + hp_xfer_pad, (temp2 & ~BIT(4))); BIT 1161 drivers/scsi/FlashPoint.c WR_HARPOON(ioport + hp_xfer_pad, (temp2 | BIT(4))); BIT 1165 drivers/scsi/FlashPoint.c if (!(temp3 & BIT(7))) BIT 1167 drivers/scsi/FlashPoint.c if (!(temp3 & BIT(6))) BIT 5846 drivers/scsi/FlashPoint.c (unsigned char)(BIT(7) + BIT(6)))); BIT 5853 drivers/scsi/FlashPoint.c ~(unsigned char)BIT(6))); BIT 5854 drivers/scsi/FlashPoint.c FPT_scwirod(p_port, BIT(6)); BIT 5872 drivers/scsi/FlashPoint.c curr_data = p_data | BIT(7) | BIT(5); /*Start with DB7 & DB5 asserted. */ BIT 5876 drivers/scsi/FlashPoint.c curr_data &= ~BIT(7); BIT 5880 drivers/scsi/FlashPoint.c FPT_scwirod(p_port, BIT(7)); /*Wait for DB7 to be released. */ BIT 5881 drivers/scsi/FlashPoint.c while (!(RD_HARPOON(p_port + hp_scsidata_0) & BIT(5))) ; BIT 5885 drivers/scsi/FlashPoint.c curr_data |= BIT(6); BIT 5889 drivers/scsi/FlashPoint.c curr_data &= ~BIT(5); BIT 5893 drivers/scsi/FlashPoint.c FPT_scwirod(p_port, BIT(5)); /*Wait for DB5 to be released. */ BIT 5895 drivers/scsi/FlashPoint.c curr_data &= ~(BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)); /*Release data bits */ BIT 5896 drivers/scsi/FlashPoint.c curr_data |= BIT(7); BIT 5900 drivers/scsi/FlashPoint.c curr_data &= ~BIT(6); BIT 5904 drivers/scsi/FlashPoint.c FPT_scwirod(p_port, BIT(6)); /*Wait for DB6 to be released. */ BIT 5987 drivers/scsi/FlashPoint.c if (ret_data & BIT(1)) { BIT 6294 drivers/scsi/FlashPoint.c if (p_id_string[0] & BIT(5)) BIT 6326 drivers/scsi/FlashPoint.c if (p_id_string[0] & BIT(5)) BIT 6333 drivers/scsi/FlashPoint.c if (p_id_string[0] & BIT(7)) { BIT 6337 drivers/scsi/FlashPoint.c if (p_id_string[0] & BIT(5)) BIT 6358 drivers/scsi/FlashPoint.c FPT_scamInfo[match].id_string[0] |= BIT(7); BIT 6370 drivers/scsi/FlashPoint.c if (p_id_string[0] & BIT(5)) BIT 961 drivers/scsi/NCR5380.c (disconnect_mask & BIT(scmd_id(cmd))); BIT 10 drivers/scsi/aha1542.h #define STST BIT(7) /* Self Test in Progress */ BIT 11 drivers/scsi/aha1542.h #define DIAGF BIT(6) /* Internal Diagnostic Failure */ BIT 12 drivers/scsi/aha1542.h #define INIT BIT(5) /* Mailbox Initialization Required */ BIT 13 drivers/scsi/aha1542.h #define IDLE BIT(4) /* SCSI Host Adapter Idle */ BIT 14 drivers/scsi/aha1542.h #define CDF BIT(3) /* Command/Data Out Port Full */ BIT 15 drivers/scsi/aha1542.h #define DF BIT(2) /* Data In Port Full */ BIT 17 drivers/scsi/aha1542.h #define INVDCMD BIT(0) /* Invalid H A Command */ BIT 21 drivers/scsi/aha1542.h #define ANYINTR BIT(7) /* Any Interrupt */ BIT 22 drivers/scsi/aha1542.h #define SCRD BIT(3) /* SCSI Reset Detected */ BIT 23 drivers/scsi/aha1542.h #define HACC BIT(2) /* HA Command Complete */ BIT 24 drivers/scsi/aha1542.h #define MBOA BIT(1) /* MBO Empty */ BIT 25 drivers/scsi/aha1542.h #define MBIF BIT(0) /* MBI Full */ BIT 30 drivers/scsi/aha1542.h #define HRST BIT(7) /* Hard Reset */ BIT 31 drivers/scsi/aha1542.h #define SRST BIT(6) /* Soft Reset */ BIT 32 drivers/scsi/aha1542.h #define IRST BIT(5) /* Interrupt Reset */ BIT 33 drivers/scsi/aha1542.h #define SCRST BIT(4) /* SCSI Bus Reset */ BIT 1097 drivers/scsi/bfa/bfa_fc.h FCP_TM_ABORT_TASK_SET = BIT(1), BIT 1098 drivers/scsi/bfa/bfa_fc.h FCP_TM_CLEAR_TASK_SET = BIT(2), BIT 1099 drivers/scsi/bfa/bfa_fc.h FCP_TM_LUN_RESET = BIT(4), BIT 1100 drivers/scsi/bfa/bfa_fc.h FCP_TM_TARGET_RESET = BIT(5), /* obsolete in FCP-3 */ BIT 1101 drivers/scsi/bfa/bfa_fc.h FCP_TM_CLEAR_ACA = BIT(6), BIT 911 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask = BIT(FIP_DT_PRI) | BIT(FIP_DT_MAC) | BIT(FIP_DT_NAME) | BIT 912 drivers/scsi/fcoe/fcoe_ctlr.c BIT(FIP_DT_FAB) | BIT(FIP_DT_FKA); BIT 935 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask &= ~BIT(FIP_DT_PRI); BIT 950 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask &= ~BIT(FIP_DT_MAC); BIT 957 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask &= ~BIT(FIP_DT_NAME); BIT 966 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask &= ~BIT(FIP_DT_FAB); BIT 977 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask &= ~BIT(FIP_DT_FKA); BIT 1372 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask = BIT(FIP_DT_MAC) | BIT(FIP_DT_NAME); BIT 1409 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask &= ~BIT(FIP_DT_MAC); BIT 1417 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask &= ~BIT(FIP_DT_NAME); BIT 2294 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask = BIT(FIP_DT_MAC) | BIT(FIP_DT_NAME) | BIT 2295 drivers/scsi/fcoe/fcoe_ctlr.c BIT(FIP_DT_VN_ID); BIT 2299 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask = BIT(FIP_DT_MAC) | BIT(FIP_DT_NAME) | BIT 2300 drivers/scsi/fcoe/fcoe_ctlr.c BIT(FIP_DT_VN_ID) | BIT(FIP_DT_FC4F) | BIT 2301 drivers/scsi/fcoe/fcoe_ctlr.c BIT(FIP_DT_FCOE_SIZE); BIT 2320 drivers/scsi/fcoe/fcoe_ctlr.c if (!(desc_mask & BIT(dtype))) { BIT 2328 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask &= ~BIT(dtype); BIT 2821 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask = BIT(FIP_DT_MAC) | BIT(FIP_DT_NAME); BIT 2840 drivers/scsi/fcoe/fcoe_ctlr.c if (!(desc_mask & BIT(dtype))) { BIT 2848 drivers/scsi/fcoe/fcoe_ctlr.c desc_mask &= ~BIT(dtype); BIT 184 drivers/scsi/fdomain.c outb(BIT(sh->this_id) | BIT(target), fd->base + REG_SCSI_DATA_NOACK); BIT 283 drivers/scsi/fdomain.c outb(BIT(cmd->device->host->this_id) | BIT(scmd_id(cmd)), BIT 419 drivers/scsi/fdomain.c outb(BIT(cmd->device->host->this_id), fd->base + REG_SCSI_DATA_NOACK); BIT 18 drivers/scsi/fdomain.h #define BSTAT_BSY BIT(0) /* Busy */ BIT 19 drivers/scsi/fdomain.h #define BSTAT_MSG BIT(1) /* Message */ BIT 20 drivers/scsi/fdomain.h #define BSTAT_IO BIT(2) /* Input/Output */ BIT 21 drivers/scsi/fdomain.h #define BSTAT_CMD BIT(3) /* Command/Data */ BIT 22 drivers/scsi/fdomain.h #define BSTAT_REQ BIT(4) /* Request and Not Ack */ BIT 23 drivers/scsi/fdomain.h #define BSTAT_SEL BIT(5) /* Select */ BIT 24 drivers/scsi/fdomain.h #define BSTAT_ACK BIT(6) /* Acknowledge and Request */ BIT 25 drivers/scsi/fdomain.h #define BSTAT_ATN BIT(7) /* Attention */ BIT 27 drivers/scsi/fdomain.h #define BCTL_RST BIT(0) /* Bus Reset */ BIT 28 drivers/scsi/fdomain.h #define BCTL_SEL BIT(1) /* Select */ BIT 29 drivers/scsi/fdomain.h #define BCTL_BSY BIT(2) /* Busy */ BIT 30 drivers/scsi/fdomain.h #define BCTL_ATN BIT(3) /* Attention */ BIT 31 drivers/scsi/fdomain.h #define BCTL_IO BIT(4) /* Input/Output */ BIT 32 drivers/scsi/fdomain.h #define BCTL_CMD BIT(5) /* Command/Data */ BIT 33 drivers/scsi/fdomain.h #define BCTL_MSG BIT(6) /* Message */ BIT 34 drivers/scsi/fdomain.h #define BCTL_BUSEN BIT(7) /* Enable bus drivers */ BIT 36 drivers/scsi/fdomain.h #define ASTAT_IRQ BIT(0) /* Interrupt active */ BIT 37 drivers/scsi/fdomain.h #define ASTAT_ARB BIT(1) /* Arbitration complete */ BIT 38 drivers/scsi/fdomain.h #define ASTAT_PARERR BIT(2) /* Parity error */ BIT 39 drivers/scsi/fdomain.h #define ASTAT_RST BIT(3) /* SCSI reset occurred */ BIT 40 drivers/scsi/fdomain.h #define ASTAT_FIFODIR BIT(4) /* FIFO direction */ BIT 41 drivers/scsi/fdomain.h #define ASTAT_FIFOEN BIT(5) /* FIFO enabled */ BIT 42 drivers/scsi/fdomain.h #define ASTAT_PAREN BIT(6) /* Parity enabled */ BIT 43 drivers/scsi/fdomain.h #define ASTAT_BUSEN BIT(7) /* Bus drivers enabled */ BIT 46 drivers/scsi/fdomain.h #define ICTL_FIFO BIT(4) /* Int. on FIFO count */ BIT 47 drivers/scsi/fdomain.h #define ICTL_ARB BIT(5) /* Int. on Arbitration complete */ BIT 48 drivers/scsi/fdomain.h #define ICTL_SEL BIT(6) /* Int. on SCSI Select */ BIT 49 drivers/scsi/fdomain.h #define ICTL_REQ BIT(7) /* Int. on SCSI Request */ BIT 51 drivers/scsi/fdomain.h #define FSTAT_ONOTEMPTY BIT(0) /* Output FIFO not empty */ BIT 52 drivers/scsi/fdomain.h #define FSTAT_INOTEMPTY BIT(1) /* Input FIFO not empty */ BIT 53 drivers/scsi/fdomain.h #define FSTAT_NOTEMPTY BIT(2) /* Main FIFO not empty */ BIT 54 drivers/scsi/fdomain.h #define FSTAT_NOTFULL BIT(3) /* Main FIFO not full */ BIT 57 drivers/scsi/fdomain.h #define MCTL_ACTDEASS BIT(4) /* Active deassert of REQ and ACK */ BIT 58 drivers/scsi/fdomain.h #define MCTL_TARGET BIT(5) /* Enable target mode */ BIT 59 drivers/scsi/fdomain.h #define MCTL_FASTSYNC BIT(6) /* Enable Fast Synchronous */ BIT 60 drivers/scsi/fdomain.h #define MCTL_SYNC BIT(7) /* Enable Synchronous */ BIT 62 drivers/scsi/fdomain.h #define IRQ_FIFO BIT(1) /* FIFO interrupt */ BIT 63 drivers/scsi/fdomain.h #define IRQ_REQ BIT(2) /* SCSI Request interrupt */ BIT 64 drivers/scsi/fdomain.h #define IRQ_SEL BIT(3) /* SCSI Select interrupt */ BIT 65 drivers/scsi/fdomain.h #define IRQ_ARB BIT(4) /* SCSI Arbitration interrupt */ BIT 66 drivers/scsi/fdomain.h #define IRQ_RST BIT(5) /* SCSI Reset interrupt */ BIT 67 drivers/scsi/fdomain.h #define IRQ_FORCED BIT(6) /* Forced interrupt */ BIT 68 drivers/scsi/fdomain.h #define IRQ_TIMEOUT BIT(7) /* Bus timeout */ BIT 70 drivers/scsi/fdomain.h #define ACTL_RESET BIT(0) /* Reset FIFO, parity, reset int. */ BIT 71 drivers/scsi/fdomain.h #define ACTL_FIRQ BIT(1) /* Set Forced interrupt */ BIT 72 drivers/scsi/fdomain.h #define ACTL_ARB BIT(2) /* Initiate Bus Arbitration */ BIT 73 drivers/scsi/fdomain.h #define ACTL_PAREN BIT(3) /* Enable SCSI Parity */ BIT 74 drivers/scsi/fdomain.h #define ACTL_IRQEN BIT(4) /* Enable interrupts */ BIT 75 drivers/scsi/fdomain.h #define ACTL_CLRFIRQ BIT(5) /* Clear Forced interrupt */ BIT 76 drivers/scsi/fdomain.h #define ACTL_FIFOWR BIT(6) /* FIFO Direction (1=write) */ BIT 77 drivers/scsi/fdomain.h #define ACTL_FIFOEN BIT(7) /* Enable FIFO */ BIT 80 drivers/scsi/fdomain.h #define ACTL2_RAMOVRLY BIT(0) /* Enable RAM overlay */ BIT 81 drivers/scsi/fdomain.h #define ACTL2_SLEEP BIT(7) /* Sleep mode */ BIT 86 drivers/scsi/fdomain.h #define ASTAT3_ACTDEASS BIT(0) /* Active deassert enabled */ BIT 87 drivers/scsi/fdomain.h #define ASTAT3_RAMOVRLY BIT(1) /* RAM overlay enabled */ BIT 88 drivers/scsi/fdomain.h #define ASTAT3_TARGERR BIT(2) /* Target error */ BIT 89 drivers/scsi/fdomain.h #define ASTAT3_IRQEN BIT(3) /* Interrupts enabled */ BIT 92 drivers/scsi/fdomain.h #define CFG1_BUS BIT(0) /* 0 = ISA */ BIT 97 drivers/scsi/fdomain.h #define CFG2_ROMDIS BIT(0) /* ROM disabled */ BIT 98 drivers/scsi/fdomain.h #define CFG2_RAMDIS BIT(1) /* RAM disabled */ BIT 99 drivers/scsi/fdomain.h #define CFG2_IRQEDGE BIT(2) /* Edge-triggered interrupts */ BIT 100 drivers/scsi/fdomain.h #define CFG2_NOWS BIT(3) /* No wait states */ BIT 101 drivers/scsi/fdomain.h #define CFG2_32BIT BIT(7) /* 32-bit mode */ BIT 58 drivers/scsi/fnic/fnic.h #define FNIC_TAG_ABORT BIT(30) /* tag bit indicating abort */ BIT 59 drivers/scsi/fnic/fnic.h #define FNIC_TAG_DEV_RST BIT(29) /* indicates device reset */ BIT 60 drivers/scsi/fnic/fnic.h #define FNIC_TAG_MASK (BIT(24) - 1) /* mask for lookup */ BIT 68 drivers/scsi/fnic/fnic.h #define FNIC_IO_INITIALIZED BIT(0) BIT 69 drivers/scsi/fnic/fnic.h #define FNIC_IO_ISSUED BIT(1) BIT 70 drivers/scsi/fnic/fnic.h #define FNIC_IO_DONE BIT(2) BIT 71 drivers/scsi/fnic/fnic.h #define FNIC_IO_REQ_NULL BIT(3) BIT 72 drivers/scsi/fnic/fnic.h #define FNIC_IO_ABTS_PENDING BIT(4) BIT 73 drivers/scsi/fnic/fnic.h #define FNIC_IO_ABORTED BIT(5) BIT 74 drivers/scsi/fnic/fnic.h #define FNIC_IO_ABTS_ISSUED BIT(6) BIT 75 drivers/scsi/fnic/fnic.h #define FNIC_IO_TERM_ISSUED BIT(7) BIT 76 drivers/scsi/fnic/fnic.h #define FNIC_IO_INTERNAL_TERM_ISSUED BIT(8) BIT 77 drivers/scsi/fnic/fnic.h #define FNIC_IO_ABT_TERM_DONE BIT(9) BIT 78 drivers/scsi/fnic/fnic.h #define FNIC_IO_ABT_TERM_REQ_NULL BIT(10) BIT 79 drivers/scsi/fnic/fnic.h #define FNIC_IO_ABT_TERM_TIMED_OUT BIT(11) BIT 80 drivers/scsi/fnic/fnic.h #define FNIC_DEVICE_RESET BIT(12) /* Device reset request */ BIT 81 drivers/scsi/fnic/fnic.h #define FNIC_DEV_RST_ISSUED BIT(13) BIT 82 drivers/scsi/fnic/fnic.h #define FNIC_DEV_RST_TIMED_OUT BIT(14) BIT 83 drivers/scsi/fnic/fnic.h #define FNIC_DEV_RST_ABTS_ISSUED BIT(15) BIT 84 drivers/scsi/fnic/fnic.h #define FNIC_DEV_RST_TERM_ISSUED BIT(16) BIT 85 drivers/scsi/fnic/fnic.h #define FNIC_DEV_RST_DONE BIT(17) BIT 86 drivers/scsi/fnic/fnic.h #define FNIC_DEV_RST_REQ_NULL BIT(18) BIT 87 drivers/scsi/fnic/fnic.h #define FNIC_DEV_RST_ABTS_DONE BIT(19) BIT 88 drivers/scsi/fnic/fnic.h #define FNIC_DEV_RST_TERM_DONE BIT(20) BIT 89 drivers/scsi/fnic/fnic.h #define FNIC_DEV_RST_ABTS_PENDING BIT(21) BIT 115 drivers/scsi/fnic/fnic.h #define __FNIC_FLAGS_FWRESET BIT(0) /* fwreset in progress */ BIT 116 drivers/scsi/fnic/fnic.h #define __FNIC_FLAGS_BLOCK_IO BIT(1) /* IOs are blocked */ BIT 1384 drivers/scsi/hisi_sas/hisi_sas_main.c if (state & BIT(sas_phy->id)) { BIT 1418 drivers/scsi/hisi_sas/hisi_sas_main.c if (state & BIT(phy_no)) { BIT 1468 drivers/scsi/hisi_sas/hisi_sas_main.c if (!(state & BIT(sas_phy->id))) BIT 422 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF), BIT 429 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF), BIT 436 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF), BIT 443 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF), BIT 450 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF), BIT 457 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF), BIT 464 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF), BIT 471 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF), BIT 478 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF), BIT 485 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF), BIT 495 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), BIT 502 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), BIT 509 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), BIT 516 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), BIT 523 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), BIT 530 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), BIT 537 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), BIT 544 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), BIT 551 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), BIT 558 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), BIT 1135 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no))) BIT 1330 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (hisi_hba->reject_stp_links_msk & BIT(i)) BIT 1334 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (!(reg_val & BIT(0))) { BIT 1352 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (hisi_hba->reject_stp_links_msk & BIT(i)) BIT 1355 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (reg_val & BIT(i)) { BIT 1415 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (dfx_val & BIT(16)) BIT 1437 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10))) BIT 2789 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (reg_value & BIT(phy_no)) { BIT 2833 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF), BIT 2837 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF), BIT 2841 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), BIT 2845 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), BIT 2849 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), BIT 2853 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), BIT 2903 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { BIT 3000 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, BIT 3001 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, BIT 3002 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, BIT 3003 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, BIT 3004 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, BIT 3005 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, BIT 3006 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, BIT 3007 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, BIT 3012 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, BIT 3013 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, BIT 3014 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(10), .msg = "GETDQE_FIFO" }, BIT 3015 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(11), .msg = "CMDP_FIFO" }, BIT 3016 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, BIT 3022 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), BIT 3026 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), BIT 3030 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), BIT 3034 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), BIT 3039 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), BIT 3044 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), BIT 3048 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), BIT 3091 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { BIT 925 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | BIT 926 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c BIT(CHL_INT2_RX_CODE_ERR_OFF) | BIT 927 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c BIT(CHL_INT2_RX_INVLD_DW_OFF); BIT 938 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (state & BIT(phy_no)) { BIT 1015 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (phy_state & BIT(i)) BIT 1017 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c bitmap |= BIT(i); BIT 1629 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF), BIT 1633 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF), BIT 1637 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), BIT 1641 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), BIT 1645 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), BIT 1649 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), BIT 1653 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF), BIT 1657 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF), BIT 1661 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF), BIT 1665 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF), BIT 1735 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | BIT 1736 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c BIT(CHL_INT2_RX_CODE_ERR_OFF) | BIT 1737 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c BIT(CHL_INT2_RX_INVLD_DW_OFF); BIT 1743 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { BIT 1748 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { BIT 1754 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (reg_value & BIT(4)) BIT 1764 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) BIT 1768 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF)) BIT 1772 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF)) BIT 1777 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && BIT 1784 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c !((reg_value >> 8) & BIT(phy_no)), BIT 1834 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), BIT 1841 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), BIT 1848 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), BIT 1855 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), BIT 1862 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), BIT 1869 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), BIT 1876 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), BIT 1883 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), BIT 1890 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), BIT 1897 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), BIT 1904 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF), BIT 1949 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, BIT 1950 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, BIT 1951 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, BIT 1952 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, BIT 1953 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, BIT 1954 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, BIT 1955 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, BIT 1956 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, BIT 1961 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, BIT 1962 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, BIT 1963 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(10), .msg = "GETDQE_FIFO" }, BIT 1964 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(11), .msg = "CMDP_FIFO" }, BIT 1965 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, BIT 1971 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), BIT 1975 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), BIT 1979 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), BIT 1983 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), BIT 1988 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), BIT 1993 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), BIT 1997 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), BIT 2001 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF), BIT 2005 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF), BIT 2009 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF), BIT 2013 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF), BIT 2071 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { BIT 2673 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (intr_coal_ticks >= BIT(24)) { BIT 2712 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (intr_coal_count >= BIT(8)) { BIT 135 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.h #define SCSOLNT BIT(SCSOLNT_RESP_SHIFT) BIT 136 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.h #define UCSOLNT BIT(UCSOLNT_RESP_SHIFT) BIT 166 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.h #define CMD_FAST_FAIL BIT(0) BIT 167 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.h #define DELAY_SEND BIT(1) BIT 269 drivers/scsi/mac_scsi.c #define CTRL_INTERRUPTS_ENABLE BIT(1) BIT 270 drivers/scsi/mac_scsi.c #define CTRL_HANDSHAKE_MODE BIT(3) BIT 290 drivers/scsi/nsp32.c #define NSP32_DEBUG_QUEUECOMMAND BIT(0) BIT 291 drivers/scsi/nsp32.c #define NSP32_DEBUG_REGISTER BIT(1) BIT 292 drivers/scsi/nsp32.c #define NSP32_DEBUG_AUTOSCSI BIT(2) BIT 293 drivers/scsi/nsp32.c #define NSP32_DEBUG_INTR BIT(3) BIT 294 drivers/scsi/nsp32.c #define NSP32_DEBUG_SGLIST BIT(4) BIT 295 drivers/scsi/nsp32.c #define NSP32_DEBUG_BUSFREE BIT(5) BIT 296 drivers/scsi/nsp32.c #define NSP32_DEBUG_CDB_CONTENTS BIT(6) BIT 297 drivers/scsi/nsp32.c #define NSP32_DEBUG_RESELECTION BIT(7) BIT 298 drivers/scsi/nsp32.c #define NSP32_DEBUG_MSGINOCCUR BIT(8) BIT 299 drivers/scsi/nsp32.c #define NSP32_DEBUG_EEPROM BIT(9) BIT 300 drivers/scsi/nsp32.c #define NSP32_DEBUG_MSGOUTOCCUR BIT(10) BIT 301 drivers/scsi/nsp32.c #define NSP32_DEBUG_BUSRESET BIT(11) BIT 302 drivers/scsi/nsp32.c #define NSP32_DEBUG_RESTART BIT(12) BIT 303 drivers/scsi/nsp32.c #define NSP32_DEBUG_SYNC BIT(13) BIT 304 drivers/scsi/nsp32.c #define NSP32_DEBUG_WAIT BIT(14) BIT 305 drivers/scsi/nsp32.c #define NSP32_DEBUG_TARGETFLAG BIT(15) BIT 306 drivers/scsi/nsp32.c #define NSP32_DEBUG_PROC BIT(16) BIT 307 drivers/scsi/nsp32.c #define NSP32_DEBUG_INIT BIT(17) BIT 308 drivers/scsi/nsp32.c #define NSP32_SPECIAL_PRINT_REGISTER BIT(20) BIT 515 drivers/scsi/nsp32.c param->target_id = BIT(host_id) | BIT(target); BIT 625 drivers/scsi/nsp32.c nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID, BIT(host_id) | BIT(target)); BIT 810 drivers/scsi/nsp32.c tmpid &= (~BIT(host_id)); BIT 83 drivers/scsi/nsp32.h # define IRQSTATUS_LATCHED_MSG BIT(0) BIT 84 drivers/scsi/nsp32.h # define IRQSTATUS_LATCHED_IO BIT(1) BIT 85 drivers/scsi/nsp32.h # define IRQSTATUS_LATCHED_CD BIT(2) BIT 86 drivers/scsi/nsp32.h # define IRQSTATUS_LATCHED_BUS_FREE BIT(3) BIT 87 drivers/scsi/nsp32.h # define IRQSTATUS_RESELECT_OCCUER BIT(4) BIT 88 drivers/scsi/nsp32.h # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5) BIT 89 drivers/scsi/nsp32.h # define IRQSTATUS_SCSIRESET_IRQ BIT(6) BIT 90 drivers/scsi/nsp32.h # define IRQSTATUS_TIMER_IRQ BIT(7) BIT 91 drivers/scsi/nsp32.h # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8) BIT 92 drivers/scsi/nsp32.h # define IRQSTATUS_PCI_IRQ BIT(9) BIT 93 drivers/scsi/nsp32.h # define IRQSTATUS_BMCNTERR_IRQ BIT(10) BIT 94 drivers/scsi/nsp32.h # define IRQSTATUS_AUTOSCSI_IRQ BIT(11) BIT 95 drivers/scsi/nsp32.h # define PCI_IRQ_MASK BIT(12) BIT 96 drivers/scsi/nsp32.h # define TIMER_IRQ_MASK BIT(13) BIT 97 drivers/scsi/nsp32.h # define FIFO_IRQ_MASK BIT(14) BIT 98 drivers/scsi/nsp32.h # define SCSI_IRQ_MASK BIT(15) BIT 114 drivers/scsi/nsp32.h # define CB_MMIO_MODE BIT(0) BIT 115 drivers/scsi/nsp32.h # define CB_IO_MODE BIT(1) BIT 116 drivers/scsi/nsp32.h # define BM_TEST BIT(2) BIT 117 drivers/scsi/nsp32.h # define BM_TEST_DIR BIT(3) BIT 118 drivers/scsi/nsp32.h # define DUAL_EDGE_ENABLE BIT(4) BIT 119 drivers/scsi/nsp32.h # define NO_TRANSFER_TO_HOST BIT(5) BIT 120 drivers/scsi/nsp32.h # define TRANSFER_GO BIT(7) BIT 121 drivers/scsi/nsp32.h # define BLIEND_MODE BIT(8) BIT 122 drivers/scsi/nsp32.h # define BM_START BIT(9) BIT 123 drivers/scsi/nsp32.h # define ADVANCED_BM_WRITE BIT(10) BIT 124 drivers/scsi/nsp32.h # define BM_SINGLE_MODE BIT(11) BIT 125 drivers/scsi/nsp32.h # define FIFO_TRUE_FULL BIT(12) BIT 126 drivers/scsi/nsp32.h # define FIFO_TRUE_EMPTY BIT(13) BIT 127 drivers/scsi/nsp32.h # define ALL_COUNTER_CLR BIT(14) BIT 128 drivers/scsi/nsp32.h # define FIFOTEST BIT(15) BIT 134 drivers/scsi/nsp32.h # define TIMER_STOP BIT(8) BIT 141 drivers/scsi/nsp32.h # define FIFO_EMPTY_SHLD_FLAG BIT(14) BIT 142 drivers/scsi/nsp32.h # define FIFO_FULL_SHLD_FLAG BIT(15) BIT 145 drivers/scsi/nsp32.h # define SREQSMPLRATE_RATE0 BIT(0) BIT 146 drivers/scsi/nsp32.h # define SREQSMPLRATE_RATE1 BIT(1) BIT 147 drivers/scsi/nsp32.h # define SAMPLING_ENABLE BIT(2) BIT 153 drivers/scsi/nsp32.h # define BUSCTL_SEL BIT(0) BIT 154 drivers/scsi/nsp32.h # define BUSCTL_RST BIT(1) BIT 155 drivers/scsi/nsp32.h # define BUSCTL_DATAOUT_ENB BIT(2) BIT 156 drivers/scsi/nsp32.h # define BUSCTL_ATN BIT(3) BIT 157 drivers/scsi/nsp32.h # define BUSCTL_ACK BIT(4) BIT 158 drivers/scsi/nsp32.h # define BUSCTL_BSY BIT(5) BIT 159 drivers/scsi/nsp32.h # define AUTODIRECTION BIT(6) BIT 160 drivers/scsi/nsp32.h # define ACKENB BIT(7) BIT 163 drivers/scsi/nsp32.h # define ACK_COUNTER_CLR BIT(0) BIT 164 drivers/scsi/nsp32.h # define SREQ_COUNTER_CLR BIT(1) BIT 165 drivers/scsi/nsp32.h # define FIFO_HOST_POINTER_CLR BIT(2) BIT 166 drivers/scsi/nsp32.h # define FIFO_REST_COUNT_CLR BIT(3) BIT 167 drivers/scsi/nsp32.h # define BM_COUNTER_CLR BIT(4) BIT 168 drivers/scsi/nsp32.h # define SAVED_ACK_CLR BIT(5) BIT 177 drivers/scsi/nsp32.h # define BUSMON_MSG BIT(0) BIT 178 drivers/scsi/nsp32.h # define BUSMON_IO BIT(1) BIT 179 drivers/scsi/nsp32.h # define BUSMON_CD BIT(2) BIT 180 drivers/scsi/nsp32.h # define BUSMON_BSY BIT(3) BIT 181 drivers/scsi/nsp32.h # define BUSMON_ACK BIT(4) BIT 182 drivers/scsi/nsp32.h # define BUSMON_REQ BIT(5) BIT 183 drivers/scsi/nsp32.h # define BUSMON_SEL BIT(6) BIT 184 drivers/scsi/nsp32.h # define BUSMON_ATN BIT(7) BIT 189 drivers/scsi/nsp32.h # define PARITY_CHECK_ENABLE BIT(0) BIT 190 drivers/scsi/nsp32.h # define PARITY_ERROR_CLEAR BIT(1) BIT 193 drivers/scsi/nsp32.h # define PARITY_ERROR_NORMAL BIT(1) BIT 194 drivers/scsi/nsp32.h # define PARITY_ERROR_LSB BIT(1) BIT 195 drivers/scsi/nsp32.h # define PARITY_ERROR_MSB BIT(2) BIT 200 drivers/scsi/nsp32.h # define CLEAR_CDB_FIFO_POINTER BIT(0) BIT 201 drivers/scsi/nsp32.h # define AUTO_COMMAND_PHASE BIT(1) BIT 202 drivers/scsi/nsp32.h # define AUTOSCSI_START BIT(2) BIT 203 drivers/scsi/nsp32.h # define AUTOSCSI_RESTART BIT(3) BIT 204 drivers/scsi/nsp32.h # define AUTO_PARAMETER BIT(4) BIT 205 drivers/scsi/nsp32.h # define AUTO_ATN BIT(5) BIT 206 drivers/scsi/nsp32.h # define AUTO_MSGIN_00_OR_04 BIT(6) BIT 207 drivers/scsi/nsp32.h # define AUTO_MSGIN_02 BIT(7) BIT 208 drivers/scsi/nsp32.h # define AUTO_MSGIN_03 BIT(8) BIT 211 drivers/scsi/nsp32.h # define ARBIT_GO BIT(0) BIT 212 drivers/scsi/nsp32.h # define ARBIT_CLEAR BIT(1) BIT 216 drivers/scsi/nsp32.h # define ARBIT_WIN BIT(1) BIT 217 drivers/scsi/nsp32.h # define ARBIT_FAIL BIT(2) BIT 218 drivers/scsi/nsp32.h # define AUTO_PARAMETER_VALID BIT(3) BIT 219 drivers/scsi/nsp32.h # define SGT_VALID BIT(4) BIT 231 drivers/scsi/nsp32.h # define SCAM_MSG BIT(0) BIT 232 drivers/scsi/nsp32.h # define SCAM_IO BIT(1) BIT 233 drivers/scsi/nsp32.h # define SCAM_CD BIT(2) BIT 234 drivers/scsi/nsp32.h # define SCAM_BSY BIT(3) BIT 235 drivers/scsi/nsp32.h # define SCAM_SEL BIT(4) BIT 236 drivers/scsi/nsp32.h # define SCAM_XFEROK BIT(5) BIT 239 drivers/scsi/nsp32.h # define SD0 BIT(0) BIT 240 drivers/scsi/nsp32.h # define SD1 BIT(1) BIT 241 drivers/scsi/nsp32.h # define SD2 BIT(2) BIT 242 drivers/scsi/nsp32.h # define SD3 BIT(3) BIT 243 drivers/scsi/nsp32.h # define SD4 BIT(4) BIT 244 drivers/scsi/nsp32.h # define SD5 BIT(5) BIT 245 drivers/scsi/nsp32.h # define SD6 BIT(6) BIT 246 drivers/scsi/nsp32.h # define SD7 BIT(7) BIT 257 drivers/scsi/nsp32.h # define SGTEND BIT(31) /* Last SGT marker */ BIT 263 drivers/scsi/nsp32.h # define COMMAND_PHASE BIT(0) BIT 264 drivers/scsi/nsp32.h # define DATA_IN_PHASE BIT(1) BIT 265 drivers/scsi/nsp32.h # define DATA_OUT_PHASE BIT(2) BIT 266 drivers/scsi/nsp32.h # define MSGOUT_PHASE BIT(3) BIT 267 drivers/scsi/nsp32.h # define STATUS_PHASE BIT(4) BIT 268 drivers/scsi/nsp32.h # define ILLEGAL_PHASE BIT(5) BIT 269 drivers/scsi/nsp32.h # define BUS_FREE_OCCUER BIT(6) BIT 270 drivers/scsi/nsp32.h # define MSG_IN_OCCUER BIT(7) BIT 271 drivers/scsi/nsp32.h # define MSG_OUT_OCCUER BIT(8) BIT 272 drivers/scsi/nsp32.h # define SELECTION_TIMEOUT BIT(9) BIT 273 drivers/scsi/nsp32.h # define MSGIN_00_VALID BIT(10) BIT 274 drivers/scsi/nsp32.h # define MSGIN_02_VALID BIT(11) BIT 275 drivers/scsi/nsp32.h # define MSGIN_03_VALID BIT(12) BIT 276 drivers/scsi/nsp32.h # define MSGIN_04_VALID BIT(13) BIT 277 drivers/scsi/nsp32.h # define AUTOSCSI_BUSY BIT(15) BIT 282 drivers/scsi/nsp32.h # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1)) BIT 283 drivers/scsi/nsp32.h # define MV_VALID BIT(7) BIT 299 drivers/scsi/nsp32.h # define CLOCK_2 BIT(0) /* MCLK/2 */ BIT 300 drivers/scsi/nsp32.h # define CLOCK_4 BIT(1) /* MCLK/4 */ BIT 301 drivers/scsi/nsp32.h # define PCICLK BIT(7) /* PCICLK (33MHz) */ BIT 304 drivers/scsi/nsp32.h # define BPWR BIT(0) BIT 305 drivers/scsi/nsp32.h # define SENSE BIT(1) /* Read Only */ BIT 310 drivers/scsi/nsp32.h # define LED_OFF BIT(0) BIT 313 drivers/scsi/nsp32.h # define IRQSELECT_RESELECT_IRQ BIT(0) BIT 314 drivers/scsi/nsp32.h # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1) BIT 315 drivers/scsi/nsp32.h # define IRQSELECT_SCSIRESET_IRQ BIT(2) BIT 316 drivers/scsi/nsp32.h # define IRQSELECT_TIMER_IRQ BIT(3) BIT 317 drivers/scsi/nsp32.h # define IRQSELECT_FIFO_SHLD_IRQ BIT(4) BIT 318 drivers/scsi/nsp32.h # define IRQSELECT_TARGET_ABORT_IRQ BIT(5) BIT 319 drivers/scsi/nsp32.h # define IRQSELECT_MASTER_ABORT_IRQ BIT(6) BIT 320 drivers/scsi/nsp32.h # define IRQSELECT_SERR_IRQ BIT(7) BIT 321 drivers/scsi/nsp32.h # define IRQSELECT_PERR_IRQ BIT(8) BIT 322 drivers/scsi/nsp32.h # define IRQSELECT_BMCNTERR_IRQ BIT(9) BIT 323 drivers/scsi/nsp32.h # define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10) BIT 326 drivers/scsi/nsp32.h # define OLD_MSG BIT(0) BIT 327 drivers/scsi/nsp32.h # define OLD_IO BIT(1) BIT 328 drivers/scsi/nsp32.h # define OLD_CD BIT(2) BIT 329 drivers/scsi/nsp32.h # define OLD_BUSY BIT(3) BIT 335 drivers/scsi/nsp32.h # define ROM_WRITE_ENB BIT(0) BIT 336 drivers/scsi/nsp32.h # define IO_ACCESS_ENB BIT(1) BIT 337 drivers/scsi/nsp32.h # define ROM_ADR_CLEAR BIT(2) BIT 344 drivers/scsi/nsp32.h # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */ BIT 345 drivers/scsi/nsp32.h # define OEM1 BIT(2) /* OEM select */ BIT 346 drivers/scsi/nsp32.h # define OPTB BIT(3) /* KME mode select */ BIT 347 drivers/scsi/nsp32.h # define OPTC BIT(4) /* KME mode select */ BIT 348 drivers/scsi/nsp32.h # define OPTD BIT(5) /* KME mode select */ BIT 349 drivers/scsi/nsp32.h # define OPTE BIT(6) /* KME mode select */ BIT 350 drivers/scsi/nsp32.h # define OPTF BIT(7) /* Power management */ BIT 354 drivers/scsi/nsp32.h # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0) BIT 355 drivers/scsi/nsp32.h # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */ BIT 356 drivers/scsi/nsp32.h # define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */ BIT 357 drivers/scsi/nsp32.h # define DELAYED_BMSTART BIT(3) BIT 358 drivers/scsi/nsp32.h # define MASTER_TERMINATION_SELECT BIT(4) BIT 359 drivers/scsi/nsp32.h # define BMREQ_NEGATE_TIMING_SEL BIT(5) BIT 360 drivers/scsi/nsp32.h # define AUTOSEL_TIMING_SEL BIT(6) BIT 361 drivers/scsi/nsp32.h # define MISC_MABORT_MASK BIT(7) BIT 362 drivers/scsi/nsp32.h # define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8) BIT 365 drivers/scsi/nsp32.h # define BM_CYCLE0 BIT(0) BIT 366 drivers/scsi/nsp32.h # define BM_CYCLE1 BIT(1) BIT 367 drivers/scsi/nsp32.h # define BM_FRAME_ASSERT_TIMING BIT(2) BIT 368 drivers/scsi/nsp32.h # define BM_IRDY_ASSERT_TIMING BIT(3) BIT 369 drivers/scsi/nsp32.h # define BM_SINGLE_BUS_MASTER BIT(4) BIT 370 drivers/scsi/nsp32.h # define MEMRD_CMD0 BIT(5) BIT 371 drivers/scsi/nsp32.h # define SGT_AUTO_PARA_MEMED_CMD BIT(6) BIT 372 drivers/scsi/nsp32.h # define MEMRD_CMD1 BIT(7) BIT 376 drivers/scsi/nsp32.h # define SREQ_EDGH_SELECT BIT(0) BIT 379 drivers/scsi/nsp32.h # define REQCNT_UP BIT(0) BIT 380 drivers/scsi/nsp32.h # define ACKCNT_UP BIT(1) BIT 381 drivers/scsi/nsp32.h # define BMADR_UP BIT(4) BIT 382 drivers/scsi/nsp32.h # define BMCNT_UP BIT(5) BIT 383 drivers/scsi/nsp32.h # define SGT_CNT_UP BIT(7) BIT 392 drivers/scsi/nsp32.h # define SCL BIT(0) BIT 393 drivers/scsi/nsp32.h # define ENA BIT(1) BIT 394 drivers/scsi/nsp32.h # define SDA BIT(2) BIT 473 drivers/scsi/nsp32.h #define NSP32_TRANSFER_BUSMASTER BIT(0) BIT 474 drivers/scsi/nsp32.h #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */ BIT 475 drivers/scsi/nsp32.h #define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */ BIT 484 drivers/scsi/nsp32.h #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */ BIT 485 drivers/scsi/nsp32.h #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */ BIT 519 drivers/scsi/nsp32.h #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */ BIT 520 drivers/scsi/nsp32.h #define SDTR_TARGET BIT(1) /* sending SDTR from target */ BIT 521 drivers/scsi/nsp32.h #define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */ BIT 111 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_QUEUECOMMAND BIT(0) BIT 112 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_REGISTER BIT(1) BIT 113 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_AUTOSCSI BIT(2) BIT 114 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_INTR BIT(3) BIT 115 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_SGLIST BIT(4) BIT 116 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_BUSFREE BIT(5) BIT 117 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_CDB_CONTENTS BIT(6) BIT 118 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_RESELECTION BIT(7) BIT 119 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_MSGINOCCUR BIT(8) BIT 120 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_EEPROM BIT(9) BIT 121 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_MSGOUTOCCUR BIT(10) BIT 122 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_BUSRESET BIT(11) BIT 123 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_RESTART BIT(12) BIT 124 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_SYNC BIT(13) BIT 125 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_WAIT BIT(14) BIT 126 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_TARGETFLAG BIT(15) BIT 127 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_PROC BIT(16) BIT 128 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_INIT BIT(17) BIT 129 drivers/scsi/pcmcia/nsp_cs.c #define NSP_DEBUG_DATA_IO BIT(18) BIT 130 drivers/scsi/pcmcia/nsp_cs.c #define NSP_SPECIAL_PRINT_REGISTER BIT(20) BIT 405 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIDATALATCH, BIT(host_id) | BIT(target)); BIT 463 drivers/scsi/pcmcia/nsp_cs.c if ((data->ScsiClockDiv & (BIT(0)|BIT(1))) == CLOCK_20M) { BIT 663 drivers/scsi/pcmcia/nsp_cs.c tmp = id_reg & (~BIT(host_id)); BIT 666 drivers/scsi/pcmcia/nsp_cs.c if (tmp & BIT(0)) { BIT 764 drivers/scsi/pcmcia/nsp_cs.c res &= ~(BIT(1)|BIT(0)); /* align 4 */ BIT 772 drivers/scsi/pcmcia/nsp_cs.c res &= ~(BIT(1)|BIT(0)); /* align 4 */ BIT 863 drivers/scsi/pcmcia/nsp_cs.c res &= ~(BIT(1)|BIT(0)); /* align 4 */ BIT 871 drivers/scsi/pcmcia/nsp_cs.c res &= ~(BIT(1)|BIT(0)); /* align 4 */ BIT 40 drivers/scsi/pcmcia/nsp_cs.h # define IRQCONTROL_RESELECT_CLEAR BIT(0) BIT 41 drivers/scsi/pcmcia/nsp_cs.h # define IRQCONTROL_PHASE_CHANGE_CLEAR BIT(1) BIT 42 drivers/scsi/pcmcia/nsp_cs.h # define IRQCONTROL_TIMER_CLEAR BIT(2) BIT 43 drivers/scsi/pcmcia/nsp_cs.h # define IRQCONTROL_FIFO_CLEAR BIT(3) BIT 52 drivers/scsi/pcmcia/nsp_cs.h # define IRQSTATUS_SCSI BIT(0) BIT 53 drivers/scsi/pcmcia/nsp_cs.h # define IRQSTATUS_TIMER BIT(2) BIT 54 drivers/scsi/pcmcia/nsp_cs.h # define IRQSTATUS_FIFO BIT(3) BIT 58 drivers/scsi/pcmcia/nsp_cs.h # define IF_IFSEL BIT(0) BIT 59 drivers/scsi/pcmcia/nsp_cs.h # define IF_REGSEL BIT(2) BIT 64 drivers/scsi/pcmcia/nsp_cs.h # define FIFOSTATUS_FULL_EMPTY BIT(7) BIT 81 drivers/scsi/pcmcia/nsp_cs.h # define FAST_20 BIT(2) BIT 84 drivers/scsi/pcmcia/nsp_cs.h # define POWER_ON BIT(0) BIT 87 drivers/scsi/pcmcia/nsp_cs.h # define SCSI_PHASE_CHANGE_EI BIT(0) BIT 88 drivers/scsi/pcmcia/nsp_cs.h # define RESELECT_EI BIT(4) BIT 89 drivers/scsi/pcmcia/nsp_cs.h # define FIFO_IRQ_EI BIT(5) BIT 90 drivers/scsi/pcmcia/nsp_cs.h # define SCSI_RESET_IRQ_EI BIT(6) BIT 93 drivers/scsi/pcmcia/nsp_cs.h # define LATCHED_MSG BIT(0) BIT 94 drivers/scsi/pcmcia/nsp_cs.h # define LATCHED_IO BIT(1) BIT 95 drivers/scsi/pcmcia/nsp_cs.h # define LATCHED_CD BIT(2) BIT 96 drivers/scsi/pcmcia/nsp_cs.h # define LATCHED_BUS_FREE BIT(3) BIT 97 drivers/scsi/pcmcia/nsp_cs.h # define PHASE_CHANGE_IRQ BIT(4) BIT 98 drivers/scsi/pcmcia/nsp_cs.h # define RESELECT_IRQ BIT(5) BIT 99 drivers/scsi/pcmcia/nsp_cs.h # define FIFO_IRQ BIT(6) BIT 100 drivers/scsi/pcmcia/nsp_cs.h # define SCSI_RESET_IRQ BIT(7) BIT 105 drivers/scsi/pcmcia/nsp_cs.h # define SCSI_SEL BIT(0) BIT 106 drivers/scsi/pcmcia/nsp_cs.h # define SCSI_RST BIT(1) BIT 107 drivers/scsi/pcmcia/nsp_cs.h # define SCSI_DATAOUT_ENB BIT(2) BIT 108 drivers/scsi/pcmcia/nsp_cs.h # define SCSI_ATN BIT(3) BIT 109 drivers/scsi/pcmcia/nsp_cs.h # define SCSI_ACK BIT(4) BIT 110 drivers/scsi/pcmcia/nsp_cs.h # define SCSI_BSY BIT(5) BIT 111 drivers/scsi/pcmcia/nsp_cs.h # define AUTODIRECTION BIT(6) BIT 112 drivers/scsi/pcmcia/nsp_cs.h # define ACKENB BIT(7) BIT 117 drivers/scsi/pcmcia/nsp_cs.h # define ARBIT_GO BIT(0) BIT 118 drivers/scsi/pcmcia/nsp_cs.h # define ARBIT_FLAG_CLEAR BIT(1) BIT 122 drivers/scsi/pcmcia/nsp_cs.h # define ARBIT_WIN BIT(1) BIT 123 drivers/scsi/pcmcia/nsp_cs.h # define ARBIT_FAIL BIT(2) BIT 124 drivers/scsi/pcmcia/nsp_cs.h # define RESELECT_FLAG BIT(3) BIT 130 drivers/scsi/pcmcia/nsp_cs.h # define CLEAR_COMMAND_POINTER BIT(0) BIT 131 drivers/scsi/pcmcia/nsp_cs.h # define AUTO_COMMAND_GO BIT(1) BIT 137 drivers/scsi/pcmcia/nsp_cs.h # define POINTER_CLEAR BIT(0) BIT 138 drivers/scsi/pcmcia/nsp_cs.h # define ACK_COUNTER_CLEAR BIT(1) BIT 139 drivers/scsi/pcmcia/nsp_cs.h # define REQ_COUNTER_CLEAR BIT(2) BIT 140 drivers/scsi/pcmcia/nsp_cs.h # define HOST_COUNTER_CLEAR BIT(3) BIT 141 drivers/scsi/pcmcia/nsp_cs.h # define READ_SOURCE (BIT(4) | BIT(5)) BIT 143 drivers/scsi/pcmcia/nsp_cs.h # define REQ_COUNTER (BIT(4)) BIT 144 drivers/scsi/pcmcia/nsp_cs.h # define HOST_COUNTER (BIT(5)) BIT 149 drivers/scsi/pcmcia/nsp_cs.h # define MODE_MEM8 BIT(0) BIT 150 drivers/scsi/pcmcia/nsp_cs.h # define MODE_MEM32 BIT(1) BIT 151 drivers/scsi/pcmcia/nsp_cs.h # define MODE_ADR24 BIT(2) BIT 152 drivers/scsi/pcmcia/nsp_cs.h # define MODE_ADR32 BIT(3) BIT 153 drivers/scsi/pcmcia/nsp_cs.h # define MODE_IO8 BIT(4) BIT 154 drivers/scsi/pcmcia/nsp_cs.h # define MODE_IO32 BIT(5) BIT 155 drivers/scsi/pcmcia/nsp_cs.h # define TRANSFER_GO BIT(6) BIT 156 drivers/scsi/pcmcia/nsp_cs.h # define BRAIND BIT(7) BIT 171 drivers/scsi/pcmcia/nsp_cs.h # define TPL_ROM_WRITE_EN BIT(0) BIT 172 drivers/scsi/pcmcia/nsp_cs.h # define TPWR_OUT BIT(1) BIT 173 drivers/scsi/pcmcia/nsp_cs.h # define TPWR_SENSE BIT(2) BIT 174 drivers/scsi/pcmcia/nsp_cs.h # define RA8_CONTROL BIT(3) BIT 186 drivers/scsi/pcmcia/nsp_cs.h #define S_MESSAGE BIT(0) /* Message line from SCSI bus */ BIT 187 drivers/scsi/pcmcia/nsp_cs.h #define S_IO BIT(1) /* Input/Output line from SCSI bus */ BIT 188 drivers/scsi/pcmcia/nsp_cs.h #define S_CD BIT(2) /* Command/Data line from SCSI bus */ BIT 189 drivers/scsi/pcmcia/nsp_cs.h #define S_BUSY BIT(3) /* Busy line from SCSI bus */ BIT 190 drivers/scsi/pcmcia/nsp_cs.h #define S_ACK BIT(4) /* Acknowledge line from SCSI bus */ BIT 191 drivers/scsi/pcmcia/nsp_cs.h #define S_REQUEST BIT(5) /* Request line from SCSI bus */ BIT 192 drivers/scsi/pcmcia/nsp_cs.h #define S_SELECT BIT(6) /* */ BIT 193 drivers/scsi/pcmcia/nsp_cs.h #define S_ATN BIT(7) /* */ BIT 101 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_GEN_CHAP_ENABLED BIT(0) BIT 102 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_GEN_DHCP_TCPIP_CONFIG_ENABLED BIT(1) BIT 103 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_GEN_DHCP_ISCSI_CONFIG_ENABLED BIT(2) BIT 104 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_GEN_IPV6_ENABLED BIT(3) BIT 105 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_GEN_IPV4_FALLBACK_ENABLED BIT(4) BIT 106 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_GEN_ISNS_WORLD_LOGIN BIT(5) BIT 107 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_GEN_ISNS_SELECTIVE_LOGIN BIT(6) BIT 108 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_GEN_ADDR_REDIRECT_ENABLED BIT(7) BIT 109 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_GEN_CHAP_MUTUAL_ENABLED BIT(8) BIT 139 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_INITIATOR_IP_VERSION_PRIORITY_V6 BIT(0) BIT 140 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_INITIATOR_VLAN_ENABLED BIT(1) BIT 147 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_TARGET_ENABLED BIT(0) BIT 148 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_BOOT_TIME_LOGIN_STATUS BIT(1) BIT 176 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_BLK_CTRL_FLAG_IS_NOT_EMPTY BIT(0) BIT 177 drivers/scsi/qedi/qedi_nvm_iscsi_cfg.h #define NVM_ISCSI_CFG_BLK_CTRL_FLAG_PF_MAPPED BIT(1) BIT 1031 drivers/scsi/scsi_sysfs.c if (!(sdev->sdev_bflags & (__force blist_flags_t)BIT(i))) BIT 60 drivers/scsi/snic/snic.h #define SNIC_TAG_ABORT BIT(30) /* Tag indicating abort */ BIT 61 drivers/scsi/snic/snic.h #define SNIC_TAG_DEV_RST BIT(29) /* Tag for device reset */ BIT 62 drivers/scsi/snic/snic.h #define SNIC_TAG_IOCTL_DEV_RST BIT(28) /* Tag for User Device Reset */ BIT 63 drivers/scsi/snic/snic.h #define SNIC_TAG_MASK (BIT(24) - 1) /* Mask for lookup */ BIT 70 drivers/scsi/snic/snic.h #define SNIC_IO_INITIALIZED BIT(0) BIT 71 drivers/scsi/snic/snic.h #define SNIC_IO_ISSUED BIT(1) BIT 72 drivers/scsi/snic/snic.h #define SNIC_IO_DONE BIT(2) BIT 73 drivers/scsi/snic/snic.h #define SNIC_IO_REQ_NULL BIT(3) BIT 74 drivers/scsi/snic/snic.h #define SNIC_IO_ABTS_PENDING BIT(4) BIT 75 drivers/scsi/snic/snic.h #define SNIC_IO_ABORTED BIT(5) BIT 76 drivers/scsi/snic/snic.h #define SNIC_IO_ABTS_ISSUED BIT(6) BIT 77 drivers/scsi/snic/snic.h #define SNIC_IO_TERM_ISSUED BIT(7) BIT 78 drivers/scsi/snic/snic.h #define SNIC_IO_ABTS_TIMEDOUT BIT(8) BIT 79 drivers/scsi/snic/snic.h #define SNIC_IO_ABTS_TERM_DONE BIT(9) BIT 80 drivers/scsi/snic/snic.h #define SNIC_IO_ABTS_TERM_REQ_NULL BIT(10) BIT 81 drivers/scsi/snic/snic.h #define SNIC_IO_ABTS_TERM_TIMEDOUT BIT(11) BIT 82 drivers/scsi/snic/snic.h #define SNIC_IO_INTERNAL_TERM_PENDING BIT(12) BIT 83 drivers/scsi/snic/snic.h #define SNIC_IO_INTERNAL_TERM_ISSUED BIT(13) BIT 84 drivers/scsi/snic/snic.h #define SNIC_DEVICE_RESET BIT(14) BIT 85 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_ISSUED BIT(15) BIT 86 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_TIMEDOUT BIT(16) BIT 87 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_ABTS_ISSUED BIT(17) BIT 88 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_TERM_ISSUED BIT(18) BIT 89 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_DONE BIT(19) BIT 90 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_REQ_NULL BIT(20) BIT 91 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_ABTS_DONE BIT(21) BIT 92 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_TERM_DONE BIT(22) BIT 93 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_ABTS_PENDING BIT(23) BIT 94 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_PENDING BIT(24) BIT 95 drivers/scsi/snic/snic.h #define SNIC_DEV_RST_NOTSUP BIT(25) BIT 96 drivers/scsi/snic/snic.h #define SNIC_SCSI_CLEANUP BIT(26) BIT 97 drivers/scsi/snic/snic.h #define SNIC_HOST_RESET_ISSUED BIT(27) BIT 139 drivers/scsi/ufs/cdns-pltfrm.c data |= BIT(24); BIT 92 drivers/scsi/ufs/ufs-hisi.h #define UFS_HISI_CAP_RESERVED BIT(0) BIT 93 drivers/scsi/ufs/ufs-hisi.h #define UFS_HISI_CAP_PHY10nm BIT(1) BIT 1164 drivers/scsi/ufs/ufs-qcom.c host->dev_ref_clk_en_mask = BIT(26); BIT 1178 drivers/scsi/ufs/ufs-qcom.c host->dev_ref_clk_en_mask = BIT(5); BIT 90 drivers/scsi/ufs/ufs-qcom.h #define TEST_BUS_EN BIT(18) BIT 92 drivers/scsi/ufs/ufs-qcom.h #define UFS_REG_TEST_BUS_EN BIT(30) BIT 126 drivers/scsi/ufs/ufs-qcom.h #define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0) BIT 127 drivers/scsi/ufs/ufs-qcom.h #define UFS_QCOM_DBG_PRINT_ICE_REGS_EN BIT(1) BIT 128 drivers/scsi/ufs/ufs-qcom.h #define UFS_QCOM_DBG_PRINT_TEST_BUS_EN BIT(2) BIT 138 drivers/scsi/ufs/ufs-qcom.h #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) BIT 17 drivers/sh/clk/cpg.c #define CPG_CKSTP_BIT BIT(8) BIT 52 drivers/slimbus/qcom-ctrl.c #define MGR_INT_TX_NACKED_2 BIT(25) BIT 53 drivers/slimbus/qcom-ctrl.c #define MGR_INT_MSG_BUF_CONTE BIT(26) BIT 54 drivers/slimbus/qcom-ctrl.c #define MGR_INT_RX_MSG_RCVD BIT(30) BIT 55 drivers/slimbus/qcom-ctrl.c #define MGR_INT_TX_MSG_SENT BIT(31) BIT 24 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_CFG_ENABLE BIT(0) BIT 25 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_CFG_RX_MSGQ_EN BIT(1) BIT 26 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_CFG_TX_MSGQ_EN BIT(2) BIT 28 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_LADDR BIT(1) BIT 31 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_INT_RECFG_DONE BIT(24) BIT 32 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_INT_TX_NACKED_2 BIT(25) BIT 33 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_INT_MSG_BUF_CONTE BIT(26) BIT 34 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_INT_MSG_TX_INVAL BIT(27) BIT 35 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_INT_IE_VE_CHG BIT(28) BIT 36 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_INT_DEV_ERR BIT(29) BIT 37 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_INT_RX_MSG_RCVD BIT(30) BIT 38 drivers/slimbus/qcom-ngd-ctrl.c #define NGD_INT_TX_MSG_SENT BIT(31) BIT 946 drivers/slimbus/qcom-ngd-ctrl.c wbuf[txn.msg->num_bytes] |= BIT(5); BIT 80 drivers/slimbus/slimbus.h #define SLIM_CHANNEL_CONTENT_FL BIT(7) BIT 51 drivers/soc/actions/owl-sps.c ack_mask = BIT(pd->info->ack_bit); BIT 52 drivers/soc/actions/owl-sps.c pwr_mask = BIT(pd->info->pwr_bit); BIT 30 drivers/soc/amlogic/meson-canvas.c #define CANVAS_LUT_WR_EN BIT(9) BIT 31 drivers/soc/amlogic/meson-canvas.c #define CANVAS_LUT_RD_EN BIT(8) BIT 22 drivers/soc/amlogic/meson-clk-measure.c #define MSR_ENABLE BIT(16) BIT 23 drivers/soc/amlogic/meson-clk-measure.c #define MSR_CONT BIT(17) /* continuous measurement */ BIT 24 drivers/soc/amlogic/meson-clk-measure.c #define MSR_INTR BIT(18) /* interrupts */ BIT 25 drivers/soc/amlogic/meson-clk-measure.c #define MSR_RUN BIT(19) BIT 27 drivers/soc/amlogic/meson-clk-measure.c #define MSR_BUSY BIT(31) BIT 71 drivers/soc/amlogic/meson-ee-pwrc.c .sleep_mask = BIT(8), BIT 73 drivers/soc/amlogic/meson-ee-pwrc.c .iso_mask = BIT(9), BIT 79 drivers/soc/amlogic/meson-ee-pwrc.c .sleep_mask = BIT(__bit), \ BIT 81 drivers/soc/amlogic/meson-ee-pwrc.c .iso_mask = BIT(__bit), \ BIT 111 drivers/soc/amlogic/meson-ee-pwrc.c { __reg, BIT(8) }, \ BIT 112 drivers/soc/amlogic/meson-ee-pwrc.c { __reg, BIT(9) }, \ BIT 113 drivers/soc/amlogic/meson-ee-pwrc.c { __reg, BIT(10) }, \ BIT 114 drivers/soc/amlogic/meson-ee-pwrc.c { __reg, BIT(11) }, \ BIT 115 drivers/soc/amlogic/meson-ee-pwrc.c { __reg, BIT(12) }, \ BIT 116 drivers/soc/amlogic/meson-ee-pwrc.c { __reg, BIT(13) }, \ BIT 117 drivers/soc/amlogic/meson-ee-pwrc.c { __reg, BIT(14) }, \ BIT 118 drivers/soc/amlogic/meson-ee-pwrc.c { __reg, BIT(15) } BIT 22 drivers/soc/amlogic/meson-gx-pwrc-vpu.c #define GEN_PWR_VPU_HDMI BIT(8) BIT 23 drivers/soc/amlogic/meson-gx-pwrc-vpu.c #define GEN_PWR_VPU_HDMI_ISO BIT(9) BIT 69 drivers/soc/amlogic/meson-gx-pwrc-vpu.c BIT(i), BIT(i)); BIT 112 drivers/soc/amlogic/meson-gx-pwrc-vpu.c BIT(i), BIT(i)); BIT 168 drivers/soc/amlogic/meson-gx-pwrc-vpu.c BIT(i), 0); BIT 222 drivers/soc/amlogic/meson-gx-pwrc-vpu.c BIT(i), 0); BIT 21 drivers/soc/aspeed/aspeed-lpc-ctrl.c #define HICR5_ENL2H BIT(8) BIT 22 drivers/soc/aspeed/aspeed-lpc-ctrl.c #define HICR5_ENFWH BIT(10) BIT 32 drivers/soc/aspeed/aspeed-lpc-snoop.c #define HICR5_EN_SNP0W BIT(0) BIT 33 drivers/soc/aspeed/aspeed-lpc-snoop.c #define HICR5_ENINT_SNP0W BIT(1) BIT 34 drivers/soc/aspeed/aspeed-lpc-snoop.c #define HICR5_EN_SNP1W BIT(2) BIT 35 drivers/soc/aspeed/aspeed-lpc-snoop.c #define HICR5_ENINT_SNP1W BIT(3) BIT 38 drivers/soc/aspeed/aspeed-lpc-snoop.c #define HICR6_STR_SNP0W BIT(0) BIT 39 drivers/soc/aspeed/aspeed-lpc-snoop.c #define HICR6_STR_SNP1W BIT(1) BIT 51 drivers/soc/aspeed/aspeed-lpc-snoop.c #define HICRB_ENSNP0D BIT(14) BIT 52 drivers/soc/aspeed/aspeed-lpc-snoop.c #define HICRB_ENSNP1D BIT(15) BIT 39 drivers/soc/aspeed/aspeed-p2a-ctrl.c #define SCU180_ENP2A BIT(1) BIT 395 drivers/soc/aspeed/aspeed-p2a-ctrl.c #define SCU2C_DRAM BIT(25) BIT 396 drivers/soc/aspeed/aspeed-p2a-ctrl.c #define SCU2C_SPI BIT(24) BIT 397 drivers/soc/aspeed/aspeed-p2a-ctrl.c #define SCU2C_SOC BIT(23) BIT 398 drivers/soc/aspeed/aspeed-p2a-ctrl.c #define SCU2C_FLASH BIT(22) BIT 29 drivers/soc/atmel/soc.c #define AT91_CIDR_EXT BIT(31) BIT 32 drivers/soc/bcm/bcm2835-power.c #define PM_CAM0_LDOHPEN BIT(2) BIT 33 drivers/soc/bcm/bcm2835-power.c #define PM_CAM0_LDOLPEN BIT(1) BIT 34 drivers/soc/bcm/bcm2835-power.c #define PM_CAM0_CTRLEN BIT(0) BIT 37 drivers/soc/bcm/bcm2835-power.c #define PM_CAM1_LDOHPEN BIT(2) BIT 38 drivers/soc/bcm/bcm2835-power.c #define PM_CAM1_LDOLPEN BIT(1) BIT 39 drivers/soc/bcm/bcm2835-power.c #define PM_CAM1_CTRLEN BIT(0) BIT 42 drivers/soc/bcm/bcm2835-power.c #define PM_CCP2TX_LDOEN BIT(1) BIT 43 drivers/soc/bcm/bcm2835-power.c #define PM_CCP2TX_CTRLEN BIT(0) BIT 46 drivers/soc/bcm/bcm2835-power.c #define PM_DSI0_LDOHPEN BIT(2) BIT 47 drivers/soc/bcm/bcm2835-power.c #define PM_DSI0_LDOLPEN BIT(1) BIT 48 drivers/soc/bcm/bcm2835-power.c #define PM_DSI0_CTRLEN BIT(0) BIT 51 drivers/soc/bcm/bcm2835-power.c #define PM_DSI1_LDOHPEN BIT(2) BIT 52 drivers/soc/bcm/bcm2835-power.c #define PM_DSI1_LDOLPEN BIT(1) BIT 53 drivers/soc/bcm/bcm2835-power.c #define PM_DSI1_CTRLEN BIT(0) BIT 56 drivers/soc/bcm/bcm2835-power.c #define PM_HDMI_RSTDR BIT(19) BIT 57 drivers/soc/bcm/bcm2835-power.c #define PM_HDMI_LDOPD BIT(1) BIT 58 drivers/soc/bcm/bcm2835-power.c #define PM_HDMI_CTRLEN BIT(0) BIT 64 drivers/soc/bcm/bcm2835-power.c #define PM_USB_CTRLEN BIT(0) BIT 82 drivers/soc/bcm/bcm2835-power.c #define PM_ENAB BIT(12) BIT 83 drivers/soc/bcm/bcm2835-power.c #define PM_ISPRSTN BIT(8) BIT 84 drivers/soc/bcm/bcm2835-power.c #define PM_H264RSTN BIT(7) BIT 85 drivers/soc/bcm/bcm2835-power.c #define PM_PERIRSTN BIT(6) BIT 86 drivers/soc/bcm/bcm2835-power.c #define PM_V3DRSTN BIT(6) BIT 87 drivers/soc/bcm/bcm2835-power.c #define PM_ISFUNC BIT(5) BIT 88 drivers/soc/bcm/bcm2835-power.c #define PM_MRDONE BIT(4) BIT 89 drivers/soc/bcm/bcm2835-power.c #define PM_MEMREP BIT(3) BIT 90 drivers/soc/bcm/bcm2835-power.c #define PM_ISPOW BIT(2) BIT 91 drivers/soc/bcm/bcm2835-power.c #define PM_POWOK BIT(1) BIT 92 drivers/soc/bcm/bcm2835-power.c #define PM_POWUP BIT(0) BIT 122 drivers/soc/bcm/bcm2835-power.c #define ASB_REQ_STOP BIT(0) BIT 123 drivers/soc/bcm/bcm2835-power.c #define ASB_ACK BIT(1) BIT 124 drivers/soc/bcm/bcm2835-power.c #define ASB_EMPTY BIT(2) BIT 125 drivers/soc/bcm/bcm2835-power.c #define ASB_FULL BIT(3) BIT 28 drivers/soc/bcm/brcmstb/biuctrl.c #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8) BIT 53 drivers/soc/bcm/brcmstb/pm/pm-arm.c #define SHIMPHY_PAD_PLL_SEQUENCE BIT(8) BIT 54 drivers/soc/bcm/brcmstb/pm/pm-arm.c #define SHIMPHY_PAD_GATE_PLL_S3 BIT(9) BIT 65 drivers/soc/bcm/brcmstb/pm/pm-arm.c #define DDR_FORCE_CKE_RST_N BIT(3) BIT 66 drivers/soc/bcm/brcmstb/pm/pm-arm.c #define DDR_PHY_RST_N BIT(2) BIT 67 drivers/soc/bcm/brcmstb/pm/pm-arm.c #define DDR_PHY_CKE BIT(1) BIT 208 drivers/soc/bcm/brcmstb/pm/pm-mips.c tmp |= (0x05 | BIT(5)); BIT 56 drivers/soc/dove/pmu.c writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST); BIT 57 drivers/soc/dove/pmu.c writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST); BIT 67 drivers/soc/dove/pmu.c u32 val = ~BIT(id); BIT 81 drivers/soc/dove/pmu.c u32 val = BIT(id); BIT 437 drivers/soc/dove/pmu.c domain->rst_mask = BIT(args.args[0]); BIT 98 drivers/soc/fsl/qbman/bman_ccsr.c #define FBPR_AR_RPRIO_HI BIT(30) BIT 109 drivers/soc/fsl/qbman/qman_ccsr.c #define QM_CI_SCHED_CFG_SRCCIV_EN BIT(31) BIT 163 drivers/soc/fsl/qbman/qman_ccsr.c return p->info & BIT(29); BIT 173 drivers/soc/fsl/qbman/qman_ccsr.c return p->info & (BIT(24) - 1); BIT 182 drivers/soc/fsl/qbman/qman_ccsr.c return p->info & BIT(31); BIT 187 drivers/soc/fsl/qbman/qman_ccsr.c return p->info & (BIT(10) - 1); BIT 202 drivers/soc/fsl/qbman/qman_ccsr.c return p->info & (BIT(12) - 1); BIT 212 drivers/soc/fsl/qbman/qman_ccsr.c return p->info & (BIT(16) - 1); BIT 343 drivers/soc/fsl/qbman/qman_ccsr.c #define PFDR_AR_EN BIT(31) BIT 101 drivers/soc/fsl/qbman/qman_priv.h #define CGR_BIT(x) (BIT(31) >> ((x) & 0x1f)) BIT 24 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_DMAC_HIGH_PRIO BIT(0) BIT 25 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_IDE_HIGH_PRIO BIT(1) BIT 26 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_RAID_HIGH_PRIO BIT(2) BIT 27 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_SECURITY_HIGH_PRIO BIT(3) BIT 28 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_GMAC0_HIGH_PRIO BIT(4) BIT 29 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_GMAC1_HIGH_PRIO BIT(5) BIT 30 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_USB0_HIGH_PRIO BIT(6) BIT 31 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_USB1_HIGH_PRIO BIT(7) BIT 32 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_PCI_HIGH_PRIO BIT(8) BIT 33 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_TVE_HIGH_PRIO BIT(9) BIT 35 drivers/soc/imx/gpc.c #define GPU_VPU_PUP_REQ BIT(1) BIT 36 drivers/soc/imx/gpc.c #define GPU_VPU_PDN_REQ BIT(0) BIT 40 drivers/soc/imx/gpc.c #define PGC_DOMAIN_FLAG_NO_PD BIT(0) BIT 75 drivers/soc/imx/gpc.c val = BIT(pd->cntr_pdn_bit); BIT 111 drivers/soc/imx/gpc.c req = BIT(pd->cntr_pdn_bit + 1); BIT 24 drivers/soc/imx/gpcv2.c #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6) BIT 25 drivers/soc/imx/gpcv2.c #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5) BIT 26 drivers/soc/imx/gpcv2.c #define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN BIT(4) BIT 27 drivers/soc/imx/gpcv2.c #define IMX7_PCIE_PHY_A_CORE_DOMAIN BIT(3) BIT 28 drivers/soc/imx/gpcv2.c #define IMX7_MIPI_PHY_A_CORE_DOMAIN BIT(2) BIT 30 drivers/soc/imx/gpcv2.c #define IMX8M_PCIE2_A53_DOMAIN BIT(15) BIT 31 drivers/soc/imx/gpcv2.c #define IMX8M_MIPI_CSI2_A53_DOMAIN BIT(14) BIT 32 drivers/soc/imx/gpcv2.c #define IMX8M_MIPI_CSI1_A53_DOMAIN BIT(13) BIT 33 drivers/soc/imx/gpcv2.c #define IMX8M_DISP_A53_DOMAIN BIT(12) BIT 34 drivers/soc/imx/gpcv2.c #define IMX8M_HDMI_A53_DOMAIN BIT(11) BIT 35 drivers/soc/imx/gpcv2.c #define IMX8M_VPU_A53_DOMAIN BIT(10) BIT 36 drivers/soc/imx/gpcv2.c #define IMX8M_GPU_A53_DOMAIN BIT(9) BIT 37 drivers/soc/imx/gpcv2.c #define IMX8M_DDR2_A53_DOMAIN BIT(8) BIT 38 drivers/soc/imx/gpcv2.c #define IMX8M_DDR1_A53_DOMAIN BIT(7) BIT 39 drivers/soc/imx/gpcv2.c #define IMX8M_OTG2_A53_DOMAIN BIT(5) BIT 40 drivers/soc/imx/gpcv2.c #define IMX8M_OTG1_A53_DOMAIN BIT(4) BIT 41 drivers/soc/imx/gpcv2.c #define IMX8M_PCIE1_A53_DOMAIN BIT(3) BIT 42 drivers/soc/imx/gpcv2.c #define IMX8M_MIPI_A53_DOMAIN BIT(2) BIT 47 drivers/soc/imx/gpcv2.c #define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4) BIT 48 drivers/soc/imx/gpcv2.c #define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3) BIT 49 drivers/soc/imx/gpcv2.c #define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2) BIT 50 drivers/soc/imx/gpcv2.c #define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1) BIT 51 drivers/soc/imx/gpcv2.c #define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0) BIT 53 drivers/soc/imx/gpcv2.c #define IMX8M_PCIE2_SW_Pxx_REQ BIT(13) BIT 54 drivers/soc/imx/gpcv2.c #define IMX8M_MIPI_CSI2_SW_Pxx_REQ BIT(12) BIT 55 drivers/soc/imx/gpcv2.c #define IMX8M_MIPI_CSI1_SW_Pxx_REQ BIT(11) BIT 56 drivers/soc/imx/gpcv2.c #define IMX8M_DISP_SW_Pxx_REQ BIT(10) BIT 57 drivers/soc/imx/gpcv2.c #define IMX8M_HDMI_SW_Pxx_REQ BIT(9) BIT 58 drivers/soc/imx/gpcv2.c #define IMX8M_VPU_SW_Pxx_REQ BIT(8) BIT 59 drivers/soc/imx/gpcv2.c #define IMX8M_GPU_SW_Pxx_REQ BIT(7) BIT 60 drivers/soc/imx/gpcv2.c #define IMX8M_DDR2_SW_Pxx_REQ BIT(6) BIT 61 drivers/soc/imx/gpcv2.c #define IMX8M_DDR1_SW_Pxx_REQ BIT(5) BIT 62 drivers/soc/imx/gpcv2.c #define IMX8M_OTG2_SW_Pxx_REQ BIT(3) BIT 63 drivers/soc/imx/gpcv2.c #define IMX8M_OTG1_SW_Pxx_REQ BIT(2) BIT 64 drivers/soc/imx/gpcv2.c #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1) BIT 65 drivers/soc/imx/gpcv2.c #define IMX8M_MIPI_SW_Pxx_REQ BIT(0) BIT 71 drivers/soc/imx/gpcv2.c #define IMX8M_GPU_HSK_PWRDNREQN BIT(6) BIT 72 drivers/soc/imx/gpcv2.c #define IMX8M_VPU_HSK_PWRDNREQN BIT(5) BIT 73 drivers/soc/imx/gpcv2.c #define IMX8M_DISP_HSK_PWRDNREQN BIT(4) BIT 100 drivers/soc/imx/gpcv2.c #define GPC_PGC_CTRL_PCR BIT(0) BIT 151 drivers/soc/ixp4xx/ixp4xx-qmgr.c en_bitmap &= ~BIT(i); BIT 156 drivers/soc/ixp4xx/ixp4xx-qmgr.c if (stat & BIT(src & 3)) { BIT 176 drivers/soc/ixp4xx/ixp4xx-qmgr.c req_bitmap &= ~BIT(i); BIT 195 drivers/soc/ixp4xx/ixp4xx-qmgr.c req_bitmap &= ~BIT(i); BIT 22 drivers/soc/lantiq/fpi-bus.c #define XBAR_FPI_BURST_EN BIT(1) BIT 23 drivers/soc/lantiq/fpi-bus.c #define XBAR_AHB_BURST_EN BIT(2) BIT 13 drivers/soc/mediatek/mtk-cmdq-helper.c #define CMDQ_WRITE_ENABLE_MASK BIT(0) BIT 14 drivers/soc/mediatek/mtk-cmdq-helper.c #define CMDQ_EOC_IRQ_EN BIT(0) BIT 66 drivers/soc/mediatek/mtk-pmic-wrap.c #define PWRAP_SLV_CAP_SPI BIT(0) BIT 67 drivers/soc/mediatek/mtk-pmic-wrap.c #define PWRAP_SLV_CAP_DUALIO BIT(1) BIT 68 drivers/soc/mediatek/mtk-pmic-wrap.c #define PWRAP_SLV_CAP_SECURITY BIT(2) BIT 72 drivers/soc/mediatek/mtk-pmic-wrap.c #define PWRAP_CAP_BRIDGE BIT(0) BIT 73 drivers/soc/mediatek/mtk-pmic-wrap.c #define PWRAP_CAP_RESET BIT(1) BIT 74 drivers/soc/mediatek/mtk-pmic-wrap.c #define PWRAP_CAP_DCM BIT(2) BIT 75 drivers/soc/mediatek/mtk-pmic-wrap.c #define PWRAP_CAP_INT1_EN BIT(3) BIT 76 drivers/soc/mediatek/mtk-pmic-wrap.c #define PWRAP_CAP_WDT_SRC1 BIT(4) BIT 1765 drivers/soc/mediatek/mtk-pmic-wrap.c .int_en_all = ~(u32)(BIT(31) | BIT(2)), BIT 1803 drivers/soc/mediatek/mtk-pmic-wrap.c .int_en_all = ~(u32)BIT(31), BIT 1816 drivers/soc/mediatek/mtk-pmic-wrap.c .int_en_all = ~(u32)(BIT(31) | BIT(1)), BIT 1829 drivers/soc/mediatek/mtk-pmic-wrap.c .int_en_all = ~(u32)(BIT(31) | BIT(1)), BIT 1855 drivers/soc/mediatek/mtk-pmic-wrap.c .int_en_all = ~(u32)(BIT(31) | BIT(2)), BIT 26 drivers/soc/mediatek/mtk-scpsys.c #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) BIT 27 drivers/soc/mediatek/mtk-scpsys.c #define MTK_SCPD_FWAIT_SRAM BIT(1) BIT 54 drivers/soc/mediatek/mtk-scpsys.c #define PWR_RST_B_BIT BIT(0) BIT 55 drivers/soc/mediatek/mtk-scpsys.c #define PWR_ISO_BIT BIT(1) BIT 56 drivers/soc/mediatek/mtk-scpsys.c #define PWR_ON_BIT BIT(2) BIT 57 drivers/soc/mediatek/mtk-scpsys.c #define PWR_ON_2ND_BIT BIT(3) BIT 58 drivers/soc/mediatek/mtk-scpsys.c #define PWR_CLK_DIS_BIT BIT(4) BIT 60 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_CONN BIT(1) BIT 61 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_DISP BIT(3) BIT 62 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_MFG BIT(4) BIT 63 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_ISP BIT(5) BIT 64 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_VDEC BIT(7) BIT 65 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_BDP BIT(14) BIT 66 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_ETH BIT(15) BIT 67 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_HIF BIT(16) BIT 68 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_IFR_MSC BIT(17) BIT 69 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_USB2 BIT(19) /* MT2712 */ BIT 70 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_VENC_LT BIT(20) BIT 71 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_VENC BIT(21) BIT 72 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_MFG_2D BIT(22) /* MT8173 */ BIT 73 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_MFG_ASYNC BIT(23) /* MT8173 */ BIT 74 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_AUDIO BIT(24) /* MT8173, MT2712 */ BIT 75 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_USB BIT(25) /* MT8173, MT2712 */ BIT 76 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_ETHSYS BIT(24) /* MT7622 */ BIT 77 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_HIF0 BIT(25) /* MT7622 */ BIT 78 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ BIT 79 drivers/soc/mediatek/mtk-scpsys.c #define PWR_STATUS_WB BIT(27) /* MT7622 */ BIT 633 drivers/soc/mediatek/mtk-scpsys.c .bus_prot_mask = BIT(14) | BIT(21) | BIT(23), BIT 638 drivers/soc/mediatek/mtk-scpsys.c .sta_mask = BIT(22), BIT 647 drivers/soc/mediatek/mtk-scpsys.c .sta_mask = BIT(23), BIT 656 drivers/soc/mediatek/mtk-scpsys.c .sta_mask = BIT(30), BIT 681 drivers/soc/mediatek/mtk-scpsys.c .sta_mask = BIT(7), BIT 689 drivers/soc/mediatek/mtk-scpsys.c .sta_mask = BIT(21), BIT 697 drivers/soc/mediatek/mtk-scpsys.c .sta_mask = BIT(5), BIT 705 drivers/soc/mediatek/mtk-scpsys.c .sta_mask = BIT(3), BIT 710 drivers/soc/mediatek/mtk-scpsys.c .bus_prot_mask = (BIT(1) | BIT(2)), BIT 714 drivers/soc/mediatek/mtk-scpsys.c .sta_mask = BIT(24), BIT 722 drivers/soc/mediatek/mtk-scpsys.c .sta_mask = BIT(13), BIT 730 drivers/soc/mediatek/mtk-scpsys.c .sta_mask = BIT(20), BIT 20 drivers/soc/qcom/llcc-slice.c #define ACTIVATE BIT(0) BIT 21 drivers/soc/qcom/llcc-slice.c #define DEACTIVATE BIT(1) BIT 22 drivers/soc/qcom/llcc-slice.c #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) BIT 23 drivers/soc/qcom/llcc-slice.c #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) BIT 24 drivers/soc/qcom/llcc-slice.c #define ACT_CTRL_ACT_TRIG BIT(0) BIT 139 drivers/soc/qcom/qcom-geni-se.c #define CFG_AHB_CLK_CGC_ON BIT(0) BIT 140 drivers/soc/qcom/qcom-geni-se.c #define CFG_AHB_WR_ACLK_CGC_ON BIT(1) BIT 141 drivers/soc/qcom/qcom-geni-se.c #define DATA_AHB_CLK_CGC_ON BIT(2) BIT 142 drivers/soc/qcom/qcom-geni-se.c #define SCLK_CGC_ON BIT(3) BIT 143 drivers/soc/qcom/qcom-geni-se.c #define TX_CLK_CGC_ON BIT(4) BIT 144 drivers/soc/qcom/qcom-geni-se.c #define RX_CLK_CGC_ON BIT(5) BIT 145 drivers/soc/qcom/qcom-geni-se.c #define EXT_CLK_CGC_ON BIT(6) BIT 146 drivers/soc/qcom/qcom-geni-se.c #define PROG_RAM_HCLK_OFF BIT(8) BIT 147 drivers/soc/qcom/qcom-geni-se.c #define PROG_RAM_SCLK_OFF BIT(9) BIT 151 drivers/soc/qcom/qcom-geni-se.c #define DMA_RX_EVENT_EN BIT(0) BIT 152 drivers/soc/qcom/qcom-geni-se.c #define DMA_TX_EVENT_EN BIT(1) BIT 153 drivers/soc/qcom/qcom-geni-se.c #define GENI_M_EVENT_EN BIT(2) BIT 154 drivers/soc/qcom/qcom-geni-se.c #define GENI_S_EVENT_EN BIT(3) BIT 157 drivers/soc/qcom/qcom-geni-se.c #define DMA_RX_IRQ_EN BIT(0) BIT 158 drivers/soc/qcom/qcom-geni-se.c #define DMA_TX_IRQ_EN BIT(1) BIT 159 drivers/soc/qcom/qcom-geni-se.c #define GENI_M_IRQ_EN BIT(2) BIT 160 drivers/soc/qcom/qcom-geni-se.c #define GENI_S_IRQ_EN BIT(3) BIT 163 drivers/soc/qcom/qcom-geni-se.c #define DMA_RX_CLK_CGC_ON BIT(0) BIT 164 drivers/soc/qcom/qcom-geni-se.c #define DMA_TX_CLK_CGC_ON BIT(1) BIT 165 drivers/soc/qcom/qcom-geni-se.c #define DMA_AHB_SLV_CFG_ON BIT(2) BIT 166 drivers/soc/qcom/qcom-geni-se.c #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) BIT 167 drivers/soc/qcom/qcom-geni-se.c #define DUMMY_RX_NON_BUFFERABLE BIT(4) BIT 168 drivers/soc/qcom/qcom-geni-se.c #define RX_DMA_ZERO_PADDING_EN BIT(5) BIT 365 drivers/soc/qcom/qcom-geni-se.c #define PACKING_STOP_BIT BIT(0) BIT 612 drivers/soc/qcom/qcom-geni-se.c #define GENI_SE_DMA_DONE_EN BIT(0) BIT 613 drivers/soc/qcom/qcom-geni-se.c #define GENI_SE_DMA_EOT_EN BIT(1) BIT 614 drivers/soc/qcom/qcom-geni-se.c #define GENI_SE_DMA_AHB_ERR_EN BIT(2) BIT 615 drivers/soc/qcom/qcom-geni-se.c #define GENI_SE_DMA_EOT_BUF BIT(0) BIT 244 drivers/soc/qcom/rmtfs_mem.c rmtfs_mem->perms = BIT(QCOM_SCM_VMID_HLOS); BIT 54 drivers/soc/qcom/rpmh-rsc.c #define TCS_AMC_MODE_ENABLE BIT(16) BIT 55 drivers/soc/qcom/rpmh-rsc.c #define TCS_AMC_MODE_TRIGGER BIT(24) BIT 59 drivers/soc/qcom/rpmh-rsc.c #define CMD_MSGID_RESP_REQ BIT(8) BIT 60 drivers/soc/qcom/rpmh-rsc.c #define CMD_MSGID_WRITE BIT(16) BIT 61 drivers/soc/qcom/rpmh-rsc.c #define CMD_STATUS_ISSUED BIT(8) BIT 62 drivers/soc/qcom/rpmh-rsc.c #define CMD_STATUS_COMPL BIT(16) BIT 197 drivers/soc/qcom/rpmh-rsc.c if (tcs->mask & BIT(tcs_id)) BIT 244 drivers/soc/qcom/rpmh-rsc.c write_tcs_reg(drv, RSC_DRV_IRQ_CLEAR, 0, BIT(i)); BIT 272 drivers/soc/qcom/rpmh-rsc.c cmd_enable |= BIT(j); BIT 160 drivers/soc/qcom/smp2p.c regmap_write(smp2p->ipc_regmap, smp2p->ipc_offset, BIT(smp2p->ipc_bit)); BIT 228 drivers/soc/qcom/smp2p.c if (!(status & BIT(i))) BIT 231 drivers/soc/qcom/smp2p.c if ((val & BIT(i) && test_bit(i, entry->irq_rising)) || BIT 232 drivers/soc/qcom/smp2p.c (!(val & BIT(i)) && test_bit(i, entry->irq_falling))) { BIT 178 drivers/soc/qcom/smsm.c BIT(hostp->ipc_bit)); BIT 211 drivers/soc/qcom/smsm.c if (!(changed & BIT(i))) BIT 214 drivers/soc/qcom/smsm.c if (val & BIT(i)) { BIT 246 drivers/soc/qcom/smsm.c val &= ~BIT(irq); BIT 273 drivers/soc/qcom/smsm.c val |= BIT(irq); BIT 30 drivers/soc/qcom/spm.c #define SPM_CTL_EN BIT(0) BIT 82 drivers/soc/renesas/rcar-sysc.c if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit)) BIT 91 drivers/soc/renesas/rcar-sysc.c iowrite32(BIT(sysc_ch->chan_bit), BIT 99 drivers/soc/renesas/rcar-sysc.c unsigned int isr_mask = BIT(sysc_ch->isr_bit); BIT 100 drivers/soc/renesas/rcar-sysc.c unsigned int chan_mask = BIT(sysc_ch->chan_bit); BIT 163 drivers/soc/renesas/rcar-sysc.c if (st & BIT(sysc_ch->chan_bit)) BIT 16 drivers/soc/renesas/rcar-sysc.h #define PD_CPU BIT(0) /* Area contains main CPU core */ BIT 17 drivers/soc/renesas/rcar-sysc.h #define PD_SCU BIT(1) /* Area contains SCU and L2 cache */ BIT 18 drivers/soc/renesas/rcar-sysc.h #define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */ BIT 51 drivers/soc/renesas/rmobile-sysc.c unsigned int mask = BIT(rmobile_pd->bit_shift); BIT 79 drivers/soc/renesas/rmobile-sysc.c unsigned int mask = BIT(rmobile_pd->bit_shift); BIT 719 drivers/soc/rockchip/pm_domains.c [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), BIT 720 drivers/soc/rockchip/pm_domains.c [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), BIT 721 drivers/soc/rockchip/pm_domains.c [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), BIT 722 drivers/soc/rockchip/pm_domains.c [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), BIT 723 drivers/soc/rockchip/pm_domains.c [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), BIT 724 drivers/soc/rockchip/pm_domains.c [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), BIT 725 drivers/soc/rockchip/pm_domains.c [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), BIT 726 drivers/soc/rockchip/pm_domains.c [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), BIT 730 drivers/soc/rockchip/pm_domains.c [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), BIT 731 drivers/soc/rockchip/pm_domains.c [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), BIT 732 drivers/soc/rockchip/pm_domains.c [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), BIT 733 drivers/soc/rockchip/pm_domains.c [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), BIT 734 drivers/soc/rockchip/pm_domains.c [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), BIT 735 drivers/soc/rockchip/pm_domains.c [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), BIT 736 drivers/soc/rockchip/pm_domains.c [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), BIT 740 drivers/soc/rockchip/pm_domains.c [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), BIT 741 drivers/soc/rockchip/pm_domains.c [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), BIT 742 drivers/soc/rockchip/pm_domains.c [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), BIT 743 drivers/soc/rockchip/pm_domains.c [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), BIT 744 drivers/soc/rockchip/pm_domains.c [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), BIT 748 drivers/soc/rockchip/pm_domains.c [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), BIT 749 drivers/soc/rockchip/pm_domains.c [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), BIT 750 drivers/soc/rockchip/pm_domains.c [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), BIT 751 drivers/soc/rockchip/pm_domains.c [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), BIT 752 drivers/soc/rockchip/pm_domains.c [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), BIT 756 drivers/soc/rockchip/pm_domains.c [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), BIT 757 drivers/soc/rockchip/pm_domains.c [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), BIT 758 drivers/soc/rockchip/pm_domains.c [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), BIT 759 drivers/soc/rockchip/pm_domains.c [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), BIT 760 drivers/soc/rockchip/pm_domains.c [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), BIT 764 drivers/soc/rockchip/pm_domains.c [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), BIT 765 drivers/soc/rockchip/pm_domains.c [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), BIT 766 drivers/soc/rockchip/pm_domains.c [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), BIT 767 drivers/soc/rockchip/pm_domains.c [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), BIT 768 drivers/soc/rockchip/pm_domains.c [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), BIT 769 drivers/soc/rockchip/pm_domains.c [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), BIT 770 drivers/soc/rockchip/pm_domains.c [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), BIT 771 drivers/soc/rockchip/pm_domains.c [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), BIT 772 drivers/soc/rockchip/pm_domains.c [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), BIT 773 drivers/soc/rockchip/pm_domains.c [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), BIT 774 drivers/soc/rockchip/pm_domains.c [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), BIT 778 drivers/soc/rockchip/pm_domains.c [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), BIT 779 drivers/soc/rockchip/pm_domains.c [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), BIT 780 drivers/soc/rockchip/pm_domains.c [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), BIT 781 drivers/soc/rockchip/pm_domains.c [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), BIT 785 drivers/soc/rockchip/pm_domains.c [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), BIT 786 drivers/soc/rockchip/pm_domains.c [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), BIT 787 drivers/soc/rockchip/pm_domains.c [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), BIT 788 drivers/soc/rockchip/pm_domains.c [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), BIT 789 drivers/soc/rockchip/pm_domains.c [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), BIT 790 drivers/soc/rockchip/pm_domains.c [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), BIT 791 drivers/soc/rockchip/pm_domains.c [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), BIT 792 drivers/soc/rockchip/pm_domains.c [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), BIT 793 drivers/soc/rockchip/pm_domains.c [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), BIT 797 drivers/soc/rockchip/pm_domains.c [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), BIT 798 drivers/soc/rockchip/pm_domains.c [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), BIT 799 drivers/soc/rockchip/pm_domains.c [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), BIT 800 drivers/soc/rockchip/pm_domains.c [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), BIT 801 drivers/soc/rockchip/pm_domains.c [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), BIT 802 drivers/soc/rockchip/pm_domains.c [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), BIT 803 drivers/soc/rockchip/pm_domains.c [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), BIT 807 drivers/soc/rockchip/pm_domains.c [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), BIT 808 drivers/soc/rockchip/pm_domains.c [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), BIT 809 drivers/soc/rockchip/pm_domains.c [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), BIT 810 drivers/soc/rockchip/pm_domains.c [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), BIT 811 drivers/soc/rockchip/pm_domains.c [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), BIT 815 drivers/soc/rockchip/pm_domains.c [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), BIT 816 drivers/soc/rockchip/pm_domains.c [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), BIT 817 drivers/soc/rockchip/pm_domains.c [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), BIT 818 drivers/soc/rockchip/pm_domains.c [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), BIT 819 drivers/soc/rockchip/pm_domains.c [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), BIT 820 drivers/soc/rockchip/pm_domains.c [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), BIT 821 drivers/soc/rockchip/pm_domains.c [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), BIT 822 drivers/soc/rockchip/pm_domains.c [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), BIT 823 drivers/soc/rockchip/pm_domains.c [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), BIT 824 drivers/soc/rockchip/pm_domains.c [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), BIT 825 drivers/soc/rockchip/pm_domains.c [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), BIT 826 drivers/soc/rockchip/pm_domains.c [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), BIT 827 drivers/soc/rockchip/pm_domains.c [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), BIT 828 drivers/soc/rockchip/pm_domains.c [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), BIT 829 drivers/soc/rockchip/pm_domains.c [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), BIT 830 drivers/soc/rockchip/pm_domains.c [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), BIT 831 drivers/soc/rockchip/pm_domains.c [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), BIT 832 drivers/soc/rockchip/pm_domains.c [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), BIT 833 drivers/soc/rockchip/pm_domains.c [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), BIT 834 drivers/soc/rockchip/pm_domains.c [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), BIT 835 drivers/soc/rockchip/pm_domains.c [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), BIT 836 drivers/soc/rockchip/pm_domains.c [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), BIT 837 drivers/soc/rockchip/pm_domains.c [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), BIT 838 drivers/soc/rockchip/pm_domains.c [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), BIT 839 drivers/soc/rockchip/pm_domains.c [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), BIT 840 drivers/soc/rockchip/pm_domains.c [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), BIT 841 drivers/soc/rockchip/pm_domains.c [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), BIT 31 drivers/soc/tegra/fuse/fuse-tegra30.c #define FUSE_HAS_REVISION_INFO BIT(0) BIT 53 drivers/soc/tegra/pmc.c #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ BIT 54 drivers/soc/tegra/pmc.c #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ BIT 55 drivers/soc/tegra/pmc.c #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ BIT 56 drivers/soc/tegra/pmc.c #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ BIT 57 drivers/soc/tegra/pmc.c #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ BIT 58 drivers/soc/tegra/pmc.c #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ BIT 59 drivers/soc/tegra/pmc.c #define PMC_CNTRL_MAIN_RST BIT(4) BIT 62 drivers/soc/tegra/pmc.c #define DPD_SAMPLE_ENABLE BIT(0) BIT 66 drivers/soc/tegra/pmc.c #define PWRGATE_TOGGLE_START BIT(8) BIT 76 drivers/soc/tegra/pmc.c #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) BIT 77 drivers/soc/tegra/pmc.c #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) BIT 78 drivers/soc/tegra/pmc.c #define PMC_SCRATCH0_MODE_RCM BIT(1) BIT 91 drivers/soc/tegra/pmc.c #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) BIT 92 drivers/soc/tegra/pmc.c #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) BIT 117 drivers/soc/tegra/pmc.c #define PMC_SCRATCH55_RESET_TEGRA BIT(31) BIT 120 drivers/soc/tegra/pmc.c #define PMC_SCRATCH55_16BITOP BIT(15) BIT 138 drivers/soc/tegra/pmc.c #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) BIT 430 drivers/soc/tegra/pmc.c return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; BIT 1170 drivers/soc/tegra/pmc.c *mask = BIT(pad->dpd % 32); BIT 1343 drivers/soc/tegra/pmc.c value &= ~BIT(pad->voltage); BIT 1345 drivers/soc/tegra/pmc.c value |= BIT(pad->voltage); BIT 1351 drivers/soc/tegra/pmc.c value |= BIT(pad->voltage); BIT 1358 drivers/soc/tegra/pmc.c value &= ~BIT(pad->voltage); BIT 1360 drivers/soc/tegra/pmc.c value |= BIT(pad->voltage); BIT 1389 drivers/soc/tegra/pmc.c if ((value & BIT(pad->voltage)) == 0) BIT 32 drivers/soc/ti/knav_dma.c #define DMA_LOOPBACK BIT(31) BIT 33 drivers/soc/ti/knav_dma.c #define DMA_ENABLE BIT(31) BIT 34 drivers/soc/ti/knav_dma.c #define DMA_TEARDOWN BIT(30) BIT 36 drivers/soc/ti/knav_dma.c #define DMA_TX_FILT_PSWORDS BIT(29) BIT 37 drivers/soc/ti/knav_dma.c #define DMA_TX_FILT_EINFO BIT(30) BIT 46 drivers/soc/ti/knav_dma.c #define CHAN_HAS_EPIB BIT(30) BIT 47 drivers/soc/ti/knav_dma.c #define CHAN_HAS_PSINFO BIT(29) BIT 48 drivers/soc/ti/knav_dma.c #define CHAN_ERR_RETRY BIT(28) BIT 49 drivers/soc/ti/knav_dma.c #define CHAN_PSINFO_AT_SOP BIT(25) BIT 16 drivers/soc/ti/knav_qmss.h #define THRESH_GTE BIT(7) BIT 20 drivers/soc/ti/knav_qmss.h #define PDSP_CTRL_SOFT_RESET BIT(0) BIT 21 drivers/soc/ti/knav_qmss.h #define PDSP_CTRL_ENABLE BIT(1) BIT 22 drivers/soc/ti/knav_qmss.h #define PDSP_CTRL_RUNNING BIT(15) BIT 36 drivers/soc/ti/knav_qmss.h #define ACC_CFG_MULTI_QUEUE BIT(21) BIT 343 drivers/soc/ti/knav_qmss.h #define RANGE_RESERVED BIT(0) BIT 344 drivers/soc/ti/knav_qmss.h #define RANGE_HAS_IRQ BIT(1) BIT 345 drivers/soc/ti/knav_qmss.h #define RANGE_HAS_ACCUMULATOR BIT(2) BIT 346 drivers/soc/ti/knav_qmss.h #define RANGE_MULTI_QUEUE BIT(3) BIT 69 drivers/soc/ti/knav_qmss_acc.c mask = BIT(kq->acc->channel % 32); BIT 216 drivers/soc/ti/knav_qmss_acc.c new = old | BIT(queue); BIT 218 drivers/soc/ti/knav_qmss_acc.c new = old & ~BIT(queue); BIT 313 drivers/soc/ti/knav_qmss_acc.c queue_mask = BIT(range->num_queues) - 1; BIT 24 drivers/soc/xilinx/zynqmp_pm_domains.c #define ZYNQMP_PM_DOMAIN_REQUESTED BIT(0) BIT 31 drivers/soc/zte/zx2967_pm_domains.c val |= BIT(zpd->bit); BIT 33 drivers/soc/zte/zx2967_pm_domains.c val &= ~BIT(zpd->bit); BIT 39 drivers/soc/zte/zx2967_pm_domains.c & BIT(zpd->bit); BIT 48 drivers/soc/zte/zx2967_pm_domains.c val |= BIT(zpd->bit); BIT 53 drivers/soc/zte/zx2967_pm_domains.c val &= ~BIT(zpd->bit); BIT 58 drivers/soc/zte/zx2967_pm_domains.c val |= BIT(zpd->bit); BIT 74 drivers/soc/zte/zx2967_pm_domains.c val &= ~BIT(zpd->bit); BIT 79 drivers/soc/zte/zx2967_pm_domains.c val |= BIT(zpd->bit); BIT 84 drivers/soc/zte/zx2967_pm_domains.c val &= ~BIT(zpd->bit); BIT 90 drivers/soc/zte/zx2967_pm_domains.c val &= ~BIT(zpd->bit); BIT 92 drivers/soc/zte/zx2967_pm_domains.c val |= BIT(zpd->bit); BIT 98 drivers/soc/zte/zx2967_pm_domains.c & BIT(zpd->bit); BIT 314 drivers/soundwire/bus.c msg->addr |= BIT(15); BIT 31 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONFIG_MMASTER BIT(7) BIT 32 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONFIG_BUS_REL BIT(6) BIT 33 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONFIG_SNIFFER BIT(5) BIT 34 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONFIG_SSPMOD BIT(4) BIT 35 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONFIG_CMD BIT(3) BIT 42 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONTROL_CMD_RST BIT(7) BIT 43 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONTROL_SOFT_RST BIT(6) BIT 44 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONTROL_SW_RST BIT(5) BIT 45 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONTROL_HW_RST BIT(4) BIT 46 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONTROL_CLK_PAUSE BIT(3) BIT 47 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONTROL_CLK_STOP_CLR BIT(2) BIT 48 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONTROL_CMD_ACCEPT BIT(1) BIT 49 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONTROL_BLOCK_WAKEUP BIT(0) BIT 59 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONFIG_UPDATE_BIT BIT(0) BIT 70 drivers/soundwire/cadence_master.c #define CDNS_MCP_STAT_ACTIVE_BANK BIT(20) BIT 71 drivers/soundwire/cadence_master.c #define CDNS_MCP_STAT_CLK_STOP BIT(16) BIT 76 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_IRQ BIT(31) BIT 77 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_WAKEUP BIT(16) BIT 78 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_SLAVE_RSVD BIT(15) BIT 79 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_SLAVE_ALERT BIT(14) BIT 80 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_SLAVE_ATTACH BIT(13) BIT 81 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_SLAVE_NATTACH BIT(12) BIT 83 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_DPINT BIT(11) BIT 84 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_CTRL_CLASH BIT(10) BIT 85 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_DATA_CLASH BIT(9) BIT 86 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_PARITY BIT(8) BIT 87 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_CMD_ERR BIT(7) BIT 88 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_RX_NE BIT(3) BIT 89 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_RX_WL BIT(2) BIT 90 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_TXE BIT(1) BIT 91 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_TXF BIT(0) BIT 100 drivers/soundwire/cadence_master.c #define CDNS_MCP_SLAVE_INTSTAT_NPRESENT BIT(0) BIT 101 drivers/soundwire/cadence_master.c #define CDNS_MCP_SLAVE_INTSTAT_ATTACHED BIT(1) BIT 102 drivers/soundwire/cadence_master.c #define CDNS_MCP_SLAVE_INTSTAT_ALERT BIT(2) BIT 103 drivers/soundwire/cadence_master.c #define CDNS_MCP_SLAVE_INTSTAT_RESERVED BIT(3) BIT 125 drivers/soundwire/cadence_master.c #define CDNS_MCP_CMD_SSP_TAG BIT(31) BIT 136 drivers/soundwire/cadence_master.c #define CDNS_MCP_RESP_ACK BIT(0) BIT 137 drivers/soundwire/cadence_master.c #define CDNS_MCP_RESP_NACK BIT(1) BIT 155 drivers/soundwire/cadence_master.c #define CDNS_DPN_CONFIG_BPM BIT(18) BIT 171 drivers/soundwire/cadence_master.c #define CDNS_PORTCTRL_DIRN BIT(7) BIT 172 drivers/soundwire/cadence_master.c #define CDNS_PORTCTRL_BANK_INVERT BIT(8) BIT 178 drivers/soundwire/cadence_master.c #define CDNS_PDI_CONFIG_SOFT_RESET BIT(24) BIT 45 drivers/soundwire/intel.c #define SDW_SHIM_LCTL_SPA BIT(0) BIT 46 drivers/soundwire/intel.c #define SDW_SHIM_LCTL_CPA BIT(8) BIT 50 drivers/soundwire/intel.c #define SDW_SHIM_SYNC_SYNCCPU BIT(15) BIT 52 drivers/soundwire/intel.c #define SDW_SHIM_SYNC_CMDSYNC BIT(16) BIT 53 drivers/soundwire/intel.c #define SDW_SHIM_SYNC_SYNCGO BIT(24) BIT 62 drivers/soundwire/intel.c #define SDW_SHIM_PCMSYCM_DIR BIT(15) BIT 69 drivers/soundwire/intel.c #define SDW_SHIM_IOCTL_MIF BIT(0) BIT 70 drivers/soundwire/intel.c #define SDW_SHIM_IOCTL_CO BIT(1) BIT 71 drivers/soundwire/intel.c #define SDW_SHIM_IOCTL_COE BIT(2) BIT 72 drivers/soundwire/intel.c #define SDW_SHIM_IOCTL_DO BIT(3) BIT 73 drivers/soundwire/intel.c #define SDW_SHIM_IOCTL_DOE BIT(4) BIT 74 drivers/soundwire/intel.c #define SDW_SHIM_IOCTL_BKE BIT(5) BIT 75 drivers/soundwire/intel.c #define SDW_SHIM_IOCTL_WPDD BIT(6) BIT 76 drivers/soundwire/intel.c #define SDW_SHIM_IOCTL_CIBD BIT(8) BIT 77 drivers/soundwire/intel.c #define SDW_SHIM_IOCTL_DIBD BIT(9) BIT 79 drivers/soundwire/intel.c #define SDW_SHIM_CTMCTL_DACTQE BIT(0) BIT 80 drivers/soundwire/intel.c #define SDW_SHIM_CTMCTL_DODS BIT(1) BIT 83 drivers/soundwire/intel.c #define SDW_SHIM_WAKEEN_ENABLE BIT(0) BIT 84 drivers/soundwire/intel.c #define SDW_SHIM_WAKESTS_STATUS BIT(0) BIT 94 drivers/soundwire/intel.c #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1) BIT 118 drivers/soundwire/intel_init.c if (link_mask && !(link_mask & BIT(i))) { BIT 53 drivers/soundwire/mipi_disco.c prop->clk_stop_modes |= BIT(SDW_CLK_STOP_MODE0); BIT 57 drivers/soundwire/mipi_disco.c prop->clk_stop_modes |= BIT(SDW_CLK_STOP_MODE1); BIT 53 drivers/spi/atmel-quadspi.c #define QSPI_CR_QSPIEN BIT(0) BIT 54 drivers/spi/atmel-quadspi.c #define QSPI_CR_QSPIDIS BIT(1) BIT 55 drivers/spi/atmel-quadspi.c #define QSPI_CR_SWRST BIT(7) BIT 56 drivers/spi/atmel-quadspi.c #define QSPI_CR_LASTXFER BIT(24) BIT 59 drivers/spi/atmel-quadspi.c #define QSPI_MR_SMM BIT(0) BIT 60 drivers/spi/atmel-quadspi.c #define QSPI_MR_LLB BIT(1) BIT 61 drivers/spi/atmel-quadspi.c #define QSPI_MR_WDRBT BIT(2) BIT 62 drivers/spi/atmel-quadspi.c #define QSPI_MR_SMRM BIT(3) BIT 75 drivers/spi/atmel-quadspi.c #define QSPI_SR_RDRF BIT(0) BIT 76 drivers/spi/atmel-quadspi.c #define QSPI_SR_TDRE BIT(1) BIT 77 drivers/spi/atmel-quadspi.c #define QSPI_SR_TXEMPTY BIT(2) BIT 78 drivers/spi/atmel-quadspi.c #define QSPI_SR_OVRES BIT(3) BIT 79 drivers/spi/atmel-quadspi.c #define QSPI_SR_CSR BIT(8) BIT 80 drivers/spi/atmel-quadspi.c #define QSPI_SR_CSS BIT(9) BIT 81 drivers/spi/atmel-quadspi.c #define QSPI_SR_INSTRE BIT(10) BIT 82 drivers/spi/atmel-quadspi.c #define QSPI_SR_QSPIENS BIT(24) BIT 87 drivers/spi/atmel-quadspi.c #define QSPI_SCR_CPOL BIT(0) BIT 88 drivers/spi/atmel-quadspi.c #define QSPI_SCR_CPHA BIT(1) BIT 109 drivers/spi/atmel-quadspi.c #define QSPI_IFR_INSTEN BIT(4) BIT 110 drivers/spi/atmel-quadspi.c #define QSPI_IFR_ADDREN BIT(5) BIT 111 drivers/spi/atmel-quadspi.c #define QSPI_IFR_OPTEN BIT(6) BIT 112 drivers/spi/atmel-quadspi.c #define QSPI_IFR_DATAEN BIT(7) BIT 118 drivers/spi/atmel-quadspi.c #define QSPI_IFR_ADDRL BIT(10) BIT 119 drivers/spi/atmel-quadspi.c #define QSPI_IFR_TFRTYP_MEM BIT(12) BIT 120 drivers/spi/atmel-quadspi.c #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13) BIT 121 drivers/spi/atmel-quadspi.c #define QSPI_IFR_CRM BIT(14) BIT 124 drivers/spi/atmel-quadspi.c #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */ BIT 127 drivers/spi/atmel-quadspi.c #define QSPI_SMR_SCREN BIT(0) BIT 128 drivers/spi/atmel-quadspi.c #define QSPI_SMR_RVDIS BIT(1) BIT 131 drivers/spi/atmel-quadspi.c #define QSPI_WPMR_WPEN BIT(0) BIT 136 drivers/spi/atmel-quadspi.c #define QSPI_WPSR_WPVS BIT(0) BIT 70 drivers/spi/spi-altera.c writel(BIT(spi->chip_select), hw->base + ALTERA_SPI_SLAVE_SEL); BIT 46 drivers/spi/spi-armada-3700.c #define A3700_SPI_EN BIT(16) BIT 47 drivers/spi/spi-armada-3700.c #define A3700_SPI_ADDR_NOT_CONFIG BIT(12) BIT 48 drivers/spi/spi-armada-3700.c #define A3700_SPI_WFIFO_OVERFLOW BIT(11) BIT 49 drivers/spi/spi-armada-3700.c #define A3700_SPI_WFIFO_UNDERFLOW BIT(10) BIT 50 drivers/spi/spi-armada-3700.c #define A3700_SPI_RFIFO_OVERFLOW BIT(9) BIT 51 drivers/spi/spi-armada-3700.c #define A3700_SPI_RFIFO_UNDERFLOW BIT(8) BIT 52 drivers/spi/spi-armada-3700.c #define A3700_SPI_WFIFO_FULL BIT(7) BIT 53 drivers/spi/spi-armada-3700.c #define A3700_SPI_WFIFO_EMPTY BIT(6) BIT 54 drivers/spi/spi-armada-3700.c #define A3700_SPI_RFIFO_FULL BIT(5) BIT 55 drivers/spi/spi-armada-3700.c #define A3700_SPI_RFIFO_EMPTY BIT(4) BIT 56 drivers/spi/spi-armada-3700.c #define A3700_SPI_WFIFO_RDY BIT(3) BIT 57 drivers/spi/spi-armada-3700.c #define A3700_SPI_RFIFO_RDY BIT(2) BIT 58 drivers/spi/spi-armada-3700.c #define A3700_SPI_XFER_RDY BIT(1) BIT 59 drivers/spi/spi-armada-3700.c #define A3700_SPI_XFER_DONE BIT(0) BIT 62 drivers/spi/spi-armada-3700.c #define A3700_SPI_WFIFO_THRS BIT(28) BIT 63 drivers/spi/spi-armada-3700.c #define A3700_SPI_RFIFO_THRS BIT(24) BIT 64 drivers/spi/spi-armada-3700.c #define A3700_SPI_AUTO_CS BIT(20) BIT 65 drivers/spi/spi-armada-3700.c #define A3700_SPI_DMA_RD_EN BIT(18) BIT 66 drivers/spi/spi-armada-3700.c #define A3700_SPI_FIFO_MODE BIT(17) BIT 67 drivers/spi/spi-armada-3700.c #define A3700_SPI_SRST BIT(16) BIT 68 drivers/spi/spi-armada-3700.c #define A3700_SPI_XFER_START BIT(15) BIT 69 drivers/spi/spi-armada-3700.c #define A3700_SPI_XFER_STOP BIT(14) BIT 70 drivers/spi/spi-armada-3700.c #define A3700_SPI_INST_PIN BIT(13) BIT 71 drivers/spi/spi-armada-3700.c #define A3700_SPI_ADDR_PIN BIT(12) BIT 72 drivers/spi/spi-armada-3700.c #define A3700_SPI_DATA_PIN1 BIT(11) BIT 73 drivers/spi/spi-armada-3700.c #define A3700_SPI_DATA_PIN0 BIT(10) BIT 74 drivers/spi/spi-armada-3700.c #define A3700_SPI_FIFO_FLUSH BIT(9) BIT 75 drivers/spi/spi-armada-3700.c #define A3700_SPI_RW_EN BIT(8) BIT 76 drivers/spi/spi-armada-3700.c #define A3700_SPI_CLK_POL BIT(7) BIT 77 drivers/spi/spi-armada-3700.c #define A3700_SPI_CLK_PHA BIT(6) BIT 78 drivers/spi/spi-armada-3700.c #define A3700_SPI_BYTE_LEN BIT(5) BIT 79 drivers/spi/spi-armada-3700.c #define A3700_SPI_CLK_PRESCALE BIT(0) BIT 100 drivers/spi/spi-armada-3700.c #define A3700_SPI_CLK_CAPT_EDGE BIT(7) BIT 34 drivers/spi/spi-at91-usart.c #define US_CR_RSTRX BIT(2) BIT 35 drivers/spi/spi-at91-usart.c #define US_CR_RSTTX BIT(3) BIT 36 drivers/spi/spi-at91-usart.c #define US_CR_RXEN BIT(4) BIT 37 drivers/spi/spi-at91-usart.c #define US_CR_RXDIS BIT(5) BIT 38 drivers/spi/spi-at91-usart.c #define US_CR_TXEN BIT(6) BIT 39 drivers/spi/spi-at91-usart.c #define US_CR_TXDIS BIT(7) BIT 43 drivers/spi/spi-at91-usart.c #define US_MR_CPHA BIT(8) BIT 44 drivers/spi/spi-at91-usart.c #define US_MR_CPOL BIT(16) BIT 45 drivers/spi/spi-at91-usart.c #define US_MR_CLKO BIT(18) BIT 46 drivers/spi/spi-at91-usart.c #define US_MR_WRDBT BIT(20) BIT 47 drivers/spi/spi-at91-usart.c #define US_MR_LOOP BIT(15) BIT 49 drivers/spi/spi-at91-usart.c #define US_IR_RXRDY BIT(0) BIT 50 drivers/spi/spi-at91-usart.c #define US_IR_TXRDY BIT(1) BIT 51 drivers/spi/spi-at91-usart.c #define US_IR_OVRE BIT(5) BIT 53 drivers/spi/spi-at91-usart.c #define US_BRGR_SIZE BIT(16) BIT 56 drivers/spi/spi-at91-usart.c #define US_MAX_CLK_DIV BIT(16) BIT 34 drivers/spi/spi-ath79.c #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ BIT 36 drivers/spi/spi-ath79.c #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ BIT 37 drivers/spi/spi-ath79.c #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ BIT 38 drivers/spi/spi-ath79.c #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) BIT 39 drivers/spi/spi-axi-spi-engine.c #define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0) BIT 40 drivers/spi/spi-axi-spi-engine.c #define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1) BIT 41 drivers/spi/spi-axi-spi-engine.c #define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2) BIT 42 drivers/spi/spi-axi-spi-engine.c #define SPI_ENGINE_INT_SYNC BIT(3) BIT 44 drivers/spi/spi-axi-spi-engine.c #define SPI_ENGINE_CONFIG_CPHA BIT(0) BIT 45 drivers/spi/spi-axi-spi-engine.c #define SPI_ENGINE_CONFIG_CPOL BIT(1) BIT 46 drivers/spi/spi-axi-spi-engine.c #define SPI_ENGINE_CONFIG_3WIRE BIT(2) BIT 189 drivers/spi/spi-axi-spi-engine.c mask ^= BIT(spi->chip_select); BIT 64 drivers/spi/spi-bcm-qspi.c #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0) BIT 65 drivers/spi/spi-bcm-qspi.c #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1) BIT 66 drivers/spi/spi-bcm-qspi.c #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2) BIT 67 drivers/spi/spi-bcm-qspi.c #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3) BIT 68 drivers/spi/spi-bcm-qspi.c #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4) BIT 73 drivers/spi/spi-bcm-qspi.c #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1) BIT 75 drivers/spi/spi-bcm-qspi.c #define BSPI_RAF_CTRL_START_MASK BIT(0) BIT 76 drivers/spi/spi-bcm-qspi.c #define BSPI_RAF_CTRL_CLEAR_MASK BIT(1) BIT 78 drivers/spi/spi-bcm-qspi.c #define BSPI_BPP_MODE_SELECT_MASK BIT(8) BIT 79 drivers/spi/spi-bcm-qspi.c #define BSPI_BPP_ADDR_SELECT_MASK BIT(16) BIT 99 drivers/spi/spi-bcm-qspi.c #define MSPI_MASTER_BIT BIT(7) BIT 102 drivers/spi/spi-bcm-qspi.c #define MSPI_CDRAM_CONT_BIT BIT(7) BIT 103 drivers/spi/spi-bcm-qspi.c #define MSPI_CDRAM_BITSE_BIT BIT(6) BIT 106 drivers/spi/spi-bcm-qspi.c #define MSPI_SPCR2_SPE BIT(6) BIT 107 drivers/spi/spi-bcm-qspi.c #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7) BIT 109 drivers/spi/spi-bcm-qspi.c #define MSPI_MSPI_STATUS_SPIF BIT(0) BIT 13 drivers/spi/spi-bcm-qspi.h #define INTR_BSPI_LR_OVERREAD_MASK BIT(4) BIT 14 drivers/spi/spi-bcm-qspi.h #define INTR_BSPI_LR_SESSION_DONE_MASK BIT(3) BIT 15 drivers/spi/spi-bcm-qspi.h #define INTR_BSPI_LR_IMPATIENT_MASK BIT(2) BIT 16 drivers/spi/spi-bcm-qspi.h #define INTR_BSPI_LR_SESSION_ABORTED_MASK BIT(1) BIT 17 drivers/spi/spi-bcm-qspi.h #define INTR_BSPI_LR_FULLNESS_REACHED_MASK BIT(0) BIT 33 drivers/spi/spi-bcm-qspi.h #define INTR_MSPI_HALTED_MASK BIT(6) BIT 34 drivers/spi/spi-bcm-qspi.h #define INTR_MSPI_DONE_MASK BIT(5) BIT 29 drivers/spi/spi-bcm63xx-hsspi.c #define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16) BIT 30 drivers/spi/spi-bcm63xx-hsspi.c #define GLOBAL_CTRL_CLK_POLARITY BIT(17) BIT 31 drivers/spi/spi-bcm63xx-hsspi.c #define GLOBAL_CTRL_MOSI_IDLE BIT(18) BIT 39 drivers/spi/spi-bcm63xx-hsspi.c #define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0) BIT 40 drivers/spi/spi-bcm63xx-hsspi.c #define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1) BIT 41 drivers/spi/spi-bcm63xx-hsspi.c #define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2) BIT 42 drivers/spi/spi-bcm63xx-hsspi.c #define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3) BIT 43 drivers/spi/spi-bcm63xx-hsspi.c #define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4) BIT 61 drivers/spi/spi-bcm63xx-hsspi.c #define CLK_CTRL_SPI_CLK_2X_SEL BIT(14) BIT 62 drivers/spi/spi-bcm63xx-hsspi.c #define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15) BIT 65 drivers/spi/spi-bcm63xx-hsspi.c #define SIGNAL_CTRL_LATCH_RISING BIT(12) BIT 66 drivers/spi/spi-bcm63xx-hsspi.c #define SIGNAL_CTRL_LAUNCH_RISING BIT(13) BIT 67 drivers/spi/spi-bcm63xx-hsspi.c #define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16) BIT 74 drivers/spi/spi-bcm63xx-hsspi.c #define MODE_CTRL_MODE_3WIRE BIT(20) BIT 80 drivers/spi/spi-bcm63xx-hsspi.c #define HSSPI_OP_MULTIBIT BIT(11) BIT 120 drivers/spi/spi-bcm63xx-hsspi.c reg &= ~BIT(cs); BIT 121 drivers/spi/spi-bcm63xx-hsspi.c if (active == !(bs->cs_polarity & BIT(cs))) BIT 122 drivers/spi/spi-bcm63xx-hsspi.c reg |= BIT(cs); BIT 244 drivers/spi/spi-bcm63xx-hsspi.c reg |= BIT(spi->chip_select); BIT 246 drivers/spi/spi-bcm63xx-hsspi.c reg &= ~BIT(spi->chip_select); BIT 251 drivers/spi/spi-bcm63xx-hsspi.c bs->cs_polarity |= BIT(spi->chip_select); BIT 253 drivers/spi/spi-bcm63xx-hsspi.c bs->cs_polarity &= ~BIT(spi->chip_select); BIT 27 drivers/spi/spi-davinci.c #define SPIFMT_PHASE_MASK BIT(16) BIT 28 drivers/spi/spi-davinci.c #define SPIFMT_POLARITY_MASK BIT(17) BIT 29 drivers/spi/spi-davinci.c #define SPIFMT_DISTIMER_MASK BIT(18) BIT 30 drivers/spi/spi-davinci.c #define SPIFMT_SHIFTDIR_MASK BIT(20) BIT 31 drivers/spi/spi-davinci.c #define SPIFMT_WAITENA_MASK BIT(21) BIT 32 drivers/spi/spi-davinci.c #define SPIFMT_PARITYENA_MASK BIT(22) BIT 33 drivers/spi/spi-davinci.c #define SPIFMT_ODD_PARITY_MASK BIT(23) BIT 39 drivers/spi/spi-davinci.c #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ BIT 40 drivers/spi/spi-davinci.c #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ BIT 41 drivers/spi/spi-davinci.c #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ BIT 42 drivers/spi/spi-davinci.c #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ BIT 50 drivers/spi/spi-davinci.c #define SPIDAT1_CSHOLD_MASK BIT(12) BIT 51 drivers/spi/spi-davinci.c #define SPIDAT1_WDEL BIT(10) BIT 54 drivers/spi/spi-davinci.c #define SPIGCR1_CLKMOD_MASK BIT(1) BIT 55 drivers/spi/spi-davinci.c #define SPIGCR1_MASTER_MASK BIT(0) BIT 56 drivers/spi/spi-davinci.c #define SPIGCR1_POWERDOWN_MASK BIT(8) BIT 57 drivers/spi/spi-davinci.c #define SPIGCR1_LOOPBACK_MASK BIT(16) BIT 58 drivers/spi/spi-davinci.c #define SPIGCR1_SPIENA_MASK BIT(24) BIT 61 drivers/spi/spi-davinci.c #define SPIBUF_TXFULL_MASK BIT(29) BIT 62 drivers/spi/spi-davinci.c #define SPIBUF_RXEMPTY_MASK BIT(31) BIT 75 drivers/spi/spi-davinci.c #define SPIFLG_DLEN_ERR_MASK BIT(0) BIT 76 drivers/spi/spi-davinci.c #define SPIFLG_TIMEOUT_MASK BIT(1) BIT 77 drivers/spi/spi-davinci.c #define SPIFLG_PARERR_MASK BIT(2) BIT 78 drivers/spi/spi-davinci.c #define SPIFLG_DESYNC_MASK BIT(3) BIT 79 drivers/spi/spi-davinci.c #define SPIFLG_BITERR_MASK BIT(4) BIT 80 drivers/spi/spi-davinci.c #define SPIFLG_OVRRUN_MASK BIT(6) BIT 81 drivers/spi/spi-davinci.c #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) BIT 87 drivers/spi/spi-davinci.c #define SPIINT_DMA_REQ_EN BIT(16) BIT 74 drivers/spi/spi-dln2.c #define DLN2_SPI_ATTR_LEAVE_SS_LOW BIT(0) BIT 155 drivers/spi/spi-dln2.c return dln2_spi_cs_set(dln2, BIT(cs)); BIT 343 drivers/spi/spi-dln2.c *bpw_mask |= BIT(rx->frame_sizes[i] - 1); BIT 43 drivers/spi/spi-dw-mmio.c #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13) BIT 69 drivers/spi/spi-dw-mmio.c sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs)); BIT 145 drivers/spi/spi-dw.c dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); BIT 38 drivers/spi/spi-ep93xx.c #define SSPCR1_RIE BIT(0) BIT 39 drivers/spi/spi-ep93xx.c #define SSPCR1_TIE BIT(1) BIT 40 drivers/spi/spi-ep93xx.c #define SSPCR1_RORIE BIT(2) BIT 41 drivers/spi/spi-ep93xx.c #define SSPCR1_LBM BIT(3) BIT 42 drivers/spi/spi-ep93xx.c #define SSPCR1_SSE BIT(4) BIT 43 drivers/spi/spi-ep93xx.c #define SSPCR1_MS BIT(5) BIT 44 drivers/spi/spi-ep93xx.c #define SSPCR1_SOD BIT(6) BIT 49 drivers/spi/spi-ep93xx.c #define SSPSR_TFE BIT(0) BIT 50 drivers/spi/spi-ep93xx.c #define SSPSR_TNF BIT(1) BIT 51 drivers/spi/spi-ep93xx.c #define SSPSR_RNE BIT(2) BIT 52 drivers/spi/spi-ep93xx.c #define SSPSR_RFF BIT(3) BIT 53 drivers/spi/spi-ep93xx.c #define SSPSR_BSY BIT(4) BIT 57 drivers/spi/spi-ep93xx.c #define SSPIIR_RIS BIT(0) BIT 58 drivers/spi/spi-ep93xx.c #define SSPIIR_TIS BIT(1) BIT 59 drivers/spi/spi-ep93xx.c #define SSPIIR_RORIS BIT(2) BIT 31 drivers/spi/spi-fsl-dspi.c #define SPI_MCR_MASTER BIT(31) BIT 33 drivers/spi/spi-fsl-dspi.c #define SPI_MCR_CLR_TXF BIT(11) BIT 34 drivers/spi/spi-fsl-dspi.c #define SPI_MCR_CLR_RXF BIT(10) BIT 35 drivers/spi/spi-fsl-dspi.c #define SPI_MCR_XSPI BIT(3) BIT 42 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_CPOL BIT(26) BIT 43 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_CPHA BIT(25) BIT 44 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_LSBFE BIT(24) BIT 58 drivers/spi/spi-fsl-dspi.c #define SPI_SR_TCFQF BIT(31) BIT 59 drivers/spi/spi-fsl-dspi.c #define SPI_SR_EOQF BIT(28) BIT 60 drivers/spi/spi-fsl-dspi.c #define SPI_SR_TFUF BIT(27) BIT 61 drivers/spi/spi-fsl-dspi.c #define SPI_SR_TFFF BIT(25) BIT 62 drivers/spi/spi-fsl-dspi.c #define SPI_SR_CMDTCF BIT(23) BIT 63 drivers/spi/spi-fsl-dspi.c #define SPI_SR_SPEF BIT(21) BIT 64 drivers/spi/spi-fsl-dspi.c #define SPI_SR_RFOF BIT(19) BIT 65 drivers/spi/spi-fsl-dspi.c #define SPI_SR_TFIWF BIT(18) BIT 66 drivers/spi/spi-fsl-dspi.c #define SPI_SR_RFDF BIT(17) BIT 67 drivers/spi/spi-fsl-dspi.c #define SPI_SR_CMDFFF BIT(16) BIT 74 drivers/spi/spi-fsl-dspi.c #define SPI_RSER_TFFFE BIT(25) BIT 75 drivers/spi/spi-fsl-dspi.c #define SPI_RSER_TFFFD BIT(24) BIT 76 drivers/spi/spi-fsl-dspi.c #define SPI_RSER_RFDFE BIT(17) BIT 77 drivers/spi/spi-fsl-dspi.c #define SPI_RSER_RFDFD BIT(16) BIT 80 drivers/spi/spi-fsl-dspi.c #define SPI_RSER_TCFQE BIT(31) BIT 81 drivers/spi/spi-fsl-dspi.c #define SPI_RSER_EOQFE BIT(28) BIT 84 drivers/spi/spi-fsl-dspi.c #define SPI_PUSHR_CMD_CONT BIT(15) BIT 86 drivers/spi/spi-fsl-dspi.c #define SPI_PUSHR_CMD_EOQ BIT(11) BIT 87 drivers/spi/spi-fsl-dspi.c #define SPI_PUSHR_CMD_CTCNT BIT(10) BIT 88 drivers/spi/spi-fsl-dspi.c #define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0)) BIT 34 drivers/spi/spi-fsl-espi.c #define SPMODE_ENABLE BIT(31) BIT 35 drivers/spi/spi-fsl-espi.c #define SPMODE_LOOP BIT(30) BIT 40 drivers/spi/spi-fsl-espi.c #define CSMODE_CI_INACTIVEHIGH BIT(31) BIT 41 drivers/spi/spi-fsl-espi.c #define CSMODE_CP_BEGIN_EDGECLK BIT(30) BIT 42 drivers/spi/spi-fsl-espi.c #define CSMODE_REV BIT(29) BIT 43 drivers/spi/spi-fsl-espi.c #define CSMODE_DIV16 BIT(28) BIT 45 drivers/spi/spi-fsl-espi.c #define CSMODE_POL_1 BIT(20) BIT 62 drivers/spi/spi-fsl-espi.c #define SPIE_TXE BIT(15) /* TX FIFO empty */ BIT 63 drivers/spi/spi-fsl-espi.c #define SPIE_DON BIT(14) /* TX done */ BIT 64 drivers/spi/spi-fsl-espi.c #define SPIE_RXT BIT(13) /* RX FIFO threshold */ BIT 65 drivers/spi/spi-fsl-espi.c #define SPIE_RXF BIT(12) /* RX FIFO full */ BIT 66 drivers/spi/spi-fsl-espi.c #define SPIE_TXT BIT(11) /* TX FIFO threshold*/ BIT 67 drivers/spi/spi-fsl-espi.c #define SPIE_RNE BIT(9) /* RX FIFO not empty */ BIT 68 drivers/spi/spi-fsl-espi.c #define SPIE_TNF BIT(8) /* TX FIFO not full */ BIT 71 drivers/spi/spi-fsl-espi.c #define SPIM_TXE BIT(15) /* TX FIFO empty */ BIT 72 drivers/spi/spi-fsl-espi.c #define SPIM_DON BIT(14) /* TX done */ BIT 73 drivers/spi/spi-fsl-espi.c #define SPIM_RXT BIT(13) /* RX FIFO threshold */ BIT 74 drivers/spi/spi-fsl-espi.c #define SPIM_RXF BIT(12) /* RX FIFO full */ BIT 75 drivers/spi/spi-fsl-espi.c #define SPIM_TXT BIT(11) /* TX FIFO threshold*/ BIT 76 drivers/spi/spi-fsl-espi.c #define SPIM_RNE BIT(9) /* RX FIFO not empty */ BIT 77 drivers/spi/spi-fsl-espi.c #define SPIM_TNF BIT(8) /* TX FIFO not full */ BIT 81 drivers/spi/spi-fsl-espi.c #define SPCOM_DO BIT(28) /* Dual output */ BIT 82 drivers/spi/spi-fsl-espi.c #define SPCOM_TO BIT(27) /* TX only */ BIT 60 drivers/spi/spi-fsl-lpspi.c #define CR_RRF BIT(9) BIT 61 drivers/spi/spi-fsl-lpspi.c #define CR_RTF BIT(8) BIT 62 drivers/spi/spi-fsl-lpspi.c #define CR_RST BIT(1) BIT 63 drivers/spi/spi-fsl-lpspi.c #define CR_MEN BIT(0) BIT 64 drivers/spi/spi-fsl-lpspi.c #define SR_MBF BIT(24) BIT 65 drivers/spi/spi-fsl-lpspi.c #define SR_TCF BIT(10) BIT 66 drivers/spi/spi-fsl-lpspi.c #define SR_FCF BIT(9) BIT 67 drivers/spi/spi-fsl-lpspi.c #define SR_RDF BIT(1) BIT 68 drivers/spi/spi-fsl-lpspi.c #define SR_TDF BIT(0) BIT 69 drivers/spi/spi-fsl-lpspi.c #define IER_TCIE BIT(10) BIT 70 drivers/spi/spi-fsl-lpspi.c #define IER_FCIE BIT(9) BIT 71 drivers/spi/spi-fsl-lpspi.c #define IER_RDIE BIT(1) BIT 72 drivers/spi/spi-fsl-lpspi.c #define IER_TDIE BIT(0) BIT 73 drivers/spi/spi-fsl-lpspi.c #define DER_RDDE BIT(1) BIT 74 drivers/spi/spi-fsl-lpspi.c #define DER_TDDE BIT(0) BIT 75 drivers/spi/spi-fsl-lpspi.c #define CFGR1_PCSCFG BIT(27) BIT 76 drivers/spi/spi-fsl-lpspi.c #define CFGR1_PINCFG (BIT(24)|BIT(25)) BIT 77 drivers/spi/spi-fsl-lpspi.c #define CFGR1_PCSPOL BIT(8) BIT 78 drivers/spi/spi-fsl-lpspi.c #define CFGR1_NOSTALL BIT(3) BIT 79 drivers/spi/spi-fsl-lpspi.c #define CFGR1_MASTER BIT(0) BIT 81 drivers/spi/spi-fsl-lpspi.c #define RSR_RXEMPTY BIT(1) BIT 82 drivers/spi/spi-fsl-lpspi.c #define TCR_CPOL BIT(31) BIT 83 drivers/spi/spi-fsl-lpspi.c #define TCR_CPHA BIT(30) BIT 84 drivers/spi/spi-fsl-lpspi.c #define TCR_CONT BIT(21) BIT 85 drivers/spi/spi-fsl-lpspi.c #define TCR_CONTC BIT(20) BIT 86 drivers/spi/spi-fsl-lpspi.c #define TCR_RXMSK BIT(19) BIT 87 drivers/spi/spi-fsl-lpspi.c #define TCR_TXMSK BIT(18) BIT 55 drivers/spi/spi-fsl-qspi.c #define QUADSPI_MCR_MDIS_MASK BIT(14) BIT 56 drivers/spi/spi-fsl-qspi.c #define QUADSPI_MCR_CLR_TXF_MASK BIT(11) BIT 57 drivers/spi/spi-fsl-qspi.c #define QUADSPI_MCR_CLR_RXF_MASK BIT(10) BIT 58 drivers/spi/spi-fsl-qspi.c #define QUADSPI_MCR_DDR_EN_MASK BIT(7) BIT 60 drivers/spi/spi-fsl-qspi.c #define QUADSPI_MCR_SWRSTHD_MASK BIT(1) BIT 61 drivers/spi/spi-fsl-qspi.c #define QUADSPI_MCR_SWRSTSD_MASK BIT(0) BIT 72 drivers/spi/spi-fsl-qspi.c #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31) BIT 86 drivers/spi/spi-fsl-qspi.c #define QUADSPI_SMPR_FSDLY_MASK BIT(6) BIT 87 drivers/spi/spi-fsl-qspi.c #define QUADSPI_SMPR_FSPHS_MASK BIT(5) BIT 88 drivers/spi/spi-fsl-qspi.c #define QUADSPI_SMPR_HSENA_MASK BIT(0) BIT 92 drivers/spi/spi-fsl-qspi.c #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8) BIT 97 drivers/spi/spi-fsl-qspi.c #define QUADSPI_SR_IP_ACC_MASK BIT(1) BIT 98 drivers/spi/spi-fsl-qspi.c #define QUADSPI_SR_AHB_ACC_MASK BIT(2) BIT 101 drivers/spi/spi-fsl-qspi.c #define QUADSPI_FR_TFF_MASK BIT(0) BIT 104 drivers/spi/spi-fsl-qspi.c #define QUADSPI_RSER_TFIE BIT(0) BIT 107 drivers/spi/spi-fsl-qspi.c #define QUADSPI_SPTRCLR_IPPTRC BIT(8) BIT 108 drivers/spi/spi-fsl-qspi.c #define QUADSPI_SPTRCLR_BFPTRC BIT(0) BIT 120 drivers/spi/spi-fsl-qspi.c #define QUADSPI_LCKER_LOCK BIT(0) BIT 121 drivers/spi/spi-fsl-qspi.c #define QUADSPI_LCKER_UNLOCK BIT(1) BIT 168 drivers/spi/spi-fsl-qspi.c #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0) BIT 171 drivers/spi/spi-fsl-qspi.c #define QUADSPI_QUIRK_4X_INT_CLK BIT(1) BIT 178 drivers/spi/spi-fsl-qspi.c #define QUADSPI_QUIRK_TKT253890 BIT(2) BIT 181 drivers/spi/spi-fsl-qspi.c #define QUADSPI_QUIRK_TKT245618 BIT(3) BIT 187 drivers/spi/spi-fsl-qspi.c #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4) BIT 193 drivers/spi/spi-fsl-qspi.c #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5) BIT 18 drivers/spi/spi-geni-qcom.c #define CPHA BIT(0) BIT 26 drivers/spi/spi-geni-qcom.c #define CPOL BIT(2) BIT 35 drivers/spi/spi-geni-qcom.c #define CS_TOGGLE BIT(0) BIT 61 drivers/spi/spi-geni-qcom.c #define SPI_PRE_CMD_DELAY BIT(0) BIT 62 drivers/spi/spi-geni-qcom.c #define TIMESTAMP_BEFORE BIT(1) BIT 63 drivers/spi/spi-geni-qcom.c #define FRAGMENTATION BIT(2) BIT 64 drivers/spi/spi-geni-qcom.c #define TIMESTAMP_AFTER BIT(3) BIT 65 drivers/spi/spi-geni-qcom.c #define POST_CMD_DELAY BIT(4) BIT 225 drivers/spi/spi-geni-qcom.c demux_output_inv = BIT(spi_slv->chip_select); BIT 36 drivers/spi/spi-img-spfi.c #define SPFI_CONTROL_CONTINUE BIT(12) BIT 37 drivers/spi/spi-img-spfi.c #define SPFI_CONTROL_SOFT_RESET BIT(11) BIT 38 drivers/spi/spi-img-spfi.c #define SPFI_CONTROL_SEND_DMA BIT(10) BIT 39 drivers/spi/spi-img-spfi.c #define SPFI_CONTROL_GET_DMA BIT(9) BIT 40 drivers/spi/spi-img-spfi.c #define SPFI_CONTROL_SE BIT(8) BIT 46 drivers/spi/spi-img-spfi.c #define SPFI_CONTROL_SPFI_EN BIT(0) BIT 55 drivers/spi/spi-img-spfi.c #define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x)) BIT 56 drivers/spi/spi-img-spfi.c #define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x)) BIT 66 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_IACCESS BIT(12) BIT 67 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_GDEX8BIT BIT(11) BIT 68 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_ALLDONETRIG BIT(9) BIT 69 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_GDFUL BIT(8) BIT 70 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_GDHF BIT(7) BIT 71 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_GDEX32BIT BIT(6) BIT 72 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_GDTRIG BIT(5) BIT 73 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_SDFUL BIT(3) BIT 74 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_SDHF BIT(2) BIT 75 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_SDE BIT(1) BIT 76 drivers/spi/spi-img-spfi.c #define SPFI_INTERRUPT_SDTRIG BIT(0) BIT 44 drivers/spi/spi-imx.c #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ BIT 280 drivers/spi/spi-imx.c #define MX51_ECSPI_TESTREG_LBC BIT(31) BIT 60 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ BIT 61 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ BIT 75 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ BIT 76 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ BIT 77 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ BIT 78 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ BIT 79 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ BIT 80 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ BIT 81 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ BIT 82 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ BIT 83 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ BIT 84 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ BIT 85 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ BIT 86 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_HB BIT(4) /* Heading control */ BIT 87 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ BIT 88 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ BIT 92 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ BIT 93 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ BIT 94 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ BIT 95 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ BIT 96 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ BIT 97 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ BIT 98 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */ BIT 99 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ BIT 100 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ BIT 105 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ BIT 106 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ BIT 107 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ BIT 108 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ BIT 109 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ BIT 110 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ BIT 111 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ BIT 112 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ BIT 113 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ BIT 114 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ BIT 115 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ BIT 116 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ BIT 117 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ BIT 118 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ BIT 119 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ BIT 120 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ BIT 130 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ BIT 131 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ BIT 135 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ BIT 136 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ BIT 152 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ BIT 153 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ BIT 154 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ BIT 155 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ BIT 156 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ BIT 157 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ BIT 158 drivers/spi/spi-lantiq-ssc.c #define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ BIT 133 drivers/spi/spi-loopback-test.c .iterate_transfer_mask = BIT(0) | BIT(1), BIT 150 drivers/spi/spi-loopback-test.c .iterate_transfer_mask = BIT(0), BIT 167 drivers/spi/spi-loopback-test.c .iterate_transfer_mask = BIT(1), BIT 184 drivers/spi/spi-loopback-test.c .iterate_transfer_mask = BIT(0) | BIT(1), BIT 200 drivers/spi/spi-loopback-test.c .iterate_transfer_mask = BIT(0), BIT 217 drivers/spi/spi-loopback-test.c .iterate_transfer_mask = BIT(1), BIT 234 drivers/spi/spi-loopback-test.c .iterate_transfer_mask = BIT(0) | BIT(1), BIT 255 drivers/spi/spi-loopback-test.c .iterate_transfer_mask = BIT(0), BIT 276 drivers/spi/spi-loopback-test.c .iterate_transfer_mask = BIT(1), BIT 295 drivers/spi/spi-loopback-test.c .iterate_transfer_mask = BIT(0) | BIT(1), BIT 826 drivers/spi/spi-loopback-test.c if (!(test.iterate_transfer_mask & (BIT(test.transfer_count) - 1))) BIT 866 drivers/spi/spi-loopback-test.c if (!(test.iterate_transfer_mask & BIT(i))) BIT 46 drivers/spi/spi-meson-spicc.c #define SPICC_ENABLE BIT(0) BIT 47 drivers/spi/spi-meson-spicc.c #define SPICC_MODE_MASTER BIT(1) BIT 48 drivers/spi/spi-meson-spicc.c #define SPICC_XCH BIT(2) BIT 49 drivers/spi/spi-meson-spicc.c #define SPICC_SMC BIT(3) BIT 50 drivers/spi/spi-meson-spicc.c #define SPICC_POL BIT(4) BIT 51 drivers/spi/spi-meson-spicc.c #define SPICC_PHA BIT(5) BIT 52 drivers/spi/spi-meson-spicc.c #define SPICC_SSCTL BIT(6) BIT 53 drivers/spi/spi-meson-spicc.c #define SPICC_SSPOL BIT(7) BIT 68 drivers/spi/spi-meson-spicc.c #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */ BIT 69 drivers/spi/spi-meson-spicc.c #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */ BIT 70 drivers/spi/spi-meson-spicc.c #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */ BIT 71 drivers/spi/spi-meson-spicc.c #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */ BIT 72 drivers/spi/spi-meson-spicc.c #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */ BIT 73 drivers/spi/spi-meson-spicc.c #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */ BIT 74 drivers/spi/spi-meson-spicc.c #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */ BIT 75 drivers/spi/spi-meson-spicc.c #define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */ BIT 78 drivers/spi/spi-meson-spicc.c #define SPICC_DMA_ENABLE BIT(0) BIT 83 drivers/spi/spi-meson-spicc.c #define SPICC_DMA_URGENT BIT(19) BIT 88 drivers/spi/spi-meson-spicc.c #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */ BIT 89 drivers/spi/spi-meson-spicc.c #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */ BIT 90 drivers/spi/spi-meson-spicc.c #define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */ BIT 91 drivers/spi/spi-meson-spicc.c #define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */ BIT 92 drivers/spi/spi-meson-spicc.c #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */ BIT 93 drivers/spi/spi-meson-spicc.c #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */ BIT 94 drivers/spi/spi-meson-spicc.c #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */ BIT 95 drivers/spi/spi-meson-spicc.c #define SPICC_TC BIT(7) /* Transfert Complete Interrupt */ BIT 104 drivers/spi/spi-meson-spicc.c #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */ BIT 105 drivers/spi/spi-meson-spicc.c #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */ BIT 106 drivers/spi/spi-meson-spicc.c #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */ BIT 107 drivers/spi/spi-meson-spicc.c #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */ BIT 448 drivers/spi/spi-meson-spicc.c writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG); BIT 43 drivers/spi/spi-meson-spifc.c #define CMD_USER BIT(18) BIT 44 drivers/spi/spi-meson-spifc.c #define CTRL_ENABLE_AHB BIT(17) BIT 45 drivers/spi/spi-meson-spifc.c #define CLOCK_SOURCE BIT(31) BIT 52 drivers/spi/spi-meson-spifc.c #define USER_DIN_EN_MS BIT(0) BIT 53 drivers/spi/spi-meson-spifc.c #define USER_CMP_MODE BIT(2) BIT 54 drivers/spi/spi-meson-spifc.c #define USER_UC_DOUT_SEL BIT(27) BIT 55 drivers/spi/spi-meson-spifc.c #define USER_UC_DIN_SEL BIT(28) BIT 56 drivers/spi/spi-meson-spifc.c #define USER_UC_MASK ((BIT(5) - 1) << 27) BIT 61 drivers/spi/spi-meson-spifc.c #define USER4_CS_ACT BIT(30) BIT 62 drivers/spi/spi-meson-spifc.c #define SLAVE_TRST_DONE BIT(4) BIT 63 drivers/spi/spi-meson-spifc.c #define SLAVE_OP_MODE BIT(30) BIT 64 drivers/spi/spi-meson-spifc.c #define SLAVE_SW_RST BIT(31) BIT 52 drivers/spi/spi-mt65xx.c #define SPI_CMD_ACT BIT(0) BIT 53 drivers/spi/spi-mt65xx.c #define SPI_CMD_RESUME BIT(1) BIT 54 drivers/spi/spi-mt65xx.c #define SPI_CMD_RST BIT(2) BIT 55 drivers/spi/spi-mt65xx.c #define SPI_CMD_PAUSE_EN BIT(4) BIT 56 drivers/spi/spi-mt65xx.c #define SPI_CMD_DEASSERT BIT(5) BIT 57 drivers/spi/spi-mt65xx.c #define SPI_CMD_SAMPLE_SEL BIT(6) BIT 58 drivers/spi/spi-mt65xx.c #define SPI_CMD_CS_POL BIT(7) BIT 59 drivers/spi/spi-mt65xx.c #define SPI_CMD_CPHA BIT(8) BIT 60 drivers/spi/spi-mt65xx.c #define SPI_CMD_CPOL BIT(9) BIT 61 drivers/spi/spi-mt65xx.c #define SPI_CMD_RX_DMA BIT(10) BIT 62 drivers/spi/spi-mt65xx.c #define SPI_CMD_TX_DMA BIT(11) BIT 63 drivers/spi/spi-mt65xx.c #define SPI_CMD_TXMSBF BIT(12) BIT 64 drivers/spi/spi-mt65xx.c #define SPI_CMD_RXMSBF BIT(13) BIT 65 drivers/spi/spi-mt65xx.c #define SPI_CMD_RX_ENDIAN BIT(14) BIT 66 drivers/spi/spi-mt65xx.c #define SPI_CMD_TX_ENDIAN BIT(15) BIT 67 drivers/spi/spi-mt65xx.c #define SPI_CMD_FINISH_IE BIT(16) BIT 68 drivers/spi/spi-mt65xx.c #define SPI_CMD_PAUSE_IE BIT(17) BIT 27 drivers/spi/spi-mt7621.c #define SPISTAT_BUSY BIT(0) BIT 30 drivers/spi/spi-mt7621.c #define SPITRANS_BUSY BIT(16) BIT 36 drivers/spi/spi-mt7621.c #define SPI_CTL_START BIT(8) BIT 39 drivers/spi/spi-mt7621.c #define MASTER_MORE_BUFMODE BIT(2) BIT 40 drivers/spi/spi-mt7621.c #define MASTER_FULL_DUPLEX BIT(10) BIT 49 drivers/spi/spi-mt7621.c #define MT7621_CPHA BIT(5) BIT 50 drivers/spi/spi-mt7621.c #define MT7621_CPOL BIT(4) BIT 51 drivers/spi/spi-mt7621.c #define MT7621_LSB_FIRST BIT(3) BIT 97 drivers/spi/spi-mt7621.c polar = BIT(cs); BIT 22 drivers/spi/spi-mxic.c #define HC_CFG_DUAL_SLAVE BIT(31) BIT 23 drivers/spi/spi-mxic.c #define HC_CFG_INDIVIDUAL BIT(30) BIT 31 drivers/spi/spi-mxic.c #define HC_CFG_CLK_PH_EN BIT(20) BIT 32 drivers/spi/spi-mxic.c #define HC_CFG_CLK_POL_INV BIT(19) BIT 33 drivers/spi/spi-mxic.c #define HC_CFG_BIG_ENDIAN BIT(18) BIT 34 drivers/spi/spi-mxic.c #define HC_CFG_DATA_PASS BIT(17) BIT 36 drivers/spi/spi-mxic.c #define HC_CFG_MAN_START_EN BIT(3) BIT 37 drivers/spi/spi-mxic.c #define HC_CFG_MAN_START BIT(2) BIT 38 drivers/spi/spi-mxic.c #define HC_CFG_MAN_CS_EN BIT(1) BIT 39 drivers/spi/spi-mxic.c #define HC_CFG_MAN_CS_ASSERT BIT(0) BIT 45 drivers/spi/spi-mxic.c #define INT_RDY_PIN BIT(26) BIT 46 drivers/spi/spi-mxic.c #define INT_RDY_SR BIT(25) BIT 47 drivers/spi/spi-mxic.c #define INT_LNR_SUSP BIT(24) BIT 48 drivers/spi/spi-mxic.c #define INT_ECC_ERR BIT(17) BIT 49 drivers/spi/spi-mxic.c #define INT_CRC_ERR BIT(16) BIT 50 drivers/spi/spi-mxic.c #define INT_LWR_DIS BIT(12) BIT 51 drivers/spi/spi-mxic.c #define INT_LRD_DIS BIT(11) BIT 52 drivers/spi/spi-mxic.c #define INT_SDMA_INT BIT(10) BIT 53 drivers/spi/spi-mxic.c #define INT_DMA_FINISH BIT(9) BIT 54 drivers/spi/spi-mxic.c #define INT_RX_NOT_FULL BIT(3) BIT 55 drivers/spi/spi-mxic.c #define INT_RX_NOT_EMPTY BIT(2) BIT 56 drivers/spi/spi-mxic.c #define INT_TX_NOT_FULL BIT(1) BIT 57 drivers/spi/spi-mxic.c #define INT_TX_EMPTY BIT(0) BIT 60 drivers/spi/spi-mxic.c #define HC_EN_BIT BIT(0) BIT 69 drivers/spi/spi-mxic.c #define OP_READ BIT(23) BIT 73 drivers/spi/spi-mxic.c #define OP_OCTA_CRC_EN BIT(12) BIT 74 drivers/spi/spi-mxic.c #define OP_DQS_EN BIT(11) BIT 75 drivers/spi/spi-mxic.c #define OP_ENHC_EN BIT(10) BIT 76 drivers/spi/spi-mxic.c #define OP_PREAMBLE_EN BIT(9) BIT 77 drivers/spi/spi-mxic.c #define OP_DATA_DDR BIT(8) BIT 79 drivers/spi/spi-mxic.c #define OP_ADDR_DDR BIT(5) BIT 81 drivers/spi/spi-mxic.c #define OP_CMD_DDR BIT(2) BIT 89 drivers/spi/spi-mxic.c #define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16)) BIT 91 drivers/spi/spi-mxic.c #define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16)) BIT 98 drivers/spi/spi-mxic.c #define LMODE_EN BIT(31) BIT 112 drivers/spi/spi-mxic.c #define DMAC_CFG_PERIPH_EN BIT(31) BIT 113 drivers/spi/spi-mxic.c #define DMAC_CFG_ALLFLUSH_EN BIT(30) BIT 114 drivers/spi/spi-mxic.c #define DMAC_CFG_LASTFLUSH_EN BIT(29) BIT 118 drivers/spi/spi-mxic.c #define DMAC_CFG_DIR_READ BIT(1) BIT 119 drivers/spi/spi-mxic.c #define DMAC_CFG_START BIT(0) BIT 127 drivers/spi/spi-mxic.c #define DMAM_CFG_START BIT(31) BIT 128 drivers/spi/spi-mxic.c #define DMAM_CFG_CONT BIT(30) BIT 130 drivers/spi/spi-mxic.c #define DMAM_CFG_DIR_READ BIT(1) BIT 131 drivers/spi/spi-mxic.c #define DMAM_CFG_EN BIT(0) BIT 141 drivers/spi/spi-mxic.c #define RDM_CFG1_RDM_EN BIT(31) BIT 145 drivers/spi/spi-mxic.c #define LWR_SUSP_CTRL_EN BIT(31) BIT 148 drivers/spi/spi-mxic.c #define DMAS_CTRL_DIR_READ BIT(31) BIT 149 drivers/spi/spi-mxic.c #define DMAS_CTRL_EN BIT(30) BIT 152 drivers/spi/spi-mxic.c #define DATA_STROB_EDO_EN BIT(2) BIT 153 drivers/spi/spi-mxic.c #define DATA_STROB_INV_POL BIT(1) BIT 154 drivers/spi/spi-mxic.c #define DATA_STROB_DELAY_2CYC BIT(0) BIT 160 drivers/spi/spi-mxic.c #define GPIO_PT(x) BIT(3 + ((x) * 16)) BIT 161 drivers/spi/spi-mxic.c #define GPIO_RESET(x) BIT(2 + ((x) * 16)) BIT 162 drivers/spi/spi-mxic.c #define GPIO_HOLDB(x) BIT(1 + ((x) * 16)) BIT 163 drivers/spi/spi-mxic.c #define GPIO_WPB(x) BIT((x) * 16) BIT 20 drivers/spi/spi-npcm-fiu.c #define NPCM7XX_INTCR3_FIU_FIX BIT(6) BIT 41 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DRD_CFG_LCK BIT(31) BIT 52 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DWR_CFG_LCK BIT(31) BIT 63 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_LCK BIT(31) BIT 64 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_CMMLCK BIT(30) BIT 69 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_CMDSIZ BIT(10) BIT 85 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CTS_RDYIE BIT(25) BIT 86 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CTS_RDYST BIT(24) BIT 87 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CTS_SW_CS BIT(16) BIT 89 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CTS_EXEC_DONE BIT(0) BIT 320 drivers/spi/spi-npcm-fiu.c u32 uma_cfg = BIT(10); BIT 375 drivers/spi/spi-npcm-fiu.c u32 uma_cfg = BIT(10); BIT 45 drivers/spi/spi-npcm-pspi.c #define NPCM_PSPI_CTL1_SPIEN BIT(0) BIT 46 drivers/spi/spi-npcm-pspi.c #define NPCM_PSPI_CTL1_MOD BIT(2) BIT 47 drivers/spi/spi-npcm-pspi.c #define NPCM_PSPI_CTL1_EIR BIT(5) BIT 48 drivers/spi/spi-npcm-pspi.c #define NPCM_PSPI_CTL1_EIW BIT(6) BIT 49 drivers/spi/spi-npcm-pspi.c #define NPCM_PSPI_CTL1_SCM BIT(7) BIT 50 drivers/spi/spi-npcm-pspi.c #define NPCM_PSPI_CTL1_SCIDL BIT(8) BIT 53 drivers/spi/spi-npcm-pspi.c #define NPCM_PSPI_STAT_BSY BIT(0) BIT 54 drivers/spi/spi-npcm-pspi.c #define NPCM_PSPI_STAT_RBF BIT(1) BIT 65 drivers/spi/spi-npcm-pspi.c #define NPCM7XX_PSPI1_RESET BIT(22) BIT 66 drivers/spi/spi-npcm-pspi.c #define NPCM7XX_PSPI2_RESET BIT(23) BIT 66 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR0_LEARN_EN BIT(15) BIT 67 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR0_SCRFRUN_EN BIT(14) BIT 68 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR0_OCTCOMB_EN BIT(13) BIT 69 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR0_DOZE_EN BIT(12) BIT 70 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR0_HSEN BIT(11) BIT 71 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR0_SERCLKDIV BIT(8) BIT 72 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR0_ATDF_EN BIT(7) BIT 73 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR0_ARDF_EN BIT(6) BIT 76 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR0_MDIS BIT(1) BIT 77 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR0_SWRST BIT(0) BIT 85 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_SAMEDEVICEEN BIT(15) BIT 86 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_CLRLRPHS BIT(14) BIT 87 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_ABRDATSZ BIT(8) BIT 88 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_ABRLEARN BIT(7) BIT 89 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_ABR_READ BIT(6) BIT 90 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_ABRWRITE BIT(5) BIT 91 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_ABRDUMMY BIT(4) BIT 92 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_ABR_MODE BIT(3) BIT 93 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_ABRCADDR BIT(2) BIT 94 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_ABRRADDR BIT(1) BIT 95 drivers/spi/spi-nxp-fspi.c #define FSPI_MCR2_ABR_CMD BIT(0) BIT 98 drivers/spi/spi-nxp-fspi.c #define FSPI_AHBCR_RDADDROPT BIT(6) BIT 99 drivers/spi/spi-nxp-fspi.c #define FSPI_AHBCR_PREF_EN BIT(5) BIT 100 drivers/spi/spi-nxp-fspi.c #define FSPI_AHBCR_BUFF_EN BIT(4) BIT 101 drivers/spi/spi-nxp-fspi.c #define FSPI_AHBCR_CACH_EN BIT(3) BIT 102 drivers/spi/spi-nxp-fspi.c #define FSPI_AHBCR_CLRTXBUF BIT(2) BIT 103 drivers/spi/spi-nxp-fspi.c #define FSPI_AHBCR_CLRRXBUF BIT(1) BIT 104 drivers/spi/spi-nxp-fspi.c #define FSPI_AHBCR_PAR_EN BIT(0) BIT 107 drivers/spi/spi-nxp-fspi.c #define FSPI_INTEN_SCLKSBWR BIT(9) BIT 108 drivers/spi/spi-nxp-fspi.c #define FSPI_INTEN_SCLKSBRD BIT(8) BIT 109 drivers/spi/spi-nxp-fspi.c #define FSPI_INTEN_DATALRNFL BIT(7) BIT 110 drivers/spi/spi-nxp-fspi.c #define FSPI_INTEN_IPTXWE BIT(6) BIT 111 drivers/spi/spi-nxp-fspi.c #define FSPI_INTEN_IPRXWA BIT(5) BIT 112 drivers/spi/spi-nxp-fspi.c #define FSPI_INTEN_AHBCMDERR BIT(4) BIT 113 drivers/spi/spi-nxp-fspi.c #define FSPI_INTEN_IPCMDERR BIT(3) BIT 114 drivers/spi/spi-nxp-fspi.c #define FSPI_INTEN_AHBCMDGE BIT(2) BIT 115 drivers/spi/spi-nxp-fspi.c #define FSPI_INTEN_IPCMDGE BIT(1) BIT 116 drivers/spi/spi-nxp-fspi.c #define FSPI_INTEN_IPCMDDONE BIT(0) BIT 119 drivers/spi/spi-nxp-fspi.c #define FSPI_INTR_SCLKSBWR BIT(9) BIT 120 drivers/spi/spi-nxp-fspi.c #define FSPI_INTR_SCLKSBRD BIT(8) BIT 121 drivers/spi/spi-nxp-fspi.c #define FSPI_INTR_DATALRNFL BIT(7) BIT 122 drivers/spi/spi-nxp-fspi.c #define FSPI_INTR_IPTXWE BIT(6) BIT 123 drivers/spi/spi-nxp-fspi.c #define FSPI_INTR_IPRXWA BIT(5) BIT 124 drivers/spi/spi-nxp-fspi.c #define FSPI_INTR_AHBCMDERR BIT(4) BIT 125 drivers/spi/spi-nxp-fspi.c #define FSPI_INTR_IPCMDERR BIT(3) BIT 126 drivers/spi/spi-nxp-fspi.c #define FSPI_INTR_AHBCMDGE BIT(2) BIT 127 drivers/spi/spi-nxp-fspi.c #define FSPI_INTR_IPCMDGE BIT(1) BIT 128 drivers/spi/spi-nxp-fspi.c #define FSPI_INTR_IPCMDDONE BIT(0) BIT 147 drivers/spi/spi-nxp-fspi.c #define FSPI_AHBRXBUF0CR7_PREF BIT(31) BIT 171 drivers/spi/spi-nxp-fspi.c #define FSPI_FLSHXCR1_WA BIT(10) BIT 179 drivers/spi/spi-nxp-fspi.c #define FSPI_FLSHXCR2_CLRINSP BIT(24) BIT 180 drivers/spi/spi-nxp-fspi.c #define FSPI_FLSHXCR2_AWRWAIT BIT(16) BIT 189 drivers/spi/spi-nxp-fspi.c #define FSPI_IPCR1_IPAREN BIT(31) BIT 195 drivers/spi/spi-nxp-fspi.c #define FSPI_IPCMD_TRG BIT(0) BIT 200 drivers/spi/spi-nxp-fspi.c #define FSPI_IPRXFCR_CLR BIT(0) BIT 201 drivers/spi/spi-nxp-fspi.c #define FSPI_IPRXFCR_DMA_EN BIT(1) BIT 205 drivers/spi/spi-nxp-fspi.c #define FSPI_IPTXFCR_CLR BIT(0) BIT 206 drivers/spi/spi-nxp-fspi.c #define FSPI_IPTXFCR_DMA_EN BIT(1) BIT 210 drivers/spi/spi-nxp-fspi.c #define FSPI_DLLACR_OVRDEN BIT(8) BIT 213 drivers/spi/spi-nxp-fspi.c #define FSPI_DLLBCR_OVRDEN BIT(8) BIT 219 drivers/spi/spi-nxp-fspi.c #define FSPI_STS0_ARB_IDLE BIT(1) BIT 220 drivers/spi/spi-nxp-fspi.c #define FSPI_STS0_SEQ_IDLE BIT(0) BIT 231 drivers/spi/spi-nxp-fspi.c #define FSPI_AHBSPNST_ACTIVE BIT(0) BIT 57 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) BIT 59 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) BIT 60 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) BIT 61 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) BIT 63 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_PHA BIT(0) BIT 64 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_POL BIT(1) BIT 66 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) BIT 68 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) BIT 69 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) BIT 71 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) BIT 72 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) BIT 73 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) BIT 74 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) BIT 75 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_IS BIT(18) BIT 76 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) BIT 77 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) BIT 78 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_FFET BIT(27) BIT 79 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_FFER BIT(28) BIT 80 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) BIT 82 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) BIT 83 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) BIT 84 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) BIT 85 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) BIT 87 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_CHCTRL_EN BIT(0) BIT 90 drivers/spi/spi-omap2-mcspi.c #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) BIT 41 drivers/spi/spi-orion.c #define ORION_SPI_IF_RXLSBF BIT(14) BIT 42 drivers/spi/spi-orion.c #define ORION_SPI_IF_TXLSBF BIT(13) BIT 51 drivers/spi/spi-pic32-sqi.c #define PESQI_CPHA BIT(3) BIT 52 drivers/spi/spi-pic32-sqi.c #define PESQI_CPOL BIT(4) BIT 53 drivers/spi/spi-pic32-sqi.c #define PESQI_LSBF BIT(5) BIT 54 drivers/spi/spi-pic32-sqi.c #define PESQI_RXLATCH BIT(7) BIT 55 drivers/spi/spi-pic32-sqi.c #define PESQI_SERMODE BIT(8) BIT 56 drivers/spi/spi-pic32-sqi.c #define PESQI_WP_EN BIT(9) BIT 57 drivers/spi/spi-pic32-sqi.c #define PESQI_HOLD_EN BIT(10) BIT 58 drivers/spi/spi-pic32-sqi.c #define PESQI_BURST_EN BIT(12) BIT 59 drivers/spi/spi-pic32-sqi.c #define PESQI_CS_CTRL_HW BIT(15) BIT 60 drivers/spi/spi-pic32-sqi.c #define PESQI_SOFT_RESET BIT(16) BIT 66 drivers/spi/spi-pic32-sqi.c #define PESQI_EN BIT(23) BIT 69 drivers/spi/spi-pic32-sqi.c #define PESQI_CLK_EN BIT(0) BIT 70 drivers/spi/spi-pic32-sqi.c #define PESQI_CLK_STABLE BIT(1) BIT 81 drivers/spi/spi-pic32-sqi.c #define PESQI_TXEMPTY BIT(0) BIT 82 drivers/spi/spi-pic32-sqi.c #define PESQI_TXFULL BIT(1) BIT 83 drivers/spi/spi-pic32-sqi.c #define PESQI_TXTHR BIT(2) BIT 84 drivers/spi/spi-pic32-sqi.c #define PESQI_RXEMPTY BIT(3) BIT 85 drivers/spi/spi-pic32-sqi.c #define PESQI_RXFULL BIT(4) BIT 86 drivers/spi/spi-pic32-sqi.c #define PESQI_RXTHR BIT(5) BIT 87 drivers/spi/spi-pic32-sqi.c #define PESQI_BDDONE BIT(9) /* BD processing complete */ BIT 88 drivers/spi/spi-pic32-sqi.c #define PESQI_PKTCOMP BIT(10) /* packet processing complete */ BIT 89 drivers/spi/spi-pic32-sqi.c #define PESQI_DMAERR BIT(11) /* error */ BIT 92 drivers/spi/spi-pic32-sqi.c #define PESQI_DMA_EN BIT(0) /* enable DMA engine */ BIT 93 drivers/spi/spi-pic32-sqi.c #define PESQI_POLL_EN BIT(1) /* enable polling */ BIT 94 drivers/spi/spi-pic32-sqi.c #define PESQI_BDP_START BIT(2) /* start BD processor */ BIT 106 drivers/spi/spi-pic32-sqi.c #define BD_CBD_INT_EN BIT(16) /* Current BD is processed */ BIT 107 drivers/spi/spi-pic32-sqi.c #define BD_PKT_INT_EN BIT(17) /* All BDs of PKT processed */ BIT 108 drivers/spi/spi-pic32-sqi.c #define BD_LIFM BIT(18) /* last data of pkt */ BIT 109 drivers/spi/spi-pic32-sqi.c #define BD_LAST BIT(19) /* end of list */ BIT 110 drivers/spi/spi-pic32-sqi.c #define BD_DATA_RECV BIT(20) /* receive data */ BIT 111 drivers/spi/spi-pic32-sqi.c #define BD_DDR BIT(21) /* DDR mode */ BIT 112 drivers/spi/spi-pic32-sqi.c #define BD_DUAL BIT(22) /* Dual SPI */ BIT 113 drivers/spi/spi-pic32-sqi.c #define BD_QUAD BIT(23) /* Quad SPI */ BIT 114 drivers/spi/spi-pic32-sqi.c #define BD_LSBF BIT(25) /* LSB First */ BIT 115 drivers/spi/spi-pic32-sqi.c #define BD_STAT_CHECK BIT(27) /* Status poll */ BIT 117 drivers/spi/spi-pic32-sqi.c #define BD_CS_DEASSERT BIT(30) /* de-assert CS after current BD */ BIT 118 drivers/spi/spi-pic32-sqi.c #define BD_EN BIT(31) /* BD owned by H/W */ BIT 58 drivers/spi/spi-pic32.c #define CTRL_MSTEN BIT(5) /* enable master mode */ BIT 59 drivers/spi/spi-pic32.c #define CTRL_CKP BIT(6) /* active low */ BIT 60 drivers/spi/spi-pic32.c #define CTRL_CKE BIT(8) /* Tx on falling edge */ BIT 61 drivers/spi/spi-pic32.c #define CTRL_SMP BIT(9) /* Rx at middle or end of tx */ BIT 67 drivers/spi/spi-pic32.c #define CTRL_SIDL BIT(13) /* sleep when idle */ BIT 68 drivers/spi/spi-pic32.c #define CTRL_ON BIT(15) /* enable macro */ BIT 69 drivers/spi/spi-pic32.c #define CTRL_ENHBUF BIT(16) /* enable enhanced buffering */ BIT 70 drivers/spi/spi-pic32.c #define CTRL_MCLKSEL BIT(23) /* select clock source */ BIT 71 drivers/spi/spi-pic32.c #define CTRL_MSSEN BIT(28) /* macro driven /SS */ BIT 72 drivers/spi/spi-pic32.c #define CTRL_FRMEN BIT(31) /* enable framing mode */ BIT 75 drivers/spi/spi-pic32.c #define STAT_RF_EMPTY BIT(5) /* RX Fifo empty */ BIT 76 drivers/spi/spi-pic32.c #define STAT_RX_OV BIT(6) /* err, s/w needs to clear */ BIT 77 drivers/spi/spi-pic32.c #define STAT_TX_UR BIT(8) /* UR in Framed SPI modes */ BIT 78 drivers/spi/spi-pic32.c #define STAT_FRM_ERR BIT(12) /* Multiple Frame Sync pulse */ BIT 88 drivers/spi/spi-pic32.c #define CTRL2_TX_UR_EN BIT(10) /* Enable int on Tx under-run */ BIT 89 drivers/spi/spi-pic32.c #define CTRL2_RX_OV_EN BIT(11) /* Enable int on Rx over-run */ BIT 90 drivers/spi/spi-pic32.c #define CTRL2_FRM_ERR_EN BIT(12) /* Enable frame err int */ BIT 457 drivers/spi/spi-pl022.c tmp &= ~BIT(pl022->cur_cs); BIT 459 drivers/spi/spi-pl022.c tmp |= BIT(pl022->cur_cs); BIT 65 drivers/spi/spi-pxa2xx.c #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) BIT 66 drivers/spi/spi-pxa2xx.c #define LPSS_CS_CONTROL_SW_MODE BIT(0) BIT 67 drivers/spi/spi-pxa2xx.c #define LPSS_CS_CONTROL_CS_HIGH BIT(1) BIT 19 drivers/spi/spi-qcom-qspi.c #define FULL_CYCLE_MODE BIT(3) BIT 20 drivers/spi/spi-qcom-qspi.c #define FB_CLK_EN BIT(4) BIT 21 drivers/spi/spi-qcom-qspi.c #define PIN_HOLDN BIT(6) BIT 22 drivers/spi/spi-qcom-qspi.c #define PIN_WPN BIT(7) BIT 23 drivers/spi/spi-qcom-qspi.c #define DMA_ENABLE BIT(8) BIT 24 drivers/spi/spi-qcom-qspi.c #define BIG_ENDIAN_MODE BIT(9) BIT 27 drivers/spi/spi-qcom-qspi.c #define CHIP_SELECT_NUM BIT(12) BIT 28 drivers/spi/spi-qcom-qspi.c #define SBL_EN BIT(13) BIT 49 drivers/spi/spi-qcom-qspi.c #define HSHARED BIT(11) BIT 50 drivers/spi/spi-qcom-qspi.c #define HINNERSHARED BIT(12) BIT 54 drivers/spi/spi-qcom-qspi.c #define RESP_FIFO_UNDERRUN BIT(0) BIT 55 drivers/spi/spi-qcom-qspi.c #define RESP_FIFO_NOT_EMPTY BIT(1) BIT 56 drivers/spi/spi-qcom-qspi.c #define RESP_FIFO_RDY BIT(2) BIT 57 drivers/spi/spi-qcom-qspi.c #define HRESP_FROM_NOC_ERR BIT(3) BIT 58 drivers/spi/spi-qcom-qspi.c #define WR_FIFO_EMPTY BIT(9) BIT 59 drivers/spi/spi-qcom-qspi.c #define WR_FIFO_FULL BIT(10) BIT 60 drivers/spi/spi-qcom-qspi.c #define WR_FIFO_OVERRUN BIT(11) BIT 61 drivers/spi/spi-qcom-qspi.c #define TRANSACTION_DONE BIT(16) BIT 72 drivers/spi/spi-qcom-qspi.c #define TRANSFER_DIRECTION BIT(0) BIT 75 drivers/spi/spi-qcom-qspi.c #define TRANSFER_FRAGMENT BIT(8) BIT 94 drivers/spi/spi-qcom-qspi.c #define CONTINUOUS_MODE BIT(0) BIT 97 drivers/spi/spi-qcom-qspi.c #define FIFO_EMPTY BIT(11) BIT 100 drivers/spi/spi-qcom-qspi.c #define RDY_64BYTE BIT(3) BIT 101 drivers/spi/spi-qcom-qspi.c #define RDY_32BYTE BIT(2) BIT 102 drivers/spi/spi-qcom-qspi.c #define RDY_16BYTE BIT(1) BIT 103 drivers/spi/spi-qcom-qspi.c #define FIFO_RDY BIT(0) BIT 106 drivers/spi/spi-qcom-qspi.c #define RESET_FIFO BIT(0) BIT 44 drivers/spi/spi-qup.c #define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13) BIT 45 drivers/spi/spi-qup.c #define QUP_CONFIG_NO_INPUT BIT(7) BIT 46 drivers/spi/spi-qup.c #define QUP_CONFIG_NO_OUTPUT BIT(6) BIT 50 drivers/spi/spi-qup.c #define QUP_STATE_VALID BIT(2) BIT 60 drivers/spi/spi-qup.c #define QUP_IO_M_PACK_EN BIT(15) BIT 61 drivers/spi/spi-qup.c #define QUP_IO_M_UNPACK_EN BIT(14) BIT 78 drivers/spi/spi-qup.c #define QUP_OP_IN_BLOCK_READ_REQ BIT(13) BIT 79 drivers/spi/spi-qup.c #define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12) BIT 80 drivers/spi/spi-qup.c #define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11) BIT 81 drivers/spi/spi-qup.c #define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10) BIT 82 drivers/spi/spi-qup.c #define QUP_OP_IN_SERVICE_FLAG BIT(9) BIT 83 drivers/spi/spi-qup.c #define QUP_OP_OUT_SERVICE_FLAG BIT(8) BIT 84 drivers/spi/spi-qup.c #define QUP_OP_IN_FIFO_FULL BIT(7) BIT 85 drivers/spi/spi-qup.c #define QUP_OP_OUT_FIFO_FULL BIT(6) BIT 86 drivers/spi/spi-qup.c #define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5) BIT 87 drivers/spi/spi-qup.c #define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4) BIT 90 drivers/spi/spi-qup.c #define QUP_ERROR_OUTPUT_OVER_RUN BIT(5) BIT 91 drivers/spi/spi-qup.c #define QUP_ERROR_INPUT_UNDER_RUN BIT(4) BIT 92 drivers/spi/spi-qup.c #define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3) BIT 93 drivers/spi/spi-qup.c #define QUP_ERROR_INPUT_OVER_RUN BIT(2) BIT 96 drivers/spi/spi-qup.c #define SPI_CONFIG_HS_MODE BIT(10) BIT 97 drivers/spi/spi-qup.c #define SPI_CONFIG_INPUT_FIRST BIT(9) BIT 98 drivers/spi/spi-qup.c #define SPI_CONFIG_LOOPBACK BIT(8) BIT 101 drivers/spi/spi-qup.c #define SPI_IO_C_FORCE_CS BIT(11) BIT 102 drivers/spi/spi-qup.c #define SPI_IO_C_CLK_IDLE_HIGH BIT(10) BIT 103 drivers/spi/spi-qup.c #define SPI_IO_C_MX_CS_MODE BIT(8) BIT 104 drivers/spi/spi-qup.c #define SPI_IO_C_CS_N_POLARITY_0 BIT(4) BIT 107 drivers/spi/spi-qup.c #define SPI_IO_C_TRISTATE_CS BIT(1) BIT 108 drivers/spi/spi-qup.c #define SPI_IO_C_NO_TRI_STATE BIT(0) BIT 111 drivers/spi/spi-qup.c #define SPI_ERROR_CLK_OVER_RUN BIT(1) BIT 112 drivers/spi/spi-qup.c #define SPI_ERROR_CLK_UNDER_RUN BIT(0) BIT 40 drivers/spi/spi-rb4xx.c if (value & BIT(0)) BIT 62 drivers/spi/spi-rb4xx.c if (value & BIT(1)) BIT 64 drivers/spi/spi-rb4xx.c if (value & BIT(0)) BIT 235 drivers/spi/spi-rockchip.c BIT(spi->chip_select)); BIT 238 drivers/spi/spi-rockchip.c BIT(spi->chip_select)); BIT 25 drivers/spi/spi-sc18is602.c #define SC18IS602_MODE_CPHA BIT(2) BIT 26 drivers/spi/spi-sc18is602.c #define SC18IS602_MODE_CPOL BIT(3) BIT 27 drivers/spi/spi-sc18is602.c #define SC18IS602_MODE_LSB_FIRST BIT(5) BIT 86 drivers/spi/spi-sh-msiof.c #define MDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */ BIT 96 drivers/spi/spi-sh-msiof.c #define MDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */ BIT 98 drivers/spi/spi-sh-msiof.c #define TMDR1_PCON BIT(30) /* Transfer Signal Connection */ BIT 105 drivers/spi/spi-sh-msiof.c #define MDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */ BIT 120 drivers/spi/spi-sh-msiof.c #define CTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */ BIT 123 drivers/spi/spi-sh-msiof.c #define CTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */ BIT 131 drivers/spi/spi-sh-msiof.c #define CTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */ BIT 132 drivers/spi/spi-sh-msiof.c #define CTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */ BIT 133 drivers/spi/spi-sh-msiof.c #define CTR_TXE BIT(9) /* Transmit Enable */ BIT 134 drivers/spi/spi-sh-msiof.c #define CTR_RXE BIT(8) /* Receive Enable */ BIT 135 drivers/spi/spi-sh-msiof.c #define CTR_TXRST BIT(1) /* Transmit Reset */ BIT 136 drivers/spi/spi-sh-msiof.c #define CTR_RXRST BIT(0) /* Receive Reset */ BIT 165 drivers/spi/spi-sh-msiof.c #define STR_TFEMP BIT(29) /* Transmit FIFO Empty */ BIT 166 drivers/spi/spi-sh-msiof.c #define STR_TDREQ BIT(28) /* Transmit Data Transfer Request */ BIT 167 drivers/spi/spi-sh-msiof.c #define STR_TEOF BIT(23) /* Frame Transmission End */ BIT 168 drivers/spi/spi-sh-msiof.c #define STR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */ BIT 169 drivers/spi/spi-sh-msiof.c #define STR_TFOVF BIT(20) /* Transmit FIFO Overflow */ BIT 170 drivers/spi/spi-sh-msiof.c #define STR_TFUDF BIT(19) /* Transmit FIFO Underflow */ BIT 171 drivers/spi/spi-sh-msiof.c #define STR_RFFUL BIT(13) /* Receive FIFO Full */ BIT 172 drivers/spi/spi-sh-msiof.c #define STR_RDREQ BIT(12) /* Receive Data Transfer Request */ BIT 173 drivers/spi/spi-sh-msiof.c #define STR_REOF BIT(7) /* Frame Reception End */ BIT 174 drivers/spi/spi-sh-msiof.c #define STR_RFSERR BIT(5) /* Receive Frame Synchronization Error */ BIT 175 drivers/spi/spi-sh-msiof.c #define STR_RFUDF BIT(4) /* Receive FIFO Underflow */ BIT 176 drivers/spi/spi-sh-msiof.c #define STR_RFOVF BIT(3) /* Receive FIFO Overflow */ BIT 179 drivers/spi/spi-sh-msiof.c #define IER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */ BIT 180 drivers/spi/spi-sh-msiof.c #define IER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */ BIT 181 drivers/spi/spi-sh-msiof.c #define IER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */ BIT 182 drivers/spi/spi-sh-msiof.c #define IER_TEOFE BIT(23) /* Frame Transmission End Enable */ BIT 183 drivers/spi/spi-sh-msiof.c #define IER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */ BIT 184 drivers/spi/spi-sh-msiof.c #define IER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */ BIT 185 drivers/spi/spi-sh-msiof.c #define IER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */ BIT 186 drivers/spi/spi-sh-msiof.c #define IER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */ BIT 187 drivers/spi/spi-sh-msiof.c #define IER_RFFULE BIT(13) /* Receive FIFO Full Enable */ BIT 188 drivers/spi/spi-sh-msiof.c #define IER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */ BIT 189 drivers/spi/spi-sh-msiof.c #define IER_REOFE BIT(7) /* Frame Reception End Enable */ BIT 190 drivers/spi/spi-sh-msiof.c #define IER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */ BIT 191 drivers/spi/spi-sh-msiof.c #define IER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */ BIT 192 drivers/spi/spi-sh-msiof.c #define IER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */ BIT 567 drivers/spi/spi-sh-msiof.c clr |= BIT(MDR1_SYNCAC_SHIFT); BIT 569 drivers/spi/spi-sh-msiof.c set |= BIT(MDR1_SYNCAC_SHIFT); BIT 1157 drivers/spi/spi-sh-msiof.c used_ss_mask |= BIT(i); BIT 47 drivers/spi/spi-sifive.c #define SIFIVE_SPI_SCKMODE_PHA BIT(0) BIT 48 drivers/spi/spi-sifive.c #define SIFIVE_SPI_SCKMODE_POL BIT(1) BIT 74 drivers/spi/spi-sifive.c #define SIFIVE_SPI_FMT_ENDIAN BIT(2) BIT 75 drivers/spi/spi-sifive.c #define SIFIVE_SPI_FMT_DIR BIT(3) BIT 81 drivers/spi/spi-sifive.c #define SIFIVE_SPI_TXDATA_FULL BIT(31) BIT 85 drivers/spi/spi-sifive.c #define SIFIVE_SPI_RXDATA_EMPTY BIT(31) BIT 88 drivers/spi/spi-sifive.c #define SIFIVE_SPI_IP_TXWM BIT(0) BIT 89 drivers/spi/spi-sifive.c #define SIFIVE_SPI_IP_RXWM BIT(1) BIT 138 drivers/spi/spi-sifive.c spi->cs_inactive &= ~BIT(device->chip_select); BIT 140 drivers/spi/spi-sifive.c spi->cs_inactive |= BIT(device->chip_select); BIT 29 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_SLV_MODE BIT(16) BIT 30 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_CMD_MODE BIT(17) BIT 31 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_CS_IO_OUT BIT(18) BIT 32 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_CS_IO_MODE BIT(19) BIT 33 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20) BIT 34 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_CS_IDLE_STAT BIT(21) BIT 35 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TRAN_MSB BIT(22) BIT 36 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_DRV_POS_EDGE BIT(23) BIT 37 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_CS_HOLD_TIME BIT(24) BIT 38 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25) BIT 44 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30) BIT 45 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_MUL_DAT_MODE BIT(31) BIT 48 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0) BIT 49 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1) BIT 50 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2) BIT 51 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3) BIT 52 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4) BIT 53 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5) BIT 54 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6) BIT 55 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7) BIT 56 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8) BIT 57 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9) BIT 58 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_FRM_END_INT_EN BIT(10) BIT 61 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RX_DONE BIT(0) BIT 62 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TX_DONE BIT(1) BIT 63 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RX_OFLOW BIT(2) BIT 64 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TX_UFLOW BIT(3) BIT 65 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RX_IO_DMA BIT(4) BIT 66 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RX_FIFO_FULL BIT(6) BIT 67 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7) BIT 68 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8) BIT 69 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9) BIT 70 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_FRM_END BIT(10) BIT 73 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RX_EN BIT(0) BIT 74 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_TX_EN BIT(1) BIT 75 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_CMD_TX_EN BIT(2) BIT 77 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_IO_MODE_SEL BIT(0) BIT 78 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2) BIT 81 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_FIFO_RESET BIT(0) BIT 82 drivers/spi/spi-sirf.c #define SIRFSOC_SPI_FIFO_START BIT(1) BIT 89 drivers/spi/spi-sirf.c #define SIRFSOC_USP_SYNC_MODE BIT(0) BIT 90 drivers/spi/spi-sirf.c #define SIRFSOC_USP_SLV_MODE BIT(1) BIT 91 drivers/spi/spi-sirf.c #define SIRFSOC_USP_LSB BIT(4) BIT 92 drivers/spi/spi-sirf.c #define SIRFSOC_USP_EN BIT(5) BIT 93 drivers/spi/spi-sirf.c #define SIRFSOC_USP_RXD_FALLING_EDGE BIT(6) BIT 94 drivers/spi/spi-sirf.c #define SIRFSOC_USP_TXD_FALLING_EDGE BIT(7) BIT 95 drivers/spi/spi-sirf.c #define SIRFSOC_USP_CS_HIGH_VALID BIT(9) BIT 96 drivers/spi/spi-sirf.c #define SIRFSOC_USP_SCLK_IDLE_STAT BIT(11) BIT 97 drivers/spi/spi-sirf.c #define SIRFSOC_USP_TFS_IO_MODE BIT(14) BIT 98 drivers/spi/spi-sirf.c #define SIRFSOC_USP_TFS_IO_INPUT BIT(19) BIT 130 drivers/spi/spi-sirf.c #define SIRFSOC_USP_CS_HIGH_VALUE BIT(1) BIT 27 drivers/spi/spi-slave-mt27xx.c #define DMA_DONE_EN BIT(7) BIT 28 drivers/spi/spi-slave-mt27xx.c #define DATA_DONE_EN BIT(2) BIT 29 drivers/spi/spi-slave-mt27xx.c #define RSTA_DONE_EN BIT(1) BIT 30 drivers/spi/spi-slave-mt27xx.c #define CMD_INVALID_EN BIT(0) BIT 33 drivers/spi/spi-slave-mt27xx.c #define DMA_DONE_ST BIT(7) BIT 34 drivers/spi/spi-slave-mt27xx.c #define DATA_DONE_ST BIT(2) BIT 35 drivers/spi/spi-slave-mt27xx.c #define RSTA_DONE_ST BIT(1) BIT 36 drivers/spi/spi-slave-mt27xx.c #define CMD_INVALID_ST BIT(0) BIT 39 drivers/spi/spi-slave-mt27xx.c #define DMA_DONE_MASK BIT(7) BIT 40 drivers/spi/spi-slave-mt27xx.c #define DATA_DONE_MASK BIT(2) BIT 41 drivers/spi/spi-slave-mt27xx.c #define RSTA_DONE_MASK BIT(1) BIT 42 drivers/spi/spi-slave-mt27xx.c #define CMD_INVALID_MASK BIT(0) BIT 45 drivers/spi/spi-slave-mt27xx.c #define SPIS_TX_ENDIAN BIT(7) BIT 46 drivers/spi/spi-slave-mt27xx.c #define SPIS_RX_ENDIAN BIT(6) BIT 47 drivers/spi/spi-slave-mt27xx.c #define SPIS_TXMSBF BIT(5) BIT 48 drivers/spi/spi-slave-mt27xx.c #define SPIS_RXMSBF BIT(4) BIT 49 drivers/spi/spi-slave-mt27xx.c #define SPIS_CPHA BIT(3) BIT 50 drivers/spi/spi-slave-mt27xx.c #define SPIS_CPOL BIT(2) BIT 51 drivers/spi/spi-slave-mt27xx.c #define SPIS_TX_EN BIT(1) BIT 52 drivers/spi/spi-slave-mt27xx.c #define SPIS_RX_EN BIT(0) BIT 55 drivers/spi/spi-slave-mt27xx.c #define TX_DMA_TRIG_EN BIT(31) BIT 56 drivers/spi/spi-slave-mt27xx.c #define TX_DMA_EN BIT(30) BIT 57 drivers/spi/spi-slave-mt27xx.c #define RX_DMA_EN BIT(29) BIT 61 drivers/spi/spi-slave-mt27xx.c #define SPIS_DMA_ADDR_EN BIT(1) BIT 62 drivers/spi/spi-slave-mt27xx.c #define SPIS_SOFT_RST BIT(0) BIT 41 drivers/spi/spi-sprd-adi.c #define BIT_CLK_ALL_ON BIT(30) BIT 44 drivers/spi/spi-sprd-adi.c #define BIT_RD_CMD_BUSY BIT(31) BIT 50 drivers/spi/spi-sprd-adi.c #define BIT_FIFO_FULL BIT(11) BIT 51 drivers/spi/spi-sprd-adi.c #define BIT_FIFO_EMPTY BIT(10) BIT 79 drivers/spi/spi-sprd-adi.c #define BIT_WDG_RUN BIT(1) BIT 80 drivers/spi/spi-sprd-adi.c #define BIT_WDG_RST BIT(3) BIT 86 drivers/spi/spi-sprd-adi.c #define BIT_WDG_EN BIT(2) BIT 443 drivers/spi/spi-sprd-adi.c value |= BIT(chn_id); BIT 447 drivers/spi/spi-sprd-adi.c value |= BIT(chn_id - 32); BIT 52 drivers/spi/spi-sprd.c #define SPRD_SPI_SCK_REV BIT(13) BIT 53 drivers/spi/spi-sprd.c #define SPRD_SPI_NG_TX BIT(1) BIT 54 drivers/spi/spi-sprd.c #define SPRD_SPI_NG_RX BIT(0) BIT 57 drivers/spi/spi-sprd.c #define SPRD_SPI_CS0_VALID BIT(8) BIT 60 drivers/spi/spi-sprd.c #define SPRD_SPI_TX_END_INT_EN BIT(8) BIT 61 drivers/spi/spi-sprd.c #define SPRD_SPI_RX_END_INT_EN BIT(9) BIT 64 drivers/spi/spi-sprd.c #define SPRD_SPI_TX_END_RAW BIT(8) BIT 65 drivers/spi/spi-sprd.c #define SPRD_SPI_RX_END_RAW BIT(9) BIT 68 drivers/spi/spi-sprd.c #define SPRD_SPI_TX_END_CLR BIT(8) BIT 69 drivers/spi/spi-sprd.c #define SPRD_SPI_RX_END_CLR BIT(9) BIT 72 drivers/spi/spi-sprd.c #define SPRD_SPI_MASK_RX_END BIT(9) BIT 73 drivers/spi/spi-sprd.c #define SPRD_SPI_MASK_TX_END BIT(8) BIT 76 drivers/spi/spi-sprd.c #define SPRD_SPI_TX_BUSY BIT(8) BIT 79 drivers/spi/spi-sprd.c #define SPRD_SPI_RX_MODE BIT(12) BIT 80 drivers/spi/spi-sprd.c #define SPRD_SPI_TX_MODE BIT(13) BIT 84 drivers/spi/spi-sprd.c #define SPRD_SPI_DMA_EN BIT(6) BIT 87 drivers/spi/spi-sprd.c #define SPRD_SPI_START_RX BIT(9) BIT 91 drivers/spi/spi-sprd.c #define SPRD_SPI_RX_END_INT_CLR BIT(9) BIT 92 drivers/spi/spi-sprd.c #define SPRD_SPI_TX_END_INT_CLR BIT(8) BIT 95 drivers/spi/spi-sprd.c #define SPRD_SPI_RX_END_IRQ BIT(9) BIT 96 drivers/spi/spi-sprd.c #define SPRD_SPI_TX_END_IRQ BIT(8) BIT 99 drivers/spi/spi-sprd.c #define SPRD_SPI_SW_RX_REQ BIT(0) BIT 100 drivers/spi/spi-sprd.c #define SPRD_SPI_SW_TX_REQ BIT(1) BIT 103 drivers/spi/spi-sprd.c #define SPRD_SPI_DATA_LINE2_EN BIT(15) BIT 38 drivers/spi/spi-st-ssc4.c #define SSC_CTL_HB BIT(4) BIT 39 drivers/spi/spi-st-ssc4.c #define SSC_CTL_PH BIT(5) BIT 40 drivers/spi/spi-st-ssc4.c #define SSC_CTL_PO BIT(6) BIT 41 drivers/spi/spi-st-ssc4.c #define SSC_CTL_SR BIT(7) BIT 42 drivers/spi/spi-st-ssc4.c #define SSC_CTL_MS BIT(8) BIT 43 drivers/spi/spi-st-ssc4.c #define SSC_CTL_EN BIT(9) BIT 44 drivers/spi/spi-st-ssc4.c #define SSC_CTL_LPB BIT(10) BIT 45 drivers/spi/spi-st-ssc4.c #define SSC_CTL_EN_TX_FIFO BIT(11) BIT 46 drivers/spi/spi-st-ssc4.c #define SSC_CTL_EN_RX_FIFO BIT(12) BIT 47 drivers/spi/spi-st-ssc4.c #define SSC_CTL_EN_CLST_RX BIT(13) BIT 50 drivers/spi/spi-st-ssc4.c #define SSC_IEN_TEEN BIT(2) BIT 213 drivers/spi/spi-st-ssc4.c if (sscbrg < 0x07 || sscbrg > BIT(16)) { BIT 221 drivers/spi/spi-st-ssc4.c if (sscbrg == BIT(16)) /* 16-bit counter wraps */ BIT 25 drivers/spi/spi-stm32-qspi.c #define CR_EN BIT(0) BIT 26 drivers/spi/spi-stm32-qspi.c #define CR_ABORT BIT(1) BIT 27 drivers/spi/spi-stm32-qspi.c #define CR_DMAEN BIT(2) BIT 28 drivers/spi/spi-stm32-qspi.c #define CR_TCEN BIT(3) BIT 29 drivers/spi/spi-stm32-qspi.c #define CR_SSHIFT BIT(4) BIT 30 drivers/spi/spi-stm32-qspi.c #define CR_DFM BIT(6) BIT 31 drivers/spi/spi-stm32-qspi.c #define CR_FSEL BIT(7) BIT 33 drivers/spi/spi-stm32-qspi.c #define CR_TEIE BIT(16) BIT 34 drivers/spi/spi-stm32-qspi.c #define CR_TCIE BIT(17) BIT 35 drivers/spi/spi-stm32-qspi.c #define CR_FTIE BIT(18) BIT 36 drivers/spi/spi-stm32-qspi.c #define CR_SMIE BIT(19) BIT 37 drivers/spi/spi-stm32-qspi.c #define CR_TOIE BIT(20) BIT 44 drivers/spi/spi-stm32-qspi.c #define SR_TEF BIT(0) BIT 45 drivers/spi/spi-stm32-qspi.c #define SR_TCF BIT(1) BIT 46 drivers/spi/spi-stm32-qspi.c #define SR_FTF BIT(2) BIT 47 drivers/spi/spi-stm32-qspi.c #define SR_SMF BIT(3) BIT 48 drivers/spi/spi-stm32-qspi.c #define SR_TOF BIT(4) BIT 49 drivers/spi/spi-stm32-qspi.c #define SR_BUSY BIT(5) BIT 53 drivers/spi/spi-stm32-qspi.c #define FCR_CTEF BIT(0) BIT 54 drivers/spi/spi-stm32-qspi.c #define FCR_CTCF BIT(1) BIT 31 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_CPHA BIT(0) BIT 32 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_CPOL BIT(1) BIT 33 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_MSTR BIT(2) BIT 36 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_SPE BIT(6) BIT 37 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_LSBFRST BIT(7) BIT 38 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_SSI BIT(8) BIT 39 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_SSM BIT(9) BIT 40 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_RXONLY BIT(10) BIT 41 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_DFF BIT(11) BIT 42 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_CRCNEXT BIT(12) BIT 43 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_CRCEN BIT(13) BIT 44 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_BIDIOE BIT(14) BIT 45 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_BIDIMODE BIT(15) BIT 50 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR2_RXDMAEN BIT(0) BIT 51 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR2_TXDMAEN BIT(1) BIT 52 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR2_SSOE BIT(2) BIT 53 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR2_FRF BIT(4) BIT 54 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR2_ERRIE BIT(5) BIT 55 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR2_RXNEIE BIT(6) BIT 56 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR2_TXEIE BIT(7) BIT 59 drivers/spi/spi-stm32.c #define STM32F4_SPI_SR_RXNE BIT(0) BIT 60 drivers/spi/spi-stm32.c #define STM32F4_SPI_SR_TXE BIT(1) BIT 61 drivers/spi/spi-stm32.c #define STM32F4_SPI_SR_CHSIDE BIT(2) BIT 62 drivers/spi/spi-stm32.c #define STM32F4_SPI_SR_UDR BIT(3) BIT 63 drivers/spi/spi-stm32.c #define STM32F4_SPI_SR_CRCERR BIT(4) BIT 64 drivers/spi/spi-stm32.c #define STM32F4_SPI_SR_MODF BIT(5) BIT 65 drivers/spi/spi-stm32.c #define STM32F4_SPI_SR_OVR BIT(6) BIT 66 drivers/spi/spi-stm32.c #define STM32F4_SPI_SR_BSY BIT(7) BIT 67 drivers/spi/spi-stm32.c #define STM32F4_SPI_SR_FRE BIT(8) BIT 70 drivers/spi/spi-stm32.c #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11) BIT 89 drivers/spi/spi-stm32.c #define STM32H7_SPI_CR1_SPE BIT(0) BIT 90 drivers/spi/spi-stm32.c #define STM32H7_SPI_CR1_MASRX BIT(8) BIT 91 drivers/spi/spi-stm32.c #define STM32H7_SPI_CR1_CSTART BIT(9) BIT 92 drivers/spi/spi-stm32.c #define STM32H7_SPI_CR1_CSUSP BIT(10) BIT 93 drivers/spi/spi-stm32.c #define STM32H7_SPI_CR1_HDDIR BIT(11) BIT 94 drivers/spi/spi-stm32.c #define STM32H7_SPI_CR1_SSI BIT(12) BIT 105 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG1_RXDMAEN BIT(14) BIT 106 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG1_TXDMAEN BIT(15) BIT 119 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG2_MASTER BIT(22) BIT 120 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG2_LSBFRST BIT(23) BIT 121 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG2_CPHA BIT(24) BIT 122 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG2_CPOL BIT(25) BIT 123 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG2_SSM BIT(26) BIT 124 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG2_AFCNTR BIT(31) BIT 127 drivers/spi/spi-stm32.c #define STM32H7_SPI_IER_RXPIE BIT(0) BIT 128 drivers/spi/spi-stm32.c #define STM32H7_SPI_IER_TXPIE BIT(1) BIT 129 drivers/spi/spi-stm32.c #define STM32H7_SPI_IER_DXPIE BIT(2) BIT 130 drivers/spi/spi-stm32.c #define STM32H7_SPI_IER_EOTIE BIT(3) BIT 131 drivers/spi/spi-stm32.c #define STM32H7_SPI_IER_TXTFIE BIT(4) BIT 132 drivers/spi/spi-stm32.c #define STM32H7_SPI_IER_OVRIE BIT(6) BIT 133 drivers/spi/spi-stm32.c #define STM32H7_SPI_IER_MODFIE BIT(9) BIT 137 drivers/spi/spi-stm32.c #define STM32H7_SPI_SR_RXP BIT(0) BIT 138 drivers/spi/spi-stm32.c #define STM32H7_SPI_SR_TXP BIT(1) BIT 139 drivers/spi/spi-stm32.c #define STM32H7_SPI_SR_EOT BIT(3) BIT 140 drivers/spi/spi-stm32.c #define STM32H7_SPI_SR_OVR BIT(6) BIT 141 drivers/spi/spi-stm32.c #define STM32H7_SPI_SR_MODF BIT(9) BIT 142 drivers/spi/spi-stm32.c #define STM32H7_SPI_SR_SUSP BIT(11) BIT 145 drivers/spi/spi-stm32.c #define STM32H7_SPI_SR_RXWNE BIT(15) BIT 151 drivers/spi/spi-stm32.c #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0) BIT 28 drivers/spi/spi-sun4i.c #define SUN4I_CTL_ENABLE BIT(0) BIT 29 drivers/spi/spi-sun4i.c #define SUN4I_CTL_MASTER BIT(1) BIT 30 drivers/spi/spi-sun4i.c #define SUN4I_CTL_CPHA BIT(2) BIT 31 drivers/spi/spi-sun4i.c #define SUN4I_CTL_CPOL BIT(3) BIT 32 drivers/spi/spi-sun4i.c #define SUN4I_CTL_CS_ACTIVE_LOW BIT(4) BIT 33 drivers/spi/spi-sun4i.c #define SUN4I_CTL_LMTF BIT(6) BIT 34 drivers/spi/spi-sun4i.c #define SUN4I_CTL_TF_RST BIT(8) BIT 35 drivers/spi/spi-sun4i.c #define SUN4I_CTL_RF_RST BIT(9) BIT 36 drivers/spi/spi-sun4i.c #define SUN4I_CTL_XCH BIT(10) BIT 39 drivers/spi/spi-sun4i.c #define SUN4I_CTL_DHB BIT(15) BIT 40 drivers/spi/spi-sun4i.c #define SUN4I_CTL_CS_MANUAL BIT(16) BIT 41 drivers/spi/spi-sun4i.c #define SUN4I_CTL_CS_LEVEL BIT(17) BIT 42 drivers/spi/spi-sun4i.c #define SUN4I_CTL_TP BIT(18) BIT 45 drivers/spi/spi-sun4i.c #define SUN4I_INT_CTL_RF_F34 BIT(4) BIT 46 drivers/spi/spi-sun4i.c #define SUN4I_INT_CTL_TF_E34 BIT(12) BIT 47 drivers/spi/spi-sun4i.c #define SUN4I_INT_CTL_TC BIT(16) BIT 60 drivers/spi/spi-sun4i.c #define SUN4I_CLK_CTL_DRS BIT(12) BIT 27 drivers/spi/spi-sun6i.c #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) BIT 28 drivers/spi/spi-sun6i.c #define SUN6I_GBL_CTL_MASTER BIT(1) BIT 29 drivers/spi/spi-sun6i.c #define SUN6I_GBL_CTL_TP BIT(7) BIT 30 drivers/spi/spi-sun6i.c #define SUN6I_GBL_CTL_RST BIT(31) BIT 33 drivers/spi/spi-sun6i.c #define SUN6I_TFR_CTL_CPHA BIT(0) BIT 34 drivers/spi/spi-sun6i.c #define SUN6I_TFR_CTL_CPOL BIT(1) BIT 35 drivers/spi/spi-sun6i.c #define SUN6I_TFR_CTL_SPOL BIT(2) BIT 38 drivers/spi/spi-sun6i.c #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) BIT 39 drivers/spi/spi-sun6i.c #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) BIT 40 drivers/spi/spi-sun6i.c #define SUN6I_TFR_CTL_DHB BIT(8) BIT 41 drivers/spi/spi-sun6i.c #define SUN6I_TFR_CTL_FBS BIT(12) BIT 42 drivers/spi/spi-sun6i.c #define SUN6I_TFR_CTL_XCH BIT(31) BIT 45 drivers/spi/spi-sun6i.c #define SUN6I_INT_CTL_RF_RDY BIT(0) BIT 46 drivers/spi/spi-sun6i.c #define SUN6I_INT_CTL_TF_ERQ BIT(4) BIT 47 drivers/spi/spi-sun6i.c #define SUN6I_INT_CTL_RF_OVF BIT(8) BIT 48 drivers/spi/spi-sun6i.c #define SUN6I_INT_CTL_TC BIT(12) BIT 55 drivers/spi/spi-sun6i.c #define SUN6I_FIFO_CTL_RF_RST BIT(15) BIT 58 drivers/spi/spi-sun6i.c #define SUN6I_FIFO_CTL_TF_RST BIT(31) BIT 71 drivers/spi/spi-sun6i.c #define SUN6I_CLK_CTL_DRS BIT(12) BIT 45 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_MCTRL_MEN BIT(0) BIT 46 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_MCTRL_COMMAND_SEQUENCE_EN BIT(1) BIT 47 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_MCTRL_CDSS BIT(3) BIT 48 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_MCTRL_MES BIT(4) BIT 49 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_MCTRL_SYNCON BIT(5) BIT 51 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_PCC_CPHA BIT(0) BIT 52 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_PCC_CPOL BIT(1) BIT 53 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_PCC_ACES BIT(2) BIT 54 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_PCC_RTM BIT(3) BIT 55 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_PCC_SSPOL BIT(4) BIT 56 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_PCC_SDIR BIT(7) BIT 57 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_PCC_SENDIAN BIT(8) BIT 58 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_PCC_SAFESYNC BIT(16) BIT 63 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_TXF_FIFO_FULL BIT(0) BIT 64 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_TXF_FIFO_EMPTY BIT(1) BIT 65 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_TXF_SLAVE_RELEASED BIT(6) BIT 67 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_TXE_FIFO_FULL BIT(0) BIT 68 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_TXE_FIFO_EMPTY BIT(1) BIT 69 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_TXE_SLAVE_RELEASED BIT(6) BIT 71 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_RXF_FIFO_MORE_THAN_THRESHOLD BIT(5) BIT 72 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_RXF_SLAVE_RELEASED BIT(6) BIT 74 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_RXE_FIFO_MORE_THAN_THRESHOLD BIT(5) BIT 75 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_RXE_SLAVE_RELEASED BIT(6) BIT 77 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_DMCFG_SSDC BIT(1) BIT 78 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_DMCFG_MSTARTEN BIT(2) BIT 80 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_DMSTART_START BIT(0) BIT 81 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_DMSTOP_STOP BIT(8) BIT 102 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_FIFOCFG_RX_FLUSH BIT(11) BIT 103 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_FIFOCFG_TX_FLUSH BIT(12) BIT 110 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_TRANSFER_MODE_TX BIT(1) BIT 111 drivers/spi/spi-synquacer.c #define SYNQUACER_HSSPI_TRANSFER_MODE_RX BIT(2) BIT 27 drivers/spi/spi-tegra20-sflash.c #define SPI_GO BIT(30) BIT 28 drivers/spi/spi-tegra20-sflash.c #define SPI_M_S BIT(28) BIT 44 drivers/spi/spi-tegra20-sflash.c #define SPI_CS_POL_INVERT BIT(16) BIT 45 drivers/spi/spi-tegra20-sflash.c #define SPI_TX_EN BIT(15) BIT 46 drivers/spi/spi-tegra20-sflash.c #define SPI_RX_EN BIT(14) BIT 47 drivers/spi/spi-tegra20-sflash.c #define SPI_CS_VAL_HIGH BIT(13) BIT 49 drivers/spi/spi-tegra20-sflash.c #define SPI_CS_SW BIT(12) BIT 52 drivers/spi/spi-tegra20-sflash.c #define SPI_CS3_EN BIT(8) BIT 53 drivers/spi/spi-tegra20-sflash.c #define SPI_CS2_EN BIT(7) BIT 54 drivers/spi/spi-tegra20-sflash.c #define SPI_CS1_EN BIT(6) BIT 55 drivers/spi/spi-tegra20-sflash.c #define SPI_CS0_EN BIT(5) BIT 64 drivers/spi/spi-tegra20-sflash.c #define SPI_BSY BIT(31) BIT 65 drivers/spi/spi-tegra20-sflash.c #define SPI_RDY BIT(30) BIT 66 drivers/spi/spi-tegra20-sflash.c #define SPI_TXF_FLUSH BIT(29) BIT 67 drivers/spi/spi-tegra20-sflash.c #define SPI_RXF_FLUSH BIT(28) BIT 68 drivers/spi/spi-tegra20-sflash.c #define SPI_RX_UNF BIT(27) BIT 69 drivers/spi/spi-tegra20-sflash.c #define SPI_TX_OVF BIT(26) BIT 70 drivers/spi/spi-tegra20-sflash.c #define SPI_RXF_EMPTY BIT(25) BIT 71 drivers/spi/spi-tegra20-sflash.c #define SPI_RXF_FULL BIT(24) BIT 72 drivers/spi/spi-tegra20-sflash.c #define SPI_TXF_EMPTY BIT(23) BIT 73 drivers/spi/spi-tegra20-sflash.c #define SPI_TXF_FULL BIT(22) BIT 81 drivers/spi/spi-tegra20-sflash.c #define SPI_DMA_EN BIT(31) BIT 82 drivers/spi/spi-tegra20-sflash.c #define SPI_IE_RXC BIT(27) BIT 83 drivers/spi/spi-tegra20-sflash.c #define SPI_IE_TXC BIT(26) BIT 84 drivers/spi/spi-tegra20-sflash.c #define SPI_PACKED BIT(20) BIT 19 drivers/spi/spi-test.h #define RX_START BIT(30) BIT 20 drivers/spi/spi-test.h #define TX_START BIT(31) BIT 25 drivers/spi/spi-test.h #define SPI_TEST_MAX_SIZE_HALF BIT(29) BIT 43 drivers/spi/spi-uniphier.c #define SSI_CTL_EN BIT(0) BIT 47 drivers/spi/spi-uniphier.c #define SSI_CKS_CKPHS BIT(14) BIT 48 drivers/spi/spi-uniphier.c #define SSI_CKS_CKINIT BIT(13) BIT 49 drivers/spi/spi-uniphier.c #define SSI_CKS_CKDLY BIT(12) BIT 60 drivers/spi/spi-uniphier.c #define SSI_FPS_FSPOL BIT(15) BIT 61 drivers/spi/spi-uniphier.c #define SSI_FPS_FSTRT BIT(14) BIT 64 drivers/spi/spi-uniphier.c #define SSI_SR_RNE BIT(0) BIT 67 drivers/spi/spi-uniphier.c #define SSI_IE_RCIE BIT(3) BIT 68 drivers/spi/spi-uniphier.c #define SSI_IE_RORIE BIT(0) BIT 71 drivers/spi/spi-uniphier.c #define SSI_IS_RXRS BIT(9) BIT 72 drivers/spi/spi-uniphier.c #define SSI_IS_RCID BIT(3) BIT 73 drivers/spi/spi-uniphier.c #define SSI_IS_RORID BIT(0) BIT 76 drivers/spi/spi-uniphier.c #define SSI_IC_TCIC BIT(4) BIT 77 drivers/spi/spi-uniphier.c #define SSI_IC_RCIC BIT(3) BIT 78 drivers/spi/spi-uniphier.c #define SSI_IC_RORIC BIT(0) BIT 81 drivers/spi/spi-uniphier.c #define SSI_FC_TXFFL BIT(12) BIT 83 drivers/spi/spi-uniphier.c #define SSI_FC_RXFFL BIT(4) BIT 17 drivers/spi/spi-xcomm.c #define SPI_XCOMM_SETTINGS_3WIRE BIT(6) BIT 18 drivers/spi/spi-xcomm.c #define SPI_XCOMM_SETTINGS_CS_HIGH BIT(5) BIT 19 drivers/spi/spi-xcomm.c #define SPI_XCOMM_SETTINGS_SAMPLE_END BIT(4) BIT 20 drivers/spi/spi-xcomm.c #define SPI_XCOMM_SETTINGS_CPHA BIT(3) BIT 21 drivers/spi/spi-xcomm.c #define SPI_XCOMM_SETTINGS_CPOL BIT(2) BIT 65 drivers/spi/spi-xcomm.c chipselect |= BIT(cs); BIT 67 drivers/spi/spi-xcomm.c chipselect &= ~BIT(cs); BIT 164 drivers/spi/spi-xcomm.c settings |= BIT(5); BIT 166 drivers/spi/spi-xcomm.c settings &= ~BIT(5); BIT 216 drivers/spi/spi-xilinx.c cs ^= BIT(spi->chip_select); BIT 231 drivers/spi/spi-xilinx.c xspi->cs_inactive &= ~BIT(spi->chip_select); BIT 233 drivers/spi/spi-xilinx.c xspi->cs_inactive |= BIT(spi->chip_select); BIT 17 drivers/spi/spi-xlp.c #define XLP_SPI_CPHA BIT(0) BIT 18 drivers/spi/spi-xlp.c #define XLP_SPI_CPOL BIT(1) BIT 19 drivers/spi/spi-xlp.c #define XLP_SPI_CS_POL BIT(2) BIT 20 drivers/spi/spi-xlp.c #define XLP_SPI_TXMISO_EN BIT(3) BIT 21 drivers/spi/spi-xlp.c #define XLP_SPI_TXMOSI_EN BIT(4) BIT 22 drivers/spi/spi-xlp.c #define XLP_SPI_RXMISO_EN BIT(5) BIT 23 drivers/spi/spi-xlp.c #define XLP_SPI_CS_LSBFE BIT(10) BIT 24 drivers/spi/spi-xlp.c #define XLP_SPI_RXCAP_EN BIT(11) BIT 35 drivers/spi/spi-xlp.c #define XLP_SPI_CMD_CONT BIT(4) BIT 40 drivers/spi/spi-xlp.c #define XLP_SPI_XFR_PENDING BIT(0) BIT 41 drivers/spi/spi-xlp.c #define XLP_SPI_XFR_DONE BIT(1) BIT 42 drivers/spi/spi-xlp.c #define XLP_SPI_TX_INT BIT(2) BIT 43 drivers/spi/spi-xlp.c #define XLP_SPI_RX_INT BIT(3) BIT 44 drivers/spi/spi-xlp.c #define XLP_SPI_TX_UF BIT(4) BIT 45 drivers/spi/spi-xlp.c #define XLP_SPI_RX_OF BIT(5) BIT 50 drivers/spi/spi-xlp.c #define XLP_SPI_INTR_DONE BIT(0) BIT 51 drivers/spi/spi-xlp.c #define XLP_SPI_INTR_TXTH BIT(1) BIT 52 drivers/spi/spi-xlp.c #define XLP_SPI_INTR_RXTH BIT(2) BIT 53 drivers/spi/spi-xlp.c #define XLP_SPI_INTR_TXUF BIT(3) BIT 54 drivers/spi/spi-xlp.c #define XLP_SPI_INTR_RXOF BIT(4) BIT 73 drivers/spi/spi-xlp.c #define XLP_SPI_SYS_RESET BIT(0) BIT 74 drivers/spi/spi-xlp.c #define XLP_SPI_SYS_CLKDIS BIT(1) BIT 75 drivers/spi/spi-xlp.c #define XLP_SPI_SYS_PMEN BIT(8) BIT 47 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_CONFIG_IFMODE_MASK BIT(31) /* Flash Memory Interface */ BIT 48 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_CONFIG_MANSRT_MASK BIT(16) /* Manual TX Start */ BIT 49 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK BIT(15) /* Enable Manual TX Mode */ BIT 50 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_CONFIG_SSFORCE_MASK BIT(14) /* Manual Chip Select */ BIT 52 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_CONFIG_CPHA_MASK BIT(2) /* Clock Phase Control */ BIT 53 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */ BIT 54 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_CONFIG_SSCTRL_MASK BIT(10) /* Slave Select Mask */ BIT 56 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */ BIT 74 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */ BIT 75 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */ BIT 76 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */ BIT 77 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */ BIT 78 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */ BIT 79 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */ BIT 94 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_ENABLE_ENABLE_MASK BIT(0) /* QSPI Enable Bit Mask */ BIT 102 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_LCFG_TWO_MEM_MASK BIT(30) /* LQSPI Two memories Mask */ BIT 103 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_LCFG_SEP_BUS_MASK BIT(29) /* LQSPI Separate bus Mask */ BIT 104 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_LCFG_U_PAGE_MASK BIT(28) /* LQSPI Upper Page Mask */ BIT 295 drivers/spi/spi-zynq-qspi.c config_reg |= (((~(BIT(spi->chip_select))) << BIT 45 drivers/spmi/spmi-pmic-arb.c #define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */ BIT 46 drivers/spmi/spmi-pmic-arb.c #define PMIC_ARB_APID_VALID BIT(15) BIT 47 drivers/spmi/spmi-pmic-arb.c #define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24)) BIT 56 drivers/spmi/spmi-pmic-arb.c PMIC_ARB_STATUS_DONE = BIT(0), BIT 57 drivers/spmi/spmi-pmic-arb.c PMIC_ARB_STATUS_FAILURE = BIT(1), BIT 58 drivers/spmi/spmi-pmic-arb.c PMIC_ARB_STATUS_DENIED = BIT(2), BIT 59 drivers/spmi/spmi-pmic-arb.c PMIC_ARB_STATUS_DROPPED = BIT(3), BIT 101 drivers/spmi/spmi-pmic-arb.c #define SPMI_PIC_ACC_ENABLE_BIT BIT(0) BIT 490 drivers/spmi/spmi-pmic-arb.c u8 irq_mask = BIT(id); BIT 516 drivers/spmi/spmi-pmic-arb.c status &= ~BIT(id); BIT 545 drivers/spmi/spmi-pmic-arb.c status &= ~BIT(id); BIT 564 drivers/spmi/spmi-pmic-arb.c writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); BIT 566 drivers/spmi/spmi-pmic-arb.c data = BIT(irq); BIT 573 drivers/spmi/spmi-pmic-arb.c u8 data = BIT(irq); BIT 590 drivers/spmi/spmi-pmic-arb.c if (!(buf[0] & BIT(irq))) { BIT 596 drivers/spmi/spmi-pmic-arb.c buf[0] = BIT(irq); BIT 597 drivers/spmi/spmi-pmic-arb.c buf[1] = BIT(irq); BIT 611 drivers/spmi/spmi-pmic-arb.c type.type |= BIT(irq); BIT 613 drivers/spmi/spmi-pmic-arb.c type.polarity_high |= BIT(irq); BIT 615 drivers/spmi/spmi-pmic-arb.c type.polarity_low |= BIT(irq); BIT 623 drivers/spmi/spmi-pmic-arb.c type.type &= ~BIT(irq); /* level trig */ BIT 625 drivers/spmi/spmi-pmic-arb.c type.polarity_high |= BIT(irq); BIT 627 drivers/spmi/spmi-pmic-arb.c type.polarity_low |= BIT(irq); BIT 656 drivers/spmi/spmi-pmic-arb.c *state = !!(status & BIT(irq)); BIT 799 drivers/spmi/spmi-pmic-arb.c if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) { BIT 102 drivers/ssb/driver_gpio.c ssb_chipco_gpio_intmask(&bus->chipco, BIT(gpio), 0); BIT 109 drivers/ssb/driver_gpio.c u32 val = ssb_chipco_gpio_in(&bus->chipco, BIT(gpio)); BIT 111 drivers/ssb/driver_gpio.c ssb_chipco_gpio_polarity(&bus->chipco, BIT(gpio), val); BIT 112 drivers/ssb/driver_gpio.c ssb_chipco_gpio_intmask(&bus->chipco, BIT(gpio), BIT(gpio)); BIT 299 drivers/ssb/driver_gpio.c ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), 0); BIT 306 drivers/ssb/driver_gpio.c u32 val = ssb_extif_gpio_in(&bus->extif, BIT(gpio)); BIT 308 drivers/ssb/driver_gpio.c ssb_extif_gpio_polarity(&bus->extif, BIT(gpio), val); BIT 309 drivers/ssb/driver_gpio.c ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), BIT(gpio)); BIT 100 drivers/staging/android/ion/ion.h #define ION_HEAP_FLAG_DEFER_FREE BIT(0) BIT 111 drivers/staging/android/ion/ion.h #define ION_PRIV_FLAG_SHRINKER_FREE BIT(0) BIT 24 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c #define WZRD_CLKOUT0_FRAC_EN BIT(18) BIT 25 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c #define WZRD_CLKFBOUT_FRAC_EN BIT(26) BIT 43 drivers/staging/comedi/comedi_fops.c #define COMEDI_SRF_RT BIT(1) BIT 44 drivers/staging/comedi/comedi_fops.c #define COMEDI_SRF_ERROR BIT(2) BIT 45 drivers/staging/comedi/comedi_fops.c #define COMEDI_SRF_RUNNING BIT(27) BIT 46 drivers/staging/comedi/comedi_fops.c #define COMEDI_SRF_FREE_SPRIV BIT(31) BIT 384 drivers/staging/comedi/comedidev.h COMEDI_CB_EOS = BIT(0), BIT 385 drivers/staging/comedi/comedidev.h COMEDI_CB_EOA = BIT(1), BIT 386 drivers/staging/comedi/comedidev.h COMEDI_CB_BLOCK = BIT(2), BIT 387 drivers/staging/comedi/comedidev.h COMEDI_CB_EOBUF = BIT(3), BIT 388 drivers/staging/comedi/comedidev.h COMEDI_CB_ERROR = BIT(4), BIT 389 drivers/staging/comedi/comedidev.h COMEDI_CB_OVERFLOW = BIT(5), BIT 19 drivers/staging/comedi/drivers/8255.h #define I8255_CTRL_C_LO_IO BIT(0) BIT 20 drivers/staging/comedi/drivers/8255.h #define I8255_CTRL_B_IO BIT(1) BIT 21 drivers/staging/comedi/drivers/8255.h #define I8255_CTRL_B_MODE BIT(2) BIT 22 drivers/staging/comedi/drivers/8255.h #define I8255_CTRL_C_HI_IO BIT(3) BIT 23 drivers/staging/comedi/drivers/8255.h #define I8255_CTRL_A_IO BIT(4) BIT 25 drivers/staging/comedi/drivers/8255.h #define I8255_CTRL_CW BIT(7) BIT 173 drivers/staging/comedi/drivers/8255_pci.c #define WENAB BIT(7) /* window enable */ BIT 81 drivers/staging/comedi/drivers/addi_apci_1032.c #define APCI1032_CTRL_INT_ENA BIT(2) BIT 91 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_EEPROM_VCC_STATUS BIT(8) BIT 93 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_EEPROM_DI BIT(3) BIT 94 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_EEPROM_DO BIT(2) BIT 95 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_EEPROM_CS BIT(1) BIT 96 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_EEPROM_CLK BIT(0) BIT 127 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_DI_IRQ_ENA BIT(2) BIT 128 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_DI_IRQ_MODE BIT(1) /* 1=AND, 0=OR */ BIT 131 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_DO_INT_CTRL_CC_INT_ENA BIT(1) BIT 132 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_DO_INT_CTRL_VCC_INT_ENA BIT(0) BIT 134 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_DO_INT_STATUS_CC BIT(1) BIT 135 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_DO_INT_STATUS_VCC BIT(0) BIT 137 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_DO_IRQ_INTR BIT(0) BIT 156 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_EVENT_COS BIT(31) BIT 157 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_EVENT_TIMER BIT(30) BIT 158 drivers/staging/comedi/drivers/addi_apci_1564.c #define APCI1564_EVENT_COUNTER(x) BIT(27 + (x)) /* counter 0-2 */ BIT 28 drivers/staging/comedi/drivers/addi_apci_2032.c #define APCI2032_INT_CTRL_VCC_ENA BIT(0) BIT 29 drivers/staging/comedi/drivers/addi_apci_2032.c #define APCI2032_INT_CTRL_CC_ENA BIT(1) BIT 31 drivers/staging/comedi/drivers/addi_apci_2032.c #define APCI2032_INT_STATUS_VCC BIT(0) BIT 32 drivers/staging/comedi/drivers/addi_apci_2032.c #define APCI2032_INT_STATUS_CC BIT(1) BIT 34 drivers/staging/comedi/drivers/addi_apci_2032.c #define APCI2032_STATUS_IRQ BIT(0) BIT 25 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_FIFO_ADVANCE_ON_BYTE_2 BIT(29) BIT 32 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_CTRL_EXT_TRIG BIT(15) BIT 33 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_CTRL_GATE(x) BIT(12 + (x)) BIT 38 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_STATUS_EOC_INT BIT(15) BIT 39 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_STATUS_AMCC_INT BIT(14) BIT 40 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_STATUS_EOS_INT BIT(13) BIT 41 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_STATUS_TIMER2_INT BIT(12) BIT 45 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_STATUS_FIFO_FULL BIT(2) BIT 46 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_STATUS_FIFO_EMPTY BIT(1) BIT 47 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_STATUS_DA_READY BIT(0) BIT 51 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_CHANLIST_UNIPOLAR BIT(7) BIT 79 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_MODE_SCAN_ENA BIT(3) BIT 80 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_MODE_TIMER2_IRQ_ENA BIT(2) BIT 81 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_MODE_EOS_IRQ_ENA BIT(1) BIT 82 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_MODE_EOC_IRQ_ENA BIT(0) BIT 90 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_ADDON_CTRL_AMWEN_ENA BIT(1) BIT 91 drivers/staging/comedi/drivers/addi_apci_3120.c #define APCI3120_ADDON_CTRL_A2P_FIFO_ENA BIT(0) BIT 52 drivers/staging/comedi/drivers/addi_apci_3501.c #define APCI3501_AO_CTRL_BIPOLAR BIT(0) BIT 53 drivers/staging/comedi/drivers/addi_apci_3501.c #define APCI3501_AO_STATUS_READY BIT(8) BIT 57 drivers/staging/comedi/drivers/addi_apci_3501.c #define APCI3501_AO_DATA_BIPOLAR BIT(31) BIT 21 drivers/staging/comedi/drivers/addi_apci_3xxx.c #define CONV_UNIT_NS BIT(0) BIT 22 drivers/staging/comedi/drivers/addi_apci_3xxx.c #define CONV_UNIT_US BIT(1) BIT 23 drivers/staging/comedi/drivers/addi_apci_3xxx.c #define CONV_UNIT_MS BIT(2) BIT 14 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_SYNC_CTR_TRIG BIT(8) BIT 15 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_SYNC_CTR_DIS BIT(7) BIT 16 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_SYNC_CTR_ENA BIT(6) BIT 17 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_SYNC_TIMER_TRIG BIT(5) BIT 18 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_SYNC_TIMER_DIS BIT(4) BIT 19 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_SYNC_TIMER_ENA BIT(3) BIT 20 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_SYNC_WDOG_TRIG BIT(2) BIT 21 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_SYNC_WDOG_DIS BIT(1) BIT 22 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_SYNC_WDOG_ENA BIT(0) BIT 29 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_EXT_CLK_STATUS BIT(21) BIT 30 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_CASCADE BIT(20) BIT 31 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_CNTR_ENA BIT(19) BIT 32 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_CNT_UP BIT(18) BIT 39 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_GATE BIT(10) BIT 40 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_TRIG BIT(9) BIT 45 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_TIMER_ENA BIT(4) BIT 46 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_RESET_ENA BIT(3) BIT 47 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_WARN_ENA BIT(2) BIT 48 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_IRQ_ENA BIT(1) BIT 49 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_CTRL_ENA BIT(0) BIT 52 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_STATUS_SOFT_CLR BIT(3) BIT 53 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_STATUS_HARDWARE_TRIG BIT(2) BIT 54 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_STATUS_SOFT_TRIG BIT(1) BIT 55 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_STATUS_OVERFLOW BIT(0) BIT 58 drivers/staging/comedi/drivers/addi_tcw.h #define ADDI_TCW_IRQ BIT(0) BIT 35 drivers/staging/comedi/drivers/adl_pci6208.c #define PCI6208_AO_STATUS_DATA_SEND BIT(0) BIT 67 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_AI_STAT_AD_BUSY BIT(7) BIT 68 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_AI_STAT_FF_FF BIT(6) BIT 69 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_AI_STAT_FF_HF BIT(5) BIT 70 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_AI_STAT_FF_EF BIT(4) BIT 74 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_AI_TRIG_CTRL_TRGEVENT BIT(5) BIT 75 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_AI_TRIG_CTRL_POTRG BIT(4) BIT 76 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_AI_TRIG_CTRL_PTRG BIT(3) BIT 77 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_AI_TRIG_CTRL_ETIS BIT(2) BIT 78 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_AI_TRIG_CTRL_TPST BIT(1) BIT 79 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_AI_TRIG_CTRL_ASCAN BIT(0) BIT 81 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_INT_CTRL_ISC2 BIT(3) BIT 82 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_INT_CTRL_FFEN BIT(2) BIT 83 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_INT_CTRL_ISC1 BIT(1) BIT 84 drivers/staging/comedi/drivers/adl_pci9111.c #define PCI9111_INT_CTRL_ISC0 BIT(0) BIT 94 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_STATUS_NFULL BIT(8) /* 0=FIFO full (fatal) */ BIT 95 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_STATUS_NHFULL BIT(7) /* 0=FIFO half full */ BIT 96 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_STATUS_NEPTY BIT(6) /* 0=FIFO empty */ BIT 97 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_STATUS_ACMP BIT(5) /* 1=about trigger complete */ BIT 98 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_STATUS_DTH BIT(4) /* 1=ext. digital trigger */ BIT 99 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_STATUS_BOVER BIT(3) /* 1=burst overrun (fatal) */ BIT 100 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_STATUS_ADOS BIT(2) /* 1=A/D over speed (warn) */ BIT 101 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_STATUS_ADOR BIT(1) /* 1=A/D overrun (fatal) */ BIT 102 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_STATUS_ADRDY BIT(0) /* 1=A/D ready */ BIT 104 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CTRL_UNIP BIT(7) /* 1=unipolar */ BIT 105 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CTRL_DIFF BIT(6) /* 1=differential inputs */ BIT 106 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CTRL_SOFTG BIT(5) /* 1=8254 software gate */ BIT 107 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CTRL_EXTG BIT(4) /* 1=8254 TGIN(pin 46) gate */ BIT 108 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CTRL_EXTM BIT(3) /* 1=ext. trigger (pin 44) */ BIT 109 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CTRL_TMRTR BIT(2) /* 1=8254 is trigger source */ BIT 110 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CTRL_INT BIT(1) /* 1=enable interrupt */ BIT 111 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CTRL_DMA BIT(0) /* 1=enable DMA */ BIT 120 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CFG_PDTRG BIT(7) /* 1=positive trigger */ BIT 121 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CFG_PETRG BIT(6) /* 1=positive ext. trigger */ BIT 122 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CFG_BSSH BIT(5) /* 1=with sample & hold */ BIT 123 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CFG_BM BIT(4) /* 1=burst mode */ BIT 124 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CFG_BS BIT(3) /* 1=burst mode start */ BIT 125 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CFG_PM BIT(2) /* 1=post trigger */ BIT 126 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CFG_AM BIT(1) /* 1=about trigger */ BIT 127 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_AI_CFG_START BIT(0) /* 1=trigger start */ BIT 130 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_INT_CTRL_TIMER BIT(3) /* timer interrupt */ BIT 131 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_INT_CTRL_ABOUT BIT(2) /* about trigger complete */ BIT 132 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_INT_CTRL_HFULL BIT(1) /* A/D FIFO half full */ BIT 133 drivers/staging/comedi/drivers/adl_pci9118.c #define PCI9118_INT_CTRL_DTRG BIT(0) /* ext. digital trigger */ BIT 56 drivers/staging/comedi/drivers/adq12b.c #define ADQ12B_CTREG_MSKP BIT(7) /* enable pacer interrupt */ BIT 57 drivers/staging/comedi/drivers/adq12b.c #define ADQ12B_CTREG_GTP BIT(6) /* enable pacer */ BIT 61 drivers/staging/comedi/drivers/adq12b.c #define ADQ12B_STINR_OUT2 BIT(7) /* timer 2 output state */ BIT 62 drivers/staging/comedi/drivers/adq12b.c #define ADQ12B_STINR_OUTP BIT(6) /* pacer output state */ BIT 63 drivers/staging/comedi/drivers/adq12b.c #define ADQ12B_STINR_EOC BIT(5) /* A/D end-of-conversion */ BIT 45 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_RANGE_DIFF BIT(5) BIT 46 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_RANGE_UNI BIT(4) BIT 53 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_STATUS_IRQ BIT(11) /* 1=IRQ occurred */ BIT 54 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_STATUS_FF BIT(10) /* 1=FIFO is full, fatal error */ BIT 55 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_STATUS_FH BIT(9) /* 1=FIFO is half full */ BIT 56 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_STATUS_FE BIT(8) /* 1=FIFO is empty */ BIT 58 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_CTRL_CNT0 BIT(6) /* 1=ext. clk, 0=int. 100kHz clk */ BIT 59 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_CTRL_ONEFH BIT(5) /* 1=on FIFO half full, 0=on sample */ BIT 60 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_CTRL_IRQEN BIT(4) /* 1=enable IRQ */ BIT 61 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_CTRL_GATE BIT(3) /* 1=enable ext. trigger GATE (8254?) */ BIT 62 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_CTRL_EXT BIT(2) /* 1=enable ext. trigger source */ BIT 63 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_CTRL_PACER BIT(1) /* 1=enable int. 8254 trigger source */ BIT 64 drivers/staging/comedi/drivers/adv_pci1710.c #define PCI171X_CTRL_SW BIT(0) /* 1=enable software trigger source */ BIT 58 drivers/staging/comedi/drivers/adv_pci1720.c #define PCI1720_SYNC_CTRL_SC0 BIT(0) BIT 49 drivers/staging/comedi/drivers/adv_pci1723.c #define PCI1723_CTRL_BUSY BIT(15) BIT 50 drivers/staging/comedi/drivers/adv_pci1723.c #define PCI1723_CTRL_INIT BIT(14) BIT 51 drivers/staging/comedi/drivers/adv_pci1723.c #define PCI1723_CTRL_SELF BIT(8) BIT 59 drivers/staging/comedi/drivers/adv_pci1723.c #define PCI1723_CALIB_CTRL_CS BIT(2) BIT 60 drivers/staging/comedi/drivers/adv_pci1723.c #define PCI1723_CALIB_CTRL_DAT BIT(1) BIT 61 drivers/staging/comedi/drivers/adv_pci1723.c #define PCI1723_CALIB_CTRL_CLK BIT(0) BIT 64 drivers/staging/comedi/drivers/adv_pci1723.c #define PCI1723_DIO_CTRL_HDIO BIT(1) BIT 65 drivers/staging/comedi/drivers/adv_pci1723.c #define PCI1723_DIO_CTRL_LDIO BIT(0) BIT 48 drivers/staging/comedi/drivers/adv_pci1724.c #define PCI1724_DAC_CTRL_GX(x) BIT(20 + ((x) / 8)) BIT 57 drivers/staging/comedi/drivers/adv_pci1724.c #define PCI1724_SYNC_CTRL_DACSTAT BIT(1) BIT 58 drivers/staging/comedi/drivers/adv_pci1724.c #define PCI1724_SYNC_CTRL_SYN BIT(0) BIT 52 drivers/staging/comedi/drivers/adv_pci1760.c #define PCI1760_INTCSR1_IRQ_ENA BIT(5) BIT 53 drivers/staging/comedi/drivers/adv_pci1760.c #define PCI1760_INTCSR2_OMB_IRQ BIT(0) BIT 54 drivers/staging/comedi/drivers/adv_pci1760.c #define PCI1760_INTCSR2_IMB_IRQ BIT(1) BIT 55 drivers/staging/comedi/drivers/adv_pci1760.c #define PCI1760_INTCSR2_IRQ_STATUS BIT(6) BIT 56 drivers/staging/comedi/drivers/adv_pci1760.c #define PCI1760_INTCSR2_IRQ_ASSERTED BIT(7) BIT 85 drivers/staging/comedi/drivers/adv_pci1760.c #define PCI1760_CMD_GET_INT_FLAGS_MATCH BIT(0) BIT 86 drivers/staging/comedi/drivers/adv_pci1760.c #define PCI1760_CMD_GET_INT_FLAGS_COS BIT(1) BIT 87 drivers/staging/comedi/drivers/adv_pci1760.c #define PCI1760_CMD_GET_INT_FLAGS_OFLOW BIT(2) BIT 213 drivers/staging/comedi/drivers/adv_pci1760.c ret |= BIT(chan); BIT 215 drivers/staging/comedi/drivers/adv_pci1760.c ret &= ~BIT(chan); BIT 290 drivers/staging/comedi/drivers/adv_pci1760.c data[1] = (ret & BIT(chan)) ? 1 : 0; BIT 34 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_STATUS_ADC_EOC BIT(7) BIT 35 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_STATUS_PORT_C_COS BIT(6) BIT 36 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_STATUS_IRQ_ENA BIT(2) BIT 38 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_INTERRUPT_ADC BIT(7) BIT 39 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_INTERRUPT_COS BIT(6) BIT 40 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_INTERRUPT_COUNTER1 BIT(5) BIT 41 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_INTERRUPT_PORT_C3 BIT(4) BIT 42 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_INTERRUPT_PORT_C0 BIT(3) BIT 43 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_INTERRUPT_ENA BIT(2) BIT 59 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_DIO_CONTROL_TST BIT(0) BIT 64 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_TRIGGER_ADTRIG BIT(1) BIT 65 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_TRIGGER_DACTRIG BIT(0) BIT 68 drivers/staging/comedi/drivers/aio_aio12_8.c #define AIO12_8_DAC_ENABLE_REF_ENA BIT(0) BIT 42 drivers/staging/comedi/drivers/aio_iiro_16.c #define AIO_IIRO_16_STATUS_IRQE BIT(7) BIT 43 drivers/staging/comedi/drivers/aio_iiro_16.c #define AIO_IIRO_16_STATUS_INPUT_8_15 BIT(1) BIT 44 drivers/staging/comedi/drivers/aio_iiro_16.c #define AIO_IIRO_16_STATUS_INPUT_0_7 BIT(0) BIT 148 drivers/staging/comedi/drivers/amplc_pci224.c #define PCI224_DACCON_FIFOWRAP BIT(7) BIT 150 drivers/staging/comedi/drivers/amplc_pci224.c #define PCI224_DACCON_FIFOENAB BIT(8) BIT 168 drivers/staging/comedi/drivers/amplc_pci224.c #define PCI224_DACCON_BUSY BIT(15) BIT 170 drivers/staging/comedi/drivers/amplc_pci224.c #define PCI224_DACCON_FIFORESET BIT(12) BIT 172 drivers/staging/comedi/drivers/amplc_pci224.c #define PCI224_DACCON_GLOBALRESET BIT(13) BIT 239 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P2_DAC_FIFO_EN BIT(8) /* FIFO enable */ BIT 253 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P2_DAC_FIFO_WRAP BIT(7) /* FIFO wraparound mode */ BIT 266 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_DAC_BUSY BIT(1) /* DAC busy. */ BIT 271 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P2_DAC_FIFO_UNDERRUN_LATCHED BIT(5) /* Underrun error */ BIT 272 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P2_DAC_FIFO_EMPTY BIT(13) /* FIFO empty */ BIT 273 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P2_DAC_FIFO_FULL BIT(14) /* FIFO full */ BIT 274 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P2_DAC_FIFO_HALF BIT(15) /* FIFO half full */ BIT 283 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P2_DAC_FIFO_UNDERRUN_CLEAR BIT(5) /* Clear underrun */ BIT 284 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P2_DAC_FIFO_RESET BIT(12) /* FIFO reset */ BIT 318 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_ADC_FIFO_EN BIT(8) /* FIFO enable */ BIT 332 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_ADC_FIFO_RESET BIT(12) /* FIFO reset */ BIT 333 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_ADC_GLOB_RESET BIT(13) /* Global reset */ BIT 338 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_ADC_BUSY BIT(15) /* ADC busy */ BIT 339 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_ADC_FIFO_EMPTY BIT(12) /* FIFO empty */ BIT 340 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_ADC_FIFO_FULL BIT(13) /* FIFO full */ BIT 341 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_ADC_FIFO_HALF BIT(14) /* FIFO half full */ BIT 342 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_ADC_FIFO_FULL_LATCHED BIT(5) /* FIFO overrun occurred */ BIT 354 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P_EXTFUNC_GAT_EXTTRIG BIT(0) BIT 357 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P2_EXTFUNC_DACFIFO BIT(1) BIT 405 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_INT_PPI_C0 BIT(0) BIT 406 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_INT_PPI_C3 BIT(1) BIT 407 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_INT_ADC BIT(2) BIT 408 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230_INT_ZCLK_CT1 BIT(5) BIT 410 drivers/staging/comedi/drivers/amplc_pci230.c #define PCI230P2_INT_DAC BIT(4) BIT 416 drivers/staging/comedi/drivers/amplc_pci230.c RES_Z2CT0 = BIT(0), /* Z2-CT0 */ BIT 417 drivers/staging/comedi/drivers/amplc_pci230.c RES_Z2CT1 = BIT(1), /* Z2-CT1 */ BIT 418 drivers/staging/comedi/drivers/amplc_pci230.c RES_Z2CT2 = BIT(2) /* Z2-CT2 */ BIT 2468 drivers/staging/comedi/drivers/amplc_pci230.c outw(BIT(0), devpriv->daqio + PCI230_ADCEN); BIT 41 drivers/staging/comedi/drivers/c6xdigio.c #define C6XDIGIO_DATA_PWM BIT(5) BIT 42 drivers/staging/comedi/drivers/c6xdigio.c #define C6XDIGIO_DATA_ENCODER BIT(6) BIT 45 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC1_INTE BIT(15) /* 1=enable; 0=disable */ BIT 54 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC1_OVR BIT(10) /* ro - 1=FIFO overflow */ BIT 61 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC1_EOC BIT(7) /* ro - 0=busy; 1=ready */ BIT 62 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC1_SEDIFF BIT(5) /* 0=diff; 1=se */ BIT 63 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC1_INTB BIT(4) /* ro - 0=latched; 1=cleared */ BIT 65 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC1_DAC1CS BIT(3) /* wo - DAC1 chip select */ BIT 66 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC1_DACCLK BIT(2) /* wo - Serial DAC clock */ BIT 67 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC1_DACSD BIT(1) /* wo - Serial DAC data */ BIT 68 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC1_DAC0CS BIT(0) /* wo - DAC0 chip select */ BIT 71 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC2_BME BIT(14) /* 1=burst enable; 0=disable */ BIT 78 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC2_UDIR BIT(7) /* 1=dio7:4 output; 0=input */ BIT 79 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC2_LDIR BIT(6) /* 1=dio3:0 output; 0=input */ BIT 80 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC2_TRGPOL BIT(5) /* 1=active lo; 0=hi */ BIT 81 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC2_TRGSEL BIT(4) /* 1=edge; 0=level */ BIT 82 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC2_FFNE BIT(3) /* ro - 1=FIFO not empty */ BIT 83 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC2_TRGCLR BIT(3) /* wo - 1=clr (monstable) */ BIT 84 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC2_CLK2 BIT(2) /* 1=10 MHz; 0=1 MHz */ BIT 85 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC2_CTR1 BIT(1) /* 1=int. 100 kHz; 0=ext. clk */ BIT 86 drivers/staging/comedi/drivers/cb_das16_cs.c #define DAS16CS_MISC2_TRG0 BIT(0) /* 1=enable; 0=disable */ BIT 77 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_INTE BIT(2) /* int enable */ BIT 78 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_DAHFIE BIT(3) /* dac half full int enable */ BIT 79 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_EOAIE BIT(4) /* end of acq. int enable */ BIT 80 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_DAHFI BIT(5) /* dac half full status / clear */ BIT 81 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_EOAI BIT(6) /* end of acq. int status / clear */ BIT 82 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_INT_CLR BIT(7) /* int status / clear */ BIT 83 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_EOBI BIT(9) /* end of burst int status */ BIT 84 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_ADHFI BIT(10) /* half-full int status */ BIT 85 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_ADNEI BIT(11) /* fifo not empty int status (latch) */ BIT 86 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_ADNE BIT(12) /* fifo not empty status (realtime) */ BIT 87 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_DAEMIE BIT(12) /* dac empty int enable */ BIT 88 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_LADFUL BIT(13) /* fifo overflow / clear */ BIT 89 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CTRL_DAEMI BIT(14) /* dac fifo empty int status / clear */ BIT 101 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_AI_SE BIT(10) /* Inputs in single-ended mode */ BIT 102 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_AI_UNIP BIT(11) /* Analog front-end unipolar mode */ BIT 109 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_AI_EOC BIT(14) /* adc not busy */ BIT 118 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_TRIG_POL BIT(2) /* invert trigger (1602 only) */ BIT 119 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_TRIG_MODE BIT(3) /* edge/level triggered (1602 only) */ BIT 120 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_TRIG_EN BIT(4) /* enable external start trigger */ BIT 121 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_TRIG_BURSTE BIT(5) /* burst mode enable */ BIT 122 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_TRIG_CLR BIT(7) /* clear external trigger */ BIT 125 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CALIB_8800_SEL BIT(8) /* select 8800 caldac */ BIT 126 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CALIB_TRIM_SEL BIT(9) /* select ad7376 trim pot */ BIT 127 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CALIB_DAC08_SEL BIT(10) /* select dac08 caldac */ BIT 129 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CALIB_EN BIT(14) /* calibration source enable */ BIT 130 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_CALIB_DATA BIT(15) /* serial data bit going to caldac */ BIT 133 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_AO_EMPTY BIT(0) /* fifo empty, write clear (1602) */ BIT 134 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_AO_DACEN BIT(1) /* dac enable */ BIT 135 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_AO_START BIT(2) /* start/arm fifo (1602) */ BIT 142 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_AO_CHAN_EN(c) BIT(5 + ((c) & 0x1)) BIT 144 drivers/staging/comedi/drivers/cb_pcidas.c #define PCIDAS_AO_UPDATE_BOTH BIT(7) /* update both dacs */ BIT 45 drivers/staging/comedi/drivers/cb_pcidda.c #define CB_DDA_DA_CTRL_SU BIT(0) /* Simultaneous update */ BIT 46 drivers/staging/comedi/drivers/cb_pcidda.c #define CB_DDA_DA_CTRL_EN BIT(1) /* Enable specified DAC */ BIT 51 drivers/staging/comedi/drivers/cb_pcidda.c #define CB_DDA_DA_CTRL_UNIP BIT(8) /* Unipolar range */ BIT 63 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_STATUS_EOC BIT(7) BIT 64 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_STATUS_UB BIT(6) BIT 65 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_STATUS_MUX BIT(5) BIT 66 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_STATUS_CLK BIT(4) BIT 69 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_CONV_STATUS_EOC BIT(7) BIT 70 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_CONV_STATUS_EOB BIT(6) BIT 71 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_CONV_STATUS_EOA BIT(5) BIT 72 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_CONV_STATUS_FNE BIT(4) BIT 73 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_CONV_STATUS_FHF BIT(3) BIT 74 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_CONV_STATUS_OVERRUN BIT(2) BIT 76 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_IRQ_INTE BIT(7) BIT 77 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_IRQ_INT BIT(6) BIT 78 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_IRQ_OVERRUN BIT(4) BIT 79 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_IRQ_EOA BIT(3) BIT 80 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_IRQ_EOA_INT_SEL BIT(2) BIT 87 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_PACER_GATE_STATUS BIT(6) BIT 88 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_PACER_GATE_POL BIT(5) BIT 89 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_PACER_GATE_LATCH BIT(4) BIT 90 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_PACER_GATE_EN BIT(3) BIT 91 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_PACER_EXT_PACER_POL BIT(2) BIT 98 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_BURST_BME BIT(1) BIT 99 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_BURST_CONV_EN BIT(0) BIT 103 drivers/staging/comedi/drivers/cb_pcimdas.c #define PCIMDAS_USER_CNTR_CTR1_CLK_SEL BIT(0) BIT 47 drivers/staging/comedi/drivers/comedi_8254.h #define I8254_CTRL_READBACK(x) (I8254_CTRL_SEL_CTR(3) | BIT(x)) BIT 69 drivers/staging/comedi/drivers/comedi_parport.c #define PARPORT_CTRL_IRQ_ENA BIT(4) BIT 70 drivers/staging/comedi/drivers/comedi_parport.c #define PARPORT_CTRL_BIDIR_ENA BIT(5) BIT 36 drivers/staging/comedi/drivers/das08.c #define DAS08_STATUS_AI_BUSY BIT(7) /* AI conversion in progress */ BIT 42 drivers/staging/comedi/drivers/das08.c #define DAS08_STATUS_IRQ BIT(3) /* latched interrupt input */ BIT 52 drivers/staging/comedi/drivers/das08.c #define DAS08_CONTROL_INTE BIT(3) /* interrupt enable (not "JR" boards) */ BIT 239 drivers/staging/comedi/drivers/das08.c data[n] = BIT(15) + magnitude; BIT 241 drivers/staging/comedi/drivers/das08.c data[n] = BIT(15) - magnitude; BIT 86 drivers/staging/comedi/drivers/das16.c #define DAS16_STATUS_BUSY BIT(7) BIT 87 drivers/staging/comedi/drivers/das16.c #define DAS16_STATUS_UNIPOLAR BIT(6) BIT 88 drivers/staging/comedi/drivers/das16.c #define DAS16_STATUS_MUXBIT BIT(5) BIT 89 drivers/staging/comedi/drivers/das16.c #define DAS16_STATUS_INT BIT(4) BIT 91 drivers/staging/comedi/drivers/das16.c #define DAS16_CTRL_INTE BIT(7) BIT 93 drivers/staging/comedi/drivers/das16.c #define DAS16_CTRL_DMAE BIT(2) BIT 100 drivers/staging/comedi/drivers/das16.c #define DAS16_PACER_CTR0 BIT(1) BIT 101 drivers/staging/comedi/drivers/das16.c #define DAS16_PACER_TRIG0 BIT(0) BIT 106 drivers/staging/comedi/drivers/das16.c #define DAS1600_CONV_DISABLE BIT(6) BIT 108 drivers/staging/comedi/drivers/das16.c #define DAS1600_BURST_VAL BIT(6) BIT 110 drivers/staging/comedi/drivers/das16.c #define DAS1600_ENABLE_VAL BIT(6) BIT 112 drivers/staging/comedi/drivers/das16.c #define DAS1600_STATUS_BME BIT(6) BIT 113 drivers/staging/comedi/drivers/das16.c #define DAS1600_STATUS_ME BIT(5) BIT 114 drivers/staging/comedi/drivers/das16.c #define DAS1600_STATUS_CD BIT(4) BIT 115 drivers/staging/comedi/drivers/das16.c #define DAS1600_STATUS_WS BIT(1) BIT 116 drivers/staging/comedi/drivers/das16.c #define DAS1600_STATUS_CLK_10MHZ BIT(0) BIT 57 drivers/staging/comedi/drivers/das16m1.c #define DAS16M1_CS_EXT_TRIG BIT(0) BIT 58 drivers/staging/comedi/drivers/das16m1.c #define DAS16M1_CS_OVRUN BIT(5) BIT 59 drivers/staging/comedi/drivers/das16m1.c #define DAS16M1_CS_IRQDATA BIT(7) BIT 69 drivers/staging/comedi/drivers/das16m1.c #define DAS16M1_INTR_CTRL_INTE BIT(7) BIT 44 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_FFNE BIT(0) BIT 45 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_FHALF BIT(1) BIT 46 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_FFULL BIT(2) BIT 47 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_XINT BIT(3) BIT 48 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_INT BIT(4) BIT 49 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_XTRIG BIT(5) BIT 50 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_INDGT BIT(6) BIT 51 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_10MHZ BIT(7) BIT 52 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_W_CLRINT BIT(0) BIT 53 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_W_CLRXTR BIT(1) BIT 54 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_W_CLRXIN BIT(2) BIT 55 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_W_EXTEND BIT(4) BIT 56 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_W_ARMED BIT(5) BIT 57 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_W_POSTMODE BIT(6) BIT 58 drivers/staging/comedi/drivers/das6402.c #define DAS6402_STATUS_W_10MHZ BIT(7) BIT 65 drivers/staging/comedi/drivers/das6402.c #define DAS6402_CTRL_BURSTEN BIT(2) BIT 66 drivers/staging/comedi/drivers/das6402.c #define DAS6402_CTRL_XINTE BIT(3) BIT 68 drivers/staging/comedi/drivers/das6402.c #define DAS6402_CTRL_INTE BIT(7) BIT 70 drivers/staging/comedi/drivers/das6402.c #define DAS6402_TRIG_TGEN BIT(0) BIT 71 drivers/staging/comedi/drivers/das6402.c #define DAS6402_TRIG_TGSEL BIT(1) BIT 72 drivers/staging/comedi/drivers/das6402.c #define DAS6402_TRIG_TGPOL BIT(2) BIT 73 drivers/staging/comedi/drivers/das6402.c #define DAS6402_TRIG_PRETRIG BIT(3) BIT 82 drivers/staging/comedi/drivers/das6402.c #define DAS6402_MODE_ENHANCED BIT(4) BIT 83 drivers/staging/comedi/drivers/das6402.c #define DAS6402_MODE_SE BIT(5) BIT 84 drivers/staging/comedi/drivers/das6402.c #define DAS6402_MODE_UNI BIT(6) BIT 40 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AUX_DOUT2 BIT(2) /* J3.42 - OUT2 (OUT2EN) */ BIT 41 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AUX_DOUT1 BIT(1) /* J3.43 */ BIT 42 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AUX_DOUT0 BIT(0) /* J3.44 - OUT0 (OUT0EN) */ BIT 47 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AUX_DI_DACBUSY BIT(7) BIT 48 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AUX_DI_CALBUSY BIT(6) BIT 49 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AUX_DI3 BIT(3) /* J3.45 - ADCLK (CLKSEL) */ BIT 50 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AUX_DI2 BIT(2) /* J3.46 - GATE12 (GT12EN) */ BIT 51 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AUX_DI1 BIT(1) /* J3.47 - GATE0 (GT0EN) */ BIT 52 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AUX_DI0 BIT(0) /* J3.48 - CLK0 (SRC0) */ BIT 58 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_FIFO_CTRL_FIFOEN BIT(3) BIT 59 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_FIFO_CTRL_SCANEN BIT(2) BIT 60 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_FIFO_CTRL_FIFORST BIT(1) BIT 62 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_FIFO_STATUS_EF BIT(7) BIT 63 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_FIFO_STATUS_HF BIT(6) BIT 64 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_FIFO_STATUS_FF BIT(5) BIT 65 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_FIFO_STATUS_OVF BIT(4) BIT 66 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_FIFO_STATUS_FIFOEN BIT(3) BIT 67 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_FIFO_STATUS_SCANEN BIT(2) BIT 70 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_CTRL_RESETA BIT(5) BIT 71 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_CTRL_RESETD BIT(4) BIT 72 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_CTRL_INTRST BIT(3) BIT 78 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AI_STATUS_STS BIT(7) BIT 79 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AI_STATUS_SD1 BIT(6) BIT 80 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AI_STATUS_SD0 BIT(5) BIT 83 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_INTCLK_ADINT BIT(7) BIT 84 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_INTCLK_DINT BIT(6) BIT 85 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_INTCLK_TINT BIT(5) BIT 86 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_INTCLK_CLKEN BIT(1) /* 1=see below 0=software */ BIT 87 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_INTCLK_CLKSEL BIT(0) /* 1=OUT2 0=EXTCLK */ BIT 89 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_CTRDIO_CFG_FREQ12 BIT(7) /* CLK12 1=100KHz 0=10MHz */ BIT 90 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_CTRDIO_CFG_FREQ0 BIT(6) /* CLK0 1=10KHz 0=10MHz */ BIT 91 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_CTRDIO_CFG_OUT2EN BIT(5) /* J3.42 1=OUT2 is DOUT2 */ BIT 92 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_CTRDIO_CFG_OUT0EN BIT(4) /* J3,44 1=OUT0 is DOUT0 */ BIT 93 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_CTRDIO_CFG_GT0EN BIT(2) /* J3.47 1=DIN1 is GATE0 */ BIT 94 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_CTRDIO_CFG_SRC0 BIT(1) /* CLK0 is 0=FREQ0 1=J3.48 */ BIT 95 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_CTRDIO_CFG_GT12EN BIT(0) /* J3.46 1=DIN2 is GATE12 */ BIT 102 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AI_CFG_RANGE BIT(3) /* 0=5V 1=10V */ BIT 103 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AI_CFG_ADBU BIT(2) /* 0=bipolar 1=unipolar */ BIT 106 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AI_READBACK_WAIT BIT(7) /* DMM32AT_AI_STATUS_STS */ BIT 107 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AI_READBACK_RANGE BIT(3) BIT 108 drivers/staging/comedi/drivers/dmm32at.c #define DMM32AT_AI_READBACK_ADBU BIT(2) BIT 73 drivers/staging/comedi/drivers/dt2801.c #define DT_MOD_DMA BIT(4) BIT 74 drivers/staging/comedi/drivers/dt2801.c #define DT_MOD_CONT BIT(5) BIT 75 drivers/staging/comedi/drivers/dt2801.c #define DT_MOD_EXTCLK BIT(6) BIT 76 drivers/staging/comedi/drivers/dt2801.c #define DT_MOD_EXTTRIG BIT(7) BIT 79 drivers/staging/comedi/drivers/dt2801.c #define DT_S_DATA_OUT_READY BIT(0) BIT 80 drivers/staging/comedi/drivers/dt2801.c #define DT_S_DATA_IN_FULL BIT(1) BIT 81 drivers/staging/comedi/drivers/dt2801.c #define DT_S_READY BIT(2) BIT 82 drivers/staging/comedi/drivers/dt2801.c #define DT_S_COMMAND BIT(3) BIT 83 drivers/staging/comedi/drivers/dt2801.c #define DT_S_COMPOSITE_ERROR BIT(7) BIT 50 drivers/staging/comedi/drivers/dt2811.c #define DT2811_ADCSR_ADDONE BIT(7) /* r 1=A/D conv done */ BIT 51 drivers/staging/comedi/drivers/dt2811.c #define DT2811_ADCSR_ADERROR BIT(6) /* r 1=A/D error */ BIT 52 drivers/staging/comedi/drivers/dt2811.c #define DT2811_ADCSR_ADBUSY BIT(5) /* r 1=A/D busy */ BIT 53 drivers/staging/comedi/drivers/dt2811.c #define DT2811_ADCSR_CLRERROR BIT(4) BIT 54 drivers/staging/comedi/drivers/dt2811.c #define DT2811_ADCSR_DMAENB BIT(3) /* r/w 1=dma ena */ BIT 55 drivers/staging/comedi/drivers/dt2811.c #define DT2811_ADCSR_INTENB BIT(2) /* r/w 1=interrupts ena */ BIT 567 drivers/staging/comedi/drivers/dt2811.c if (it->options[1] <= 7 && (BIT(it->options[1]) & 0xac)) { BIT 63 drivers/staging/comedi/drivers/dt282x.c #define DT2821_ADCSR_ADERR BIT(15) BIT 64 drivers/staging/comedi/drivers/dt282x.c #define DT2821_ADCSR_ADCLK BIT(9) BIT 65 drivers/staging/comedi/drivers/dt282x.c #define DT2821_ADCSR_MUXBUSY BIT(8) BIT 66 drivers/staging/comedi/drivers/dt282x.c #define DT2821_ADCSR_ADDONE BIT(7) BIT 67 drivers/staging/comedi/drivers/dt282x.c #define DT2821_ADCSR_IADDONE BIT(6) BIT 71 drivers/staging/comedi/drivers/dt282x.c #define DT2821_CHANCSR_LLE BIT(15) BIT 76 drivers/staging/comedi/drivers/dt282x.c #define DT2821_DACSR_DAERR BIT(15) BIT 78 drivers/staging/comedi/drivers/dt282x.c #define DT2821_DACSR_SSEL BIT(8) BIT 79 drivers/staging/comedi/drivers/dt282x.c #define DT2821_DACSR_DACRDY BIT(7) BIT 80 drivers/staging/comedi/drivers/dt282x.c #define DT2821_DACSR_IDARDY BIT(6) BIT 81 drivers/staging/comedi/drivers/dt282x.c #define DT2821_DACSR_DACLK BIT(5) BIT 82 drivers/staging/comedi/drivers/dt282x.c #define DT2821_DACSR_HBOE BIT(1) BIT 83 drivers/staging/comedi/drivers/dt282x.c #define DT2821_DACSR_LBOE BIT(0) BIT 87 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_DMAD BIT(15) BIT 88 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_ERRINTEN BIT(14) BIT 89 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_CLRDMADNE BIT(13) BIT 90 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_DDMA BIT(12) BIT 96 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_BUFFB BIT(9) BIT 97 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_SCDN BIT(8) BIT 98 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_DACON BIT(7) BIT 99 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_ADCINIT BIT(6) BIT 100 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_DACINIT BIT(5) BIT 101 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_PRLD BIT(4) BIT 102 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_STRIG BIT(3) BIT 103 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_XTRIG BIT(2) BIT 104 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_XCLK BIT(1) BIT 105 drivers/staging/comedi/drivers/dt282x.c #define DT2821_SUPCSR_BDINIT BIT(0) BIT 112 drivers/staging/comedi/drivers/dt282x.c #define DT2821_PRESCALE(x) BIT(x) BIT 72 drivers/staging/comedi/drivers/dt3000.c #define DPR_INTR_CMDONE BIT(7) BIT 73 drivers/staging/comedi/drivers/dt3000.c #define DPR_INTR_CTDONE BIT(6) BIT 74 drivers/staging/comedi/drivers/dt3000.c #define DPR_INTR_DAHWERR BIT(5) BIT 75 drivers/staging/comedi/drivers/dt3000.c #define DPR_INTR_DASWERR BIT(4) BIT 76 drivers/staging/comedi/drivers/dt3000.c #define DPR_INTR_DAEMPTY BIT(3) BIT 77 drivers/staging/comedi/drivers/dt3000.c #define DPR_INTR_ADHWERR BIT(2) BIT 78 drivers/staging/comedi/drivers/dt3000.c #define DPR_INTR_ADSWERR BIT(1) BIT 79 drivers/staging/comedi/drivers/dt3000.c #define DPR_INTR_ADFULL BIT(0) BIT 119 drivers/staging/comedi/drivers/dt3000.c #define DPR_PARAM6_AD_DIFF BIT(0) BIT 57 drivers/staging/comedi/drivers/dyna_pci10xx.c if (status & BIT(15)) BIT 46 drivers/staging/comedi/drivers/gsc_hpdi.c #define FEATURES_REG_PRESENT_BIT BIT(15) BIT 48 drivers/staging/comedi/drivers/gsc_hpdi.c #define BOARD_RESET_BIT BIT(0) BIT 49 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_FIFO_RESET_BIT BIT(1) BIT 50 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_FIFO_RESET_BIT BIT(2) BIT 51 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_ENABLE_BIT BIT(4) BIT 52 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_ENABLE_BIT BIT(5) BIT 53 drivers/staging/comedi/drivers/gsc_hpdi.c #define DEMAND_DMA_DIRECTION_TX_BIT BIT(6) /* ch 0 only */ BIT 54 drivers/staging/comedi/drivers/gsc_hpdi.c #define LINE_VALID_ON_STATUS_VALID_BIT BIT(7) BIT 55 drivers/staging/comedi/drivers/gsc_hpdi.c #define START_TX_BIT BIT(8) BIT 56 drivers/staging/comedi/drivers/gsc_hpdi.c #define CABLE_THROTTLE_ENABLE_BIT BIT(9) BIT 57 drivers/staging/comedi/drivers/gsc_hpdi.c #define TEST_MODE_ENABLE_BIT BIT(31) BIT 60 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_IN_PROGRESS_BIT BIT(7) BIT 61 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_NOT_EMPTY_BIT BIT(8) BIT 62 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_NOT_ALMOST_EMPTY_BIT BIT(9) BIT 63 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_NOT_ALMOST_FULL_BIT BIT(10) BIT 64 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_NOT_FULL_BIT BIT(11) BIT 65 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_NOT_EMPTY_BIT BIT(12) BIT 66 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_NOT_ALMOST_EMPTY_BIT BIT(13) BIT 67 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_NOT_ALMOST_FULL_BIT BIT(14) BIT 68 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_NOT_FULL_BIT BIT(15) BIT 69 drivers/staging/comedi/drivers/gsc_hpdi.c #define BOARD_JUMPER0_INSTALLED_BIT BIT(16) BIT 70 drivers/staging/comedi/drivers/gsc_hpdi.c #define BOARD_JUMPER1_INSTALLED_BIT BIT(17) BIT 71 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_OVERRUN_BIT BIT(21) BIT 72 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_UNDERRUN_BIT BIT(22) BIT 73 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_OVERRUN_BIT BIT(23) BIT 79 drivers/staging/comedi/drivers/gsc_hpdi.c #define FIFO_SIZE_PRESENT_BIT BIT(0) BIT 80 drivers/staging/comedi/drivers/gsc_hpdi.c #define FIFO_WORDS_PRESENT_BIT BIT(1) BIT 81 drivers/staging/comedi/drivers/gsc_hpdi.c #define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT BIT(2) BIT 82 drivers/staging/comedi/drivers/gsc_hpdi.c #define GPIO_SUPPORTED_BIT BIT(3) BIT 83 drivers/staging/comedi/drivers/gsc_hpdi.c #define PLX_DMA_CH1_SUPPORTED_BIT BIT(4) BIT 84 drivers/staging/comedi/drivers/gsc_hpdi.c #define OVERRUN_UNDERRUN_SUPPORTED_BIT BIT(5) BIT 92 drivers/staging/comedi/drivers/gsc_hpdi.c #define FRAME_VALID_START_INTR BIT(0) BIT 93 drivers/staging/comedi/drivers/gsc_hpdi.c #define FRAME_VALID_END_INTR BIT(1) BIT 94 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_FIFO_EMPTY_INTR BIT(8) BIT 95 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_FIFO_ALMOST_EMPTY_INTR BIT(9) BIT 96 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_FIFO_ALMOST_FULL_INTR BIT(10) BIT 97 drivers/staging/comedi/drivers/gsc_hpdi.c #define TX_FIFO_FULL_INTR BIT(11) BIT 98 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_EMPTY_INTR BIT(12) BIT 99 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_ALMOST_EMPTY_INTR BIT(13) BIT 100 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_ALMOST_FULL_INTR BIT(14) BIT 101 drivers/staging/comedi/drivers/gsc_hpdi.c #define RX_FULL_INTR BIT(15) BIT 43 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_ADC_CSR_ST BIT(0) /* Start ADC */ BIT 44 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_ADC_CSR_BSY BIT(0) /* ADC busy */ BIT 45 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_ADC_CSR_BI BIT(4) /* Bipolar input range */ BIT 46 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_ADC_CSR_RA BIT(5) /* Input range 0 = 5V, 1 = 10V */ BIT 47 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_ADC_CSR_DI BIT(6) /* Input mode 1 = differential */ BIT 52 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_DAC_CSR_ST BIT(0) /* Start DAC */ BIT 53 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_DAC_CSR_BSY BIT(0) /* DAC busy */ BIT 54 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_DAC_CSR_BI BIT(4) /* Bipolar output range */ BIT 55 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_DAC_CSR_RA BIT(5) /* Output range 0 = 5V, 1 = 10V */ BIT 62 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_INT_ADC_RDY BIT(0) /* A/D conversion ready interrupt */ BIT 63 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_INT_DAC_RDY BIT(1) /* D/A conversion ready interrupt */ BIT 64 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_INT_DOUT_ERR BIT(2) /* Digital output error interrupt */ BIT 65 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_INT_DIN_STAT BIT(3) /* Digital input status change int. */ BIT 66 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_INT_CIE0 BIT(4) /* Counter 0 overrun interrupt */ BIT 67 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_INT_CIE1 BIT(5) /* Counter 1 overrun interrupt */ BIT 68 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_INT_CIE2 BIT(6) /* Counter 2 overrun interrupt */ BIT 69 drivers/staging/comedi/drivers/icp_multi.c #define ICP_MULTI_INT_CIE3 BIT(7) /* Counter 3 overrun interrupt */ BIT 41 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_ID_MOD1_EMPTY BIT(7) BIT 42 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_ID_MOD2_EMPTY BIT(6) BIT 43 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_ID_MOD3_EMPTY BIT(5) BIT 48 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_MOD_STATUS_IRQ_MOD1 BIT(7) BIT 49 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_MOD_STATUS_IRQ_MOD2 BIT(6) BIT 50 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_MOD_STATUS_IRQ_MOD3 BIT(5) BIT 54 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_DIR_DIO3_OUT BIT(7) BIT 55 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_DIR_DIO2_OUT BIT(6) BIT 56 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_BUF_DISAB_DIO3 BIT(5) BIT 57 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_BUF_DISAB_DIO2 BIT(4) BIT 58 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_DIR_DIO1_OUT BIT(3) BIT 59 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_DIR_DIO0_OUT BIT(2) BIT 60 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_BUF_DISAB_DIO1 BIT(1) BIT 61 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_BUF_DISAB_DIO0 BIT(0) BIT 63 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_CTRL01_SET BIT(7) BIT 64 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_CTRL01_DIO0_IN BIT(4) BIT 65 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_CTRL01_DIO1_IN BIT(1) BIT 69 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_CTRL23_SET BIT(7) BIT 70 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_CTRL23_DIO2_IN BIT(4) BIT 71 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_CTRL23_DIO3_IN BIT(1) BIT 82 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_STATUS_CMD_BUSY BIT(7) BIT 83 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_STATUS_CMD_HW_ENA BIT(1) BIT 84 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_STATUS_CMD_EXT_START BIT(0) BIT 90 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_CONF_ENA BIT(2) BIT 92 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_OPT_TRIG_ENA BIT(5) BIT 93 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_OPT_TRIG_INV BIT(4) BIT 95 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_OPT_BURST_MODE BIT(0) BIT 97 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_STATUS_INT BIT(7) BIT 98 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_STATUS_TRIG BIT(6) BIT 99 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_STATUS_TRIG_ENA BIT(5) BIT 100 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_STATUS_PACER_ERR BIT(2) BIT 101 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_STATUS_DATA_ERR BIT(1) BIT 102 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_STATUS_SET_TIME_ERR BIT(0) BIT 113 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_CHANLIST_ONBOARD_ONLY BIT(5) BIT 115 drivers/staging/comedi/drivers/ii_pci20kc.c #define II20K_AI_CHANLIST_MUX_ENA BIT(2) BIT 49 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_CTRL_MODE_0 BIT(0) BIT 50 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_CTRL_MODE_1 BIT(1) BIT 51 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_CTRL_STOP BIT(2) BIT 52 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_CTRL_ENABLE_FIFO BIT(3) BIT 53 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_CTRL_ENABLE_EX_TRIG BIT(4) BIT 54 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_CTRL_EX_TRIG_EDGE BIT(5) BIT 55 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_CTRL_IMMEDIATE_STOP BIT(7) BIT 56 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_CTRL_ENABLE_DO BIT(8) BIT 57 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_CTRL_ENABLE_IRQ BIT(9) BIT 58 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_CTRL_RESET_IRQ BIT(10) BIT 60 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_STATUS_FSM BIT(0) BIT 61 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_STATUS_FF BIT(1) BIT 62 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_STATUS_HF BIT(2) BIT 63 drivers/staging/comedi/drivers/me4000.c #define ME4000_AO_STATUS_EF BIT(3) BIT 69 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_MODE_0 BIT(0) BIT 70 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_MODE_1 BIT(1) BIT 71 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_MODE_2 BIT(2) BIT 72 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_SAMPLE_HOLD BIT(3) BIT 73 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_IMMEDIATE_STOP BIT(4) BIT 74 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_STOP BIT(5) BIT 75 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_CHANNEL_FIFO BIT(6) BIT 76 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_DATA_FIFO BIT(7) BIT 77 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_FULLSCALE BIT(8) BIT 78 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_OFFSET BIT(9) BIT 79 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_EX_TRIG_ANALOG BIT(10) BIT 80 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_EX_TRIG BIT(11) BIT 81 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_EX_TRIG_FALLING BIT(12) BIT 82 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_EX_IRQ BIT(13) BIT 83 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_EX_IRQ_RESET BIT(14) BIT 84 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_LE_IRQ BIT(15) BIT 85 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_LE_IRQ_RESET BIT(16) BIT 86 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_HF_IRQ BIT(17) BIT 87 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_HF_IRQ_RESET BIT(18) BIT 88 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_SC_IRQ BIT(19) BIT 89 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_SC_IRQ_RESET BIT(20) BIT 90 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_SC_RELOAD BIT(21) BIT 91 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_STATUS_EF_CHANNEL BIT(22) BIT 92 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_STATUS_HF_CHANNEL BIT(23) BIT 93 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_STATUS_FF_CHANNEL BIT(24) BIT 94 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_STATUS_EF_DATA BIT(25) BIT 95 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_STATUS_HF_DATA BIT(26) BIT 96 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_STATUS_FF_DATA BIT(27) BIT 97 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_STATUS_LE BIT(28) BIT 98 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_STATUS_FSM BIT(29) BIT 99 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_CTRL_EX_TRIG_BOTH BIT(31) BIT 101 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_LIST_INPUT_DIFFERENTIAL BIT(5) BIT 103 drivers/staging/comedi/drivers/me4000.c #define ME4000_AI_LIST_LAST_ENTRY BIT(8) BIT 113 drivers/staging/comedi/drivers/me4000.c #define ME4000_IRQ_STATUS_EX BIT(0) BIT 114 drivers/staging/comedi/drivers/me4000.c #define ME4000_IRQ_STATUS_LE BIT(1) BIT 115 drivers/staging/comedi/drivers/me4000.c #define ME4000_IRQ_STATUS_AI_HF BIT(2) BIT 116 drivers/staging/comedi/drivers/me4000.c #define ME4000_IRQ_STATUS_AO_0_HF BIT(3) BIT 117 drivers/staging/comedi/drivers/me4000.c #define ME4000_IRQ_STATUS_AO_1_HF BIT(4) BIT 118 drivers/staging/comedi/drivers/me4000.c #define ME4000_IRQ_STATUS_AO_2_HF BIT(5) BIT 119 drivers/staging/comedi/drivers/me4000.c #define ME4000_IRQ_STATUS_AO_3_HF BIT(6) BIT 120 drivers/staging/comedi/drivers/me4000.c #define ME4000_IRQ_STATUS_SC BIT(7) BIT 128 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_MODE_0 BIT(0) BIT 129 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_MODE_1 BIT(1) BIT 130 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_MODE_2 BIT(2) BIT 131 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_MODE_3 BIT(3) BIT 132 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_MODE_4 BIT(4) BIT 133 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_MODE_5 BIT(5) BIT 134 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_MODE_6 BIT(6) BIT 135 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_MODE_7 BIT(7) BIT 136 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_FUNCTION_0 BIT(8) BIT 137 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_FUNCTION_1 BIT(9) BIT 138 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_FIFO_HIGH_0 BIT(10) BIT 139 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_FIFO_HIGH_1 BIT(11) BIT 140 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_FIFO_HIGH_2 BIT(12) BIT 141 drivers/staging/comedi/drivers/me4000.c #define ME4000_DIO_CTRL_FIFO_HIGH_3 BIT(13) BIT 39 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL1_INT_ENA BIT(15) BIT 40 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL1_COUNTER_B_IRQ BIT(12) BIT 41 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL1_COUNTER_A_IRQ BIT(11) BIT 42 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL1_CHANLIST_READY_IRQ BIT(10) BIT 43 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL1_EXT_IRQ BIT(9) BIT 44 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL1_ADFIFO_HALFFULL_IRQ BIT(8) BIT 45 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL1_SCAN_COUNT_ENA BIT(5) BIT 46 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL1_SIMULTANEOUS_ENA BIT(4) BIT 47 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL1_TRIGGER_FALLING_EDGE BIT(3) BIT 48 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL1_CONTINUOUS_MODE BIT(2) BIT 56 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL2_ADFIFO_ENA BIT(10) BIT 57 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL2_CHANLIST_ENA BIT(9) BIT 58 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL2_PORT_B_ENA BIT(7) BIT 59 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL2_PORT_A_ENA BIT(6) BIT 60 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL2_COUNTER_B_ENA BIT(4) BIT 61 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL2_COUNTER_A_ENA BIT(3) BIT 62 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL2_DAC_ENA BIT(1) BIT 63 drivers/staging/comedi/drivers/me_daq.c #define ME_CTRL2_BUFFERED_DAC BIT(0) BIT 65 drivers/staging/comedi/drivers/me_daq.c #define ME_STATUS_COUNTER_B_IRQ BIT(12) BIT 66 drivers/staging/comedi/drivers/me_daq.c #define ME_STATUS_COUNTER_A_IRQ BIT(11) BIT 67 drivers/staging/comedi/drivers/me_daq.c #define ME_STATUS_CHANLIST_READY_IRQ BIT(10) BIT 68 drivers/staging/comedi/drivers/me_daq.c #define ME_STATUS_EXT_IRQ BIT(9) BIT 69 drivers/staging/comedi/drivers/me_daq.c #define ME_STATUS_ADFIFO_HALFFULL_IRQ BIT(8) BIT 70 drivers/staging/comedi/drivers/me_daq.c #define ME_STATUS_ADFIFO_FULL BIT(4) BIT 71 drivers/staging/comedi/drivers/me_daq.c #define ME_STATUS_ADFIFO_HALFFULL BIT(3) BIT 72 drivers/staging/comedi/drivers/me_daq.c #define ME_STATUS_ADFIFO_EMPTY BIT(2) BIT 73 drivers/staging/comedi/drivers/me_daq.c #define ME_STATUS_CHANLIST_FULL BIT(1) BIT 74 drivers/staging/comedi/drivers/me_daq.c #define ME_STATUS_FST_ACTIVE BIT(0) BIT 79 drivers/staging/comedi/drivers/me_daq.c #define ME_AI_FIFO_CHANLIST_DIFF BIT(7) BIT 80 drivers/staging/comedi/drivers/me_daq.c #define ME_AI_FIFO_CHANLIST_UNIPOLAR BIT(6) BIT 84 drivers/staging/comedi/drivers/me_daq.c #define ME_DAC_CTRL_BIPOLAR(x) BIT(7 - ((x) & 0x3)) BIT 85 drivers/staging/comedi/drivers/me_daq.c #define ME_DAC_CTRL_GAIN(x) BIT(11 - ((x) & 0x3)) BIT 27 drivers/staging/comedi/drivers/mf6x4.c #define MF6X4_GPIOC_EOLC BIT(17) /* End Of Last Conversion */ BIT 28 drivers/staging/comedi/drivers/mf6x4.c #define MF6X4_GPIOC_LDAC BIT(23) /* Load DACs */ BIT 29 drivers/staging/comedi/drivers/mf6x4.c #define MF6X4_GPIOC_DACEN BIT(26) BIT 34 drivers/staging/comedi/drivers/mf6x4.c #define MF6X4_ADCTRL_CHAN(x) BIT(chan) BIT 65 drivers/staging/comedi/drivers/mite.c #define CHOR_DMARESET BIT(31) BIT 66 drivers/staging/comedi/drivers/mite.c #define CHOR_SET_SEND_TC BIT(11) BIT 67 drivers/staging/comedi/drivers/mite.c #define CHOR_CLR_SEND_TC BIT(10) BIT 68 drivers/staging/comedi/drivers/mite.c #define CHOR_SET_LPAUSE BIT(9) BIT 69 drivers/staging/comedi/drivers/mite.c #define CHOR_CLR_LPAUSE BIT(8) BIT 70 drivers/staging/comedi/drivers/mite.c #define CHOR_CLRDONE BIT(7) BIT 71 drivers/staging/comedi/drivers/mite.c #define CHOR_CLRRB BIT(6) BIT 72 drivers/staging/comedi/drivers/mite.c #define CHOR_CLRLC BIT(5) BIT 73 drivers/staging/comedi/drivers/mite.c #define CHOR_FRESET BIT(4) BIT 74 drivers/staging/comedi/drivers/mite.c #define CHOR_ABORT BIT(3) /* stop without emptying fifo */ BIT 75 drivers/staging/comedi/drivers/mite.c #define CHOR_STOP BIT(2) /* stop after emptying fifo */ BIT 76 drivers/staging/comedi/drivers/mite.c #define CHOR_CONT BIT(1) BIT 77 drivers/staging/comedi/drivers/mite.c #define CHOR_START BIT(0) BIT 79 drivers/staging/comedi/drivers/mite.c #define CHCR_SET_DMA_IE BIT(31) BIT 80 drivers/staging/comedi/drivers/mite.c #define CHCR_CLR_DMA_IE BIT(30) BIT 81 drivers/staging/comedi/drivers/mite.c #define CHCR_SET_LINKP_IE BIT(29) BIT 82 drivers/staging/comedi/drivers/mite.c #define CHCR_CLR_LINKP_IE BIT(28) BIT 83 drivers/staging/comedi/drivers/mite.c #define CHCR_SET_SAR_IE BIT(27) BIT 84 drivers/staging/comedi/drivers/mite.c #define CHCR_CLR_SAR_IE BIT(26) BIT 85 drivers/staging/comedi/drivers/mite.c #define CHCR_SET_DONE_IE BIT(25) BIT 86 drivers/staging/comedi/drivers/mite.c #define CHCR_CLR_DONE_IE BIT(24) BIT 87 drivers/staging/comedi/drivers/mite.c #define CHCR_SET_MRDY_IE BIT(23) BIT 88 drivers/staging/comedi/drivers/mite.c #define CHCR_CLR_MRDY_IE BIT(22) BIT 89 drivers/staging/comedi/drivers/mite.c #define CHCR_SET_DRDY_IE BIT(21) BIT 90 drivers/staging/comedi/drivers/mite.c #define CHCR_CLR_DRDY_IE BIT(20) BIT 91 drivers/staging/comedi/drivers/mite.c #define CHCR_SET_LC_IE BIT(19) BIT 92 drivers/staging/comedi/drivers/mite.c #define CHCR_CLR_LC_IE BIT(18) BIT 93 drivers/staging/comedi/drivers/mite.c #define CHCR_SET_CONT_RB_IE BIT(17) BIT 94 drivers/staging/comedi/drivers/mite.c #define CHCR_CLR_CONT_RB_IE BIT(16) BIT 101 drivers/staging/comedi/drivers/mite.c #define CHCR_BYTE_SWAP_DEVICE BIT(6) BIT 102 drivers/staging/comedi/drivers/mite.c #define CHCR_BYTE_SWAP_MEMORY BIT(4) BIT 116 drivers/staging/comedi/drivers/mite.c #define DCR_NORMAL BIT(29) BIT 127 drivers/staging/comedi/drivers/mite.c #define CHSR_INT BIT(31) BIT 128 drivers/staging/comedi/drivers/mite.c #define CHSR_LPAUSES BIT(29) BIT 129 drivers/staging/comedi/drivers/mite.c #define CHSR_SARS BIT(27) BIT 130 drivers/staging/comedi/drivers/mite.c #define CHSR_DONE BIT(25) BIT 131 drivers/staging/comedi/drivers/mite.c #define CHSR_MRDY BIT(23) BIT 132 drivers/staging/comedi/drivers/mite.c #define CHSR_DRDY BIT(21) BIT 133 drivers/staging/comedi/drivers/mite.c #define CHSR_LINKC BIT(19) BIT 134 drivers/staging/comedi/drivers/mite.c #define CHSR_CONTS_RB BIT(17) BIT 135 drivers/staging/comedi/drivers/mite.c #define CHSR_ERROR BIT(15) BIT 136 drivers/staging/comedi/drivers/mite.c #define CHSR_SABORT BIT(14) BIT 137 drivers/staging/comedi/drivers/mite.c #define CHSR_HABORT BIT(13) BIT 138 drivers/staging/comedi/drivers/mite.c #define CHSR_STOPS BIT(12) BIT 144 drivers/staging/comedi/drivers/mite.c #define CHSR_XFERR BIT(9) BIT 145 drivers/staging/comedi/drivers/mite.c #define CHSR_END BIT(8) BIT 146 drivers/staging/comedi/drivers/mite.c #define CHSR_DRQ1 BIT(7) BIT 147 drivers/staging/comedi/drivers/mite.c #define CHSR_DRQ0 BIT(6) BIT 183 drivers/staging/comedi/drivers/mite.c #define CR_AMDEVICE BIT(0) BIT 842 drivers/staging/comedi/drivers/mite.c wpdep = BIT(wpdep); BIT 90 drivers/staging/comedi/drivers/mite.h #define WENAB BIT(7) /* window enable */ BIT 61 drivers/staging/comedi/drivers/mpc624.c #define MPC624_ADBUSY BIT(5) BIT 62 drivers/staging/comedi/drivers/mpc624.c #define MPC624_ADSDO BIT(4) BIT 63 drivers/staging/comedi/drivers/mpc624.c #define MPC624_ADFO BIT(3) BIT 64 drivers/staging/comedi/drivers/mpc624.c #define MPC624_ADCS BIT(2) BIT 65 drivers/staging/comedi/drivers/mpc624.c #define MPC624_ADSCK BIT(1) BIT 66 drivers/staging/comedi/drivers/mpc624.c #define MPC624_ADSDI BIT(0) BIT 69 drivers/staging/comedi/drivers/mpc624.c #define MPC624_EOC_BIT BIT(31) BIT 70 drivers/staging/comedi/drivers/mpc624.c #define MPC624_DMY_BIT BIT(30) BIT 71 drivers/staging/comedi/drivers/mpc624.c #define MPC624_SGN_BIT BIT(29) BIT 126 drivers/staging/comedi/drivers/mpc624.c bit = (data_out & BIT(31)) ? MPC624_ADSDI : 0; BIT 41 drivers/staging/comedi/drivers/multiq3.c #define MULTIQ3_STATUS_EOC BIT(3) BIT 42 drivers/staging/comedi/drivers/multiq3.c #define MULTIQ3_STATUS_EOC_I BIT(4) BIT 48 drivers/staging/comedi/drivers/multiq3.c #define MULTIQ3_CTRL_EN BIT(6) BIT 49 drivers/staging/comedi/drivers/multiq3.c #define MULTIQ3_CTRL_AZ BIT(7) BIT 50 drivers/staging/comedi/drivers/multiq3.c #define MULTIQ3_CTRL_CAL BIT(8) BIT 51 drivers/staging/comedi/drivers/multiq3.c #define MULTIQ3_CTRL_SH BIT(9) BIT 52 drivers/staging/comedi/drivers/multiq3.c #define MULTIQ3_CTRL_CLK BIT(10) BIT 36 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_CLR_EDGE BIT(3) BIT 37 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_CLR_OVERFLOW BIT(2) BIT 38 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_CLR_FILT BIT(1) BIT 39 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_CLR_INTERVAL BIT(0) BIT 45 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_STATUS_IRQ BIT(2) BIT 46 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_STATUS_OVERFLOW BIT(1) BIT 47 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_STATUS_EDGE BIT(0) BIT 49 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_CTRL_FALLING BIT(4) BIT 50 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_CTRL_RISING BIT(3) BIT 51 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_CTRL_IRQ BIT(2) BIT 52 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_CTRL_OVERFLOW BIT(1) BIT 53 drivers/staging/comedi/drivers/ni_6527.c #define NI6527_CTRL_EDGE BIT(0) BIT 62 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CLR_WDOG_INT BIT(6) BIT 63 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CLR_WDOG_PING BIT(5) BIT 64 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CLR_WDOG_EXP BIT(4) BIT 65 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CLR_EDGE_INT BIT(3) BIT 66 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CLR_OVERFLOW_INT BIT(2) BIT 68 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_STATUS_WDOG_INT BIT(5) BIT 69 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_STATUS_FALL_EDGE BIT(4) BIT 70 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_STATUS_RISE_EDGE BIT(3) BIT 71 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_STATUS_INT BIT(2) BIT 72 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_STATUS_OVERFLOW_INT BIT(1) BIT 73 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_STATUS_EDGE_INT BIT(0) BIT 75 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CTRL_WDOG_ENA BIT(5) BIT 76 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CTRL_FALL_EDGE_ENA BIT(4) BIT 77 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CTRL_RISE_EDGE_ENA BIT(3) BIT 78 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CTRL_INT_ENA BIT(2) BIT 79 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CTRL_OVERFLOW_ENA BIT(1) BIT 80 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_CTRL_EDGE_ENA BIT(0) BIT 88 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_AUTO_CLK_SEL_STATUS BIT(1) BIT 89 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_AUTO_CLK_SEL_DISABLE BIT(0) BIT 91 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_WDOG_CTRL_ENA BIT(0) BIT 93 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_RTSI_CFG_RISE_SENSE BIT(2) BIT 94 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_RTSI_CFG_FALL_SENSE BIT(1) BIT 95 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_RTSI_CFG_SYNC_DETECT BIT(0) BIT 97 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_WDOG_STATUS_EXP BIT(0) BIT 105 drivers/staging/comedi/drivers/ni_65xx.c #define NI_65XX_IO_SEL_INPUT BIT(0) BIT 607 drivers/staging/comedi/drivers/ni_65xx.c #define WENAB BIT(7) /* window enable */ BIT 72 drivers/staging/comedi/drivers/ni_660x.c #define NI660X_CLK_CFG_COUNTER_SWAP BIT(21) BIT 74 drivers/staging/comedi/drivers/ni_660x.c #define NI660X_GLOBAL_INT_COUNTER0 BIT(8) BIT 75 drivers/staging/comedi/drivers/ni_660x.c #define NI660X_GLOBAL_INT_COUNTER1 BIT(9) BIT 76 drivers/staging/comedi/drivers/ni_660x.c #define NI660X_GLOBAL_INT_COUNTER2 BIT(10) BIT 77 drivers/staging/comedi/drivers/ni_660x.c #define NI660X_GLOBAL_INT_COUNTER3 BIT(11) BIT 78 drivers/staging/comedi/drivers/ni_660x.c #define NI660X_GLOBAL_INT_CASCADE BIT(29) BIT 79 drivers/staging/comedi/drivers/ni_660x.c #define NI660X_GLOBAL_INT_GLOBAL_POL BIT(30) BIT 80 drivers/staging/comedi/drivers/ni_660x.c #define NI660X_GLOBAL_INT_GLOBAL BIT(31) BIT 135 drivers/staging/comedi/drivers/ni_670x.c #define WENAB BIT(7) /* window enable */ BIT 43 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG2_FFRTEN BIT(13) BIT 46 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG2_PROMEN BIT(2) BIT 47 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG2_SCLK BIT(1) BIT 48 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG2_SDATA BIT(0) BIT 50 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG3_DMAMODE BIT(6) BIT 51 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG3_CLKOUT BIT(5) BIT 52 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG3_RCLKEN BIT(4) BIT 53 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG3_DOUTEN2 BIT(3) BIT 54 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG3_DOUTEN1 BIT(2) BIT 55 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG3_EN2_5V BIT(1) BIT 56 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG3_SCANEN BIT(0) BIT 59 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_EXTINT2EN BIT(15) BIT 60 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_EXTINT1EN BIT(14) BIT 61 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_CNTINT2EN BIT(13) BIT 62 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_CNTINT1EN BIT(12) BIT 63 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_TCINTEN BIT(11) BIT 64 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_CNT1SRC BIT(10) BIT 65 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_CNT2SRC BIT(9) BIT 66 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_FIFOEN BIT(8) BIT 67 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_GRP2WR BIT(7) BIT 68 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_EXTUPDEN BIT(6) BIT 69 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_DMARQ BIT(5) BIT 70 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_CFG1_DMAEN BIT(4) BIT 73 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_STATUS_FH BIT(6) BIT 74 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_STATUS_FE BIT(5) BIT 75 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_STATUS_FF BIT(4) BIT 76 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_STATUS_INT2 BIT(3) BIT 77 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_STATUS_INT1 BIT(2) BIT 78 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_STATUS_TCINT BIT(1) BIT 79 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_STATUS_PROMOUT BIT(0) BIT 89 drivers/staging/comedi/drivers/ni_at_ao.c #define ATAO_2_RTSISHFT_RSI BIT(0) BIT 247 drivers/staging/comedi/drivers/ni_at_ao.c for (bit = BIT(10); bit; bit >>= 1) { BIT 242 drivers/staging/comedi/drivers/ni_daq_700.c s->maxdata = BIT(12) - 1; BIT 46 drivers/staging/comedi/drivers/ni_labpc_pci.c #define WENAB BIT(7) /* window enable */ BIT 13 drivers/staging/comedi/drivers/ni_labpc_regs.h #define STAT1_DAVAIL BIT(0) BIT 14 drivers/staging/comedi/drivers/ni_labpc_regs.h #define STAT1_OVERRUN BIT(1) BIT 15 drivers/staging/comedi/drivers/ni_labpc_regs.h #define STAT1_OVERFLOW BIT(2) BIT 16 drivers/staging/comedi/drivers/ni_labpc_regs.h #define STAT1_CNTINT BIT(3) BIT 17 drivers/staging/comedi/drivers/ni_labpc_regs.h #define STAT1_GATA0 BIT(5) BIT 18 drivers/staging/comedi/drivers/ni_labpc_regs.h #define STAT1_EXTGATA0 BIT(6) BIT 21 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD1_TWOSCMP BIT(3) BIT 23 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD1_SCANEN BIT(7) BIT 25 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD2_PRETRIG BIT(0) BIT 26 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD2_HWTRIG BIT(1) BIT 27 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD2_SWTRIG BIT(2) BIT 28 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD2_TBSEL BIT(3) BIT 29 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD2_2SDAC0 BIT(4) BIT 30 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD2_2SDAC1 BIT(5) BIT 31 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD2_LDAC(x) BIT(6 + ((x) & 0x1)) BIT 33 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD3_DMAEN BIT(0) BIT 34 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD3_DIOINTEN BIT(1) BIT 35 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD3_DMATCINTEN BIT(2) BIT 36 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD3_CNTINTEN BIT(3) BIT 37 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD3_ERRINTEN BIT(4) BIT 38 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD3_FIFOINTEN BIT(5) BIT 47 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD6_NRSE BIT(0) BIT 48 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD6_ADCUNI BIT(1) BIT 49 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD6_DACUNI(x) BIT(2 + ((x) & 0x1)) BIT 50 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD6_HFINTEN BIT(5) BIT 51 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD6_DQINTEN BIT(6) BIT 52 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD6_SCANUP BIT(7) BIT 54 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD4_INTSCAN BIT(0) BIT 55 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD4_EOIRCV BIT(1) BIT 56 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD4_ECLKDRV BIT(2) BIT 57 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD4_SEDIFF BIT(3) BIT 58 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD4_ECLKRCV BIT(4) BIT 63 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD5_WRTPRT BIT(2) BIT 64 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD5_DITHEREN BIT(3) BIT 65 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD5_CALDACLD BIT(4) BIT 66 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD5_SCLK BIT(5) BIT 67 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD5_SDATA BIT(6) BIT 68 drivers/staging/comedi/drivers/ni_labpc_regs.h #define CMD5_EEPROMCS BIT(7) BIT 70 drivers/staging/comedi/drivers/ni_labpc_regs.h #define STAT2_PROMOUT BIT(0) BIT 71 drivers/staging/comedi/drivers/ni_labpc_regs.h #define STAT2_OUTA1 BIT(1) BIT 72 drivers/staging/comedi/drivers/ni_labpc_regs.h #define STAT2_FIFONHF BIT(2) BIT 556 drivers/staging/comedi/drivers/ni_mio_common.c #define NI_STC_DMA_CHAN_SEL(x) (((x) < 4) ? BIT(x) : \ BIT 4802 drivers/staging/comedi/drivers/ni_mio_common.c *data ^= BIT(15); BIT 6211 drivers/staging/comedi/drivers/ni_mio_common.c s->maxdata = BIT(16) - 1; BIT 54 drivers/staging/comedi/drivers/ni_pcidio.c #define INT_STATUS_1 BIT(0) BIT 55 drivers/staging/comedi/drivers/ni_pcidio.c #define INT_STATUS_2 BIT(1) BIT 60 drivers/staging/comedi/drivers/ni_pcidio.c #define OPEN_INT BIT(2) BIT 62 drivers/staging/comedi/drivers/ni_pcidio.c #define DATA_LEFT BIT(0) BIT 63 drivers/staging/comedi/drivers/ni_pcidio.c #define REQ BIT(2) BIT 64 drivers/staging/comedi/drivers/ni_pcidio.c #define STOP_TRIG BIT(3) BIT 68 drivers/staging/comedi/drivers/ni_pcidio.c #define TRANSFER_READY BIT(0) BIT 69 drivers/staging/comedi/drivers/ni_pcidio.c #define COUNT_EXPIRED BIT(1) BIT 70 drivers/staging/comedi/drivers/ni_pcidio.c #define WAITED BIT(5) BIT 71 drivers/staging/comedi/drivers/ni_pcidio.c #define PRIMARY_TC BIT(6) BIT 72 drivers/staging/comedi/drivers/ni_pcidio.c #define SECONDARY_TC BIT(7) BIT 79 drivers/staging/comedi/drivers/ni_pcidio.c #define CLEAR_WAITED BIT(3) BIT 80 drivers/staging/comedi/drivers/ni_pcidio.c #define CLEAR_PRIMARY_TC BIT(4) BIT 81 drivers/staging/comedi/drivers/ni_pcidio.c #define CLEAR_SECONDARY_TC BIT(5) BIT 82 drivers/staging/comedi/drivers/ni_pcidio.c #define DMA_RESET BIT(6) BIT 83 drivers/staging/comedi/drivers/ni_pcidio.c #define FIFO_RESET BIT(7) BIT 104 drivers/staging/comedi/drivers/ni_pcidio.c #define CLEAR_EXPIRED BIT(0) BIT 109 drivers/staging/comedi/drivers/ni_pcidio.c #define FIFO_ENABLE_A BIT(0) BIT 110 drivers/staging/comedi/drivers/ni_pcidio.c #define FIFO_ENABLE_B BIT(1) BIT 111 drivers/staging/comedi/drivers/ni_pcidio.c #define FIFO_ENABLE_C BIT(2) BIT 112 drivers/staging/comedi/drivers/ni_pcidio.c #define FIFO_ENABLE_D BIT(3) BIT 114 drivers/staging/comedi/drivers/ni_pcidio.c #define GROUP_DIRECTION BIT(7) BIT 119 drivers/staging/comedi/drivers/ni_pcidio.c #define NUMBERED BIT(3) BIT 124 drivers/staging/comedi/drivers/ni_pcidio.c #define INVERT_STOP_TRIG BIT(7) BIT 145 drivers/staging/comedi/drivers/ni_pcidio.c #define INVERT_ACK BIT(0) BIT 146 drivers/staging/comedi/drivers/ni_pcidio.c #define INVERT_REQ BIT(1) BIT 147 drivers/staging/comedi/drivers/ni_pcidio.c #define INVERT_CLOCK BIT(2) BIT 148 drivers/staging/comedi/drivers/ni_pcidio.c #define INVERT_SERIAL BIT(3) BIT 149 drivers/staging/comedi/drivers/ni_pcidio.c #define OPEN_ACK BIT(4) BIT 150 drivers/staging/comedi/drivers/ni_pcidio.c #define OPEN_CLOCK BIT(5) BIT 155 drivers/staging/comedi/drivers/ni_pcidio.c #define EXCHANGE_PINS BIT(7) BIT 177 drivers/staging/comedi/drivers/ni_pcidio.c #define REQUIRE_R_LEVEL BIT(5) BIT 182 drivers/staging/comedi/drivers/ni_pcidio.c #define INVERT_START BIT(2) BIT 184 drivers/staging/comedi/drivers/ni_pcidio.c #define REQ_START BIT(6) BIT 185 drivers/staging/comedi/drivers/ni_pcidio.c #define PRE_START BIT(7) BIT 188 drivers/staging/comedi/drivers/ni_pcidio.c #define DETECTION_METHOD BIT(0) BIT 189 drivers/staging/comedi/drivers/ni_pcidio.c #define INVERT_MATCH BIT(1) BIT 190 drivers/staging/comedi/drivers/ni_pcidio.c #define IE_PATTERN_DETECTION BIT(2) BIT 461 drivers/staging/comedi/drivers/ni_routes.c regval = BIT(6); BIT 137 drivers/staging/comedi/drivers/ni_routes.h return value & BIT(6); BIT 25 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_G0_GATE BIT(15) BIT 26 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_G0_TC BIT(14) BIT 27 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_AI_ERR BIT(13) BIT 28 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_AI_STOP BIT(12) BIT 29 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_AI_START BIT(11) BIT 30 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_AI_START2 BIT(10) BIT 31 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_AI_START1 BIT(9) BIT 32 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_AI_SC_TC BIT(8) BIT 33 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7) BIT 34 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_G0_TC_ERR BIT(6) BIT 35 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ACK_G0_GATE_ERR BIT(5) BIT 45 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_G1_GATE BIT(15) BIT 46 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_G1_TC BIT(14) BIT 47 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_ERR BIT(13) BIT 48 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_STOP BIT(12) BIT 49 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_START BIT(11) BIT 50 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_UPDATE BIT(10) BIT 51 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_START1 BIT(9) BIT 52 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_BC_TC BIT(8) BIT 53 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_UC_TC BIT(7) BIT 54 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_UI2_TC BIT(6) BIT 55 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_UI2_TC_ERR BIT(5) BIT 56 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_BC_TC_ERR BIT(4) BIT 57 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR BIT(3) BIT 58 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_G1_TC_ERR BIT(2) BIT 59 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ACK_G1_GATE_ERR BIT(1) BIT 71 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_END_ON_SC_TC BIT(15) BIT 72 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_END_ON_EOS BIT(14) BIT 73 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_START1_DISABLE BIT(11) BIT 74 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_SC_SAVE_TRACE BIT(10) BIT 75 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_SI_SW_ON_SC_TC BIT(9) BIT 76 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_SI_SW_ON_STOP BIT(8) BIT 77 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_SI_SW_ON_TC BIT(7) BIT 78 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_SC_SW_ON_TC BIT(4) BIT 79 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_STOP_PULSE BIT(3) BIT 80 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_START_PULSE BIT(2) BIT 81 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_START2_PULSE BIT(1) BIT 82 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD2_START1_PULSE BIT(0) BIT 86 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_START_STOP_GATE_ENA BIT(13) BIT 87 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_UC_SAVE_TRACE BIT(12) BIT 88 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_BC_GATE_ENA BIT(11) BIT 89 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_BC_SAVE_TRACE BIT(10) BIT 90 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_UI_SW_ON_BC_TC BIT(9) BIT 91 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_UI_SW_ON_STOP BIT(8) BIT 92 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_UI_SW_ON_TC BIT(7) BIT 93 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_UC_SW_ON_BC_TC BIT(6) BIT 94 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_UC_SW_ON_TC BIT(5) BIT 95 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_BC_SW_ON_TC BIT(4) BIT 96 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_MUTE_B BIT(3) BIT 97 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_MUTE_A BIT(2) BIT 98 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_UPDATE2_PULSE BIT(1) BIT 99 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD2_START1_PULSE BIT(0) BIT 105 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_ATRIG_RESET BIT(14) BIT 106 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_DISARM BIT(13) BIT 107 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_SI2_ARM BIT(12) BIT 108 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_SI2_LOAD BIT(11) BIT 109 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_SI_ARM BIT(10) BIT 110 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_SI_LOAD BIT(9) BIT 111 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_DIV_ARM BIT(8) BIT 112 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_DIV_LOAD BIT(7) BIT 113 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_SC_ARM BIT(6) BIT 114 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_SC_LOAD BIT(5) BIT 115 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_SCAN_IN_PROG_PULSE BIT(4) BIT 116 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_EXTMUX_CLK_PULSE BIT(3) BIT 117 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_LOCALMUX_CLK_PULSE BIT(2) BIT 118 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_SC_TC_PULSE BIT(1) BIT 119 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_CMD1_CONVERT_PULSE BIT(0) BIT 122 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_ATRIG_RESET BIT(15) BIT 123 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_START_PULSE BIT(14) BIT 124 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_DISARM BIT(13) BIT 125 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_UI2_ARM_DISARM BIT(12) BIT 126 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_UI2_LOAD BIT(11) BIT 127 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_UI_ARM BIT(10) BIT 128 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_UI_LOAD BIT(9) BIT 129 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_UC_ARM BIT(8) BIT 130 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_UC_LOAD BIT(7) BIT 131 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_BC_ARM BIT(6) BIT 132 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_BC_LOAD BIT(5) BIT 133 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_DAC1_UPDATE_MODE BIT(4) BIT 134 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_LDAC1_SRC_SEL BIT(3) BIT 135 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_DAC0_UPDATE_MODE BIT(2) BIT 136 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_LDAC0_SRC_SEL BIT(1) BIT 137 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_CMD1_UPDATE_PULSE BIT(0) BIT 144 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_DIO_SDIN BIT(4) BIT 145 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_DIO_SDOUT BIT(0) BIT 148 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_DIO_SDCLK BIT(11) BIT 149 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_DIO_CTRL_HW_SER_TIMEBASE BIT(10) BIT 150 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_DIO_CTRL_HW_SER_ENA BIT(9) BIT 151 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_DIO_CTRL_HW_SER_START BIT(8) BIT 158 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE1_CONVERT_POLARITY BIT(5) BIT 159 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE1_SI_POLARITY BIT(4) BIT 160 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE1_START_STOP BIT(3) BIT 161 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE1_RSVD BIT(2) BIT 162 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE1_CONTINUOUS BIT(1) BIT 163 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE1_TRIGGER_ONCE BIT(0) BIT 166 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_SC_GATE_ENA BIT(15) BIT 167 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_START_STOP_GATE_ENA BIT(14) BIT 168 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_PRE_TRIGGER BIT(13) BIT 169 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_EXTMUX_PRESENT BIT(12) BIT 170 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_SI2_INIT_LOAD_SRC BIT(9) BIT 171 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_SI2_RELOAD_MODE BIT(8) BIT 172 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_SI_INIT_LOAD_SRC BIT(7) BIT 174 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_SI_WR_SWITCH BIT(3) BIT 175 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_SC_INIT_LOAD_SRC BIT(2) BIT 176 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_SC_RELOAD_MODE BIT(1) BIT 177 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE2_SC_WR_SWITCH BIT(0) BIT 200 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE1_MULTI_CHAN BIT(5) BIT 201 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE1_UPDATE_SRC_POLARITY BIT(4) BIT 202 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE1_UI_SRC_POLARITY BIT(3) BIT 203 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE1_UC_SW_EVERY_TC BIT(2) BIT 204 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE1_CONTINUOUS BIT(1) BIT 205 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE1_TRIGGER_ONCE BIT(0) BIT 214 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_FIFO_REXMIT_ENA BIT(13) BIT 215 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_START1_DISABLE BIT(12) BIT 216 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_UC_INIT_LOAD_SRC BIT(11) BIT 217 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_UC_WR_SWITCH BIT(10) BIT 218 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_UI2_INIT_LOAD_SRC BIT(9) BIT 219 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_UI2_RELOAD_MODE BIT(8) BIT 220 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_UI_INIT_LOAD_SRC BIT(7) BIT 222 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_UI_WR_SWITCH BIT(3) BIT 223 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_BC_INIT_LOAD_SRC BIT(2) BIT 224 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_BC_RELOAD_MODE BIT(1) BIT 225 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE2_BC_WR_SWITCH BIT(0) BIT 235 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_ENA BIT(15) BIT 236 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_TIMEBASE_SEL BIT(14) BIT 237 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 BIT(13) BIT 238 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_SLOW_DIV2 BIT(12) BIT 239 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_SLOW_TIMEBASE BIT(11) BIT 240 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_G_SRC_DIV2 BIT(10) BIT 241 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_TO_BOARD_DIV2 BIT(9) BIT 242 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_TO_BOARD BIT(8) BIT 243 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_AI_OUT_DIV2 BIT(7) BIT 244 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_AI_SRC_DIV2 BIT(6) BIT 245 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_AO_OUT_DIV2 BIT(5) BIT 246 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_CLK_FOUT_AO_SRC_DIV2 BIT(4) BIT 256 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c))) BIT 257 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RTSI_TRIG_DIR_SUB_SEL1 BIT(2) /* only for M-Series */ BIT 259 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RTSI_TRIG_USE_CLK BIT(1) BIT 260 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RTSI_TRIG_DRV_CLK BIT(0) BIT 263 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INT_CTRL_INTB_ENA BIT(15) BIT 265 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INT_CTRL_INTA_ENA BIT(11) BIT 267 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INT_CTRL_PASSTHRU0_POL BIT(3) BIT 268 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INT_CTRL_PASSTHRU1_POL BIT(2) BIT 269 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INT_CTRL_3PIN_INT BIT(1) BIT 270 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INT_CTRL_INT_POL BIT(0) BIT 273 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_OUT_CTRL_START_SEL BIT(10) BIT 285 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_ATRIG_ETC_GPFO_1_ENA BIT(15) BIT 286 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_ATRIG_ETC_GPFO_0_ENA BIT(14) BIT 289 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_ATRIG_ETC_GPFO_1_SEL BIT(7) BIT 291 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_ATRIG_ETC_DRV BIT(4) BIT 292 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_ATRIG_ETC_ENA BIT(3) BIT 298 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_START_POLARITY BIT(15) BIT 299 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STOP_POLARITY BIT(14) BIT 300 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STOP_SYNC BIT(13) BIT 301 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STOP_EDGE BIT(12) BIT 303 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_START_SYNC BIT(6) BIT 304 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_START_EDGE BIT(5) BIT 308 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_TRIG_START1_POLARITY BIT(15) BIT 309 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_TRIG_START2_POLARITY BIT(14) BIT 310 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_TRIG_START2_SYNC BIT(13) BIT 311 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_TRIG_START2_EDGE BIT(12) BIT 313 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_TRIG_START1_SYNC BIT(6) BIT 314 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_TRIG_START1_EDGE BIT(5) BIT 320 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_START_UI2_SW_GATE BIT(15) BIT 321 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_START_UI2_EXT_GATE_POL BIT(14) BIT 322 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_START_POLARITY BIT(13) BIT 323 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_START_AOFREQ_ENA BIT(12) BIT 325 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_START_SYNC BIT(6) BIT 326 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_START_EDGE BIT(5) BIT 330 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_TRIG_UI2_EXT_GATE_ENA BIT(15) BIT 331 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_TRIG_DELAYED_START1 BIT(14) BIT 332 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_TRIG_START1_POLARITY BIT(13) BIT 333 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_TRIG_UI2_SRC_POLARITY BIT(12) BIT 335 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_TRIG_START1_SYNC BIT(6) BIT 336 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_TRIG_START1_EDGE BIT(5) BIT 344 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE3_UI2_SW_NEXT_TC BIT(13) BIT 345 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE3_UC_SW_EVERY_BC_TC BIT(12) BIT 346 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE3_TRIG_LEN BIT(11) BIT 347 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR BIT(5) BIT 348 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR BIT(4) BIT 349 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE3_STOP_ON_BC_TC_ERR BIT(3) BIT 350 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE3_NOT_AN_UPDATE BIT(2) BIT 351 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE3_SW_GATE BIT(1) BIT 352 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_MODE3_LAST_GATE_DISABLE BIT(0) /* M-Series only */ BIT 355 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RESET_SOFTWARE BIT(11) BIT 356 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RESET_AO_CFG_END BIT(9) BIT 357 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RESET_AI_CFG_END BIT(8) BIT 358 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RESET_AO_CFG_START BIT(5) BIT 359 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RESET_AI_CFG_START BIT(4) BIT 360 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RESET_G1 BIT(3) BIT 361 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RESET_G0 BIT(2) BIT 362 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RESET_AO BIT(1) BIT 363 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RESET_AI BIT(0) BIT 367 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ENA_PASSTHRU0 BIT(9) BIT 368 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ENA_G0_GATE BIT(8) BIT 369 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ENA_AI_FIFO BIT(7) BIT 370 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ENA_G0_TC BIT(6) BIT 371 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ENA_AI_ERR BIT(5) BIT 372 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ENA_AI_STOP BIT(4) BIT 373 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ENA_AI_START BIT(3) BIT 374 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ENA_AI_START2 BIT(2) BIT 375 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ENA_AI_START1 BIT(1) BIT 376 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTA_ENA_AI_SC_TC BIT(0) BIT 387 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_PASSTHRU1 BIT(11) BIT 388 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_G1_GATE BIT(10) BIT 389 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_G1_TC BIT(9) BIT 390 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_AO_FIFO BIT(8) BIT 391 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_AO_UI2_TC BIT(7) BIT 392 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_AO_UC_TC BIT(6) BIT 393 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_AO_ERR BIT(5) BIT 394 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_AO_STOP BIT(4) BIT 395 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_AO_START BIT(3) BIT 396 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_AO_UPDATE BIT(2) BIT 397 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_AO_START1 BIT(1) BIT 398 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_INTB_ENA_AO_BC_TC BIT(0) BIT 401 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_SHIFTIN_PW BIT(15) BIT 402 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_EOC_POLARITY BIT(14) BIT 403 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_SOC_POLARITY BIT(13) BIT 404 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_SHIFTIN_POL BIT(12) BIT 405 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_CONVERT_TIMEBASE BIT(11) BIT 406 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_CONVERT_PW BIT(10) BIT 407 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_CONVERT_ORIG_PULSE BIT(9) BIT 408 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_FIFO_FLAGS_POL BIT(8) BIT 409 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_OVERRUN_MODE BIT(7) BIT 410 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_EXTMUX_CLK_PW BIT(6) BIT 411 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_LOCALMUX_CLK_PW BIT(5) BIT 412 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_PERSONAL_AIFREQ_POL BIT(4) BIT 415 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_MULTI_DACS BIT(15) /* M-Series only */ BIT 416 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_NUM_DAC BIT(14) /* 1:single; 0:dual */ BIT 417 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_FAST_CPU BIT(13) /* M-Series reserved */ BIT 418 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_TMRDACWR_PW BIT(12) BIT 419 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_FIFO_FLAGS_POL BIT(11) /* M-Series reserved */ BIT 420 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_FIFO_ENA BIT(10) BIT 421 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_AOFREQ_POL BIT(9) /* M-Series reserved */ BIT 422 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_DMA_PIO_CTRL BIT(8) /* M-Series reserved */ BIT 423 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_UPDATE_ORIG_PULSE BIT(7) BIT 424 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_UPDATE_TIMEBASE BIT(6) BIT 425 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_UPDATE_PW BIT(5) BIT 426 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_BC_SRC_SEL BIT(4) BIT 427 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_PERSONAL_INTERVAL_BUFFER_MODE BIT(3) BIT 431 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_RTSI_TRIGB_SUB_SEL1 BIT(15) /* not for M-Series */ BIT 445 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_OUT_CTRL_EXT_GATE_ENA BIT(15) BIT 449 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_OUT_CTRL_EXT_GATE_POL BIT(3) BIT 450 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_OUT_CTRL_UPDATE2_TOGGLE BIT(2) BIT 458 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE3_TRIG_LEN BIT(15) BIT 459 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE3_DELAY_START BIT(14) BIT 460 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE3_SOFTWARE_GATE BIT(13) BIT 461 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE3_SI_TRIG_DELAY BIT(12) BIT 462 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE3_SI2_SRC_SEL BIT(11) BIT 463 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE3_DELAYED_START2 BIT(10) BIT 464 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE3_DELAYED_START1 BIT(9) BIT 465 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE3_EXT_GATE_MODE BIT(8) BIT 471 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_MODE3_EXT_GATE_POL BIT(5) BIT 475 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_INTA BIT(15) BIT 476 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_FIFO_F BIT(14) BIT 477 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_FIFO_HF BIT(13) BIT 478 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_FIFO_E BIT(12) BIT 479 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_OVERRUN BIT(11) BIT 480 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_OVERFLOW BIT(10) BIT 481 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_SC_TC_ERR BIT(9) BIT 486 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_START2 BIT(8) BIT 487 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_START1 BIT(7) BIT 488 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_SC_TC BIT(6) BIT 489 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_START BIT(5) BIT 490 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_STOP BIT(4) BIT 491 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_G0_TC BIT(3) BIT 492 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_G0_GATE BIT(2) BIT 493 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_FIFO_REQ BIT(1) BIT 494 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AI_STATUS1_PASSTHRU0 BIT(0) BIT 497 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_INTB BIT(15) BIT 498 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_FIFO_F BIT(14) BIT 499 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_FIFO_HF BIT(13) BIT 500 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_FIFO_E BIT(12) BIT 501 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_BC_TC_ERR BIT(11) BIT 502 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_START BIT(10) BIT 503 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_OVERRUN BIT(9) BIT 504 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_START1 BIT(8) BIT 505 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_BC_TC BIT(7) BIT 506 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_UC_TC BIT(6) BIT 507 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_UPDATE BIT(5) BIT 508 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_UI2_TC BIT(4) BIT 509 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_G1_TC BIT(3) BIT 510 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_G1_GATE BIT(2) BIT 511 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_FIFO_REQ BIT(1) BIT 512 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_AO_STATUS1_PASSTHRU1 BIT(0) BIT 533 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_STATUS1_SERIO_IN_PROG BIT(12) BIT 538 drivers/staging/comedi/drivers/ni_stc.h #define NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS BIT(5) BIT 550 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_STATUS_AI_FIFO_LOWER_NE BIT(3) BIT 551 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_STATUS_PROMOUT BIT(0) BIT 564 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_SERIAL_CMD_DAC_LD(x) BIT(3 + (x)) BIT 565 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_SERIAL_CMD_EEPROM_CS BIT(2) BIT 566 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_SERIAL_CMD_SDATA BIT(1) BIT 567 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_SERIAL_CMD_SCLK BIT(0) BIT 575 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_AI_CFG_LO_LAST_CHAN BIT(15) BIT 576 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_AI_CFG_LO_GEN_TRIG BIT(12) BIT 577 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_AI_CFG_LO_DITHER BIT(9) BIT 578 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_AI_CFG_LO_UNI BIT(8) BIT 586 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_AI_CFG_HI_AC_COUPLE BIT(11) BIT 591 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_AO_GROUND_REF BIT(3) BIT 592 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_AO_EXT_REF BIT(2) BIT 593 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_AO_DEGLITCH BIT(1) BIT 594 drivers/staging/comedi/drivers/ni_stc.h #define NI_E_AO_CFG_BIP BIT(0) BIT 633 drivers/staging/comedi/drivers/ni_stc.h #define NI6143_CALIB_CHAN_RELAY_ON BIT(15) BIT 634 drivers/staging/comedi/drivers/ni_stc.h #define NI6143_CALIB_CHAN_RELAY_OFF BIT(14) BIT 659 drivers/staging/comedi/drivers/ni_stc.h #define NI611X_AO_MISC_CLEAR_WG BIT(0) BIT 664 drivers/staging/comedi/drivers/ni_stc.h #define NI67XX_CAL_STATUS_BUSY BIT(0) BIT 665 drivers/staging/comedi/drivers/ni_stc.h #define NI67XX_CAL_STATUS_OSC_DETECT BIT(1) BIT 666 drivers/staging/comedi/drivers/ni_stc.h #define NI67XX_CAL_STATUS_OVERRANGE BIT(2) BIT 671 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CMD_CB BIT(7) BIT 672 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CMD_SINGLE_CONV BIT(6) BIT 673 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CMD_CONT_CONV BIT(5) BIT 674 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CMD_READ BIT(4) BIT 677 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CMD_PWR_SAVE BIT(0) BIT 685 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CFG_AOUT(x) BIT(22 + (x)) BIT 686 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CFG_DOUT(x) BIT(18 + (x)) BIT 687 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CFG_LOW_PWR_MODE BIT(16) BIT 698 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CFG_UNIPOLAR BIT(12) BIT 699 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CFG_RESET BIT(7) BIT 700 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CFG_RESET_VALID BIT(6) BIT 701 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CFG_PORT_FLAG BIT(5) BIT 702 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CFG_PWR_SAVE_SEL BIT(4) BIT 703 drivers/staging/comedi/drivers/ni_stc.h #define CS5529_CFG_DONE_FLAG BIT(3) BIT 736 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_AI_CFG_LAST_CHAN BIT(14) BIT 737 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_AI_CFG_DITHER BIT(13) BIT 738 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_AI_CFG_POLARITY BIT(12) BIT 751 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_INTC_ENA BIT(0) BIT 753 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_INTC_STATUS BIT(0) BIT 768 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_AO_CFG_BANK_BIPOLAR BIT(7) BIT 769 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_AO_CFG_BANK_UPDATE_TIMED BIT(6) BIT 780 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CLK_FOUT2_RTSI_10MHZ BIT(7) BIT 781 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CLK_FOUT2_TIMEBASE3_PLL BIT(6) BIT 782 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CLK_FOUT2_TIMEBASE1_PLL BIT(5) BIT 797 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_PLL_CTRL_ENA BIT(12) BIT 803 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_PLL_STATUS_LOCKED BIT(0) BIT 812 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CFG_BYPASS_FIFO BIT(31) BIT 813 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CFG_BYPASS_AI_POLARITY BIT(22) BIT 814 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CFG_BYPASS_AI_DITHER BIT(21) BIT 836 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDIO_STATUS_CDI_OVERFLOW BIT(20) BIT 837 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDIO_STATUS_CDI_OVERRUN BIT(19) BIT 840 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDIO_STATUS_CDI_FIFO_REQ BIT(18) BIT 841 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDIO_STATUS_CDI_FIFO_FULL BIT(17) BIT 842 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDIO_STATUS_CDI_FIFO_EMPTY BIT(16) BIT 843 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDIO_STATUS_CDO_UNDERFLOW BIT(4) BIT 844 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDIO_STATUS_CDO_OVERRUN BIT(3) BIT 847 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDIO_STATUS_CDO_FIFO_REQ BIT(2) BIT 848 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDIO_STATUS_CDO_FIFO_FULL BIT(1) BIT 849 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDIO_STATUS_CDO_FIFO_EMPTY BIT(0) BIT 851 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_CMD_SW_UPDATE BIT(20) BIT 852 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_SW_UPDATE BIT(19) BIT 853 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_F_E_INT_ENA_CLR BIT(17) BIT 854 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_F_E_INT_ENA_SET BIT(16) BIT 855 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_CMD_ERR_INT_CONFIRM BIT(15) BIT 856 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_ERR_INT_CONFIRM BIT(14) BIT 857 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_CMD_F_REQ_INT_ENA_CLR BIT(13) BIT 858 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_CMD_F_REQ_INT_ENA_SET BIT(12) BIT 859 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_F_REQ_INT_ENA_CLR BIT(11) BIT 860 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_F_REQ_INT_ENA_SET BIT(10) BIT 861 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_CMD_ERR_INT_ENA_CLR BIT(9) BIT 862 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_CMD_ERR_INT_ENA_SET BIT(8) BIT 863 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_ERR_INT_ENA_CLR BIT(7) BIT 864 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_ERR_INT_ENA_SET BIT(6) BIT 865 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_CMD_RESET BIT(5) BIT 866 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_RESET BIT(4) BIT 867 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_CMD_ARM BIT(3) BIT 868 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_CMD_DISARM BIT(2) BIT 869 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_ARM BIT(1) BIT 870 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_CMD_DISARM BIT(0) BIT 880 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_MODE_FIFO_MODE BIT(11) BIT 881 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_MODE_POLARITY BIT(10) BIT 882 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDI_MODE_HALT_ON_ERROR BIT(9) BIT 894 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_MODE_FIFO_MODE BIT(11) BIT 895 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_MODE_POLARITY BIT(10) BIT 896 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_MODE_HALT_ON_ERROR BIT(9) BIT 897 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_CDO_MODE_RETRANSMIT BIT(8) BIT 904 drivers/staging/comedi/drivers/ni_stc.h #define NI_M_AO_REF_ATTENUATION_X5 BIT(0) BIT 17 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_ARM BIT(0) BIT 18 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_SAVE_TRACE BIT(1) BIT 19 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_LOAD BIT(2) BIT 20 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_DISARM BIT(4) BIT 23 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_WRITE_SWITCH BIT(7) BIT 24 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_SYNC_GATE BIT(8) BIT 25 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_LITTLE_BIG_ENDIAN BIT(9) BIT 26 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_BANK_SWITCH_START BIT(10) BIT 27 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_BANK_SWITCH_MODE BIT(11) BIT 28 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_BANK_SWITCH_ENABLE BIT(12) BIT 29 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_ARM_COPY BIT(13) BIT 30 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_SAVE_TRACE_COPY BIT(14) BIT 31 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_DISARM_COPY BIT(15) BIT 41 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE_ON_BOTH_EDGES BIT(2) BIT 53 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_LOAD_SRC_SEL BIT(7) BIT 65 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_LOADING_ON_TC BIT(12) BIT 66 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE_POL_INVERT BIT(13) BIT 67 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_LOADING_ON_GATE BIT(14) BIT 68 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_RELOAD_SRC_SWITCHING BIT(15) BIT 72 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_READ_ACKS_IRQ BIT(0) BIT 73 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_WRITE_ACKS_IRQ BIT(1) BIT 80 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE_SEL_LOAD_SRC BIT(12) BIT 81 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_OR_GATE BIT(13) BIT 82 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_OUTPUT_POL_INVERT BIT(14) BIT 83 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_SRC_POL_INVERT BIT(15) BIT 93 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_INDEX_MODE BIT(4) BIT 96 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_HW_ARM_ENA BIT(7) BIT 100 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_660X_PRESCALE_X8 BIT(12) BIT 101 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_M_PRESCALE_X8 BIT(13) BIT 102 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_660X_ALT_SYNC BIT(13) BIT 103 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_M_ALT_SYNC BIT(14) BIT 104 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_660X_PRESCALE_X2 BIT(14) BIT 105 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_M_PRESCALE_X2 BIT(15) BIT 107 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE2_MODE BIT(0) BIT 111 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE2_POL_INVERT BIT(13) BIT 112 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE2_SUBSEL BIT(14) BIT 113 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_SRC_SUBSEL BIT(15) BIT 115 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_SAVE(x) (((x) % 2) ? BIT(1) : BIT(0)) BIT 116 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_COUNTING(x) (((x) % 2) ? BIT(3) : BIT(2)) BIT 117 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_NEXT_LOAD_SRC(x) (((x) % 2) ? BIT(5) : BIT(4)) BIT 118 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_STALE_DATA(x) (((x) % 2) ? BIT(7) : BIT(6)) BIT 119 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_ARMED(x) (((x) % 2) ? BIT(9) : BIT(8)) BIT 120 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_NO_LOAD_BETWEEN_GATES(x) (((x) % 2) ? BIT(11) : BIT(10)) BIT 121 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_TC_ERROR(x) (((x) % 2) ? BIT(13) : BIT(12)) BIT 122 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE_ERROR(x) (((x) % 2) ? BIT(15) : BIT(14)) BIT 124 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_RESET(x) BIT(2 + ((x) % 2)) BIT 127 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_OUTPUT(x) (((x) % 2) ? BIT(1) : BIT(0)) BIT 128 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_HW_SAVE(x) (((x) % 2) ? BIT(13) : BIT(12)) BIT 129 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_PERMANENT_STALE(x) (((x) % 2) ? BIT(15) : BIT(14)) BIT 131 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_DMA_ENABLE BIT(0) BIT 132 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_DMA_WRITE BIT(1) BIT 133 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_DMA_INT_ENA BIT(2) BIT 134 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_DMA_RESET BIT(3) BIT 135 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_DMA_BANKSW_ERROR BIT(4) BIT 137 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_DMA_READBANK BIT(13) BIT 138 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_DRQ_ERROR BIT(14) BIT 139 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_DRQ_STATUS BIT(15) BIT 142 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE_ERROR_CONFIRM(x) (((x) % 2) ? BIT(1) : BIT(5)) BIT 143 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_TC_ERROR_CONFIRM(x) (((x) % 2) ? BIT(2) : BIT(6)) BIT 144 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_TC_INTERRUPT_ACK BIT(14) BIT 145 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE_INTERRUPT_ACK BIT(15) BIT 147 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE_INTERRUPT BIT(2) BIT 148 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_TC BIT(3) BIT 149 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_INTERRUPT BIT(15) BIT 151 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_TC_INTERRUPT_ENABLE(x) (((x) % 2) ? BIT(9) : BIT(6)) BIT 152 drivers/staging/comedi/drivers/ni_tio_internal.h #define GI_GATE_INTERRUPT_ENABLE(x) (((x) % 2) ? BIT(10) : BIT(8)) BIT 43 drivers/staging/comedi/drivers/pcl711.c #define PCL711_AI_MSB_DRDY BIT(4) BIT 54 drivers/staging/comedi/drivers/pcl711.c #define PCL711_MUX_CS0 BIT(4) BIT 55 drivers/staging/comedi/drivers/pcl711.c #define PCL711_MUX_CS1 BIT(5) BIT 129 drivers/staging/comedi/drivers/pcl812.c #define PCL812_AI_MSB_DRDY BIT(4) BIT 135 drivers/staging/comedi/drivers/pcl812.c #define PCL812_STATUS_DRDY BIT(5) BIT 139 drivers/staging/comedi/drivers/pcl812.c #define PCL812_MUX_CS0 BIT(4) BIT 140 drivers/staging/comedi/drivers/pcl812.c #define PCL812_MUX_CS1 BIT(5) BIT 57 drivers/staging/comedi/drivers/pcl816.c #define PCL816_CTRL_SOFT_TRIG BIT(0) BIT 58 drivers/staging/comedi/drivers/pcl816.c #define PCL816_CTRL_PACER_TRIG BIT(1) BIT 59 drivers/staging/comedi/drivers/pcl816.c #define PCL816_CTRL_EXT_TRIG BIT(2) BIT 60 drivers/staging/comedi/drivers/pcl816.c #define PCL816_CTRL_POE BIT(3) BIT 61 drivers/staging/comedi/drivers/pcl816.c #define PCL816_CTRL_DMAEN BIT(4) BIT 62 drivers/staging/comedi/drivers/pcl816.c #define PCL816_CTRL_INTEN BIT(5) BIT 69 drivers/staging/comedi/drivers/pcl816.c #define PCL816_STATUS_INTACT BIT(6) BIT 70 drivers/staging/comedi/drivers/pcl816.c #define PCL816_STATUS_DRDY BIT(7) BIT 119 drivers/staging/comedi/drivers/pcl818.c #define PCL818_STATUS_INT BIT(4) BIT 120 drivers/staging/comedi/drivers/pcl818.c #define PCL818_STATUS_MUX BIT(5) BIT 121 drivers/staging/comedi/drivers/pcl818.c #define PCL818_STATUS_UNI BIT(6) BIT 122 drivers/staging/comedi/drivers/pcl818.c #define PCL818_STATUS_EOC BIT(7) BIT 129 drivers/staging/comedi/drivers/pcl818.c #define PCL818_CTRL_DMAE BIT(2) BIT 131 drivers/staging/comedi/drivers/pcl818.c #define PCL818_CTRL_INTE BIT(7) BIT 133 drivers/staging/comedi/drivers/pcl818.c #define PCL818_CNTENABLE_PACER_TRIG0 BIT(0) BIT 134 drivers/staging/comedi/drivers/pcl818.c #define PCL818_CNTENABLE_CNT0_INT_CLK BIT(1) /* 0=ext clk */ BIT 43 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_DIO_DIR_C0_OUT BIT(0) BIT 44 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_DIO_DIR_B0_OUT BIT(1) BIT 45 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_DIO_DIR_A0_OUT BIT(2) BIT 46 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_DIO_DIR_C1_OUT BIT(3) BIT 47 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_DIO_DIR_B1_OUT BIT(4) BIT 48 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_DIO_DIR_A1_OUT BIT(5) BIT 50 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_GATE_CTRL_C0_ENA BIT(0) BIT 51 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_GATE_CTRL_B0_ENA BIT(1) BIT 52 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_GATE_CTRL_A0_ENA BIT(2) BIT 53 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_GATE_CTRL_C1_ENA BIT(3) BIT 54 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_GATE_CTRL_B1_ENA BIT(4) BIT 55 drivers/staging/comedi/drivers/pcm3724.c #define PCM3724_GATE_CTRL_A1_ENA BIT(5) BIT 78 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_CMD_SE BIT(7) BIT 79 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_CMD_ODD_CHAN BIT(6) BIT 85 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_STATUS_DATA_READY BIT(7) BIT 86 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_STATUS_DATA_DMA_PEND BIT(6) BIT 87 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_STATUS_CMD_DMA_PEND BIT(5) BIT 88 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_STATUS_IRQ_PEND BIT(4) BIT 89 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_STATUS_DATA_DRQ_ENA BIT(2) BIT 90 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_STATUS_REG_SEL BIT(3) BIT 91 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_STATUS_CMD_DRQ_ENA BIT(1) BIT 92 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_STATUS_IRQ_ENA BIT(0) BIT 95 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_RES_ENA_AI_RES_ACCESS BIT(3) BIT 96 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AI_RES_ENA_DIO_RES_ACCESS BIT(4) BIT 119 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AO_STATUS_DATA_READY BIT(7) BIT 120 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AO_STATUS_DATA_DMA_PEND BIT(6) BIT 121 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AO_STATUS_CMD_DMA_PEND BIT(5) BIT 122 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AO_STATUS_IRQ_PEND BIT(4) BIT 123 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AO_STATUS_DATA_DRQ_ENA BIT(2) BIT 124 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AO_STATUS_REG_SEL BIT(3) BIT 125 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AO_STATUS_CMD_DRQ_ENA BIT(1) BIT 126 drivers/staging/comedi/drivers/pcmmio.c #define PCMMIO_AO_STATUS_IRQ_ENA BIT(0) BIT 18 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_LI1ENAB BIT(0) /* LI1 enabled */ BIT 19 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_LI1POL BIT(1) /* LI1 active high */ BIT 20 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_LI1STAT BIT(2) /* LI1 active */ BIT 21 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_LI2ENAB BIT(3) /* LI2 enabled */ BIT 22 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_LI2POL BIT(4) /* LI2 active high */ BIT 23 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_LI2STAT BIT(5) /* LI2 active */ BIT 24 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_PCIENAB BIT(6) /* PCIINT enabled */ BIT 25 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_SOFTINT BIT(7) /* generate soft int */ BIT 26 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_LI1SEL BIT(8) /* LI1 edge */ BIT 27 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_LI2SEL BIT(9) /* LI2 edge */ BIT 28 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_LI1CLRINT BIT(10) /* LI1 clear int */ BIT 29 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_LI2CLRINT BIT(11) /* LI2 clear int */ BIT 30 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_INTCSR_ISAMODE BIT(12) /* ISA interface mode */ BIT 37 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_WAITO BIT(0) /* UIO0 or WAITO# select */ BIT 38 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_UIO0_DIR BIT(1) /* UIO0 direction */ BIT 39 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_UIO0_DATA BIT(2) /* UIO0 data */ BIT 40 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_LLOCKO BIT(3) /* UIO1 or LLOCKo# select */ BIT 41 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_UIO1_DIR BIT(4) /* UIO1 direction */ BIT 42 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_UIO1_DATA BIT(5) /* UIO1 data */ BIT 43 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_CS2 BIT(6) /* UIO2 or CS2# select */ BIT 44 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_UIO2_DIR BIT(7) /* UIO2 direction */ BIT 45 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_UIO2_DATA BIT(8) /* UIO2 data */ BIT 46 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_CS3 BIT(9) /* UIO3 or CS3# select */ BIT 47 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_UIO3_DIR BIT(10) /* UIO3 direction */ BIT 48 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_UIO3_DATA BIT(11) /* UIO3 data */ BIT 53 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_PCI2_1_FEATURES BIT(14) /* PCI v2.1 features enabled */ BIT 54 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_PCI_R_W_FLUSH BIT(15) /* read w/write flush mode */ BIT 55 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_PCI_R_NO_FLUSH BIT(16) /* read no flush mode */ BIT 56 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_PCI_R_NO_WRITE BIT(17) /* read no write mode */ BIT 57 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_PCI_W_RELEASE BIT(18) /* write release bus mode */ BIT 59 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_LOCK_ENAB BIT(23) /* slave LOCK# enable */ BIT 61 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_EEPROM_CLK BIT(24) /* EEPROM clock */ BIT 62 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_EEPROM_CS BIT(25) /* EEPROM chip select */ BIT 63 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_EEPROM_DOUT BIT(26) /* EEPROM write bit */ BIT 64 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_EEPROM_DIN BIT(27) /* EEPROM read bit */ BIT 65 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_EEPROM_PRESENT BIT(28) /* EEPROM present */ BIT 66 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_RELOAD_CFG BIT(29) /* reload configuration */ BIT 67 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_PCI_RESET BIT(30) /* PCI adapter reset */ BIT 68 drivers/staging/comedi/drivers/plx9052.h #define PLX9052_CNTRL_MASK_REV BIT(31) /* mask revision */ BIT 58 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */ BIT 59 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASRR_MLOC_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */ BIT 60 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASRR_MLOC_LT1MB (BIT(1) * 1) /* Locate in 1st meg */ BIT 61 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASRR_MLOC_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */ BIT 63 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */ BIT 74 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASBA_EN BIT(0) /* Enable slave decode */ BIT 86 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_LT(x) (BIT(0) * ((x) & 0xff)) BIT 90 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PT(x) (BIT(8) * ((x) & 0xff)) BIT 94 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_LTEN BIT(16) BIT 96 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PTEN BIT(17) BIT 98 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_BREQEN BIT(18) BIT 100 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PRIO_ROT (BIT(19) * 0) /* Rotational priority */ BIT 101 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */ BIT 102 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */ BIT 105 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_DSGUBM BIT(21) BIT 107 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_DSLLOCKOEN BIT(22) BIT 109 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PCIREQM BIT(23) BIT 111 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PCIV21M BIT(24) BIT 113 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PCIRNWM BIT(25) BIT 115 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PCIRWFM BIT(26) BIT 117 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_GLTBREQ BIT(27) BIT 119 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PCIRNFM BIT(28) BIT 124 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_SUBSYSIDS BIT(29) BIT 130 drivers/staging/comedi/drivers/plx9080.h #define PLX_BIGEND_CONFIG BIT(0) BIT 132 drivers/staging/comedi/drivers/plx9080.h #define PLX_BIGEND_DM BIT(1) BIT 134 drivers/staging/comedi/drivers/plx9080.h #define PLX_BIGEND_DSAS0 BIT(2) BIT 136 drivers/staging/comedi/drivers/plx9080.h #define PLX_BIGEND_EROM BIT(3) BIT 138 drivers/staging/comedi/drivers/plx9080.h #define PLX_BIGEND_BEBLM BIT(4) BIT 140 drivers/staging/comedi/drivers/plx9080.h #define PLX_BIGEND_DSAS1 BIT(5) BIT 142 drivers/staging/comedi/drivers/plx9080.h #define PLX_BIGEND_DMA1 BIT(6) BIT 144 drivers/staging/comedi/drivers/plx9080.h #define PLX_BIGEND_DMA0 BIT(7) BIT 165 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_MSWIDTH_8 (BIT(0) * 0) /* 8 bits wide */ BIT 166 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_MSWIDTH_16 (BIT(0) * 1) /* 16 bits wide */ BIT 167 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_MSWIDTH_32 (BIT(0) * 2) /* 32 bits wide */ BIT 168 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_MSWIDTH_32A (BIT(0) * 3) /* 32 bits wide */ BIT 171 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_MSIWS(x) (BIT(2) * ((x) & 0xf)) BIT 175 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_MSREADYIEN BIT(6) BIT 177 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_MSBTERMIEN BIT(7) BIT 179 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_MSPREDIS BIT(8) BIT 181 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD1_MSBURSTEN BIT(8) BIT 183 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMPREDIS BIT(9) BIT 185 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD1_MSPREDIS BIT(9) BIT 187 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_RPFCOUNTEN BIT(10) BIT 189 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_PFCOUNT(x) (BIT(11) * ((x) & 0xf)) BIT 193 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMWIDTH_8 (BIT(16) * 0) /* 8 bits wide */ BIT 194 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMWIDTH_16 (BIT(16) * 1) /* 16 bits wide */ BIT 195 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMWIDTH_32 (BIT(16) * 2) /* 32 bits wide */ BIT 196 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMWIDTH_32A (BIT(16) * 3) /* 32 bits wide */ BIT 199 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMIWS(x) (BIT(18) * ((x) & 0xf)) BIT 203 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMREADYIEN BIT(22) BIT 205 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMBTERMIEN BIT(23) BIT 207 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_MSBURSTEN BIT(24) BIT 209 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EELONGLOAD BIT(25) BIT 211 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMBURSTEN BIT(26) BIT 213 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_DSWMTRDY BIT(27) BIT 215 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_TRDELAY(x) (BIT(28) * ((x) & 0xF)) BIT 232 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_MEMACCEN BIT(0) BIT 234 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_IOACCEN BIT(1) BIT 236 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_LLOCKIEN BIT(2) BIT 238 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_RPSIZE_CONT ((BIT(12) * 0) | (BIT(3) * 0)) BIT 239 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_RPSIZE_4 ((BIT(12) * 0) | (BIT(3) * 1)) BIT 240 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_RPSIZE_8 ((BIT(12) * 1) | (BIT(3) * 0)) BIT 241 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_RPSIZE_16 ((BIT(12) * 1) | (BIT(3) * 1)) BIT 242 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_RPSIZE_MASK (BIT(12) | BIT(3)) BIT 244 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_RMIRDY BIT(4) BIT 246 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_PAFL(x) ((BIT(10) * !!((x) & 0x10)) | \ BIT 247 drivers/staging/comedi/drivers/plx9080.h (BIT(5) * ((x) & 0xf))) BIT 248 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_TO_PAFL(v) ((((BIT(10) & (v)) >> 1) | \ BIT 250 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_PAFL_MASK (BIT(10) | GENMASK(8, 5)) BIT 252 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_WIM BIT(9) BIT 254 drivers/staging/comedi/drivers/plx9080.h #define PLX_DBPBAM_PFLIMIT BIT(11) BIT 256 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_IOREMAPSEL BIT(13) BIT 258 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_WDELAY_NONE (BIT(14) * 0) BIT 259 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_WDELAY_4 (BIT(14) * 1) BIT 260 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_WDELAY_8 (BIT(14) * 2) BIT 261 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_WDELAY_16 (BIT(14) * 3) BIT 270 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_TYPE0 (BIT(0) * 0) BIT 271 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_TYPE1 (BIT(0) * 1) BIT 274 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_REGNUM(x) (BIT(2) * ((x) & 0x3f)) BIT 278 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_FUNCNUM(x) (BIT(8) * ((x) & 0x7)) BIT 282 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_DEVNUM(x) (BIT(11) * ((x) & 0x1f)) BIT 286 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_BUSNUM(x) (BIT(16) * ((x) & 0xff)) BIT 290 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_CONFIGEN BIT(31) BIT 325 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_LSEABORTEN BIT(0) BIT 327 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_LSEPARITYEN BIT(1) BIT 329 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_GENSERR BIT(2) BIT 331 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_MBIEN BIT(3) BIT 333 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_PIEN BIT(8) BIT 335 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_PDBIEN BIT(9) BIT 337 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_PABORTIEN BIT(10) BIT 339 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_PLIEN BIT(11) BIT 341 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_RAEN BIT(12) BIT 343 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_PDBIA BIT(13) BIT 345 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_PABORTIA BIT(14) BIT 347 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_PLIA BIT(15) BIT 349 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_LIOEN BIT(16) BIT 351 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_LDBIEN BIT(17) BIT 353 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_DMA0IEN BIT(18) BIT 355 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_DMA1IEN BIT(19) BIT 359 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_LDBIA BIT(20) BIT 361 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_DMA0IA BIT(21) BIT 363 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_DMA1IA BIT(22) BIT 367 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_BISTIA BIT(23) BIT 369 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_ABNOTDM BIT(24) BIT 371 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_ABNOTDMA0 BIT(25) BIT 373 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_ABNOTDMA1 BIT(26) BIT 378 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_ABNOTRETRY BIT(27) BIT 380 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_MB0IA BIT(28) BIT 382 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_MB1IA BIT(29) BIT 384 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_MB2IA BIT(30) BIT 386 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_MB3IA BIT(31) BIT 388 drivers/staging/comedi/drivers/plx9080.h #define PLX_INTCSR_MBIA(n) BIT(28 + (n)) BIT 397 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_CCRDMA(x) (BIT(0) * ((x) & 0xf)) BIT 402 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_CCWDMA(x) (BIT(4) * ((x) & 0xf)) BIT 407 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_CCRDM(x) (BIT(8) * ((x) & 0xf)) BIT 412 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_CCWDM(x) (BIT(12) * ((x) & 0xf)) BIT 417 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_USERO BIT(16) BIT 419 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_USERI BIT(17) BIT 421 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_EESK BIT(24) BIT 423 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_EECS BIT(25) BIT 425 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_EEWB BIT(26) BIT 427 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_EERB BIT(27) BIT 429 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_EEPRESENT BIT(28) BIT 431 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_EERELOAD BIT(29) BIT 433 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_RESET BIT(30) BIT 435 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_INITDONE BIT(31) BIT 461 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_WIDTH_8 (BIT(0) * 0) /* 8 bits wide */ BIT 462 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_WIDTH_16 (BIT(0) * 1) /* 16 bits wide */ BIT 463 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_WIDTH_32 (BIT(0) * 2) /* 32 bits wide */ BIT 464 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_WIDTH_32A (BIT(0) * 3) /* 32 bits wide */ BIT 467 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_IWS(x) (BIT(2) * ((x) & 0xf)) BIT 471 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_READYIEN BIT(6) BIT 473 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_BTERMIEN BIT(7) BIT 475 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_BURSTEN BIT(8) BIT 477 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_CHAINEN BIT(9) BIT 479 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_DONEIEN BIT(10) BIT 481 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_LACONST BIT(11) BIT 483 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_DEMAND BIT(12) BIT 485 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_WINVALIDATE BIT(13) BIT 487 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_EOTEN BIT(14) BIT 489 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_STOP BIT(15) BIT 491 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_CLRCOUNT BIT(16) BIT 493 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_INTRPCI BIT(17) BIT 516 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMADPR_DESCPCI BIT(0) BIT 518 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMADPR_CHAINEND BIT(1) BIT 520 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMADPR_TCINTR BIT(2) BIT 522 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMADPR_XFERL2P BIT(3) BIT 532 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMACSR_ENABLE BIT(0) BIT 534 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMACSR_START BIT(1) BIT 536 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMACSR_ABORT BIT(2) BIT 538 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMACSR_CLEARINTR BIT(3) BIT 540 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMACSR_DONE BIT(4) BIT 554 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C0PLAF(x) (BIT(0) * ((x) & 0xf)) BIT 558 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C0LPAE(x) (BIT(4) * ((x) & 0xf)) BIT 562 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C0LPAF(x) (BIT(8) * ((x) & 0xf)) BIT 566 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C0PLAE(x) (BIT(12) * ((x) & 0xf)) BIT 570 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C1PLAF(x) (BIT(16) * ((x) & 0xf)) BIT 574 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C1LPAE(x) (BIT(20) * ((x) & 0xf)) BIT 578 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C1LPAF(x) (BIT(24) * ((x) & 0xf)) BIT 582 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C1PLAE(x) (BIT(28) * ((x) & 0xf)) BIT 59 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_SCANLIST_DIFFERENTIAL BIT(14) BIT 62 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_SCANLIST_START BIT(7) BIT 72 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CTRL_EXPANSION BIT(5) BIT 73 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CTRL_EOS_INT_ENA BIT(4) BIT 74 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CTRL_FIFO_INT_ENA BIT(3) BIT 75 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CTRL_TRIG_MODE BIT(2) /* 0=one-shot; 1=continuous */ BIT 76 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CTRL_TRIG_SRC BIT(1) /* 0=internal; 1=external */ BIT 77 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CTRL_TRIG_EDGE BIT(0) /* 0=rising; 1=falling */ BIT 80 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_STATUS_IDLE BIT(7) BIT 81 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_STATUS_RUNNING BIT(6) BIT 82 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_STATUS_DATA_LOST BIT(5) BIT 83 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_STATUS_END_OF_SCAN BIT(4) BIT 84 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_STATUS_FIFO_THRESHOLD BIT(3) BIT 85 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_STATUS_FIFO_FULL BIT(2) BIT 86 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_STATUS_FIFO_NEARFULL BIT(1) BIT 87 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_STATUS_FIFO_EMPTY BIT(0) BIT 102 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CMD_ARM BIT(7) /* monostable */ BIT 103 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CMD_RSTF BIT(6) /* monostable */ BIT 104 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CMD_RSTQ BIT(5) /* monostable */ BIT 105 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CMD_STOP BIT(4) /* monostable */ BIT 106 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CMD_LATCH BIT(3) /* monostable */ BIT 111 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_CMD_FIFO_DATA BIT(0) BIT 119 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_EXT_ANALOG_TRIG BIT(7) BIT 120 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_PRETRIG BIT(6) BIT 121 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_TIMER_INT_ENA BIT(5) BIT 127 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_TIMER_CLK_SRC_EXT BIT(2) BIT 134 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_RUNNING BIT(7) BIT 135 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_TRIGGERED BIT(6) BIT 136 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_DA_BUFFER BIT(5) BIT 137 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_TIMER_OVERFLOW BIT(4) BIT 138 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_CONVERSION BIT(3) BIT 139 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_DATA_LOST BIT(2) BIT 140 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_FIFO_NEARFULL BIT(1) BIT 141 drivers/staging/comedi/drivers/quatech_daqp_cs.c #define DAQP_AUX_FIFO_EMPTY BIT(0) BIT 99 drivers/staging/comedi/drivers/rtd520.c #define FS_DAC1_NOT_EMPTY BIT(0) /* DAC1 FIFO not empty */ BIT 100 drivers/staging/comedi/drivers/rtd520.c #define FS_DAC1_HEMPTY BIT(1) /* DAC1 FIFO half empty */ BIT 101 drivers/staging/comedi/drivers/rtd520.c #define FS_DAC1_NOT_FULL BIT(2) /* DAC1 FIFO not full */ BIT 102 drivers/staging/comedi/drivers/rtd520.c #define FS_DAC2_NOT_EMPTY BIT(4) /* DAC2 FIFO not empty */ BIT 103 drivers/staging/comedi/drivers/rtd520.c #define FS_DAC2_HEMPTY BIT(5) /* DAC2 FIFO half empty */ BIT 104 drivers/staging/comedi/drivers/rtd520.c #define FS_DAC2_NOT_FULL BIT(6) /* DAC2 FIFO not full */ BIT 105 drivers/staging/comedi/drivers/rtd520.c #define FS_ADC_NOT_EMPTY BIT(8) /* ADC FIFO not empty */ BIT 106 drivers/staging/comedi/drivers/rtd520.c #define FS_ADC_HEMPTY BIT(9) /* ADC FIFO half empty */ BIT 107 drivers/staging/comedi/drivers/rtd520.c #define FS_ADC_NOT_FULL BIT(10) /* ADC FIFO not full */ BIT 108 drivers/staging/comedi/drivers/rtd520.c #define FS_DIN_NOT_EMPTY BIT(12) /* DIN FIFO not empty */ BIT 109 drivers/staging/comedi/drivers/rtd520.c #define FS_DIN_HEMPTY BIT(13) /* DIN FIFO half empty */ BIT 110 drivers/staging/comedi/drivers/rtd520.c #define FS_DIN_NOT_FULL BIT(14) /* DIN FIFO not full */ BIT 116 drivers/staging/comedi/drivers/rtd520.c #define IRQM_ADC_FIFO_WRITE BIT(0) /* ADC FIFO Write */ BIT 117 drivers/staging/comedi/drivers/rtd520.c #define IRQM_CGT_RESET BIT(1) /* Reset CGT */ BIT 118 drivers/staging/comedi/drivers/rtd520.c #define IRQM_CGT_PAUSE BIT(3) /* Pause CGT */ BIT 119 drivers/staging/comedi/drivers/rtd520.c #define IRQM_ADC_ABOUT_CNT BIT(4) /* About Counter out */ BIT 120 drivers/staging/comedi/drivers/rtd520.c #define IRQM_ADC_DELAY_CNT BIT(5) /* Delay Counter out */ BIT 121 drivers/staging/comedi/drivers/rtd520.c #define IRQM_ADC_SAMPLE_CNT BIT(6) /* ADC Sample Counter */ BIT 122 drivers/staging/comedi/drivers/rtd520.c #define IRQM_DAC1_UCNT BIT(7) /* DAC1 Update Counter */ BIT 123 drivers/staging/comedi/drivers/rtd520.c #define IRQM_DAC2_UCNT BIT(8) /* DAC2 Update Counter */ BIT 124 drivers/staging/comedi/drivers/rtd520.c #define IRQM_UTC1 BIT(9) /* User TC1 out */ BIT 125 drivers/staging/comedi/drivers/rtd520.c #define IRQM_UTC1_INV BIT(10) /* User TC1 out, inverted */ BIT 126 drivers/staging/comedi/drivers/rtd520.c #define IRQM_UTC2 BIT(11) /* User TC2 out */ BIT 127 drivers/staging/comedi/drivers/rtd520.c #define IRQM_DIGITAL_IT BIT(12) /* Digital Interrupt */ BIT 128 drivers/staging/comedi/drivers/rtd520.c #define IRQM_EXTERNAL_IT BIT(13) /* External Interrupt */ BIT 129 drivers/staging/comedi/drivers/rtd520.c #define IRQM_ETRIG_RISING BIT(14) /* Ext Trigger rising-edge */ BIT 130 drivers/staging/comedi/drivers/rtd520.c #define IRQM_ETRIG_FALLING BIT(15) /* Ext Trigger falling-edge */ BIT 51 drivers/staging/comedi/drivers/rti800.c #define RTI800_CSR_BUSY BIT(7) BIT 52 drivers/staging/comedi/drivers/rti800.c #define RTI800_CSR_DONE BIT(6) BIT 53 drivers/staging/comedi/drivers/rti800.c #define RTI800_CSR_OVERRUN BIT(5) BIT 54 drivers/staging/comedi/drivers/rti800.c #define RTI800_CSR_TCR BIT(4) BIT 55 drivers/staging/comedi/drivers/rti800.c #define RTI800_CSR_DMA_ENAB BIT(3) BIT 56 drivers/staging/comedi/drivers/rti800.c #define RTI800_CSR_INTR_TC BIT(2) BIT 57 drivers/staging/comedi/drivers/rti800.c #define RTI800_CSR_INTR_EC BIT(1) BIT 58 drivers/staging/comedi/drivers/rti800.c #define RTI800_CSR_INTR_OVRN BIT(0) BIT 40 drivers/staging/comedi/drivers/s526.c #define S526_TIMER_RESTART BIT(0) BIT 42 drivers/staging/comedi/drivers/s526.c #define S526_WDOG_INVERTED BIT(4) BIT 43 drivers/staging/comedi/drivers/s526.c #define S526_WDOG_ENA BIT(3) BIT 46 drivers/staging/comedi/drivers/s526.c #define S526_AO_CTRL_RESET BIT(3) BIT 48 drivers/staging/comedi/drivers/s526.c #define S526_AO_CTRL_START BIT(0) BIT 50 drivers/staging/comedi/drivers/s526.c #define S526_AI_CTRL_DELAY BIT(15) BIT 53 drivers/staging/comedi/drivers/s526.c #define S526_AI_CTRL_START BIT(0) BIT 57 drivers/staging/comedi/drivers/s526.c #define S526_DIO_CTRL_DIO3_NEG BIT(15) /* irq on DIO3 neg/pos edge */ BIT 58 drivers/staging/comedi/drivers/s526.c #define S526_DIO_CTRL_DIO2_NEG BIT(14) /* irq on DIO2 neg/pos edge */ BIT 59 drivers/staging/comedi/drivers/s526.c #define S526_DIO_CTRL_DIO1_NEG BIT(13) /* irq on DIO1 neg/pos edge */ BIT 60 drivers/staging/comedi/drivers/s526.c #define S526_DIO_CTRL_DIO0_NEG BIT(12) /* irq on DIO0 neg/pos edge */ BIT 61 drivers/staging/comedi/drivers/s526.c #define S526_DIO_CTRL_GRP2_OUT BIT(11) BIT 62 drivers/staging/comedi/drivers/s526.c #define S526_DIO_CTRL_GRP1_OUT BIT(10) BIT 63 drivers/staging/comedi/drivers/s526.c #define S526_DIO_CTRL_GRP2_NEG BIT(8) /* irq on DIO[4-7] neg/pos edge */ BIT 66 drivers/staging/comedi/drivers/s526.c #define S526_INT_DIO(x) BIT(8 + ((x) & 0x7)) BIT 67 drivers/staging/comedi/drivers/s526.c #define S526_INT_EEPROM BIT(7) /* status only */ BIT 68 drivers/staging/comedi/drivers/s526.c #define S526_INT_CNTR(x) BIT(3 + (3 - ((x) & 0x3))) BIT 69 drivers/staging/comedi/drivers/s526.c #define S526_INT_AI BIT(2) BIT 70 drivers/staging/comedi/drivers/s526.c #define S526_INT_AO BIT(1) BIT 71 drivers/staging/comedi/drivers/s526.c #define S526_INT_TIMER BIT(0) BIT 73 drivers/staging/comedi/drivers/s526.c #define S526_MISC_LED_OFF BIT(0) BIT 143 drivers/staging/comedi/drivers/s526.c #define S526_GPCT_CTRL_COUT_STATUS BIT(4) /* R */ BIT 144 drivers/staging/comedi/drivers/s526.c #define S526_GPCT_CTRL_INDEX_STATUS BIT(5) /* R */ BIT 160 drivers/staging/comedi/drivers/s526.c #define S525_GPCT_CTRL_CT_ARM BIT(13) /* W */ BIT 161 drivers/staging/comedi/drivers/s526.c #define S525_GPCT_CTRL_CT_LOAD BIT(14) /* W */ BIT 162 drivers/staging/comedi/drivers/s526.c #define S526_GPCT_CTRL_CT_RESET BIT(15) /* W */ BIT 168 drivers/staging/comedi/drivers/s526.c #define S526_EEPROM_CTRL_START BIT(0) BIT 336 drivers/staging/comedi/drivers/tests/ni_routes_test.c BIT(6), BIT 339 drivers/staging/comedi/drivers/tests/ni_routes_test.c BIT(6), BIT 342 drivers/staging/comedi/drivers/tests/ni_routes_test.c BIT(6), BIT 345 drivers/staging/comedi/drivers/tests/ni_routes_test.c BIT(6), BIT 348 drivers/staging/comedi/drivers/tests/ni_routes_test.c BIT(6), BIT 351 drivers/staging/comedi/drivers/tests/ni_routes_test.c BIT(6), BIT 354 drivers/staging/comedi/drivers/tests/ni_routes_test.c BIT(6), BIT 357 drivers/staging/comedi/drivers/tests/ni_routes_test.c BIT(6), BIT 90 drivers/staging/comedi/drivers/vmk80xx.c #define IC3_VERSION BIT(0) BIT 91 drivers/staging/comedi/drivers/vmk80xx.c #define IC6_VERSION BIT(1) BIT 11 drivers/staging/comedi/drivers/z8536.h #define Z8536_INT_CTRL_MIE BIT(7) /* Master Interrupt Enable */ BIT 12 drivers/staging/comedi/drivers/z8536.h #define Z8536_INT_CTRL_DLC BIT(6) /* Disable Lower Chain */ BIT 13 drivers/staging/comedi/drivers/z8536.h #define Z8536_INT_CTRL_NV BIT(5) /* No Vector */ BIT 14 drivers/staging/comedi/drivers/z8536.h #define Z8536_INT_CTRL_PA_VIS BIT(4) /* Port A Vect Inc Status */ BIT 15 drivers/staging/comedi/drivers/z8536.h #define Z8536_INT_CTRL_PB_VIS BIT(3) /* Port B Vect Inc Status */ BIT 16 drivers/staging/comedi/drivers/z8536.h #define Z8536_INT_CTRL_VT_VIS BIT(2) /* C/T Vect Inc Status */ BIT 17 drivers/staging/comedi/drivers/z8536.h #define Z8536_INT_CTRL_RJA BIT(1) /* Right Justified Addresses */ BIT 18 drivers/staging/comedi/drivers/z8536.h #define Z8536_INT_CTRL_RESET BIT(0) /* Reset */ BIT 22 drivers/staging/comedi/drivers/z8536.h #define Z8536_CFG_CTRL_PBE BIT(7) /* Port B Enable */ BIT 23 drivers/staging/comedi/drivers/z8536.h #define Z8536_CFG_CTRL_CT1E BIT(6) /* C/T 1 Enable */ BIT 24 drivers/staging/comedi/drivers/z8536.h #define Z8536_CFG_CTRL_CT2E BIT(5) /* C/T 2 Enable */ BIT 25 drivers/staging/comedi/drivers/z8536.h #define Z8536_CFG_CTRL_PCE_CT3E BIT(4) /* Port C & C/T 3 Enable */ BIT 26 drivers/staging/comedi/drivers/z8536.h #define Z8536_CFG_CTRL_PLC BIT(3) /* Port A/B Link Control */ BIT 27 drivers/staging/comedi/drivers/z8536.h #define Z8536_CFG_CTRL_PAE BIT(2) /* Port A Enable */ BIT 59 drivers/staging/comedi/drivers/z8536.h #define Z8536_STAT_IUS BIT(7) /* Interrupt Under Service */ BIT 60 drivers/staging/comedi/drivers/z8536.h #define Z8536_STAT_IE BIT(6) /* Interrupt Enable */ BIT 61 drivers/staging/comedi/drivers/z8536.h #define Z8536_STAT_IP BIT(5) /* Interrupt Pending */ BIT 62 drivers/staging/comedi/drivers/z8536.h #define Z8536_STAT_ERR BIT(4) /* Interrupt Error */ BIT 65 drivers/staging/comedi/drivers/z8536.h #define Z8536_PAB_STAT_ORE BIT(3) /* Output Register Empty */ BIT 66 drivers/staging/comedi/drivers/z8536.h #define Z8536_PAB_STAT_IRF BIT(2) /* Input Register Full */ BIT 67 drivers/staging/comedi/drivers/z8536.h #define Z8536_PAB_STAT_PMF BIT(1) /* Pattern Match Flag */ BIT 68 drivers/staging/comedi/drivers/z8536.h #define Z8536_PAB_CMDSTAT_IOE BIT(0) /* Interrupt On Error */ BIT 70 drivers/staging/comedi/drivers/z8536.h #define Z8536_CT_CMD_RCC BIT(3) /* Read Counter Control */ BIT 71 drivers/staging/comedi/drivers/z8536.h #define Z8536_CT_CMDSTAT_GCB BIT(2) /* Gate Command Bit */ BIT 72 drivers/staging/comedi/drivers/z8536.h #define Z8536_CT_CMD_TCB BIT(1) /* Trigger Command Bit */ BIT 73 drivers/staging/comedi/drivers/z8536.h #define Z8536_CT_STAT_CIP BIT(0) /* Count In Progress */ BIT 105 drivers/staging/comedi/drivers/z8536.h #define Z8536_CT_MODE_CSC BIT(7) /* Continuous/Single Cycle */ BIT 106 drivers/staging/comedi/drivers/z8536.h #define Z8536_CT_MODE_EOE BIT(6) /* External Output Enable */ BIT 107 drivers/staging/comedi/drivers/z8536.h #define Z8536_CT_MODE_ECE BIT(5) /* External Count Enable */ BIT 108 drivers/staging/comedi/drivers/z8536.h #define Z8536_CT_MODE_ETE BIT(4) /* External Trigger Enable */ BIT 109 drivers/staging/comedi/drivers/z8536.h #define Z8536_CT_MODE_EGE BIT(3) /* External Gate Enable */ BIT 110 drivers/staging/comedi/drivers/z8536.h #define Z8536_CT_MODE_REB BIT(2) /* Retrigger Enable Bit */ BIT 127 drivers/staging/comedi/drivers/z8536.h #define Z8536_PAB_MODE_ITB BIT(5) /* Interrupt on Two Bytes */ BIT 128 drivers/staging/comedi/drivers/z8536.h #define Z8536_PAB_MODE_SB BIT(4) /* Single Buffered mode */ BIT 129 drivers/staging/comedi/drivers/z8536.h #define Z8536_PAB_MODE_IMO BIT(3) /* Interrupt on Match Only */ BIT 136 drivers/staging/comedi/drivers/z8536.h #define Z8536_PAB_MODE_LPM BIT(0) /* Latch on Pattern Match */ BIT 137 drivers/staging/comedi/drivers/z8536.h #define Z8536_PAB_MODE_DTE BIT(0) /* Deskew Timer Enabled */ BIT 1498 drivers/staging/emxx_udc/emxx_udc.c status_data |= BIT(USB_DEVICE_SELF_POWERED); BIT 1501 drivers/staging/emxx_udc/emxx_udc.c status_data |= BIT(USB_DEVICE_REMOTE_WAKEUP); BIT 1513 drivers/staging/emxx_udc/emxx_udc.c status_data |= BIT(USB_ENDPOINT_HALT); BIT 163 drivers/staging/exfat/exfat.h #define UTBL_ROW_COUNT BIT(LOW_INDEX_BIT) BIT 164 drivers/staging/exfat/exfat.h #define UTBL_COL_COUNT BIT(HIGH_INDEX_BIT) BIT 691 drivers/staging/exfat/exfat.h #define EXFAT_HASH_SIZE BIT(EXFAT_HASH_BITS) BIT 363 drivers/staging/fbtft/fb_agm1264k-fl.c write_reg(par, 0x00, BIT(6) | (u8)addr_win.xs); BIT 386 drivers/staging/fbtft/fb_agm1264k-fl.c write_reg(par, 0x01, BIT(6)); BIT 120 drivers/staging/fbtft/fb_hx8340bn.c #define MY BIT(7) BIT 121 drivers/staging/fbtft/fb_hx8340bn.c #define MX BIT(6) BIT 122 drivers/staging/fbtft/fb_hx8340bn.c #define MV BIT(5) BIT 76 drivers/staging/fbtft/fb_hx8353d.c #define my BIT(7) BIT 77 drivers/staging/fbtft/fb_hx8353d.c #define mx BIT(6) BIT 78 drivers/staging/fbtft/fb_hx8353d.c #define mv BIT(5) BIT 188 drivers/staging/fbtft/fb_ili9163.c mactrl_data |= BIT(2); BIT 120 drivers/staging/fbtft/fb_ili9325.c BIT(12) | (bt << 8) | BIT(7) | BIT(4)); BIT 79 drivers/staging/fbtft/fb_ili9341.c #define MEM_Y BIT(7) /* MY row address order */ BIT 80 drivers/staging/fbtft/fb_ili9341.c #define MEM_X BIT(6) /* MX column address order */ BIT 81 drivers/staging/fbtft/fb_ili9341.c #define MEM_V BIT(5) /* MV row / column exchange */ BIT 82 drivers/staging/fbtft/fb_ili9341.c #define MEM_L BIT(4) /* ML vertical refresh order */ BIT 83 drivers/staging/fbtft/fb_ili9341.c #define MEM_H BIT(2) /* MH horizontal refresh order */ BIT 111 drivers/staging/fbtft/fb_s6d02a1.c #define MY BIT(7) BIT 112 drivers/staging/fbtft/fb_s6d02a1.c #define MX BIT(6) BIT 113 drivers/staging/fbtft/fb_s6d02a1.c #define MV BIT(5) BIT 131 drivers/staging/fbtft/fb_sh1106.c buf[x] |= BIT(i); BIT 41 drivers/staging/fbtft/fb_ssd1289.c BIT(13) | (par->bgr << 11) | BIT(9) | (HEIGHT - 1)); BIT 188 drivers/staging/fbtft/fb_ssd1306.c *buf |= BIT(i); BIT 84 drivers/staging/fbtft/fb_ssd1351.c write_reg(par, 0xA0, remap | 0x00 | BIT(4)); BIT 87 drivers/staging/fbtft/fb_ssd1351.c write_reg(par, 0xA0, remap | 0x03 | BIT(4)); BIT 97 drivers/staging/fbtft/fb_st7735r.c #define MY BIT(7) BIT 98 drivers/staging/fbtft/fb_st7735r.c #define MX BIT(6) BIT 99 drivers/staging/fbtft/fb_st7735r.c #define MV BIT(5) BIT 58 drivers/staging/fbtft/fb_st7789v.c #define MADCTL_BGR BIT(3) /* bitmask for RGB/BGR order */ BIT 59 drivers/staging/fbtft/fb_st7789v.c #define MADCTL_MV BIT(5) /* bitmask for page/column order */ BIT 60 drivers/staging/fbtft/fb_st7789v.c #define MADCTL_MX BIT(6) /* bitmask for column address order */ BIT 61 drivers/staging/fbtft/fb_st7789v.c #define MADCTL_MY BIT(7) /* bitmask for page address order */ BIT 19 drivers/staging/fbtft/fbtft.h #define FBTFT_OF_INIT_CMD BIT(24) BIT 20 drivers/staging/fbtft/fbtft.h #define FBTFT_OF_INIT_DELAY BIT(25) BIT 358 drivers/staging/fbtft/fbtft.h #define DEBUG_DRIVER_INIT_FUNCTIONS BIT(3) BIT 359 drivers/staging/fbtft/fbtft.h #define DEBUG_TIME_FIRST_UPDATE BIT(4) BIT 360 drivers/staging/fbtft/fbtft.h #define DEBUG_TIME_EACH_UPDATE BIT(5) BIT 361 drivers/staging/fbtft/fbtft.h #define DEBUG_DEFERRED_IO BIT(6) BIT 362 drivers/staging/fbtft/fbtft.h #define DEBUG_FBTFT_INIT_FUNCTIONS BIT(7) BIT 365 drivers/staging/fbtft/fbtft.h #define DEBUG_FB_READ BIT(8) BIT 366 drivers/staging/fbtft/fbtft.h #define DEBUG_FB_WRITE BIT(9) BIT 367 drivers/staging/fbtft/fbtft.h #define DEBUG_FB_FILLRECT BIT(10) BIT 368 drivers/staging/fbtft/fbtft.h #define DEBUG_FB_COPYAREA BIT(11) BIT 369 drivers/staging/fbtft/fbtft.h #define DEBUG_FB_IMAGEBLIT BIT(12) BIT 370 drivers/staging/fbtft/fbtft.h #define DEBUG_FB_SETCOLREG BIT(13) BIT 371 drivers/staging/fbtft/fbtft.h #define DEBUG_FB_BLANK BIT(14) BIT 373 drivers/staging/fbtft/fbtft.h #define DEBUG_SYSFS BIT(16) BIT 376 drivers/staging/fbtft/fbtft.h #define DEBUG_BACKLIGHT BIT(17) BIT 377 drivers/staging/fbtft/fbtft.h #define DEBUG_READ BIT(18) BIT 378 drivers/staging/fbtft/fbtft.h #define DEBUG_WRITE BIT(19) BIT 379 drivers/staging/fbtft/fbtft.h #define DEBUG_WRITE_VMEM BIT(20) BIT 380 drivers/staging/fbtft/fbtft.h #define DEBUG_WRITE_REGISTER BIT(21) BIT 381 drivers/staging/fbtft/fbtft.h #define DEBUG_SET_ADDR_WIN BIT(22) BIT 382 drivers/staging/fbtft/fbtft.h #define DEBUG_RESET BIT(23) BIT 383 drivers/staging/fbtft/fbtft.h #define DEBUG_MKDIRTY BIT(24) BIT 384 drivers/staging/fbtft/fbtft.h #define DEBUG_UPDATE_DISPLAY BIT(25) BIT 385 drivers/staging/fbtft/fbtft.h #define DEBUG_INIT_DISPLAY BIT(26) BIT 386 drivers/staging/fbtft/fbtft.h #define DEBUG_BLANK BIT(27) BIT 387 drivers/staging/fbtft/fbtft.h #define DEBUG_REQUEST_GPIOS BIT(28) BIT 388 drivers/staging/fbtft/fbtft.h #define DEBUG_FREE_GPIOS BIT(29) BIT 389 drivers/staging/fbtft/fbtft.h #define DEBUG_REQUEST_GPIOS_MATCH BIT(30) BIT 390 drivers/staging/fbtft/fbtft.h #define DEBUG_VERIFY_GPIOS BIT(31) BIT 468 drivers/staging/fsl-dpaa2/ethsw/dpsw.h #define DPSW_FDB_ENTRY_TYPE_DYNAMIC BIT(0) BIT 469 drivers/staging/fsl-dpaa2/ethsw/dpsw.h #define DPSW_FDB_ENTRY_TYPE_UNICAST BIT(1) BIT 608 drivers/staging/fsl-dpaa2/ethsw/ethsw.c valid = entry->if_mask[idx / 8] & BIT(idx % 8); BIT 297 drivers/staging/gasket/apex_driver.c APEX_BAR2_REG_SCU_3, BIT(6), BIT(6), BIT 343 drivers/staging/gasket/apex_driver.c APEX_BAR2_REG_SCU_3, BIT(6), 0, BIT 39 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_FMT_8 BIT(0) BIT 40 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_FMT_16 BIT(1) BIT 41 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_FMT_24 BIT(2) BIT 42 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_FMT_32 BIT(3) BIT 43 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_FMT_64 BIT(4) BIT 45 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_5512 BIT(0) BIT 46 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_8000 BIT(1) BIT 47 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_11025 BIT(2) BIT 48 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_16000 BIT(3) BIT 49 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_22050 BIT(4) BIT 50 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_32000 BIT(5) BIT 51 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_44100 BIT(6) BIT 52 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_48000 BIT(7) BIT 53 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_64000 BIT(8) BIT 54 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_88200 BIT(9) BIT 55 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_96000 BIT(10) BIT 56 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_176400 BIT(11) BIT 57 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_PCM_RATE_192000 BIT(12) BIT 59 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_DIRECTION_TX BIT(0) BIT 60 drivers/staging/greybus/audio_apbridgea.h #define AUDIO_APBRIDGEA_DIRECTION_RX BIT(1) BIT 101 drivers/staging/greybus/audio_codec.h #define GB_PLAYBACK BIT(0) BIT 102 drivers/staging/greybus/audio_codec.h #define GB_CAPTURE BIT(1) BIT 88 drivers/staging/iio/accel/adis16203.c #define ADIS16203_MSC_CTRL_PWRUP_SELF_TEST BIT(10) BIT 91 drivers/staging/iio/accel/adis16203.c #define ADIS16203_MSC_CTRL_REVERSE_ROT_EN BIT(9) BIT 94 drivers/staging/iio/accel/adis16203.c #define ADIS16203_MSC_CTRL_SELF_TEST_EN BIT(8) BIT 97 drivers/staging/iio/accel/adis16203.c #define ADIS16203_MSC_CTRL_DATA_RDY_EN BIT(2) BIT 100 drivers/staging/iio/accel/adis16203.c #define ADIS16203_MSC_CTRL_ACTIVE_HIGH BIT(1) BIT 103 drivers/staging/iio/accel/adis16203.c #define ADIS16203_MSC_CTRL_DATA_RDY_DIO1 BIT(0) BIT 108 drivers/staging/iio/accel/adis16203.c #define ADIS16203_DIAG_STAT_ALARM2 BIT(9) BIT 111 drivers/staging/iio/accel/adis16203.c #define ADIS16203_DIAG_STAT_ALARM1 BIT(8) BIT 130 drivers/staging/iio/accel/adis16203.c #define ADIS16203_GLOB_CMD_SW_RESET BIT(7) BIT 131 drivers/staging/iio/accel/adis16203.c #define ADIS16203_GLOB_CMD_CLEAR_STAT BIT(4) BIT 132 drivers/staging/iio/accel/adis16203.c #define ADIS16203_GLOB_CMD_FACTORY_CAL BIT(1) BIT 134 drivers/staging/iio/accel/adis16203.c #define ADIS16203_ERROR_ACTIVE BIT(14) BIT 218 drivers/staging/iio/accel/adis16203.c BIT(IIO_CHAN_INFO_CALIBBIAS), 0, 14), BIT 251 drivers/staging/iio/accel/adis16203.c .status_error_mask = BIT(ADIS16203_DIAG_STAT_SELFTEST_FAIL_BIT) | BIT 252 drivers/staging/iio/accel/adis16203.c BIT(ADIS16203_DIAG_STAT_SPI_FAIL_BIT) | BIT 253 drivers/staging/iio/accel/adis16203.c BIT(ADIS16203_DIAG_STAT_FLASH_UPT_BIT) | BIT 254 drivers/staging/iio/accel/adis16203.c BIT(ADIS16203_DIAG_STAT_POWER_HIGH_BIT) | BIT 255 drivers/staging/iio/accel/adis16203.c BIT(ADIS16203_DIAG_STAT_POWER_LOW_BIT), BIT 132 drivers/staging/iio/accel/adis16240.c #define ADIS16240_MSC_CTRL_XYZPEAK_OUT_EN BIT(15) BIT 135 drivers/staging/iio/accel/adis16240.c #define ADIS16240_MSC_CTRL_X_Y_ZPEAK_OUT_EN BIT(14) BIT 138 drivers/staging/iio/accel/adis16240.c #define ADIS16240_MSC_CTRL_SELF_TEST_EN BIT(8) BIT 141 drivers/staging/iio/accel/adis16240.c #define ADIS16240_MSC_CTRL_DATA_RDY_EN BIT(2) BIT 144 drivers/staging/iio/accel/adis16240.c #define ADIS16240_MSC_CTRL_ACTIVE_HIGH BIT(1) BIT 147 drivers/staging/iio/accel/adis16240.c #define ADIS16240_MSC_CTRL_DATA_RDY_DIO2 BIT(0) BIT 152 drivers/staging/iio/accel/adis16240.c #define ADIS16240_DIAG_STAT_ALARM2 BIT(9) BIT 155 drivers/staging/iio/accel/adis16240.c #define ADIS16240_DIAG_STAT_ALARM1 BIT(8) BIT 158 drivers/staging/iio/accel/adis16240.c #define ADIS16240_DIAG_STAT_CPT_BUF_FUL BIT(7) BIT 161 drivers/staging/iio/accel/adis16240.c #define ADIS16240_DIAG_STAT_CHKSUM BIT(6) BIT 167 drivers/staging/iio/accel/adis16240.c #define ADIS16240_DIAG_STAT_PWRON_BUSY BIT(4) BIT 183 drivers/staging/iio/accel/adis16240.c #define ADIS16240_GLOB_CMD_RESUME BIT(8) BIT 184 drivers/staging/iio/accel/adis16240.c #define ADIS16240_GLOB_CMD_SW_RESET BIT(7) BIT 185 drivers/staging/iio/accel/adis16240.c #define ADIS16240_GLOB_CMD_STANDBY BIT(2) BIT 187 drivers/staging/iio/accel/adis16240.c #define ADIS16240_ERROR_ACTIVE BIT(14) BIT 326 drivers/staging/iio/accel/adis16240.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_PEAK), BIT 329 drivers/staging/iio/accel/adis16240.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_PEAK), BIT 332 drivers/staging/iio/accel/adis16240.c BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_PEAK), BIT 375 drivers/staging/iio/accel/adis16240.c .status_error_mask = BIT(ADIS16240_DIAG_STAT_PWRON_FAIL_BIT) | BIT 376 drivers/staging/iio/accel/adis16240.c BIT(ADIS16240_DIAG_STAT_SPI_FAIL_BIT) | BIT 377 drivers/staging/iio/accel/adis16240.c BIT(ADIS16240_DIAG_STAT_FLASH_UPT_BIT) | BIT 378 drivers/staging/iio/accel/adis16240.c BIT(ADIS16240_DIAG_STAT_POWER_HIGH_BIT) | BIT 379 drivers/staging/iio/accel/adis16240.c BIT(ADIS16240_DIAG_STAT_POWER_LOW_BIT), BIT 42 drivers/staging/iio/adc/ad7192.c #define AD7192_COMM_WEN BIT(7) /* Write Enable */ BIT 44 drivers/staging/iio/adc/ad7192.c #define AD7192_COMM_READ BIT(6) /* Read Operation */ BIT 46 drivers/staging/iio/adc/ad7192.c #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */ BIT 49 drivers/staging/iio/adc/ad7192.c #define AD7192_STAT_RDY BIT(7) /* Ready */ BIT 50 drivers/staging/iio/adc/ad7192.c #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */ BIT 51 drivers/staging/iio/adc/ad7192.c #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */ BIT 52 drivers/staging/iio/adc/ad7192.c #define AD7192_STAT_PARITY BIT(4) /* Parity */ BIT 53 drivers/staging/iio/adc/ad7192.c #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */ BIT 54 drivers/staging/iio/adc/ad7192.c #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */ BIT 55 drivers/staging/iio/adc/ad7192.c #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */ BIT 60 drivers/staging/iio/adc/ad7192.c #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */ BIT 62 drivers/staging/iio/adc/ad7192.c #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ BIT 63 drivers/staging/iio/adc/ad7192.c #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/ BIT 64 drivers/staging/iio/adc/ad7192.c #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */ BIT 65 drivers/staging/iio/adc/ad7192.c #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/ BIT 66 drivers/staging/iio/adc/ad7192.c #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */ BIT 67 drivers/staging/iio/adc/ad7192.c #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */ BIT 91 drivers/staging/iio/adc/ad7192.c #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */ BIT 92 drivers/staging/iio/adc/ad7192.c #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */ BIT 95 drivers/staging/iio/adc/ad7192.c #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */ BIT 96 drivers/staging/iio/adc/ad7192.c #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */ BIT 97 drivers/staging/iio/adc/ad7192.c #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */ BIT 98 drivers/staging/iio/adc/ad7192.c #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */ BIT 101 drivers/staging/iio/adc/ad7192.c #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */ BIT 102 drivers/staging/iio/adc/ad7192.c #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */ BIT 103 drivers/staging/iio/adc/ad7192.c #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */ BIT 104 drivers/staging/iio/adc/ad7192.c #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */ BIT 105 drivers/staging/iio/adc/ad7192.c #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */ BIT 106 drivers/staging/iio/adc/ad7192.c #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */ BIT 107 drivers/staging/iio/adc/ad7192.c #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */ BIT 108 drivers/staging/iio/adc/ad7192.c #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */ BIT 134 drivers/staging/iio/adc/ad7192.c #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */ BIT 135 drivers/staging/iio/adc/ad7192.c #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */ BIT 136 drivers/staging/iio/adc/ad7192.c #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */ BIT 137 drivers/staging/iio/adc/ad7192.c #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */ BIT 138 drivers/staging/iio/adc/ad7192.c #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */ BIT 139 drivers/staging/iio/adc/ad7192.c #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */ BIT 140 drivers/staging/iio/adc/ad7192.c #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */ BIT 207 drivers/staging/iio/adc/ad7192.c .read_mask = BIT(6), BIT 772 drivers/staging/iio/adc/ad7192.c BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY); BIT 775 drivers/staging/iio/adc/ad7192.c BIT(IIO_CHAN_INFO_SCALE); BIT 59 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_CONV_INPUT_6CELL_AUX1_3_4 BIT(6) BIT 60 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_CONV_INPUT_6CELL BIT(7) BIT 61 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_CONV_INPUT_SELF_TEST (BIT(7) | BIT(6)) BIT 63 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_CONV_RES_READ_6CELL_AUX1_3_4 BIT(4) BIT 64 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_CONV_RES_READ_6CELL BIT(5) BIT 65 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_CONV_RES_READ_NO (BIT(5) | BIT(4)) BIT 67 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_CONV_START_CS BIT(3) BIT 69 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_CONV_AVG_2 BIT(1) BIT 70 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_CONV_AVG_4 BIT(2) BIT 71 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_CONV_AVG_8 (BIT(2) | BIT(1)) BIT 73 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_HB_PWRDN_SW BIT(0) BIT 75 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_LB_SWRST BIT(7) BIT 77 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_LB_ACQ_TIME_800ns BIT(5) BIT 78 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_LB_ACQ_TIME_1200ns BIT(6) BIT 79 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_LB_ACQ_TIME_1600ns (BIT(6) | BIT(5)) BIT 81 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_LB_MUST_SET BIT(4) BIT 82 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_LB_THERMISTOR_EN BIT(3) BIT 83 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_LB_LOCK_DEV_ADDR BIT(2) BIT 84 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_LB_INC_DEV_ADDR BIT(1) BIT 85 drivers/staging/iio/adc/ad7280a.c #define AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN BIT(0) BIT 87 drivers/staging/iio/adc/ad7280a.c #define AD7280A_ALERT_GEN_STATIC_HIGH BIT(6) BIT 88 drivers/staging/iio/adc/ad7280a.c #define AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN (BIT(7) | BIT(6)) BIT 521 drivers/staging/iio/adc/ad7280a.c chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); BIT 522 drivers/staging/iio/adc/ad7280a.c chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); BIT 539 drivers/staging/iio/adc/ad7280a.c chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); BIT 540 drivers/staging/iio/adc/ad7280a.c chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); BIT 25 drivers/staging/iio/adc/ad7280a.h #define AD7280A_ALERT_REMOVE_VIN5 BIT(2) BIT 26 drivers/staging/iio/adc/ad7280a.h #define AD7280A_ALERT_REMOVE_VIN4_VIN5 BIT(3) BIT 27 drivers/staging/iio/adc/ad7280a.h #define AD7280A_ALERT_REMOVE_AUX5 BIT(0) BIT 28 drivers/staging/iio/adc/ad7280a.h #define AD7280A_ALERT_REMOVE_AUX4_AUX5 BIT(1) BIT 233 drivers/staging/iio/adc/ad7816.c data = BIT(AD7816_TEMP_FLOAT_OFFSET) - data; BIT 1744 drivers/staging/iio/addac/adt7316.c if (stat1 & BIT(0)) BIT 1750 drivers/staging/iio/addac/adt7316.c if (stat1 & BIT(1)) BIT 1756 drivers/staging/iio/addac/adt7316.c if (stat1 & BIT(2)) BIT 1762 drivers/staging/iio/addac/adt7316.c if (stat1 & BIT(3)) BIT 1768 drivers/staging/iio/addac/adt7316.c if (stat1 & BIT(5)) BIT 1774 drivers/staging/iio/addac/adt7316.c if (stat1 & BIT(6)) BIT 1780 drivers/staging/iio/addac/adt7316.c if (stat1 & BIT(7)) BIT 24 drivers/staging/iio/cdc/ad7150.c #define AD7150_STATUS_OUT1 BIT(3) BIT 25 drivers/staging/iio/cdc/ad7150.c #define AD7150_STATUS_OUT2 BIT(5) BIT 39 drivers/staging/iio/cdc/ad7150.c #define AD7150_CFG_FIX BIT(7) BIT 238 drivers/staging/iio/cdc/ad7150.c cfg = ret & ~((0x03 << 5) | BIT(7)); BIT 440 drivers/staging/iio/cdc/ad7150.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 441 drivers/staging/iio/cdc/ad7150.c BIT(IIO_EV_INFO_ENABLE), BIT 445 drivers/staging/iio/cdc/ad7150.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 446 drivers/staging/iio/cdc/ad7150.c BIT(IIO_EV_INFO_ENABLE), BIT 450 drivers/staging/iio/cdc/ad7150.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 451 drivers/staging/iio/cdc/ad7150.c BIT(IIO_EV_INFO_ENABLE), BIT 455 drivers/staging/iio/cdc/ad7150.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 456 drivers/staging/iio/cdc/ad7150.c BIT(IIO_EV_INFO_ENABLE), BIT 460 drivers/staging/iio/cdc/ad7150.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 461 drivers/staging/iio/cdc/ad7150.c BIT(IIO_EV_INFO_ENABLE), BIT 465 drivers/staging/iio/cdc/ad7150.c .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT 466 drivers/staging/iio/cdc/ad7150.c BIT(IIO_EV_INFO_ENABLE), BIT 474 drivers/staging/iio/cdc/ad7150.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 475 drivers/staging/iio/cdc/ad7150.c BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ BIT 41 drivers/staging/iio/cdc/ad7746.c #define AD7746_STATUS_EXCERR BIT(3) BIT 42 drivers/staging/iio/cdc/ad7746.c #define AD7746_STATUS_RDY BIT(2) BIT 43 drivers/staging/iio/cdc/ad7746.c #define AD7746_STATUS_RDYVT BIT(1) BIT 44 drivers/staging/iio/cdc/ad7746.c #define AD7746_STATUS_RDYCAP BIT(0) BIT 47 drivers/staging/iio/cdc/ad7746.c #define AD7746_CAPSETUP_CAPEN BIT(7) BIT 48 drivers/staging/iio/cdc/ad7746.c #define AD7746_CAPSETUP_CIN2 BIT(6) /* AD7746 only */ BIT 49 drivers/staging/iio/cdc/ad7746.c #define AD7746_CAPSETUP_CAPDIFF BIT(5) BIT 50 drivers/staging/iio/cdc/ad7746.c #define AD7746_CAPSETUP_CACHOP BIT(0) BIT 58 drivers/staging/iio/cdc/ad7746.c #define AD7746_VTSETUP_EXTREF BIT(4) BIT 59 drivers/staging/iio/cdc/ad7746.c #define AD7746_VTSETUP_VTSHORT BIT(1) BIT 60 drivers/staging/iio/cdc/ad7746.c #define AD7746_VTSETUP_VTCHOP BIT(0) BIT 63 drivers/staging/iio/cdc/ad7746.c #define AD7746_EXCSETUP_CLKCTRL BIT(7) BIT 64 drivers/staging/iio/cdc/ad7746.c #define AD7746_EXCSETUP_EXCON BIT(6) BIT 65 drivers/staging/iio/cdc/ad7746.c #define AD7746_EXCSETUP_EXCB BIT(5) BIT 66 drivers/staging/iio/cdc/ad7746.c #define AD7746_EXCSETUP_NEXCB BIT(4) BIT 67 drivers/staging/iio/cdc/ad7746.c #define AD7746_EXCSETUP_EXCA BIT(3) BIT 68 drivers/staging/iio/cdc/ad7746.c #define AD7746_EXCSETUP_NEXCA BIT(2) BIT 84 drivers/staging/iio/cdc/ad7746.c #define AD7746_CAPDAC_DACEN BIT(7) BIT 126 drivers/staging/iio/cdc/ad7746.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 127 drivers/staging/iio/cdc/ad7746.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | BIT 128 drivers/staging/iio/cdc/ad7746.c BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 137 drivers/staging/iio/cdc/ad7746.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 138 drivers/staging/iio/cdc/ad7746.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | BIT 139 drivers/staging/iio/cdc/ad7746.c BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 147 drivers/staging/iio/cdc/ad7746.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 155 drivers/staging/iio/cdc/ad7746.c .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), BIT 163 drivers/staging/iio/cdc/ad7746.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 164 drivers/staging/iio/cdc/ad7746.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET), BIT 165 drivers/staging/iio/cdc/ad7746.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 166 drivers/staging/iio/cdc/ad7746.c BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 175 drivers/staging/iio/cdc/ad7746.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 176 drivers/staging/iio/cdc/ad7746.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET), BIT 177 drivers/staging/iio/cdc/ad7746.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 178 drivers/staging/iio/cdc/ad7746.c BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 186 drivers/staging/iio/cdc/ad7746.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 187 drivers/staging/iio/cdc/ad7746.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET), BIT 188 drivers/staging/iio/cdc/ad7746.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 189 drivers/staging/iio/cdc/ad7746.c BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 199 drivers/staging/iio/cdc/ad7746.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT 200 drivers/staging/iio/cdc/ad7746.c BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET), BIT 201 drivers/staging/iio/cdc/ad7746.c .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT 202 drivers/staging/iio/cdc/ad7746.c BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT 61 drivers/staging/iio/frequency/ad9832.c #define AD9832_FREQ BIT(11) BIT 63 drivers/staging/iio/frequency/ad9832.c #define AD9832_SYNC BIT(13) BIT 64 drivers/staging/iio/frequency/ad9832.c #define AD9832_SELSRC BIT(12) BIT 65 drivers/staging/iio/frequency/ad9832.c #define AD9832_SLEEP BIT(13) BIT 66 drivers/staging/iio/frequency/ad9832.c #define AD9832_RESET BIT(12) BIT 67 drivers/staging/iio/frequency/ad9832.c #define AD9832_CLR BIT(11) BIT 158 drivers/staging/iio/frequency/ad9832.c if (phase > BIT(AD9832_PHASE_BITS)) BIT 31 drivers/staging/iio/frequency/ad9834.c #define AD9834_REG_FREQ0 BIT(14) BIT 32 drivers/staging/iio/frequency/ad9834.c #define AD9834_REG_FREQ1 BIT(15) BIT 33 drivers/staging/iio/frequency/ad9834.c #define AD9834_REG_PHASE0 (BIT(15) | BIT(14)) BIT 34 drivers/staging/iio/frequency/ad9834.c #define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13)) BIT 38 drivers/staging/iio/frequency/ad9834.c #define AD9834_B28 BIT(13) BIT 39 drivers/staging/iio/frequency/ad9834.c #define AD9834_HLB BIT(12) BIT 40 drivers/staging/iio/frequency/ad9834.c #define AD9834_FSEL BIT(11) BIT 41 drivers/staging/iio/frequency/ad9834.c #define AD9834_PSEL BIT(10) BIT 42 drivers/staging/iio/frequency/ad9834.c #define AD9834_PIN_SW BIT(9) BIT 43 drivers/staging/iio/frequency/ad9834.c #define AD9834_RESET BIT(8) BIT 44 drivers/staging/iio/frequency/ad9834.c #define AD9834_SLEEP1 BIT(7) BIT 45 drivers/staging/iio/frequency/ad9834.c #define AD9834_SLEEP12 BIT(6) BIT 46 drivers/staging/iio/frequency/ad9834.c #define AD9834_OPBITEN BIT(5) BIT 47 drivers/staging/iio/frequency/ad9834.c #define AD9834_SIGN_PIB BIT(4) BIT 48 drivers/staging/iio/frequency/ad9834.c #define AD9834_DIV2 BIT(3) BIT 49 drivers/staging/iio/frequency/ad9834.c #define AD9834_MODE BIT(1) BIT 54 drivers/staging/iio/frequency/ad9834.c #define RES_MASK(bits) (BIT(bits) - 1) BIT 104 drivers/staging/iio/frequency/ad9834.c unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS); BIT 135 drivers/staging/iio/frequency/ad9834.c if (phase > BIT(AD9834_PHASE_BITS)) BIT 119 drivers/staging/iio/impedance-analyzer/ad5933.c AD5933_CHANNEL(IIO_TEMP, NULL, BIT(IIO_CHAN_INFO_RAW) | BIT 120 drivers/staging/iio/impedance-analyzer/ad5933.c BIT(IIO_CHAN_INFO_SCALE), AD5933_REG_TEMP_DATA, -1, 14), BIT 286 drivers/staging/iio/impedance-analyzer/ad5933.c do_div(freqreg, BIT(27)); BIT 422 drivers/staging/iio/impedance-analyzer/ad5933.c val = (val >> 1) | BIT(9); BIT 183 drivers/staging/iio/meter/ade7854.c val |= BIT(7); /* Software Chip Reset */ BIT 422 drivers/staging/iio/meter/ade7854.c irqen |= BIT(17); /* 1: interrupt enabled when all periodical BIT 426 drivers/staging/iio/meter/ade7854.c irqen &= ~BIT(17); BIT 563 drivers/staging/iio/resolver/ad2s1210.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 568 drivers/staging/iio/resolver/ad2s1210.c .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), BIT 117 drivers/staging/kpc2000/kpc2000_i2c.c #define FEATURE_SMBUS_PEC BIT(0) BIT 118 drivers/staging/kpc2000/kpc2000_i2c.c #define FEATURE_BLOCK_BUFFER BIT(1) BIT 119 drivers/staging/kpc2000/kpc2000_i2c.c #define FEATURE_BLOCK_PROC BIT(2) BIT 120 drivers/staging/kpc2000/kpc2000_i2c.c #define FEATURE_I2C_BLOCK_READ BIT(3) BIT 122 drivers/staging/kpc2000/kpc2000_i2c.c #define FEATURE_IDF BIT(15) BIT 17 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.c #define KPC_DMA_NUM_MINORS BIT(MINORBITS) BIT 69 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_IRQ_ENABLE BIT(0) BIT 70 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_IRQ_ACTIVE BIT(1) BIT 71 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_DESC_COMPLETE BIT(2) BIT 72 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_DESC_ALIGN_ERR BIT(3) BIT 73 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_DESC_FETCH_ERR BIT(4) BIT 74 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_SW_ABORT_ERR BIT(5) BIT 75 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_DESC_CHAIN_END BIT(7) BIT 76 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_DMA_ENABLE BIT(8) BIT 77 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_DMA_RUNNING BIT(10) BIT 78 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_DMA_WAITING BIT(11) BIT 79 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_DMA_WAITING_PERSIST BIT(12) BIT 80 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_DMA_RESET_REQUEST BIT(14) BIT 81 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define ENG_CTL_DMA_RESET BIT(15) BIT 126 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_CTL_SOP BIT(7) BIT 127 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_CTL_EOP BIT(6) BIT 128 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_CTL_AFIFO BIT(2) BIT 129 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_CTL_IRQONERR BIT(1) BIT 130 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_CTL_IRQONDONE BIT(0) BIT 132 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_STS_SOP BIT(7) BIT 133 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_STS_EOP BIT(6) BIT 134 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_STS_ERROR BIT(4) BIT 135 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_STS_USMSZ BIT(3) BIT 136 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_STS_USLSZ BIT(2) BIT 137 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_STS_SHORT BIT(1) BIT 138 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_STS_COMPLETE BIT(0) BIT 140 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_ESTS_ECRC BIT(2) BIT 141 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_ESTS_POISON BIT(1) BIT 142 drivers/staging/kpc2000/kpc_dma/kpc_dma_driver.h #define DMA_DESC_ESTS_UNSUCCESSFUL BIT(0) BIT 55 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_TYPE_HMAC_MD5_RC4 BIT(0) BIT 56 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_TYPE_HMAC_SHA1_AES BIT(1) BIT 57 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_KEY_TYPE BIT(3) /* 1 = Pairwise, 0 = Group key */ BIT 61 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_INSTALL BIT(6) /* pairwise */ BIT 62 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_TXRX BIT(6) /* group */ BIT 63 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_ACK BIT(7) BIT 64 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_MIC BIT(8) BIT 65 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_SECURE BIT(9) BIT 66 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_ERROR BIT(10) BIT 67 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_REQUEST BIT(11) BIT 68 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_ENCR_KEY_DATA BIT(12) /* IEEE 802.11i/RSN only */ BIT 63 drivers/staging/ks7010/ks7010_sdio.c #define INT_GCR_B BIT(7) BIT 64 drivers/staging/ks7010/ks7010_sdio.c #define INT_GCR_A BIT(6) BIT 65 drivers/staging/ks7010/ks7010_sdio.c #define INT_WRITE_STATUS BIT(5) BIT 66 drivers/staging/ks7010/ks7010_sdio.c #define INT_WRITE_INDEX BIT(4) BIT 67 drivers/staging/ks7010/ks7010_sdio.c #define INT_WRITE_SIZE BIT(3) BIT 68 drivers/staging/ks7010/ks7010_sdio.c #define INT_READ_STATUS BIT(2) BIT 69 drivers/staging/ks7010/ks7010_sdio.c #define INT_READ_INDEX BIT(1) BIT 70 drivers/staging/ks7010/ks7010_sdio.c #define INT_READ_SIZE BIT(0) BIT 63 drivers/staging/ks7010/ks_wlan.h #define SME_MODE_SET BIT(0) BIT 64 drivers/staging/ks7010/ks_wlan.h #define SME_RTS BIT(1) BIT 65 drivers/staging/ks7010/ks_wlan.h #define SME_FRAG BIT(2) BIT 66 drivers/staging/ks7010/ks_wlan.h #define SME_WEP_FLAG BIT(3) BIT 67 drivers/staging/ks7010/ks_wlan.h #define SME_WEP_INDEX BIT(4) BIT 68 drivers/staging/ks7010/ks_wlan.h #define SME_WEP_VAL1 BIT(5) BIT 69 drivers/staging/ks7010/ks_wlan.h #define SME_WEP_VAL2 BIT(6) BIT 70 drivers/staging/ks7010/ks_wlan.h #define SME_WEP_VAL3 BIT(7) BIT 71 drivers/staging/ks7010/ks_wlan.h #define SME_WEP_VAL4 BIT(8) BIT 73 drivers/staging/ks7010/ks_wlan.h #define SME_RSN BIT(9) BIT 74 drivers/staging/ks7010/ks_wlan.h #define SME_RSN_MULTICAST BIT(10) BIT 75 drivers/staging/ks7010/ks_wlan.h #define SME_RSN_UNICAST BIT(11) BIT 76 drivers/staging/ks7010/ks_wlan.h #define SME_RSN_AUTH BIT(12) BIT 78 drivers/staging/ks7010/ks_wlan.h #define SME_AP_SCAN BIT(13) BIT 79 drivers/staging/ks7010/ks_wlan.h #define SME_MULTICAST BIT(14) BIT 55 drivers/staging/media/allegro-dvt/allegro-core.c #define AL5_MCU_RESET_SOFT BIT(0) BIT 56 drivers/staging/media/allegro-dvt/allegro-core.c #define AL5_MCU_RESET_REGS BIT(1) BIT 58 drivers/staging/media/allegro-dvt/allegro-core.c #define AL5_MCU_RESET_MODE_SLEEP BIT(0) BIT 59 drivers/staging/media/allegro-dvt/allegro-core.c #define AL5_MCU_RESET_MODE_HALT BIT(1) BIT 61 drivers/staging/media/allegro-dvt/allegro-core.c #define AL5_MCU_STA_SLEEP BIT(0) BIT 73 drivers/staging/media/allegro-dvt/allegro-core.c #define AL5_ITC_CPU_IRQ_STA_TRIGGERED BIT(0) BIT 331 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_WPP BIT(0) BIT 332 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_TILE BIT(1) BIT 333 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_LF BIT(2) BIT 334 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_LF_X_SLICE BIT(3) BIT 335 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_LF_X_TILE BIT(4) BIT 336 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_SCL_LST BIT(5) BIT 337 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_CONST_INTRA_PRED BIT(6) BIT 338 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_QP_TAB_RELATIVE BIT(7) BIT 339 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_FIX_PREDICTOR BIT(8) BIT 340 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_CUSTOM_LDA BIT(9) BIT 341 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_ENABLE_AUTO_QP BIT(10) BIT 342 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_ADAPT_AUTO_QP BIT(11) BIT 343 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_TRANSFO_SKIP BIT(13) BIT 344 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_FORCE_REC BIT(15) BIT 345 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_FORCE_MV_OUT BIT(16) BIT 346 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_FORCE_MV_CLIP BIT(17) BIT 347 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_LOWLAT_SYNC BIT(18) BIT 348 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_LOWLAT_INT BIT(19) BIT 349 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_RDO_COST_MODE BIT(20) BIT 459 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_USE_QP_TABLE BIT(0) BIT 460 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_FORCE_LOAD BIT(1) BIT 461 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_USE_L2 BIT(2) BIT 462 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_DISABLE_INTRA BIT(3) BIT 463 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_DEPENDENT_SLICES BIT(4) BIT 471 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_SCENE_CHANGE BIT(0) BIT 472 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_RESTART_GOP BIT(1) BIT 473 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_USE_LONG_TERM BIT(2) BIT 474 drivers/staging/media/allegro-dvt/allegro-core.c #define AL_OPT_UPDATE_PARAMS BIT(3) BIT 887 drivers/staging/media/allegro-dvt/allegro-core.c regmap_write(dev->regmap, AL5_MCU_INTERRUPT, BIT(0)); BIT 1024 drivers/staging/media/allegro-dvt/allegro-core.c msg.constraint_set_flags = BIT(1); BIT 1028 drivers/staging/media/allegro-dvt/allegro-core.c msg.sps_param = BIT(20) | 0x4a; BIT 1029 drivers/staging/media/allegro-dvt/allegro-core.c msg.pps_param = BIT(2); BIT 1873 drivers/staging/media/allegro-dvt/allegro-core.c return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, BIT(0)); BIT 1903 drivers/staging/media/allegro-dvt/allegro-core.c err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, BIT(0)); BIT 48 drivers/staging/media/hantro/hantro.h #define HANTRO_JPEG_ENCODER BIT(0) BIT 50 drivers/staging/media/hantro/hantro.h #define HANTRO_MPEG2_DECODER BIT(16) BIT 51 drivers/staging/media/hantro/hantro.h #define HANTRO_VP8_DECODER BIT(17) BIT 52 drivers/staging/media/hantro/hantro.h #define HANTRO_H264_DECODER BIT(18) BIT 310 drivers/staging/media/hantro/hantro.h if (hantro_debug & BIT(level)) \ BIT 147 drivers/staging/media/hantro/hantro_g1_h264_dec.c dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); BIT 150 drivers/staging/media/hantro/hantro_g1_h264_dec.c dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); BIT 23 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_E(v) ((v) ? BIT(0) : 0) BIT 26 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) BIT 27 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) BIT 28 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) BIT 29 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) BIT 30 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) BIT 31 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) BIT 33 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) BIT 34 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) BIT 35 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(8) : 0) BIT 36 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(6) : 0) BIT 37 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_SCMD_DIS(v) ((v) ? BIT(5) : 0) BIT 41 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_RLC_MODE_E(v) ((v) ? BIT(27) : 0) BIT 42 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_PIC_INTERLACE_E(v) ((v) ? BIT(23) : 0) BIT 43 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(22) : 0) BIT 44 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_PIC_B_E(v) ((v) ? BIT(21) : 0) BIT 45 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_PIC_INTER_E(v) ((v) ? BIT(20) : 0) BIT 46 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(19) : 0) BIT 47 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_FWD_INTERLACE_E(v) ((v) ? BIT(18) : 0) BIT 48 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_FILTERING_DIS(v) ((v) ? BIT(14) : 0) BIT 49 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_WRITE_MVS_E(v) ((v) ? BIT(12) : 0) BIT 54 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0) BIT 55 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_TOPFIELDFIRST_E(v) ((v) ? BIT(5) : 0) BIT 58 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_QSCALE_TYPE(v) ((v) ? BIT(24) : 0) BIT 59 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_CON_MV_E(v) ((v) ? BIT(4) : 0) BIT 61 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_INTRA_VLC_TAB(v) ((v) ? BIT(1) : 0) BIT 62 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_FRAME_PRED_DCT(v) ((v) ? BIT(0) : 0) BIT 67 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_ALT_SCAN_FLAG_E(v) ((v) ? BIT(19) : 0) BIT 72 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_MV_ACCURACY_FWD(v) ((v) ? BIT(2) : 0) BIT 73 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_MV_ACCURACY_BWD(v) ((v) ? BIT(1) : 0) BIT 14 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24) BIT 15 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18) BIT 16 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17) BIT 17 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16) BIT 18 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15) BIT 19 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14) BIT 20 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13) BIT 21 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12) BIT 22 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_IRQ BIT(8) BIT 23 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) BIT 24 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_INTERRUPT_DEC_E BIT(0) BIT 27 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_TIMEOUT_E BIT(23) BIT 28 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_STRSWAP32_E BIT(22) BIT 29 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_STRENDIAN_E BIT(21) BIT 30 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_INSWAP32_E BIT(20) BIT 31 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_OUTSWAP32_E BIT(19) BIT 32 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_DATA_DISC_E BIT(18) BIT 33 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_TILED_MODE_MSB BIT(17) BIT 34 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_OUT_TILED_E BIT(17) BIT 36 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_CLK_GATE_E BIT(10) BIT 37 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_IN_ENDIAN BIT(9) BIT 38 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_OUT_ENDIAN BIT(8) BIT 40 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_TILED_MODE_LSB BIT(7) BIT 41 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_ADV_PRE_DIS BIT(6) BIT 42 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_CONFIG_DEC_SCMD_DIS BIT(5) BIT 46 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_RLC_MODE_E BIT(27) BIT 47 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_SKIP_MODE BIT(26) BIT 48 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_DIVX3_E BIT(25) BIT 49 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_PJPEG_E BIT(24) BIT 50 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_PIC_INTERLACE_E BIT(23) BIT 51 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_PIC_FIELDMODE_E BIT(22) BIT 52 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_PIC_B_E BIT(21) BIT 53 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_PIC_INTER_E BIT(20) BIT 54 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_PIC_TOPFIELD_E BIT(19) BIT 55 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_FWD_INTERLACE_E BIT(18) BIT 56 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_SORENSON_E BIT(17) BIT 57 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_REF_TOPFIELD_E BIT(16) BIT 58 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_DEC_OUT_DIS BIT(15) BIT 59 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_FILTERING_DIS BIT(14) BIT 60 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_WEBP_E BIT(13) BIT 61 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_MVC_E BIT(13) BIT 62 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_PIC_FIXED_QUANT BIT(13) BIT 63 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_WRITE_MVS_E BIT(12) BIT 64 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_REFTOPFIRST_E BIT(11) BIT 65 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_SEQ_MBAFF_E BIT(10) BIT 66 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_PICORD_COUNT_E BIT(9) BIT 67 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL0_DEC_AHB_HLOCK_E BIT(8) BIT 74 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL1_ALT_SCAN_E BIT(6) BIT 75 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL1_TOPFIELDFIRST_E BIT(5) BIT 79 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL1_PIC_REFER_FLAG BIT(0) BIT 82 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_SYNC_MARKER_E BIT(25) BIT 83 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_TYPE1_QUANT_E BIT(24) BIT 86 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E BIT(0) BIT 89 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_DQ_PROFILE BIT(24) BIT 90 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_DQBI_LEVEL BIT(23) BIT 91 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_RANGE_RED_FRM_E BIT(22) BIT 92 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_FAST_UVMC_E BIT(20) BIT 93 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_TRANSDCTAB BIT(17) BIT 101 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_QSCALE_TYPE BIT(24) BIT 102 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_CON_MV_E BIT(4) BIT 104 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_INTRA_VLC_TAB BIT(1) BIT 105 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_FRAME_PRED_DCT BIT(0) BIT 108 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_JPEG_FILRIGHT_E BIT(7) BIT 109 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_JPEG_STREAM_ALL BIT(6) BIT 110 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_CR_AC_VLCTABLE BIT(5) BIT 111 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_CB_AC_VLCTABLE BIT(4) BIT 112 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_CR_DC_VLCTABLE BIT(3) BIT 113 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_CB_DC_VLCTABLE BIT(2) BIT 114 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_CR_DC_VLCTABLE3 BIT(1) BIT 115 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_CB_DC_VLCTABLE3 BIT(0) BIT 117 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_HUFFMAN_E BIT(17) BIT 118 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL2_MULTISTREAM_E BIT(16) BIT 124 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL3_START_CODE_E BIT(31) BIT 126 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL3_CH_8PIX_ILEAV_E BIT(24) BIT 130 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_CABAC_E BIT(31) BIT 131 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_BLACKWHITE_E BIT(30) BIT 132 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(29) BIT 133 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_WEIGHT_PRED_E BIT(28) BIT 135 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_AVS_H264_H_EXT BIT(25) BIT 138 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_BITPLANE0_E BIT(31) BIT 139 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_BITPLANE1_E BIT(30) BIT 140 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_BITPLANE2_E BIT(29) BIT 143 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_TTMBF BIT(19) BIT 145 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_VC1_HEIGHT_EXT BIT(13) BIT 146 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_BILIN_MC_E BIT(12) BIT 147 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_UNIQP_E BIT(11) BIT 148 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_HALFQP_E BIT(10) BIT 150 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_2ND_BYTE_EMUL_E BIT(7) BIT 151 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_DQUANT_E BIT(6) BIT 152 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_VC1_ADV_E BIT(5) BIT 153 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_PJPEG_FILDOWN_E BIT(26) BIT 154 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_PJPEG_WDIV8 BIT(25) BIT 155 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_PJPEG_HDIV8 BIT(24) BIT 162 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_CH_MV_RES BIT(13) BIT 165 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL4_VP7_VERSION BIT(5) BIT 167 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL5_CONST_INTRA_E BIT(31) BIT 168 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL5_FILT_CTRL_PRES BIT(30) BIT 169 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(29) BIT 170 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL5_8X8TRANS_FLAG_E BIT(28) BIT 172 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL5_IDR_PIC_E BIT(16) BIT 178 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL5_VARIANCE_TEST_E BIT(13) BIT 181 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL5_DIVX_IDCT_E BIT(8) BIT 195 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL6_ICOMP0_E BIT(24) BIT 208 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_FWD_PIC1_ICOMP1_E BIT(24) BIT 212 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1) BIT 213 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_FWD_PIC1_SEGMENT_E BIT(0) BIT 221 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_DEC_CTRL7_ICOMP2_E BIT(24) BIT 232 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_ADDR_REF_FIELD_E BIT(1) BIT 233 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_ADDR_REF_TOPC_E BIT(0) BIT 235 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_REF_PIC_FILT_TYPE_E BIT(31) BIT 288 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_REF_BUF_CTRL_REFBU_E BIT(31) BIT 291 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_REF_BUF_CTRL_REFBU_EVAL_E BIT(13) BIT 292 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_REF_BUF_CTRL_REFBU_FPARMOD_E BIT(12) BIT 295 drivers/staging/media/hantro/hantro_g1_regs.h #define G1_REG_REF_BUF_CTRL2_REFBU2_BUF_E BIT(31) BIT 14 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_INTERRUPT_FRAME_RDY BIT(2) BIT 15 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_INTERRUPT_DIS_BIT BIT(1) BIT 16 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_INTERRUPT_BIT BIT(0) BIT 18 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_AXI_CTRL_OUTPUT_SWAP16 BIT(15) BIT 19 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_AXI_CTRL_INPUT_SWAP16 BIT(14) BIT 21 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_AXI_CTRL_GATE_BIT BIT(4) BIT 22 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_AXI_CTRL_OUTPUT_SWAP32 BIT(3) BIT 23 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_AXI_CTRL_INPUT_SWAP32 BIT(2) BIT 24 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_AXI_CTRL_OUTPUT_SWAP8 BIT(1) BIT 25 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_AXI_CTRL_INPUT_SWAP8 BIT(0) BIT 36 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_ENC_CTRL_TIMEOUT_EN BIT(31) BIT 37 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_ENC_CTRL_NAL_MODE_BIT BIT(29) BIT 46 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_ENC_CTRL_EN_BIT BIT(0) BIT 59 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_ENC_CTRL0_CONSTR_INTRA_PRED BIT(0) BIT 67 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_ENC_CTRL2_DISABLE_QUARTER_PIXMV BIT(22) BIT 68 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_ENC_CTRL2_TRANS8X8_MODE_EN BIT(21) BIT 70 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_ENC_CTRL2_ENTROPY_CODING_MODE BIT(18) BIT 71 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_ENC_CTRL2_H264_INTER4X4_MODE BIT(17) BIT 72 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_ENC_CTRL2_H264_STREAM_MODE BIT(16) BIT 75 drivers/staging/media/hantro/hantro_h1_regs.h #define H1_REG_ENC_CTRL3_MUTIMV_EN BIT(30) BIT 23 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) BIT 25 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) BIT 26 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) BIT 27 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) BIT 39 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0) BIT 40 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0) BIT 41 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0) BIT 42 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0) BIT 43 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0) BIT 44 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0) BIT 46 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0) BIT 51 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0) BIT 52 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0) BIT 53 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0) BIT 54 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_PIC_B_E(v) ((v) ? BIT(15) : 0) BIT 55 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_PIC_INTER_E(v) ((v) ? BIT(14) : 0) BIT 56 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0) BIT 57 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_FWD_INTERLACE_E(v) ((v) ? BIT(12) : 0) BIT 58 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0) BIT 59 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0) BIT 60 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0) BIT 64 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0) BIT 65 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_TOPFIELDFIRST_E(v) ((v) ? BIT(5) : 0) BIT 68 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_QSCALE_TYPE(v) ((v) ? BIT(24) : 0) BIT 69 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_CON_MV_E(v) ((v) ? BIT(4) : 0) BIT 71 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_INTRA_VLC_TAB(v) ((v) ? BIT(1) : 0) BIT 72 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_FRAME_PRED_DCT(v) ((v) ? BIT(0) : 0) BIT 74 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_ALT_SCAN_FLAG_E(v) ((v) ? BIT(19) : 0) BIT 79 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_MV_ACCURACY_FWD(v) ((v) ? BIT(2) : 0) BIT 80 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_MV_ACCURACY_BWD(v) ((v) ? BIT(1) : 0) BIT 27 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_CONFIG_DEC_STRENDIAN_E BIT(5) BIT 28 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_CONFIG_DEC_STRSWAP32_E BIT(4) BIT 29 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_CONFIG_DEC_OUTSWAP32_E BIT(3) BIT 30 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_CONFIG_DEC_INSWAP32_E BIT(2) BIT 31 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_CONFIG_DEC_OUT_ENDIAN BIT(1) BIT 32 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_CONFIG_DEC_IN_ENDIAN BIT(0) BIT 36 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_DEC_CTRL0_PIC_INTER_E BIT(14) BIT 37 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_CONFIG_DEC_TIMEOUT_E BIT(5) BIT 38 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_CONFIG_DEC_CLK_GATE_E BIT(4) BIT 45 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT BIT(13) BIT 46 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_DEC_CTRL4_BILIN_MC_E BIT(12) BIT 57 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_REF_PIC_FILT_TYPE_E BIT(31) BIT 61 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_VP8_GREF_SIGN_BIAS BIT(0) BIT 62 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_VP8_AREF_SIGN_BIAS BIT(0) BIT 68 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1) BIT 69 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c #define VDPU_REG_FWD_PIC1_SEGMENT_E BIT(0) BIT 93 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_AXI_CTRL_BIRST_DISABLE BIT(0) BIT 103 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_DISABLE_QUARTER_PIXEL_MV BIT(28) BIT 106 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_ENTROPY_CODING_MODE BIT(20) BIT 107 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_H264_TRANS8X8_MODE BIT(17) BIT 108 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_H264_INTER4X4_MODE BIT(16) BIT 109 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_H264_STREAM_MODE BIT(15) BIT 160 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_VP8_SEGMENT_MAP_UPDATE BIT(30) BIT 161 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_VP8_SEGMENT_EN BIT(29) BIT 162 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_VP8_MV_REF_IDX2_EN BIT(28) BIT 188 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_SIZE_TABLE_PRESENT BIT(0) BIT 197 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_FILTER_DISABLE BIT(5) BIT 199 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_CONSTRAINED_INTRA_PREDICTION BIT(0) BIT 237 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_SPLIT_MV_MODE_EN BIT(0) BIT 251 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_MVC_ANCHOR_PIC_FLAG BIT(7) BIT 254 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_MVC_INTER_VIEW_FLAG BIT(0) BIT 263 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_ENCODE_ENABLE BIT(0) BIT 268 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INPUT_SWAP8 BIT(31) BIT 269 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INPUT_SWAP16 BIT(30) BIT 270 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INPUT_SWAP32 BIT(29) BIT 271 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_OUTPUT_SWAP8 BIT(28) BIT 272 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_OUTPUT_SWAP16 BIT(27) BIT 273 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_OUTPUT_SWAP32 BIT(26) BIT 274 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_TEST_IRQ BIT(24) BIT 276 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_TEST_REG BIT(19) BIT 277 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_TEST_MEMORY BIT(18) BIT 289 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_NON BIT(28) BIT 290 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_MV_WRITE_EN BIT(24) BIT 291 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_RECON_WRITE_DIS BIT(20) BIT 292 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_SLICE_READY_EN BIT(16) BIT 293 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_CLK_GATING_EN BIT(12) BIT 294 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_TIMEOUT_EN BIT(10) BIT 295 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_RESET BIT(9) BIT 296 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_DIS_BIT BIT(8) BIT 297 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_TIMEOUT BIT(6) BIT 298 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_BUFFER_FULL BIT(5) BIT 299 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_BUS_ERROR BIT(4) BIT 300 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_FUSE BIT(3) BIT 301 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_SLICE_READY BIT(2) BIT 302 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_FRAME_READY BIT(1) BIT 303 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VEPU_REG_INTERRUPT_BIT BIT(0) BIT 313 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_TILED_MODE_LSB BIT(12) BIT 314 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_ADV_PRE_DIS BIT(11) BIT 315 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_SCMD_DIS BIT(10) BIT 316 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_SKIP_MODE BIT(9) BIT 317 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_FILTERING_DIS BIT(8) BIT 318 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_PIC_FIXED_QUANT BIT(7) BIT 320 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_TILED_MODE_MSB(x) BIT(0) BIT 321 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_OUT_TILED_E BIT(0) BIT 324 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_STREAM_LEN_HI BIT(24) BIT 333 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_STRENDIAN_E BIT(5) BIT 334 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_STRSWAP32_E BIT(4) BIT 335 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_OUTSWAP32_E BIT(3) BIT 336 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_INSWAP32_E BIT(2) BIT 337 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_OUT_ENDIAN BIT(1) BIT 338 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_IN_ENDIAN BIT(0) BIT 340 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_TIMEOUT BIT(13) BIT 341 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_ERROR_INT BIT(12) BIT 342 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_PIC_INF BIT(10) BIT 343 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_SLICE_INT BIT(9) BIT 344 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_ASO_INT BIT(8) BIT 345 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_BUFFER_INT BIT(6) BIT 346 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_BUS_INT BIT(5) BIT 347 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_RDY_INT BIT(4) BIT 348 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_IRQ_DIS BIT(1) BIT 349 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_IRQ BIT(0) BIT 351 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_AXI_DEC_SEL BIT(23) BIT 352 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_DATA_DISC_E BIT(22) BIT 353 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_PARAL_BUS_E(x) BIT(21) BIT 358 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_AHB_HLOCK_E BIT(31) BIT 359 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CACHE_E BIT(29) BIT 360 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_PREFETCH_SINGLE_CHANNEL_E BIT(28) BIT 361 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTRA_3_CYCLE_ENHANCE BIT(27) BIT 362 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTRA_DOUBLE_SPEED BIT(26) BIT 363 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTER_DOUBLE_SPEED BIT(25) BIT 364 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL3_START_CODE_E BIT(22) BIT 365 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL3_CH_8PIX_ILEAV_E BIT(21) BIT 366 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_RLC_MODE_E BIT(20) BIT 367 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_DIVX3_E BIT(19) BIT 368 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_PJPEG_E BIT(18) BIT 369 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_PIC_INTERLACE_E BIT(17) BIT 370 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_PIC_FIELDMODE_E BIT(16) BIT 371 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_PIC_B_E BIT(15) BIT 372 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_PIC_INTER_E BIT(14) BIT 373 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_PIC_TOPFIELD_E BIT(13) BIT 374 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_FWD_INTERLACE_E BIT(12) BIT 375 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_SORENSON_E BIT(11) BIT 376 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_WRITE_MVS_E BIT(10) BIT 377 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_REF_TOPFIELD_E BIT(9) BIT 378 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_REFTOPFIRST_E BIT(8) BIT 379 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_SEQ_MBAFF_E BIT(7) BIT 380 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_PICORD_COUNT_E BIT(6) BIT 381 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_TIMEOUT_E BIT(5) BIT 382 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_CONFIG_DEC_CLK_GATE_E BIT(4) BIT 383 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL0_DEC_OUT_DIS BIT(2) BIT 384 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_REF_BUF_CTRL2_REFBU2_BUF_E BIT(1) BIT 385 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_INTERRUPT_DEC_E BIT(0) BIT 408 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_ADDR_REF_FIELD_E BIT(1) BIT 409 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_ADDR_REF_TOPC_E BIT(0) BIT 464 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL5_FILT_CTRL_PRES BIT(31) BIT 465 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(30) BIT 477 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL5_IDR_PIC_E BIT(8) BIT 478 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(7) BIT 479 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL4_BLACKWHITE_E BIT(6) BIT 480 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL4_CABAC_E BIT(5) BIT 481 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL4_WEIGHT_PRED_E BIT(4) BIT 482 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL5_CONST_INTRA_E BIT(3) BIT 483 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL5_8X8TRANS_FLAG_E BIT(2) BIT 484 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL2_TYPE1_QUANT_E BIT(1) BIT 485 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL2_FIELDPIC_FLAG_E BIT(0) BIT 496 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT BIT(13) BIT 497 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_DEC_CTRL4_BILIN_MC_E BIT(12) BIT 539 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_REF_PIC_FILT_TYPE_E BIT(31) BIT 551 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_VP8_GREF_SIGN_BIAS BIT(0) BIT 552 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_VP8_AREF_SIGN_BIAS BIT(0) BIT 558 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1) BIT 559 drivers/staging/media/hantro/rk3399_vpu_regs.h #define VDPU_REG_FWD_PIC1_SEGMENT_E BIT(0) BIT 285 drivers/staging/media/imx/imx-media.h #define IMX_MEDIA_GRP_ID_CSI2 BIT(8) BIT 286 drivers/staging/media/imx/imx-media.h #define IMX_MEDIA_GRP_ID_CSI BIT(9) BIT 289 drivers/staging/media/imx/imx-media.h #define IMX_MEDIA_GRP_ID_IPU_CSI0 BIT(IMX_MEDIA_GRP_ID_IPU_CSI_BIT) BIT 291 drivers/staging/media/imx/imx-media.h #define IMX_MEDIA_GRP_ID_IPU_VDIC BIT(12) BIT 292 drivers/staging/media/imx/imx-media.h #define IMX_MEDIA_GRP_ID_IPU_IC_PRP BIT(13) BIT 293 drivers/staging/media/imx/imx-media.h #define IMX_MEDIA_GRP_ID_IPU_IC_PRPENC BIT(14) BIT 294 drivers/staging/media/imx/imx-media.h #define IMX_MEDIA_GRP_ID_IPU_IC_PRPVF BIT(15) BIT 65 drivers/staging/media/imx/imx6-mipi-csi2.c #define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n)) BIT 66 drivers/staging/media/imx/imx6-mipi-csi2.c #define PHY_RXCLKACTIVEHS BIT(8) BIT 67 drivers/staging/media/imx/imx6-mipi-csi2.c #define PHY_RXULPSCLKNOT BIT(9) BIT 68 drivers/staging/media/imx/imx6-mipi-csi2.c #define PHY_STOPSTATECLK BIT(10) BIT 76 drivers/staging/media/imx/imx6-mipi-csi2.c #define PHY_TESTCLR BIT(0) BIT 77 drivers/staging/media/imx/imx6-mipi-csi2.c #define PHY_TESTCLK BIT(1) BIT 79 drivers/staging/media/imx/imx6-mipi-csi2.c #define PHY_TESTEN BIT(16) BIT 86 drivers/staging/media/imx/imx6-mipi-csi2.c #define CSI2IPU_YUV422_YUYV BIT(2) BIT 42 drivers/staging/media/imx/imx7-media-csi.c #define BIT_SWAP16_EN BIT(31) BIT 43 drivers/staging/media/imx/imx7-media-csi.c #define BIT_EXT_VSYNC BIT(30) BIT 44 drivers/staging/media/imx/imx7-media-csi.c #define BIT_EOF_INT_EN BIT(29) BIT 45 drivers/staging/media/imx/imx7-media-csi.c #define BIT_PRP_IF_EN BIT(28) BIT 46 drivers/staging/media/imx/imx7-media-csi.c #define BIT_CCIR_MODE BIT(27) BIT 47 drivers/staging/media/imx/imx7-media-csi.c #define BIT_COF_INT_EN BIT(26) BIT 48 drivers/staging/media/imx/imx7-media-csi.c #define BIT_SF_OR_INTEN BIT(25) BIT 49 drivers/staging/media/imx/imx7-media-csi.c #define BIT_RF_OR_INTEN BIT(24) BIT 50 drivers/staging/media/imx/imx7-media-csi.c #define BIT_SFF_DMA_DONE_INTEN BIT(22) BIT 51 drivers/staging/media/imx/imx7-media-csi.c #define BIT_STATFF_INTEN BIT(21) BIT 52 drivers/staging/media/imx/imx7-media-csi.c #define BIT_FB2_DMA_DONE_INTEN BIT(20) BIT 53 drivers/staging/media/imx/imx7-media-csi.c #define BIT_FB1_DMA_DONE_INTEN BIT(19) BIT 54 drivers/staging/media/imx/imx7-media-csi.c #define BIT_RXFF_INTEN BIT(18) BIT 55 drivers/staging/media/imx/imx7-media-csi.c #define BIT_SOF_POL BIT(17) BIT 56 drivers/staging/media/imx/imx7-media-csi.c #define BIT_SOF_INTEN BIT(16) BIT 58 drivers/staging/media/imx/imx7-media-csi.c #define BIT_HSYNC_POL BIT(11) BIT 59 drivers/staging/media/imx/imx7-media-csi.c #define BIT_CCIR_EN BIT(10) BIT 60 drivers/staging/media/imx/imx7-media-csi.c #define BIT_MCLKEN BIT(9) BIT 61 drivers/staging/media/imx/imx7-media-csi.c #define BIT_FCC BIT(8) BIT 62 drivers/staging/media/imx/imx7-media-csi.c #define BIT_PACK_DIR BIT(7) BIT 63 drivers/staging/media/imx/imx7-media-csi.c #define BIT_CLR_STATFIFO BIT(6) BIT 64 drivers/staging/media/imx/imx7-media-csi.c #define BIT_CLR_RXFIFO BIT(5) BIT 65 drivers/staging/media/imx/imx7-media-csi.c #define BIT_GCLK_MODE BIT(4) BIT 66 drivers/staging/media/imx/imx7-media-csi.c #define BIT_INV_DATA BIT(3) BIT 67 drivers/staging/media/imx/imx7-media-csi.c #define BIT_INV_PCLK BIT(2) BIT 68 drivers/staging/media/imx/imx7-media-csi.c #define BIT_REDGE BIT(1) BIT 69 drivers/staging/media/imx/imx7-media-csi.c #define BIT_PIXEL_BIT BIT(0) BIT 75 drivers/staging/media/imx/imx7-media-csi.c #define BIT_FRMCNT_RST BIT(15) BIT 76 drivers/staging/media/imx/imx7-media-csi.c #define BIT_DMA_REFLASH_RFF BIT(14) BIT 77 drivers/staging/media/imx/imx7-media-csi.c #define BIT_DMA_REFLASH_SFF BIT(13) BIT 78 drivers/staging/media/imx/imx7-media-csi.c #define BIT_DMA_REQ_EN_RFF BIT(12) BIT 79 drivers/staging/media/imx/imx7-media-csi.c #define BIT_DMA_REQ_EN_SFF BIT(11) BIT 81 drivers/staging/media/imx/imx7-media-csi.c #define BIT_HRESP_ERR_EN BIT(7) BIT 83 drivers/staging/media/imx/imx7-media-csi.c #define BIT_TWO_8BIT_SENSOR BIT(3) BIT 84 drivers/staging/media/imx/imx7-media-csi.c #define BIT_ZERO_PACK_EN BIT(2) BIT 85 drivers/staging/media/imx/imx7-media-csi.c #define BIT_ECC_INT_EN BIT(1) BIT 86 drivers/staging/media/imx/imx7-media-csi.c #define BIT_ECC_AUTO_EN BIT(0) BIT 92 drivers/staging/media/imx/imx7-media-csi.c #define BIT_ADDR_CH_ERR_INT BIT(28) BIT 93 drivers/staging/media/imx/imx7-media-csi.c #define BIT_FIELD0_INT BIT(27) BIT 94 drivers/staging/media/imx/imx7-media-csi.c #define BIT_FIELD1_INT BIT(26) BIT 95 drivers/staging/media/imx/imx7-media-csi.c #define BIT_SFF_OR_INT BIT(25) BIT 96 drivers/staging/media/imx/imx7-media-csi.c #define BIT_RFF_OR_INT BIT(24) BIT 97 drivers/staging/media/imx/imx7-media-csi.c #define BIT_DMA_TSF_DONE_SFF BIT(22) BIT 98 drivers/staging/media/imx/imx7-media-csi.c #define BIT_STATFF_INT BIT(21) BIT 99 drivers/staging/media/imx/imx7-media-csi.c #define BIT_DMA_TSF_DONE_FB2 BIT(20) BIT 100 drivers/staging/media/imx/imx7-media-csi.c #define BIT_DMA_TSF_DONE_FB1 BIT(19) BIT 101 drivers/staging/media/imx/imx7-media-csi.c #define BIT_RXFF_INT BIT(18) BIT 102 drivers/staging/media/imx/imx7-media-csi.c #define BIT_EOF_INT BIT(17) BIT 103 drivers/staging/media/imx/imx7-media-csi.c #define BIT_SOF_INT BIT(16) BIT 104 drivers/staging/media/imx/imx7-media-csi.c #define BIT_F2_INT BIT(15) BIT 105 drivers/staging/media/imx/imx7-media-csi.c #define BIT_F1_INT BIT(14) BIT 106 drivers/staging/media/imx/imx7-media-csi.c #define BIT_COF_INT BIT(13) BIT 107 drivers/staging/media/imx/imx7-media-csi.c #define BIT_HRESP_ERR_INT BIT(7) BIT 108 drivers/staging/media/imx/imx7-media-csi.c #define BIT_ECC_INT BIT(1) BIT 109 drivers/staging/media/imx/imx7-media-csi.c #define BIT_DRDY BIT(0) BIT 112 drivers/staging/media/imx/imx7-media-csi.c #define BIT_CSI_HW_ENABLE BIT(31) BIT 120 drivers/staging/media/imx/imx7-media-csi.c #define BIT_DATA_FROM_MIPI BIT(22) BIT 121 drivers/staging/media/imx/imx7-media-csi.c #define BIT_MIPI_YU_SWAP BIT(21) BIT 122 drivers/staging/media/imx/imx7-media-csi.c #define BIT_MIPI_DOUBLE_CMPNT BIT(20) BIT 123 drivers/staging/media/imx/imx7-media-csi.c #define BIT_BASEADDR_CHG_ERR_EN BIT(9) BIT 124 drivers/staging/media/imx/imx7-media-csi.c #define BIT_BASEADDR_SWITCH_SEL BIT(5) BIT 125 drivers/staging/media/imx/imx7-media-csi.c #define BIT_BASEADDR_SWITCH_EN BIT(4) BIT 126 drivers/staging/media/imx/imx7-media-csi.c #define BIT_PARALLEL24_EN BIT(3) BIT 127 drivers/staging/media/imx/imx7-media-csi.c #define BIT_DEINTERLACE_EN BIT(2) BIT 128 drivers/staging/media/imx/imx7-media-csi.c #define BIT_TVDECODER_IN_EN BIT(1) BIT 129 drivers/staging/media/imx/imx7-media-csi.c #define BIT_NTSC_EN BIT(0) BIT 48 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16) BIT 49 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10) BIT 50 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) BIT 51 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_CMN_CTRL_RESET BIT(1) BIT 52 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0) BIT 64 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) BIT 68 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_EVEN_BEFORE BIT(31) BIT 69 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_EVEN_AFTER BIT(30) BIT 70 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_ODD_BEFORE BIT(29) BIT 71 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_ODD_AFTER BIT(28) BIT 72 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_FRAME_START BIT(24) BIT 73 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_FRAME_END BIT(20) BIT 74 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_ERR_SOT_HS BIT(16) BIT 75 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_ERR_LOST_FS BIT(12) BIT 76 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_ERR_LOST_FE BIT(8) BIT 77 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_ERR_OVER BIT(4) BIT 78 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_ERR_WRONG_CFG BIT(3) BIT 79 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_ERR_ECC BIT(2) BIT 80 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_ERR_CRC BIT(1) BIT 81 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTMSK_ERR_UNKNOWN BIT(0) BIT 85 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_EVEN_BEFORE BIT(31) BIT 86 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_EVEN_AFTER BIT(30) BIT 87 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_EVEN BIT(30) BIT 88 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_ODD_BEFORE BIT(29) BIT 89 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_ODD_AFTER BIT(28) BIT 92 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_FRAME_START BIT(24) BIT 93 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_FRAME_END BIT(20) BIT 94 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_ERR_SOT_HS BIT(16) BIT 95 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_ERR_LOST_FS BIT(12) BIT 96 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_ERR_LOST_FE BIT(8) BIT 97 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_ERR_OVER BIT(4) BIT 98 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_ERR_WRONG_CFG BIT(3) BIT 99 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_ERR_ECC BIT(2) BIT 100 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_ERR_CRC BIT(1) BIT 101 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_INTSRC_ERR_UNKNOWN BIT(0) BIT 106 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_DPHYSTATUS_ULPS_DAT BIT(8) BIT 107 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT BIT(4) BIT 108 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_DPHYSTATUS_ULPS_CLK BIT(1) BIT 109 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK BIT(0) BIT 117 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK BIT(6) BIT 118 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT BIT(5) BIT 119 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_DPHYCTRL_ENABLE_DAT BIT(1) BIT 120 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_DPHYCTRL_ENABLE_CLK BIT(0) BIT 140 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT BIT(12) BIT 141 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11) BIT 46 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_PM_CTRL_START BIT(0) BIT 47 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_PM_CTRL_CFG_DONE BIT(1) BIT 48 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_PM_CTRL_RACE_TO_HALT BIT(2) BIT 49 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_PM_CTRL_NACK_ALL BIT(3) BIT 50 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_PM_CTRL_CSS_PWRDN BIT(4) BIT 51 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_PM_CTRL_RST_AT_EOF BIT(5) BIT 52 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_PM_CTRL_FORCE_HALT BIT(6) BIT 53 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_PM_CTRL_FORCE_UNHALT BIT(7) BIT 54 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_PM_CTRL_FORCE_PWRDN BIT(8) BIT 55 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_PM_CTRL_FORCE_RESET BIT(9) BIT 63 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_INT_CSS_IRQ BIT(31) BIT 66 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_STATE_HALT_STS BIT(0) BIT 67 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_STATE_IDLE_STS BIT(1) BIT 68 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_STATE_POWER_UP BIT(2) BIT 69 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_STATE_POWER_DOWN BIT(3) BIT 79 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_RST BIT(0) BIT 80 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_START BIT(1) BIT 81 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_BREAK BIT(2) BIT 82 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_RUN BIT(3) BIT 83 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_BROKEN BIT(4) BIT 84 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_IDLE BIT(5) BIT 85 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_SLEEPING BIT(6) BIT 86 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_STALLING BIT(7) BIT 87 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_IRQ_CLEAR BIT(8) BIT 88 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_IRQ_READY BIT(10) BIT 89 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_IRQ_SLEEPING BIT(11) BIT 90 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_ICACHE_INV BIT(12) BIT 91 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_CTRL_IPREFETCH_EN BIT(13) BIT 122 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_SP1_PORT_SP12DMA BIT(0) BIT 123 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_SP1_PORT_DMA2SP1 BIT(2) BIT 124 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_SP1_PORT_SP12SP2 BIT(4) BIT 125 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_SP1_PORT_SP22SP1 BIT(6) BIT 126 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_SP1_PORT_SP12ISP BIT(8) BIT 127 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_SP1_PORT_ISP2SP1 BIT(10) BIT 129 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_SP2_PORT_SP22DMA BIT(0) BIT 130 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_SP2_PORT_DMA2SP2 BIT(2) BIT 131 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_SP2_PORT_SP22SP1 BIT(4) BIT 132 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_SP2_PORT_SP12SP2 BIT(6) BIT 134 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_ISP_PORT_ISP2DMA BIT(0) BIT 135 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_ISP_PORT_DMA2ISP BIT(2) BIT 136 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_ISP_PORT_ISP2SP1 BIT(4) BIT 137 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_ISP_PORT_SP12ISP BIT(6) BIT 140 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_MOD_PORT_SP12DMA BIT(0) BIT 141 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_MOD_PORT_DMA2SP1 BIT(2) BIT 142 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_MOD_PORT_SP22DMA BIT(4) BIT 143 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_MOD_PORT_DMA2SP2 BIT(6) BIT 144 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_MOD_PORT_ISP2DMA BIT(8) BIT 145 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_MOD_PORT_DMA2ISP BIT(10) BIT 146 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_MOD_PORT_CELLS2GDC BIT(12) BIT 147 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_MOD_PORT_GDC2CELLS BIT(14) BIT 148 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_MOD_PORT_CELLS2DECOMP BIT(16) BIT 149 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_GP_STRMON_STAT_MOD_PORT_DECOMP2CELLS BIT(18) BIT 170 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SP1 BIT(0) BIT 171 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SP2 BIT(1) BIT 172 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ISP BIT(2) BIT 173 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SP1_STREAM_MON BIT(3) BIT 174 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SP2_STREAM_MON BIT(4) BIT 175 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ISP_STREAM_MON BIT(5) BIT 176 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_MOD_STREAM_MON BIT(6) BIT 177 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_MOD_ISP_STREAM_MON BIT(7) BIT 178 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ACCS_STREAM_MON BIT(8) BIT 179 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ACCS_SP1_STREAM_MON BIT(9) BIT 180 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ACCS_SP2_STREAM_MON BIT(10) BIT 181 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ISP_PMEM_ERROR BIT(11) BIT 182 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ISP_BAMEM_ERROR BIT(12) BIT 183 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ISP_VMEM_ERROR BIT(13) BIT 184 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ISP_DMEM_ERROR BIT(14) BIT 185 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SP1_ICACHE_MEM_ERROR BIT(15) BIT 186 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SP1_DMEM_ERROR BIT(16) BIT 187 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SP2_ICACHE_MEM_ERROR BIT(17) BIT 188 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SP2_DMEM_ERROR BIT(18) BIT 189 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ACCS_SCRATCH_MEM_ERROR BIT(19) BIT 190 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_GP_TIMER(n) BIT(20 + (n)) /* n=0..1 */ BIT 191 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_DMA BIT(22) BIT 192 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SW_PIN(n) BIT(23 + (n)) /* n=0..4 */ BIT 193 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_ACC_SYS BIT(28) BIT 194 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_OUT_FORM_IRQ_CTRL BIT(29) BIT 195 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SP1_IRQ_CTRL BIT(30) BIT 196 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_IRQCTRL_IRQ_SP2_IRQ_CTRL BIT(31) BIT 269 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_ABI_PIPE_CONFIG_ACQUIRE_ISP BIT(31) BIT 270 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_ABI_PORT_CONFIG_TYPE_INPUT_HOST BIT(0) BIT 271 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_ABI_PORT_CONFIG_TYPE_OUTPUT_HOST BIT(4) BIT 17 drivers/staging/media/ipu3/ipu3-tables.h #define IMGU_SCALER_FP BIT(31) /* 1.0 in fixed point */ BIT 88 drivers/staging/media/meson/vdec/codec_mpeg12.c amvdec_write_dos(core, POWER_CTL_VLD, BIT(4)); BIT 77 drivers/staging/media/meson/vdec/dos_regs.h #define MEM_FILL_ON_LEVEL BIT(10) BIT 78 drivers/staging/media/meson/vdec/dos_regs.h #define MEM_CTRL_EMPTY_EN BIT(2) BIT 79 drivers/staging/media/meson/vdec/dos_regs.h #define MEM_CTRL_FILL_EN BIT(1) BIT 84 drivers/staging/media/meson/vdec/dos_regs.h #define MEM_BUFCTRL_MANUAL BIT(1) BIT 27 drivers/staging/media/meson/vdec/esparser.c #define ES_WRITE BIT(5) BIT 28 drivers/staging/media/meson/vdec/esparser.c #define ES_SEARCH BIT(1) BIT 29 drivers/staging/media/meson/vdec/esparser.c #define ES_PARSER_START BIT(0) BIT 292 drivers/staging/media/meson/vdec/esparser.c BIT(PARSER_INT_HOST_EN_BIT)); BIT 20 drivers/staging/media/meson/vdec/vdec_1.c #define GEN_PWR_VDEC_1 (BIT(3) | BIT(2)) BIT 59 drivers/staging/media/meson/vdec/vdec_1.c amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(31)); BIT 91 drivers/staging/media/meson/vdec/vdec_1.c amvdec_write_dos(core, POWER_CTL_VLD, BIT(4)); BIT 140 drivers/staging/media/meson/vdec/vdec_1.c amvdec_write_dos(core, DOS_SW_RESET0, BIT(12) | BIT(11)); BIT 191 drivers/staging/media/meson/vdec/vdec_1.c amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(31)); BIT 209 drivers/staging/media/meson/vdec/vdec_1.c amvdec_write_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(17)); BIT 211 drivers/staging/media/meson/vdec/vdec_1.c amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(17)); BIT 1267 drivers/staging/media/omap4iss/iss_csi2.c sd->grp_id = BIT(16); /* group ID for iss subdevs */ BIT 115 drivers/staging/media/omap4iss/iss_csi2.h #define CSI2_OUTPUT_IPIPEIF BIT(0) BIT 116 drivers/staging/media/omap4iss/iss_csi2.h #define CSI2_OUTPUT_MEMORY BIT(1) BIT 507 drivers/staging/media/omap4iss/iss_ipipe.c sd->grp_id = BIT(16); /* group ID for iss subdevs */ BIT 20 drivers/staging/media/omap4iss/iss_ipipe.h #define IPIPE_OUTPUT_VP BIT(0) BIT 738 drivers/staging/media/omap4iss/iss_ipipeif.c sd->grp_id = BIT(16); /* group ID for iss subdevs */ BIT 21 drivers/staging/media/omap4iss/iss_ipipeif.h #define IPIPEIF_OUTPUT_MEMORY BIT(0) BIT 22 drivers/staging/media/omap4iss/iss_ipipeif.h #define IPIPEIF_OUTPUT_VP BIT(1) BIT 21 drivers/staging/media/omap4iss/iss_regs.h #define ISS_HL_SYSCONFIG_SOFTRESET BIT(0) BIT 28 drivers/staging/media/omap4iss/iss_regs.h #define ISS_HL_IRQ_HS_VS BIT(17) BIT 29 drivers/staging/media/omap4iss/iss_regs.h #define ISS_HL_IRQ_SIMCOP(i) BIT(12 + (i)) BIT 30 drivers/staging/media/omap4iss/iss_regs.h #define ISS_HL_IRQ_BTE BIT(11) BIT 31 drivers/staging/media/omap4iss/iss_regs.h #define ISS_HL_IRQ_CBUFF BIT(10) BIT 32 drivers/staging/media/omap4iss/iss_regs.h #define ISS_HL_IRQ_CCP2(i) BIT((i) > 3 ? 16 : 14 + (i)) BIT 33 drivers/staging/media/omap4iss/iss_regs.h #define ISS_HL_IRQ_CSIB BIT(5) BIT 34 drivers/staging/media/omap4iss/iss_regs.h #define ISS_HL_IRQ_CSIA BIT(4) BIT 35 drivers/staging/media/omap4iss/iss_regs.h #define ISS_HL_IRQ_ISP(i) BIT(i) BIT 45 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKCTRL_VPORT2_CLK BIT(30) BIT 46 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKCTRL_VPORT1_CLK BIT(29) BIT 47 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKCTRL_VPORT0_CLK BIT(28) BIT 48 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKCTRL_CCP2 BIT(4) BIT 49 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKCTRL_CSI2_B BIT(3) BIT 50 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKCTRL_CSI2_A BIT(2) BIT 51 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKCTRL_ISP BIT(1) BIT 52 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKCTRL_SIMCOP BIT(0) BIT 55 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKSTAT_VPORT2_CLK BIT(30) BIT 56 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKSTAT_VPORT1_CLK BIT(29) BIT 57 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKSTAT_VPORT0_CLK BIT(28) BIT 58 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKSTAT_CCP2 BIT(4) BIT 59 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKSTAT_CSI2_B BIT(3) BIT 60 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKSTAT_CSI2_A BIT(2) BIT 61 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKSTAT_ISP BIT(1) BIT 62 drivers/staging/media/omap4iss/iss_regs.h #define ISS_CLKSTAT_SIMCOP BIT(0) BIT 74 drivers/staging/media/omap4iss/iss_regs.h #define REGISTER0_HSCLOCKCONFIG BIT(24) BIT 81 drivers/staging/media/omap4iss/iss_regs.h #define REGISTER1_RESET_DONE_CTRLCLK BIT(29) BIT 82 drivers/staging/media/omap4iss/iss_regs.h #define REGISTER1_CLOCK_MISS_DETECTOR_STATUS BIT(25) BIT 102 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_SYSSTATUS_RESET_DONE BIT(0) BIT 109 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_IRQ_OCP_ERR BIT(14) BIT 110 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_IRQ_SHORT_PACKET BIT(13) BIT 111 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_IRQ_ECC_CORRECTION BIT(12) BIT 112 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_IRQ_ECC_NO_CORRECTION BIT(11) BIT 113 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_IRQ_COMPLEXIO_ERR BIT(9) BIT 114 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_IRQ_FIFO_OVF BIT(8) BIT 115 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_IRQ_CONTEXT0 BIT(0) BIT 163 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT BIT(26) BIT 164 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER BIT(25) BIT 165 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_STATEULPM5 BIT(24) BIT 166 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_STATEULPM4 BIT(23) BIT 167 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_STATEULPM3 BIT(22) BIT 168 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_STATEULPM2 BIT(21) BIT 169 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_STATEULPM1 BIT(20) BIT 170 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRCONTROL5 BIT(19) BIT 171 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRCONTROL4 BIT(18) BIT 172 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRCONTROL3 BIT(17) BIT 173 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRCONTROL2 BIT(16) BIT 174 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRCONTROL1 BIT(15) BIT 175 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRESC5 BIT(14) BIT 176 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRESC4 BIT(13) BIT 177 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRESC3 BIT(12) BIT 178 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRESC2 BIT(11) BIT 179 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRESC1 BIT(10) BIT 180 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5 BIT(9) BIT 181 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4 BIT(8) BIT 182 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3 BIT(7) BIT 183 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2 BIT(6) BIT 184 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1 BIT(5) BIT 185 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRSOTHS5 BIT(4) BIT 186 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRSOTHS4 BIT(3) BIT 187 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRSOTHS3 BIT(2) BIT 188 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRSOTHS2 BIT(1) BIT 189 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_COMPLEXIO_IRQ_ERRSOTHS1 BIT(0) BIT 194 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_TIMING_FORCE_RX_MODE_IO1 BIT(15) BIT 195 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_TIMING_STOP_STATE_X16_IO1 BIT(14) BIT 196 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_TIMING_STOP_STATE_X4_IO1 BIT(13) BIT 201 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_CTRL1_GENERIC BIT(30) BIT 206 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_CTRL1_EOF_EN BIT(7) BIT 207 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_CTRL1_EOL_EN BIT(6) BIT 208 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_CTRL1_CS_EN BIT(5) BIT 209 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_CTRL1_COUNT_UNLOCK BIT(4) BIT 210 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_CTRL1_PING_PONG BIT(3) BIT 211 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_CTRL1_CTX_EN BIT(0) BIT 243 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_IRQ_ECC_CORRECTION BIT(8) BIT 244 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_IRQ_LINE_NUMBER BIT(7) BIT 245 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_IRQ_FRAME_NUMBER BIT(6) BIT 246 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_IRQ_CS BIT(5) BIT 247 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_IRQ_LE BIT(3) BIT 248 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_IRQ_LS BIT(2) BIT 249 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_IRQ_FE BIT(1) BIT 250 drivers/staging/media/omap4iss/iss_regs.h #define CSI2_CTX_IRQ_FS BIT(0) BIT 271 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_OCP_ERR BIT(31) BIT 272 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_IPIPE_INT_DPC_RNEW1 BIT(29) BIT 273 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_IPIPE_INT_DPC_RNEW0 BIT(28) BIT 274 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_IPIPE_INT_DPC_INIT BIT(27) BIT 275 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_IPIPE_INT_EOF BIT(25) BIT 276 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_H3A_INT_EOF BIT(24) BIT 277 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_RSZ_INT_EOF1 BIT(23) BIT 278 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_RSZ_INT_EOF0 BIT(22) BIT 279 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR BIT(19) BIT 280 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_RSZ_FIFO_OVF BIT(18) BIT 281 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_RSZ_INT_CYC_RSZB BIT(17) BIT 282 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_RSZ_INT_CYC_RSZA BIT(16) BIT 283 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_RSZ_INT_DMA BIT(15) BIT 284 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_RSZ_INT_LAST_PIX BIT(14) BIT 285 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_RSZ_INT_REG BIT(13) BIT 286 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_H3A_INT BIT(12) BIT 287 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_AF_INT BIT(11) BIT 288 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_AEW_INT BIT(10) BIT 289 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_IPIPEIF_IRQ BIT(9) BIT 290 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_IPIPE_INT_HST BIT(8) BIT 291 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_IPIPE_INT_BSC BIT(7) BIT 292 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_IPIPE_INT_DMA BIT(6) BIT 293 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_IPIPE_INT_LAST_PIX BIT(5) BIT 294 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_IPIPE_INT_REG BIT(4) BIT 295 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_IRQ_ISIF_INT(i) BIT(i) BIT 298 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_MSTANDBY BIT(24) BIT 299 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_VD_PULSE_EXT BIT(23) BIT 300 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_MSTANDBY_WAIT BIT(20) BIT 301 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_BL_CLK_ENABLE BIT(15) BIT 302 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_ISIF_CLK_ENABLE BIT(14) BIT 303 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_H3A_CLK_ENABLE BIT(13) BIT 304 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_RSZ_CLK_ENABLE BIT(12) BIT 305 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_IPIPE_CLK_ENABLE BIT(11) BIT 306 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_IPIPEIF_CLK_ENABLE BIT(10) BIT 307 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_SYNC_ENABLE BIT(9) BIT 308 drivers/staging/media/omap4iss/iss_regs.h #define ISP5_CTRL_PSYNC_CLK_SEL BIT(8) BIT 312 drivers/staging/media/omap4iss/iss_regs.h #define ISIF_SYNCEN_DWEN BIT(1) BIT 313 drivers/staging/media/omap4iss/iss_regs.h #define ISIF_SYNCEN_SYEN BIT(0) BIT 337 drivers/staging/media/omap4iss/iss_regs.h #define ISIF_HSIZE_ADCR BIT(12) BIT 372 drivers/staging/media/omap4iss/iss_regs.h #define ISIF_CCDCFG_Y8POS BIT(11) BIT 390 drivers/staging/media/omap4iss/iss_regs.h #define IPIPEIF_CFG2_YUV8P BIT(7) BIT 391 drivers/staging/media/omap4iss/iss_regs.h #define IPIPEIF_CFG2_YUV8 BIT(6) BIT 392 drivers/staging/media/omap4iss/iss_regs.h #define IPIPEIF_CFG2_YUV16 BIT(3) BIT 393 drivers/staging/media/omap4iss/iss_regs.h #define IPIPEIF_CFG2_VDPOL BIT(2) BIT 394 drivers/staging/media/omap4iss/iss_regs.h #define IPIPEIF_CFG2_HDPOL BIT(1) BIT 395 drivers/staging/media/omap4iss/iss_regs.h #define IPIPEIF_CFG2_INTSW BIT(0) BIT 401 drivers/staging/media/omap4iss/iss_regs.h #define IPIPE_SRC_EN_EN BIT(0) BIT 404 drivers/staging/media/omap4iss/iss_regs.h #define IPIPE_SRC_MODE_WRT BIT(1) BIT 405 drivers/staging/media/omap4iss/iss_regs.h #define IPIPE_SRC_MODE_OST BIT(0) BIT 448 drivers/staging/media/omap4iss/iss_regs.h #define IPIPE_GCK_MMR_REG BIT(0) BIT 451 drivers/staging/media/omap4iss/iss_regs.h #define IPIPE_GCK_PIX_G3 BIT(3) BIT 452 drivers/staging/media/omap4iss/iss_regs.h #define IPIPE_GCK_PIX_G2 BIT(2) BIT 453 drivers/staging/media/omap4iss/iss_regs.h #define IPIPE_GCK_PIX_G1 BIT(1) BIT 454 drivers/staging/media/omap4iss/iss_regs.h #define IPIPE_GCK_PIX_G0 BIT(0) BIT 632 drivers/staging/media/omap4iss/iss_regs.h #define IPIPE_YUV_PHS_LPF BIT(1) BIT 633 drivers/staging/media/omap4iss/iss_regs.h #define IPIPE_YUV_PHS_POS BIT(0) BIT 738 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_SYSCONFIG_RSZB_CLK_EN BIT(9) BIT 739 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_SYSCONFIG_RSZA_CLK_EN BIT(8) BIT 751 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_SRC_EN_SRC_EN BIT(0) BIT 754 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_SRC_MODE_OST BIT(0) BIT 755 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_SRC_MODE_WRT BIT(1) BIT 758 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_SRC_FMT0_BYPASS BIT(1) BIT 759 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_SRC_FMT0_SEL BIT(0) BIT 762 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_SRC_FMT1_IN420 BIT(1) BIT 772 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_GCK_MMR_MMR BIT(0) BIT 775 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_GCK_SDR_CORE BIT(0) BIT 789 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_SEQ_HRVB BIT(2) BIT 790 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_SEQ_HRVA BIT(0) BIT 794 drivers/staging/media/omap4iss/iss_regs.h #define RZA_MODE_ONE_SHOT BIT(0) BIT 858 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_EN_EN BIT(0) BIT 860 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_420_CEN BIT(1) BIT 861 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_420_YEN BIT(0) BIT 877 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_V_TYP_C BIT(1) BIT 878 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_V_TYP_Y BIT(0) BIT 889 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_H_TYP_C BIT(1) BIT 890 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_H_TYP_Y BIT(0) BIT 897 drivers/staging/media/omap4iss/iss_regs.h #define RSZ_DWN_EN_DWN_EN BIT(0) BIT 781 drivers/staging/media/omap4iss/iss_resizer.c sd->grp_id = BIT(16); /* group ID for iss subdevs */ BIT 21 drivers/staging/media/omap4iss/iss_resizer.h #define RESIZER_OUTPUT_MEMORY BIT(0) BIT 29 drivers/staging/media/sunxi/cedrus/cedrus.h #define CEDRUS_CAPABILITY_UNTILED BIT(0) BIT 31 drivers/staging/media/sunxi/cedrus/cedrus.h #define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) BIT 125 drivers/staging/media/sunxi/cedrus/cedrus_h264.c used_dpbs |= BIT(position); BIT 206 drivers/staging/media/sunxi/cedrus/cedrus_h264.c sram_array[i] |= BIT(0); BIT 379 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= decode->nal_ref_idc ? BIT(12) : 0; BIT 85 drivers/staging/media/sunxi/cedrus/cedrus_regs.h ((v) ? BIT(7) : 0) BIT 87 drivers/staging/media/sunxi/cedrus/cedrus_regs.h ((v) ? BIT(6) : 0) BIT 89 drivers/staging/media/sunxi/cedrus/cedrus_regs.h ((v) ? BIT(5) : 0) BIT 91 drivers/staging/media/sunxi/cedrus/cedrus_regs.h ((v) ? BIT(4) : 0) BIT 93 drivers/staging/media/sunxi/cedrus/cedrus_regs.h ((v) ? BIT(3) : 0) BIT 95 drivers/staging/media/sunxi/cedrus/cedrus_regs.h ((v) ? BIT(2) : 0) BIT 97 drivers/staging/media/sunxi/cedrus/cedrus_regs.h ((v) ? BIT(1) : 0) BIT 99 drivers/staging/media/sunxi/cedrus/cedrus_regs.h ((v) ? BIT(0) : 0) BIT 120 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_CTRL_MC_CACHE_EN BIT(31) BIT 121 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_CTRL_SW_VLD BIT(27) BIT 122 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_CTRL_SW_IQ_IS BIT(17) BIT 123 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_CTRL_QP_AC_DC_OUT_EN BIT(14) BIT 124 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_CTRL_ROTATE_SCALE_OUT_EN BIT(8) BIT 125 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_CTRL_MC_NO_WRITEBACK BIT(7) BIT 126 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_CTRL_ROTATE_IRQ_EN BIT(6) BIT 127 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_CTRL_VLD_DATA_REQ_IRQ_EN BIT(5) BIT 128 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_CTRL_ERROR_IRQ_EN BIT(4) BIT 129 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_CTRL_FINISH_IRQ_EN BIT(3) BIT 136 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_TRIGGER_MB_BOUNDARY BIT(31) BIT 150 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_TRIGGER_VP62_AC_GET_BITS BIT(7) BIT 173 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_START_DETECT_BUSY BIT(27) BIT 174 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_VP6_BIT BIT(26) BIT 175 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_VP6_BIT_BUSY BIT(25) BIT 176 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_MAF_BUSY BIT(23) BIT 177 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_VP6_MVP_BUSY BIT(22) BIT 178 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_JPEG_BIT_END BIT(21) BIT 179 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_JPEG_RESTART_ERROR BIT(20) BIT 180 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_JPEG_MARKER BIT(19) BIT 181 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_ROTATE_BUSY BIT(18) BIT 182 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_DEBLOCKING_BUSY BIT(17) BIT 183 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_SCALE_DOWN_BUSY BIT(16) BIT 184 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_IQIS_BUF_EMPTY BIT(15) BIT 185 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_IDCT_BUF_EMPTY BIT(14) BIT 186 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_VE_BUSY BIT(13) BIT 187 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_MC_BUSY BIT(12) BIT 188 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_IDCT_BUSY BIT(11) BIT 189 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_IQIS_BUSY BIT(10) BIT 190 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_DCAC_BUSY BIT(9) BIT 191 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_VLD_BUSY BIT(8) BIT 192 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_ROTATE_SUCCESS BIT(3) BIT 193 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_VLD_DATA_REQ BIT(2) BIT 194 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_ERROR BIT(1) BIT 195 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_STATUS_SUCCESS BIT(0) BIT 204 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_VLD_ADDR_FIRST_PIC_DATA BIT(30) BIT 205 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_VLD_ADDR_LAST_PIC_DATA BIT(29) BIT 206 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_DEC_MPEG_VLD_ADDR_VALID_PIC_DATA BIT(28) BIT 239 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_SPS_MBS_ONLY BIT(18) BIT 240 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) BIT 241 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_SPS_DIRECT_8X8_INFERENCE BIT(16) BIT 244 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_PPS_ENTROPY_CODING_MODE BIT(15) BIT 245 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_PPS_WEIGHTED_PRED BIT(4) BIT 246 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_PPS_CONSTRAINED_INTRA_PRED BIT(1) BIT 247 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_PPS_TRANSFORM_8X8_MODE BIT(0) BIT 250 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_SHS_FIRST_SLICE_IN_PIC BIT(5) BIT 251 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_SHS_FIELD_PIC BIT(4) BIT 252 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_SHS_BOTTOM_FIELD BIT(3) BIT 253 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_SHS_DIRECT_SPATIAL_MV_PRED BIT(2) BIT 256 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD BIT(12) BIT 261 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT BIT(24) BIT 264 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_CTRL_VLD_DATA_REQ_INT BIT(2) BIT 265 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_CTRL_DECODE_ERR_INT BIT(1) BIT 266 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_CTRL_SLICE_DECODE_INT BIT(0) BIT 286 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_VLD_ADDR_FIRST BIT(30) BIT 287 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_VLD_ADDR_LAST BIT(29) BIT 288 drivers/staging/media/sunxi/cedrus/cedrus_regs.h #define VE_H264_VLD_ADDR_VALID BIT(28) BIT 27 drivers/staging/media/sunxi/cedrus/cedrus_video.c #define CEDRUS_DECODE_SRC BIT(0) BIT 28 drivers/staging/media/sunxi/cedrus/cedrus_video.c #define CEDRUS_DECODE_DST BIT(1) BIT 37 drivers/staging/media/tegra-vde/vde.c #define BSE_ICMDQUE_EMPTY BIT(3) BIT 38 drivers/staging/media/tegra-vde/vde.c #define BSE_DMA_BUSY BIT(23) BIT 148 drivers/staging/media/tegra-vde/vde.c !(value & BIT(2)), 1, 100); BIT 59 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_TX_2B_OFFSET BIT(31) BIT 60 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_CLK_GATE BIT(30) BIT 61 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_BYTE_SWAP BIT(29) BIT 62 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_MULTI_DMA BIT(10) BIT 63 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_TWO_BUF BIT(9) BIT 64 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_32B_DESC BIT(8) BIT 65 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_BIG_ENDIAN BIT(7) BIT 66 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_TX_DONE BIT(6) BIT 69 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_RX_BUSY BIT(3) BIT 70 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_RX_DMA BIT(2) BIT 71 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_TX_BUSY BIT(1) BIT 72 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_GLO_TX_DMA BIT(0) BIT 87 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_DELAY_INT_EN BIT(15) BIT 99 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_INT_DELAY_RX_COH BIT(31) BIT 100 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_INT_DELAY_RX_INT BIT(30) BIT 101 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_INT_DELAY_TX_COH BIT(29) BIT 102 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_INT_DELAY_TX_INT BIT(28) BIT 105 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_INT_RX_Q0 BIT(16) BIT 108 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_INT_TX_Q0 BIT(0) BIT 112 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_DESC_DONE BIT(31) BIT 113 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_DESC_LS0 BIT(30) BIT 115 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_DESC_TAG BIT(15) BIT 116 drivers/staging/mt7621-dma/mtk-hsdma.c #define HSDMA_DESC_LS1 BIT(14) BIT 20 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_PIPE_RST BIT(12) BIT 21 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_PIPE_CMD_FRC BIT(4) BIT 29 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_FRC_H_XTAL_TYPE BIT(8) BIT 34 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_FRC_PHY_EN BIT(4) BIT 35 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_PHY_EN BIT(5) BIT 66 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_LCDDS_CLK_PH_INV BIT(5) BIT 76 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_FRC_MSTCKDIV BIT(5) BIT 80 drivers/staging/mt7621-pci/pci-mt7621.c #define PCIE_REVISION_ID BIT(0) BIT 83 drivers/staging/mt7621-pci/pci-mt7621.c #define PCIE_BAR_ENABLE BIT(0) BIT 84 drivers/staging/mt7621-pci/pci-mt7621.c #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) BIT 85 drivers/staging/mt7621-pci/pci-mt7621.c #define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) BIT 86 drivers/staging/mt7621-pci/pci-mt7621.c #define PCIE_PORT_LINKUP BIT(0) BIT 88 drivers/staging/mt7621-pci/pci-mt7621.c #define PCIE_CLK_GEN_EN BIT(31) BIT 91 drivers/staging/mt7621-pci/pci-mt7621.c #define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25)) BIT 94 drivers/staging/mt7621-pci/pci-mt7621.c #define PERST_MODE_GPIO BIT(10) BIT 564 drivers/staging/mt7621-pci/pci-mt7621.c pcie_link_status |= BIT(slot); BIT 36 drivers/staging/nvec/nvec.c #define I2C_CNFG_PACKET_MODE_EN BIT(10) BIT 37 drivers/staging/nvec/nvec.c #define I2C_CNFG_NEW_MASTER_SFM BIT(11) BIT 41 drivers/staging/nvec/nvec.c #define I2C_SL_NEWSL BIT(2) BIT 42 drivers/staging/nvec/nvec.c #define I2C_SL_NACK BIT(1) BIT 43 drivers/staging/nvec/nvec.c #define I2C_SL_RESP BIT(0) BIT 44 drivers/staging/nvec/nvec.c #define I2C_SL_IRQ BIT(3) BIT 45 drivers/staging/nvec/nvec.c #define END_TRANS BIT(4) BIT 46 drivers/staging/nvec/nvec.c #define RCVD BIT(2) BIT 47 drivers/staging/nvec/nvec.c #define RNW BIT(1) BIT 73 drivers/staging/nvec/nvec.c #define LID_SWITCH BIT(1) BIT 74 drivers/staging/nvec/nvec.c #define PWR_BUTTON BIT(15) BIT 48 drivers/staging/nvec/nvec_kbd.c buf[2] = BIT(0) | BIT(1) | BIT(2); BIT 200 drivers/staging/octeon/ethernet-rx.c BIT(rx_group->group)); BIT 206 drivers/staging/octeon/ethernet-rx.c BIT(rx_group->group)); BIT 231 drivers/staging/octeon/ethernet-rx.c BIT(rx_group->group)); BIT 233 drivers/staging/octeon/ethernet-rx.c BIT(rx_group->group)); BIT 238 drivers/staging/octeon/ethernet-rx.c wq_int.s.iq_dis = BIT(rx_group->group); BIT 239 drivers/staging/octeon/ethernet-rx.c wq_int.s.wq_int = BIT(rx_group->group); BIT 439 drivers/staging/octeon/ethernet-rx.c if (!(pow_receive_groups & BIT(i))) BIT 465 drivers/staging/octeon/ethernet-rx.c if (!(pow_receive_groups & BIT(i))) BIT 524 drivers/staging/octeon/ethernet-rx.c if (!(pow_receive_groups & BIT(i))) BIT 709 drivers/staging/octeon/ethernet.c pow_receive_groups = BIT(pow_receive_group); BIT 13 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_PASSTHRU BIT(0) BIT 14 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_SLEEP BIT(1) BIT 15 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_SLEEP_AUTO BIT(2) BIT 16 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_BL_ENABLE BIT(3) BIT 17 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_BLANK BIT(4) BIT 18 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_CSWIZZLE BIT(5) BIT 19 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_COL_AA BIT(6) BIT 20 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_MONO_LUMA BIT(7) BIT 21 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_SCAN_INT BIT(8) BIT 22 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_CLOCKDIV BIT(9) BIT 23 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_DEBUG BIT(14) BIT 24 drivers/staging/olpc_dcon/olpc_dcon.h #define MODE_SELFTEST BIT(15) BIT 39 drivers/staging/olpc_dcon/olpc_dcon.h #define MEM_DLL_CLOCK_DELAY BIT(0) BIT 41 drivers/staging/olpc_dcon/olpc_dcon.h #define MEM_POWER_DOWN BIT(8) BIT 43 drivers/staging/olpc_dcon/olpc_dcon.h #define MEM_SOFT_RESET BIT(0) BIT 48 drivers/staging/pi433/pi433_if.c #define N_PI433_MINORS BIT(MINORBITS) /*32*/ /* ... up to 256 */ BIT 31 drivers/staging/ralink-gdma/ralink-gdma.c #define GDMA_REG_CTRL0_SRC_ADDR_FIXED BIT(7) BIT 32 drivers/staging/ralink-gdma/ralink-gdma.c #define GDMA_REG_CTRL0_DST_ADDR_FIXED BIT(6) BIT 35 drivers/staging/ralink-gdma/ralink-gdma.c #define GDMA_REG_CTRL0_DONE_INT BIT(2) BIT 36 drivers/staging/ralink-gdma/ralink-gdma.c #define GDMA_REG_CTRL0_ENABLE BIT(1) BIT 37 drivers/staging/ralink-gdma/ralink-gdma.c #define GDMA_REG_CTRL0_SW_MODE BIT(0) BIT 47 drivers/staging/ralink-gdma/ralink-gdma.c #define GDMA_REG_CTRL1_COHERENT BIT(2) BIT 48 drivers/staging/ralink-gdma/ralink-gdma.c #define GDMA_REG_CTRL1_FAIL BIT(1) BIT 49 drivers/staging/ralink-gdma/ralink-gdma.c #define GDMA_REG_CTRL1_MASK BIT(0) BIT 59 drivers/staging/ralink-gdma/ralink-gdma.c #define GDMA_REG_GCT_ARBIT_RR BIT(0) BIT 70 drivers/staging/ralink-gdma/ralink-gdma.c #define GDMA_RT305X_CTRL1_FAIL BIT(4) BIT 853 drivers/staging/ralink-gdma/ralink-gdma.c dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 854 drivers/staging/ralink-gdma/ralink-gdma.c dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 855 drivers/staging/ralink-gdma/ralink-gdma.c dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); BIT 124 drivers/staging/rtl8188eu/core/rtw_ap.c if (pstapriv->tim_bitmap & BIT(0))/* for bc/mc frames */ BIT 125 drivers/staging/rtl8188eu/core/rtw_ap.c *dst_ie++ = BIT(0);/* bitmap ctrl */ BIT 245 drivers/staging/rtl8188eu/core/rtw_ap.c pstapriv->tim_bitmap |= BIT(psta->aid); BIT 357 drivers/staging/rtl8188eu/core/rtw_ap.c if (psta_ht->ht_cap.mcs.rx_mask[0] & BIT(i)) BIT 358 drivers/staging/rtl8188eu/core/rtw_ap.c tx_ra_bitmap |= BIT(i + 12); BIT 381 drivers/staging/rtl8188eu/core/rtw_ap.c arg |= BIT(7);/* support entry 2~31 */ BIT 384 drivers/staging/rtl8188eu/core/rtw_ap.c arg |= BIT(5); BIT 398 drivers/staging/rtl8188eu/core/rtw_ap.c init_rate |= BIT(6); BIT 463 drivers/staging/rtl8188eu/core/rtw_ap.c arg |= BIT(7); BIT 675 drivers/staging/rtl8188eu/core/rtw_ap.c if ((pregpriv->cbw40_enable) && (pht_info->infos[0] & BIT(2))) { BIT 826 drivers/staging/rtl8188eu/core/rtw_ap.c if (cap & BIT(4)) BIT 844 drivers/staging/rtl8188eu/core/rtw_ap.c psecuritypriv->wpa_psk |= BIT(1); BIT 866 drivers/staging/rtl8188eu/core/rtw_ap.c psecuritypriv->wpa_psk |= BIT(0); BIT 888 drivers/staging/rtl8188eu/core/rtw_ap.c *(p + 8) |= BIT(7); BIT 893 drivers/staging/rtl8188eu/core/rtw_ap.c *(p + 10) &= ~BIT(4); /* BE */ BIT 894 drivers/staging/rtl8188eu/core/rtw_ap.c *(p + 14) &= ~BIT(4); /* BK */ BIT 895 drivers/staging/rtl8188eu/core/rtw_ap.c *(p + 18) &= ~BIT(4); /* VI */ BIT 896 drivers/staging/rtl8188eu/core/rtw_ap.c *(p + 22) &= ~BIT(4); /* VO */ BIT 1036 drivers/staging/rtl8188eu/core/rtw_cmd.c pstapriv->tim_bitmap &= ~BIT(0); BIT 1037 drivers/staging/rtl8188eu/core/rtw_cmd.c pstapriv->sta_dz_bitmap &= ~BIT(0); BIT 320 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(0))) { BIT 328 drivers/staging/rtl8188eu/core/rtw_efuse.c badworden &= (~BIT(0)); BIT 330 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(1))) { BIT 338 drivers/staging/rtl8188eu/core/rtw_efuse.c badworden &= (~BIT(1)); BIT 340 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(2))) { BIT 348 drivers/staging/rtl8188eu/core/rtw_efuse.c badworden &= (~BIT(2)); BIT 350 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(3))) { BIT 358 drivers/staging/rtl8188eu/core/rtw_efuse.c badworden &= (~BIT(3)); BIT 658 drivers/staging/rtl8188eu/core/rtw_efuse.c if (((pTargetPkt->word_en & BIT(0)) == 0) && BIT 659 drivers/staging/rtl8188eu/core/rtw_efuse.c ((pCurPkt->word_en & BIT(0)) == 0)) BIT 660 drivers/staging/rtl8188eu/core/rtw_efuse.c match_word_en &= ~BIT(0); /* enable word 0 */ BIT 661 drivers/staging/rtl8188eu/core/rtw_efuse.c if (((pTargetPkt->word_en & BIT(1)) == 0) && BIT 662 drivers/staging/rtl8188eu/core/rtw_efuse.c ((pCurPkt->word_en & BIT(1)) == 0)) BIT 663 drivers/staging/rtl8188eu/core/rtw_efuse.c match_word_en &= ~BIT(1); /* enable word 1 */ BIT 664 drivers/staging/rtl8188eu/core/rtw_efuse.c if (((pTargetPkt->word_en & BIT(2)) == 0) && BIT 665 drivers/staging/rtl8188eu/core/rtw_efuse.c ((pCurPkt->word_en & BIT(2)) == 0)) BIT 666 drivers/staging/rtl8188eu/core/rtw_efuse.c match_word_en &= ~BIT(2); /* enable word 2 */ BIT 667 drivers/staging/rtl8188eu/core/rtw_efuse.c if (((pTargetPkt->word_en & BIT(3)) == 0) && BIT 668 drivers/staging/rtl8188eu/core/rtw_efuse.c ((pCurPkt->word_en & BIT(3)) == 0)) BIT 669 drivers/staging/rtl8188eu/core/rtw_efuse.c match_word_en &= ~BIT(3); /* enable word 3 */ BIT 802 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(0))) BIT 804 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(1))) BIT 806 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(2))) BIT 808 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(3))) BIT 863 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(0))) { BIT 867 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(1))) { BIT 871 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(2))) { BIT 875 drivers/staging/rtl8188eu/core/rtw_efuse.c if (!(word_en & BIT(3))) { BIT 69 drivers/staging/rtl8188eu/core/rtw_ieee80211.c return BIT(i); BIT 1022 drivers/staging/rtl8188eu/core/rtw_ieee80211.c if (MCS_rate[0] & BIT(7)) BIT 1024 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(6)) BIT 1026 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(5)) BIT 1028 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(4)) BIT 1030 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(3)) BIT 1032 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(2)) BIT 1034 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(1)) BIT 1036 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(0)) BIT 1040 drivers/staging/rtl8188eu/core/rtw_ieee80211.c if (MCS_rate[1] & BIT(7)) BIT 1042 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(6)) BIT 1044 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(5)) BIT 1046 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(4)) BIT 1048 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(3)) BIT 1050 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(2)) BIT 1052 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(1)) BIT 1054 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(0)) BIT 1057 drivers/staging/rtl8188eu/core/rtw_ieee80211.c if (MCS_rate[0] & BIT(7)) BIT 1059 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(6)) BIT 1061 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(5)) BIT 1063 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(4)) BIT 1065 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(3)) BIT 1067 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(2)) BIT 1069 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(1)) BIT 1071 drivers/staging/rtl8188eu/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(0)) BIT 1582 drivers/staging/rtl8188eu/core/rtw_mlme.c pmlmepriv->key_mask |= BIT(psetkeyparm->keyid); BIT 1951 drivers/staging/rtl8188eu/core/rtw_mlme.c (le16_to_cpu(pmlmeinfo->HT_caps.cap_info) & BIT(1)) && BIT 1952 drivers/staging/rtl8188eu/core/rtw_mlme.c (pmlmeinfo->HT_info.infos[0] & BIT(2))) { BIT 2012 drivers/staging/rtl8188eu/core/rtw_mlme.c psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority); BIT 939 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c leval = cpu_to_le16(pstat->aid | BIT(14) | BIT(15)); BIT 1128 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pmlmeinfo->HT_caps.cap_info &= cpu_to_le16(~(BIT(6) | BIT(1))); BIT 1130 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pmlmeinfo->HT_caps.cap_info |= cpu_to_le16(BIT(1)); BIT 1659 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c BA_para_set = BA_para_set & ~BIT(0); BIT 1661 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c BA_para_set = BA_para_set | BIT(0); BIT 1756 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c iedata |= BIT(2);/* 20 MHz BSS Width Request */ BIT 1850 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if (psta->htpriv.agg_enable_bitmap & BIT(tid)) { BIT 1853 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c psta->htpriv.agg_enable_bitmap &= ~BIT(tid); BIT 1854 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); BIT 2142 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if (val16 & BIT(0)) { BIT 2150 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if (val16 & BIT(4)) BIT 2166 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if (le16_to_cpu(pHT_caps->cap_info) & BIT(14)) BIT 3028 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if ((psecuritypriv->wpa_psk & BIT(1)) && elems.rsn_ie) { BIT 3036 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pstat->wpa_psk |= BIT(1); BIT 3049 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c } else if ((psecuritypriv->wpa_psk & BIT(0)) && elems.wpa_ie) { BIT 3057 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pstat->wpa_psk |= BIT(0); BIT 3164 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if (pstat->qos_info & BIT(0)) BIT 3165 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pstat->uapsd_vo = BIT(0)|BIT(1); BIT 3169 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if (pstat->qos_info & BIT(1)) BIT 3170 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pstat->uapsd_vi = BIT(0)|BIT(1); BIT 3174 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if (pstat->qos_info & BIT(2)) BIT 3175 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pstat->uapsd_bk = BIT(0)|BIT(1); BIT 3179 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if (pstat->qos_info & BIT(3)) BIT 3180 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pstat->uapsd_be = BIT(0)|BIT(1); BIT 3365 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10)) ? 9 : 20; BIT 3633 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); BIT 3635 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c psta->htpriv.agg_enable_bitmap &= ~BIT(tid); BIT 3639 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if ((frame_body[3] & BIT(3)) == 0) { BIT 3643 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c } else if ((frame_body[3] & BIT(3)) == BIT(3)) { BIT 3957 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if ((0 == (padapter->registrypriv.cbw40_enable & BIT(1))) && BIT 4847 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pmlmeinfo->state &= ~(BIT(0)|BIT(1));/* clear state */ BIT 4993 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if ((pregpriv->cbw40_enable) && (pht_info->infos[0] & BIT(2))) { BIT 5217 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid; BIT 5262 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c ctrl = BIT(15) | ((pparm->algorithm) << 2); BIT 5291 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c ctrl = BIT(15) | ((pparm->algorithm) << 2); BIT 5313 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid); BIT 5410 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if ((pstapriv->tim_bitmap & BIT(0)) && (psta_bmc->sleepq_len > 0)) { BIT 180 drivers/staging/rtl8188eu/core/rtw_pwrctrl.c if (pmlmepriv->key_mask & BIT(keyid)) { BIT 573 drivers/staging/rtl8188eu/core/rtw_recv.c wmmps_ac = psta->uapsd_bk&BIT(1); BIT 577 drivers/staging/rtl8188eu/core/rtw_recv.c wmmps_ac = psta->uapsd_vi&BIT(1); BIT 581 drivers/staging/rtl8188eu/core/rtw_recv.c wmmps_ac = psta->uapsd_vo&BIT(1); BIT 586 drivers/staging/rtl8188eu/core/rtw_recv.c wmmps_ac = psta->uapsd_be&BIT(1); BIT 776 drivers/staging/rtl8188eu/core/rtw_recv.c if (GetFrameSubType(ptr) & BIT(6)) { BIT 838 drivers/staging/rtl8188eu/core/rtw_recv.c if (GetFrameSubType(ptr) & BIT(6)) { BIT 895 drivers/staging/rtl8188eu/core/rtw_recv.c wmmps_ac = psta->uapsd_bk&BIT(0); BIT 899 drivers/staging/rtl8188eu/core/rtw_recv.c wmmps_ac = psta->uapsd_vi&BIT(0); BIT 903 drivers/staging/rtl8188eu/core/rtw_recv.c wmmps_ac = psta->uapsd_vo&BIT(0); BIT 908 drivers/staging/rtl8188eu/core/rtw_recv.c wmmps_ac = psta->uapsd_be&BIT(0); BIT 921 drivers/staging/rtl8188eu/core/rtw_recv.c if ((psta->state&WIFI_SLEEP_STATE) && (pstapriv->sta_dz_bitmap&BIT(psta->aid))) { BIT 952 drivers/staging/rtl8188eu/core/rtw_recv.c pstapriv->tim_bitmap &= ~BIT(psta->aid); BIT 959 drivers/staging/rtl8188eu/core/rtw_recv.c if (pstapriv->tim_bitmap&BIT(psta->aid)) { BIT 970 drivers/staging/rtl8188eu/core/rtw_recv.c pstapriv->tim_bitmap &= ~BIT(psta->aid); BIT 1228 drivers/staging/rtl8188eu/core/rtw_recv.c pattrib->qos = (subtype & BIT(7)) ? 1 : 0; BIT 354 drivers/staging/rtl8188eu/core/rtw_sta_mgt.c pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); BIT 355 drivers/staging/rtl8188eu/core/rtw_sta_mgt.c pstapriv->tim_bitmap &= ~BIT(psta->aid); BIT 532 drivers/staging/rtl8188eu/core/rtw_wlan_util.c acm_mask |= (ACM ? BIT(1) : 0); BIT 541 drivers/staging/rtl8188eu/core/rtw_wlan_util.c acm_mask |= (ACM ? BIT(2) : 0); BIT 546 drivers/staging/rtl8188eu/core/rtw_wlan_util.c acm_mask |= (ACM ? BIT(3) : 0); BIT 613 drivers/staging/rtl8188eu/core/rtw_wlan_util.c if ((pHT_info->infos[0] & BIT(2)) && pregistrypriv->cbw40_enable) { BIT 794 drivers/staging/rtl8188eu/core/rtw_wlan_util.c if ((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1))) { BIT 939 drivers/staging/rtl8188eu/core/rtw_wlan_util.c if (val16 & BIT(4)) BIT 1164 drivers/staging/rtl8188eu/core/rtw_wlan_util.c if (mask & BIT(i)) { BIT 347 drivers/staging/rtl8188eu/core/rtw_xmit.c if (acm_mask & BIT(1)) BIT 355 drivers/staging/rtl8188eu/core/rtw_xmit.c if (acm_mask & BIT(2)) BIT 360 drivers/staging/rtl8188eu/core/rtw_xmit.c if (acm_mask & BIT(3)) BIT 825 drivers/staging/rtl8188eu/core/rtw_xmit.c if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) BIT 1106 drivers/staging/rtl8188eu/core/rtw_xmit.c protection = (*(perp + 2)) & BIT(1); BIT 1670 drivers/staging/rtl8188eu/core/rtw_xmit.c pstapriv->tim_bitmap |= BIT(0);/* */ BIT 1671 drivers/staging/rtl8188eu/core/rtw_xmit.c pstapriv->sta_dz_bitmap |= BIT(0); BIT 1688 drivers/staging/rtl8188eu/core/rtw_xmit.c if (pstapriv->sta_dz_bitmap & BIT(psta->aid)) { BIT 1698 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_bk & BIT(0); BIT 1702 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_vi & BIT(0); BIT 1706 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_vo & BIT(0); BIT 1711 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_be & BIT(0); BIT 1720 drivers/staging/rtl8188eu/core/rtw_xmit.c pstapriv->tim_bitmap |= BIT(psta->aid); BIT 1780 drivers/staging/rtl8188eu/core/rtw_xmit.c pstapriv->sta_dz_bitmap |= BIT(psta->aid); BIT 1830 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_bk & BIT(1); BIT 1834 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_vi & BIT(1); BIT 1838 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_vo & BIT(1); BIT 1843 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_be & BIT(1); BIT 1873 drivers/staging/rtl8188eu/core/rtw_xmit.c pstapriv->tim_bitmap &= ~BIT(psta->aid); BIT 1875 drivers/staging/rtl8188eu/core/rtw_xmit.c update_mask = BIT(0); BIT 1885 drivers/staging/rtl8188eu/core/rtw_xmit.c pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); BIT 1923 drivers/staging/rtl8188eu/core/rtw_xmit.c pstapriv->tim_bitmap &= ~BIT(0); BIT 1924 drivers/staging/rtl8188eu/core/rtw_xmit.c pstapriv->sta_dz_bitmap &= ~BIT(0); BIT 1926 drivers/staging/rtl8188eu/core/rtw_xmit.c update_mask |= BIT(1); BIT 1956 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_bk & BIT(1); BIT 1960 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_vi & BIT(1); BIT 1964 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_vo & BIT(1); BIT 1969 drivers/staging/rtl8188eu/core/rtw_xmit.c wmmps_ac = psta->uapsd_be & BIT(1); BIT 1995 drivers/staging/rtl8188eu/core/rtw_xmit.c pstapriv->tim_bitmap &= ~BIT(psta->aid); BIT 665 drivers/staging/rtl8188eu/hal/bb_cfg.c (u16)(regval | BIT(13) | BIT(0) | BIT(1))); BIT 102 drivers/staging/rtl8188eu/hal/fw.c usb_write8(adapt, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); BIT 103 drivers/staging/rtl8188eu/hal/fw.c usb_write8(adapt, REG_SYS_FUNC_EN + 1, (u1b_tmp | BIT(2))); BIT 136 drivers/staging/rtl8188eu/hal/hal8188e_rate_adaptive.c if (pRaInfo->RAUseRate & BIT(i)) { BIT 204 drivers/staging/rtl8188eu/hal/hal8188e_rate_adaptive.c if (pRaInfo->RAUseRate & BIT(i)) { BIT 388 drivers/staging/rtl8188eu/hal/hal8188e_rate_adaptive.c if (pRaInfo->RAUseRate & BIT(i)) { BIT 399 drivers/staging/rtl8188eu/hal/hal8188e_rate_adaptive.c if ((pRaInfo->RAUseRate) & BIT(i)) { BIT 220 drivers/staging/rtl8188eu/hal/odm.c pDM_Odm->bCckHighPower = (bool)phy_query_bb_reg(adapter, 0x824, BIT(9)); BIT 517 drivers/staging/rtl8188eu/hal/odm.c phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */ BIT 518 drivers/staging/rtl8188eu/hal/odm.c phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */ BIT 541 drivers/staging/rtl8188eu/hal/odm.c phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1); BIT 542 drivers/staging/rtl8188eu/hal/odm.c phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1); BIT 634 drivers/staging/rtl8188eu/hal/odm.c pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord) & BIT(3))>>3; BIT 663 drivers/staging/rtl8188eu/hal/odm.c phy_set_bb_reg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */ BIT 667 drivers/staging/rtl8188eu/hal/odm.c phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */ BIT 668 drivers/staging/rtl8188eu/hal/odm.c phy_set_bb_reg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */ BIT 671 drivers/staging/rtl8188eu/hal/odm.c phy_set_bb_reg(adapter, 0xc70, BIT(3), pDM_PSTable->RegC70); BIT 674 drivers/staging/rtl8188eu/hal/odm.c phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0); BIT 966 drivers/staging/rtl8188eu/hal/odm.c phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03); BIT 178 drivers/staging/rtl8188eu/hal/odm_hwconfig.c if (dm_odm->RFPathRxEnable & BIT(i)) BIT 341 drivers/staging/rtl8188eu/hal/odm_hwconfig.c pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT(0); BIT 370 drivers/staging/rtl8188eu/hal/odm_hwconfig.c OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i) & BIT(0); BIT 18 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); BIT 19 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); BIT 26 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c value32 | (BIT(23) | BIT(25))); BIT 28 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); BIT 29 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); BIT 30 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); BIT 31 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); BIT 36 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); BIT 37 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); BIT 49 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); BIT 51 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(5) | BIT(4) | BIT(3), 0); BIT 58 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c value32 | (BIT(23) | BIT(25))); BIT 60 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); BIT 61 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); BIT 62 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); BIT 63 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); BIT 68 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); BIT 69 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); BIT 71 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); BIT 77 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(10) | BIT(9) | BIT(8), 1); BIT 79 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(13) | BIT(12) | BIT(11), 2); BIT 107 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c value32 | (BIT(23) | BIT(25))); BIT 110 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c value32 | (BIT(16) | BIT(17))); BIT 116 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0x870, BIT(9) | BIT(8), 0); BIT 117 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0x864, BIT(10), 0); BIT 118 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0xb2c, BIT(22), 0); BIT 119 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0xb2c, BIT(31), 1); BIT 124 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1); BIT 125 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2); BIT 132 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0x80c, BIT(21), 1); BIT 133 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0); BIT 134 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1); BIT 137 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), 1); BIT 138 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, 0xc50, BIT(7), 1); BIT 172 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(5) | BIT(4) | BIT(3), default_ant); BIT 174 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(8) | BIT(7) | BIT(6), optional_ant); BIT 176 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(14) | BIT(13) | BIT(12), default_ant); BIT 178 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(6) | BIT(7), default_ant); BIT 181 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(5) | BIT(4) | BIT(3), default_ant); BIT 183 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(8) | BIT(7) | BIT(6), optional_ant); BIT 198 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c dm_fat_tbl->antsel_a[mac_id] = target_ant & BIT(0); BIT 199 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c dm_fat_tbl->antsel_b[mac_id] = (target_ant & BIT(1)) >> 1; BIT 200 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c dm_fat_tbl->antsel_c[mac_id] = (target_ant & BIT(2)) >> 2; BIT 312 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); BIT 314 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(15), 0); BIT 317 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(21), 0); BIT 325 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1); BIT 327 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(15), 1); BIT 330 drivers/staging/rtl8188eu/hal/odm_rtl8188e.c BIT(21), 1); BIT 84 drivers/staging/rtl8188eu/hal/phy.c rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT(8)); BIT 86 drivers/staging/rtl8188eu/hal/phy.c rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, BIT(8)); BIT 242 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, 0x818, (BIT(26) | BIT(27)), BIT 550 drivers/staging/rtl8188eu/hal/phy.c if (!(reg_eac & BIT(28)) && BIT 602 drivers/staging/rtl8188eu/hal/phy.c if (!(reg_eac & BIT(28)) && BIT 650 drivers/staging/rtl8188eu/hal/phy.c if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */ BIT 679 drivers/staging/rtl8188eu/hal/phy.c if (!(regeac & BIT(31)) && BIT 686 drivers/staging/rtl8188eu/hal/phy.c if (!(regeac & BIT(30)) && BIT 713 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(31), BIT 725 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(29), BIT 759 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(27), BIT 772 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(25), BIT 854 drivers/staging/rtl8188eu/hal/phy.c usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT(3)))); BIT 856 drivers/staging/rtl8188eu/hal/phy.c usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT(5)))); BIT 996 drivers/staging/rtl8188eu/hal/phy.c BIT(8)); BIT 1004 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT(24), 0x00); BIT 1009 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01); BIT 1010 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01); BIT 1011 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00); BIT 1012 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00); BIT 22 drivers/staging/rtl8188eu/hal/rf.c 0xfffff3ff) | BIT(10) | BIT(11)); BIT 28 drivers/staging/rtl8188eu/hal/rf.c 0xfffff3ff) | BIT(10)); BIT 30 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c valid = usb_read8(adapt, REG_HMETFR) & BIT(msgbox_num); BIT 135 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c shortGIrate = (arg & BIT(5)) ? true : false; BIT 138 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c init_rate |= BIT(6); BIT 560 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c haldata->RegCR_1 |= BIT(0); BIT 566 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL)&(~BIT(3))); BIT 567 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL) | BIT(4)); BIT 569 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c if (haldata->RegFwHwTxQCtrl & BIT(6)) { BIT 575 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl&(~BIT(6)))); BIT 576 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c haldata->RegFwHwTxQCtrl &= (~BIT(6)); BIT 609 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL) | BIT(3)); BIT 610 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL)&(~BIT(4))); BIT 618 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl | BIT(6))); BIT 619 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c haldata->RegFwHwTxQCtrl |= BIT(6); BIT 630 drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c haldata->RegCR_1 &= (~BIT(0)); BIT 96 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT(2))); BIT 97 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT(2))); BIT 166 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) | BIT(1)); BIT 169 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) & ~BIT(1)); BIT 323 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ BIT 331 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ BIT 341 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ BIT 349 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ BIT 358 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ BIT 366 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ BIT 400 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT(4)); BIT 406 drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT(1)) ? true : false; BIT 88 drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c pattrib->bdecrypted = (le32_to_cpu(report.rxdw0) & BIT(27)) ? 0 : 1;/* u8)(prxreport->swdec ? 0 : 1); */ BIT 20 drivers/staging/rtl8188eu/hal/rtl8188eu_led.c usb_write8(padapter, REG_LEDCFG2, (led_cfg & 0xf0) | BIT(5) | BIT(6)); BIT 35 drivers/staging/rtl8188eu/hal/rtl8188eu_led.c usb_write8(padapter, REG_LEDCFG2, (led_cfg | BIT(3))); BIT 73 drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */ BIT 78 drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */ BIT 81 drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */ BIT 131 drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(27)) : 0; BIT 148 drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(25)) : 0; BIT 264 drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c ptxdesc->txdw4 |= cpu_to_le32(BIT(24));/* DATA_SHORT */ BIT 279 drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c ptxdesc->txdw2 |= cpu_to_le32(BIT(19)); BIT 580 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL, (BIT(4) | BIT(3) | BIT(1))); BIT 600 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write32(Adapter, REG_LEDCFG0, usb_read32(Adapter, REG_LEDCFG0) | BIT(23)); BIT 601 drivers/staging/rtl8188eu/hal/usb_halinit.c phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01); BIT 634 drivers/staging/rtl8188eu/hal/usb_halinit.c rfpowerstate = (val8 & BIT(7)) ? rf_off : rf_on; BIT 636 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(adapt, REG_MAC_PINMUX_CFG, usb_read8(adapt, REG_MAC_PINMUX_CFG) & ~(BIT(3))); BIT 639 drivers/staging/rtl8188eu/hal/usb_halinit.c rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off; BIT 771 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_TX_RPT_CTRL, (value8 | BIT(1) | BIT(0))); BIT 864 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write32(Adapter, REG_FWHW_TXQ_CTRL, usb_read32(Adapter, REG_FWHW_TXQ_CTRL) | BIT(12)); BIT 883 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_TX_RPT_CTRL, val8 & (~BIT(1))); BIT 898 drivers/staging/rtl8188eu/hal/usb_halinit.c val8 &= ~BIT(2); /* 0x2[10], FEN_CPUEN */ BIT 908 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_32K_CTRL, val8 & (~BIT(0))); BIT 916 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_RSV_CTRL + 1, (val8 & (~BIT(3)))); BIT 918 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_RSV_CTRL + 1, val8 | BIT(3)); BIT 1106 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(adapt, REG_FWHW_TXQ_CTRL + 2, (haldata->RegFwHwTxQCtrl) | BIT(6)); BIT 1107 drivers/staging/rtl8188eu/hal/usb_halinit.c haldata->RegFwHwTxQCtrl |= BIT(6); BIT 1109 drivers/staging/rtl8188eu/hal/usb_halinit.c haldata->RegReg542 |= BIT(0); BIT 1120 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(adapt, REG_FWHW_TXQ_CTRL + 2, (haldata->RegFwHwTxQCtrl) & (~BIT(6))); BIT 1121 drivers/staging/rtl8188eu/hal/usb_halinit.c haldata->RegFwHwTxQCtrl &= (~BIT(6)); BIT 1123 drivers/staging/rtl8188eu/hal/usb_halinit.c haldata->RegReg542 &= ~(BIT(0)); BIT 1135 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4)); BIT 1172 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_DUAL_TSF_RST, BIT(0)); BIT 1175 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_MBID_NUM, usb_read8(Adapter, REG_MBID_NUM) | BIT(3) | BIT(4)); BIT 1179 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP | EN_BCN_FUNCTION | BIT(1))); BIT 1182 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL_1, usb_read8(Adapter, REG_BCN_CTRL_1) | BIT(0)); BIT 1307 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) & (~BIT(3))); BIT 1313 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(3)); BIT 1338 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); BIT 1341 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4)); BIT 1354 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4)); BIT 1365 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) & (~BIT(4))); BIT 1369 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) & (~BIT(4))); BIT 1397 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) & (~BIT(4))); BIT 1497 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write32(Adapter, RWCAM, BIT(31) | BIT(30)); BIT 1531 drivers/staging/rtl8188eu/hal/usb_halinit.c if (acm_ctrl & BIT(3)) BIT 1536 drivers/staging/rtl8188eu/hal/usb_halinit.c if (acm_ctrl & BIT(2)) BIT 1541 drivers/staging/rtl8188eu/hal/usb_halinit.c if (acm_ctrl & BIT(1)) BIT 1719 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(Adapter, REG_TDECTRL + 2, usb_read8(Adapter, REG_TDECTRL + 2) | BIT(0)); BIT 1737 drivers/staging/rtl8188eu/hal/usb_halinit.c val[0] = (BIT(0) & usb_read8(Adapter, REG_TDECTRL + 2)) ? true : false; BIT 1969 drivers/staging/rtl8188eu/hal/usb_halinit.c usb_write8(adapt, bcn_ctrl_reg, usb_read8(adapt, bcn_ctrl_reg) | BIT(1)); BIT 45 drivers/staging/rtl8188eu/include/drv_types.h #define SPEC_DEV_ID_NONE BIT(0) BIT 46 drivers/staging/rtl8188eu/include/drv_types.h #define SPEC_DEV_ID_DISABLE_HT BIT(1) BIT 47 drivers/staging/rtl8188eu/include/drv_types.h #define SPEC_DEV_ID_ENABLE_PS BIT(2) BIT 48 drivers/staging/rtl8188eu/include/drv_types.h #define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3) BIT 49 drivers/staging/rtl8188eu/include/drv_types.h #define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4) BIT 50 drivers/staging/rtl8188eu/include/drv_types.h #define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5) BIT 76 drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h WIRELESS_MODE_A = BIT(2), BIT 77 drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h WIRELESS_MODE_B = BIT(0), BIT 78 drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h WIRELESS_MODE_G = BIT(1), BIT 79 drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h WIRELESS_MODE_AUTO = BIT(5), BIT 80 drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h WIRELESS_MODE_N_24G = BIT(3), BIT 81 drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h WIRELESS_MODE_N_5G = BIT(4), BIT 82 drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h WIRELESS_MODE_AC = BIT(6) BIT 47 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_1M BIT(0) BIT 48 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_2M BIT(1) BIT 49 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_5_5M BIT(2) BIT 50 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_11M BIT(3) BIT 52 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_6M BIT(4) BIT 53 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_9M BIT(5) BIT 54 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_12M BIT(6) BIT 55 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_18M BIT(7) BIT 56 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_24M BIT(8) BIT 57 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_36M BIT(9) BIT 58 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_48M BIT(10) BIT 59 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_54M BIT(11) BIT 61 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS0 BIT(12) BIT 62 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS1 BIT(13) BIT 63 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS2 BIT(14) BIT 64 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS3 BIT(15) BIT 65 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS4 BIT(16) BIT 66 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS5 BIT(17) BIT 67 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS6 BIT(18) BIT 68 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS7 BIT(19) BIT 70 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS8 BIT(20) BIT 71 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS9 BIT(21) BIT 72 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS10 BIT(22) BIT 73 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS11 BIT(23) BIT 74 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS12 BIT(24) BIT 75 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS13 BIT(25) BIT 76 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS14 BIT(26) BIT 77 drivers/staging/rtl8188eu/include/hal_com.h #define RATE_MCS15 BIT(27) BIT 15 drivers/staging/rtl8188eu/include/hal_intf.h RTW_PCIE = BIT(0), BIT 16 drivers/staging/rtl8188eu/include/hal_intf.h RTW_USB = BIT(1), BIT 17 drivers/staging/rtl8188eu/include/hal_intf.h RTW_SDIO = BIT(2), BIT 18 drivers/staging/rtl8188eu/include/hal_intf.h RTW_GSPI = BIT(3), BIT 141 drivers/staging/rtl8188eu/include/hal_intf.h #define RF_CHANGE_BY_IPS BIT(28) BIT 142 drivers/staging/rtl8188eu/include/hal_intf.h #define RF_CHANGE_BY_PS BIT(29) BIT 143 drivers/staging/rtl8188eu/include/hal_intf.h #define RF_CHANGE_BY_HW BIT(30) BIT 144 drivers/staging/rtl8188eu/include/hal_intf.h #define RF_CHANGE_BY_SW BIT(31) BIT 48 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_AUTH BIT(0) BIT 49 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_ASSOC BIT(1) BIT 50 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_PS BIT(2) BIT 51 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_TIM BIT(3) BIT 52 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_PERM BIT(4) BIT 53 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_AUTHORIZED BIT(5) BIT 54 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ BIT 55 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_SHORT_PREAMBLE BIT(7) BIT 56 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_PREAUTH BIT(8) BIT 57 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_WME BIT(9) BIT 58 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_MFP BIT(10) BIT 59 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_HT BIT(11) BIT 60 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_WPS BIT(12) BIT 61 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_MAYBE_WPS BIT(13) BIT 62 drivers/staging/rtl8188eu/include/ieee80211.h #define WLAN_STA_NONERP BIT(31) BIT 96 drivers/staging/rtl8188eu/include/ieee80211.h #define WPA_CIPHER_NONE BIT(0) BIT 97 drivers/staging/rtl8188eu/include/ieee80211.h #define WPA_CIPHER_WEP40 BIT(1) BIT 98 drivers/staging/rtl8188eu/include/ieee80211.h #define WPA_CIPHER_WEP104 BIT(2) BIT 99 drivers/staging/rtl8188eu/include/ieee80211.h #define WPA_CIPHER_TKIP BIT(3) BIT 100 drivers/staging/rtl8188eu/include/ieee80211.h #define WPA_CIPHER_CCMP BIT(4) BIT 145 drivers/staging/rtl8188eu/include/ieee80211.h WIRELESS_11B = BIT(0), /* tx:cck only, rx:cck only, hw: cck */ BIT 146 drivers/staging/rtl8188eu/include/ieee80211.h WIRELESS_11G = BIT(1), /* tx:ofdm only, rx:ofdm & cck, hw:cck & ofdm*/ BIT 147 drivers/staging/rtl8188eu/include/ieee80211.h WIRELESS_11A = BIT(2), /* tx:ofdm only, rx: ofdm only, hw:ofdm only */ BIT 148 drivers/staging/rtl8188eu/include/ieee80211.h WIRELESS_11_24N = BIT(3), /* tx:MCS only, rx:MCS & cck, hw:MCS & cck */ BIT 149 drivers/staging/rtl8188eu/include/ieee80211.h WIRELESS_11_5N = BIT(4), /* tx:MCS only, rx:MCS & ofdm, hw:ofdm only */ BIT 150 drivers/staging/rtl8188eu/include/ieee80211.h WIRELESS_AC = BIT(6), BIT 301 drivers/staging/rtl8188eu/include/ieee80211.h #define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0) BIT 302 drivers/staging/rtl8188eu/include/ieee80211.h #define RTW_ERP_INFO_USE_PROTECTION BIT(1) BIT 303 drivers/staging/rtl8188eu/include/ieee80211.h #define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2) BIT 348 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_CCK_MODULATION BIT(0) BIT 349 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_OFDM_MODULATION BIT(1) BIT 351 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_24GHZ_BAND BIT(0) BIT 352 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_52GHZ_BAND BIT(1) BIT 373 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_CCK_RATE_1MB_MASK BIT(0) BIT 374 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_CCK_RATE_2MB_MASK BIT(1) BIT 375 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_CCK_RATE_5MB_MASK BIT(2) BIT 376 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_CCK_RATE_11MB_MASK BIT(3) BIT 377 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_OFDM_RATE_6MB_MASK BIT(4) BIT 378 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_OFDM_RATE_9MB_MASK BIT(5) BIT 379 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_OFDM_RATE_12MB_MASK BIT(6) BIT 380 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_OFDM_RATE_18MB_MASK BIT(7) BIT 381 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_OFDM_RATE_24MB_MASK BIT(8) BIT 382 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_OFDM_RATE_36MB_MASK BIT(9) BIT 383 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_OFDM_RATE_48MB_MASK BIT(10) BIT 384 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE80211_OFDM_RATE_54MB_MASK BIT(11) BIT 417 drivers/staging/rtl8188eu/include/ieee80211.h #define SEC_KEY_1 BIT(0) BIT 418 drivers/staging/rtl8188eu/include/ieee80211.h #define SEC_KEY_2 BIT(1) BIT 419 drivers/staging/rtl8188eu/include/ieee80211.h #define SEC_KEY_3 BIT(2) BIT 420 drivers/staging/rtl8188eu/include/ieee80211.h #define SEC_KEY_4 BIT(3) BIT 421 drivers/staging/rtl8188eu/include/ieee80211.h #define SEC_ACTIVE_KEY BIT(4) BIT 422 drivers/staging/rtl8188eu/include/ieee80211.h #define SEC_AUTH_MODE BIT(5) BIT 423 drivers/staging/rtl8188eu/include/ieee80211.h #define SEC_UNICAST_GROUP BIT(6) BIT 424 drivers/staging/rtl8188eu/include/ieee80211.h #define SEC_LEVEL BIT(7) BIT 425 drivers/staging/rtl8188eu/include/ieee80211.h #define SEC_ENABLED BIT(8) BIT 459 drivers/staging/rtl8188eu/include/ieee80211.h #define NETWORK_EMPTY_ESSID BIT(0) BIT 460 drivers/staging/rtl8188eu/include/ieee80211.h #define NETWORK_HAS_OFDM BIT(1) BIT 461 drivers/staging/rtl8188eu/include/ieee80211.h #define NETWORK_HAS_CCK BIT(2) BIT 512 drivers/staging/rtl8188eu/include/ieee80211.h #define CFG_IEEE80211_RESERVE_FCS BIT(0) BIT 513 drivers/staging/rtl8188eu/include/ieee80211.h #define CFG_IEEE80211_COMPUTE_FCS BIT(1) BIT 517 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE_A BIT(0) BIT 518 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE_B BIT(1) BIT 519 drivers/staging/rtl8188eu/include/ieee80211.h #define IEEE_G BIT(2) BIT 637 drivers/staging/rtl8188eu/include/ieee80211.h RTW_IEEE80211_CHAN_DISABLED = BIT(0), BIT 638 drivers/staging/rtl8188eu/include/ieee80211.h RTW_IEEE80211_CHAN_PASSIVE_SCAN = BIT(1), BIT 639 drivers/staging/rtl8188eu/include/ieee80211.h RTW_IEEE80211_CHAN_NO_IBSS = BIT(2), BIT 640 drivers/staging/rtl8188eu/include/ieee80211.h RTW_IEEE80211_CHAN_RADAR = BIT(3), BIT 641 drivers/staging/rtl8188eu/include/ieee80211.h RTW_IEEE80211_CHAN_NO_HT40PLUS = BIT(4), BIT 642 drivers/staging/rtl8188eu/include/ieee80211.h RTW_IEEE80211_CHAN_NO_HT40MINUS = BIT(5), BIT 386 drivers/staging/rtl8188eu/include/odm.h ODM_BB_DIG = BIT(0), BIT 387 drivers/staging/rtl8188eu/include/odm.h ODM_BB_RA_MASK = BIT(1), BIT 388 drivers/staging/rtl8188eu/include/odm.h ODM_BB_DYNAMIC_TXPWR = BIT(2), BIT 389 drivers/staging/rtl8188eu/include/odm.h ODM_BB_FA_CNT = BIT(3), BIT 390 drivers/staging/rtl8188eu/include/odm.h ODM_BB_RSSI_MONITOR = BIT(4), BIT 391 drivers/staging/rtl8188eu/include/odm.h ODM_BB_CCK_PD = BIT(5), BIT 392 drivers/staging/rtl8188eu/include/odm.h ODM_BB_ANT_DIV = BIT(6), BIT 393 drivers/staging/rtl8188eu/include/odm.h ODM_BB_PWR_SAVE = BIT(7), BIT 394 drivers/staging/rtl8188eu/include/odm.h ODM_BB_PWR_TRA = BIT(8), BIT 395 drivers/staging/rtl8188eu/include/odm.h ODM_BB_RATE_ADAPTIVE = BIT(9), BIT 396 drivers/staging/rtl8188eu/include/odm.h ODM_BB_PATH_DIV = BIT(10), BIT 397 drivers/staging/rtl8188eu/include/odm.h ODM_BB_PSD = BIT(11), BIT 398 drivers/staging/rtl8188eu/include/odm.h ODM_BB_RXHP = BIT(12), BIT 401 drivers/staging/rtl8188eu/include/odm.h ODM_MAC_EDCA_TURBO = BIT(16), BIT 402 drivers/staging/rtl8188eu/include/odm.h ODM_MAC_EARLY_MODE = BIT(17), BIT 405 drivers/staging/rtl8188eu/include/odm.h ODM_RF_TX_PWR_TRACK = BIT(24), BIT 406 drivers/staging/rtl8188eu/include/odm.h ODM_RF_RX_GAIN_TRACK = BIT(25), BIT 407 drivers/staging/rtl8188eu/include/odm.h ODM_RF_CALIBRATION = BIT(26), BIT 410 drivers/staging/rtl8188eu/include/odm.h #define ODM_RTL8188E BIT(4) BIT 426 drivers/staging/rtl8188eu/include/odm.h ODM_RF_TX_A = BIT(0), BIT 427 drivers/staging/rtl8188eu/include/odm.h ODM_RF_TX_B = BIT(1), BIT 428 drivers/staging/rtl8188eu/include/odm.h ODM_RF_TX_C = BIT(2), BIT 429 drivers/staging/rtl8188eu/include/odm.h ODM_RF_TX_D = BIT(3), BIT 430 drivers/staging/rtl8188eu/include/odm.h ODM_RF_RX_A = BIT(4), BIT 431 drivers/staging/rtl8188eu/include/odm.h ODM_RF_RX_B = BIT(5), BIT 432 drivers/staging/rtl8188eu/include/odm.h ODM_RF_RX_C = BIT(6), BIT 433 drivers/staging/rtl8188eu/include/odm.h ODM_RF_RX_D = BIT(7), BIT 464 drivers/staging/rtl8188eu/include/odm.h ODM_NO_LINK = BIT(0), BIT 465 drivers/staging/rtl8188eu/include/odm.h ODM_LINK = BIT(1), BIT 466 drivers/staging/rtl8188eu/include/odm.h ODM_SCAN = BIT(2), BIT 467 drivers/staging/rtl8188eu/include/odm.h ODM_POWERSAVE = BIT(3), BIT 468 drivers/staging/rtl8188eu/include/odm.h ODM_AP_MODE = BIT(4), BIT 469 drivers/staging/rtl8188eu/include/odm.h ODM_CLIENT_MODE = BIT(5), BIT 470 drivers/staging/rtl8188eu/include/odm.h ODM_AD_HOC = BIT(6), BIT 471 drivers/staging/rtl8188eu/include/odm.h ODM_WIFI_DIRECT = BIT(7), BIT 472 drivers/staging/rtl8188eu/include/odm.h ODM_WIFI_DISPLAY = BIT(8), BIT 478 drivers/staging/rtl8188eu/include/odm.h ODM_WM_B = BIT(0), BIT 479 drivers/staging/rtl8188eu/include/odm.h ODM_WM_G = BIT(1), BIT 480 drivers/staging/rtl8188eu/include/odm.h ODM_WM_A = BIT(2), BIT 481 drivers/staging/rtl8188eu/include/odm.h ODM_WM_N24G = BIT(3), BIT 482 drivers/staging/rtl8188eu/include/odm.h ODM_WM_N5G = BIT(4), BIT 483 drivers/staging/rtl8188eu/include/odm.h ODM_WM_AUTO = BIT(5), BIT 484 drivers/staging/rtl8188eu/include/odm.h ODM_WM_AC = BIT(6), BIT 489 drivers/staging/rtl8188eu/include/odm.h ODM_BAND_2_4G = BIT(0), BIT 490 drivers/staging/rtl8188eu/include/odm.h ODM_BAND_5G = BIT(1), BIT 47 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_DIG BIT(0) BIT 48 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_RA_MASK BIT(1) BIT 49 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_DYNAMIC_TXPWR BIT(2) BIT 50 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_FA_CNT BIT(3) BIT 51 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_RSSI_MONITOR BIT(4) BIT 52 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_CCK_PD BIT(5) BIT 53 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_ANT_DIV BIT(6) BIT 54 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_PWR_SAVE BIT(7) BIT 55 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_PWR_TRA BIT(8) BIT 56 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_RATE_ADAPTIVE BIT(9) BIT 57 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_PATH_DIV BIT(10) BIT 58 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_PSD BIT(11) BIT 59 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_DYNAMIC_PRICCA BIT(12) BIT 60 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_RXHP BIT(13) BIT 62 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_EDCA_TURBO BIT(16) BIT 63 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_EARLY_MODE BIT(17) BIT 65 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_TX_PWR_TRACK BIT(24) BIT 66 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_RX_GAIN_TRACK BIT(25) BIT 67 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_CALIBRATION BIT(26) BIT 69 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_COMMON BIT(30) BIT 70 drivers/staging/rtl8188eu/include/odm_debug.h #define ODM_COMP_INIT BIT(31) BIT 53 drivers/staging/rtl8188eu/include/pwrseq.h {0x0006, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ BIT 55 drivers/staging/rtl8188eu/include/pwrseq.h {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \ BIT 57 drivers/staging/rtl8188eu/include/pwrseq.h {0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ BIT 59 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \ BIT 61 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \ BIT 63 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ BIT 65 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(0), 0}, \ BIT 67 drivers/staging/rtl8188eu/include/pwrseq.h {0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ BIT 78 drivers/staging/rtl8188eu/include/pwrseq.h {0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ BIT 80 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ BIT 82 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \ BIT 91 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ BIT 93 drivers/staging/rtl8188eu/include/pwrseq.h {0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, BIT(7)}, \ BIT 95 drivers/staging/rtl8188eu/include/pwrseq.h {0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ BIT 97 drivers/staging/rtl8188eu/include/pwrseq.h {0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ BIT 106 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ BIT 115 drivers/staging/rtl8188eu/include/pwrseq.h {0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ BIT 117 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ BIT 121 drivers/staging/rtl8188eu/include/pwrseq.h {0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ BIT 123 drivers/staging/rtl8188eu/include/pwrseq.h {0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ BIT 132 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ BIT 141 drivers/staging/rtl8188eu/include/pwrseq.h {0x0006, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \ BIT 143 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ BIT 152 drivers/staging/rtl8188eu/include/pwrseq.h {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \ BIT 171 drivers/staging/rtl8188eu/include/pwrseq.h {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \ BIT 177 drivers/staging/rtl8188eu/include/pwrseq.h {0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), 0}, \ BIT 179 drivers/staging/rtl8188eu/include/pwrseq.h {0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \ BIT 193 drivers/staging/rtl8188eu/include/pwrseq.h {0x0008, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ BIT 195 drivers/staging/rtl8188eu/include/pwrseq.h {0x0109, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(7), 0}, \ BIT 197 drivers/staging/rtl8188eu/include/pwrseq.h {0x0029, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \ BIT 199 drivers/staging/rtl8188eu/include/pwrseq.h {0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ BIT 204 drivers/staging/rtl8188eu/include/pwrseq.h PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \ BIT 20 drivers/staging/rtl8188eu/include/pwrseqcmd.h #define PWR_CUT_TESTCHIP_MSK BIT(0) BIT 21 drivers/staging/rtl8188eu/include/pwrseqcmd.h #define PWR_CUT_A_MSK BIT(1) BIT 22 drivers/staging/rtl8188eu/include/pwrseqcmd.h #define PWR_CUT_B_MSK BIT(2) BIT 23 drivers/staging/rtl8188eu/include/pwrseqcmd.h #define PWR_CUT_C_MSK BIT(3) BIT 24 drivers/staging/rtl8188eu/include/pwrseqcmd.h #define PWR_CUT_D_MSK BIT(4) BIT 25 drivers/staging/rtl8188eu/include/pwrseqcmd.h #define PWR_CUT_E_MSK BIT(5) BIT 26 drivers/staging/rtl8188eu/include/pwrseqcmd.h #define PWR_CUT_F_MSK BIT(6) BIT 27 drivers/staging/rtl8188eu/include/pwrseqcmd.h #define PWR_CUT_G_MSK BIT(7) BIT 85 drivers/staging/rtl8188eu/include/rtl8188e_hal.h #define TX_SELE_HQ BIT(0) /* High Queue */ BIT 86 drivers/staging/rtl8188eu/include/rtl8188e_hal.h #define TX_SELE_LQ BIT(1) /* Low Queue */ BIT 87 drivers/staging/rtl8188eu/include/rtl8188e_hal.h #define TX_SELE_NQ BIT(2) /* Normal Queue */ BIT 339 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RXERR_RPT_RST BIT(27) BIT 443 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CmdEEPROM_En BIT(5) BIT 445 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CmdEERPOMSEL BIT(4) BIT 446 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define Cmd9346CR_9356SEL BIT(4) BIT 450 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define GPIOSEL_ENBT BIT(5) BIT 464 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HSIMR_GPIO12_0_INT_EN BIT(0) BIT 465 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HSIMR_SPS_OCP_INT_EN BIT(5) BIT 466 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HSIMR_RON_INT_EN BIT(6) BIT 467 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HSIMR_PDN_INT_EN BIT(7) BIT 468 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HSIMR_GPIO9_INT_EN BIT(25) BIT 471 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HSISR_GPIO12_0_INT BIT(0) BIT 472 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HSISR_SPS_OCP_INT BIT(5) BIT 473 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HSISR_RON_INT_EN BIT(6) BIT 474 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HSISR_PDNINT BIT(7) BIT 475 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HSISR_GPIO9_INT BIT(25) BIT 500 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CMD_INIT_LLT BIT(0) BIT 501 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CMD_READ_EFUSE_MAP BIT(1) BIT 502 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CMD_EFUSE_PATCH BIT(2) BIT 503 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CMD_IOCONFIG BIT(3) BIT 504 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CMD_INIT_LLT_ERR BIT(4) BIT 505 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CMD_READ_EFUSE_MAP_ERR BIT(5) BIT 506 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CMD_EFUSE_PATCH_ERR BIT(6) BIT 507 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CMD_IOCONFIG_ERR BIT(7) BIT 511 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_1M BIT(0) BIT 512 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_2M BIT(1) BIT 513 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_5_5M BIT(2) BIT 514 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_11M BIT(3) BIT 515 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_6M BIT(4) BIT 516 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_9M BIT(5) BIT 517 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_12M BIT(6) BIT 518 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_18M BIT(7) BIT 519 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_24M BIT(8) BIT 520 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_36M BIT(9) BIT 521 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_48M BIT(10) BIT 522 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_54M BIT(11) BIT 523 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_MCS0 BIT(12) BIT 524 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_MCS1 BIT(13) BIT 525 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_MCS2 BIT(14) BIT 526 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_MCS3 BIT(15) BIT 527 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_MCS4 BIT(16) BIT 528 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_MCS5 BIT(17) BIT 529 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_MCS6 BIT(18) BIT 530 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RRSR_MCS7 BIT(19) BIT 534 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) BIT 535 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) BIT 538 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BW_OPMODE_20MHZ BIT(2) BIT 539 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BW_OPMODE_5G BIT(1) BIT 542 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CAM_VALID BIT(15) BIT 544 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CAM_USEDK BIT(5) BIT 561 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CAM_WRITE BIT(16) BIT 563 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CAM_POLLINIG BIT(31) BIT 570 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define WOW_PMEN BIT(0) /* Power management Enable. */ BIT 571 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define WOW_WOMEN BIT(1) /* WoW function on or off. */ BIT 572 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define WOW_MAGIC BIT(2) /* Magic packet */ BIT 573 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define WOW_UWF BIT(3) /* Unicast Wakeup frame. */ BIT 579 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_TXCCK_88E BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */ BIT 580 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_PSTIMEOUT_88E BIT(29) /* Power Save Time Out Interrupt */ BIT 581 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_GTINT4_88E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ BIT 582 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_GTINT3_88E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ BIT 583 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_TBDER_88E BIT(26) /* Transmit Beacon0 Error */ BIT 584 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_TBDOK_88E BIT(25) /* Transmit Beacon0 OK */ BIT 585 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_TSF_BIT32_TOGGLE_88E BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ BIT 586 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDMAINT0_88E BIT(20) /* Beacon DMA Interrupt 0 */ BIT 587 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDERR0_88E BIT(16) /* Beacon Queue DMA Error 0 */ BIT 588 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_HSISR_IND_ON_INT_88E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ BIT 589 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDMAINT_E_88E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ BIT 590 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_ATIMEND_88E BIT(12) /* CTWidnow End or ATIM Window End */ BIT 591 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_HISR1_IND_INT_88E BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ BIT 592 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_C2HCMD_88E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ BIT 593 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_CPWM2_88E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ BIT 594 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_CPWM_88E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ BIT 595 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_HIGHDOK_88E BIT(7) /* High Queue DMA OK */ BIT 596 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_MGNTDOK_88E BIT(6) /* Management Queue DMA OK */ BIT 597 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BKDOK_88E BIT(5) /* AC_BK DMA OK */ BIT 598 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BEDOK_88E BIT(4) /* AC_BE DMA OK */ BIT 599 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_VIDOK_88E BIT(3) /* AC_VI DMA OK */ BIT 600 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_VODOK_88E BIT(2) /* AC_VO DMA OK */ BIT 601 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_RDU_88E BIT(1) /* Rx Descriptor Unavailable */ BIT 602 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_ROK_88E BIT(0) /* Receive DMA OK */ BIT 605 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDMAINT7_88E BIT(27) /* Beacon DMA Interrupt 7 */ BIT 606 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDMAINT6_88E BIT(26) /* Beacon DMA Interrupt 6 */ BIT 607 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDMAINT5_88E BIT(25) /* Beacon DMA Interrupt 5 */ BIT 608 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDMAINT4_88E BIT(24) /* Beacon DMA Interrupt 4 */ BIT 609 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDMAINT3_88E BIT(23) /* Beacon DMA Interrupt 3 */ BIT 610 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDMAINT2_88E BIT(22) /* Beacon DMA Interrupt 2 */ BIT 611 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDMAINT1_88E BIT(21) /* Beacon DMA Interrupt 1 */ BIT 612 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDERR7_88E BIT(20) /* Beacon DMA Error Int 7 */ BIT 613 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDERR6_88E BIT(19) /* Beacon DMA Error Int 6 */ BIT 614 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDERR5_88E BIT(18) /* Beacon DMA Error Int 5 */ BIT 615 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDERR4_88E BIT(17) /* Beacon DMA Error Int 4 */ BIT 616 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDERR3_88E BIT(16) /* Beacon DMA Error Int 3 */ BIT 617 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDERR2_88E BIT(15) /* Beacon DMA Error Int 2 */ BIT 618 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_BCNDERR1_88E BIT(14) /* Beacon DMA Error Int 1 */ BIT 619 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_ATIMEND_E_88E BIT(13) /* ATIM Window End Ext for Win7 */ BIT 620 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_TXERR_88E BIT(11) /* Tx Err Flag Int Status, write 1 clear. */ BIT 621 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_RXERR_88E BIT(10) /* Rx Err Flag INT Status, Write 1 clear */ BIT 622 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_TXFOVW_88E BIT(9) /* Transmit FIFO Overflow */ BIT 623 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IMR_RXFOVW_88E BIT(8) /* Receive FIFO Overflow */ BIT 660 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define StopBecon BIT(6) BIT 661 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define StopHigh BIT(5) BIT 662 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define StopMgt BIT(4) BIT 663 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define StopBK BIT(3) BIT 664 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define StopBE BIT(2) BIT 665 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define StopVI BIT(1) BIT 666 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define StopVO BIT(0) BIT 669 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_APPFCS BIT(31) /* WMAC append FCS after payload */ BIT 670 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_APP_MIC BIT(30) BIT 671 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_APP_PHYSTS BIT(28) BIT 672 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_APP_ICV BIT(29) BIT 673 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_APP_PHYST_RXFF BIT(28) BIT 674 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_APP_BA_SSN BIT(27) /* Accept BA SSN */ BIT 675 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_ENMBID BIT(24) /* Enable Multiple BssId. */ BIT 676 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_LSIGEN BIT(23) BIT 677 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_MFBEN BIT(22) BIT 678 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ BIT 679 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_AMF BIT(13) /* Accept management type frame */ BIT 680 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_ACF BIT(12) /* Accept control type frame */ BIT 681 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_ADF BIT(11) /* Accept data type frame */ BIT 682 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_AICV BIT(9) /* Accept ICV error packet */ BIT 683 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */ BIT 684 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet BIT 687 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match (Data)*/ BIT 689 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_APWRMGT BIT(5) /* Accept power management pkt*/ BIT 690 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_ADD3 BIT(4) /* Accept address 3 match pkt */ BIT 691 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_AB BIT(3) /* Accept broadcast packet */ BIT 692 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_AM BIT(2) /* Accept multicast packet */ BIT 693 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_APM BIT(1) /* Accept physical match pkt */ BIT 694 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RCR_AAP BIT(0) /* Accept all unicast packet */ BIT 711 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ISO_MD2PP BIT(0) BIT 712 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ISO_UA2USB BIT(1) BIT 713 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ISO_UD2CORE BIT(2) BIT 714 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ISO_PA2PCIE BIT(3) BIT 715 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ISO_PD2CORE BIT(4) BIT 716 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ISO_IP2MAC BIT(5) BIT 717 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ISO_DIOP BIT(6) BIT 718 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ISO_DIOE BIT(7) BIT 719 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ISO_EB2CORE BIT(8) BIT 720 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ISO_DIOR BIT(9) BIT 721 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PWC_EV12V BIT(15) BIT 724 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_BBRSTB BIT(0) BIT 725 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_BB_GLB_RSTn BIT(1) BIT 726 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_USBA BIT(2) BIT 727 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_UPLL BIT(3) BIT 728 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_USBD BIT(4) BIT 729 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_DIO_PCIE BIT(5) BIT 730 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_PCIEA BIT(6) BIT 731 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_PPLL BIT(7) BIT 732 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_PCIED BIT(8) BIT 733 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_DIOE BIT(9) BIT 734 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_CPUEN BIT(10) BIT 735 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_DCORE BIT(11) BIT 736 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_ELDR BIT(12) BIT 737 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_DIO_RF BIT(13) BIT 738 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_HWPDN BIT(14) BIT 739 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_MREGEN BIT(15) BIT 742 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PFM_LDALL BIT(0) BIT 743 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PFM_ALDN BIT(1) BIT 744 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PFM_LDKP BIT(2) BIT 745 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PFM_WOWL BIT(3) BIT 746 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EnPDN BIT(4) BIT 747 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PDN_PL BIT(5) BIT 748 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APFM_ONMAC BIT(8) BIT 749 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APFM_OFF BIT(9) BIT 750 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APFM_RSM BIT(10) BIT 751 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AFSM_HSUS BIT(11) BIT 752 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AFSM_PCIE BIT(12) BIT 753 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APDM_MAC BIT(13) BIT 754 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APDM_HOST BIT(14) BIT 755 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APDM_HPDN BIT(15) BIT 756 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RDY_MACON BIT(16) BIT 757 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SUS_HOST BIT(17) BIT 758 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ROP_ALD BIT(20) BIT 759 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ROP_PWR BIT(21) BIT 760 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ROP_SPS BIT(22) BIT 761 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SOP_MRST BIT(25) BIT 762 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SOP_FUSE BIT(26) BIT 763 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SOP_ABG BIT(27) BIT 764 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SOP_AMB BIT(28) BIT 765 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SOP_RCK BIT(29) BIT 766 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SOP_A8M BIT(30) BIT 767 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define XOP_BTCK BIT(31) BIT 770 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ANAD16V_EN BIT(0) BIT 771 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ANA8M BIT(1) BIT 772 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define MACSLP BIT(4) BIT 773 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define LOADER_CLK_EN BIT(5) BIT 777 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BOOT_FROM_EEPROM BIT(4) BIT 778 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EEPROM_EN BIT(5) BIT 785 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RF_EN BIT(0) BIT 786 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RF_RSTB BIT(1) BIT 787 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RF_SDMRSTB BIT(2) BIT 790 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define LDV12_EN BIT(0) BIT 791 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define LDV12_SDBY BIT(1) BIT 792 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define LPLDO_HSM BIT(2) BIT 793 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define LPLDO_LSM_DIS BIT(3) BIT 797 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ALD_EN BIT(18) BIT 798 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EF_PD BIT(19) BIT 799 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EF_FLAG BIT(31) BIT 802 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EF_TRPT BIT(7) BIT 804 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EF_CELL_SEL (BIT(8) | BIT(9)) BIT 805 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define LDOE25_EN BIT(31) BIT 818 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define MCUFWDL_EN BIT(0) BIT 819 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define MCUFWDL_RDY BIT(1) BIT 820 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FWDL_ChkSum_rpt BIT(2) BIT 821 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define MACINI_RDY BIT(3) BIT 822 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BBINI_RDY BIT(4) BIT 823 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RFINI_RDY BIT(5) BIT 824 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define WINTINI_RDY BIT(6) BIT 825 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */ BIT 826 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ROM_DLEN BIT(19) BIT 827 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CPRST BIT(23) BIT 830 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define XCLK_VLD BIT(0) BIT 831 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ACLK_VLD BIT(1) BIT 832 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define UCLK_VLD BIT(2) BIT 833 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PCLK_VLD BIT(3) BIT 834 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PCIRSTB BIT(4) BIT 835 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define V15_VLD BIT(5) BIT 836 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SW_OFFLOAD_EN BIT(7) BIT 837 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SIC_IDLE BIT(8) BIT 838 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BD_MAC2 BIT(9) BIT 839 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BD_MAC1 BIT(10) BIT 840 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define IC_MACPHY_MODE BIT(11) BIT 841 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) BIT 842 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BT_FUNC BIT(16) BIT 843 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define VENDOR_ID BIT(19) BIT 844 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PAD_HWPD_IDN BIT(22) BIT 845 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define TRP_VAUX_EN BIT(23) /* RTL ID */ BIT 846 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define TRP_BT_EN BIT(24) BIT 847 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BD_PKG_SEL BIT(25) BIT 848 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BD_HCI_SEL BIT(26) BIT 849 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define TYPE_ID BIT(27) BIT 855 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EFS_HCI_SEL (BIT(0) | BIT(1)) BIT 856 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PAD_HCI_SEL (BIT(2) | BIT(3)) BIT 857 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HCI_SEL (BIT(4) | BIT(5)) BIT 858 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PKG_SEL_HCI BIT(6) BIT 859 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_GPS BIT(7) BIT 860 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_BT BIT(8) BIT 861 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_WL BIT(9) BIT 862 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_PCI BIT(10) BIT 863 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define FEN_USB BIT(11) BIT 864 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BTRF_HWPDN_N BIT(12) BIT 865 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define WLRF_HWPDN_N BIT(13) BIT 866 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PDN_BT_N BIT(14) BIT 867 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PDN_GPS_N BIT(15) BIT 868 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BT_CTL_HWPDN BIT(16) BIT 869 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define GPS_CTL_HWPDN BIT(17) BIT 870 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PPHY_SUSB BIT(20) BIT 871 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define UPHY_SUSB BIT(21) BIT 872 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PCI_SUSEN BIT(22) BIT 873 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define USB_SUSEN BIT(23) BIT 874 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) BIT 877 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ BIT 884 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HCI_TXDMA_EN BIT(0) BIT 885 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HCI_RXDMA_EN BIT(1) BIT 886 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define TXDMA_EN BIT(2) BIT 887 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RXDMA_EN BIT(3) BIT 888 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PROTOCOL_EN BIT(4) BIT 889 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SCHEDULE_EN BIT(5) BIT 890 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define MACTXEN BIT(6) BIT 891 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define MACRXEN BIT(7) BIT 892 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ENSWBCN BIT(8) BIT 893 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ENSEC BIT(9) BIT 894 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ BIT 919 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RXDMA_ARBBW_EN BIT(0) BIT 920 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RXSHFT_EN BIT(1) BIT 921 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RXDMA_AGG_EN BIT(2) BIT 922 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define QS_VO_QUEUE BIT(8) BIT 923 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define QS_VI_QUEUE BIT(9) BIT 924 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define QS_BE_QUEUE BIT(10) BIT 925 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define QS_BK_QUEUE BIT(11) BIT 926 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define QS_MANAGER_QUEUE BIT(12) BIT 927 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define QS_HIGH_QUEUE BIT(13) BIT 929 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HQSEL_VOQ BIT(0) BIT 930 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HQSEL_VIQ BIT(1) BIT 931 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HQSEL_BEQ BIT(2) BIT 932 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HQSEL_BKQ BIT(3) BIT 933 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HQSEL_MGTQ BIT(4) BIT 934 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HQSEL_HIQ BIT(5) BIT 968 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HPQ_PUBLIC_DIS BIT(24) BIT 969 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define LPQ_PUBLIC_DIS BIT(25) BIT 970 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define LD_RQPN BIT(31) BIT 973 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BCN_VALID BIT(16) BIT 982 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define DROP_DATA_EN BIT(9) BIT 989 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RXPKT_RELEASE_POLL BIT(16) BIT 990 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RXDMA_IDLE BIT(17) BIT 991 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define RW_RELEASE_EN BIT(18) BIT 995 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EN_AMPDU_RTY_NEW BIT(7) BIT 1017 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EN_MBSSID BIT(1) BIT 1018 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EN_TXBCN_RPT BIT(2) BIT 1019 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EN_BCN_FUNCTION BIT(3) BIT 1020 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define DIS_TSF_UPDATE BIT(3) BIT 1023 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) BIT 1024 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define DIS_TSF_UDT0_TEST_CHIP BIT(5) BIT 1025 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define STOP_BCNQ BIT(6) BIT 1028 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AcmHw_HwEn BIT(0) BIT 1029 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AcmHw_BeqEn BIT(1) BIT 1030 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AcmHw_ViqEn BIT(2) BIT 1031 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AcmHw_VoqEn BIT(3) BIT 1032 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AcmHw_BeqStatus BIT(4) BIT 1033 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AcmHw_ViqStatus BIT(5) BIT 1034 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AcmHw_VoqStatus BIT(6) BIT 1038 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APSDOFF BIT(6) BIT 1039 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APSDOFF_STATUS BIT(7) BIT 1047 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define TSFRST BIT(0) BIT 1048 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define DIS_GCLK BIT(1) BIT 1049 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PAD_SEL BIT(2) BIT 1050 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PWR_ST BIT(6) BIT 1051 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define PWRBIT_OW_EN BIT(7) BIT 1052 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ACRC BIT(8) BIT 1053 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CFENDFORM BIT(9) BIT 1054 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ICV BIT(10) BIT 1057 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AAP BIT(0) BIT 1058 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APM BIT(1) BIT 1059 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AM BIT(2) BIT 1060 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AB BIT(3) BIT 1061 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ADD3 BIT(4) BIT 1062 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APWRMGT BIT(5) BIT 1063 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CBSSID BIT(6) BIT 1064 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CBSSID_DATA BIT(6) BIT 1065 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define CBSSID_BCN BIT(7) BIT 1066 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ACRC32 BIT(8) BIT 1067 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AICV BIT(9) BIT 1068 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ADF BIT(11) BIT 1069 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define ACF BIT(12) BIT 1070 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define AMF BIT(13) BIT 1071 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HTC_LOC_CTRL BIT(14) BIT 1072 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define UC_DATA_EN BIT(16) BIT 1073 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BM_DATA_EN BIT(17) BIT 1074 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define MFBEN BIT(22) BIT 1075 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define LSIGEN BIT(23) BIT 1076 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define EnMBID BIT(24) BIT 1077 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APP_BASSN BIT(27) BIT 1078 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APP_PHYSTS BIT(28) BIT 1079 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APP_ICV BIT(29) BIT 1080 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APP_MIC BIT(30) BIT 1081 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define APP_FCS BIT(31) BIT 1084 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ BIT 1085 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ BIT 1086 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ BIT 1087 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ BIT 1088 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ BIT 1089 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ BIT 1090 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SCR_TXBCUSEDK BIT(6) /* Force Tx Bcast pkt Use Default Key */ BIT 1091 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SCR_RXBCUSEDK BIT(7) /* Force Rx Bcast pkt Use Default Key */ BIT 1162 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_RX_REQUEST_MSK BIT(0) BIT 1163 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_AVAL_MSK BIT(1) BIT 1164 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_TXERR_MSK BIT(2) BIT 1165 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_RXERR_MSK BIT(3) BIT 1166 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_TXFOVW_MSK BIT(4) BIT 1167 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_RXFOVW_MSK BIT(5) BIT 1168 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_TXBCNOK_MSK BIT(6) BIT 1169 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_TXBCNERR_MSK BIT(7) BIT 1170 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_BCNERLY_INT_MSK BIT(16) BIT 1171 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_C2HCMD_MSK BIT(17) BIT 1172 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_CPWM1_MSK BIT(18) BIT 1173 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_CPWM2_MSK BIT(19) BIT 1174 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_HSISR_IND_MSK BIT(20) BIT 1175 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_GTINT3_IND_MSK BIT(21) BIT 1176 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_GTINT4_IND_MSK BIT(22) BIT 1177 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_PSTIMEOUT_MSK BIT(23) BIT 1178 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_OCPINT_MSK BIT(24) BIT 1179 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_ATIMEND_MSK BIT(25) BIT 1180 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_ATIMEND_E_MSK BIT(26) BIT 1181 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_CTWEND_MSK BIT(27) BIT 1184 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_MCU_ERR_MSK BIT(28) BIT 1185 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT(29) BIT 1188 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_RX_REQUEST BIT(0) BIT 1189 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_AVAL BIT(1) BIT 1190 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_TXERR BIT(2) BIT 1191 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_RXERR BIT(3) BIT 1192 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_TXFOVW BIT(4) BIT 1193 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_RXFOVW BIT(5) BIT 1194 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_TXBCNOK BIT(6) BIT 1195 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_TXBCNERR BIT(7) BIT 1196 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_BCNERLY_INT BIT(16) BIT 1197 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_C2HCMD BIT(17) BIT 1198 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_CPWM1 BIT(18) BIT 1199 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_CPWM2 BIT(19) BIT 1200 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_HSISR_IND BIT(20) BIT 1201 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_GTINT3_IND BIT(21) BIT 1202 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_GTINT4_IND BIT(22) BIT 1203 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_PSTIME BIT(23) BIT 1204 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_OCPINT BIT(24) BIT 1205 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_ATIMEND BIT(25) BIT 1206 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_ATIMEND_E BIT(26) BIT 1207 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_CTWEND BIT(27) BIT 1210 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_MCU_ERR BIT(28) BIT 1211 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define SDIO_HISR_TSF_BIT32_TOGGLE BIT(29) BIT 1221 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HCI_RESUME_PWR_RDY BIT(1) BIT 1222 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HCI_SUS_CTRL BIT(0) BIT 1234 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define USB_SPEED_MASK BIT(5) BIT 1240 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define USB_AGG_EN BIT(3) BIT 1244 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define INT_BULK_SEL BIT(4) BIT 1258 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define WL_HWPDN_EN BIT(0) BIT 1260 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define WL_HWPDN_SL BIT(1) BIT 1262 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define WL_FUNC_EN BIT(2) BIT 1264 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define WL_HWROF_EN BIT(3) BIT 1266 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BT_HWPDN_EN BIT(16) BIT 1268 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BT_HWPDN_SL BIT(17) BIT 1270 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BT_FUNC_EN BIT(18) BIT 1272 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define BT_HWROF_EN BIT(19) BIT 1274 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define GPS_HWPDN_EN BIT(20) BIT 1276 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define GPS_HWPDN_SL BIT(21) BIT 1278 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define GPS_FUNC_EN BIT(22) BIT 1281 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3) BIT 1282 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2) BIT 1283 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1) BIT 1284 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0) BIT 1294 drivers/staging/rtl8188eu/include/rtl8188e_spec.h #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) BIT 48 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define BMC BIT(24) BIT 49 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define LSG BIT(26) BIT 50 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define FSG BIT(27) BIT 51 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define OWN BIT(31) BIT 58 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define NAVUSEHDR BIT(20) BIT 63 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define AGG_EN BIT(12) BIT 64 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define AGG_BK BIT(16) BIT 66 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define ANTSEL_A BIT(24) BIT 67 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define ANTSEL_B BIT(25) BIT 74 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define EN_HWSEQ BIT(31) BIT 77 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define QOS BIT(6) BIT 78 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define HW_SSN BIT(7) BIT 79 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define USERATE BIT(8) BIT 80 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define DISDATAFB BIT(10) BIT 81 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define CTS_2_SELF BIT(11) BIT 82 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define RTS_EN BIT(12) BIT 83 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define HW_RTS_EN BIT(13) BIT 84 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define DATA_SHORT BIT(24) BIT 87 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define DATA_BW BIT(25) BIT 90 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define RTY_LMT_EN BIT(17) BIT 99 drivers/staging/rtl8188eu/include/rtl8188e_xmit.h #define SGI BIT(6) BIT 25 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_xmit_c_ BIT(0) BIT 26 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_xmit_osdep_c_ BIT(1) BIT 27 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_recv_c_ BIT(2) BIT 28 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_recv_osdep_c_ BIT(3) BIT 29 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_mlme_c_ BIT(4) BIT 30 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_mlme_osdep_c_ BIT(5) BIT 31 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_sta_mgt_c_ BIT(6) BIT 32 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_cmd_c_ BIT(7) BIT 33 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_cmd_osdep_c_ BIT(8) BIT 34 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_io_c_ BIT(9) BIT 35 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_io_osdep_c_ BIT(10) BIT 36 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_os_intfs_c_ BIT(11) BIT 37 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_security_c_ BIT(12) BIT 38 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_eeprom_c_ BIT(13) BIT 39 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_hal_init_c_ BIT(14) BIT 40 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_hci_hal_init_c_ BIT(15) BIT 41 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_ioctl_c_ BIT(16) BIT 42 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_ioctl_set_c_ BIT(17) BIT 43 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_ioctl_query_c_ BIT(18) BIT 44 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_pwrctrl_c_ BIT(19) BIT 45 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_hci_intfs_c_ BIT(20) BIT 46 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_hci_ops_c_ BIT(21) BIT 47 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_osdep_service_c_ BIT(22) BIT 48 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_mp_ BIT(23) BIT 49 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_hci_ops_os_c_ BIT(24) BIT 50 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl871x_ioctl_os_c BIT(25) BIT 51 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl8712_cmd_c_ BIT(26) BIT 52 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl8192c_xmit_c_ BIT(27) BIT 53 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_hal_xmit_c_ BIT(28) BIT 54 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_efuse_ BIT(29) BIT 55 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl8712_recv_c_ BIT(30) BIT 56 drivers/staging/rtl8188eu/include/rtw_debug.h #define _module_rtl8712_led_c_ BIT(31) BIT 39 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_DIG BIT(0) BIT 40 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_RA_MASK BIT(1) BIT 41 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_DYNAMIC_TXPWR BIT(2) BIT 42 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_BB_FA_CNT BIT(3) BIT 44 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_RSSI_MONITOR BIT(4) BIT 45 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_CCK_PD BIT(5) BIT 46 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_ANT_DIV BIT(6) BIT 47 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_PWR_SAVE BIT(7) BIT 48 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_PWR_TRA BIT(8) BIT 49 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_RATE_ADAPTIVE BIT(9) BIT 50 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_PATH_DIV BIT(10) BIT 51 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_BB_PSD BIT(11) BIT 54 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_MAC_EDCA_TURBO BIT(16) BIT 55 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_MAC_EARLY_MODE BIT(17) BIT 58 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_RF_TX_PWR_TRACK BIT(24) BIT 59 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_RF_RX_GAIN_TRACK BIT(25) BIT 60 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h #define DYNAMIC_RF_CALIBRATION BIT(26) BIT 25 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define XMIT_ALIVE BIT(0) BIT 26 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define RECV_ALIVE BIT(1) BIT 27 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define CMD_ALIVE BIT(2) BIT 28 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define EVT_ALIVE BIT(3) BIT 52 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define PS_DPS BIT(0) BIT 54 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define PS_RF_OFF BIT(1) BIT 55 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define PS_ALL_ON BIT(2) BIT 56 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define PS_ST_ACTIVE BIT(3) BIT 58 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define PS_ISR_ENABLE BIT(4) BIT 59 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define PS_IMR_ENABLE BIT(5) BIT 60 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define PS_ACK BIT(6) BIT 61 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define PS_TOGGLE BIT(7) BIT 103 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_ASPM BIT(0) /* PCI ASPM */ BIT 104 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /* PCI clock request */ BIT 105 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /* PCI D3 mode */ BIT 106 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) /* NIC halt, re-init hw param*/ BIT 107 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /* FW free, re-download the FW*/ BIT 108 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_FW_32K BIT(5) /* FW in 32k */ BIT 109 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) /* Always enable ASPM and Clock BIT 112 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define RT_RF_LPS_DISALBE_2R BIT(30) /* When LPS is on, disable 2R BIT 115 drivers/staging/rtl8188eu/include/rtw_pwrctrl.h #define RT_RF_LPS_LEVEL_ASPM BIT(31) /* LPS with ASPM */ BIT 20 drivers/staging/rtl8188eu/include/rtw_sreset.h #define USB_VEN_REQ_CMD_FAIL BIT(0) BIT 21 drivers/staging/rtl8188eu/include/rtw_sreset.h #define USB_READ_PORT_FAIL BIT(1) BIT 22 drivers/staging/rtl8188eu/include/rtw_sreset.h #define USB_WRITE_PORT_FAIL BIT(2) BIT 23 drivers/staging/rtl8188eu/include/rtw_sreset.h #define WIFI_MAC_TXDMA_ERROR BIT(3) BIT 24 drivers/staging/rtl8188eu/include/rtw_sreset.h #define WIFI_TX_HANG BIT(4) BIT 25 drivers/staging/rtl8188eu/include/rtw_sreset.h #define WIFI_RX_HANG BIT(5) BIT 26 drivers/staging/rtl8188eu/include/rtw_sreset.h #define WIFI_IF_NOT_EXIST BIT(6) BIT 55 drivers/staging/rtl8188eu/include/rtw_xmit.h pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ BIT 68 drivers/staging/rtl8188eu/include/rtw_xmit.h pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6); \ BIT 36 drivers/staging/rtl8188eu/include/wifi.h WIFI_CTRL_TYPE = (BIT(2)), BIT 37 drivers/staging/rtl8188eu/include/wifi.h WIFI_DATA_TYPE = (BIT(3)), BIT 38 drivers/staging/rtl8188eu/include/wifi.h WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), /* QoS Data */ BIT 44 drivers/staging/rtl8188eu/include/wifi.h WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE), BIT 45 drivers/staging/rtl8188eu/include/wifi.h WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE), BIT 46 drivers/staging/rtl8188eu/include/wifi.h WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE), BIT 47 drivers/staging/rtl8188eu/include/wifi.h WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE), BIT 48 drivers/staging/rtl8188eu/include/wifi.h WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE), BIT 49 drivers/staging/rtl8188eu/include/wifi.h WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE), BIT 50 drivers/staging/rtl8188eu/include/wifi.h WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE), BIT 51 drivers/staging/rtl8188eu/include/wifi.h WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE), BIT 52 drivers/staging/rtl8188eu/include/wifi.h WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE), BIT 53 drivers/staging/rtl8188eu/include/wifi.h WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE), BIT 54 drivers/staging/rtl8188eu/include/wifi.h WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE), BIT 57 drivers/staging/rtl8188eu/include/wifi.h WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), BIT 58 drivers/staging/rtl8188eu/include/wifi.h WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), BIT 59 drivers/staging/rtl8188eu/include/wifi.h WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), BIT 60 drivers/staging/rtl8188eu/include/wifi.h WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE), BIT 61 drivers/staging/rtl8188eu/include/wifi.h WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE), BIT 62 drivers/staging/rtl8188eu/include/wifi.h WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT 67 drivers/staging/rtl8188eu/include/wifi.h WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE), BIT 68 drivers/staging/rtl8188eu/include/wifi.h WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE), BIT 69 drivers/staging/rtl8188eu/include/wifi.h WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE), BIT 70 drivers/staging/rtl8188eu/include/wifi.h WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE), BIT 71 drivers/staging/rtl8188eu/include/wifi.h WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE), BIT 72 drivers/staging/rtl8188eu/include/wifi.h WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE), BIT 73 drivers/staging/rtl8188eu/include/wifi.h WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE), BIT 74 drivers/staging/rtl8188eu/include/wifi.h WIFI_QOS_DATA_NULL = (BIT(6) | WIFI_QOS_DATA_TYPE), BIT 136 drivers/staging/rtl8188eu/include/wifi.h #define _TO_DS_ BIT(8) BIT 137 drivers/staging/rtl8188eu/include/wifi.h #define _FROM_DS_ BIT(9) BIT 138 drivers/staging/rtl8188eu/include/wifi.h #define _MORE_FRAG_ BIT(10) BIT 139 drivers/staging/rtl8188eu/include/wifi.h #define _RETRY_ BIT(11) BIT 140 drivers/staging/rtl8188eu/include/wifi.h #define _PWRMGT_ BIT(12) BIT 141 drivers/staging/rtl8188eu/include/wifi.h #define _MORE_DATA_ BIT(13) BIT 142 drivers/staging/rtl8188eu/include/wifi.h #define _PRIVACY_ BIT(14) BIT 143 drivers/staging/rtl8188eu/include/wifi.h #define _ORDER_ BIT(15) BIT 206 drivers/staging/rtl8188eu/include/wifi.h (le16_to_cpu(*(__le16 *)(pbuf)) & (BIT(3) | BIT(2))) BIT 208 drivers/staging/rtl8188eu/include/wifi.h #define GetFrameSubType(pbuf) (le16_to_cpu(*(__le16 *)(pbuf)) & (BIT(7) |\ BIT 209 drivers/staging/rtl8188eu/include/wifi.h BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))) BIT 213 drivers/staging/rtl8188eu/include/wifi.h *(__le16 *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | \ BIT 214 drivers/staging/rtl8188eu/include/wifi.h BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ BIT 421 drivers/staging/rtl8188eu/include/wifi.h #define cap_ESS BIT(0) BIT 422 drivers/staging/rtl8188eu/include/wifi.h #define cap_IBSS BIT(1) BIT 423 drivers/staging/rtl8188eu/include/wifi.h #define cap_CFPollable BIT(2) BIT 424 drivers/staging/rtl8188eu/include/wifi.h #define cap_CFRequest BIT(3) BIT 425 drivers/staging/rtl8188eu/include/wifi.h #define cap_Privacy BIT(4) BIT 426 drivers/staging/rtl8188eu/include/wifi.h #define cap_ShortPremble BIT(5) BIT 427 drivers/staging/rtl8188eu/include/wifi.h #define cap_PBCC BIT(6) BIT 428 drivers/staging/rtl8188eu/include/wifi.h #define cap_ChAgility BIT(7) BIT 429 drivers/staging/rtl8188eu/include/wifi.h #define cap_SpecMgmt BIT(8) BIT 430 drivers/staging/rtl8188eu/include/wifi.h #define cap_QoSi BIT(9) BIT 431 drivers/staging/rtl8188eu/include/wifi.h #define cap_ShortSlot BIT(10) BIT 562 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8)BIT(0) | BIT(1)) BIT 563 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8)BIT(0)) BIT 564 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8)BIT(0) | BIT(1)) BIT 565 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8)BIT(2)) BIT 566 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_HT_PARAM_RIFS_MODE ((u8)BIT(3)) BIT 567 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8)BIT(4)) BIT 568 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8)BIT(5)) BIT 573 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8)BIT(2)) BIT 574 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8)BIT(3)) BIT 575 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8)BIT(4)) BIT 577 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16)BIT(6)) BIT 578 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16)BIT(7)) BIT 579 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_STBC_PARAM_SECONDARY_BC ((u16)BIT(8)) BIT 580 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16)BIT(9)) BIT 581 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16)BIT(10)) BIT 582 drivers/staging/rtl8188eu/include/wifi.h #define HT_INFO_STBC_PARAM_PCO_PHASE ((u16)BIT(11)) BIT 410 drivers/staging/rtl8192u/ieee80211/ieee80211.h #define FC_QOS_BIT BIT(7) BIT 1564 drivers/staging/rtl8192u/ieee80211/ieee80211.h #define RF_CHANGE_BY_SW BIT(31) BIT 1565 drivers/staging/rtl8192u/ieee80211/ieee80211.h #define RF_CHANGE_BY_HW BIT(30) BIT 1566 drivers/staging/rtl8192u/ieee80211/ieee80211.h #define RF_CHANGE_BY_PS BIT(29) BIT 1567 drivers/staging/rtl8192u/ieee80211/ieee80211.h #define RF_CHANGE_BY_IPS BIT(28) BIT 188 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c *pos++ = (key->key_idx << 6) | BIT(5) /* Ext IV included */; BIT 244 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c if (!(keyidx & BIT(5))) { BIT 330 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c *pos++ = (tkey->key_idx << 6) | BIT(5) /* Ext IV included */; BIT 389 drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c if (!(keyidx & BIT(5))) { BIT 2319 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0xf)) ? '1' : '0', BIT 2320 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0xe)) ? '1' : '0', BIT 2321 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0xd)) ? '1' : '0', BIT 2322 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0xc)) ? '1' : '0', BIT 2323 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0xb)) ? '1' : '0', BIT 2324 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0xa)) ? '1' : '0', BIT 2325 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0x9)) ? '1' : '0', BIT 2326 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0x8)) ? '1' : '0', BIT 2327 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0x7)) ? '1' : '0', BIT 2328 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0x6)) ? '1' : '0', BIT 2329 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0x5)) ? '1' : '0', BIT 2330 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0x4)) ? '1' : '0', BIT 2331 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0x3)) ? '1' : '0', BIT 2332 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0x2)) ? '1' : '0', BIT 2333 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0x1)) ? '1' : '0', BIT 2334 drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c (capability & BIT(0x0)) ? '1' : '0'); BIT 74 drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c if (network->mode & BIT(i)) { BIT 380 drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c sec.flags |= BIT(key); BIT 402 drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c sec.flags |= BIT(key); BIT 623 drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c sec.flags |= BIT(idx); BIT 123 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[6] = addr & BIT(1); BIT 124 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[5] = addr & BIT(2); BIT 125 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[4] = addr & BIT(3); BIT 126 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[3] = addr & BIT(4); BIT 127 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[2] = addr & BIT(5); BIT 128 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[1] = addr & BIT(6); BIT 129 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[0] = addr & BIT(7); BIT 133 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[4] = addr & BIT(1); BIT 134 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[3] = addr & BIT(2); BIT 135 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[2] = addr & BIT(3); BIT 136 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[1] = addr & BIT(4); BIT 137 drivers/staging/rtl8192u/r8180_93cx6.c addr_str[0] = addr & BIT(5); BIT 59 drivers/staging/rtl8192u/r8192U.h #define COMP_TRACE BIT(0) /* Function call tracing. */ BIT 60 drivers/staging/rtl8192u/r8192U.h #define COMP_DBG BIT(1) BIT 61 drivers/staging/rtl8192u/r8192U.h #define COMP_INIT BIT(2) /* Driver initialization/halt/reset. */ BIT 63 drivers/staging/rtl8192u/r8192U.h #define COMP_RECV BIT(3) /* Receive data path. */ BIT 64 drivers/staging/rtl8192u/r8192U.h #define COMP_SEND BIT(4) /* Send data path. */ BIT 65 drivers/staging/rtl8192u/r8192U.h #define COMP_IO BIT(5) BIT 67 drivers/staging/rtl8192u/r8192U.h #define COMP_POWER BIT(6) BIT 69 drivers/staging/rtl8192u/r8192U.h #define COMP_EPROM BIT(7) BIT 70 drivers/staging/rtl8192u/r8192U.h #define COMP_SWBW BIT(8) /* Bandwidth switch. */ BIT 71 drivers/staging/rtl8192u/r8192U.h #define COMP_POWER_TRACKING BIT(9) /* 8190 TX Power Tracking */ BIT 72 drivers/staging/rtl8192u/r8192U.h #define COMP_TURBO BIT(10) /* Turbo Mode */ BIT 73 drivers/staging/rtl8192u/r8192U.h #define COMP_QOS BIT(11) BIT 74 drivers/staging/rtl8192u/r8192U.h #define COMP_RATE BIT(12) /* Rate Adaptive mechanism */ BIT 75 drivers/staging/rtl8192u/r8192U.h #define COMP_RM BIT(13) /* Radio Measurement */ BIT 76 drivers/staging/rtl8192u/r8192U.h #define COMP_DIG BIT(14) BIT 77 drivers/staging/rtl8192u/r8192U.h #define COMP_PHY BIT(15) BIT 78 drivers/staging/rtl8192u/r8192U.h #define COMP_CH BIT(16) /* Channel setting debug */ BIT 79 drivers/staging/rtl8192u/r8192U.h #define COMP_TXAGC BIT(17) /* Tx power */ BIT 80 drivers/staging/rtl8192u/r8192U.h #define COMP_HIPWR BIT(18) /* High Power Mechanism */ BIT 81 drivers/staging/rtl8192u/r8192U.h #define COMP_HALDM BIT(19) /* HW Dynamic Mechanism */ BIT 82 drivers/staging/rtl8192u/r8192U.h #define COMP_SEC BIT(20) /* Event handling */ BIT 83 drivers/staging/rtl8192u/r8192U.h #define COMP_LED BIT(21) BIT 84 drivers/staging/rtl8192u/r8192U.h #define COMP_RF BIT(22) BIT 85 drivers/staging/rtl8192u/r8192U.h #define COMP_RXDESC BIT(23) /* Rx desc information for SD3 debug */ BIT 89 drivers/staging/rtl8192u/r8192U.h #define COMP_FIRMWARE BIT(24) /* Firmware downloading */ BIT 90 drivers/staging/rtl8192u/r8192U.h #define COMP_HT BIT(25) /* 802.11n HT related information */ BIT 91 drivers/staging/rtl8192u/r8192U.h #define COMP_AMSDU BIT(26) /* A-MSDU Debugging */ BIT 92 drivers/staging/rtl8192u/r8192U.h #define COMP_SCAN BIT(27) BIT 93 drivers/staging/rtl8192u/r8192U.h #define COMP_DOWN BIT(29) /* rm driver module */ BIT 94 drivers/staging/rtl8192u/r8192U.h #define COMP_RESET BIT(30) /* Silent reset */ BIT 95 drivers/staging/rtl8192u/r8192U.h #define COMP_ERR BIT(31) /* Error out, always on */ BIT 222 drivers/staging/rtl8192u/r8192U_core.c ulcommand |= BIT(31) | BIT(30); BIT 4976 drivers/staging/rtl8192u/r8192U_core.c usConfig |= BIT(15) | (KeyType << 2); BIT 4978 drivers/staging/rtl8192u/r8192U_core.c usConfig |= BIT(15) | (KeyType << 2) | KeyIndex; BIT 4983 drivers/staging/rtl8192u/r8192U_core.c TargetCommand |= BIT(31) | BIT(16); BIT 313 drivers/staging/rtl8192u/r8192U_dm.c (pra->upper_rssi_threshold_ratr & (~BIT(31))) | BIT 314 drivers/staging/rtl8192u/r8192U_dm.c ((bshort_gi_enabled) ? BIT(31) : 0); BIT 317 drivers/staging/rtl8192u/r8192U_dm.c (pra->middle_rssi_threshold_ratr & (~BIT(31))) | BIT 318 drivers/staging/rtl8192u/r8192U_dm.c ((bshort_gi_enabled) ? BIT(31) : 0); BIT 322 drivers/staging/rtl8192u/r8192U_dm.c (pra->low_rssi_threshold_ratr_40M & (~BIT(31))) | BIT 323 drivers/staging/rtl8192u/r8192U_dm.c ((bshort_gi_enabled) ? BIT(31) : 0); BIT 326 drivers/staging/rtl8192u/r8192U_dm.c (pra->low_rssi_threshold_ratr_20M & (~BIT(31))) | BIT 327 drivers/staging/rtl8192u/r8192U_dm.c ((bshort_gi_enabled) ? BIT(31) : 0); BIT 331 drivers/staging/rtl8192u/r8192U_dm.c (pra->ping_rssi_ratr & (~BIT(31))) | BIT 332 drivers/staging/rtl8192u/r8192U_dm.c ((bshort_gi_enabled) ? BIT(31) : 0); BIT 2292 drivers/staging/rtl8192u/r8192U_dm.c if (tmp1byte & BIT(6) || tmp1byte & BIT(0)) { BIT 11 drivers/staging/rtl8192u/r819xU_cmdpkt.h #define ISR_TX_BCN_OK BIT(27) /* Transmit Beacon OK */ BIT 12 drivers/staging/rtl8192u/r819xU_cmdpkt.h #define ISR_TX_BCN_ERR BIT(26) /* Transmit Beacon Error */ BIT 13 drivers/staging/rtl8192u/r819xU_cmdpkt.h #define ISR_BCN_TIMER_INTR BIT(13) /* Beacon Timer Interrupt */ BIT 1095 drivers/staging/rtl8192u/r819xU_phy.c rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), BIT 1120 drivers/staging/rtl8192u/r819xU_phy.c rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), BIT 62 drivers/staging/rtl8712/drv_types.h #define SPEC_DEV_ID_DISABLE_HT BIT(1) BIT 187 drivers/staging/rtl8712/hal_init.c txdesc->txdw0 |= cpu_to_le32(BIT(28)); BIT 216 drivers/staging/rtl8712/hal_init.c txdesc->txdw0 |= cpu_to_le32(BIT(28)); BIT 239 drivers/staging/rtl8712/hal_init.c r8712_write8(adapter, SYS_CLKR, tmp8 | BIT(2)); BIT 241 drivers/staging/rtl8712/hal_init.c if (tmp8_a != (tmp8 | BIT(2))) BIT 245 drivers/staging/rtl8712/hal_init.c r8712_write8(adapter, SYS_FUNC_EN + 1, tmp8 | BIT(2)); BIT 247 drivers/staging/rtl8712/hal_init.c if (tmp8_a != (tmp8 | BIT(2))) BIT 272 drivers/staging/rtl8712/hal_init.c txdesc->txdw0 |= cpu_to_le32(BIT(28)); BIT 289 drivers/staging/rtl8712/hal_init.c if (tmp8 & BIT(4)) /* When boot from EEPROM, BIT 325 drivers/staging/rtl8712/hal_init.c r8712_write32(padapter, RCR, (val32 | BIT(26))); /* Enable RX TCP BIT 331 drivers/staging/rtl8712/hal_init.c r8712_write32(padapter, RCR, (val32 | BIT(25))); /* Append PHY status */ BIT 336 drivers/staging/rtl8712/hal_init.c BIT(0)); /* page = 128bytes */ BIT 338 drivers/staging/rtl8712/hal_init.c BIT(7)); /* enable usb rx aggregation */ BIT 345 drivers/staging/rtl8712/hal_init.c | BIT(7)); BIT 54 drivers/staging/rtl8712/ieee80211.h #define WPA_CIPHER_NONE BIT(0) BIT 55 drivers/staging/rtl8712/ieee80211.h #define WPA_CIPHER_WEP40 BIT(1) BIT 56 drivers/staging/rtl8712/ieee80211.h #define WPA_CIPHER_WEP104 BIT(2) BIT 57 drivers/staging/rtl8712/ieee80211.h #define WPA_CIPHER_TKIP BIT(3) BIT 58 drivers/staging/rtl8712/ieee80211.h #define WPA_CIPHER_CCMP BIT(4) BIT 289 drivers/staging/rtl8712/ieee80211.h #define WLAN_CAPABILITY_BSS BIT(0) BIT 290 drivers/staging/rtl8712/ieee80211.h #define WLAN_CAPABILITY_IBSS BIT(1) BIT 291 drivers/staging/rtl8712/ieee80211.h #define WLAN_CAPABILITY_CF_POLLABLE BIT(2) BIT 292 drivers/staging/rtl8712/ieee80211.h #define WLAN_CAPABILITY_CF_POLL_REQUEST BIT(3) BIT 293 drivers/staging/rtl8712/ieee80211.h #define WLAN_CAPABILITY_PRIVACY BIT(4) BIT 294 drivers/staging/rtl8712/ieee80211.h #define WLAN_CAPABILITY_SHORT_PREAMBLE BIT(5) BIT 295 drivers/staging/rtl8712/ieee80211.h #define WLAN_CAPABILITY_PBCC BIT(6) BIT 296 drivers/staging/rtl8712/ieee80211.h #define WLAN_CAPABILITY_CHANNEL_AGILITY BIT(7) BIT 297 drivers/staging/rtl8712/ieee80211.h #define WLAN_CAPABILITY_SHORT_SLOT BIT(10) BIT 315 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_STATMASK_SIGNAL BIT(0) BIT 316 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_STATMASK_RSSI BIT(1) BIT 317 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_STATMASK_NOISE BIT(2) BIT 318 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_STATMASK_RATE BIT(3) BIT 321 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_CCK_MODULATION BIT(0) BIT 322 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_OFDM_MODULATION BIT(1) BIT 324 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_24GHZ_BAND BIT(0) BIT 325 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_52GHZ_BAND BIT(1) BIT 345 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_CCK_RATE_1MB_MASK BIT(0) BIT 346 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_CCK_RATE_2MB_MASK BIT(1) BIT 347 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_CCK_RATE_5MB_MASK BIT(2) BIT 348 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_CCK_RATE_11MB_MASK BIT(3) BIT 349 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_OFDM_RATE_6MB_MASK BIT(4) BIT 350 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_OFDM_RATE_9MB_MASK BIT(5) BIT 351 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_OFDM_RATE_12MB_MASK BIT(6) BIT 352 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_OFDM_RATE_18MB_MASK BIT(7) BIT 353 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_OFDM_RATE_24MB_MASK BIT(8) BIT 354 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_OFDM_RATE_36MB_MASK BIT(9) BIT 355 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_OFDM_RATE_48MB_MASK BIT(10) BIT 356 drivers/staging/rtl8712/ieee80211.h #define IEEE80211_OFDM_RATE_54MB_MASK BIT(11) BIT 459 drivers/staging/rtl8712/ieee80211.h #define SEC_KEY_1 BIT(0) BIT 460 drivers/staging/rtl8712/ieee80211.h #define SEC_KEY_2 BIT(1) BIT 461 drivers/staging/rtl8712/ieee80211.h #define SEC_KEY_3 BIT(2) BIT 462 drivers/staging/rtl8712/ieee80211.h #define SEC_KEY_4 BIT(3) BIT 463 drivers/staging/rtl8712/ieee80211.h #define SEC_ACTIVE_KEY BIT(4) BIT 464 drivers/staging/rtl8712/ieee80211.h #define SEC_AUTH_MODE BIT(5) BIT 465 drivers/staging/rtl8712/ieee80211.h #define SEC_UNICAST_GROUP BIT(6) BIT 466 drivers/staging/rtl8712/ieee80211.h #define SEC_LEVEL BIT(7) BIT 467 drivers/staging/rtl8712/ieee80211.h #define SEC_ENABLED BIT(8) BIT 623 drivers/staging/rtl8712/ieee80211.h #define NETWORK_EMPTY_ESSID BIT(0) BIT 624 drivers/staging/rtl8712/ieee80211.h #define NETWORK_HAS_OFDM BIT(1) BIT 625 drivers/staging/rtl8712/ieee80211.h #define NETWORK_HAS_CCK BIT(2) BIT 677 drivers/staging/rtl8712/ieee80211.h #define CFG_IEEE80211_RESERVE_FCS BIT(0) BIT 678 drivers/staging/rtl8712/ieee80211.h #define CFG_IEEE80211_COMPUTE_FCS BIT(1) BIT 682 drivers/staging/rtl8712/ieee80211.h #define IEEE_A BIT(0) BIT 683 drivers/staging/rtl8712/ieee80211.h #define IEEE_B BIT(1) BIT 684 drivers/staging/rtl8712/ieee80211.h #define IEEE_G BIT(2) BIT 16 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _APSDOFF_STATUS BIT(15) BIT 17 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _APSDOFF BIT(14) BIT 18 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _BBRSTn BIT(13) /*Enable OFDM/CCK*/ BIT 19 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _BB_GLB_RSTn BIT(12) /*Enable BB*/ BIT 20 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _SCHEDULE_EN BIT(10) /*Enable MAC scheduler*/ BIT 21 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _MACRXEN BIT(9) BIT 22 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _MACTXEN BIT(8) BIT 23 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _DDMA_EN BIT(7) /*FW off load function enable*/ BIT 24 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _FW2HW_EN BIT(6) /*MAC every module reset */ BIT 25 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _RXDMA_EN BIT(5) BIT 26 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _TXDMA_EN BIT(4) BIT 27 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _HCI_RXDMA_EN BIT(3) BIT 28 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _HCI_TXDMA_EN BIT(2) BIT 31 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _STOPHCCA BIT(6) BIT 32 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _STOPHIGH BIT(5) BIT 33 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _STOPMGT BIT(4) BIT 34 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _STOPVO BIT(3) BIT 35 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _STOPVI BIT(2) BIT 36 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _STOPBE BIT(1) BIT 37 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _STOPBK BIT(0) BIT 40 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _DISCW BIT(20) BIT 41 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _ICV BIT(19) BIT 42 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _CFEND_FMT BIT(17) BIT 43 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _CRC BIT(16) BIT 44 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _FWRDY BIT(7) BIT 45 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _BASECHG BIT(6) BIT 46 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _IMEM_RDY BIT(5) BIT 47 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _DMEM_CODE_DONE BIT(4) BIT 48 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _EMEM_CHK_RPT BIT(3) BIT 49 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _EMEM_CODE_DONE BIT(2) BIT 50 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _IMEM_CHK_RPT BIT(1) BIT 51 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _IMEM_CODE_DONE BIT(0) BIT 56 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _ENMBID BIT(27) BIT 57 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _APP_PHYST_RXFF BIT(25) BIT 58 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _APP_PHYST_STAFF BIT(24) BIT 59 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _CBSSID BIT(23) BIT 60 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _APWRMGT BIT(22) BIT 61 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _ADD3 BIT(21) BIT 62 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _AMF BIT(20) BIT 63 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _ACF BIT(19) BIT 64 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _ADF BIT(18) BIT 65 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _APP_MIC BIT(17) BIT 66 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _APP_ICV BIT(16) BIT 69 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _AICV BIT(12) BIT 72 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _ACRC32 BIT(5) BIT 73 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _AB BIT(3) BIT 74 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _AM BIT(2) BIT 75 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _APM BIT(1) BIT 76 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _AAP BIT(0) BIT 85 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _ENBT BIT(0) BIT 88 drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h #define _ENMBID_MODE BIT(15) BIT 11 drivers/staging/rtl8712/rtl8712_debugctrl_bitdef.h #define _BIST_RST BIT(0) BIT 19 drivers/staging/rtl8712/rtl8712_debugctrl_bitdef.h #define _WDGCLR BIT(8) BIT 35 drivers/staging/rtl8712/rtl8712_debugctrl_bitdef.h #define _TURN1 BIT(0) BIT 35 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _AVG_TIME_UP BIT(3) BIT 39 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _VOQ_ACM_STATUS BIT(6) BIT 40 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _VIQ_ACM_STATUS BIT(5) BIT 41 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _BEQ_ACM_STATUS BIT(4) BIT 42 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _VOQ_ACM_EN BIT(3) BIT 43 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _VIQ_ACM_EN BIT(2) BIT 44 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _BEQ_ACM_EN BIT(1) BIT 45 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _ACMHWEN BIT(0) BIT 48 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _VO_ACM_RUT BIT(18) BIT 52 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _VI_ACM_RUT BIT(18) BIT 56 drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h #define _BE_ACM_RUT BIT(18) BIT 189 drivers/staging/rtl8712/rtl8712_efuse.c if (!(word_en & BIT(word_idx))) BIT 201 drivers/staging/rtl8712/rtl8712_efuse.c if (!(word_en & BIT(word_idx))) { BIT 301 drivers/staging/rtl8712/rtl8712_efuse.c if (BIT(i) & word_en) { BIT 302 drivers/staging/rtl8712/rtl8712_efuse.c if (BIT(i) & pkt.word_en) { BIT 327 drivers/staging/rtl8712/rtl8712_efuse.c if (BIT(i) & pkt.word_en) { BIT 517 drivers/staging/rtl8712/rtl8712_efuse.c word_en &= ~BIT(i >> 1); BIT 528 drivers/staging/rtl8712/rtl8712_efuse.c word_en &= ~BIT(i >> 1); BIT 538 drivers/staging/rtl8712/rtl8712_efuse.c word_en &= ~BIT(i >> 1); BIT 17 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _TXSTATUS_OVF BIT(15) BIT 20 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _STATUSFF1_OVF BIT(7) BIT 21 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _STATUSFF1_EMPTY BIT(6) BIT 22 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _STATUSFF0_OVF BIT(5) BIT 23 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _STATUSFF0_EMPTY BIT(4) BIT 24 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _RXFF1_OVF BIT(3) BIT 25 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _RXFF1_EMPTY BIT(2) BIT 26 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _RXFF0_OVF BIT(1) BIT 27 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _RXFF0_EMPTY BIT(0) BIT 45 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _C2HFF_POLL BIT(4) BIT 46 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _RXPKT_POLL BIT(0) BIT 61 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _RXFF0_DEC_POLL BIT(15) BIT 68 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _RXFF1_DEC_POLL BIT(15) BIT 75 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT13EN BIT(13) BIT 76 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT12EN BIT(12) BIT 77 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT11EN BIT(11) BIT 78 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT10EN BIT(10) BIT 79 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT9EN BIT(9) BIT 80 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT8EN BIT(8) BIT 81 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT5EN BIT(5) BIT 82 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT4EN BIT(4) BIT 83 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT3EN BIT(3) BIT 84 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT2EN BIT(2) BIT 85 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT1EN BIT(1) BIT 86 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MGTFLT0EN BIT(0) BIT 89 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _CTRLFLT15EN BIT(15) BIT 90 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _CTRLFLT14EN BIT(14) BIT 91 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _CTRLFLT13EN BIT(13) BIT 92 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _CTRLFLT12EN BIT(12) BIT 93 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _CTRLFLT11EN BIT(11) BIT 94 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _CTRLFLT10EN BIT(10) BIT 95 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _CTRLFLT9EN BIT(9) BIT 96 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _CTRLFLT8EN BIT(8) BIT 97 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _CTRLFLT7EN BIT(7) BIT 98 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _CTRLFLT6EN BIT(6) BIT 101 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT15EN BIT(15) BIT 102 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT14EN BIT(14) BIT 103 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT13EN BIT(13) BIT 104 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT12EN BIT(12) BIT 105 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT11EN BIT(11) BIT 106 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT10EN BIT(10) BIT 107 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT9EN BIT(9) BIT 108 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT8EN BIT(8) BIT 109 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT7EN BIT(7) BIT 110 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT6EN BIT(6) BIT 111 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT5EN BIT(5) BIT 112 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT4EN BIT(4) BIT 113 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT3EN BIT(3) BIT 114 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT2EN BIT(2) BIT 115 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT1EN BIT(1) BIT 116 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _DATAFLT0EN BIT(0) BIT 119 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MESHAFLT1EN BIT(1) BIT 120 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _MESHAFLT0EN BIT(0) BIT 123 drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h #define _TXPKTNUM_DEC BIT(8) BIT 32 drivers/staging/rtl8712/rtl8712_gp_bitdef.h #define _LED1SV BIT(7) BIT 35 drivers/staging/rtl8712/rtl8712_gp_bitdef.h #define _LED0SV BIT(3) BIT 42 drivers/staging/rtl8712/rtl8712_gp_bitdef.h #define _HST_RDRDY BIT(_HST_RDRDY_SHT) BIT 45 drivers/staging/rtl8712/rtl8712_gp_bitdef.h #define _CPU_WTBUSY BIT(_CPU_WTBUSY_SHT) BIT 53 drivers/staging/rtl8712/rtl8712_gp_bitdef.h #define GPIOMUX_EN BIT(3) /* When this bit is set to "1", BIT 61 drivers/staging/rtl8712/rtl8712_gp_bitdef.h #define GPIOSEL_GPIO_MASK (~(BIT(0) | BIT(1))) BIT 63 drivers/staging/rtl8712/rtl8712_gp_bitdef.h #define HAL_8192S_HW_GPIO_OFF_BIT BIT(3) BIT 65 drivers/staging/rtl8712/rtl8712_gp_bitdef.h #define HAL_8192S_HW_GPIO_WPS_BIT BIT(4) BIT 12 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _CPUERR BIT(29) BIT 13 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _ATIMEND BIT(28) BIT 14 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _TXBCNOK BIT(27) BIT 15 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _TXBCNERR BIT(26) BIT 16 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BCNDMAINT4 BIT(25) BIT 17 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BCNDMAINT3 BIT(24) BIT 18 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BCNDMAINT2 BIT(23) BIT 19 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BCNDMAINT1 BIT(22) BIT 20 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BCNDOK4 BIT(21) BIT 21 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BCNDOK3 BIT(20) BIT 22 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BCNDOK2 BIT(19) BIT 23 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BCNDOK1 BIT(18) BIT 24 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _TIMEOUT2 BIT(17) BIT 25 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _TIMEOUT1 BIT(16) BIT 26 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _TXFOVW BIT(15) BIT 27 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _PSTIMEOUT BIT(14) BIT 28 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BCNDMAINT0 BIT(13) BIT 29 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _FOVW BIT(12) BIT 30 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _RDU BIT(11) BIT 31 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _RXCMDOK BIT(10) BIT 32 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BCNDOK0 BIT(9) BIT 33 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _HIGHDOK BIT(8) BIT 34 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _COMDOK BIT(7) BIT 35 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _MGTDOK BIT(6) BIT 36 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _HCCADOK BIT(5) BIT 37 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BKDOK BIT(4) BIT 38 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _BEDOK BIT(3) BIT 39 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _VIDOK BIT(2) BIT 40 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _VODOK BIT(1) BIT 41 drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h #define _RXOK BIT(0) BIT 148 drivers/staging/rtl8712/rtl8712_led.c r8712_write8(padapter, LEDCFG, (LedCfg | BIT(3))); BIT 152 drivers/staging/rtl8712/rtl8712_led.c r8712_write8(padapter, LEDCFG, (LedCfg | BIT(7))); BIT 21 drivers/staging/rtl8712/rtl8712_macsetting_bitdef.h #define _POOLING BIT(31) BIT 22 drivers/staging/rtl8712/rtl8712_macsetting_bitdef.h #define _WRITE_EN BIT(16) BIT 11 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _UWF BIT(3) BIT 12 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _MAGIC BIT(2) BIT 13 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _WOW_EN BIT(1) BIT 14 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _PMEN BIT(0) BIT 20 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _PSSWITCH_ACT BIT(7) BIT 25 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _LPNAV_EN BIT(31) BIT 33 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _TOGGLING BIT(7) BIT 34 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _WWLAN BIT(3) BIT 35 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _RPS_ST BIT(2) BIT 36 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _WLAN_TRX BIT(1) BIT 37 drivers/staging/rtl8712/rtl8712_powersave_bitdef.h #define _SYS_CLK BIT(0) BIT 14 drivers/staging/rtl8712/rtl8712_ratectrl_bitdef.h #define _RRSR_SHORT BIT(23) BIT 152 drivers/staging/rtl8712/rtl8712_recv.c pattrib->bdecrypted = ((le32_to_cpu(prxstat->rxdw0) & BIT(27)) >> 27) BIT 154 drivers/staging/rtl8712/rtl8712_recv.c pattrib->crc_err = (le32_to_cpu(prxstat->rxdw0) & BIT(14)) >> 14; BIT 158 drivers/staging/rtl8712/rtl8712_recv.c if (le32_to_cpu(prxstat->rxdw3) & BIT(13)) { BIT 160 drivers/staging/rtl8712/rtl8712_recv.c if (le32_to_cpu(prxstat->rxdw3) & BIT(11)) BIT 164 drivers/staging/rtl8712/rtl8712_recv.c if (le32_to_cpu(prxstat->rxdw3) & BIT(12)) BIT 440 drivers/staging/rtl8712/rtl8712_recv.c } while (le32_to_cpu(voffset) & BIT(31)); BIT 11 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _SECCAM_POLLING BIT(31) BIT 12 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _SECCAM_CLR BIT(30) BIT 13 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _SECCAM_WE BIT(16) BIT 18 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _SECCAM_INFO BIT(31) BIT 19 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _SEC_KEYFOUND BIT(30) BIT 26 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _NOSKMC BIT(5) BIT 27 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _SKBYA2 BIT(4) BIT 28 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _RXDEC BIT(3) BIT 29 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _TXENC BIT(2) BIT 30 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _RXUSEDK BIT(1) BIT 31 drivers/staging/rtl8712/rtl8712_security_bitdef.h #define _TXUSEDK BIT(0) BIT 24 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define iso_LDR2RP BIT(iso_LDR2RP_SHT) /* 1:isolation, 0:attach*/ BIT 28 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_DIO_SDIO BIT(FEN_DIO_SDIO_SHT) BIT 30 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_SDIO BIT(FEN_SDIO_SHT) BIT 32 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_USBA BIT(FEN_USBA_SHT) BIT 34 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_UPLL BIT(FEN_UPLL_SHT) BIT 36 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_USBD BIT(FEN_USBD_SHT) BIT 38 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_DIO_PCIE BIT(FEN_DIO_PCIE_SHT) BIT 40 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_PCIEA BIT(FEN_PCIEA_SHT) BIT 42 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_PPLL BIT(FEN_PPLL_SHT) BIT 44 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_PCIED BIT(FEN_PCIED_SHT) BIT 46 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_CPUEN BIT(FEN_CPUEN_SHT) BIT 48 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_DCORE BIT(FEN_DCORE_SHT) BIT 50 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FEN_ELDR BIT(FEN_ELDR_SHT) BIT 52 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define PWC_DV2LDR BIT(PWC_DV2LDR_SHT) /* Loader Power Enable*/ BIT 56 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define SYS_CLKSEL BIT(SYS_CLKSEL_SHT) /* System Clock 80MHz*/ BIT 58 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define PS_CLKSEL BIT(PS_CLKSEL_SHT) /*System power save BIT 62 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define CPU_CLKSEL BIT(CPU_CLKSEL_SHT) /* System Clock select, BIT 67 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define INT32K_EN BIT(INT32K_EN_SHT) BIT 69 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define MACSLP BIT(MACSLP_SHT) BIT 71 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define MAC_CLK_EN BIT(MAC_CLK_EN_SHT) /* MAC Clock Enable.*/ BIT 73 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define SYS_CLK_EN BIT(SYS_CLK_EN_SHT) BIT 75 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define RING_CLK_EN BIT(RING_CLK_EN_SHT) BIT 77 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define SWHW_SEL BIT(SWHW_SEL_SHT) /* Load done, BIT 81 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define FWHW_SEL BIT(FWHW_SEL_SHT) /* Sleep exit, BIT 90 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define _EEM0 BIT(6) BIT 91 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define _EEM1 BIT(7) BIT 92 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define _EEPROM_EN BIT(5) BIT 93 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define _9356SEL BIT(4) BIT 94 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define _EECS BIT(3) BIT 95 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define _EESK BIT(2) BIT 96 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define _EEDI BIT(1) BIT 97 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define _EEDO BIT(0) BIT 101 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define AFE_MISC_USB_MBEN BIT(AFE_MISC_USB_MBEN_SHT) BIT 103 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define AFE_MISC_USB_BGEN BIT(AFE_MISC_USB_BGEN_SHT) BIT 106 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define AFE_MISC_LD12_VDAJ BIT(AFE_MISC_LD12_VDAJ_SHT) BIT 108 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define AFE_MISC_I32_EN BIT(AFE_MISC_I32_EN_SHT) BIT 110 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define AFE_MISC_E32_EN BIT(AFE_MISC_E32_EN_SHT) BIT 112 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define AFE_MISC_MBEN BIT(AFE_MISC_MBEN_SHT)/* Enable AFE Macro BIT 116 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define AFE_MISC_BGEN BIT(AFE_MISC_BGEN_SHT)/* Enable AFE Macro BIT 124 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define SPS1_SWEN BIT(1) /* Enable vsps18 SW Macro Block.*/ BIT 125 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define SPS1_LDEN BIT(0) /* Enable VSPS12 LDO Macro block.*/ BIT 131 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define LDA15_EN BIT(0) /* Enable LDOA15 Macro Block*/ BIT 137 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define LDV12_EN BIT(0) /* Enable LDOVD12 Macro Block*/ BIT 138 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define LDV12_SDBY BIT(1) /* LDOVD12 standby mode*/ BIT 141 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define _CLK_GATE_EN BIT(0) BIT 145 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define EF_FLAG BIT(31) /* Access Flag, Write:1; BIT 152 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define EF_PDN_EN BIT(19) /* EFuse Power down enable*/ BIT 153 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define ALD_EN BIT(18) /* Autoload Enable*/ BIT 158 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define LDOE25_EN BIT(31) /* Enable LDOE25 Macro Block*/ BIT 161 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define EFUSE_CLK_EN BIT(1) /* E-Fuse Clock Enable*/ BIT 162 drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h #define EFUSE_CLK_SEL BIT(0) /* E-Fuse Clock Select, BIT 36 drivers/staging/rtl8712/rtl8712_timectrl_bitdef.h #define _ENSWBCN BIT(15) BIT 18 drivers/staging/rtl8712/rtl8712_wmac_bitdef.h #define _NAV_UPPER_EN BIT(18) BIT 19 drivers/staging/rtl8712/rtl8712_wmac_bitdef.h #define _NAV_MTO_EN BIT(17) BIT 20 drivers/staging/rtl8712/rtl8712_wmac_bitdef.h #define _NAV_UPPER BIT(16) BIT 27 drivers/staging/rtl8712/rtl8712_wmac_bitdef.h #define _20MHZBW BIT(2) BIT 30 drivers/staging/rtl8712/rtl8712_wmac_bitdef.h #define _BACAM_POLL BIT(31) BIT 31 drivers/staging/rtl8712/rtl8712_wmac_bitdef.h #define _BACAM_RST BIT(17) BIT 32 drivers/staging/rtl8712/rtl8712_wmac_bitdef.h #define _BACAM_RW BIT(16) BIT 478 drivers/staging/rtl8712/rtl8712_xmit.c ptxdesc->txdw1 |= cpu_to_le32(BIT(16));/*Non-QoS*/ BIT 557 drivers/staging/rtl8712/rtl8712_xmit.c ptxdesc->txdw1 |= cpu_to_le32(BIT(16));/* Non-QoS */ BIT 52 drivers/staging/rtl8712/rtl8712_xmit.h #define OWN BIT(31) BIT 53 drivers/staging/rtl8712/rtl8712_xmit.h #define FSG BIT(27) BIT 54 drivers/staging/rtl8712/rtl8712_xmit.h #define LSG BIT(26) BIT 61 drivers/staging/rtl8712/rtl8712_xmit.h #define HWPC BIT(31) BIT 64 drivers/staging/rtl8712/rtl8712_xmit.h #define BMC BIT(7) BIT 65 drivers/staging/rtl8712/rtl8712_xmit.h #define BK BIT(30) BIT 66 drivers/staging/rtl8712/rtl8712_xmit.h #define AGG_EN BIT(29) BIT 73 drivers/staging/rtl8712/rtl8712_xmit.h #define TXBW BIT(18) BIT 76 drivers/staging/rtl8712/rtl8712_xmit.h #define DISFB BIT(15) BIT 32 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_xmit_c_ BIT(0) BIT 33 drivers/staging/rtl8712/rtl871x_debug.h #define _module_xmit_osdep_c_ BIT(1) BIT 34 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_recv_c_ BIT(2) BIT 35 drivers/staging/rtl8712/rtl871x_debug.h #define _module_recv_osdep_c_ BIT(3) BIT 36 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_mlme_c_ BIT(4) BIT 37 drivers/staging/rtl8712/rtl871x_debug.h #define _module_mlme_osdep_c_ BIT(5) BIT 38 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_sta_mgt_c_ BIT(6) BIT 39 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_cmd_c_ BIT(7) BIT 40 drivers/staging/rtl8712/rtl871x_debug.h #define _module_cmd_osdep_c_ BIT(8) BIT 41 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_io_c_ BIT(9) BIT 42 drivers/staging/rtl8712/rtl871x_debug.h #define _module_io_osdep_c_ BIT(10) BIT 43 drivers/staging/rtl8712/rtl871x_debug.h #define _module_os_intfs_c_ BIT(11) BIT 44 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_security_c_ BIT(12) BIT 45 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_eeprom_c_ BIT(13) BIT 46 drivers/staging/rtl8712/rtl871x_debug.h #define _module_hal_init_c_ BIT(14) BIT 47 drivers/staging/rtl8712/rtl871x_debug.h #define _module_hci_hal_init_c_ BIT(15) BIT 48 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_ioctl_c_ BIT(16) BIT 49 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_ioctl_set_c_ BIT(17) BIT 50 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_pwrctrl_c_ BIT(19) BIT 51 drivers/staging/rtl8712/rtl871x_debug.h #define _module_hci_intfs_c_ BIT(20) BIT 52 drivers/staging/rtl8712/rtl871x_debug.h #define _module_hci_ops_c_ BIT(21) BIT 53 drivers/staging/rtl8712/rtl871x_debug.h #define _module_osdep_service_c_ BIT(22) BIT 54 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_mp_ioctl_c_ BIT(23) BIT 55 drivers/staging/rtl8712/rtl871x_debug.h #define _module_hci_ops_os_c_ BIT(24) BIT 56 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_ioctl_os_c BIT(25) BIT 57 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl8712_cmd_c_ BIT(26) BIT 58 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl871x_mp_c_ BIT(27) BIT 59 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl8712_xmit_c_ BIT(28) BIT 60 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl8712_efuse_c_ BIT(29) BIT 61 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl8712_recv_c_ BIT(30) BIT 62 drivers/staging/rtl8712/rtl871x_debug.h #define _module_rtl8712_led_c_ BIT(31) BIT 30 drivers/staging/rtl8712/rtl871x_io.h #define _IO_WRITE_ BIT(7) BIT 31 drivers/staging/rtl8712/rtl871x_io.h #define _IO_FIXED_ BIT(8) BIT 32 drivers/staging/rtl8712/rtl871x_io.h #define _IO_BURST_ BIT(9) BIT 33 drivers/staging/rtl8712/rtl871x_io.h #define _IO_BYTE_ BIT(10) BIT 34 drivers/staging/rtl8712/rtl871x_io.h #define _IO_HW_ BIT(11) BIT 35 drivers/staging/rtl8712/rtl871x_io.h #define _IO_WORD_ BIT(12) BIT 36 drivers/staging/rtl8712/rtl871x_io.h #define _IO_SYNC_ BIT(13) BIT 44 drivers/staging/rtl8712/rtl871x_io.h #define _IO_ERR_ BIT(2) BIT 45 drivers/staging/rtl8712/rtl871x_io.h #define _IO_SUCCESS_ BIT(1) BIT 46 drivers/staging/rtl8712/rtl871x_io.h #define _IO_DONE_ BIT(0) BIT 66 drivers/staging/rtl8712/rtl871x_io.h #define _INTF_ASYNC_ BIT(0) /*support async io*/ BIT 341 drivers/staging/rtl8712/rtl871x_mp.c regBwOpMode |= BIT(2); BIT 343 drivers/staging/rtl8712/rtl871x_mp.c regBwOpMode &= ~(BIT(2)); BIT 380 drivers/staging/rtl8712/rtl871x_mp.c BIT(10) | BIT(11), 0x01); BIT 384 drivers/staging/rtl8712/rtl871x_mp.c BIT(10) | BIT(11), 0x00); BIT 1013 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_AAP BIT(0) BIT 1014 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_APM BIT(1) /* accept physical match */ BIT 1015 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_AM BIT(2) /* accept multicast */ BIT 1016 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_AB BIT(3) /* accept broadcast */ BIT 1017 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_ACRC32 BIT(5) /* accept error packet */ BIT 1018 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_9356SEL BIT(6) BIT 1019 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_AICV BIT(12) /* Accept ICV error packet */ BIT 1020 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) /* Rx FIFO threshold */ BIT 1021 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_ADF BIT(18) /* Accept Data(frame type) frame */ BIT 1022 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_ACF BIT(19) /* Accept control frame */ BIT 1023 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_AMF BIT(20) /* Accept management frame */ BIT 1024 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_ADD3 BIT(21) BIT 1025 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_APWRMGT BIT(22) /* Accept power management packet */ BIT 1026 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_CBSSID BIT(23) /* Accept BSSID match packet */ BIT 1027 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_ENMARP BIT(28) /* enable mac auto reset phy */ BIT 1028 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_EnCS1 BIT(29) /* enable carrier sense method 1 */ BIT 1029 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_EnCS2 BIT(30) /* enable carrier sense method 2 */ BIT 1031 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define RCR_OnlyErlPkt BIT(31) BIT 21 drivers/staging/rtl8712/rtl871x_pwrctrl.h #define CMD_ALIVE BIT(2) BIT 45 drivers/staging/rtl8712/rtl871x_pwrctrl.h #define PS_DPS BIT(0) BIT 47 drivers/staging/rtl8712/rtl871x_pwrctrl.h #define PS_RF_OFF BIT(1) BIT 48 drivers/staging/rtl8712/rtl871x_pwrctrl.h #define PS_ALL_ON BIT(2) BIT 49 drivers/staging/rtl8712/rtl871x_pwrctrl.h #define PS_ST_ACTIVE BIT(3) BIT 50 drivers/staging/rtl8712/rtl871x_pwrctrl.h #define PS_LP BIT(4) /* low performance */ BIT 387 drivers/staging/rtl8712/rtl871x_recv.c if (GetFrameSubType(ptr) & (BIT(4) | BIT(5) | BIT(6))) BIT 579 drivers/staging/rtl8712/rtl871x_recv.c pattrib->qos = (subtype & BIT(7)) ? 1 : 0; BIT 725 drivers/staging/rtl8712/rtl871x_xmit.c protection = (*(perp + 2)) & BIT(1); BIT 56 drivers/staging/rtl8712/rtl871x_xmit.h pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ BIT 70 drivers/staging/rtl8712/rtl871x_xmit.h pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ BIT 95 drivers/staging/rtl8712/usb_halinit.c 0x102500ab) | BIT(6) | BIT(7)); BIT 158 drivers/staging/rtl8712/usb_halinit.c r8712_write8(adapter, 0x1025FE5c, (val8 | BIT(7))); BIT 160 drivers/staging/rtl8712/usb_halinit.c r8712_write8(adapter, 0x102500ab, (val8 | BIT(6) | BIT(7))); BIT 254 drivers/staging/rtl8712/usb_halinit.c r8712_write8(adapter, 0x1025FE5c, (val8 | BIT(7))); BIT 418 drivers/staging/rtl8712/usb_intf.c (tmpU1b & (~BIT(7)))); BIT 40 drivers/staging/rtl8712/wifi.h WIFI_CTRL_TYPE = (BIT(2)), BIT 41 drivers/staging/rtl8712/wifi.h WIFI_DATA_TYPE = (BIT(3)), BIT 42 drivers/staging/rtl8712/wifi.h WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), /*!< QoS Data */ BIT 48 drivers/staging/rtl8712/wifi.h WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE), BIT 49 drivers/staging/rtl8712/wifi.h WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE), BIT 50 drivers/staging/rtl8712/wifi.h WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE), BIT 51 drivers/staging/rtl8712/wifi.h WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE), BIT 52 drivers/staging/rtl8712/wifi.h WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE), BIT 53 drivers/staging/rtl8712/wifi.h WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE), BIT 54 drivers/staging/rtl8712/wifi.h WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE), BIT 55 drivers/staging/rtl8712/wifi.h WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE), BIT 56 drivers/staging/rtl8712/wifi.h WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE), BIT 57 drivers/staging/rtl8712/wifi.h WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE), BIT 58 drivers/staging/rtl8712/wifi.h WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE), BIT 60 drivers/staging/rtl8712/wifi.h WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), BIT 61 drivers/staging/rtl8712/wifi.h WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), BIT 62 drivers/staging/rtl8712/wifi.h WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), BIT 63 drivers/staging/rtl8712/wifi.h WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE), BIT 64 drivers/staging/rtl8712/wifi.h WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE), BIT 65 drivers/staging/rtl8712/wifi.h WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), BIT 68 drivers/staging/rtl8712/wifi.h WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE), BIT 69 drivers/staging/rtl8712/wifi.h WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE), BIT 70 drivers/staging/rtl8712/wifi.h WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE), BIT 71 drivers/staging/rtl8712/wifi.h WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE), BIT 72 drivers/staging/rtl8712/wifi.h WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE), BIT 73 drivers/staging/rtl8712/wifi.h WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE), BIT 74 drivers/staging/rtl8712/wifi.h WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE), BIT 132 drivers/staging/rtl8712/wifi.h #define _TO_DS_ BIT(8) BIT 133 drivers/staging/rtl8712/wifi.h #define _FROM_DS_ BIT(9) BIT 134 drivers/staging/rtl8712/wifi.h #define _MORE_FRAG_ BIT(10) BIT 135 drivers/staging/rtl8712/wifi.h #define _RETRY_ BIT(11) BIT 136 drivers/staging/rtl8712/wifi.h #define _PWRMGT_ BIT(12) BIT 137 drivers/staging/rtl8712/wifi.h #define _MORE_DATA_ BIT(13) BIT 138 drivers/staging/rtl8712/wifi.h #define _PRIVACY_ BIT(14) BIT 139 drivers/staging/rtl8712/wifi.h #define _ORDER_ BIT(15) BIT 219 drivers/staging/rtl8712/wifi.h (BIT(3) | BIT(2))) BIT 223 drivers/staging/rtl8712/wifi.h *(__le16 *)(pbuf) &= cpu_to_le16(~(BIT(3) | \ BIT 224 drivers/staging/rtl8712/wifi.h BIT(2))); \ BIT 229 drivers/staging/rtl8712/wifi.h (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | \ BIT 230 drivers/staging/rtl8712/wifi.h BIT(2))) BIT 234 drivers/staging/rtl8712/wifi.h *(__le16 *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | \ BIT 235 drivers/staging/rtl8712/wifi.h BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ BIT 414 drivers/staging/rtl8712/wifi.h #define cap_ESS BIT(0) BIT 415 drivers/staging/rtl8712/wifi.h #define cap_IBSS BIT(1) BIT 416 drivers/staging/rtl8712/wifi.h #define cap_CFPollable BIT(2) BIT 417 drivers/staging/rtl8712/wifi.h #define cap_CFRequest BIT(3) BIT 418 drivers/staging/rtl8712/wifi.h #define cap_Privacy BIT(4) BIT 419 drivers/staging/rtl8712/wifi.h #define cap_ShortPremble BIT(5) BIT 147 drivers/staging/rtl8723bs/core/rtw_ap.c if (pstapriv->tim_bitmap & BIT(0))/* for bc/mc frames */ BIT 148 drivers/staging/rtl8723bs/core/rtw_ap.c *dst_ie++ = BIT(0);/* bitmap ctrl */ BIT 301 drivers/staging/rtl8723bs/core/rtw_ap.c pstapriv->tim_bitmap |= BIT(psta->aid); BIT 873 drivers/staging/rtl8723bs/core/rtw_ap.c if ((cbw40_enable) && (pht_info->infos[0] & BIT(2))) { BIT 1070 drivers/staging/rtl8723bs/core/rtw_ap.c if (cap & BIT(4)) BIT 1098 drivers/staging/rtl8723bs/core/rtw_ap.c psecuritypriv->wpa_psk |= BIT(1); BIT 1129 drivers/staging/rtl8723bs/core/rtw_ap.c psecuritypriv->wpa_psk |= BIT(0); BIT 1156 drivers/staging/rtl8723bs/core/rtw_ap.c *(p + 8) |= BIT(7);/* QoS Info, support U-APSD */ BIT 1159 drivers/staging/rtl8723bs/core/rtw_ap.c *(p + 10) &= ~BIT(4); /* BE */ BIT 1160 drivers/staging/rtl8723bs/core/rtw_ap.c *(p + 14) &= ~BIT(4); /* BK */ BIT 1161 drivers/staging/rtl8723bs/core/rtw_ap.c *(p + 18) &= ~BIT(4); /* VI */ BIT 1162 drivers/staging/rtl8723bs/core/rtw_ap.c *(p + 22) &= ~BIT(4); /* VO */ BIT 1506 drivers/staging/rtl8723bs/core/rtw_ap.c padapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid); BIT 1718 drivers/staging/rtl8723bs/core/rtw_cmd.c if (pstapriv->tim_bitmap & BIT(0)) BIT 1721 drivers/staging/rtl8723bs/core/rtw_cmd.c pstapriv->tim_bitmap &= ~BIT(0); BIT 1722 drivers/staging/rtl8723bs/core/rtw_cmd.c pstapriv->sta_dz_bitmap &= ~BIT(0); BIT 137 drivers/staging/rtl8723bs/core/rtw_efuse.c if (!(word_en & BIT(0))) BIT 139 drivers/staging/rtl8723bs/core/rtw_efuse.c if (!(word_en & BIT(1))) BIT 141 drivers/staging/rtl8723bs/core/rtw_efuse.c if (!(word_en & BIT(2))) BIT 143 drivers/staging/rtl8723bs/core/rtw_efuse.c if (!(word_en & BIT(3))) BIT 365 drivers/staging/rtl8723bs/core/rtw_efuse.c PHY_SetMacReg(padapter, EFUSE_TEST, BIT(11), 0); BIT 413 drivers/staging/rtl8723bs/core/rtw_efuse.c if (!(word_en&BIT(0))) { BIT 417 drivers/staging/rtl8723bs/core/rtw_efuse.c if (!(word_en&BIT(1))) { BIT 421 drivers/staging/rtl8723bs/core/rtw_efuse.c if (!(word_en&BIT(2))) { BIT 425 drivers/staging/rtl8723bs/core/rtw_efuse.c if (!(word_en&BIT(3))) { BIT 63 drivers/staging/rtl8723bs/core/rtw_ieee80211.c return BIT(i); BIT 1237 drivers/staging/rtl8723bs/core/rtw_ieee80211.c if (MCS_rate[0] & BIT(7)) BIT 1239 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(6)) BIT 1241 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(5)) BIT 1243 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(4)) BIT 1245 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(3)) BIT 1247 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(2)) BIT 1249 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(1)) BIT 1251 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(0)) BIT 1255 drivers/staging/rtl8723bs/core/rtw_ieee80211.c if (MCS_rate[1] & BIT(7)) BIT 1257 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(6)) BIT 1259 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(5)) BIT 1261 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(4)) BIT 1263 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(3)) BIT 1265 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(2)) BIT 1267 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(1)) BIT 1269 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[1] & BIT(0)) BIT 1272 drivers/staging/rtl8723bs/core/rtw_ieee80211.c if (MCS_rate[0] & BIT(7)) BIT 1274 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(6)) BIT 1276 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(5)) BIT 1278 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(4)) BIT 1280 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(3)) BIT 1282 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(2)) BIT 1284 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(1)) BIT 1286 drivers/staging/rtl8723bs/core/rtw_ieee80211.c else if (MCS_rate[0] & BIT(0)) BIT 2266 drivers/staging/rtl8723bs/core/rtw_mlme.c adapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid); BIT 2695 drivers/staging/rtl8723bs/core/rtw_mlme.c if (pht_info->infos[0] & BIT(2)) { BIT 2883 drivers/staging/rtl8723bs/core/rtw_mlme.c BIT(1)) && (pmlmeinfo->HT_info.infos[0] & BIT(2))) { BIT 2983 drivers/staging/rtl8723bs/core/rtw_mlme.c psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority); BIT 1316 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if ((psecuritypriv->wpa_psk & BIT(1)) && elems.rsn_ie) { BIT 1325 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c pstat->wpa_psk |= BIT(1); BIT 1339 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c } else if ((psecuritypriv->wpa_psk & BIT(0)) && elems.wpa_ie) { BIT 1348 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c pstat->wpa_psk |= BIT(0); BIT 1467 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if (pstat->qos_info&BIT(0)) BIT 1468 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c pstat->uapsd_vo = BIT(0)|BIT(1); BIT 1472 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if (pstat->qos_info&BIT(1)) BIT 1473 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c pstat->uapsd_vi = BIT(0)|BIT(1); BIT 1477 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if (pstat->qos_info&BIT(2)) BIT 1478 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c pstat->uapsd_bk = BIT(0)|BIT(1); BIT 1482 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if (pstat->qos_info&BIT(3)) BIT 1483 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c pstat->uapsd_be = BIT(0)|BIT(1); BIT 1686 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10)) ? 9 : 20; BIT 1971 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c psta->htpriv.agg_enable_bitmap |= BIT(tid); BIT 1972 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); BIT 1974 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c psta->htpriv.agg_enable_bitmap &= ~BIT(tid); BIT 1979 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c psta->htpriv.agg_enable_bitmap &= ~BIT(tid); BIT 1988 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if ((frame_body[3] & BIT(3)) == 0) { BIT 1990 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c ~BIT((frame_body[3] >> 4) & 0xf); BIT 1992 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c ~BIT((frame_body[3] >> 4) & 0xf); BIT 1996 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c } else if ((frame_body[3] & BIT(3)) == BIT(3)) { BIT 3153 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c le_tmp = cpu_to_le16(pstat->aid | BIT(14) | BIT(15)); BIT 3943 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c BA_para_set |= BIT(1) & IEEE80211_ADDBA_PARAM_POLICY_MASK; BIT 4003 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c le_tmp = cpu_to_le16(BA_para_set & ~BIT(0)); BIT 4005 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c le_tmp = cpu_to_le16(BA_para_set | BIT(0)); BIT 4098 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c iedata |= BIT(2);/* 20 MHz BSS Width Request */ BIT 4214 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if (psta->htpriv.agg_enable_bitmap & BIT(tid)) { BIT 4217 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c psta->htpriv.agg_enable_bitmap &= ~BIT(tid); BIT 4218 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); BIT 4534 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if (val16 & BIT(0)) { BIT 4542 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if (val16 & BIT(4)) BIT 4558 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if (le16_to_cpu(pHT_caps->u.HT_cap_element.HT_caps_info) & BIT(14)) BIT 6021 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c pmlmeinfo->state &= ~(BIT(0)|BIT(1));/* clear state */ BIT 6199 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if ((cbw40_enable) && (pht_info->infos[0] & BIT(2))) { BIT 6452 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c ctrl = BIT(15) | BIT6 | ((pparm->algorithm) << 2) | pparm->keyid; BIT 6503 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid; BIT 6532 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid); BIT 6685 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if ((pstapriv->tim_bitmap&BIT(0)) && (psta_bmc->sleepq_len > 0)) { BIT 435 drivers/staging/rtl8723bs/core/rtw_pwrctrl.c if (!(val8 & BIT(4))) { /* 0x08 bit4 = 1 --> in 32k, bit4 = 0 --> leave 32k */ BIT 481 drivers/staging/rtl8723bs/core/rtw_pwrctrl.c if (val8 & BIT(4)) BIT 909 drivers/staging/rtl8723bs/core/rtw_pwrctrl.c if (val8 & BIT(4)) BIT 1050 drivers/staging/rtl8723bs/core/rtw_pwrctrl.c if (val8 & BIT(4)) BIT 1092 drivers/staging/rtl8723bs/core/rtw_pwrctrl.c if (val8 & BIT(4)) BIT 1350 drivers/staging/rtl8723bs/core/rtw_pwrctrl.c if (pwrpriv->ps_deny & BIT(reason)) { BIT 1354 drivers/staging/rtl8723bs/core/rtw_pwrctrl.c pwrpriv->ps_deny |= BIT(reason); BIT 1376 drivers/staging/rtl8723bs/core/rtw_pwrctrl.c if ((pwrpriv->ps_deny & BIT(reason)) == 0) { BIT 1380 drivers/staging/rtl8723bs/core/rtw_pwrctrl.c pwrpriv->ps_deny &= ~BIT(reason); BIT 710 drivers/staging/rtl8723bs/core/rtw_recv.c wmmps_ac = psta->uapsd_bk&BIT(1); BIT 714 drivers/staging/rtl8723bs/core/rtw_recv.c wmmps_ac = psta->uapsd_vi&BIT(1); BIT 718 drivers/staging/rtl8723bs/core/rtw_recv.c wmmps_ac = psta->uapsd_vo&BIT(1); BIT 723 drivers/staging/rtl8723bs/core/rtw_recv.c wmmps_ac = psta->uapsd_be&BIT(1); BIT 957 drivers/staging/rtl8723bs/core/rtw_recv.c if (GetFrameSubType(ptr) & BIT(6)) { BIT 1061 drivers/staging/rtl8723bs/core/rtw_recv.c if (GetFrameSubType(ptr) & BIT(6)) { BIT 1120 drivers/staging/rtl8723bs/core/rtw_recv.c wmmps_ac = psta->uapsd_bk&BIT(0); BIT 1124 drivers/staging/rtl8723bs/core/rtw_recv.c wmmps_ac = psta->uapsd_vi&BIT(0); BIT 1128 drivers/staging/rtl8723bs/core/rtw_recv.c wmmps_ac = psta->uapsd_vo&BIT(0); BIT 1133 drivers/staging/rtl8723bs/core/rtw_recv.c wmmps_ac = psta->uapsd_be&BIT(0); BIT 1146 drivers/staging/rtl8723bs/core/rtw_recv.c if ((psta->state&WIFI_SLEEP_STATE) && (pstapriv->sta_dz_bitmap&BIT(psta->aid))) { BIT 1178 drivers/staging/rtl8723bs/core/rtw_recv.c pstapriv->tim_bitmap &= ~BIT(psta->aid); BIT 1195 drivers/staging/rtl8723bs/core/rtw_recv.c if (pstapriv->tim_bitmap&BIT(psta->aid)) { BIT 1206 drivers/staging/rtl8723bs/core/rtw_recv.c pstapriv->tim_bitmap &= ~BIT(psta->aid); BIT 1570 drivers/staging/rtl8723bs/core/rtw_recv.c pattrib->qos = (subtype & BIT(7)) ? 1:0; BIT 1165 drivers/staging/rtl8723bs/core/rtw_security.c mic_iv[1] |= BIT(4); BIT 1299 drivers/staging/rtl8723bs/core/rtw_security.c ctr_preload[1] |= BIT(4); BIT 2396 drivers/staging/rtl8723bs/core/rtw_security.c if (securitypriv->key_mask & BIT(keyid)) { BIT 464 drivers/staging/rtl8723bs/core/rtw_sta_mgt.c pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); BIT 465 drivers/staging/rtl8723bs/core/rtw_sta_mgt.c pstapriv->tim_bitmap &= ~BIT(psta->aid); BIT 657 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if (!(cam_ctl->bitmap & BIT(cam_id))) BIT 752 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if (!(cam_ctl->bitmap & BIT(i))) BIT 771 drivers/staging/rtl8723bs/core/rtw_wlan_util.c cam_ctl->bitmap |= BIT(cam_id); BIT 786 drivers/staging/rtl8723bs/core/rtw_wlan_util.c cam_ctl->bitmap &= ~(BIT(cam_id)); BIT 906 drivers/staging/rtl8723bs/core/rtw_wlan_util.c acm_mask |= (ACM ? BIT(1):0); BIT 918 drivers/staging/rtl8723bs/core/rtw_wlan_util.c acm_mask |= (ACM ? BIT(2):0); BIT 924 drivers/staging/rtl8723bs/core/rtw_wlan_util.c acm_mask |= (ACM ? BIT(3):0); BIT 1009 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if ((pHT_info->infos[0] & BIT(2)) && cbw40_enable) { BIT 1245 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if ((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1))) { BIT 1420 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if (val16 & BIT(4)) BIT 1604 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if (mask & BIT(i)) { BIT 2091 drivers/staging/rtl8723bs/core/rtw_wlan_util.c direction = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num; BIT 2095 drivers/staging/rtl8723bs/core/rtw_wlan_util.c value = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 1) & BIT(gpio_num)) >> gpio_num; BIT 2097 drivers/staging/rtl8723bs/core/rtw_wlan_util.c value = (rtw_read8(adapter, REG_GPIO_PIN_CTRL) & BIT(gpio_num)) >> gpio_num; BIT 2123 drivers/staging/rtl8723bs/core/rtw_wlan_util.c direction = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num; BIT 2128 drivers/staging/rtl8723bs/core/rtw_wlan_util.c rtw_write8(adapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 1) | BIT(gpio_num)); BIT 2130 drivers/staging/rtl8723bs/core/rtw_wlan_util.c rtw_write8(adapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(gpio_num)); BIT 2160 drivers/staging/rtl8723bs/core/rtw_wlan_util.c rtw_write8(adapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) | BIT(gpio_num)); BIT 2162 drivers/staging/rtl8723bs/core/rtw_wlan_util.c rtw_write8(adapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & ~BIT(gpio_num)); BIT 631 drivers/staging/rtl8723bs/core/rtw_xmit.c if (acm_mask & BIT(1)) BIT 639 drivers/staging/rtl8723bs/core/rtw_xmit.c if (acm_mask & BIT(2)) BIT 644 drivers/staging/rtl8723bs/core/rtw_xmit.c if (acm_mask & BIT(3)) BIT 1119 drivers/staging/rtl8723bs/core/rtw_xmit.c if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) BIT 1574 drivers/staging/rtl8723bs/core/rtw_xmit.c protection = (*(perp + 2)) & BIT(1); BIT 2448 drivers/staging/rtl8723bs/core/rtw_xmit.c if (!(pstapriv->tim_bitmap & BIT(0))) BIT 2451 drivers/staging/rtl8723bs/core/rtw_xmit.c pstapriv->tim_bitmap |= BIT(0);/* */ BIT 2452 drivers/staging/rtl8723bs/core/rtw_xmit.c pstapriv->sta_dz_bitmap |= BIT(0); BIT 2482 drivers/staging/rtl8723bs/core/rtw_xmit.c if (pstapriv->sta_dz_bitmap & BIT(psta->aid)) { BIT 2494 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_bk&BIT(0); BIT 2498 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_vi&BIT(0); BIT 2502 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_vo&BIT(0); BIT 2507 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_be&BIT(0); BIT 2515 drivers/staging/rtl8723bs/core/rtw_xmit.c if (!(pstapriv->tim_bitmap & BIT(psta->aid))) BIT 2518 drivers/staging/rtl8723bs/core/rtw_xmit.c pstapriv->tim_bitmap |= BIT(psta->aid); BIT 2602 drivers/staging/rtl8723bs/core/rtw_xmit.c pstapriv->sta_dz_bitmap |= BIT(psta->aid); BIT 2657 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_bk&BIT(1); BIT 2661 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_vi&BIT(1); BIT 2665 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_vo&BIT(1); BIT 2670 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_be&BIT(1); BIT 2707 drivers/staging/rtl8723bs/core/rtw_xmit.c if (pstapriv->tim_bitmap & BIT(psta->aid)) { BIT 2711 drivers/staging/rtl8723bs/core/rtw_xmit.c update_mask = BIT(0); BIT 2714 drivers/staging/rtl8723bs/core/rtw_xmit.c pstapriv->tim_bitmap &= ~BIT(psta->aid); BIT 2725 drivers/staging/rtl8723bs/core/rtw_xmit.c pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); BIT 2765 drivers/staging/rtl8723bs/core/rtw_xmit.c if (pstapriv->tim_bitmap & BIT(0)) { BIT 2769 drivers/staging/rtl8723bs/core/rtw_xmit.c update_mask |= BIT(1); BIT 2771 drivers/staging/rtl8723bs/core/rtw_xmit.c pstapriv->tim_bitmap &= ~BIT(0); BIT 2772 drivers/staging/rtl8723bs/core/rtw_xmit.c pstapriv->sta_dz_bitmap &= ~BIT(0); BIT 2812 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_bk&BIT(1); BIT 2816 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_vi&BIT(1); BIT 2820 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_vo&BIT(1); BIT 2825 drivers/staging/rtl8723bs/core/rtw_xmit.c wmmps_ac = psta->uapsd_be&BIT(1); BIT 2849 drivers/staging/rtl8723bs/core/rtw_xmit.c pstapriv->tim_bitmap &= ~BIT(psta->aid); BIT 432 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define AcmHw_HwEn_8723B BIT(0) BIT 433 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define AcmHw_VoqEn_8723B BIT(1) BIT 434 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define AcmHw_ViqEn_8723B BIT(2) BIT 435 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define AcmHw_BeqEn_8723B BIT(3) BIT 436 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define AcmHw_VoqStatus_8723B BIT(5) BIT 437 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define AcmHw_ViqStatus_8723B BIT(6) BIT 438 drivers/staging/rtl8723bs/hal/Hal8723BReg.h #define AcmHw_BeqStatus_8723B BIT(7) BIT 1112 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(31), ((X*Oldval_0>>7) & 0x1)); BIT 1129 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(29), ((Y*Oldval_0>>7) & 0x1)); BIT 1193 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(27), ((X*Oldval_1>>7) & 0x1)); BIT 1213 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(25), ((Y*Oldval_1>>7) & 0x1)); BIT 996 drivers/staging/rtl8723bs/hal/hal_com.c if (psta->htpriv.ht_cap.supp_mcs_set[i/8] & BIT(i%8)) BIT 997 drivers/staging/rtl8723bs/hal/hal_com.c tx_ra_bitmap |= BIT(i+12); BIT 595 drivers/staging/rtl8723bs/hal/odm.h ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */ BIT 596 drivers/staging/rtl8723bs/hal/odm.h ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ BIT 597 drivers/staging/rtl8723bs/hal/odm.h ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ BIT 598 drivers/staging/rtl8723bs/hal/odm.h ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */ BIT 599 drivers/staging/rtl8723bs/hal/odm.h ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ BIT 600 drivers/staging/rtl8723bs/hal/odm.h ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */ BIT 601 drivers/staging/rtl8723bs/hal/odm.h ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */ BIT 602 drivers/staging/rtl8723bs/hal/odm.h ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ BIT 607 drivers/staging/rtl8723bs/hal/odm.h ODM_PACKAGE_QFN68 = BIT(0), BIT 608 drivers/staging/rtl8723bs/hal/odm.h ODM_PACKAGE_TFBGA90 = BIT(1), BIT 609 drivers/staging/rtl8723bs/hal/odm.h ODM_PACKAGE_TFBGA79 = BIT(2), BIT 614 drivers/staging/rtl8723bs/hal/odm.h TYPE_GPA1 = BIT(1)|BIT(0) BIT 619 drivers/staging/rtl8723bs/hal/odm.h TYPE_APA1 = BIT(1)|BIT(0) BIT 624 drivers/staging/rtl8723bs/hal/odm.h TYPE_GLNA1 = BIT(2)|BIT(0), BIT 625 drivers/staging/rtl8723bs/hal/odm.h TYPE_GLNA2 = BIT(3)|BIT(1), BIT 626 drivers/staging/rtl8723bs/hal/odm.h TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) BIT 631 drivers/staging/rtl8723bs/hal/odm.h TYPE_ALNA1 = BIT(2)|BIT(0), BIT 632 drivers/staging/rtl8723bs/hal/odm.h TYPE_ALNA2 = BIT(3)|BIT(1), BIT 633 drivers/staging/rtl8723bs/hal/odm.h TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) BIT 158 drivers/staging/rtl8723bs/hal/odm_HWConfig.c if (pDM_Odm->RFPathRxEnable & BIT(i)) BIT 30 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c valid = rtw_read8(padapter, REG_HMETFR) & BIT(msgbox_num); BIT 1051 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c if ((rlbm == 2) && (byte5 & BIT(4))) { BIT 1258 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c while (!(res&BIT(7)) && count < 25) { BIT 1940 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c v8 |= BIT(0); /* ENSWBCN */ BIT 1952 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c if (pHalData->RegFwHwTxQCtrl & BIT(6)) BIT 1956 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl & ~BIT(6)); BIT 1957 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c pHalData->RegFwHwTxQCtrl &= ~BIT(6); BIT 2009 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl | BIT(6)); BIT 2010 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c pHalData->RegFwHwTxQCtrl |= BIT(6); BIT 2015 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c v8 &= ~BIT(0); /* ~ENSWBCN */ BIT 2255 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c val8 |= BIT(0); /* ENSWBCN */ BIT 2267 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c if (pHalData->RegFwHwTxQCtrl & BIT(6)) BIT 2271 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c pHalData->RegFwHwTxQCtrl &= ~BIT(6); BIT 2318 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c pHalData->RegFwHwTxQCtrl |= BIT(6); BIT 2324 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c val8 &= ~BIT(0); /* ~ENSWBCN */ BIT 200 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c io_rst &= ~BIT(0); BIT 204 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c cpu_rst &= ~BIT(2); BIT 210 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c io_rst |= BIT(0); BIT 214 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c cpu_rst |= BIT(2); BIT 749 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c tempval |= BIT(6); BIT 758 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c tempval &= ~BIT(7); BIT 764 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c tempval |= BIT(7); BIT 773 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c tempval &= ~BIT(6); BIT 790 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (tempval & BIT(0)) { /* SDIO local register is suspend */ BIT 794 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c tempval &= ~BIT(0); BIT 1401 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (!(word_en & BIT(0))) { BIT 1409 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c badworden &= (~BIT(0)); BIT 1412 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (!(word_en & BIT(1))) { BIT 1420 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c badworden &= (~BIT(1)); BIT 1424 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (!(word_en & BIT(2))) { BIT 1432 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c badworden &= (~BIT(2)); BIT 1436 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (!(word_en & BIT(3))) { BIT 1444 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c badworden &= (~BIT(3)); BIT 1971 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7)|BIT(7)); /* enable single pkt ampdu */ BIT 1975 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8723B, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL)&(~BIT(7))); BIT 2002 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->RegFwHwTxQCtrl |= BIT(6); BIT 2005 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->RegReg542 |= BIT(0); BIT 2019 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->RegFwHwTxQCtrl &= ~BIT(6); BIT 2022 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->RegReg542 &= ~BIT(0); BIT 2245 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */ BIT 2654 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->EEPROMBluetoothAntNum = tempval & BIT(0); BIT 2657 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pHalData->ant_path = (tempval & BIT(6))?ODM_RF_PATH_B:ODM_RF_PATH_A; BIT 3116 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & BIT(7)) BIT 3124 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (padapter->fix_rate & BIT(7)) BIT 3387 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0)); BIT 3506 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0)); BIT 3976 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtw_write32(padapter, RWCAM, BIT(31)|BIT(30)); BIT 4016 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (ctrl & BIT(1)) /* BE */ BIT 4019 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (ctrl & BIT(2)) /* VI */ BIT 4022 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (ctrl & BIT(3)) /* VO */ BIT 4108 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c #define RW_RELEASE_EN BIT(18) BIT 4109 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c #define RXDMA_IDLE BIT(17) BIT 4181 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val8 |= BIT(0); BIT 4190 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val8 &= ~BIT(4); BIT 4219 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (val32 & BIT(val8)) BIT 4221 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val32 |= BIT(val8); BIT 4238 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (!(val32 & BIT(val8))) BIT 4240 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c val32 &= ~BIT(val8); BIT 4265 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = (BIT(0) & val8) ? true : false; BIT 4319 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c *val = (val16 & BIT(10)) ? true:false; BIT 55 drivers/staging/rtl8723bs/hal/sdio_halinit.c value32 |= BIT(12);/* 4+8 */ BIT 57 drivers/staging/rtl8723bs/hal/sdio_halinit.c value32 |= BIT(20);/* 4+16 */ BIT 66 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index)); BIT 71 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index)); BIT 75 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index)); BIT 77 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index)); BIT 86 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index)); BIT 91 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index)); BIT 95 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index)); BIT 97 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index)); BIT 116 drivers/staging/rtl8723bs/hal/sdio_halinit.c value8 |= BIT(7); BIT 124 drivers/staging/rtl8723bs/hal/sdio_halinit.c value8 |= BIT(5); BIT 141 drivers/staging/rtl8723bs/hal/sdio_halinit.c value8 |= BIT(1); /* Enable falling edge triggering interrupt */ BIT 144 drivers/staging/rtl8723bs/hal/sdio_halinit.c value8 |= BIT(1); BIT 179 drivers/staging/rtl8723bs/hal/sdio_halinit.c value16 |= BIT(11); /* BIT_EEPRPAD_RFE_CTRL_EN */ BIT 184 drivers/staging/rtl8723bs/hal/sdio_halinit.c value32 |= BIT(23); /* DPDT_SEL_EN, 1 for SW control */ BIT 189 drivers/staging/rtl8723bs/hal/sdio_halinit.c value8 &= ~BIT(0); /* BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */ BIT 742 drivers/staging/rtl8723bs/hal/sdio_halinit.c val8 |= BIT(6); BIT 780 drivers/staging/rtl8723bs/hal/sdio_halinit.c reg_val &= ~(BIT(0) | BIT(1)); BIT 788 drivers/staging/rtl8723bs/hal/sdio_halinit.c reg_val &= ~(BIT(4) | BIT(7)); BIT 791 drivers/staging/rtl8723bs/hal/sdio_halinit.c reg_val |= BIT(4) | BIT(7); BIT 964 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12)); BIT 1045 drivers/staging/rtl8723bs/hal/sdio_halinit.c u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */ BIT 1054 drivers/staging/rtl8723bs/hal/sdio_halinit.c u1bTmp &= ~BIT(0); BIT 1057 drivers/staging/rtl8723bs/hal/sdio_halinit.c u1bTmp |= BIT(0); BIT 1097 drivers/staging/rtl8723bs/hal/sdio_halinit.c val8 |= BIT(0); BIT 1378 drivers/staging/rtl8723bs/hal/sdio_halinit.c val8 |= BIT(6); BIT 59 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_INTF_SDIO_MSK BIT(0) BIT 60 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_INTF_USB_MSK BIT(1) BIT 61 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_INTF_PCI_MSK BIT(2) BIT 62 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) BIT 67 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_FAB_TSMC_MSK BIT(0) BIT 68 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_FAB_UMC_MSK BIT(1) BIT 69 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) BIT 74 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_CUT_TESTCHIP_MSK BIT(0) BIT 75 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_CUT_A_MSK BIT(1) BIT 76 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_CUT_B_MSK BIT(2) BIT 77 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_CUT_C_MSK BIT(3) BIT 78 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_CUT_D_MSK BIT(4) BIT 79 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_CUT_E_MSK BIT(5) BIT 80 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_CUT_F_MSK BIT(6) BIT 81 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define PWR_CUT_G_MSK BIT(7) BIT 73 drivers/staging/rtl8723bs/include/drv_types.h #define SPEC_DEV_ID_NONE BIT(0) BIT 74 drivers/staging/rtl8723bs/include/drv_types.h #define SPEC_DEV_ID_DISABLE_HT BIT(1) BIT 75 drivers/staging/rtl8723bs/include/drv_types.h #define SPEC_DEV_ID_ENABLE_PS BIT(2) BIT 76 drivers/staging/rtl8723bs/include/drv_types.h #define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3) BIT 77 drivers/staging/rtl8723bs/include/drv_types.h #define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4) BIT 78 drivers/staging/rtl8723bs/include/drv_types.h #define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5) BIT 182 drivers/staging/rtl8723bs/include/hal_com.h #define TX_SELE_HQ BIT(0) /* High Queue */ BIT 183 drivers/staging/rtl8723bs/include/hal_com.h #define TX_SELE_LQ BIT(1) /* Low Queue */ BIT 184 drivers/staging/rtl8723bs/include/hal_com.h #define TX_SELE_NQ BIT(2) /* Normal Queue */ BIT 185 drivers/staging/rtl8723bs/include/hal_com.h #define TX_SELE_EQ BIT(3) /* Extern Queue */ BIT 126 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_FUN_EN BIT(0) BIT 127 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_PATTERN_MATCH BIT(1) BIT 128 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_MAGIC_PKT BIT(2) BIT 129 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_UNICAST BIT(3) BIT 130 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_ALL_PKT_DROP BIT(4) BIT 131 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_GPIO_ACTIVE BIT(5) BIT 132 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_REKEY_WAKEUP BIT(6) BIT 133 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_DEAUTH_WAKEUP BIT(7) BIT 135 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0) BIT 136 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_FW_PARSE_MAGIC_PKT BIT(1) BIT 138 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_REMOTE_WAKE_CTRL_EN BIT(0) BIT 139 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_REALWOWLAN_EN BIT(5) BIT 141 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_KEEP_ALIVE_EN BIT(0) BIT 142 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_ADOPT_USER BIT(1) BIT 143 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOWLAN_KEEP_ALIVE_PKT_TYPE BIT(2) BIT 145 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_REMOTE_WAKE_CTRL_EN BIT(0) BIT 146 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_ARP_EN BIT(1) BIT 147 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_REALWOWLAN_EN BIT(5) BIT 148 drivers/staging/rtl8723bs/include/hal_com_h2c.h #define FW_WOW_FW_UNICAST_EN BIT(7) BIT 393 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RXERR_RPT_RST BIT(27) BIT 676 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_1M BIT(0) BIT 677 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_2M BIT(1) BIT 678 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_5_5M BIT(2) BIT 679 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_11M BIT(3) BIT 681 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_6M BIT(4) BIT 682 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_9M BIT(5) BIT 683 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_12M BIT(6) BIT 684 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_18M BIT(7) BIT 685 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_24M BIT(8) BIT 686 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_36M BIT(9) BIT 687 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_48M BIT(10) BIT 688 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_54M BIT(11) BIT 690 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS0 BIT(12) BIT 691 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS1 BIT(13) BIT 692 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS2 BIT(14) BIT 693 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS3 BIT(15) BIT 694 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS4 BIT(16) BIT 695 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS5 BIT(17) BIT 696 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS6 BIT(18) BIT 697 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS7 BIT(19) BIT 699 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS8 BIT(20) BIT 700 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS9 BIT(21) BIT 701 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS10 BIT(22) BIT 702 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS11 BIT(23) BIT 703 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS12 BIT(24) BIT 704 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS13 BIT(25) BIT 705 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS14 BIT(26) BIT 706 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RATE_MCS15 BIT(27) BIT 1062 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ISO_MD2PP BIT(0) BIT 1063 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ISO_UA2USB BIT(1) BIT 1064 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ISO_UD2CORE BIT(2) BIT 1065 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ISO_PA2PCIE BIT(3) BIT 1066 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ISO_PD2CORE BIT(4) BIT 1067 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ISO_IP2MAC BIT(5) BIT 1068 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ISO_DIOP BIT(6) BIT 1069 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ISO_DIOE BIT(7) BIT 1070 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ISO_EB2CORE BIT(8) BIT 1071 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ISO_DIOR BIT(9) BIT 1072 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PWC_EV12V BIT(15) BIT 1076 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_BBRSTB BIT(0) BIT 1077 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_BB_GLB_RSTn BIT(1) BIT 1078 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_USBA BIT(2) BIT 1079 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_UPLL BIT(3) BIT 1080 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_USBD BIT(4) BIT 1081 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_DIO_PCIE BIT(5) BIT 1082 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_PCIEA BIT(6) BIT 1083 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_PPLL BIT(7) BIT 1084 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_PCIED BIT(8) BIT 1085 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_DIOE BIT(9) BIT 1086 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_CPUEN BIT(10) BIT 1087 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_DCORE BIT(11) BIT 1088 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_ELDR BIT(12) BIT 1089 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_EN_25_1 BIT(13) BIT 1090 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_HWPDN BIT(14) BIT 1091 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_MREGEN BIT(15) BIT 1094 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PFM_LDALL BIT(0) BIT 1095 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PFM_ALDN BIT(1) BIT 1096 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PFM_LDKP BIT(2) BIT 1097 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PFM_WOWL BIT(3) BIT 1098 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EnPDN BIT(4) BIT 1099 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PDN_PL BIT(5) BIT 1100 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APFM_ONMAC BIT(8) BIT 1101 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APFM_OFF BIT(9) BIT 1102 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APFM_RSM BIT(10) BIT 1103 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AFSM_HSUS BIT(11) BIT 1104 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AFSM_PCIE BIT(12) BIT 1105 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APDM_MAC BIT(13) BIT 1106 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APDM_HOST BIT(14) BIT 1107 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APDM_HPDN BIT(15) BIT 1108 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RDY_MACON BIT(16) BIT 1109 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SUS_HOST BIT(17) BIT 1110 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ROP_ALD BIT(20) BIT 1111 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ROP_PWR BIT(21) BIT 1112 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ROP_SPS BIT(22) BIT 1113 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SOP_MRST BIT(25) BIT 1114 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SOP_FUSE BIT(26) BIT 1115 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SOP_ABG BIT(27) BIT 1116 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SOP_AMB BIT(28) BIT 1117 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SOP_RCK BIT(29) BIT 1118 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SOP_A8M BIT(30) BIT 1119 drivers/staging/rtl8723bs/include/hal_com_reg.h #define XOP_BTCK BIT(31) BIT 1122 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ANAD16V_EN BIT(0) BIT 1123 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ANA8M BIT(1) BIT 1124 drivers/staging/rtl8723bs/include/hal_com_reg.h #define MACSLP BIT(4) BIT 1125 drivers/staging/rtl8723bs/include/hal_com_reg.h #define LOADER_CLK_EN BIT(5) BIT 1129 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BOOT_FROM_EEPROM BIT(4) BIT 1130 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EEPROMSEL BIT(4) BIT 1131 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EEPROM_EN BIT(5) BIT 1135 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RF_EN BIT(0) BIT 1136 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RF_RSTB BIT(1) BIT 1137 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RF_SDMRSTB BIT(2) BIT 1141 drivers/staging/rtl8723bs/include/hal_com_reg.h #define LDV12_EN BIT(0) BIT 1142 drivers/staging/rtl8723bs/include/hal_com_reg.h #define LDV12_SDBY BIT(1) BIT 1143 drivers/staging/rtl8723bs/include/hal_com_reg.h #define LPLDO_HSM BIT(2) BIT 1144 drivers/staging/rtl8723bs/include/hal_com_reg.h #define LPLDO_LSM_DIS BIT(3) BIT 1150 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EF_TRPT BIT(7) BIT 1151 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EF_CELL_SEL (BIT(8)|BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ BIT 1152 drivers/staging/rtl8723bs/include/hal_com_reg.h #define LDOE25_EN BIT(31) BIT 1163 drivers/staging/rtl8723bs/include/hal_com_reg.h #define MCUFWDL_EN BIT(0) BIT 1164 drivers/staging/rtl8723bs/include/hal_com_reg.h #define MCUFWDL_RDY BIT(1) BIT 1165 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FWDL_ChkSum_rpt BIT(2) BIT 1166 drivers/staging/rtl8723bs/include/hal_com_reg.h #define MACINI_RDY BIT(3) BIT 1167 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BBINI_RDY BIT(4) BIT 1168 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RFINI_RDY BIT(5) BIT 1169 drivers/staging/rtl8723bs/include/hal_com_reg.h #define WINTINI_RDY BIT(6) BIT 1170 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RAM_DL_SEL BIT(7) BIT 1171 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ROM_DLEN BIT(19) BIT 1172 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CPRST BIT(23) BIT 1176 drivers/staging/rtl8723bs/include/hal_com_reg.h #define XCLK_VLD BIT(0) BIT 1177 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ACLK_VLD BIT(1) BIT 1178 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UCLK_VLD BIT(2) BIT 1179 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PCLK_VLD BIT(3) BIT 1180 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PCIRSTB BIT(4) BIT 1181 drivers/staging/rtl8723bs/include/hal_com_reg.h #define V15_VLD BIT(5) BIT 1182 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SW_OFFLOAD_EN BIT(7) BIT 1183 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SIC_IDLE BIT(8) BIT 1184 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BD_MAC2 BIT(9) BIT 1185 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BD_MAC1 BIT(10) BIT 1186 drivers/staging/rtl8723bs/include/hal_com_reg.h #define IC_MACPHY_MODE BIT(11) BIT 1187 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) BIT 1188 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BT_FUNC BIT(16) BIT 1189 drivers/staging/rtl8723bs/include/hal_com_reg.h #define VENDOR_ID BIT(19) BIT 1190 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EXT_VENDOR_ID (BIT(18)|BIT(19)) /* Currently only for RTL8723B */ BIT 1191 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PAD_HWPD_IDN BIT(22) BIT 1192 drivers/staging/rtl8723bs/include/hal_com_reg.h #define TRP_VAUX_EN BIT(23) /* RTL ID */ BIT 1193 drivers/staging/rtl8723bs/include/hal_com_reg.h #define TRP_BT_EN BIT(24) BIT 1194 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BD_PKG_SEL BIT(25) BIT 1195 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BD_HCI_SEL BIT(26) BIT 1196 drivers/staging/rtl8723bs/include/hal_com_reg.h #define TYPE_ID BIT(27) BIT 1197 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RF_TYPE_ID BIT(27) BIT 1199 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ BIT 1200 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SPS_SEL BIT(24) /* 1:LDO regulator mode; 0:Switching regulator mode */ BIT 1208 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EFS_HCI_SEL (BIT(0)|BIT(1)) BIT 1209 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PAD_HCI_SEL (BIT(2)|BIT(3)) BIT 1210 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HCI_SEL (BIT(4)|BIT(5)) BIT 1211 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PKG_SEL_HCI BIT(6) BIT 1212 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_GPS BIT(7) BIT 1213 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_BT BIT(8) BIT 1214 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_WL BIT(9) BIT 1215 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_PCI BIT(10) BIT 1216 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FEN_USB BIT(11) BIT 1217 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BTRF_HWPDN_N BIT(12) BIT 1218 drivers/staging/rtl8723bs/include/hal_com_reg.h #define WLRF_HWPDN_N BIT(13) BIT 1219 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PDN_BT_N BIT(14) BIT 1220 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PDN_GPS_N BIT(15) BIT 1221 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BT_CTL_HWPDN BIT(16) BIT 1222 drivers/staging/rtl8723bs/include/hal_com_reg.h #define GPS_CTL_HWPDN BIT(17) BIT 1223 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PPHY_SUSB BIT(20) BIT 1224 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UPHY_SUSB BIT(21) BIT 1225 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PCI_SUSEN BIT(22) BIT 1226 drivers/staging/rtl8723bs/include/hal_com_reg.h #define USB_SUSEN BIT(23) BIT 1227 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) BIT 1238 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HCI_TXDMA_EN BIT(0) BIT 1239 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HCI_RXDMA_EN BIT(1) BIT 1240 drivers/staging/rtl8723bs/include/hal_com_reg.h #define TXDMA_EN BIT(2) BIT 1241 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RXDMA_EN BIT(3) BIT 1242 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PROTOCOL_EN BIT(4) BIT 1243 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SCHEDULE_EN BIT(5) BIT 1244 drivers/staging/rtl8723bs/include/hal_com_reg.h #define MACTXEN BIT(6) BIT 1245 drivers/staging/rtl8723bs/include/hal_com_reg.h #define MACRXEN BIT(7) BIT 1246 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ENSWBCN BIT(8) BIT 1247 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ENSEC BIT(9) BIT 1248 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ BIT 1274 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RXDMA_ARBBW_EN BIT(0) BIT 1275 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RXSHFT_EN BIT(1) BIT 1276 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RXDMA_AGG_EN BIT(2) BIT 1277 drivers/staging/rtl8723bs/include/hal_com_reg.h #define QS_VO_QUEUE BIT(8) BIT 1278 drivers/staging/rtl8723bs/include/hal_com_reg.h #define QS_VI_QUEUE BIT(9) BIT 1279 drivers/staging/rtl8723bs/include/hal_com_reg.h #define QS_BE_QUEUE BIT(10) BIT 1280 drivers/staging/rtl8723bs/include/hal_com_reg.h #define QS_BK_QUEUE BIT(11) BIT 1281 drivers/staging/rtl8723bs/include/hal_com_reg.h #define QS_MANAGER_QUEUE BIT(12) BIT 1282 drivers/staging/rtl8723bs/include/hal_com_reg.h #define QS_HIGH_QUEUE BIT(13) BIT 1284 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HQSEL_VOQ BIT(0) BIT 1285 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HQSEL_VIQ BIT(1) BIT 1286 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HQSEL_BEQ BIT(2) BIT 1287 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HQSEL_BKQ BIT(3) BIT 1288 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HQSEL_MGTQ BIT(4) BIT 1289 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HQSEL_HIQ BIT(5) BIT 1333 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HPQ_PUBLIC_DIS BIT(24) BIT 1334 drivers/staging/rtl8723bs/include/hal_com_reg.h #define LPQ_PUBLIC_DIS BIT(25) BIT 1335 drivers/staging/rtl8723bs/include/hal_com_reg.h #define LD_RQPN BIT(31) BIT 1344 drivers/staging/rtl8723bs/include/hal_com_reg.h #define DROP_DATA_EN BIT(9) BIT 1351 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BIT_TDE_DBG_SEL BIT(23) BIT 1352 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BIT_AUTO_INIT_LLT BIT(16) BIT 1377 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RXPKT_RELEASE_POLL BIT(16) BIT 1378 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RXDMA_IDLE BIT(17) BIT 1379 drivers/staging/rtl8723bs/include/hal_com_reg.h #define RW_RELEASE_EN BIT(18) BIT 1387 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EN_AMPDU_RTY_NEW BIT(7) BIT 1416 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EN_TXBCN_RPT BIT(2) BIT 1417 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EN_BCN_FUNCTION BIT(3) BIT 1418 drivers/staging/rtl8723bs/include/hal_com_reg.h #define STOP_BCNQ BIT(6) BIT 1419 drivers/staging/rtl8723bs/include/hal_com_reg.h #define DIS_RX_BSSID_FIT BIT(6) BIT 1421 drivers/staging/rtl8723bs/include/hal_com_reg.h #define DIS_ATIM BIT(0) BIT 1422 drivers/staging/rtl8723bs/include/hal_com_reg.h #define DIS_BCNQ_SUB BIT(1) BIT 1423 drivers/staging/rtl8723bs/include/hal_com_reg.h #define DIS_TSF_UDT BIT(4) BIT 1426 drivers/staging/rtl8723bs/include/hal_com_reg.h #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) BIT 1427 drivers/staging/rtl8723bs/include/hal_com_reg.h #define DIS_TSF_UDT0_TEST_CHIP BIT(5) BIT 1431 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AcmHw_HwEn BIT(0) BIT 1432 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AcmHw_BeqEn BIT(1) BIT 1433 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AcmHw_ViqEn BIT(2) BIT 1434 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AcmHw_VoqEn BIT(3) BIT 1435 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AcmHw_BeqStatus BIT(4) BIT 1436 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AcmHw_ViqStatus BIT(5) BIT 1437 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AcmHw_VoqStatus BIT(6) BIT 1440 drivers/staging/rtl8723bs/include/hal_com_reg.h #define DUAL_TSF_RST_P2P BIT(4) BIT 1444 drivers/staging/rtl8723bs/include/hal_com_reg.h #define NOA_DESC_SEL_1 BIT(4) BIT 1453 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APSDOFF BIT(6) BIT 1456 drivers/staging/rtl8723bs/include/hal_com_reg.h #define TSFRST BIT(0) BIT 1457 drivers/staging/rtl8723bs/include/hal_com_reg.h #define DIS_GCLK BIT(1) BIT 1458 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PAD_SEL BIT(2) BIT 1459 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PWR_ST BIT(6) BIT 1460 drivers/staging/rtl8723bs/include/hal_com_reg.h #define PWRBIT_OW_EN BIT(7) BIT 1461 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ACRC BIT(8) BIT 1462 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CFENDFORM BIT(9) BIT 1463 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ICV BIT(10) BIT 1467 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AAP BIT(0) BIT 1468 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APM BIT(1) BIT 1469 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AM BIT(2) BIT 1470 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AB BIT(3) BIT 1471 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ADD3 BIT(4) BIT 1472 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APWRMGT BIT(5) BIT 1473 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CBSSID BIT(6) BIT 1474 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CBSSID_DATA BIT(6) BIT 1475 drivers/staging/rtl8723bs/include/hal_com_reg.h #define CBSSID_BCN BIT(7) BIT 1476 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ACRC32 BIT(8) BIT 1477 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AICV BIT(9) BIT 1478 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ADF BIT(11) BIT 1479 drivers/staging/rtl8723bs/include/hal_com_reg.h #define ACF BIT(12) BIT 1480 drivers/staging/rtl8723bs/include/hal_com_reg.h #define AMF BIT(13) BIT 1481 drivers/staging/rtl8723bs/include/hal_com_reg.h #define HTC_LOC_CTRL BIT(14) BIT 1482 drivers/staging/rtl8723bs/include/hal_com_reg.h #define UC_DATA_EN BIT(16) BIT 1483 drivers/staging/rtl8723bs/include/hal_com_reg.h #define BM_DATA_EN BIT(17) BIT 1484 drivers/staging/rtl8723bs/include/hal_com_reg.h #define MFBEN BIT(22) BIT 1485 drivers/staging/rtl8723bs/include/hal_com_reg.h #define LSIGEN BIT(23) BIT 1486 drivers/staging/rtl8723bs/include/hal_com_reg.h #define EnMBID BIT(24) BIT 1487 drivers/staging/rtl8723bs/include/hal_com_reg.h #define FORCEACK BIT(26) BIT 1488 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APP_BASSN BIT(27) BIT 1489 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APP_PHYSTS BIT(28) BIT 1490 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APP_ICV BIT(29) BIT 1491 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APP_MIC BIT(30) BIT 1492 drivers/staging/rtl8723bs/include/hal_com_reg.h #define APP_FCS BIT(31) BIT 1496 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ BIT 1497 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ BIT 1498 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ BIT 1499 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ BIT 1500 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ BIT 1501 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ BIT 1502 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SCR_TXBCUSEDK BIT(6) /* Force Tx Broadcast packets Use Default Key */ BIT 1503 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SCR_RXBCUSEDK BIT(7) /* Force Rx Broadcast packets Use Default Key */ BIT 1504 drivers/staging/rtl8723bs/include/hal_com_reg.h #define SCR_CHK_KEYID BIT(8) BIT 1652 drivers/staging/rtl8723bs/include/hal_com_reg.h #define USB_SPEED_MASK BIT(5) BIT 1658 drivers/staging/rtl8723bs/include/hal_com_reg.h #define USB_AGG_EN BIT(3) BIT 1662 drivers/staging/rtl8723bs/include/hal_com_reg.h #define INT_BULK_SEL BIT(4) BIT 49 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_AUTH BIT(0) BIT 50 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_ASSOC BIT(1) BIT 51 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_PS BIT(2) BIT 52 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_TIM BIT(3) BIT 53 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_PERM BIT(4) BIT 54 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_AUTHORIZED BIT(5) BIT 55 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ BIT 56 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_SHORT_PREAMBLE BIT(7) BIT 57 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_PREAUTH BIT(8) BIT 58 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_WME BIT(9) BIT 59 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_MFP BIT(10) BIT 60 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_HT BIT(11) BIT 61 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_WPS BIT(12) BIT 62 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_MAYBE_WPS BIT(13) BIT 63 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_VHT BIT(14) BIT 64 drivers/staging/rtl8723bs/include/ieee80211.h #define WLAN_STA_NONERP BIT(31) BIT 92 drivers/staging/rtl8723bs/include/ieee80211.h #define WPA_CIPHER_NONE BIT(0) BIT 93 drivers/staging/rtl8723bs/include/ieee80211.h #define WPA_CIPHER_WEP40 BIT(1) BIT 94 drivers/staging/rtl8723bs/include/ieee80211.h #define WPA_CIPHER_WEP104 BIT(2) BIT 95 drivers/staging/rtl8723bs/include/ieee80211.h #define WPA_CIPHER_TKIP BIT(3) BIT 96 drivers/staging/rtl8723bs/include/ieee80211.h #define WPA_CIPHER_CCMP BIT(4) BIT 159 drivers/staging/rtl8723bs/include/ieee80211.h WIRELESS_11B = BIT(0), /* tx: cck only , rx: cck only, hw: cck */ BIT 160 drivers/staging/rtl8723bs/include/ieee80211.h WIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */ BIT 161 drivers/staging/rtl8723bs/include/ieee80211.h WIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */ BIT 162 drivers/staging/rtl8723bs/include/ieee80211.h WIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */ BIT 163 drivers/staging/rtl8723bs/include/ieee80211.h WIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */ BIT 164 drivers/staging/rtl8723bs/include/ieee80211.h WIRELESS_AUTO = BIT(5), BIT 165 drivers/staging/rtl8723bs/include/ieee80211.h WIRELESS_11AC = BIT(6), BIT 304 drivers/staging/rtl8723bs/include/ieee80211.h #define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0) BIT 305 drivers/staging/rtl8723bs/include/ieee80211.h #define RTW_ERP_INFO_USE_PROTECTION BIT(1) BIT 306 drivers/staging/rtl8723bs/include/ieee80211.h #define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2) BIT 17 drivers/staging/rtl8723bs/include/osdep_service.h #ifndef BIT BIT 164 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define BIT_USB_RXDMA_AGG_EN BIT(31) BIT 165 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define RXDMA_AGG_MODE_EN BIT(1) BIT 168 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define RXPKT_RELEASE_POLL BIT(16) BIT 169 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define RXDMA_IDLE BIT(17) BIT 170 drivers/staging/rtl8723bs/include/rtl8723b_spec.h #define RW_RELEASE_EN BIT(18) BIT 27 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define BMC BIT(24) BIT 28 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define LSG BIT(26) BIT 29 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define FSG BIT(27) BIT 30 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define OWN BIT(31) BIT 35 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define BK BIT(6) BIT 38 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define NAVUSEHDR BIT(20) BIT 40 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define HWPC BIT(31) BIT 43 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define AGG_EN BIT(29) BIT 49 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define QoS BIT(6) BIT 50 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define HW_SEQ_EN BIT(7) BIT 51 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define USERATE BIT(8) BIT 52 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define DISDATAFB BIT(10) BIT 53 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define DATA_SHORT BIT(24) BIT 54 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define DATA_BW BIT(25) BIT 57 drivers/staging/rtl8723bs/include/rtl8723b_xmit.h #define SGI BIT(6) BIT 24 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_xmit_c_ BIT(0) BIT 25 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_xmit_osdep_c_ BIT(1) BIT 26 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_recv_c_ BIT(2) BIT 27 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_recv_osdep_c_ BIT(3) BIT 28 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_mlme_c_ BIT(4) BIT 29 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_mlme_osdep_c_ BIT(5) BIT 30 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_sta_mgt_c_ BIT(6) BIT 31 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_cmd_c_ BIT(7) BIT 32 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_cmd_osdep_c_ BIT(8) BIT 33 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_io_c_ BIT(9) BIT 34 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_io_osdep_c_ BIT(10) BIT 35 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_os_intfs_c_ BIT(11) BIT 36 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_security_c_ BIT(12) BIT 37 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_eeprom_c_ BIT(13) BIT 38 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_hal_init_c_ BIT(14) BIT 39 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_hci_hal_init_c_ BIT(15) BIT 40 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_ioctl_c_ BIT(16) BIT 41 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_ioctl_set_c_ BIT(17) BIT 42 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_ioctl_query_c_ BIT(18) BIT 43 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_pwrctrl_c_ BIT(19) BIT 44 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_hci_intfs_c_ BIT(20) BIT 45 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_hci_ops_c_ BIT(21) BIT 46 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_osdep_service_c_ BIT(22) BIT 47 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_mp_ BIT(23) BIT 48 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_hci_ops_os_c_ BIT(24) BIT 49 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl871x_ioctl_os_c BIT(25) BIT 50 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl8712_cmd_c_ BIT(26) BIT 52 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl8192c_xmit_c_ BIT(28) BIT 53 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_hal_xmit_c_ BIT(28) BIT 54 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_efuse_ BIT(29) BIT 55 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl8712_recv_c_ BIT(30) BIT 56 drivers/staging/rtl8723bs/include/rtw_debug.h #define _module_rtl8712_led_c_ BIT(31) BIT 21 drivers/staging/rtl8723bs/include/rtw_io.h #define _IO_WRITE_ BIT(7) BIT 22 drivers/staging/rtl8723bs/include/rtw_io.h #define _IO_FIXED_ BIT(8) BIT 23 drivers/staging/rtl8723bs/include/rtw_io.h #define _IO_BURST_ BIT(9) BIT 24 drivers/staging/rtl8723bs/include/rtw_io.h #define _IO_BYTE_ BIT(10) BIT 25 drivers/staging/rtl8723bs/include/rtw_io.h #define _IO_HW_ BIT(11) BIT 26 drivers/staging/rtl8723bs/include/rtw_io.h #define _IO_WORD_ BIT(12) BIT 27 drivers/staging/rtl8723bs/include/rtw_io.h #define _IO_SYNC_ BIT(13) BIT 39 drivers/staging/rtl8723bs/include/rtw_io.h #define _IO_ERR_ BIT(2) BIT 40 drivers/staging/rtl8723bs/include/rtw_io.h #define _IO_SUCCESS_ BIT(1) BIT 41 drivers/staging/rtl8723bs/include/rtw_io.h #define _IO_DONE_ BIT(0) BIT 73 drivers/staging/rtl8723bs/include/rtw_io.h #define _INTF_ASYNC_ BIT(0) /* support async io */ BIT 27 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define XMIT_ALIVE BIT(0) BIT 28 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RECV_ALIVE BIT(1) BIT 29 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define CMD_ALIVE BIT(2) BIT 30 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define EVT_ALIVE BIT(3) BIT 31 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define BTCOEX_ALIVE BIT(4) BIT 60 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define PS_DPS BIT(0) BIT 62 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define PS_RF_OFF BIT(1) BIT 63 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define PS_ALL_ON BIT(2) BIT 64 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define PS_ST_ACTIVE BIT(3) BIT 66 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define PS_ISR_ENABLE BIT(4) BIT 67 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define PS_IMR_ENABLE BIT(5) BIT 68 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define PS_ACK BIT(6) BIT 69 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define PS_TOGGLE BIT(7) BIT 113 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_ASPM BIT(0) /* PCI ASPM */ BIT 114 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /* PCI clock request */ BIT 115 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /* PCI D3 mode */ BIT 116 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) /* NIC halt, re-initialize hw parameters */ BIT 117 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /* FW free, re-download the FW */ BIT 118 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_RF_OFF_LEVL_FW_32K BIT(5) /* FW in 32k */ BIT 119 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) /* Always enable ASPM and Clock Req in initialization. */ BIT 120 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_RF_LPS_DISALBE_2R BIT(30) /* When LPS is on, disable 2R if no packet is received or transmittd. */ BIT 121 drivers/staging/rtl8723bs/include/rtw_pwrctrl.h #define RT_RF_LPS_LEVEL_ASPM BIT(31) /* LPS with ASPM */ BIT 212 drivers/staging/rtl8723bs/include/rtw_recv.h #define EOR BIT(30) BIT 57 drivers/staging/rtl8723bs/include/rtw_xmit.h pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ BIT 70 drivers/staging/rtl8723bs/include/rtw_xmit.h pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ BIT 11 drivers/staging/rtl8723bs/include/wifi.h #ifdef BIT BIT 48 drivers/staging/rtl8723bs/include/wifi.h WIFI_CTRL_TYPE = (BIT(2)), BIT 49 drivers/staging/rtl8723bs/include/wifi.h WIFI_DATA_TYPE = (BIT(3)), BIT 50 drivers/staging/rtl8723bs/include/wifi.h WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), /* QoS Data */ BIT 57 drivers/staging/rtl8723bs/include/wifi.h WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE), BIT 58 drivers/staging/rtl8723bs/include/wifi.h WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE), BIT 59 drivers/staging/rtl8723bs/include/wifi.h WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE), BIT 60 drivers/staging/rtl8723bs/include/wifi.h WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE), BIT 61 drivers/staging/rtl8723bs/include/wifi.h WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE), BIT 62 drivers/staging/rtl8723bs/include/wifi.h WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE), BIT 63 drivers/staging/rtl8723bs/include/wifi.h WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE), BIT 64 drivers/staging/rtl8723bs/include/wifi.h WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE), BIT 65 drivers/staging/rtl8723bs/include/wifi.h WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE), BIT 66 drivers/staging/rtl8723bs/include/wifi.h WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE), BIT 67 drivers/staging/rtl8723bs/include/wifi.h WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE), BIT 68 drivers/staging/rtl8723bs/include/wifi.h WIFI_ACTION_NOACK = (BIT(7) | BIT(6) | BIT(5) | WIFI_MGT_TYPE), BIT 71 drivers/staging/rtl8723bs/include/wifi.h WIFI_NDPA = (BIT(6) | BIT(4) | WIFI_CTRL_TYPE), BIT 72 drivers/staging/rtl8723bs/include/wifi.h WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), BIT 73 drivers/staging/rtl8723bs/include/wifi.h WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), BIT 74 drivers/staging/rtl8723bs/include/wifi.h WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), BIT 75 drivers/staging/rtl8723bs/include/wifi.h WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE), BIT 76 drivers/staging/rtl8723bs/include/wifi.h WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE), BIT 77 drivers/staging/rtl8723bs/include/wifi.h WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), BIT 81 drivers/staging/rtl8723bs/include/wifi.h WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE), BIT 82 drivers/staging/rtl8723bs/include/wifi.h WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE), BIT 83 drivers/staging/rtl8723bs/include/wifi.h WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE), BIT 84 drivers/staging/rtl8723bs/include/wifi.h WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE), BIT 85 drivers/staging/rtl8723bs/include/wifi.h WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE), BIT 86 drivers/staging/rtl8723bs/include/wifi.h WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE), BIT 87 drivers/staging/rtl8723bs/include/wifi.h WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE), BIT 88 drivers/staging/rtl8723bs/include/wifi.h WIFI_QOS_DATA_NULL = (BIT(6) | WIFI_QOS_DATA_TYPE), BIT 192 drivers/staging/rtl8723bs/include/wifi.h #define _TO_DS_ BIT(8) BIT 193 drivers/staging/rtl8723bs/include/wifi.h #define _FROM_DS_ BIT(9) BIT 194 drivers/staging/rtl8723bs/include/wifi.h #define _MORE_FRAG_ BIT(10) BIT 195 drivers/staging/rtl8723bs/include/wifi.h #define _RETRY_ BIT(11) BIT 196 drivers/staging/rtl8723bs/include/wifi.h #define _PWRMGT_ BIT(12) BIT 197 drivers/staging/rtl8723bs/include/wifi.h #define _MORE_DATA_ BIT(13) BIT 198 drivers/staging/rtl8723bs/include/wifi.h #define _PRIVACY_ BIT(14) BIT 199 drivers/staging/rtl8723bs/include/wifi.h #define _ORDER_ BIT(15) BIT 265 drivers/staging/rtl8723bs/include/wifi.h (le16_to_cpu(*(__le16 *)(pbuf)) & (BIT(3) | BIT(2))) BIT 269 drivers/staging/rtl8723bs/include/wifi.h *(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(3) | BIT(2))); \ BIT 273 drivers/staging/rtl8723bs/include/wifi.h #define GetFrameSubType(pbuf) (le16_to_cpu(*(__le16 *)(pbuf)) & (BIT(7) |\ BIT 274 drivers/staging/rtl8723bs/include/wifi.h BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))) BIT 278 drivers/staging/rtl8723bs/include/wifi.h *(__le16 *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | \ BIT 279 drivers/staging/rtl8723bs/include/wifi.h BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ BIT 606 drivers/staging/rtl8723bs/include/wifi.h #define cap_ESS BIT(0) BIT 607 drivers/staging/rtl8723bs/include/wifi.h #define cap_IBSS BIT(1) BIT 608 drivers/staging/rtl8723bs/include/wifi.h #define cap_CFPollable BIT(2) BIT 609 drivers/staging/rtl8723bs/include/wifi.h #define cap_CFRequest BIT(3) BIT 610 drivers/staging/rtl8723bs/include/wifi.h #define cap_Privacy BIT(4) BIT 611 drivers/staging/rtl8723bs/include/wifi.h #define cap_ShortPremble BIT(5) BIT 612 drivers/staging/rtl8723bs/include/wifi.h #define cap_PBCC BIT(6) BIT 613 drivers/staging/rtl8723bs/include/wifi.h #define cap_ChAgility BIT(7) BIT 614 drivers/staging/rtl8723bs/include/wifi.h #define cap_SpecMgmt BIT(8) BIT 615 drivers/staging/rtl8723bs/include/wifi.h #define cap_QoS BIT(9) BIT 616 drivers/staging/rtl8723bs/include/wifi.h #define cap_ShortSlot BIT(10) BIT 816 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8) BIT(0) | BIT(1)) BIT 817 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8) BIT(0)) BIT 818 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8) BIT(0) | BIT(1)) BIT 819 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8) BIT(2)) BIT 820 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_HT_PARAM_RIFS_MODE ((u8) BIT(3)) BIT 821 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8) BIT(4)) BIT 822 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8) BIT(5)) BIT 827 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8) BIT(2)) BIT 828 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8) BIT(3)) BIT 829 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8) BIT(4)) BIT 831 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16) BIT(6)) BIT 832 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16) BIT(7)) BIT 833 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_STBC_PARAM_SECONDARY_BCN ((u16) BIT(8)) BIT 834 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16) BIT(9)) BIT 835 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16) BIT(10)) BIT 836 drivers/staging/rtl8723bs/include/wifi.h #define HT_INFO_STBC_PARAM_PCO_PHASE ((u16) BIT(11)) BIT 971 drivers/staging/rtl8723bs/include/wifi.h #define P2P_INVITATION_FLAGS_PERSISTENT BIT(0) BIT 981 drivers/staging/rtl8723bs/include/wifi.h #define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0) BIT 982 drivers/staging/rtl8723bs/include/wifi.h #define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1) BIT 983 drivers/staging/rtl8723bs/include/wifi.h #define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2) BIT 984 drivers/staging/rtl8723bs/include/wifi.h #define P2P_DEVCAP_INFRA_MANAGED BIT(3) BIT 985 drivers/staging/rtl8723bs/include/wifi.h #define P2P_DEVCAP_DEVICE_LIMIT BIT(4) BIT 986 drivers/staging/rtl8723bs/include/wifi.h #define P2P_DEVCAP_INVITATION_PROC BIT(5) BIT 989 drivers/staging/rtl8723bs/include/wifi.h #define P2P_GRPCAP_GO BIT(0) BIT 990 drivers/staging/rtl8723bs/include/wifi.h #define P2P_GRPCAP_PERSISTENT_GROUP BIT(1) BIT 991 drivers/staging/rtl8723bs/include/wifi.h #define P2P_GRPCAP_GROUP_LIMIT BIT(2) BIT 992 drivers/staging/rtl8723bs/include/wifi.h #define P2P_GRPCAP_INTRABSS BIT(3) BIT 993 drivers/staging/rtl8723bs/include/wifi.h #define P2P_GRPCAP_CROSS_CONN BIT(4) BIT 994 drivers/staging/rtl8723bs/include/wifi.h #define P2P_GRPCAP_PERSISTENT_RECONN BIT(5) BIT 995 drivers/staging/rtl8723bs/include/wifi.h #define P2P_GRPCAP_GROUP_FORMATION BIT(6) BIT 175 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) BIT 179 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 180 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 184 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 185 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 186 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 187 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 188 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 189 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 190 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_ACTION >> 4) BIT 195 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 196 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 197 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 198 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 199 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 200 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 201 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_ACTION >> 4) BIT 205 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 206 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 210 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 211 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 212 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 213 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 214 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 215 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 216 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c BIT(IEEE80211_STYPE_ACTION >> 4) BIT 3160 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c if (pwdev_priv->invit_info.flags & BIT(0) BIT 3342 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) BIT 3343 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c | BIT(NL80211_IFTYPE_ADHOC) BIT 3344 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c | BIT(NL80211_IFTYPE_AP) BIT 3345 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c | BIT(NL80211_IFTYPE_MONITOR) BIT 3350 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR); BIT 3067 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c mcs_bitmap |= BIT(i); BIT 1310 drivers/staging/rts5208/rtsx_chip.c if ((val & BIT(31)) == 0) { BIT 1335 drivers/staging/rts5208/rtsx_chip.c if ((val & BIT(31)) == 0) BIT 261 drivers/staging/rts5208/rtsx_chip.h #define CMD_DONE_INT BIT(31) BIT 262 drivers/staging/rts5208/rtsx_chip.h #define DATA_DONE_INT BIT(30) BIT 263 drivers/staging/rts5208/rtsx_chip.h #define TRANS_OK_INT BIT(29) BIT 264 drivers/staging/rts5208/rtsx_chip.h #define TRANS_FAIL_INT BIT(28) BIT 265 drivers/staging/rts5208/rtsx_chip.h #define XD_INT BIT(27) BIT 266 drivers/staging/rts5208/rtsx_chip.h #define MS_INT BIT(26) BIT 267 drivers/staging/rts5208/rtsx_chip.h #define SD_INT BIT(25) BIT 268 drivers/staging/rts5208/rtsx_chip.h #define GPIO0_INT BIT(24) BIT 269 drivers/staging/rts5208/rtsx_chip.h #define OC_INT BIT(23) BIT 270 drivers/staging/rts5208/rtsx_chip.h #define SD_WRITE_PROTECT BIT(19) BIT 271 drivers/staging/rts5208/rtsx_chip.h #define XD_EXIST BIT(18) BIT 272 drivers/staging/rts5208/rtsx_chip.h #define MS_EXIST BIT(17) BIT 273 drivers/staging/rts5208/rtsx_chip.h #define SD_EXIST BIT(16) BIT 275 drivers/staging/rts5208/rtsx_chip.h #define MS_OC_INT BIT(23) BIT 276 drivers/staging/rts5208/rtsx_chip.h #define SD_OC_INT BIT(22) BIT 286 drivers/staging/rts5208/rtsx_chip.h #define CMD_DONE_INT_EN BIT(31) BIT 287 drivers/staging/rts5208/rtsx_chip.h #define DATA_DONE_INT_EN BIT(30) BIT 288 drivers/staging/rts5208/rtsx_chip.h #define TRANS_OK_INT_EN BIT(29) BIT 289 drivers/staging/rts5208/rtsx_chip.h #define TRANS_FAIL_INT_EN BIT(28) BIT 290 drivers/staging/rts5208/rtsx_chip.h #define XD_INT_EN BIT(27) BIT 291 drivers/staging/rts5208/rtsx_chip.h #define MS_INT_EN BIT(26) BIT 292 drivers/staging/rts5208/rtsx_chip.h #define SD_INT_EN BIT(25) BIT 293 drivers/staging/rts5208/rtsx_chip.h #define GPIO0_INT_EN BIT(24) BIT 294 drivers/staging/rts5208/rtsx_chip.h #define OC_INT_EN BIT(23) BIT 296 drivers/staging/rts5208/rtsx_chip.h #define MS_OC_INT_EN BIT(23) BIT 297 drivers/staging/rts5208/rtsx_chip.h #define SD_OC_INT_EN BIT(22) BIT 314 drivers/staging/rts5208/rtsx_chip.h #define SD_CARD BIT(SD_NR) BIT 315 drivers/staging/rts5208/rtsx_chip.h #define MS_CARD BIT(MS_NR) BIT 316 drivers/staging/rts5208/rtsx_chip.h #define XD_CARD BIT(XD_NR) BIT 317 drivers/staging/rts5208/rtsx_chip.h #define SPI_CARD BIT(SPI_NR) BIT 215 drivers/staging/rts5208/rtsx_transport.c u32 val = BIT(31); BIT 229 drivers/staging/rts5208/rtsx_transport.c u32 val = BIT(31); BIT 635 drivers/staging/rts5208/rtsx_transport.c u32 val = BIT(31); BIT 48 drivers/staging/sm750fb/ddk750_chip.c return DEFAULT_INPUT_CLOCK * M / N / BIT(OD) / BIT(POD); BIT 360 drivers/staging/sm750fb/ddk750_chip.c X = BIT(d); BIT 22 drivers/staging/sm750fb/ddk750_display.h #define PRI_TP_MASK BIT(PRI_TP_OFFSET) BIT 32 drivers/staging/sm750fb/ddk750_display.h #define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET) BIT 34 drivers/staging/sm750fb/ddk750_display.h #define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) | PNL_SEQ_USAGE) BIT 42 drivers/staging/sm750fb/ddk750_display.h #define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET) BIT 44 drivers/staging/sm750fb/ddk750_display.h #define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) | DUAL_TFT_USAGE) BIT 53 drivers/staging/sm750fb/ddk750_display.h #define SEC_TP_MASK BIT(SEC_TP_OFFSET) BIT 73 drivers/staging/sm750fb/ddk750_display.h #define DAC_MASK BIT(DAC_OFFSET) BIT 7 drivers/staging/sm750fb/ddk750_reg.h #define DE_STATE1_DE_ABORT BIT(0) BIT 10 drivers/staging/sm750fb/ddk750_reg.h #define DE_STATE2_DE_FIFO_EMPTY BIT(3) BIT 11 drivers/staging/sm750fb/ddk750_reg.h #define DE_STATE2_DE_STATUS_BUSY BIT(2) BIT 12 drivers/staging/sm750fb/ddk750_reg.h #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1) BIT 20 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_PCI_BURST BIT(29) BIT 21 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_PCI_MASTER BIT(25) BIT 22 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24) BIT 23 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23) BIT 24 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22) BIT 25 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21) BIT 26 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_CSC_STATUS_BUSY BIT(20) BIT 27 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_CRT_VSYNC_ACTIVE BIT(19) BIT 28 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE BIT(18) BIT 29 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING BIT(17) BIT 30 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_DMA_STATUS_BUSY BIT(16) BIT 31 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_PCI_BURST_READ BIT(15) BIT 32 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_DE_ABORT BIT(13) BIT 33 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK BIT(11) BIT 34 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_PCI_RETRY_OFF BIT(7) BIT 40 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_CRT_TRISTATE BIT(3) BIT 41 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_PCIMEM_TRISTATE BIT(2) BIT 42 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_LOCALMEM_TRISTATE BIT(1) BIT 43 drivers/staging/sm750fb/ddk750_reg.h #define SYSTEM_CTRL_PANEL_TRISTATE BIT(0) BIT 46 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_DRAM_RERESH_COUNT BIT(27) BIT 52 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_INT_OUTPUT_INVERT BIT(24) BIT 53 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_PLL_CLK_COUNT BIT(23) BIT 54 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_DAC_POWER_OFF BIT(20) BIT 55 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_CLK_SELECT_TESTCLK BIT(16) BIT 65 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_DRAM_TWTR BIT(11) BIT 66 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_DRAM_TWR BIT(10) BIT 67 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_DRAM_TRP BIT(9) BIT 68 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_DRAM_TRFC BIT(8) BIT 69 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_DRAM_TRAS BIT(7) BIT 70 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_LOCALMEM_RESET BIT(6) BIT 71 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_LOCALMEM_STATE_INACTIVE BIT(5) BIT 72 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_CPU_CAS_LATENCY BIT(4) BIT 73 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_DLL_OFF BIT(3) BIT 74 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_DRAM_OUTPUT_HIGH BIT(2) BIT 75 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_LOCALMEM_BUS_SIZE BIT(1) BIT 76 drivers/staging/sm750fb/ddk750_reg.h #define MISC_CTRL_EMBEDDED_LOCALMEM_OFF BIT(0) BIT 79 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_31 BIT(31) BIT 80 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_30 BIT(30) BIT 81 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_29 BIT(29) BIT 82 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_28 BIT(28) BIT 83 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_27 BIT(27) BIT 84 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_26 BIT(26) BIT 85 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_25 BIT(25) BIT 86 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_24 BIT(24) BIT 87 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_23 BIT(23) BIT 88 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_22 BIT(22) BIT 89 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_21 BIT(21) BIT 90 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_20 BIT(20) BIT 91 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_19 BIT(19) BIT 92 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_18 BIT(18) BIT 93 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_17 BIT(17) BIT 94 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_16 BIT(16) BIT 95 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_15 BIT(15) BIT 96 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_14 BIT(14) BIT 97 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_13 BIT(13) BIT 98 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_12 BIT(12) BIT 99 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_11 BIT(11) BIT 100 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_10 BIT(10) BIT 101 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_9 BIT(9) BIT 102 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_8 BIT(8) BIT 103 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_7 BIT(7) BIT 104 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_6 BIT(6) BIT 105 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_5 BIT(5) BIT 106 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_4 BIT(4) BIT 107 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_3 BIT(3) BIT 108 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_2 BIT(2) BIT 109 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_1 BIT(1) BIT 110 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_MUX_0 BIT(0) BIT 113 drivers/staging/sm750fb/ddk750_reg.h #define LOCALMEM_ARBITRATION_ROTATE BIT(28) BIT 179 drivers/staging/sm750fb/ddk750_reg.h #define PCIMEM_ARBITRATION_ROTATE BIT(28) BIT 245 drivers/staging/sm750fb/ddk750_reg.h #define RAW_INT_ZVPORT1_VSYNC BIT(4) BIT 246 drivers/staging/sm750fb/ddk750_reg.h #define RAW_INT_ZVPORT0_VSYNC BIT(3) BIT 247 drivers/staging/sm750fb/ddk750_reg.h #define RAW_INT_CRT_VSYNC BIT(2) BIT 248 drivers/staging/sm750fb/ddk750_reg.h #define RAW_INT_PANEL_VSYNC BIT(1) BIT 249 drivers/staging/sm750fb/ddk750_reg.h #define RAW_INT_VGA_VSYNC BIT(0) BIT 252 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_GPIO31 BIT(31) BIT 253 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_GPIO30 BIT(30) BIT 254 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_GPIO29 BIT(29) BIT 255 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_GPIO28 BIT(28) BIT 256 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_GPIO27 BIT(27) BIT 257 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_GPIO26 BIT(26) BIT 258 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_GPIO25 BIT(25) BIT 259 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_I2C BIT(12) BIT 260 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_PWM BIT(11) BIT 261 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_DMA1 BIT(10) BIT 262 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_DMA0 BIT(9) BIT 263 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_PCI BIT(8) BIT 264 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_SSP1 BIT(7) BIT 265 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_SSP0 BIT(6) BIT 266 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_DE BIT(5) BIT 267 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_ZVPORT1_VSYNC BIT(4) BIT 268 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_ZVPORT0_VSYNC BIT(3) BIT 269 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_CRT_VSYNC BIT(2) BIT 270 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_PANEL_VSYNC BIT(1) BIT 271 drivers/staging/sm750fb/ddk750_reg.h #define INT_STATUS_VGA_VSYNC BIT(0) BIT 274 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_GPIO31 BIT(31) BIT 275 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_GPIO30 BIT(30) BIT 276 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_GPIO29 BIT(29) BIT 277 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_GPIO28 BIT(28) BIT 278 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_GPIO27 BIT(27) BIT 279 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_GPIO26 BIT(26) BIT 280 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_GPIO25 BIT(25) BIT 281 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_I2C BIT(12) BIT 282 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_PWM BIT(11) BIT 283 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_DMA1 BIT(10) BIT 284 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_DMA BIT(9) BIT 285 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_PCI BIT(8) BIT 286 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_SSP1 BIT(7) BIT 287 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_SSP0 BIT(6) BIT 288 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_DE BIT(5) BIT 289 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_ZVPORT1_VSYNC BIT(4) BIT 290 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_ZVPORT0_VSYNC BIT(3) BIT 291 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_CRT_VSYNC BIT(2) BIT 292 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_PANEL_VSYNC BIT(1) BIT 293 drivers/staging/sm750fb/ddk750_reg.h #define INT_MASK_VGA_VSYNC BIT(0) BIT 320 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_VGA BIT(10) BIT 321 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_PWM BIT(9) BIT 322 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_I2C BIT(8) BIT 323 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_SSP BIT(7) BIT 324 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_GPIO BIT(6) BIT 325 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_ZVPORT BIT(5) BIT 326 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_CSC BIT(4) BIT 327 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_DE BIT(3) BIT 328 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_DISPLAY BIT(2) BIT 329 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_LOCALMEM BIT(1) BIT 330 drivers/staging/sm750fb/ddk750_reg.h #define CURRENT_GATE_DMA BIT(0) BIT 343 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_VGA BIT(10) BIT 344 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_PWM BIT(9) BIT 345 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_I2C BIT(8) BIT 346 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_SSP BIT(7) BIT 347 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_GPIO BIT(6) BIT 348 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_ZVPORT BIT(5) BIT 349 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_CSC BIT(4) BIT 350 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_DE BIT(3) BIT 351 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_DISPLAY BIT(2) BIT 352 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_LOCALMEM BIT(1) BIT 353 drivers/staging/sm750fb/ddk750_reg.h #define MODE0_GATE_DMA BIT(0) BIT 366 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_VGA BIT(10) BIT 367 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_PWM BIT(9) BIT 368 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_I2C BIT(8) BIT 369 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_SSP BIT(7) BIT 370 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_GPIO BIT(6) BIT 371 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_ZVPORT BIT(5) BIT 372 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_CSC BIT(4) BIT 373 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_DE BIT(3) BIT 374 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_DISPLAY BIT(2) BIT 375 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_LOCALMEM BIT(1) BIT 376 drivers/staging/sm750fb/ddk750_reg.h #define MODE1_GATE_DMA BIT(0) BIT 380 drivers/staging/sm750fb/ddk750_reg.h #define POWER_MODE_CTRL_336CLK BIT(4) BIT 382 drivers/staging/sm750fb/ddk750_reg.h #define POWER_MODE_CTRL_OSC_INPUT BIT(3) BIT 383 drivers/staging/sm750fb/ddk750_reg.h #define POWER_MODE_CTRL_ACPI BIT(2) BIT 400 drivers/staging/sm750fb/ddk750_reg.h #define PLL_CTRL_BYPASS BIT(18) BIT 401 drivers/staging/sm750fb/ddk750_reg.h #define PLL_CTRL_POWER BIT(17) BIT 402 drivers/staging/sm750fb/ddk750_reg.h #define PLL_CTRL_INPUT BIT(16) BIT 431 drivers/staging/sm750fb/ddk750_reg.h #define VGA_CONFIGURATION_PLL BIT(2) BIT 432 drivers/staging/sm750fb/ddk750_reg.h #define VGA_CONFIGURATION_MODE BIT(1) BIT 437 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_31 BIT(31) BIT 438 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_30 BIT(30) BIT 439 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_29 BIT(29) BIT 440 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_28 BIT(28) BIT 441 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_27 BIT(27) BIT 442 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_26 BIT(26) BIT 443 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_25 BIT(25) BIT 444 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_24 BIT(24) BIT 445 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_23 BIT(23) BIT 446 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_22 BIT(22) BIT 447 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_21 BIT(21) BIT 448 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_20 BIT(20) BIT 449 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_19 BIT(19) BIT 450 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_18 BIT(18) BIT 451 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_17 BIT(17) BIT 452 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_16 BIT(16) BIT 453 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_15 BIT(15) BIT 454 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_14 BIT(14) BIT 455 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_13 BIT(13) BIT 456 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_12 BIT(12) BIT 457 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_11 BIT(11) BIT 458 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_10 BIT(10) BIT 459 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_9 BIT(9) BIT 460 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_8 BIT(8) BIT 461 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_7 BIT(7) BIT 462 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_6 BIT(6) BIT 463 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_5 BIT(5) BIT 464 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_4 BIT(4) BIT 465 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_3 BIT(3) BIT 466 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_2 BIT(2) BIT 467 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_1 BIT(1) BIT 468 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_0 BIT(0) BIT 471 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_31 BIT(31) BIT 472 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_30 BIT(30) BIT 473 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_29 BIT(29) BIT 474 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_28 BIT(28) BIT 475 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_27 BIT(27) BIT 476 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_26 BIT(26) BIT 477 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_25 BIT(25) BIT 478 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_24 BIT(24) BIT 479 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_23 BIT(23) BIT 480 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_22 BIT(22) BIT 481 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_21 BIT(21) BIT 482 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_20 BIT(20) BIT 483 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_19 BIT(19) BIT 484 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_18 BIT(18) BIT 485 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_17 BIT(17) BIT 486 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_16 BIT(16) BIT 487 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_15 BIT(15) BIT 488 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_14 BIT(14) BIT 489 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_13 BIT(13) BIT 490 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_12 BIT(12) BIT 491 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_11 BIT(11) BIT 492 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_10 BIT(10) BIT 493 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_9 BIT(9) BIT 494 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_8 BIT(8) BIT 495 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_7 BIT(7) BIT 496 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_6 BIT(6) BIT 497 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_5 BIT(5) BIT 498 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_4 BIT(4) BIT 499 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_3 BIT(3) BIT 500 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_2 BIT(2) BIT 501 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_1 BIT(1) BIT 502 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_0 BIT(0) BIT 505 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_TRIGGER_31 BIT(22) BIT 506 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_TRIGGER_30 BIT(21) BIT 507 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_TRIGGER_29 BIT(20) BIT 508 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_TRIGGER_28 BIT(19) BIT 509 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_TRIGGER_27 BIT(18) BIT 510 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_TRIGGER_26 BIT(17) BIT 511 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_TRIGGER_25 BIT(16) BIT 512 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ACTIVE_31 BIT(14) BIT 513 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ACTIVE_30 BIT(13) BIT 514 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ACTIVE_29 BIT(12) BIT 515 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ACTIVE_28 BIT(11) BIT 516 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ACTIVE_27 BIT(10) BIT 517 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ACTIVE_26 BIT(9) BIT 518 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ACTIVE_25 BIT(8) BIT 519 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ENABLE_31 BIT(6) BIT 520 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ENABLE_30 BIT(5) BIT 521 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ENABLE_29 BIT(4) BIT 522 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ENABLE_28 BIT(3) BIT 523 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ENABLE_27 BIT(2) BIT 524 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ENABLE_26 BIT(1) BIT 525 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_SETUP_ENABLE_25 BIT(0) BIT 528 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_STATUS_31 BIT(22) BIT 529 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_STATUS_30 BIT(21) BIT 530 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_STATUS_29 BIT(20) BIT 531 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_STATUS_28 BIT(19) BIT 532 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_STATUS_27 BIT(18) BIT 533 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_STATUS_26 BIT(17) BIT 534 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_INTERRUPT_STATUS_25 BIT(16) BIT 543 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_FPEN BIT(27) BIT 544 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_VBIASEN BIT(26) BIT 545 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_DATA BIT(25) BIT 546 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_FPVDDEN BIT(24) BIT 547 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_DUAL_DISPLAY BIT(19) BIT 548 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL BIT(18) BIT 554 drivers/staging/sm750fb/ddk750_reg.h #define DISPLAY_CTRL_CLOCK_PHASE BIT(14) BIT 555 drivers/staging/sm750fb/ddk750_reg.h #define DISPLAY_CTRL_VSYNC_PHASE BIT(13) BIT 556 drivers/staging/sm750fb/ddk750_reg.h #define DISPLAY_CTRL_HSYNC_PHASE BIT(12) BIT 557 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_VSYNC BIT(11) BIT 558 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_CAPTURE_TIMING BIT(10) BIT 559 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_COLOR_KEY BIT(9) BIT 560 drivers/staging/sm750fb/ddk750_reg.h #define DISPLAY_CTRL_TIMING BIT(8) BIT 561 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR BIT(7) BIT 562 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_VERTICAL_PAN BIT(6) BIT 563 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR BIT(5) BIT 564 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN BIT(4) BIT 565 drivers/staging/sm750fb/ddk750_reg.h #define DISPLAY_CTRL_GAMMA BIT(3) BIT 566 drivers/staging/sm750fb/ddk750_reg.h #define DISPLAY_CTRL_PLANE BIT(2) BIT 583 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_FB_ADDRESS_STATUS BIT(31) BIT 584 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_FB_ADDRESS_EXT BIT(27) BIT 638 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_DISPLAY_CTRL_LINE_BUFFER BIT(18) BIT 644 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_DISPLAY_CTRL_BUFFER BIT(15) BIT 645 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_DISPLAY_CTRL_CAPTURE BIT(14) BIT 646 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER BIT(13) BIT 647 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_DISPLAY_CTRL_BYTE_SWAP BIT(12) BIT 648 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE BIT(11) BIT 649 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE BIT(10) BIT 650 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE BIT(9) BIT 651 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE BIT(8) BIT 653 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_DISPLAY_CTRL_GAMMA BIT(3) BIT 661 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_FB_0_ADDRESS_STATUS BIT(31) BIT 662 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_FB_0_ADDRESS_EXT BIT(27) BIT 670 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_FB_0_LAST_ADDRESS_EXT BIT(27) BIT 682 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_SCALE_VERTICAL_MODE BIT(31) BIT 684 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_SCALE_HORIZONTAL_MODE BIT(15) BIT 698 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_FB_1_ADDRESS_STATUS BIT(31) BIT 699 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_FB_1_ADDRESS_EXT BIT(27) BIT 703 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_FB_1_LAST_ADDRESS_EXT BIT(27) BIT 709 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT BIT(28) BIT 716 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE BIT(11) BIT 717 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE BIT(10) BIT 718 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE BIT(9) BIT 719 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE BIT(8) BIT 721 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY BIT(3) BIT 729 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_FB_ADDRESS_STATUS BIT(31) BIT 730 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_FB_ADDRESS_EXT BIT(27) BIT 738 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT BIT(27) BIT 750 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_SCALE_VERTICAL_MODE BIT(31) BIT 752 drivers/staging/sm750fb/ddk750_reg.h #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE BIT(15) BIT 846 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_HWC_ADDRESS_ENABLE BIT(31) BIT 847 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_HWC_ADDRESS_EXT BIT(27) BIT 851 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_HWC_LOCATION_TOP BIT(27) BIT 853 drivers/staging/sm750fb/ddk750_reg.h #define PANEL_HWC_LOCATION_LEFT BIT(11) BIT 881 drivers/staging/sm750fb/ddk750_reg.h #define ALPHA_DISPLAY_CTRL_SELECT BIT(28) BIT 889 drivers/staging/sm750fb/ddk750_reg.h #define ALPHA_DISPLAY_CTRL_CHROMA_KEY BIT(3) BIT 896 drivers/staging/sm750fb/ddk750_reg.h #define ALPHA_FB_ADDRESS_STATUS BIT(31) BIT 897 drivers/staging/sm750fb/ddk750_reg.h #define ALPHA_FB_ADDRESS_EXT BIT(27) BIT 1017 drivers/staging/sm750fb/ddk750_reg.h #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC BIT(26) BIT 1020 drivers/staging/sm750fb/ddk750_reg.h #define CRT_DISPLAY_CTRL_CRTSELECT BIT(25) BIT 1021 drivers/staging/sm750fb/ddk750_reg.h #define CRT_DISPLAY_CTRL_RGBBIT BIT(24) BIT 1024 drivers/staging/sm750fb/ddk750_reg.h #define CRT_DISPLAY_CTRL_CENTERING BIT(24) BIT 1026 drivers/staging/sm750fb/ddk750_reg.h #define CRT_DISPLAY_CTRL_LOCK_TIMING BIT(23) BIT 1027 drivers/staging/sm750fb/ddk750_reg.h #define CRT_DISPLAY_CTRL_EXPANSION BIT(22) BIT 1028 drivers/staging/sm750fb/ddk750_reg.h #define CRT_DISPLAY_CTRL_VERTICAL_MODE BIT(21) BIT 1029 drivers/staging/sm750fb/ddk750_reg.h #define CRT_DISPLAY_CTRL_HORIZONTAL_MODE BIT(20) BIT 1040 drivers/staging/sm750fb/ddk750_reg.h #define CRT_DISPLAY_CTRL_BLANK BIT(10) BIT 1048 drivers/staging/sm750fb/ddk750_reg.h #define CRT_FB_ADDRESS_STATUS BIT(31) BIT 1049 drivers/staging/sm750fb/ddk750_reg.h #define CRT_FB_ADDRESS_EXT BIT(27) BIT 1079 drivers/staging/sm750fb/ddk750_reg.h #define CRT_SIGNATURE_ANALYZER_ENABLE BIT(3) BIT 1080 drivers/staging/sm750fb/ddk750_reg.h #define CRT_SIGNATURE_ANALYZER_RESET BIT(2) BIT 1090 drivers/staging/sm750fb/ddk750_reg.h #define CRT_MONITOR_DETECT_VALUE BIT(25) BIT 1091 drivers/staging/sm750fb/ddk750_reg.h #define CRT_MONITOR_DETECT_ENABLE BIT(24) BIT 1097 drivers/staging/sm750fb/ddk750_reg.h #define CRT_SCALE_VERTICAL_MODE BIT(31) BIT 1099 drivers/staging/sm750fb/ddk750_reg.h #define CRT_SCALE_HORIZONTAL_MODE BIT(15) BIT 1105 drivers/staging/sm750fb/ddk750_reg.h #define CRT_HWC_ADDRESS_ENABLE BIT(31) BIT 1106 drivers/staging/sm750fb/ddk750_reg.h #define CRT_HWC_ADDRESS_EXT BIT(27) BIT 1110 drivers/staging/sm750fb/ddk750_reg.h #define CRT_HWC_LOCATION_TOP BIT(27) BIT 1112 drivers/staging/sm750fb/ddk750_reg.h #define CRT_HWC_LOCATION_LEFT BIT(11) BIT 1164 drivers/staging/sm750fb/ddk750_reg.h #define CSC_Y_SOURCE_BASE_EXT BIT(27) BIT 1165 drivers/staging/sm750fb/ddk750_reg.h #define CSC_Y_SOURCE_BASE_CS BIT(26) BIT 1183 drivers/staging/sm750fb/ddk750_reg.h #define CSC_U_SOURCE_BASE_EXT BIT(27) BIT 1184 drivers/staging/sm750fb/ddk750_reg.h #define CSC_U_SOURCE_BASE_CS BIT(26) BIT 1188 drivers/staging/sm750fb/ddk750_reg.h #define CSC_V_SOURCE_BASE_EXT BIT(27) BIT 1189 drivers/staging/sm750fb/ddk750_reg.h #define CSC_V_SOURCE_BASE_CS BIT(26) BIT 1201 drivers/staging/sm750fb/ddk750_reg.h #define CSC_DESTINATION_WRAP BIT(31) BIT 1218 drivers/staging/sm750fb/ddk750_reg.h #define CSC_DESTINATION_BASE_EXT BIT(27) BIT 1219 drivers/staging/sm750fb/ddk750_reg.h #define CSC_DESTINATION_BASE_CS BIT(26) BIT 1223 drivers/staging/sm750fb/ddk750_reg.h #define CSC_CONTROL_STATUS BIT(31) BIT 1236 drivers/staging/sm750fb/ddk750_reg.h #define CSC_CONTROL_HORIZONTAL_FILTER BIT(25) BIT 1237 drivers/staging/sm750fb/ddk750_reg.h #define CSC_CONTROL_VERTICAL_FILTER BIT(24) BIT 1238 drivers/staging/sm750fb/ddk750_reg.h #define CSC_CONTROL_BYTE_ORDER BIT(23) BIT 1246 drivers/staging/sm750fb/ddk750_reg.h #define I2C_CTRL_INT BIT(4) BIT 1247 drivers/staging/sm750fb/ddk750_reg.h #define I2C_CTRL_DIR BIT(3) BIT 1248 drivers/staging/sm750fb/ddk750_reg.h #define I2C_CTRL_CTRL BIT(2) BIT 1249 drivers/staging/sm750fb/ddk750_reg.h #define I2C_CTRL_MODE BIT(1) BIT 1250 drivers/staging/sm750fb/ddk750_reg.h #define I2C_CTRL_EN BIT(0) BIT 1253 drivers/staging/sm750fb/ddk750_reg.h #define I2C_STATUS_TX BIT(3) BIT 1254 drivers/staging/sm750fb/ddk750_reg.h #define I2C_STATUS_ERR BIT(2) BIT 1255 drivers/staging/sm750fb/ddk750_reg.h #define I2C_STATUS_ACK BIT(1) BIT 1256 drivers/staging/sm750fb/ddk750_reg.h #define I2C_STATUS_BSY BIT(0) BIT 1259 drivers/staging/sm750fb/ddk750_reg.h #define I2C_RESET_BUS_ERROR BIT(2) BIT 1263 drivers/staging/sm750fb/ddk750_reg.h #define I2C_SLAVE_ADDRESS_RW BIT(0) BIT 1283 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_FIELD_INPUT BIT(27) BIT 1284 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_SCAN BIT(26) BIT 1285 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER BIT(25) BIT 1286 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC BIT(24) BIT 1287 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_ADJ BIT(19) BIT 1288 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_HA BIT(18) BIT 1289 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_VSK BIT(17) BIT 1290 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_HSK BIT(16) BIT 1291 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_FD BIT(15) BIT 1292 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_VP BIT(14) BIT 1293 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_HP BIT(13) BIT 1294 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_CP BIT(12) BIT 1295 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_UVS BIT(11) BIT 1296 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_BS BIT(10) BIT 1297 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_CS BIT(9) BIT 1298 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_CF BIT(8) BIT 1299 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_FS BIT(7) BIT 1300 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_WEAVE BIT(6) BIT 1301 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_BOB BIT(5) BIT 1302 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_DB BIT(4) BIT 1303 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_CC BIT(3) BIT 1304 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_RGB BIT(2) BIT 1305 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_656 BIT(1) BIT 1306 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_CTRL_CAP BIT(0) BIT 1317 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS BIT(31) BIT 1318 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_BUF0_ADDRESS_EXT BIT(27) BIT 1319 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_BUF0_ADDRESS_CS BIT(26) BIT 1323 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS BIT(31) BIT 1324 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_BUF1_ADDRESS_EXT BIT(27) BIT 1325 drivers/staging/sm750fb/ddk750_reg.h #define ZV0_CAPTURE_BUF1_ADDRESS_CS BIT(26) BIT 1357 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_FIELD_INPUT BIT(27) BIT 1358 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_SCAN BIT(26) BIT 1359 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER BIT(25) BIT 1360 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC BIT(24) BIT 1361 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_PANEL BIT(20) BIT 1362 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_ADJ BIT(19) BIT 1363 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_HA BIT(18) BIT 1364 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_VSK BIT(17) BIT 1365 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_HSK BIT(16) BIT 1366 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_FD BIT(15) BIT 1367 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_VP BIT(14) BIT 1368 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_HP BIT(13) BIT 1369 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_CP BIT(12) BIT 1370 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_UVS BIT(11) BIT 1371 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_BS BIT(10) BIT 1372 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_CS BIT(9) BIT 1373 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_CF BIT(8) BIT 1374 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_FS BIT(7) BIT 1375 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_WEAVE BIT(6) BIT 1376 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_BOB BIT(5) BIT 1377 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_DB BIT(4) BIT 1378 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_CC BIT(3) BIT 1379 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_RGB BIT(2) BIT 1380 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_656 BIT(1) BIT 1381 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_CTRL_CAP BIT(0) BIT 1392 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS BIT(31) BIT 1393 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_BUF0_ADDRESS_EXT BIT(27) BIT 1394 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_BUF0_ADDRESS_CS BIT(26) BIT 1398 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS BIT(31) BIT 1399 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_BUF1_ADDRESS_EXT BIT(27) BIT 1400 drivers/staging/sm750fb/ddk750_reg.h #define ZV1_CAPTURE_BUF1_ADDRESS_CS BIT(26) BIT 1424 drivers/staging/sm750fb/ddk750_reg.h #define DMA_1_SOURCE_ADDRESS_EXT BIT(27) BIT 1425 drivers/staging/sm750fb/ddk750_reg.h #define DMA_1_SOURCE_ADDRESS_CS BIT(26) BIT 1429 drivers/staging/sm750fb/ddk750_reg.h #define DMA_1_DESTINATION_ADDRESS_EXT BIT(27) BIT 1430 drivers/staging/sm750fb/ddk750_reg.h #define DMA_1_DESTINATION_ADDRESS_CS BIT(26) BIT 1434 drivers/staging/sm750fb/ddk750_reg.h #define DMA_1_SIZE_CONTROL_STATUS BIT(31) BIT 1438 drivers/staging/sm750fb/ddk750_reg.h #define DMA_ABORT_INTERRUPT_ABORT_1 BIT(5) BIT 1439 drivers/staging/sm750fb/ddk750_reg.h #define DMA_ABORT_INTERRUPT_ABORT_0 BIT(4) BIT 1440 drivers/staging/sm750fb/ddk750_reg.h #define DMA_ABORT_INTERRUPT_INT_1 BIT(1) BIT 1441 drivers/staging/sm750fb/ddk750_reg.h #define DMA_ABORT_INTERRUPT_INT_0 BIT(0) BIT 1448 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_SM750LE_1 BIT(1) BIT 1449 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_SM750LE_0 BIT(0) BIT 1452 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_SM750LE_1 BIT(1) BIT 1453 drivers/staging/sm750fb/ddk750_reg.h #define GPIO_DATA_DIRECTION_SM750LE_0 BIT(0) BIT 25 drivers/staging/sm750fb/sm750_accel.h #define DE_SOURCE_WRAP BIT(31) BIT 32 drivers/staging/sm750fb/sm750_accel.h #define DE_DESTINATION_WRAP BIT(31) BIT 43 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_STATUS BIT(31) BIT 44 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_PATTERN BIT(30) BIT 45 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_UPDATE_DESTINATION_X BIT(29) BIT 46 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_QUICK_START BIT(28) BIT 47 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_DIRECTION BIT(27) BIT 48 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_MAJOR BIT(26) BIT 49 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_STEP_X BIT(25) BIT 50 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_STEP_Y BIT(24) BIT 51 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_STRETCH BIT(23) BIT 52 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_HOST BIT(22) BIT 53 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_LAST_PIXEL BIT(21) BIT 70 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_ROP_SELECT BIT(15) BIT 71 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_ROP2_SOURCE BIT(14) BIT 78 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_REPEAT_ROTATE BIT(11) BIT 79 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_TRANSPARENCY_MATCH BIT(10) BIT 80 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_TRANSPARENCY_SELECT BIT(9) BIT 81 drivers/staging/sm750fb/sm750_accel.h #define DE_CONTROL_TRANSPARENCY BIT(8) BIT 113 drivers/staging/sm750fb/sm750_accel.h #define DE_STRETCH_FORMAT_PATTERN_XY BIT(30) BIT 142 drivers/staging/sm750fb/sm750_accel.h #define DE_CLIP_TL_STATUS BIT(13) BIT 143 drivers/staging/sm750fb/sm750_accel.h #define DE_CLIP_TL_INHIBIT BIT(12) BIT 162 drivers/staging/sm750fb/sm750_accel.h #define DE_WINDOW_SOURCE_BASE_EXT BIT(27) BIT 163 drivers/staging/sm750fb/sm750_accel.h #define DE_WINDOW_SOURCE_BASE_CS BIT(26) BIT 167 drivers/staging/sm750fb/sm750_accel.h #define DE_WINDOW_DESTINATION_BASE_EXT BIT(27) BIT 168 drivers/staging/sm750fb/sm750_accel.h #define DE_WINDOW_DESTINATION_BASE_CS BIT(26) BIT 179 drivers/staging/sm750fb/sm750_accel.h #define DE_STATUS_CSC BIT(1) BIT 180 drivers/staging/sm750fb/sm750_accel.h #define DE_STATUS_2D BIT(0) BIT 27 drivers/staging/sm750fb/sm750_cursor.c #define HWC_ADDRESS_ENABLE BIT(31) BIT 28 drivers/staging/sm750fb/sm750_cursor.c #define HWC_ADDRESS_EXT BIT(27) BIT 29 drivers/staging/sm750fb/sm750_cursor.c #define HWC_ADDRESS_CS BIT(26) BIT 33 drivers/staging/sm750fb/sm750_cursor.c #define HWC_LOCATION_TOP BIT(27) BIT 36 drivers/staging/sm750fb/sm750_cursor.c #define HWC_LOCATION_LEFT BIT(11) BIT 1114 drivers/staging/vc04_services/bcm2835-camera/controls.c ~(BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | BIT 1115 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | BIT 1116 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | BIT 1117 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)), BIT 1126 drivers/staging/vc04_services/bcm2835-camera/controls.c ~(BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | BIT 1127 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | BIT 1128 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | BIT 1129 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | BIT 1130 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | BIT 1131 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | BIT 1132 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | BIT 1133 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | BIT 1134 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | BIT 1135 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | BIT 1136 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | BIT 1137 drivers/staging/vc04_services/bcm2835-camera/controls.c BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0)), BIT 1263 drivers/staging/vc04_services/bcm2835-camera/controls.c mask = BIT(V4L2_SCENE_MODE_NONE); BIT 1267 drivers/staging/vc04_services/bcm2835-camera/controls.c mask |= BIT(scene_configs[i].v4l2_scene); BIT 221 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAG_EOS BIT(0) BIT 223 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAG_FRAME_START BIT(1) BIT 225 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAG_FRAME_END BIT(2) BIT 231 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAG_KEYFRAME BIT(3) BIT 236 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAG_DISCONTINUITY BIT(4) BIT 241 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAG_CONFIG BIT(5) BIT 243 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAG_ENCRYPTED BIT(6) BIT 245 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAG_CODECSIDEINFO BIT(7) BIT 250 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAGS_SNAPSHOT BIT(8) BIT 252 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAG_CORRUPTED BIT(9) BIT 254 drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h #define MMAL_BUFFER_HEADER_FLAG_TRANSMISSION_FAILED BIT(10) BIT 2022 drivers/staging/vt6655/baseband.c MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0)); BIT 2062 drivers/staging/vt6655/baseband.c MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0)); BIT 2277 drivers/staging/vt6655/baseband.c byOrgData |= BIT(0); BIT 2299 drivers/staging/vt6655/baseband.c byOrgData &= ~(BIT(0)); BIT 810 drivers/staging/vt6655/card.c if ((priv->basic_rates) & ((u32)BIT(ii))) BIT 1740 drivers/staging/vt6655/device_main.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 1741 drivers/staging/vt6655/device_main.c BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_AP); BIT 54 drivers/staging/vt6655/power.c u16 wAID = priv->current_aid | BIT(14) | BIT(15); BIT 508 drivers/staging/vt6655/rxtx.c __le16 dur = cpu_to_le16(pDevice->current_aid | BIT(14) | BIT(15)); BIT 579 drivers/staging/vt6655/rxtx.c __le16 dur = cpu_to_le16(pDevice->current_aid | BIT(14) | BIT(15)); BIT 601 drivers/staging/vt6655/rxtx.c __le16 dur = cpu_to_le16(pDevice->current_aid | BIT(14) | BIT(15)); BIT 446 drivers/staging/vt6656/card.c if ((priv->basic_rates) & ((u16)BIT(ii))) BIT 55 drivers/staging/vt6656/device.h #define VNT_B_RATES (BIT(RATE_1M) | BIT(RATE_2M) |\ BIT 56 drivers/staging/vt6656/device.h BIT(RATE_5M) | BIT(RATE_11M)) BIT 1014 drivers/staging/vt6656/main_usb.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 1015 drivers/staging/vt6656/main_usb.c BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_AP); BIT 43 drivers/staging/vt6656/power.c u16 aid = priv->current_aid | BIT(14) | BIT(15); BIT 535 drivers/staging/wilc1000/wilc_hif.c if (ie->qos_info & BIT(7)) BIT 81 drivers/staging/wilc1000/wilc_hif.h WILC_CFG_PARAM_RETRY_SHORT = BIT(0), BIT 82 drivers/staging/wilc1000/wilc_hif.h WILC_CFG_PARAM_RETRY_LONG = BIT(1), BIT 83 drivers/staging/wilc1000/wilc_hif.h WILC_CFG_PARAM_FRAG_THRESHOLD = BIT(2), BIT 84 drivers/staging/wilc1000/wilc_hif.h WILC_CFG_PARAM_RTS_THRESHOLD = BIT(3) BIT 102 drivers/staging/wilc1000/wilc_hif.h WILC_HIF_SPI = BIT(0) BIT 833 drivers/staging/wilc1000/wilc_sdio.c if (cmd.data & BIT(0)) BIT 835 drivers/staging/wilc1000/wilc_sdio.c if (cmd.data & BIT(2)) BIT 837 drivers/staging/wilc1000/wilc_sdio.c if (cmd.data & BIT(3)) BIT 839 drivers/staging/wilc1000/wilc_sdio.c if (cmd.data & BIT(4)) BIT 841 drivers/staging/wilc1000/wilc_sdio.c if (cmd.data & BIT(5)) BIT 843 drivers/staging/wilc1000/wilc_sdio.c if (cmd.data & BIT(6)) BIT 884 drivers/staging/wilc1000/wilc_sdio.c flags = val & (BIT(MAX_NUN_INT_THRPT_ENH2) - 1); BIT 891 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT(5); BIT 894 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT(6); BIT 897 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT(7); BIT 925 drivers/staging/wilc1000/wilc_sdio.c flags = val & (BIT(MAX_NUM_INT) - 1); BIT 938 drivers/staging/wilc1000/wilc_sdio.c cmd.data = BIT(i); BIT 967 drivers/staging/wilc1000/wilc_sdio.c vmm_ctl |= BIT(0); BIT 970 drivers/staging/wilc1000/wilc_sdio.c vmm_ctl |= BIT(1); BIT 973 drivers/staging/wilc1000/wilc_sdio.c vmm_ctl |= BIT(2); BIT 1022 drivers/staging/wilc1000/wilc_sdio.c reg &= ~BIT(8); BIT 1041 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT(8); BIT 1060 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT((27 + i)); BIT 1077 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT(i); BIT 308 drivers/staging/wilc1000/wilc_spi.c wb[1] |= BIT(7); BIT 359 drivers/staging/wilc1000/wilc_spi.c wb[1] |= BIT(7); BIT 988 drivers/staging/wilc1000/wilc_spi.c flags = val & (BIT(MAX_NUM_INT) - 1); BIT 1023 drivers/staging/wilc1000/wilc_spi.c tbl_ctl |= BIT(0); BIT 1026 drivers/staging/wilc1000/wilc_spi.c tbl_ctl |= BIT(1); BIT 1071 drivers/staging/wilc1000/wilc_spi.c reg |= BIT(8); BIT 1090 drivers/staging/wilc1000/wilc_spi.c reg |= (BIT((27 + i))); BIT 1107 drivers/staging/wilc1000/wilc_spi.c reg |= BIT(i); BIT 36 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 37 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) BIT 41 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 42 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 43 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 44 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 45 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 46 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 47 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_ACTION >> 4) BIT 51 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 52 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 53 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 54 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 55 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 56 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 57 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(IEEE80211_STYPE_DEAUTH >> 4) BIT 1906 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | BIT 1907 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(NL80211_IFTYPE_AP) | BIT 1908 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(NL80211_IFTYPE_MONITOR) | BIT 1909 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(NL80211_IFTYPE_P2P_GO) | BIT 1910 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c BIT(NL80211_IFTYPE_P2P_CLIENT); BIT 398 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_write_reg(wilc, 0xf0, reg & ~BIT(0)); BIT 410 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_write_reg(wilc, 1, reg | BIT(1)); BIT 411 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_write_reg(wilc, 1, reg & ~BIT(1)); BIT 424 drivers/staging/wilc1000/wilc_wlan.c reg | BIT(0)); BIT 436 drivers/staging/wilc1000/wilc_wlan.c reg & (~BIT(0))); BIT 446 drivers/staging/wilc1000/wilc_wlan.c val32 |= BIT(6); BIT 450 drivers/staging/wilc1000/wilc_wlan.c val32 |= BIT(6); BIT 523 drivers/staging/wilc1000/wilc_wlan.c vmm_table[i] |= BIT(10); BIT 594 drivers/staging/wilc1000/wilc_wlan.c reg &= ~BIT(0); BIT 634 drivers/staging/wilc1000/wilc_wlan.c header |= BIT(30); BIT 636 drivers/staging/wilc1000/wilc_wlan.c header &= ~BIT(30); BIT 827 drivers/staging/wilc1000/wilc_wlan.c blksz = BIT(12); BIT 878 drivers/staging/wilc1000/wilc_wlan.c reg |= BIT(3); BIT 930 drivers/staging/wilc1000/wilc_wlan.c if ((reg & BIT(10)) == BIT(10)) { BIT 931 drivers/staging/wilc1000/wilc_wlan.c reg &= ~BIT(10); BIT 936 drivers/staging/wilc1000/wilc_wlan.c reg |= BIT(10); BIT 972 drivers/staging/wilc1000/wilc_wlan.c reg = BIT(0); BIT 1175 drivers/staging/wilc1000/wilc_wlan.c reg |= BIT(0); BIT 105 drivers/staging/wilc1000/wilc_wlan.h #define WILC_HAVE_SDIO_IRQ_GPIO BIT(0) BIT 106 drivers/staging/wilc1000/wilc_wlan.h #define WILC_HAVE_USE_PMU BIT(1) BIT 107 drivers/staging/wilc1000/wilc_wlan.h #define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2) BIT 108 drivers/staging/wilc1000/wilc_wlan.h #define WILC_HAVE_SLEEP_CLK_SRC_XO BIT(3) BIT 109 drivers/staging/wilc1000/wilc_wlan.h #define WILC_HAVE_EXT_PA_INV_TX_RX BIT(4) BIT 110 drivers/staging/wilc1000/wilc_wlan.h #define WILC_HAVE_LEGACY_RF_SETTINGS BIT(5) BIT 111 drivers/staging/wilc1000/wilc_wlan.h #define WILC_HAVE_XTAL_24 BIT(6) BIT 112 drivers/staging/wilc1000/wilc_wlan.h #define WILC_HAVE_DISABLE_WILC_UART BIT(7) BIT 113 drivers/staging/wilc1000/wilc_wlan.h #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8) BIT 131 drivers/staging/wilc1000/wilc_wlan.h #define WILC_ABORT_REQ_BIT BIT(31) BIT 154 drivers/staging/wilc1000/wilc_wlan.h #define INT_0 BIT(IRG_FLAGS_OFFSET) BIT 155 drivers/staging/wilc1000/wilc_wlan.h #define INT_1 BIT(IRG_FLAGS_OFFSET + 1) BIT 156 drivers/staging/wilc1000/wilc_wlan.h #define INT_2 BIT(IRG_FLAGS_OFFSET + 2) BIT 157 drivers/staging/wilc1000/wilc_wlan.h #define INT_3 BIT(IRG_FLAGS_OFFSET + 3) BIT 158 drivers/staging/wilc1000/wilc_wlan.h #define INT_4 BIT(IRG_FLAGS_OFFSET + 4) BIT 159 drivers/staging/wilc1000/wilc_wlan.h #define INT_5 BIT(IRG_FLAGS_OFFSET + 5) BIT 175 drivers/staging/wilc1000/wilc_wlan.h #define CLR_INT0 BIT(0) BIT 176 drivers/staging/wilc1000/wilc_wlan.h #define CLR_INT1 BIT(1) BIT 177 drivers/staging/wilc1000/wilc_wlan.h #define CLR_INT2 BIT(2) BIT 178 drivers/staging/wilc1000/wilc_wlan.h #define CLR_INT3 BIT(3) BIT 179 drivers/staging/wilc1000/wilc_wlan.h #define CLR_INT4 BIT(4) BIT 180 drivers/staging/wilc1000/wilc_wlan.h #define CLR_INT5 BIT(5) BIT 181 drivers/staging/wilc1000/wilc_wlan.h #define SEL_VMM_TBL0 BIT(6) BIT 182 drivers/staging/wilc1000/wilc_wlan.h #define SEL_VMM_TBL1 BIT(7) BIT 183 drivers/staging/wilc1000/wilc_wlan.h #define EN_VMM BIT(8) BIT 68 drivers/staging/wilc1000/wilc_wlan_if.h WILC_FW_ENCRYPT_ENABLED = BIT(0), BIT 69 drivers/staging/wilc1000/wilc_wlan_if.h WILC_FW_WEP = BIT(1), BIT 70 drivers/staging/wilc1000/wilc_wlan_if.h WILC_FW_WEP_EXTENDED = BIT(2), BIT 71 drivers/staging/wilc1000/wilc_wlan_if.h WILC_FW_WPA = BIT(3), BIT 72 drivers/staging/wilc1000/wilc_wlan_if.h WILC_FW_WPA2 = BIT(4), BIT 73 drivers/staging/wilc1000/wilc_wlan_if.h WILC_FW_AES = BIT(5), BIT 74 drivers/staging/wilc1000/wilc_wlan_if.h WILC_FW_TKIP = BIT(6) BIT 177 drivers/staging/wilc1000/wilc_wlan_if.h WILC_FW_USER_SCAN = BIT(0), BIT 178 drivers/staging/wilc1000/wilc_wlan_if.h WILC_FW_OBSS_PERIODIC_SCAN = BIT(1), BIT 179 drivers/staging/wilc1000/wilc_wlan_if.h WILC_FW_OBSS_ONETIME_SCAN = BIT(2) BIT 697 drivers/staging/wlan-ng/cfg80211.c wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) BIT 698 drivers/staging/wlan-ng/cfg80211.c | BIT(NL80211_IFTYPE_ADHOC); BIT 82 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_WEPFLAGS_PRIVINVOKED ((u16)BIT(0)) BIT 83 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_WEPFLAGS_EXCLUDE ((u16)BIT(1)) BIT 84 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_WEPFLAGS_DISABLE_TXCRYPT ((u16)BIT(4)) BIT 85 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_WEPFLAGS_DISABLE_RXCRYPT ((u16)BIT(7)) BIT 499 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_TXSTATUS_ACKERR ((u16)BIT(5)) BIT 500 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_TXSTATUS_FORMERR ((u16)BIT(3)) BIT 501 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_TXSTATUS_DISCON ((u16)BIT(2)) BIT 502 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_TXSTATUS_AGEDERR ((u16)BIT(1)) BIT 503 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_TXSTATUS_RETRYERR ((u16)BIT(0)) BIT 507 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_TX_TXEX ((u16)BIT(2)) BIT 508 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_TX_TXOK ((u16)BIT(1)) BIT 565 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_RXSTATUS_FCSERR ((u16)BIT(0)) BIT 676 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_CHINFORESULT_BSSACTIVE BIT(0) BIT 677 drivers/staging/wlan-ng/hfa384x.h #define HFA384x_CHINFORESULT_PCFACTIVE BIT(1) BIT 137 drivers/staging/wlan-ng/p80211hdr.h #define WLAN_GET_FC_TODS(n) ((((u16)(n)) & (BIT(8))) >> 8) BIT 138 drivers/staging/wlan-ng/p80211hdr.h #define WLAN_GET_FC_FROMDS(n) ((((u16)(n)) & (BIT(9))) >> 9) BIT 139 drivers/staging/wlan-ng/p80211hdr.h #define WLAN_GET_FC_ISWEP(n) ((((u16)(n)) & (BIT(14))) >> 14) BIT 147 drivers/staging/wlan-ng/p80211hdr.h #define DOT11_RATE5_ISBASIC_GET(r) (((u8)(r)) & BIT(7)) BIT 200 drivers/staging/wlan-ng/p80211mgmt.h #define WLAN_GET_MGMT_CAP_INFO_ESS(n) ((n) & BIT(0)) BIT 201 drivers/staging/wlan-ng/p80211mgmt.h #define WLAN_GET_MGMT_CAP_INFO_IBSS(n) (((n) & BIT(1)) >> 1) BIT 202 drivers/staging/wlan-ng/p80211mgmt.h #define WLAN_GET_MGMT_CAP_INFO_CFPOLLABLE(n) (((n) & BIT(2)) >> 2) BIT 203 drivers/staging/wlan-ng/p80211mgmt.h #define WLAN_GET_MGMT_CAP_INFO_CFPOLLREQ(n) (((n) & BIT(3)) >> 3) BIT 204 drivers/staging/wlan-ng/p80211mgmt.h #define WLAN_GET_MGMT_CAP_INFO_PRIVACY(n) (((n) & BIT(4)) >> 4) BIT 206 drivers/staging/wlan-ng/p80211mgmt.h #define WLAN_GET_MGMT_CAP_INFO_SHORT(n) (((n) & BIT(5)) >> 5) BIT 207 drivers/staging/wlan-ng/p80211mgmt.h #define WLAN_GET_MGMT_CAP_INFO_PBCC(n) (((n) & BIT(6)) >> 6) BIT 208 drivers/staging/wlan-ng/p80211mgmt.h #define WLAN_GET_MGMT_CAP_INFO_AGILITY(n) (((n) & BIT(7)) >> 7) BIT 148 drivers/staging/wlan-ng/p80211netdev.h #define HOSTWEP_SHAREDKEY BIT(3) BIT 149 drivers/staging/wlan-ng/p80211netdev.h #define HOSTWEP_DECRYPT BIT(4) BIT 150 drivers/staging/wlan-ng/p80211netdev.h #define HOSTWEP_ENCRYPT BIT(5) BIT 151 drivers/staging/wlan-ng/p80211netdev.h #define HOSTWEP_PRIVACYINVOKED BIT(6) BIT 152 drivers/staging/wlan-ng/p80211netdev.h #define HOSTWEP_EXCLUDEUNENCRYPTED BIT(7) BIT 90 drivers/staging/wlan-ng/prism2mgmt.c switch (rate & ~BIT(7)) { BIT 92 drivers/staging/wlan-ng/prism2mgmt.c return BIT(0); BIT 94 drivers/staging/wlan-ng/prism2mgmt.c return BIT(1); BIT 96 drivers/staging/wlan-ng/prism2mgmt.c return BIT(2); BIT 98 drivers/staging/wlan-ng/prism2mgmt.c return BIT(3); BIT 45 drivers/tee/optee/optee_msg.h #define OPTEE_MSG_ATTR_META BIT(8) BIT 73 drivers/tee/optee/optee_msg.h #define OPTEE_MSG_ATTR_NONCONTIG BIT(9) BIT 206 drivers/tee/optee/optee_smc.h #define OPTEE_SMC_NSEC_CAP_UNIPROCESSOR BIT(0) BIT 208 drivers/tee/optee/optee_smc.h #define OPTEE_SMC_SEC_CAP_HAVE_RESERVED_SHM BIT(0) BIT 210 drivers/tee/optee/optee_smc.h #define OPTEE_SMC_SEC_CAP_UNREGISTERED_SHM BIT(1) BIT 216 drivers/tee/optee/optee_smc.h #define OPTEE_SMC_SEC_CAP_DYNAMIC_SHM BIT(2) BIT 37 drivers/thermal/armada_thermal.c #define A375_READOUT_INVERT BIT(15) BIT 38 drivers/thermal/armada_thermal.c #define A375_HW_RESETn BIT(8) BIT 44 drivers/thermal/armada_thermal.c #define CONTROL0_TSEN_START BIT(0) BIT 45 drivers/thermal/armada_thermal.c #define CONTROL0_TSEN_RESET BIT(1) BIT 46 drivers/thermal/armada_thermal.c #define CONTROL0_TSEN_ENABLE BIT(2) BIT 47 drivers/thermal/armada_thermal.c #define CONTROL0_TSEN_AVG_BYPASS BIT(6) BIT 57 drivers/thermal/armada_thermal.c #define CONTROL1_EXT_TSEN_SW_RESET BIT(7) BIT 58 drivers/thermal/armada_thermal.c #define CONTROL1_EXT_TSEN_HW_RESETn BIT(8) BIT 59 drivers/thermal/armada_thermal.c #define CONTROL1_TSEN_INT_EN BIT(25) BIT 586 drivers/thermal/armada_thermal.c .is_valid_bit = BIT(9), BIT 598 drivers/thermal/armada_thermal.c .is_valid_bit = BIT(10), BIT 611 drivers/thermal/armada_thermal.c .is_valid_bit = BIT(10), BIT 625 drivers/thermal/armada_thermal.c .is_valid_bit = BIT(16), BIT 641 drivers/thermal/armada_thermal.c .dfx_overheat_irq = BIT(22), BIT 643 drivers/thermal/armada_thermal.c .dfx_server_irq_en = BIT(1), BIT 649 drivers/thermal/armada_thermal.c .is_valid_bit = BIT(10), BIT 664 drivers/thermal/armada_thermal.c .dfx_overheat_irq = BIT(20), BIT 666 drivers/thermal/armada_thermal.c .dfx_server_irq_en = BIT(1), BIT 26 drivers/thermal/broadcom/bcm2835_thermal.c #define BCM2835_TS_TSENSCTL_PRWDW BIT(0) BIT 27 drivers/thermal/broadcom/bcm2835_thermal.c #define BCM2835_TS_TSENSCTL_RSTB BIT(1) BIT 40 drivers/thermal/broadcom/bcm2835_thermal.c #define BCM2835_TS_TSENSCTL_EN_INT BIT(5) BIT 41 drivers/thermal/broadcom/bcm2835_thermal.c #define BCM2835_TS_TSENSCTL_DIRECT BIT(6) BIT 42 drivers/thermal/broadcom/bcm2835_thermal.c #define BCM2835_TS_TSENSCTL_CLR_INT BIT(7) BIT 55 drivers/thermal/broadcom/bcm2835_thermal.c #define BCM2835_TS_TSENSCTL_REGULEN BIT(26) BIT 63 drivers/thermal/broadcom/bcm2835_thermal.c #define BCM2835_TS_TSENSSTAT_VALID BIT(10) BIT 64 drivers/thermal/broadcom/bcm2835_thermal.c #define BCM2835_TS_TSENSSTAT_INTERRUPT BIT(11) BIT 85 drivers/thermal/broadcom/bcm2835_thermal.c if (temp >= BIT(BCM2835_TS_TSENSSTAT_DATA_BITS)) BIT 86 drivers/thermal/broadcom/bcm2835_thermal.c temp = BIT(BCM2835_TS_TSENSSTAT_DATA_BITS) - 1; BIT 25 drivers/thermal/broadcom/brcmstb_thermal.c #define AVS_TMON_STATUS_valid_msk BIT(11) BIT 30 drivers/thermal/broadcom/brcmstb_thermal.c #define AVS_TMON_EN_OVERTEMP_RESET_msk BIT(0) BIT 39 drivers/thermal/broadcom/brcmstb_thermal.c #define AVS_TMON_EN_TEMP_INT_SRCS_high BIT(1) BIT 40 drivers/thermal/broadcom/brcmstb_thermal.c #define AVS_TMON_EN_TEMP_INT_SRCS_low BIT(0) BIT 77 drivers/thermal/broadcom/sr-thermal.c if (!(sr_tmon_list & BIT(i))) BIT 808 drivers/thermal/imx_thermal.c BIT(IMX_TRIP_PASSIVE), data, BIT 241 drivers/thermal/intel/int340x_thermal/int340x_thermal_zone.c trip_mask = BIT(trip_cnt) - 1; BIT 192 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c if (!(val & BIT(30))) BIT 72 drivers/thermal/intel/intel_quark_dts_thermal.c #define QRK_DTS_RESET_BIT BIT(0) BIT 76 drivers/thermal/intel/intel_quark_dts_thermal.c #define QRK_DTS_ENABLE_BIT BIT(15) BIT 94 drivers/thermal/intel/intel_quark_dts_thermal.c #define QRK_DTS_LOCK_BIT BIT(5) BIT 25 drivers/thermal/intel/intel_soc_dts_iosf.c #define SOC_DTS_AUX0_ENABLE_BIT BIT(0) BIT 26 drivers/thermal/intel/intel_soc_dts_iosf.c #define SOC_DTS_AUX1_ENABLE_BIT BIT(1) BIT 27 drivers/thermal/intel/intel_soc_dts_iosf.c #define SOC_DTS_CPU_MODULE0_ENABLE_BIT BIT(16) BIT 28 drivers/thermal/intel/intel_soc_dts_iosf.c #define SOC_DTS_CPU_MODULE1_ENABLE_BIT BIT(17) BIT 29 drivers/thermal/intel/intel_soc_dts_iosf.c #define SOC_DTS_TE_SCI_ENABLE BIT(9) BIT 30 drivers/thermal/intel/intel_soc_dts_iosf.c #define SOC_DTS_TE_SMI_ENABLE BIT(10) BIT 31 drivers/thermal/intel/intel_soc_dts_iosf.c #define SOC_DTS_TE_MSI_ENABLE BIT(11) BIT 32 drivers/thermal/intel/intel_soc_dts_iosf.c #define SOC_DTS_TE_APICA_ENABLE BIT(14) BIT 33 drivers/thermal/intel/intel_soc_dts_iosf.c #define SOC_DTS_PTMC_APIC_DEASSERT_BIT BIT(4) BIT 258 drivers/thermal/intel/intel_soc_dts_iosf.c if (!(out & BIT(id))) { BIT 259 drivers/thermal/intel/intel_soc_dts_iosf.c out |= BIT(id); BIT 300 drivers/thermal/intel/intel_soc_dts_iosf.c trip_mask = BIT(trip_count - read_only_trip_cnt) - 1; BIT 310 drivers/thermal/intel/intel_soc_dts_iosf.c if (trip_mask & BIT(i)) BIT 312 drivers/thermal/intel/intel_soc_dts_iosf.c trip_mask &= ~BIT(i); BIT 346 drivers/thermal/intel/intel_soc_dts_iosf.c if (!(sensors->soc_dts[i].trip_mask & BIT(j))) { BIT 84 drivers/thermal/mtk_thermal.c #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) BIT 85 drivers/thermal/mtk_thermal.c #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) BIT 87 drivers/thermal/mtk_thermal.c #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) BIT 123 drivers/thermal/mtk_thermal.c #define CALIB_BUF0_VALID BIT(0) BIT 695 drivers/thermal/mtk_thermal.c writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); BIT 706 drivers/thermal/mtk_thermal.c writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN); BIT 34 drivers/thermal/qcom/qcom-spmi-temp-alarm.c #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) BIT 37 drivers/thermal/qcom/qcom-spmi-temp-alarm.c #define SHUTDOWN_CTRL1_RATE_25HZ BIT(3) BIT 39 drivers/thermal/qcom/qcom-spmi-temp-alarm.c #define ALARM_CTRL_FORCE_ENABLE BIT(7) BIT 27 drivers/thermal/qcom/tsens-8960.c #define EN BIT(0) BIT 28 drivers/thermal/qcom/tsens-8960.c #define SW_RST BIT(1) BIT 29 drivers/thermal/qcom/tsens-8960.c #define SENSOR0_EN BIT(3) BIT 30 drivers/thermal/qcom/tsens-8960.c #define SLP_CLK_ENA BIT(26) BIT 31 drivers/thermal/qcom/tsens-8960.c #define SLP_CLK_ENA_8660 BIT(24) BIT 36 drivers/thermal/qcom/tsens-8960.c #define MIN_STATUS_MASK BIT(0) BIT 37 drivers/thermal/qcom/tsens-8960.c #define LOWER_STATUS_CLR BIT(1) BIT 38 drivers/thermal/qcom/tsens-8960.c #define UPPER_STATUS_CLR BIT(2) BIT 39 drivers/thermal/qcom/tsens-8960.c #define MAX_STATUS_MASK BIT(3) BIT 56 drivers/thermal/qcom/tsens-8960.c #define TRDY_MASK BIT(7) BIT 124 drivers/thermal/qcom/tsens-8960.c mask = BIT(id + SENSOR0_SHIFT); BIT 39 drivers/thermal/rcar_gen3_thermal.c #define IRQ_TEMP1 BIT(0) BIT 40 drivers/thermal/rcar_gen3_thermal.c #define IRQ_TEMP2 BIT(1) BIT 41 drivers/thermal/rcar_gen3_thermal.c #define IRQ_TEMP3 BIT(2) BIT 42 drivers/thermal/rcar_gen3_thermal.c #define IRQ_TEMPD1 BIT(3) BIT 43 drivers/thermal/rcar_gen3_thermal.c #define IRQ_TEMPD2 BIT(4) BIT 44 drivers/thermal/rcar_gen3_thermal.c #define IRQ_TEMPD3 BIT(5) BIT 47 drivers/thermal/rcar_gen3_thermal.c #define CTSR_PONM BIT(8) BIT 48 drivers/thermal/rcar_gen3_thermal.c #define CTSR_AOUT BIT(7) BIT 49 drivers/thermal/rcar_gen3_thermal.c #define CTSR_THBGR BIT(5) BIT 50 drivers/thermal/rcar_gen3_thermal.c #define CTSR_VMEN BIT(4) BIT 51 drivers/thermal/rcar_gen3_thermal.c #define CTSR_VMST BIT(1) BIT 52 drivers/thermal/rcar_gen3_thermal.c #define CTSR_THSST BIT(0) BIT 55 drivers/thermal/rcar_gen3_thermal.c #define THCTR_PONM BIT(6) BIT 56 drivers/thermal/rcar_gen3_thermal.c #define THCTR_THSST BIT(0) BIT 188 drivers/thermal/rockchip_thermal.c #define TSADCV2_AUTO_EN BIT(0) BIT 189 drivers/thermal/rockchip_thermal.c #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) BIT 190 drivers/thermal/rockchip_thermal.c #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) BIT 192 drivers/thermal/rockchip_thermal.c #define TSADCV3_AUTO_Q_SEL_EN BIT(1) BIT 194 drivers/thermal/rockchip_thermal.c #define TSADCV2_INT_SRC_EN(chn) BIT(chn) BIT 195 drivers/thermal/rockchip_thermal.c #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) BIT 196 drivers/thermal/rockchip_thermal.c #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) BIT 198 drivers/thermal/rockchip_thermal.c #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) BIT 199 drivers/thermal/rockchip_thermal.c #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) BIT 98 drivers/thermal/samsung/exynos_tmu.c #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) BIT 20 drivers/thermal/st/st_thermal_memmap.c #define THERMAL_PDN BIT(4) BIT 21 drivers/thermal/st/st_thermal_memmap.c #define THERMAL_SRSTN BIT(10) BIT 61 drivers/thermal/st/stm_thermal.c #define TS1_EN BIT(0) BIT 62 drivers/thermal/st/stm_thermal.c #define TS1_START BIT(4) BIT 63 drivers/thermal/st/stm_thermal.c #define REFCLK_SEL BIT(20) BIT 65 drivers/thermal/st/stm_thermal.c #define Q_MEAS_OPT BIT(21) BIT 69 drivers/thermal/st/stm_thermal.c #define TS_RDY BIT(15) BIT 71 drivers/thermal/st/stm_thermal.c #define HIGH_THRESHOLD BIT(2) BIT 72 drivers/thermal/st/stm_thermal.c #define LOW_THRESHOLD BIT(1) BIT 40 drivers/thermal/tegra/soctherm.c #define SENSOR_CONFIG0_STOP BIT(0) BIT 41 drivers/thermal/tegra/soctherm.c #define SENSOR_CONFIG0_CPTR_OVER BIT(2) BIT 42 drivers/thermal/tegra/soctherm.c #define SENSOR_CONFIG0_OVER BIT(3) BIT 43 drivers/thermal/tegra/soctherm.c #define SENSOR_CONFIG0_TCALC_OVER BIT(4) BIT 54 drivers/thermal/tegra/soctherm.c #define SENSOR_CONFIG1_TEMP_ENABLE BIT(31) BIT 62 drivers/thermal/tegra/soctherm.c #define SENSOR_STATUS0_VALID_MASK BIT(31) BIT 66 drivers/thermal/tegra/soctherm.c #define SENSOR_STATUS1_TEMP_VALID_MASK BIT(31) BIT 71 drivers/thermal/tegra/soctherm.c #define READBACK_ADD_HALF BIT(7) BIT 72 drivers/thermal/tegra/soctherm.c #define READBACK_NEGATE BIT(0) BIT 78 drivers/thermal/tegra/soctherm.c #define THERMCTL_LVL0_CPU0_EN_MASK BIT(8) BIT 85 drivers/thermal/tegra/soctherm.c #define THERMCTL_LVL0_CPU0_MEM_THROT_MASK BIT(2) BIT 93 drivers/thermal/tegra/soctherm.c #define TH_INTR_MD0_MASK BIT(25) BIT 94 drivers/thermal/tegra/soctherm.c #define TH_INTR_MU0_MASK BIT(24) BIT 95 drivers/thermal/tegra/soctherm.c #define TH_INTR_GD0_MASK BIT(17) BIT 96 drivers/thermal/tegra/soctherm.c #define TH_INTR_GU0_MASK BIT(16) BIT 97 drivers/thermal/tegra/soctherm.c #define TH_INTR_CD0_MASK BIT(9) BIT 98 drivers/thermal/tegra/soctherm.c #define TH_INTR_CU0_MASK BIT(8) BIT 99 drivers/thermal/tegra/soctherm.c #define TH_INTR_PD0_MASK BIT(1) BIT 100 drivers/thermal/tegra/soctherm.c #define TH_INTR_PU0_MASK BIT(0) BIT 110 drivers/thermal/tegra/soctherm.c #define OC1_CFG_LONG_LATENCY_MASK BIT(6) BIT 111 drivers/thermal/tegra/soctherm.c #define OC1_CFG_HW_RESTORE_MASK BIT(5) BIT 112 drivers/thermal/tegra/soctherm.c #define OC1_CFG_PWR_GOOD_MASK_MASK BIT(4) BIT 114 drivers/thermal/tegra/soctherm.c #define OC1_CFG_ALARM_POLARITY_MASK BIT(1) BIT 115 drivers/thermal/tegra/soctherm.c #define OC1_CFG_EN_THROTTLE_MASK BIT(0) BIT 130 drivers/thermal/tegra/soctherm.c #define OC_INTR_OC1_MASK BIT(0) BIT 131 drivers/thermal/tegra/soctherm.c #define OC_INTR_OC2_MASK BIT(1) BIT 132 drivers/thermal/tegra/soctherm.c #define OC_INTR_OC3_MASK BIT(2) BIT 133 drivers/thermal/tegra/soctherm.c #define OC_INTR_OC4_MASK BIT(3) BIT 134 drivers/thermal/tegra/soctherm.c #define OC_INTR_OC5_MASK BIT(4) BIT 137 drivers/thermal/tegra/soctherm.c #define THROT_GLOBAL_ENB_MASK BIT(0) BIT 142 drivers/thermal/tegra/soctherm.c #define XPU_PSKIP_STATUS_SW_OVERRIDE_MASK BIT(1) BIT 143 drivers/thermal/tegra/soctherm.c #define XPU_PSKIP_STATUS_ENABLED_MASK BIT(0) BIT 149 drivers/thermal/tegra/soctherm.c #define THROT_STATUS_BREACH_MASK BIT(12) BIT 151 drivers/thermal/tegra/soctherm.c #define THROT_STATUS_ENABLED_MASK BIT(0) BIT 154 drivers/thermal/tegra/soctherm.c #define THROT_PSKIP_CTRL_ENABLE_MASK BIT(31) BIT 167 drivers/thermal/tegra/soctherm.c #define THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31) BIT 179 drivers/thermal/tegra/soctherm.c #define CDIVG_USE_THERM_CONTROLS_MASK BIT(30) BIT 187 drivers/thermal/tegra/soctherm.c #define CCROC_THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31) BIT 192 drivers/thermal/tegra/soctherm.c #define CCROC_THROT_PSKIP_CTRL_ENB_MASK BIT(31) BIT 1060 drivers/thermal/tegra/soctherm.c if (oc1 && soc_irq_cdata.irq_enable & BIT(0)) BIT 1064 drivers/thermal/tegra/soctherm.c if (oc2 && soc_irq_cdata.irq_enable & BIT(1)) BIT 1068 drivers/thermal/tegra/soctherm.c if (oc3 && soc_irq_cdata.irq_enable & BIT(2)) BIT 1072 drivers/thermal/tegra/soctherm.c if (oc4 && soc_irq_cdata.irq_enable & BIT(3)) BIT 1154 drivers/thermal/tegra/soctherm.c d->irq_enable |= BIT(data->hwirq); BIT 1170 drivers/thermal/tegra/soctherm.c d->irq_enable &= ~BIT(data->hwirq); BIT 83 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5) BIT 84 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4) BIT 85 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3) BIT 86 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2) BIT 87 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1) BIT 88 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0) BIT 91 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22) BIT 92 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21) BIT 93 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3) BIT 94 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2) BIT 95 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1) BIT 96 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0) BIT 99 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3) BIT 100 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2) BIT 101 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1) BIT 102 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0) BIT 106 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23) BIT 107 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22) BIT 108 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21) BIT 109 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5) BIT 110 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4) BIT 111 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3) BIT 112 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2) BIT 113 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1) BIT 114 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0) BIT 117 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11) BIT 118 drivers/thermal/ti-soc-thermal/dra752-bandgap.h #define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10) BIT 31 drivers/thermal/ti-soc-thermal/omap3-thermal-data.c .bgap_soc_mask = BIT(8), BIT 32 drivers/thermal/ti-soc-thermal/omap3-thermal-data.c .bgap_eocz_mask = BIT(7), BIT 36 drivers/thermal/ti-soc-thermal/omap3-thermal-data.c .mode_ctrl_mask = BIT(9), BIT 99 drivers/thermal/ti-soc-thermal/omap3-thermal-data.c .bgap_soc_mask = BIT(9), BIT 100 drivers/thermal/ti-soc-thermal/omap3-thermal-data.c .bgap_eocz_mask = BIT(8), BIT 104 drivers/thermal/ti-soc-thermal/omap3-thermal-data.c .mode_ctrl_mask = BIT(10), BIT 41 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4430_BGAP_TEMPSOFF_MASK BIT(12) BIT 42 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4430_BGAP_TSHUT_MASK BIT(11) BIT 43 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4430_SINGLE_MODE_MASK BIT(10) BIT 44 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4430_BGAP_TEMP_SENSOR_SOC_MASK BIT(9) BIT 45 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(8) BIT 106 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4460_BGAP_TEMPSOFF_MASK BIT(13) BIT 107 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK BIT(11) BIT 108 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10) BIT 112 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4460_SINGLE_MODE_MASK BIT(31) BIT 113 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4460_MASK_HOT_MASK BIT(1) BIT 114 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4460_MASK_COLD_MASK BIT(0) BIT 128 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4460_HOT_FLAG_MASK BIT(1) BIT 129 drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h #define OMAP4460_COLD_FLAG_MASK BIT(0) BIT 65 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK BIT(12) BIT 66 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_BGAP_TEMPSOFF_MASK BIT(11) BIT 67 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10) BIT 72 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23) BIT 73 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22) BIT 74 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21) BIT 75 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_MASK_HOT_CORE_MASK BIT(5) BIT 76 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_MASK_COLD_CORE_MASK BIT(4) BIT 77 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_MASK_HOT_GPU_MASK BIT(3) BIT 78 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_MASK_COLD_GPU_MASK BIT(2) BIT 79 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_MASK_HOT_MPU_MASK BIT(1) BIT 80 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_MASK_COLD_MPU_MASK BIT(0) BIT 94 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_HOT_CORE_FLAG_MASK BIT(5) BIT 95 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_COLD_CORE_FLAG_MASK BIT(4) BIT 96 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_HOT_GPU_FLAG_MASK BIT(3) BIT 97 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_COLD_GPU_FLAG_MASK BIT(2) BIT 98 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_HOT_MPU_FLAG_MASK BIT(1) BIT 99 drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h #define OMAP5430_COLD_MPU_FLAG_MASK BIT(0) BIT 278 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_TSHUT BIT(0) BIT 279 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_TSHUT_CONFIG BIT(1) BIT 280 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_TALERT BIT(2) BIT 281 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_MODE_CONFIG BIT(3) BIT 282 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_COUNTER BIT(4) BIT 283 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_POWER_SWITCH BIT(5) BIT 284 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_CLK_CTRL BIT(6) BIT 285 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_FREEZE_BIT BIT(7) BIT 286 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_COUNTER_DELAY BIT(8) BIT 287 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_HISTORY_BUFFER BIT(9) BIT 288 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_ERRATA_814 BIT(10) BIT 289 drivers/thermal/ti-soc-thermal/ti-bandgap.h #define TI_BANDGAP_FEATURE_UNRELIABLE BIT(11) BIT 27 drivers/thermal/uniphier_thermal.c #define PVTCTLEN_EN BIT(0) BIT 34 drivers/thermal/uniphier_thermal.c #define EMONREPEAT_ENDLESS BIT(24) BIT 51 drivers/thermal/uniphier_thermal.c #define SETALERT_EN BIT(0) BIT 54 drivers/thermal/uniphier_thermal.c #define PMALERTINTCTL_CLR(ch) BIT(4 * (ch) + 2) BIT 55 drivers/thermal/uniphier_thermal.c #define PMALERTINTCTL_SET(ch) BIT(4 * (ch) + 1) BIT 56 drivers/thermal/uniphier_thermal.c #define PMALERTINTCTL_EN(ch) BIT(4 * (ch) + 0) BIT 65 drivers/thermal/uniphier_thermal.c #define TMODSETUP0_EN BIT(30) BIT 67 drivers/thermal/uniphier_thermal.c #define TMODSETUP1_EN BIT(15) BIT 25 drivers/thermal/zx2967_thermal.c #define ZX2967_DCF_EN BIT(1) BIT 26 drivers/thermal/zx2967_thermal.c #define ZX2967_DCF_FREEZE BIT(0) BIT 34 drivers/thermal/zx2967_thermal.c #define ZX2967_THERMAL_READY BIT(12) BIT 16 drivers/thunderbolt/cap.c #define TMU_ACCESS_EN BIT(20) BIT 32 drivers/thunderbolt/dma_port.c #define MAIL_IN_CSS BIT(1) BIT 33 drivers/thunderbolt/dma_port.c #define MAIL_IN_OP_REQUEST BIT(0) BIT 36 drivers/thunderbolt/dma_port.c #define MAIL_OUT_STATUS_RESPONSE BIT(29) BIT 26 drivers/thunderbolt/icm.c #define PCIE2CIO_CMD_TIMEOUT BIT(31) BIT 27 drivers/thunderbolt/icm.c #define PCIE2CIO_CMD_START BIT(30) BIT 28 drivers/thunderbolt/icm.c #define PCIE2CIO_CMD_WRITE BIT(21) BIT 38 drivers/thunderbolt/icm.c #define PHY_PORT_CS1_LINK_DISABLE BIT(14) BIT 127 drivers/thunderbolt/icm.c #define INTEL_VSS_FLAGS_RTD3 BIT(0) BIT 957 drivers/thunderbolt/icm.c return pcie2cio_write(tb_priv(tb), TB_CFG_SWITCH, 0, 0x777, BIT(1)); BIT 1379 drivers/thunderbolt/icm.c return pcie2cio_write(tb_priv(tb), TB_CFG_SWITCH, 0, 0x50, BIT(9)); BIT 345 drivers/thunderbolt/nhi.c val &= ~BIT(bit); BIT 347 drivers/thunderbolt/nhi.c val |= BIT(bit); BIT 107 drivers/thunderbolt/nhi_regs.h #define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2) BIT 113 drivers/thunderbolt/nhi_regs.h #define REG_INMAIL_ERROR BIT(30) BIT 114 drivers/thunderbolt/nhi_regs.h #define REG_INMAIL_OP_REQUEST BIT(31) BIT 121 drivers/thunderbolt/nhi_regs.h #define REG_FW_STS_NVM_AUTH_DONE BIT(31) BIT 122 drivers/thunderbolt/nhi_regs.h #define REG_FW_STS_CIO_RESET_REQ BIT(30) BIT 123 drivers/thunderbolt/nhi_regs.h #define REG_FW_STS_ICM_EN_CPU BIT(2) BIT 124 drivers/thunderbolt/nhi_regs.h #define REG_FW_STS_ICM_EN_INVERT BIT(1) BIT 125 drivers/thunderbolt/nhi_regs.h #define REG_FW_STS_ICM_EN BIT(0) BIT 131 drivers/thunderbolt/nhi_regs.h #define VS_CAP_9_FW_READY BIT(31) BIT 140 drivers/thunderbolt/nhi_regs.h #define VS_CAP_18_DONE BIT(0) BIT 143 drivers/thunderbolt/nhi_regs.h #define VS_CAP_19_VALID BIT(0) BIT 148 drivers/thunderbolt/nhi_regs.h #define VS_CAP_22_FORCE_POWER BIT(1) BIT 121 drivers/thunderbolt/tb_msgs.h #define ICM_FLAGS_ERROR BIT(0) BIT 122 drivers/thunderbolt/tb_msgs.h #define ICM_FLAGS_NO_KEY BIT(1) BIT 125 drivers/thunderbolt/tb_msgs.h #define ICM_FLAGS_WRITE BIT(7) BIT 163 drivers/thunderbolt/tb_msgs.h #define ICM_SWITCH_USED BIT(0) BIT 183 drivers/thunderbolt/tb_msgs.h #define ICM_LINK_INFO_APPROVED BIT(8) BIT 184 drivers/thunderbolt/tb_msgs.h #define ICM_LINK_INFO_REJECTED BIT(9) BIT 185 drivers/thunderbolt/tb_msgs.h #define ICM_LINK_INFO_BOOT BIT(10) BIT 287 drivers/thunderbolt/tb_msgs.h #define ICM_AR_FLAGS_RTD3 BIT(6) BIT 292 drivers/thunderbolt/tb_msgs.h #define ICM_AR_INFO_BOOT_ACL_SUPPORTED BIT(13) BIT 336 drivers/thunderbolt/tb_msgs.h #define ICM_TR_FLAGS_RTD3 BIT(6) BIT 227 drivers/thunderbolt/tb_regs.h #define TB_DP_AUX_EN BIT(30) BIT 228 drivers/thunderbolt/tb_regs.h #define TB_DP_VIDEO_EN BIT(31) BIT 234 drivers/thunderbolt/tb_regs.h #define TB_DP_HDP BIT(6) BIT 236 drivers/thunderbolt/tb_regs.h #define TB_DP_HPDC BIT(9) BIT 244 drivers/thunderbolt/tb_regs.h #define TB_PCI_EN BIT(31) BIT 284 drivers/thunderbolt/tb_regs.h #define TB_LC_SX_CTRL_L1C BIT(16) BIT 285 drivers/thunderbolt/tb_regs.h #define TB_LC_SX_CTRL_L2C BIT(20) BIT 286 drivers/thunderbolt/tb_regs.h #define TB_LC_SX_CTRL_UPSTREAM BIT(30) BIT 287 drivers/thunderbolt/tb_regs.h #define TB_LC_SX_CTRL_SLP BIT(31) BIT 63 drivers/thunderbolt/xdomain.c if ((res_hdr->xd_hdr.route_hi & ~BIT(31)) != BIT 66 drivers/tty/mips_ejtag_fdc.c #define REG_FDSTAT_RXE BIT(3) /* Rx Empty */ BIT 67 drivers/tty/mips_ejtag_fdc.c #define REG_FDSTAT_RXF BIT(2) /* Rx Full */ BIT 68 drivers/tty/mips_ejtag_fdc.c #define REG_FDSTAT_TXE BIT(1) /* Tx Empty */ BIT 69 drivers/tty/mips_ejtag_fdc.c #define REG_FDSTAT_TXF BIT(0) /* Tx Full */ BIT 24 drivers/tty/serial/8250/8250_aspeed_vuart.c #define ASPEED_VUART_GCRA_VUART_EN BIT(0) BIT 25 drivers/tty/serial/8250/8250_aspeed_vuart.c #define ASPEED_VUART_GCRA_DISABLE_HOST_TX_DISCARD BIT(5) BIT 36 drivers/tty/serial/8250/8250_dw.c #define DW_UART_MCR_SIRE BIT(6) BIT 34 drivers/tty/serial/8250/8250_fintek.c #define IRQ_SHARE BIT(4) BIT 35 drivers/tty/serial/8250/8250_fintek.c #define IRQ_MODE_MASK (BIT(6) | BIT(5)) BIT 37 drivers/tty/serial/8250/8250_fintek.c #define IRQ_EDGE_HIGH BIT(5) BIT 50 drivers/tty/serial/8250/8250_fintek.c #define RTS_INVERT BIT(5) BIT 51 drivers/tty/serial/8250/8250_fintek.c #define RS485_URA BIT(4) BIT 52 drivers/tty/serial/8250/8250_fintek.c #define RXW4C_IRA BIT(3) BIT 53 drivers/tty/serial/8250/8250_fintek.c #define TXW4C_IRA BIT(2) BIT 56 drivers/tty/serial/8250/8250_fintek.c #define FIFO_MODE_MASK (BIT(1) | BIT(0)) BIT 57 drivers/tty/serial/8250/8250_fintek.c #define FIFO_MODE_128 (BIT(1) | BIT(0)) BIT 58 drivers/tty/serial/8250/8250_fintek.c #define RXFTHR_MODE_MASK (BIT(5) | BIT(4)) BIT 59 drivers/tty/serial/8250/8250_fintek.c #define RXFTHR_MODE_4X BIT(5) BIT 78 drivers/tty/serial/8250/8250_fintek.c #define F81866_IRQ_SHARE BIT(0) BIT 79 drivers/tty/serial/8250/8250_fintek.c #define F81866_IRQ_MODE0 BIT(1) BIT 82 drivers/tty/serial/8250/8250_fintek.c #define F81866_IRQ_MODE1 BIT(3) BIT 88 drivers/tty/serial/8250/8250_fintek.c #define F81866_UART_CLK_MASK (BIT(1) | BIT(0)) BIT 90 drivers/tty/serial/8250/8250_fintek.c #define F81866_UART_CLK_14_769MHZ (BIT(1) | BIT(0)) BIT 91 drivers/tty/serial/8250/8250_fintek.c #define F81866_UART_CLK_18_432MHZ BIT(0) BIT 92 drivers/tty/serial/8250/8250_fintek.c #define F81866_UART_CLK_24MHZ BIT(1) BIT 38 drivers/tty/serial/8250/8250_ingenic.c #define UART_FCR_UME BIT(4) BIT 40 drivers/tty/serial/8250/8250_ingenic.c #define UART_MCR_MDCE BIT(7) BIT 41 drivers/tty/serial/8250/8250_ingenic.c #define UART_MCR_FCM BIT(6) BIT 22 drivers/tty/serial/8250/8250_lpc18xx.c #define LPC18XX_UART_RS485CTRL_NMMEN BIT(0) BIT 23 drivers/tty/serial/8250/8250_lpc18xx.c #define LPC18XX_UART_RS485CTRL_DCTRL BIT(4) BIT 24 drivers/tty/serial/8250/8250_lpc18xx.c #define LPC18XX_UART_RS485CTRL_OINV BIT(5) BIT 40 drivers/tty/serial/8250/8250_lpss.c #define BYT_PRV_CLK_EN BIT(0) BIT 43 drivers/tty/serial/8250/8250_lpss.c #define BYT_PRV_CLK_UPDATE BIT(31) BIT 46 drivers/tty/serial/8250/8250_lpss.c #define BYT_TX_OVF_INT_MASK BIT(1) BIT 78 drivers/tty/serial/8250/8250_lpss.c unsigned long w = BIT(15) - 1; BIT 136 drivers/tty/serial/8250/8250_mid.c if (fisr & BIT(2)) { BIT 144 drivers/tty/serial/8250/8250_mid.c if (fisr & BIT(1)) { BIT 151 drivers/tty/serial/8250/8250_mid.c if (fisr & BIT(0)) BIT 207 drivers/tty/serial/8250/8250_mid.c unsigned long w = BIT(24) - 1; BIT 1461 drivers/tty/serial/8250/8250_pci.c #define FINTEK_RTS_CONTROL_BY_HW BIT(4) BIT 1463 drivers/tty/serial/8250/8250_pci.c #define FINTEK_RTS_INVERT BIT(5) BIT 45 drivers/tty/serial/8250/8250_port.c #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */ BIT 16 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RSTRX BIT(2) /* Reset Receiver */ BIT 17 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RSTTX BIT(3) /* Reset Transmitter */ BIT 18 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXEN BIT(4) /* Receiver Enable */ BIT 19 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXDIS BIT(5) /* Receiver Disable */ BIT 20 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXEN BIT(6) /* Transmitter Enable */ BIT 21 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXDIS BIT(7) /* Transmitter Disable */ BIT 22 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RSTSTA BIT(8) /* Reset Status Bits */ BIT 23 drivers/tty/serial/atmel_serial.h #define ATMEL_US_STTBRK BIT(9) /* Start Break */ BIT 24 drivers/tty/serial/atmel_serial.h #define ATMEL_US_STPBRK BIT(10) /* Stop Break */ BIT 25 drivers/tty/serial/atmel_serial.h #define ATMEL_US_STTTO BIT(11) /* Start Time-out */ BIT 26 drivers/tty/serial/atmel_serial.h #define ATMEL_US_SENDA BIT(12) /* Send Address */ BIT 27 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RSTIT BIT(13) /* Reset Iterations */ BIT 28 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RSTNACK BIT(14) /* Reset Non Acknowledge */ BIT 29 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RETTO BIT(15) /* Rearm Time-out */ BIT 30 drivers/tty/serial/atmel_serial.h #define ATMEL_US_DTREN BIT(16) /* Data Terminal Ready Enable */ BIT 31 drivers/tty/serial/atmel_serial.h #define ATMEL_US_DTRDIS BIT(17) /* Data Terminal Ready Disable */ BIT 32 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RTSEN BIT(18) /* Request To Send Enable */ BIT 33 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RTSDIS BIT(19) /* Request To Send Disable */ BIT 34 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXFCLR BIT(24) /* Transmit FIFO Clear */ BIT 35 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXFCLR BIT(25) /* Receive FIFO Clear */ BIT 36 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXFLCLR BIT(26) /* Transmit FIFO Lock Clear */ BIT 37 drivers/tty/serial/atmel_serial.h #define ATMEL_US_FIFOEN BIT(30) /* FIFO enable */ BIT 38 drivers/tty/serial/atmel_serial.h #define ATMEL_US_FIFODIS BIT(31) /* FIFO disable */ BIT 58 drivers/tty/serial/atmel_serial.h #define ATMEL_US_SYNC BIT(8) /* Synchronous Mode Select */ BIT 75 drivers/tty/serial/atmel_serial.h #define ATMEL_US_MSBF BIT(16) /* Bit Order */ BIT 76 drivers/tty/serial/atmel_serial.h #define ATMEL_US_MODE9 BIT(17) /* 9-bit Character Length */ BIT 77 drivers/tty/serial/atmel_serial.h #define ATMEL_US_CLKO BIT(18) /* Clock Output Select */ BIT 78 drivers/tty/serial/atmel_serial.h #define ATMEL_US_OVER BIT(19) /* Oversampling Mode */ BIT 79 drivers/tty/serial/atmel_serial.h #define ATMEL_US_INACK BIT(20) /* Inhibit Non Acknowledge */ BIT 80 drivers/tty/serial/atmel_serial.h #define ATMEL_US_DSNACK BIT(21) /* Disable Successive NACK */ BIT 83 drivers/tty/serial/atmel_serial.h #define ATMEL_US_FILTER BIT(28) /* Infrared Receive Line Filter */ BIT 86 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXRDY BIT(0) /* Receiver Ready */ BIT 87 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXRDY BIT(1) /* Transmitter Ready */ BIT 88 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXBRK BIT(2) /* Break Received / End of Break */ BIT 89 drivers/tty/serial/atmel_serial.h #define ATMEL_US_ENDRX BIT(3) /* End of Receiver Transfer */ BIT 90 drivers/tty/serial/atmel_serial.h #define ATMEL_US_ENDTX BIT(4) /* End of Transmitter Transfer */ BIT 91 drivers/tty/serial/atmel_serial.h #define ATMEL_US_OVRE BIT(5) /* Overrun Error */ BIT 92 drivers/tty/serial/atmel_serial.h #define ATMEL_US_FRAME BIT(6) /* Framing Error */ BIT 93 drivers/tty/serial/atmel_serial.h #define ATMEL_US_PARE BIT(7) /* Parity Error */ BIT 94 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TIMEOUT BIT(8) /* Receiver Time-out */ BIT 95 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXEMPTY BIT(9) /* Transmitter Empty */ BIT 96 drivers/tty/serial/atmel_serial.h #define ATMEL_US_ITERATION BIT(10) /* Max number of Repetitions Reached */ BIT 97 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXBUFE BIT(11) /* Transmission Buffer Empty */ BIT 98 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXBUFF BIT(12) /* Reception Buffer Full */ BIT 99 drivers/tty/serial/atmel_serial.h #define ATMEL_US_NACK BIT(13) /* Non Acknowledge */ BIT 100 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RIIC BIT(16) /* Ring Indicator Input Change */ BIT 101 drivers/tty/serial/atmel_serial.h #define ATMEL_US_DSRIC BIT(17) /* Data Set Ready Input Change */ BIT 102 drivers/tty/serial/atmel_serial.h #define ATMEL_US_DCDIC BIT(18) /* Data Carrier Detect Input Change */ BIT 103 drivers/tty/serial/atmel_serial.h #define ATMEL_US_CTSIC BIT(19) /* Clear to Send Input Change */ BIT 104 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RI BIT(20) /* RI */ BIT 105 drivers/tty/serial/atmel_serial.h #define ATMEL_US_DSR BIT(21) /* DSR */ BIT 106 drivers/tty/serial/atmel_serial.h #define ATMEL_US_DCD BIT(22) /* DCD */ BIT 107 drivers/tty/serial/atmel_serial.h #define ATMEL_US_CTS BIT(23) /* CTS */ BIT 114 drivers/tty/serial/atmel_serial.h #define ATMEL_US_SYNH BIT(15) /* Transmit/Receive Sync */ BIT 139 drivers/tty/serial/atmel_serial.h #define ATMEL_US_FRTSC BIT(7) /* FIFO RTS pin Control */ BIT 152 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXFEF BIT(0) /* Transmit FIFO Empty Flag */ BIT 153 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXFFF BIT(1) /* Transmit FIFO Full Flag */ BIT 154 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXFTHF BIT(2) /* Transmit FIFO Threshold Flag */ BIT 155 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXFEF BIT(3) /* Receive FIFO Empty Flag */ BIT 156 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXFFF BIT(4) /* Receive FIFO Full Flag */ BIT 157 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXFTHF BIT(5) /* Receive FIFO Threshold Flag */ BIT 158 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXFPTEF BIT(6) /* Transmit FIFO Pointer Error Flag */ BIT 159 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXFPTEF BIT(7) /* Receive FIFO Pointer Error Flag */ BIT 160 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXFLOCK BIT(8) /* Transmit FIFO Lock (FESR only) */ BIT 161 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXFTHF2 BIT(9) /* Receive FIFO Threshold Flag 2 */ BIT 23 drivers/tty/serial/digicolor-usart.c #define UA_ENABLE_ENABLE BIT(0) BIT 26 drivers/tty/serial/digicolor-usart.c #define UA_CONTROL_RX_ENABLE BIT(0) BIT 27 drivers/tty/serial/digicolor-usart.c #define UA_CONTROL_TX_ENABLE BIT(1) BIT 28 drivers/tty/serial/digicolor-usart.c #define UA_CONTROL_SOFT_RESET BIT(2) BIT 31 drivers/tty/serial/digicolor-usart.c #define UA_STATUS_PARITY_ERR BIT(0) BIT 32 drivers/tty/serial/digicolor-usart.c #define UA_STATUS_FRAME_ERR BIT(1) BIT 33 drivers/tty/serial/digicolor-usart.c #define UA_STATUS_OVERRUN_ERR BIT(2) BIT 34 drivers/tty/serial/digicolor-usart.c #define UA_STATUS_TX_READY BIT(6) BIT 37 drivers/tty/serial/digicolor-usart.c #define UA_CONFIG_CHAR_LEN BIT(0) BIT 38 drivers/tty/serial/digicolor-usart.c #define UA_CONFIG_STOP_BITS BIT(1) BIT 39 drivers/tty/serial/digicolor-usart.c #define UA_CONFIG_PARITY BIT(2) BIT 40 drivers/tty/serial/digicolor-usart.c #define UA_CONFIG_ODD_PARITY BIT(4) BIT 48 drivers/tty/serial/digicolor-usart.c #define UA_STATUS_FIFO_RX_EMPTY BIT(2) BIT 49 drivers/tty/serial/digicolor-usart.c #define UA_STATUS_FIFO_RX_INT_ALMOST BIT(3) BIT 50 drivers/tty/serial/digicolor-usart.c #define UA_STATUS_FIFO_TX_FULL BIT(4) BIT 51 drivers/tty/serial/digicolor-usart.c #define UA_STATUS_FIFO_TX_INT_ALMOST BIT(7) BIT 55 drivers/tty/serial/digicolor-usart.c #define UA_CONFIG_FIFO_RX_FIFO_MODE BIT(3) BIT 56 drivers/tty/serial/digicolor-usart.c #define UA_CONFIG_FIFO_TX_FIFO_MODE BIT(7) BIT 63 drivers/tty/serial/digicolor-usart.c #define UA_INT_TX BIT(0) BIT 64 drivers/tty/serial/digicolor-usart.c #define UA_INT_RX BIT(1) BIT 54 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINCR1_INIT BIT(0) BIT 55 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINCR1_MME BIT(4) BIT 56 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINCR1_BF BIT(7) BIT 58 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINSR_LINS_INITMODE BIT(12) BIT 61 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_SZIE BIT(15) BIT 62 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_OCIE BIT(14) BIT 63 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_BEIE BIT(13) BIT 64 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_CEIE BIT(12) BIT 65 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_HEIE BIT(11) BIT 66 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_FEIE BIT(8) BIT 67 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_BOIE BIT(7) BIT 68 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_LSIE BIT(6) BIT 69 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_WUIE BIT(5) BIT 70 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_DBFIE BIT(4) BIT 71 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_DBEIETOIE BIT(3) BIT 72 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_DRIE BIT(2) BIT 73 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_DTIE BIT(1) BIT 74 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_LINIER_HRIE BIT(0) BIT 80 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_ROSE BIT(23) BIT 82 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_RFBM BIT(9) BIT 83 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_TFBM BIT(8) BIT 84 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_WL1 BIT(7) BIT 85 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_PC1 BIT(6) BIT 87 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_RXEN BIT(5) BIT 88 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_TXEN BIT(4) BIT 89 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_PC0 BIT(3) BIT 91 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_PCE BIT(2) BIT 92 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_WL0 BIT(1) BIT 93 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTCR_UART BIT(0) BIT 95 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_SZF BIT(15) BIT 96 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_OCF BIT(14) BIT 97 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_PE3 BIT(13) BIT 98 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_PE2 BIT(12) BIT 99 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_PE1 BIT(11) BIT 100 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_PE0 BIT(10) BIT 101 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_RMB BIT(9) BIT 102 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_FEF BIT(8) BIT 103 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_BOF BIT(7) BIT 104 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_RPS BIT(6) BIT 105 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_WUF BIT(5) BIT 106 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_4 BIT(4) BIT 108 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_TO BIT(3) BIT 110 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_DRFRFE BIT(2) BIT 111 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_DTFTFF BIT(1) BIT 112 drivers/tty/serial/fsl_linflexuart.c #define LINFLEXD_UARTSR_NF BIT(0) BIT 37 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_IER_RXCIEN BIT(0) /* RX Space IRQ */ BIT 38 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_IER_TXCIEN BIT(1) /* TX Space IRQ */ BIT 39 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_IER_RLSIEN BIT(2) /* Receiver Line Status IRQ */ BIT 40 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_IER_MSIEN BIT(3) /* Modem Status IRQ */ BIT 46 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MCR_DTR BIT(24) BIT 47 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MCR_RTS BIT(25) BIT 48 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MCR_OUT1 BIT(26) BIT 49 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MCR_OUT2 BIT(27) BIT 50 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MCR_LOOP BIT(28) BIT 51 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MCR_RCFC BIT(29) BIT 53 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MSR_DCTS BIT(0) BIT 54 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MSR_DDSR BIT(1) BIT 55 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MSR_DRI BIT(2) BIT 56 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MSR_DDCD BIT(3) BIT 57 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MSR_CTS BIT(4) BIT 58 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MSR_DSR BIT(5) BIT 59 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MSR_RI BIT(6) BIT 60 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_MSR_DCD BIT(7) BIT 81 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_LSR_DR BIT(0) BIT 82 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_LSR_OE BIT(1) BIT 83 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_LSR_PE BIT(2) BIT 84 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_LSR_FE BIT(3) BIT 85 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_LSR_BI BIT(4) BIT 86 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_LSR_THEP BIT(5) BIT 87 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_LSR_TEXP BIT(6) BIT 88 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_LSR_RXFIFOERR BIT(7) BIT 90 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_IRQ_ID_RLS BIT(0) BIT 91 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_IRQ_ID_RDA BIT(1) BIT 92 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_IRQ_ID_CTI BIT(2) BIT 93 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_IRQ_ID_TSA BIT(3) BIT 94 drivers/tty/serial/men_z135_uart.c #define MEN_Z135_IRQ_ID_MST BIT(4) BIT 35 drivers/tty/serial/meson_uart.c #define AML_UART_TX_EN BIT(12) BIT 36 drivers/tty/serial/meson_uart.c #define AML_UART_RX_EN BIT(13) BIT 37 drivers/tty/serial/meson_uart.c #define AML_UART_TWO_WIRE_EN BIT(15) BIT 41 drivers/tty/serial/meson_uart.c #define AML_UART_PARITY_TYPE BIT(18) BIT 42 drivers/tty/serial/meson_uart.c #define AML_UART_PARITY_EN BIT(19) BIT 43 drivers/tty/serial/meson_uart.c #define AML_UART_TX_RST BIT(22) BIT 44 drivers/tty/serial/meson_uart.c #define AML_UART_RX_RST BIT(23) BIT 45 drivers/tty/serial/meson_uart.c #define AML_UART_CLEAR_ERR BIT(24) BIT 46 drivers/tty/serial/meson_uart.c #define AML_UART_RX_INT_EN BIT(27) BIT 47 drivers/tty/serial/meson_uart.c #define AML_UART_TX_INT_EN BIT(28) BIT 55 drivers/tty/serial/meson_uart.c #define AML_UART_PARITY_ERR BIT(16) BIT 56 drivers/tty/serial/meson_uart.c #define AML_UART_FRAME_ERR BIT(17) BIT 57 drivers/tty/serial/meson_uart.c #define AML_UART_TX_FIFO_WERR BIT(18) BIT 58 drivers/tty/serial/meson_uart.c #define AML_UART_RX_EMPTY BIT(20) BIT 59 drivers/tty/serial/meson_uart.c #define AML_UART_TX_FULL BIT(21) BIT 60 drivers/tty/serial/meson_uart.c #define AML_UART_TX_EMPTY BIT(22) BIT 61 drivers/tty/serial/meson_uart.c #define AML_UART_XMIT_BUSY BIT(25) BIT 72 drivers/tty/serial/meson_uart.c #define AML_UART_BAUD_USE BIT(23) BIT 73 drivers/tty/serial/meson_uart.c #define AML_UART_BAUD_XTAL BIT(24) BIT 37 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SMR_SOE BIT(0) BIT 38 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SMR_SBL BIT(3) BIT 39 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SCR_TXE BIT(0) BIT 40 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SCR_RXE BIT(1) BIT 41 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SCR_TBIE BIT(2) BIT 42 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SCR_TIE BIT(3) BIT 43 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SCR_RIE BIT(4) BIT 44 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SCR_UPCL BIT(7) BIT 49 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_ESCR_P BIT(3) BIT 50 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_ESCR_PEN BIT(4) BIT 51 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_ESCR_FLWEN BIT(7) BIT 52 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SSR_TBI BIT(0) BIT 53 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SSR_TDRE BIT(1) BIT 54 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SSR_RDRF BIT(2) BIT 55 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SSR_ORE BIT(3) BIT 56 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SSR_FRE BIT(4) BIT 57 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SSR_PE BIT(5) BIT 58 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SSR_REC BIT(7) BIT 59 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_SSR_BRK BIT(8) BIT 60 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_FCR_FE1 BIT(0) BIT 61 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_FCR_FE2 BIT(1) BIT 62 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_FCR_FCL1 BIT(2) BIT 63 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_FCR_FCL2 BIT(3) BIT 64 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_FCR_FSET BIT(4) BIT 65 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_FCR_FTIE BIT(9) BIT 66 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_FCR_FDRQ BIT(10) BIT 67 drivers/tty/serial/milbeaut_usio.c #define MLB_USIO_FCR_FRIIE BIT(11) BIT 287 drivers/tty/serial/milbeaut_usio.c writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE); BIT 372 drivers/tty/serial/milbeaut_usio.c writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE); BIT 34 drivers/tty/serial/mps2-uart.c #define UARTn_STATE_TX_FULL BIT(0) BIT 35 drivers/tty/serial/mps2-uart.c #define UARTn_STATE_RX_FULL BIT(1) BIT 36 drivers/tty/serial/mps2-uart.c #define UARTn_STATE_TX_OVERRUN BIT(2) BIT 37 drivers/tty/serial/mps2-uart.c #define UARTn_STATE_RX_OVERRUN BIT(3) BIT 40 drivers/tty/serial/mps2-uart.c #define UARTn_CTRL_TX_ENABLE BIT(0) BIT 41 drivers/tty/serial/mps2-uart.c #define UARTn_CTRL_RX_ENABLE BIT(1) BIT 42 drivers/tty/serial/mps2-uart.c #define UARTn_CTRL_TX_INT_ENABLE BIT(2) BIT 43 drivers/tty/serial/mps2-uart.c #define UARTn_CTRL_RX_INT_ENABLE BIT(3) BIT 44 drivers/tty/serial/mps2-uart.c #define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4) BIT 45 drivers/tty/serial/mps2-uart.c #define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5) BIT 48 drivers/tty/serial/mps2-uart.c #define UARTn_INT_TX BIT(0) BIT 49 drivers/tty/serial/mps2-uart.c #define UARTn_INT_RX BIT(1) BIT 50 drivers/tty/serial/mps2-uart.c #define UARTn_INT_TX_OVERRUN BIT(2) BIT 51 drivers/tty/serial/mps2-uart.c #define UARTn_INT_RX_OVERRUN BIT(3) BIT 69 drivers/tty/serial/mps2-uart.c #define UART_PORT_COMBINED_IRQ BIT(0) BIT 40 drivers/tty/serial/msm_serial.c #define UART_MR1_RX_RDY_CTL BIT(7) BIT 41 drivers/tty/serial/msm_serial.c #define UART_MR1_CTS_CTL BIT(6) BIT 44 drivers/tty/serial/msm_serial.c #define UART_MR2_ERROR_MODE BIT(6) BIT 82 drivers/tty/serial/msm_serial.c #define UART_CR_TX_DISABLE BIT(3) BIT 83 drivers/tty/serial/msm_serial.c #define UART_CR_TX_ENABLE BIT(2) BIT 84 drivers/tty/serial/msm_serial.c #define UART_CR_RX_DISABLE BIT(1) BIT 85 drivers/tty/serial/msm_serial.c #define UART_CR_RX_ENABLE BIT(0) BIT 89 drivers/tty/serial/msm_serial.c #define UART_IMR_TXLEV BIT(0) BIT 90 drivers/tty/serial/msm_serial.c #define UART_IMR_RXSTALE BIT(3) BIT 91 drivers/tty/serial/msm_serial.c #define UART_IMR_RXLEV BIT(4) BIT 92 drivers/tty/serial/msm_serial.c #define UART_IMR_DELTA_CTS BIT(5) BIT 93 drivers/tty/serial/msm_serial.c #define UART_IMR_CURRENT_CTS BIT(6) BIT 94 drivers/tty/serial/msm_serial.c #define UART_IMR_RXBREAK_START BIT(10) BIT 118 drivers/tty/serial/msm_serial.c #define UART_SR_HUNT_CHAR BIT(7) BIT 119 drivers/tty/serial/msm_serial.c #define UART_SR_RX_BREAK BIT(6) BIT 120 drivers/tty/serial/msm_serial.c #define UART_SR_PAR_FRAME_ERR BIT(5) BIT 121 drivers/tty/serial/msm_serial.c #define UART_SR_OVERRUN BIT(4) BIT 122 drivers/tty/serial/msm_serial.c #define UART_SR_TX_EMPTY BIT(3) BIT 123 drivers/tty/serial/msm_serial.c #define UART_SR_TX_READY BIT(2) BIT 124 drivers/tty/serial/msm_serial.c #define UART_SR_RX_FULL BIT(1) BIT 125 drivers/tty/serial/msm_serial.c #define UART_SR_RX_READY BIT(0) BIT 131 drivers/tty/serial/msm_serial.c #define UART_ISR_TX_READY BIT(7) BIT 138 drivers/tty/serial/msm_serial.c #define UARTDM_DMEN_RX_SC_ENABLE BIT(5) BIT 139 drivers/tty/serial/msm_serial.c #define UARTDM_DMEN_TX_SC_ENABLE BIT(4) BIT 141 drivers/tty/serial/msm_serial.c #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */ BIT 142 drivers/tty/serial/msm_serial.c #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */ BIT 144 drivers/tty/serial/msm_serial.c #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */ BIT 145 drivers/tty/serial/msm_serial.c #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */ BIT 38 drivers/tty/serial/mvebu-uart.c #define CTRL_SOFT_RST BIT(31) BIT 39 drivers/tty/serial/mvebu-uart.c #define CTRL_TXFIFO_RST BIT(15) BIT 40 drivers/tty/serial/mvebu-uart.c #define CTRL_RXFIFO_RST BIT(14) BIT 41 drivers/tty/serial/mvebu-uart.c #define CTRL_SND_BRK_SEQ BIT(11) BIT 42 drivers/tty/serial/mvebu-uart.c #define CTRL_BRK_DET_INT BIT(3) BIT 43 drivers/tty/serial/mvebu-uart.c #define CTRL_FRM_ERR_INT BIT(2) BIT 44 drivers/tty/serial/mvebu-uart.c #define CTRL_PAR_ERR_INT BIT(1) BIT 45 drivers/tty/serial/mvebu-uart.c #define CTRL_OVR_ERR_INT BIT(0) BIT 51 drivers/tty/serial/mvebu-uart.c #define CTRL_STD_TX_RDY_INT BIT(5) BIT 52 drivers/tty/serial/mvebu-uart.c #define CTRL_EXT_TX_RDY_INT BIT(6) BIT 53 drivers/tty/serial/mvebu-uart.c #define CTRL_STD_RX_RDY_INT BIT(4) BIT 54 drivers/tty/serial/mvebu-uart.c #define CTRL_EXT_RX_RDY_INT BIT(5) BIT 57 drivers/tty/serial/mvebu-uart.c #define STAT_TX_FIFO_EMP BIT(13) BIT 58 drivers/tty/serial/mvebu-uart.c #define STAT_TX_FIFO_FUL BIT(11) BIT 59 drivers/tty/serial/mvebu-uart.c #define STAT_TX_EMP BIT(6) BIT 60 drivers/tty/serial/mvebu-uart.c #define STAT_STD_TX_RDY BIT(5) BIT 61 drivers/tty/serial/mvebu-uart.c #define STAT_EXT_TX_RDY BIT(15) BIT 62 drivers/tty/serial/mvebu-uart.c #define STAT_STD_RX_RDY BIT(4) BIT 63 drivers/tty/serial/mvebu-uart.c #define STAT_EXT_RX_RDY BIT(14) BIT 64 drivers/tty/serial/mvebu-uart.c #define STAT_BRK_DET BIT(3) BIT 65 drivers/tty/serial/mvebu-uart.c #define STAT_FRM_ERR BIT(2) BIT 66 drivers/tty/serial/mvebu-uart.c #define STAT_PAR_ERR BIT(1) BIT 67 drivers/tty/serial/mvebu-uart.c #define STAT_OVR_ERR BIT(0) BIT 133 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28) BIT 135 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25) BIT 142 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24) BIT 164 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28) BIT 182 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL2_DTR BIT(10) BIT 184 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL2_LBE BIT(7) BIT 185 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0) BIT 194 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_LCTRL_SPS BIT(7) BIT 208 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_TFEIEN BIT(27) BIT 210 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_OEIEN BIT(26) BIT 212 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_BEIEN BIT(25) BIT 214 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_PEIEN BIT(24) BIT 216 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_FEIEN BIT(23) BIT 219 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_DSRMIEN BIT(19) BIT 221 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_DCDMIEN BIT(18) BIT 223 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_RIMIEN BIT(16) BIT 225 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_ABTO BIT(13) BIT 226 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_ABEO BIT(12) BIT 228 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_TFEIS BIT(11) BIT 230 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_OEIS BIT(10) BIT 232 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_BEIS BIT(9) BIT 234 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_PEIS BIT(8) BIT 236 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_FEIS BIT(7) BIT 237 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_DSRMIS BIT(3) BIT 238 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_DCDMIS BIT(2) BIT 239 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_INTR_RIMIS BIT(0) BIT 250 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_STAT_PRESENT BIT(31) BIT 252 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_STAT_HISPEED BIT(30) BIT 254 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_STAT_RXFULL BIT(26) BIT 259 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_DEBUG_TXDMARUN BIT(5) BIT 260 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_DEBUG_RXDMARUN BIT(4) BIT 262 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_DEBUG_TXCMDEND BIT(3) BIT 263 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_DEBUG_RXCMDEND BIT(2) BIT 265 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_DEBUG_TXDMARQ BIT(1) BIT 266 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_DEBUG_RXDMARQ BIT(0) BIT 278 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_RS485CTRL_ONIV BIT(5) BIT 280 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4) BIT 285 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_RS485CTRL_PINSEL BIT(3) BIT 287 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_RS485CTRL_AADEN BIT(2) BIT 289 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_RS485CTRL_RXDIS BIT(1) BIT 291 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_RS485CTRL_RS485EN BIT(0) BIT 306 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9) BIT 308 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8) BIT 310 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2) BIT 312 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_AUTOBAUD_MODE BIT(1) BIT 317 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_AUTOBAUD_START BIT(0) BIT 325 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL3_MASTERMODE BIT(6) BIT 327 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL3_SYNCMODE BIT(4) BIT 329 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL3_MSBF BIT(2) BIT 331 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL3_BAUD8 BIT(1) BIT 333 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_CTRL3_9BIT BIT(0) BIT 337 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_ISO7816CTRL_HS BIT(12) BIT 339 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8) BIT 342 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_ISO7816CTRL_INACK BIT(3) BIT 343 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2) BIT 345 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0) BIT 353 drivers/tty/serial/mxs-auart.c #define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0) BIT 55 drivers/tty/serial/omap-serial.c #define OMAP_UART_TX_WAKEUP_EN BIT(7) BIT 58 drivers/tty/serial/omap-serial.c #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0) BIT 60 drivers/tty/serial/omap-serial.c #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) BIT 61 drivers/tty/serial/omap-serial.c #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) BIT 36 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_STPS_2BITS BIT(2) BIT 43 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_AFE BIT(12) BIT 44 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_TRFS_TX BIT(14) BIT 45 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_EN BIT(15) BIT 46 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_RXDE BIT(16) BIT 47 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_TXDE BIT(17) BIT 48 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_RXIE BIT(18) BIT 49 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_TXIE BIT(19) BIT 50 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_LBEN BIT(20) BIT 52 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_RIP BIT(0) BIT 53 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_TIP BIT(1) BIT 54 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_RXER BIT(2) BIT 55 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_TFER BIT(3) BIT 56 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_RXST BIT(4) BIT 57 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_RFEM BIT(5) BIT 58 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_TFFU BIT(6) BIT 59 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_CTSS BIT(7) BIT 60 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_RTSS BIT(8) BIT 61 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_TFES BIT(10) BIT 63 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_UTBB BIT(17) BIT 90 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_ON BIT(15) BIT 91 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_FRZ BIT(14) BIT 92 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_SIDL BIT(13) BIT 93 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_IREN BIT(12) BIT 94 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_RTSMD BIT(11) BIT 95 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_RESV1 BIT(10) BIT 96 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_UEN1 BIT(9) BIT 97 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_UEN0 BIT(8) BIT 98 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_WAKE BIT(7) BIT 99 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_LPBK BIT(6) BIT 100 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_ABAUD BIT(5) BIT 101 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_RXINV BIT(4) BIT 102 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_BRGH BIT(3) BIT 103 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_PDSEL1 BIT(2) BIT 104 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_PDSEL0 BIT(1) BIT 105 drivers/tty/serial/pic32_uart.h #define PIC32_UART_MODE_STSEL BIT(0) BIT 108 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_UTXISEL1 BIT(15) BIT 109 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_UTXISEL0 BIT(14) BIT 110 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_UTXINV BIT(13) BIT 111 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_URXEN BIT(12) BIT 112 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_UTXBRK BIT(11) BIT 113 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_UTXEN BIT(10) BIT 114 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_UTXBF BIT(9) BIT 115 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_TRMT BIT(8) BIT 116 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_URXISEL1 BIT(7) BIT 117 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_URXISEL0 BIT(6) BIT 118 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_ADDEN BIT(5) BIT 119 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_RIDLE BIT(4) BIT 120 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_PERR BIT(3) BIT 121 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_FERR BIT(2) BIT 122 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_OERR BIT(1) BIT 123 drivers/tty/serial/pic32_uart.h #define PIC32_UART_STA_URXDA BIT(0) BIT 37 drivers/tty/serial/qcom_geni_serial.c #define UART_TX_PAR_EN BIT(0) BIT 38 drivers/tty/serial/qcom_geni_serial.c #define UART_CTS_MASK BIT(1) BIT 53 drivers/tty/serial/qcom_geni_serial.c #define UART_RX_INS_STATUS_BIT BIT(2) BIT 54 drivers/tty/serial/qcom_geni_serial.c #define UART_RX_PAR_EN BIT(3) BIT 63 drivers/tty/serial/qcom_geni_serial.c #define PAR_CALC_EN BIT(0) BIT 72 drivers/tty/serial/qcom_geni_serial.c #define UART_MANUAL_RFR_EN BIT(31) BIT 73 drivers/tty/serial/qcom_geni_serial.c #define UART_RFR_NOT_READY BIT(1) BIT 74 drivers/tty/serial/qcom_geni_serial.c #define UART_RFR_READY BIT(0) BIT 35 drivers/tty/serial/rda-uart.c #define RDA_UART_ENABLE BIT(0) BIT 36 drivers/tty/serial/rda-uart.c #define RDA_UART_DBITS_8 BIT(1) BIT 37 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_SBITS_2 BIT(2) BIT 38 drivers/tty/serial/rda-uart.c #define RDA_UART_PARITY_EN BIT(3) BIT 44 drivers/tty/serial/rda-uart.c #define RDA_UART_DIV_MODE BIT(20) BIT 45 drivers/tty/serial/rda-uart.c #define RDA_UART_IRDA_EN BIT(21) BIT 46 drivers/tty/serial/rda-uart.c #define RDA_UART_DMA_EN BIT(22) BIT 47 drivers/tty/serial/rda-uart.c #define RDA_UART_FLOW_CNT_EN BIT(23) BIT 48 drivers/tty/serial/rda-uart.c #define RDA_UART_LOOP_BACK_EN BIT(24) BIT 49 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_LOCK_ERR BIT(25) BIT 57 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_ACTIVE BIT(14) BIT 58 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_ACTIVE BIT(15) BIT 59 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_OVERFLOW_ERR BIT(16) BIT 60 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_OVERFLOW_ERR BIT(17) BIT 61 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_PARITY_ERR BIT(18) BIT 62 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_FRAMING_ERR BIT(19) BIT 63 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_BREAK_INT BIT(20) BIT 64 drivers/tty/serial/rda-uart.c #define RDA_UART_DCTS BIT(24) BIT 65 drivers/tty/serial/rda-uart.c #define RDA_UART_CTS BIT(25) BIT 66 drivers/tty/serial/rda-uart.c #define RDA_UART_DTR BIT(28) BIT 67 drivers/tty/serial/rda-uart.c #define RDA_UART_CLK_ENABLED BIT(31) BIT 74 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_MODEM_STATUS BIT(0) BIT 75 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_DATA_AVAILABLE BIT(1) BIT 76 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_DATA_NEEDED BIT(2) BIT 77 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_TIMEOUT BIT(3) BIT 78 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_LINE_ERR BIT(4) BIT 79 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_DMA_DONE BIT(5) BIT 80 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_DMA_DONE BIT(6) BIT 81 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_DMA_TIMEOUT BIT(7) BIT 82 drivers/tty/serial/rda-uart.c #define RDA_UART_DTR_RISE BIT(8) BIT 83 drivers/tty/serial/rda-uart.c #define RDA_UART_DTR_FALL BIT(9) BIT 86 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_MODEM_STATUS_U BIT(16) BIT 87 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_DATA_AVAILABLE_U BIT(17) BIT 88 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_DATA_NEEDED_U BIT(18) BIT 89 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_TIMEOUT_U BIT(19) BIT 90 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_LINE_ERR_U BIT(20) BIT 91 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_DMA_DONE_U BIT(21) BIT 92 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_DMA_DONE_U BIT(22) BIT 93 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_DMA_TIMEOUT_U BIT(23) BIT 94 drivers/tty/serial/rda-uart.c #define RDA_UART_DTR_RISE_U BIT(24) BIT 95 drivers/tty/serial/rda-uart.c #define RDA_UART_DTR_FALL_U BIT(25) BIT 103 drivers/tty/serial/rda-uart.c #define RDA_UART_RI BIT(0) BIT 104 drivers/tty/serial/rda-uart.c #define RDA_UART_DCD BIT(1) BIT 105 drivers/tty/serial/rda-uart.c #define RDA_UART_DSR BIT(2) BIT 106 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_BREAK_CONTROL BIT(3) BIT 107 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_FINISH_N_WAIT BIT(4) BIT 108 drivers/tty/serial/rda-uart.c #define RDA_UART_RTS BIT(5) BIT 109 drivers/tty/serial/rda-uart.c #define RDA_UART_RX_FIFO_RESET BIT(6) BIT 110 drivers/tty/serial/rda-uart.c #define RDA_UART_TX_FIFO_RESET BIT(7) BIT 44 drivers/tty/serial/rp2.c #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1) BIT 54 drivers/tty/serial/rp2.c #define RP2_IRQ_MASK_EN_m BIT(0) BIT 71 drivers/tty/serial/rp2.c #define RP2_ASIC_IRQ_EN_m BIT(20) BIT 79 drivers/tty/serial/rp2.c #define RP2_DATA_BYTE_ERR_PARITY_m BIT(8) BIT 80 drivers/tty/serial/rp2.c #define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9) BIT 81 drivers/tty/serial/rp2.c #define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10) BIT 82 drivers/tty/serial/rp2.c #define RP2_DATA_BYTE_BREAK_m BIT(11) BIT 85 drivers/tty/serial/rp2.c #define RP2_DUMMY_READ BIT(16) BIT 96 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_RXDATA_m BIT(0) BIT 97 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_DCD_m BIT(3) BIT 98 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_DSR_m BIT(4) BIT 99 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_CTS_m BIT(5) BIT 100 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_RI_m BIT(6) BIT 101 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_OVERRUN_m BIT(13) BIT 102 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16) BIT 103 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17) BIT 104 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_CD_CHANGED_m BIT(18) BIT 105 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_RI_CHANGED_m BIT(22) BIT 106 drivers/tty/serial/rp2.c #define RP2_CHAN_STAT_TXEMPTY_m BIT(25) BIT 114 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_MSRIRQ_m BIT(0) BIT 115 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_RXIRQ_m BIT(2) BIT 121 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_RX_EN_m BIT(5) BIT 122 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_RTSFLOW_m BIT(6) BIT 123 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_DTRFLOW_m BIT(7) BIT 126 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_DSRFLOW_m BIT(18) BIT 127 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_TXIRQ_m BIT(19) BIT 128 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_CTSFLOW_m BIT(23) BIT 129 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_TX_EN_m BIT(24) BIT 130 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_RTS_m BIT(25) BIT 131 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_DTR_m BIT(26) BIT 132 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_LOOP_m BIT(27) BIT 133 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_BREAK_m BIT(28) BIT 134 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_CMSPAR_m BIT(29) BIT 135 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_nPARODD_m BIT(30) BIT 136 drivers/tty/serial/rp2.c #define RP2_TXRX_CTL_PARENB_m BIT(31) BIT 142 drivers/tty/serial/rp2.c #define RP2_UART_CTL_FLUSH_RX_m BIT(3) BIT 143 drivers/tty/serial/rp2.c #define RP2_UART_CTL_FLUSH_TX_m BIT(4) BIT 144 drivers/tty/serial/rp2.c #define RP2_UART_CTL_RESET_CH_m BIT(5) BIT 145 drivers/tty/serial/rp2.c #define RP2_UART_CTL_XMIT_EN_m BIT(6) BIT 152 drivers/tty/serial/rp2.c #define RP2_UART_CTL_STOPBITS_m BIT(10) BIT 262 drivers/tty/serial/rp2.c irq_mask &= ~BIT(ch_num); BIT 264 drivers/tty/serial/rp2.c irq_mask |= BIT(ch_num); BIT 610 drivers/tty/serial/rp2.c clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9); BIT 1135 drivers/tty/serial/sc16is7xx.c return !!(val & BIT(offset)); BIT 1143 drivers/tty/serial/sc16is7xx.c sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), BIT 1144 drivers/tty/serial/sc16is7xx.c val ? BIT(offset) : 0); BIT 1153 drivers/tty/serial/sc16is7xx.c sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); BIT 1166 drivers/tty/serial/sc16is7xx.c state |= BIT(offset); BIT 1168 drivers/tty/serial/sc16is7xx.c state &= ~BIT(offset); BIT 1170 drivers/tty/serial/sc16is7xx.c sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), BIT 1171 drivers/tty/serial/sc16is7xx.c BIT(offset)); BIT 90 drivers/tty/serial/sh-sci.c #define SCI_SR(x) BIT((x) - 1) BIT 3159 drivers/tty/serial/sh-sci.c sci_ports_in_use &= ~BIT(port->port.line); BIT 3277 drivers/tty/serial/sh-sci.c if (sci_ports_in_use & BIT(index)) BIT 3373 drivers/tty/serial/sh-sci.c sci_ports_in_use |= BIT(dev_id); BIT 41 drivers/tty/serial/sh-sci.h #define SCSMR_C_A BIT(7) /* Communication Mode */ BIT 42 drivers/tty/serial/sh-sci.h #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */ BIT 44 drivers/tty/serial/sh-sci.h #define SCSMR_CHR BIT(6) /* 7-bit Character Length */ BIT 45 drivers/tty/serial/sh-sci.h #define SCSMR_PE BIT(5) /* Parity Enable */ BIT 46 drivers/tty/serial/sh-sci.h #define SCSMR_ODD BIT(4) /* Odd Parity */ BIT 47 drivers/tty/serial/sh-sci.h #define SCSMR_STOP BIT(3) /* Stop Bit Length */ BIT 51 drivers/tty/serial/sh-sci.h #define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */ BIT 63 drivers/tty/serial/sh-sci.h #define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */ BIT 64 drivers/tty/serial/sh-sci.h #define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */ BIT 70 drivers/tty/serial/sh-sci.h #define SCI_TDRE BIT(7) /* Transmit Data Register Empty */ BIT 71 drivers/tty/serial/sh-sci.h #define SCI_RDRF BIT(6) /* Receive Data Register Full */ BIT 72 drivers/tty/serial/sh-sci.h #define SCI_ORER BIT(5) /* Overrun Error */ BIT 73 drivers/tty/serial/sh-sci.h #define SCI_FER BIT(4) /* Framing Error */ BIT 74 drivers/tty/serial/sh-sci.h #define SCI_PER BIT(3) /* Parity Error */ BIT 75 drivers/tty/serial/sh-sci.h #define SCI_TEND BIT(2) /* Transmit End */ BIT 86 drivers/tty/serial/sh-sci.h #define SCIF_ER BIT(7) /* Receive Error */ BIT 87 drivers/tty/serial/sh-sci.h #define SCIF_TEND BIT(6) /* Transmission End */ BIT 88 drivers/tty/serial/sh-sci.h #define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */ BIT 89 drivers/tty/serial/sh-sci.h #define SCIF_BRK BIT(4) /* Break Detect */ BIT 90 drivers/tty/serial/sh-sci.h #define SCIF_FER BIT(3) /* Framing Error */ BIT 91 drivers/tty/serial/sh-sci.h #define SCIF_PER BIT(2) /* Parity Error */ BIT 92 drivers/tty/serial/sh-sci.h #define SCIF_RDF BIT(1) /* Receive FIFO Data Full */ BIT 93 drivers/tty/serial/sh-sci.h #define SCIF_DR BIT(0) /* Receive Data Ready */ BIT 98 drivers/tty/serial/sh-sci.h #define SCIFA_ORER BIT(9) /* Overrun Error */ BIT 108 drivers/tty/serial/sh-sci.h #define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */ BIT 109 drivers/tty/serial/sh-sci.h #define SCFCR_RTRG0 BIT(6) BIT 110 drivers/tty/serial/sh-sci.h #define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */ BIT 111 drivers/tty/serial/sh-sci.h #define SCFCR_TTRG0 BIT(4) BIT 112 drivers/tty/serial/sh-sci.h #define SCFCR_MCE BIT(3) /* Modem Control Enable */ BIT 113 drivers/tty/serial/sh-sci.h #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */ BIT 114 drivers/tty/serial/sh-sci.h #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */ BIT 115 drivers/tty/serial/sh-sci.h #define SCFCR_LOOP BIT(0) /* Loopback Test */ BIT 118 drivers/tty/serial/sh-sci.h #define SCLSR_TO BIT(2) /* Timeout */ BIT 119 drivers/tty/serial/sh-sci.h #define SCLSR_ORER BIT(0) /* Overrun Error */ BIT 122 drivers/tty/serial/sh-sci.h #define SCSPTR_RTSIO BIT(7) /* Serial Port RTS# Pin Input/Output */ BIT 123 drivers/tty/serial/sh-sci.h #define SCSPTR_RTSDT BIT(6) /* Serial Port RTS# Pin Data */ BIT 124 drivers/tty/serial/sh-sci.h #define SCSPTR_CTSIO BIT(5) /* Serial Port CTS# Pin Input/Output */ BIT 125 drivers/tty/serial/sh-sci.h #define SCSPTR_CTSDT BIT(4) /* Serial Port CTS# Pin Data */ BIT 126 drivers/tty/serial/sh-sci.h #define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */ BIT 127 drivers/tty/serial/sh-sci.h #define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */ BIT 128 drivers/tty/serial/sh-sci.h #define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */ BIT 129 drivers/tty/serial/sh-sci.h #define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */ BIT 132 drivers/tty/serial/sh-sci.h #define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */ BIT 133 drivers/tty/serial/sh-sci.h #define HSCIF_SRDE BIT(14) /* Sampling Point Register Enable */ BIT 139 drivers/tty/serial/sh-sci.h #define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */ BIT 140 drivers/tty/serial/sh-sci.h #define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */ BIT 141 drivers/tty/serial/sh-sci.h #define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */ BIT 142 drivers/tty/serial/sh-sci.h #define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */ BIT 143 drivers/tty/serial/sh-sci.h #define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */ BIT 146 drivers/tty/serial/sh-sci.h #define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */ BIT 147 drivers/tty/serial/sh-sci.h #define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */ BIT 148 drivers/tty/serial/sh-sci.h #define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */ BIT 149 drivers/tty/serial/sh-sci.h #define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */ BIT 150 drivers/tty/serial/sh-sci.h #define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */ BIT 158 drivers/tty/serial/sh-sci.h #define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */ BIT 159 drivers/tty/serial/sh-sci.h #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */ BIT 150 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_done_en = BIT(0), BIT 151 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_done_en = BIT(1), BIT 152 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_oflow_en = BIT(2), BIT 153 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_allout_en = BIT(3), BIT 154 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_io_dma_en = BIT(4), BIT 155 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_io_dma_en = BIT(5), BIT 156 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxfifo_full_en = BIT(6), BIT 157 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_txfifo_empty_en = BIT(7), BIT 158 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxfifo_thd_en = BIT(8), BIT 159 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_txfifo_thd_en = BIT(9), BIT 160 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_frm_err_en = BIT(10), BIT 161 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_timeout_en = BIT(11), BIT 162 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxd_brk_en = BIT(15), BIT 165 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_done = BIT(0), BIT 166 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_done = BIT(1), BIT 167 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_oflow = BIT(2), BIT 168 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_allout = BIT(3), BIT 169 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_io_dma = BIT(4), BIT 170 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_io_dma = BIT(5), BIT 171 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxfifo_full = BIT(6), BIT 172 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_txfifo_empty = BIT(7), BIT 173 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxfifo_thd = BIT(8), BIT 174 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_txfifo_thd = BIT(9), BIT 175 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_frm_err = BIT(10), BIT 176 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_timeout = BIT(11), BIT 177 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxd_brk = BIT(15), BIT 215 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_done_en = BIT(0), BIT 216 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_done_en = BIT(1), BIT 217 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_oflow_en = BIT(2), BIT 218 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_allout_en = BIT(3), BIT 219 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_io_dma_en = BIT(4), BIT 220 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_io_dma_en = BIT(5), BIT 221 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxfifo_full_en = BIT(6), BIT 222 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_txfifo_empty_en = BIT(7), BIT 223 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxfifo_thd_en = BIT(8), BIT 224 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_txfifo_thd_en = BIT(9), BIT 225 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_frm_err_en = BIT(10), BIT 226 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxd_brk_en = BIT(11), BIT 227 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_timeout_en = BIT(12), BIT 228 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_parity_err_en = BIT(13), BIT 229 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_cts_en = BIT(14), BIT 230 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rts_en = BIT(15), BIT 233 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_done = BIT(0), BIT 234 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_done = BIT(1), BIT 235 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_oflow = BIT(2), BIT 236 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_allout = BIT(3), BIT 237 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_io_dma = BIT(4), BIT 238 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_tx_io_dma = BIT(5), BIT 239 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxfifo_full = BIT(6), BIT 240 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_txfifo_empty = BIT(7), BIT 241 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxfifo_thd = BIT(8), BIT 242 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_txfifo_thd = BIT(9), BIT 243 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_frm_err = BIT(10), BIT 244 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rxd_brk = BIT(11), BIT 245 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rx_timeout = BIT(12), BIT 246 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_parity_err = BIT(13), BIT 247 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_cts = BIT(14), BIT 248 drivers/tty/serial/sirfsoc_uart.h .sirfsoc_rts = BIT(15), BIT 261 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_DATA_BIT_LEN_5 BIT(0) BIT 266 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_STOP_BIT_LEN_2 BIT(2) BIT 267 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_PARITY_EN BIT(3) BIT 268 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_EVEN_BIT BIT(4) BIT 271 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_STICK_BIT_EVEN BIT(3) BIT 275 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_SET_BREAK BIT(6) BIT 276 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_LOOP_BACK BIT(7) BIT 278 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_DUMMY_READ BIT(16) BIT 280 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_AFC_RX_EN BIT(8) BIT 281 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_AFC_TX_EN BIT(9) BIT 282 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_AFC_CTS_CTRL BIT(10) BIT 283 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_AFC_RTS_CTRL BIT(11) BIT 284 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_AFC_CTS_STATUS BIT(12) BIT 285 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_AFC_RTS_STATUS BIT(13) BIT 288 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_FIFO_RESET BIT(0) BIT 289 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_FIFO_START BIT(1) BIT 291 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_RX_EN BIT(0) BIT 292 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_TX_EN BIT(1) BIT 294 drivers/tty/serial/sirfsoc_uart.h #define SIRFUART_IO_MODE BIT(0) BIT 310 drivers/tty/serial/sirfsoc_uart.h #define SIRFSOC_USP_ENDIAN_CTRL_LSBF BIT(4) BIT 311 drivers/tty/serial/sirfsoc_uart.h #define SIRFSOC_USP_EN BIT(5) BIT 327 drivers/tty/serial/sirfsoc_uart.h #define SIRFSOC_USP_LOOP_BACK_CTRL BIT(2) BIT 328 drivers/tty/serial/sirfsoc_uart.h #define SIRFSOC_USP_FRADDR_CLR_EN BIT(1) BIT 43 drivers/tty/serial/sprd_serial.c #define SPRD_LSR_OE BIT(4) BIT 44 drivers/tty/serial/sprd_serial.c #define SPRD_LSR_FE BIT(3) BIT 45 drivers/tty/serial/sprd_serial.c #define SPRD_LSR_PE BIT(2) BIT 46 drivers/tty/serial/sprd_serial.c #define SPRD_LSR_BI BIT(7) BIT 47 drivers/tty/serial/sprd_serial.c #define SPRD_LSR_TX_OVER BIT(15) BIT 56 drivers/tty/serial/sprd_serial.c #define SPRD_IEN_RX_FULL BIT(0) BIT 57 drivers/tty/serial/sprd_serial.c #define SPRD_IEN_TX_EMPTY BIT(1) BIT 58 drivers/tty/serial/sprd_serial.c #define SPRD_IEN_BREAK_DETECT BIT(7) BIT 59 drivers/tty/serial/sprd_serial.c #define SPRD_IEN_TIMEOUT BIT(13) BIT 63 drivers/tty/serial/sprd_serial.c #define SPRD_ICLR_TIMEOUT BIT(13) BIT 69 drivers/tty/serial/sprd_serial.c #define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3)) BIT 74 drivers/tty/serial/sprd_serial.c #define SPRD_LCR_PARITY (BIT(0) | BIT(1)) BIT 81 drivers/tty/serial/sprd_serial.c #define SPRD_DMA_EN BIT(15) BIT 82 drivers/tty/serial/sprd_serial.c #define SPRD_LOOPBACK_EN BIT(14) BIT 83 drivers/tty/serial/sprd_serial.c #define RX_HW_FLOW_CTL_THLD BIT(6) BIT 84 drivers/tty/serial/sprd_serial.c #define RX_HW_FLOW_CTL_EN BIT(7) BIT 85 drivers/tty/serial/sprd_serial.c #define TX_HW_FLOW_CTL_EN BIT(8) BIT 105 drivers/tty/serial/sprd_serial.c #define SPRD_IMSR_RX_FIFO_FULL BIT(0) BIT 106 drivers/tty/serial/sprd_serial.c #define SPRD_IMSR_TX_FIFO_EMPTY BIT(1) BIT 107 drivers/tty/serial/sprd_serial.c #define SPRD_IMSR_BREAK_DETECT BIT(7) BIT 108 drivers/tty/serial/sprd_serial.c #define SPRD_IMSR_TIMEOUT BIT(13) BIT 110 drivers/tty/serial/stm32-usart.c stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); BIT 148 drivers/tty/serial/stm32-usart.c stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); BIT 635 drivers/tty/serial/stm32-usart.c val |= BIT(cfg->uart_enable_bit); BIT 721 drivers/tty/serial/stm32-usart.c stm32_port->rdr_mask = (BIT(bits) - 1); BIT 843 drivers/tty/serial/stm32-usart.c stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); BIT 889 drivers/tty/serial/stm32-usart.c stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); BIT 1279 drivers/tty/serial/stm32-usart.c new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); BIT 1357 drivers/tty/serial/stm32-usart.c stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); BIT 1364 drivers/tty/serial/stm32-usart.c stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); BIT 107 drivers/tty/serial/stm32-usart.h #define USART_SR_PE BIT(0) BIT 108 drivers/tty/serial/stm32-usart.h #define USART_SR_FE BIT(1) BIT 109 drivers/tty/serial/stm32-usart.h #define USART_SR_NF BIT(2) BIT 110 drivers/tty/serial/stm32-usart.h #define USART_SR_ORE BIT(3) BIT 111 drivers/tty/serial/stm32-usart.h #define USART_SR_IDLE BIT(4) BIT 112 drivers/tty/serial/stm32-usart.h #define USART_SR_RXNE BIT(5) BIT 113 drivers/tty/serial/stm32-usart.h #define USART_SR_TC BIT(6) BIT 114 drivers/tty/serial/stm32-usart.h #define USART_SR_TXE BIT(7) BIT 115 drivers/tty/serial/stm32-usart.h #define USART_SR_CTSIF BIT(9) BIT 116 drivers/tty/serial/stm32-usart.h #define USART_SR_CTS BIT(10) /* F7 */ BIT 117 drivers/tty/serial/stm32-usart.h #define USART_SR_RTOF BIT(11) /* F7 */ BIT 118 drivers/tty/serial/stm32-usart.h #define USART_SR_EOBF BIT(12) /* F7 */ BIT 119 drivers/tty/serial/stm32-usart.h #define USART_SR_ABRE BIT(14) /* F7 */ BIT 120 drivers/tty/serial/stm32-usart.h #define USART_SR_ABRF BIT(15) /* F7 */ BIT 121 drivers/tty/serial/stm32-usart.h #define USART_SR_BUSY BIT(16) /* F7 */ BIT 122 drivers/tty/serial/stm32-usart.h #define USART_SR_CMF BIT(17) /* F7 */ BIT 123 drivers/tty/serial/stm32-usart.h #define USART_SR_SBKF BIT(18) /* F7 */ BIT 124 drivers/tty/serial/stm32-usart.h #define USART_SR_WUF BIT(20) /* H7 */ BIT 125 drivers/tty/serial/stm32-usart.h #define USART_SR_TEACK BIT(21) /* F7 */ BIT 128 drivers/tty/serial/stm32-usart.h #define USART_SR_DUMMY_RX BIT(16) BIT 131 drivers/tty/serial/stm32-usart.h #define USART_CR_TC BIT(6) BIT 143 drivers/tty/serial/stm32-usart.h #define USART_CR1_SBK BIT(0) BIT 144 drivers/tty/serial/stm32-usart.h #define USART_CR1_RWU BIT(1) /* F4 */ BIT 145 drivers/tty/serial/stm32-usart.h #define USART_CR1_UESM BIT(1) /* H7 */ BIT 146 drivers/tty/serial/stm32-usart.h #define USART_CR1_RE BIT(2) BIT 147 drivers/tty/serial/stm32-usart.h #define USART_CR1_TE BIT(3) BIT 148 drivers/tty/serial/stm32-usart.h #define USART_CR1_IDLEIE BIT(4) BIT 149 drivers/tty/serial/stm32-usart.h #define USART_CR1_RXNEIE BIT(5) BIT 150 drivers/tty/serial/stm32-usart.h #define USART_CR1_TCIE BIT(6) BIT 151 drivers/tty/serial/stm32-usart.h #define USART_CR1_TXEIE BIT(7) BIT 152 drivers/tty/serial/stm32-usart.h #define USART_CR1_PEIE BIT(8) BIT 153 drivers/tty/serial/stm32-usart.h #define USART_CR1_PS BIT(9) BIT 154 drivers/tty/serial/stm32-usart.h #define USART_CR1_PCE BIT(10) BIT 155 drivers/tty/serial/stm32-usart.h #define USART_CR1_WAKE BIT(11) BIT 156 drivers/tty/serial/stm32-usart.h #define USART_CR1_M0 BIT(12) /* F7 (CR1_M for F4) */ BIT 157 drivers/tty/serial/stm32-usart.h #define USART_CR1_MME BIT(13) /* F7 */ BIT 158 drivers/tty/serial/stm32-usart.h #define USART_CR1_CMIE BIT(14) /* F7 */ BIT 159 drivers/tty/serial/stm32-usart.h #define USART_CR1_OVER8 BIT(15) BIT 162 drivers/tty/serial/stm32-usart.h #define USART_CR1_RTOIE BIT(26) /* F7 */ BIT 163 drivers/tty/serial/stm32-usart.h #define USART_CR1_EOBIE BIT(27) /* F7 */ BIT 164 drivers/tty/serial/stm32-usart.h #define USART_CR1_M1 BIT(28) /* F7 */ BIT 165 drivers/tty/serial/stm32-usart.h #define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27)) BIT 166 drivers/tty/serial/stm32-usart.h #define USART_CR1_FIFOEN BIT(29) /* H7 */ BIT 172 drivers/tty/serial/stm32-usart.h #define USART_CR2_ADDM7 BIT(4) /* F7 */ BIT 173 drivers/tty/serial/stm32-usart.h #define USART_CR2_LBCL BIT(8) BIT 174 drivers/tty/serial/stm32-usart.h #define USART_CR2_CPHA BIT(9) BIT 175 drivers/tty/serial/stm32-usart.h #define USART_CR2_CPOL BIT(10) BIT 176 drivers/tty/serial/stm32-usart.h #define USART_CR2_CLKEN BIT(11) BIT 177 drivers/tty/serial/stm32-usart.h #define USART_CR2_STOP_2B BIT(13) BIT 179 drivers/tty/serial/stm32-usart.h #define USART_CR2_LINEN BIT(14) BIT 180 drivers/tty/serial/stm32-usart.h #define USART_CR2_SWAP BIT(15) /* F7 */ BIT 181 drivers/tty/serial/stm32-usart.h #define USART_CR2_RXINV BIT(16) /* F7 */ BIT 182 drivers/tty/serial/stm32-usart.h #define USART_CR2_TXINV BIT(17) /* F7 */ BIT 183 drivers/tty/serial/stm32-usart.h #define USART_CR2_DATAINV BIT(18) /* F7 */ BIT 184 drivers/tty/serial/stm32-usart.h #define USART_CR2_MSBFIRST BIT(19) /* F7 */ BIT 185 drivers/tty/serial/stm32-usart.h #define USART_CR2_ABREN BIT(20) /* F7 */ BIT 187 drivers/tty/serial/stm32-usart.h #define USART_CR2_RTOEN BIT(23) /* F7 */ BIT 191 drivers/tty/serial/stm32-usart.h #define USART_CR3_EIE BIT(0) BIT 192 drivers/tty/serial/stm32-usart.h #define USART_CR3_IREN BIT(1) BIT 193 drivers/tty/serial/stm32-usart.h #define USART_CR3_IRLP BIT(2) BIT 194 drivers/tty/serial/stm32-usart.h #define USART_CR3_HDSEL BIT(3) BIT 195 drivers/tty/serial/stm32-usart.h #define USART_CR3_NACK BIT(4) BIT 196 drivers/tty/serial/stm32-usart.h #define USART_CR3_SCEN BIT(5) BIT 197 drivers/tty/serial/stm32-usart.h #define USART_CR3_DMAR BIT(6) BIT 198 drivers/tty/serial/stm32-usart.h #define USART_CR3_DMAT BIT(7) BIT 199 drivers/tty/serial/stm32-usart.h #define USART_CR3_RTSE BIT(8) BIT 200 drivers/tty/serial/stm32-usart.h #define USART_CR3_CTSE BIT(9) BIT 201 drivers/tty/serial/stm32-usart.h #define USART_CR3_CTSIE BIT(10) BIT 202 drivers/tty/serial/stm32-usart.h #define USART_CR3_ONEBIT BIT(11) BIT 203 drivers/tty/serial/stm32-usart.h #define USART_CR3_OVRDIS BIT(12) /* F7 */ BIT 204 drivers/tty/serial/stm32-usart.h #define USART_CR3_DDRE BIT(13) /* F7 */ BIT 205 drivers/tty/serial/stm32-usart.h #define USART_CR3_DEM BIT(14) /* F7 */ BIT 206 drivers/tty/serial/stm32-usart.h #define USART_CR3_DEP BIT(15) /* F7 */ BIT 209 drivers/tty/serial/stm32-usart.h #define USART_CR3_WUS_START_BIT BIT(21) /* H7 */ BIT 210 drivers/tty/serial/stm32-usart.h #define USART_CR3_WUFIE BIT(22) /* H7 */ BIT 211 drivers/tty/serial/stm32-usart.h #define USART_CR3_TXFTIE BIT(23) /* H7 */ BIT 212 drivers/tty/serial/stm32-usart.h #define USART_CR3_TCBGTIE BIT(24) /* H7 */ BIT 215 drivers/tty/serial/stm32-usart.h #define USART_CR3_RXFTIE BIT(28) /* H7 */ BIT 234 drivers/tty/serial/stm32-usart.h #define USART_RQR_ABRRQ BIT(0) /* F7 */ BIT 235 drivers/tty/serial/stm32-usart.h #define USART_RQR_SBKRQ BIT(1) /* F7 */ BIT 236 drivers/tty/serial/stm32-usart.h #define USART_RQR_MMRQ BIT(2) /* F7 */ BIT 237 drivers/tty/serial/stm32-usart.h #define USART_RQR_RXFRQ BIT(3) /* F7 */ BIT 238 drivers/tty/serial/stm32-usart.h #define USART_RQR_TXFRQ BIT(4) /* F7 */ BIT 241 drivers/tty/serial/stm32-usart.h #define USART_ICR_PECF BIT(0) /* F7 */ BIT 242 drivers/tty/serial/stm32-usart.h #define USART_ICR_FECF BIT(1) /* F7 */ BIT 243 drivers/tty/serial/stm32-usart.h #define USART_ICR_ORECF BIT(3) /* F7 */ BIT 244 drivers/tty/serial/stm32-usart.h #define USART_ICR_IDLECF BIT(4) /* F7 */ BIT 245 drivers/tty/serial/stm32-usart.h #define USART_ICR_TCCF BIT(6) /* F7 */ BIT 246 drivers/tty/serial/stm32-usart.h #define USART_ICR_CTSCF BIT(9) /* F7 */ BIT 247 drivers/tty/serial/stm32-usart.h #define USART_ICR_RTOCF BIT(11) /* F7 */ BIT 248 drivers/tty/serial/stm32-usart.h #define USART_ICR_EOBCF BIT(12) /* F7 */ BIT 249 drivers/tty/serial/stm32-usart.h #define USART_ICR_CMCF BIT(17) /* F7 */ BIT 250 drivers/tty/serial/stm32-usart.h #define USART_ICR_WUCF BIT(20) /* H7 */ BIT 152 drivers/tty/serial/xilinx_uartps.c #define CDNS_UART_RXBS_SUPPORT BIT(1) BIT 391 drivers/tty/vt/keyboard.c shift_state |= BIT(val); BIT 1017 drivers/tty/vt/keyboard.c .mask = BIT(_led_bit), \ BIT 80 drivers/usb/cdns3/drd.h #define OTGCMD_DEV_BUS_REQ BIT(0) BIT 82 drivers/usb/cdns3/drd.h #define OTGCMD_HOST_BUS_REQ BIT(1) BIT 84 drivers/usb/cdns3/drd.h #define OTGCMD_OTG_EN BIT(2) BIT 86 drivers/usb/cdns3/drd.h #define OTGCMD_OTG_DIS BIT(3) BIT 88 drivers/usb/cdns3/drd.h #define OTGCMD_A_DEV_EN BIT(4) BIT 90 drivers/usb/cdns3/drd.h #define OTGCMD_A_DEV_DIS BIT(5) BIT 92 drivers/usb/cdns3/drd.h #define OTGCMD_DEV_BUS_DROP BIT(8) BIT 94 drivers/usb/cdns3/drd.h #define OTGCMD_HOST_BUS_DROP BIT(9) BIT 96 drivers/usb/cdns3/drd.h #define OTGCMD_DEV_POWER_OFF BIT(11) BIT 98 drivers/usb/cdns3/drd.h #define OTGCMD_HOST_POWER_OFF BIT(12) BIT 102 drivers/usb/cdns3/drd.h #define OTGIEN_ID_CHANGE_INT BIT(0) BIT 104 drivers/usb/cdns3/drd.h #define OTGIEN_VBUSVALID_RISE_INT BIT(4) BIT 106 drivers/usb/cdns3/drd.h #define OTGIEN_VBUSVALID_FALL_INT BIT(5) BIT 113 drivers/usb/cdns3/drd.h #define OTGSTS_ID_VALUE BIT(0) BIT 115 drivers/usb/cdns3/drd.h #define OTGSTS_VBUS_VALID BIT(1) BIT 117 drivers/usb/cdns3/drd.h #define OTGSTS_SESSION_VALID BIT(2) BIT 119 drivers/usb/cdns3/drd.h #define OTGSTS_DEV_ACTIVE BIT(3) BIT 121 drivers/usb/cdns3/drd.h #define OTGSTS_HOST_ACTIVE BIT(4) BIT 123 drivers/usb/cdns3/drd.h #define OTGSTS_OTG_NRDY_MASK BIT(11) BIT 137 drivers/usb/cdns3/drd.h #define OTGSTS_XHCI_READY BIT(26) BIT 139 drivers/usb/cdns3/drd.h #define OTGSTS_DEV_READY BIT(27) BIT 149 drivers/usb/cdns3/drd.h #define OTGREFCLK_STB_CLK_SWITCH_EN BIT(31) BIT 152 drivers/usb/cdns3/drd.h #define OVERRIDE_IDPULLUP BIT(0) BIT 154 drivers/usb/cdns3/drd.h #define OVERRIDE_IDPULLUP_V0 BIT(24) BIT 249 drivers/usb/cdns3/ep0.c usb_status = BIT(USB_DEVICE_SELF_POWERED); BIT 252 drivers/usb/cdns3/ep0.c usb_status |= BIT(USB_DEVICE_REMOTE_WAKEUP); BIT 258 drivers/usb/cdns3/ep0.c usb_status |= BIT(USB_DEV_STAT_U1_ENABLED); BIT 261 drivers/usb/cdns3/ep0.c usb_status |= BIT(USB_DEV_STAT_U2_ENABLED); BIT 274 drivers/usb/cdns3/ep0.c usb_status = BIT(USB_ENDPOINT_HALT); BIT 843 drivers/usb/cdns3/ep0.c BIT(0) | BIT(16)); BIT 845 drivers/usb/cdns3/ep0.c BIT(0) | BIT(16)); BIT 1530 drivers/usb/cdns3/gadget.c mask = BIT(priv_ep->num + 16); BIT 1532 drivers/usb/cdns3/gadget.c mask = BIT(priv_ep->num); BIT 1717 drivers/usb/cdns3/gadget.c priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0; BIT 1803 drivers/usb/cdns3/gadget.c priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0; BIT 1838 drivers/usb/cdns3/gadget.c BIT(cdns3_ep_addr_to_index(bEndpointAddress))); BIT 2473 drivers/usb/cdns3/gadget.c ep_mask = BIT(i); BIT 124 drivers/usb/cdns3/gadget.h #define USB_CONF_CFGRST BIT(0) BIT 126 drivers/usb/cdns3/gadget.h #define USB_CONF_CFGSET BIT(1) BIT 128 drivers/usb/cdns3/gadget.h #define USB_CONF_USB3DIS BIT(3) BIT 130 drivers/usb/cdns3/gadget.h #define USB_CONF_USB2DIS BIT(4) BIT 132 drivers/usb/cdns3/gadget.h #define USB_CONF_LENDIAN BIT(5) BIT 138 drivers/usb/cdns3/gadget.h #define USB_CONF_BENDIAN BIT(6) BIT 140 drivers/usb/cdns3/gadget.h #define USB_CONF_SWRST BIT(7) BIT 142 drivers/usb/cdns3/gadget.h #define USB_CONF_DSING BIT(8) BIT 144 drivers/usb/cdns3/gadget.h #define USB_CONF_DMULT BIT(9) BIT 146 drivers/usb/cdns3/gadget.h #define USB_CONF_DMAOFFEN BIT(10) BIT 148 drivers/usb/cdns3/gadget.h #define USB_CONF_DMAOFFDS BIT(11) BIT 150 drivers/usb/cdns3/gadget.h #define USB_CONF_CFORCE_FS BIT(12) BIT 152 drivers/usb/cdns3/gadget.h #define USB_CONF_SFORCE_FS BIT(13) BIT 154 drivers/usb/cdns3/gadget.h #define USB_CONF_DEVEN BIT(14) BIT 156 drivers/usb/cdns3/gadget.h #define USB_CONF_DEVDS BIT(15) BIT 158 drivers/usb/cdns3/gadget.h #define USB_CONF_L1EN BIT(16) BIT 160 drivers/usb/cdns3/gadget.h #define USB_CONF_L1DS BIT(17) BIT 162 drivers/usb/cdns3/gadget.h #define USB_CONF_CLK2OFFEN BIT(18) BIT 164 drivers/usb/cdns3/gadget.h #define USB_CONF_CLK2OFFDS BIT(19) BIT 166 drivers/usb/cdns3/gadget.h #define USB_CONF_LGO_L0 BIT(20) BIT 168 drivers/usb/cdns3/gadget.h #define USB_CONF_CLK3OFFEN BIT(21) BIT 170 drivers/usb/cdns3/gadget.h #define USB_CONF_CLK3OFFDS BIT(22) BIT 173 drivers/usb/cdns3/gadget.h #define USB_CONF_U1EN BIT(24) BIT 175 drivers/usb/cdns3/gadget.h #define USB_CONF_U1DS BIT(25) BIT 177 drivers/usb/cdns3/gadget.h #define USB_CONF_U2EN BIT(26) BIT 179 drivers/usb/cdns3/gadget.h #define USB_CONF_U2DS BIT(27) BIT 181 drivers/usb/cdns3/gadget.h #define USB_CONF_LGO_U0 BIT(28) BIT 183 drivers/usb/cdns3/gadget.h #define USB_CONF_LGO_U1 BIT(29) BIT 185 drivers/usb/cdns3/gadget.h #define USB_CONF_LGO_U2 BIT(30) BIT 187 drivers/usb/cdns3/gadget.h #define USB_CONF_LGO_SSINACT BIT(31) BIT 195 drivers/usb/cdns3/gadget.h #define USB_STS_CFGSTS_MASK BIT(0) BIT 202 drivers/usb/cdns3/gadget.h #define USB_STS_OV_MASK BIT(1) BIT 209 drivers/usb/cdns3/gadget.h #define USB_STS_USB3CONS_MASK BIT(2) BIT 217 drivers/usb/cdns3/gadget.h #define USB_STS_DTRANS_MASK BIT(3) BIT 243 drivers/usb/cdns3/gadget.h #define USB_STS_ENDIAN_MASK BIT(7) BIT 251 drivers/usb/cdns3/gadget.h #define USB_STS_CLK2OFF_MASK BIT(8) BIT 259 drivers/usb/cdns3/gadget.h #define USB_STS_CLK3OFF_MASK BIT(9) BIT 266 drivers/usb/cdns3/gadget.h #define USB_STS_IN_RST_MASK BIT(10) BIT 274 drivers/usb/cdns3/gadget.h #define USB_STS_TDL_TRB_ENABLED BIT(11) BIT 280 drivers/usb/cdns3/gadget.h #define USB_STS_DEVS_MASK BIT(14) BIT 287 drivers/usb/cdns3/gadget.h #define USB_STS_ADDRESSED_MASK BIT(15) BIT 294 drivers/usb/cdns3/gadget.h #define USB_STS_L1ENS_MASK BIT(16) BIT 301 drivers/usb/cdns3/gadget.h #define USB_STS_VBUSS_MASK BIT(17) BIT 320 drivers/usb/cdns3/gadget.h #define USB_STS_USB2CONS_MASK BIT(20) BIT 327 drivers/usb/cdns3/gadget.h #define USB_STS_DISABLE_HS_MASK BIT(21) BIT 334 drivers/usb/cdns3/gadget.h #define USB_STS_U1ENS_MASK BIT(24) BIT 341 drivers/usb/cdns3/gadget.h #define USB_STS_U2ENS_MASK BIT(25) BIT 365 drivers/usb/cdns3/gadget.h #define USB_STS_DMAOFF_MASK BIT(30) BIT 372 drivers/usb/cdns3/gadget.h #define USB_STS_ENDIAN2_MASK BIT(31) BIT 377 drivers/usb/cdns3/gadget.h #define USB_CMD_SET_ADDR BIT(0) BIT 388 drivers/usb/cdns3/gadget.h #define USB_CMD_SDNFW BIT(8) BIT 390 drivers/usb/cdns3/gadget.h #define USB_CMD_STMODE BIT(9) BIT 398 drivers/usb/cdns3/gadget.h #define USB_CMD_SDNLTM BIT(12) BIT 400 drivers/usb/cdns3/gadget.h #define USB_CMD_SPKT BIT(13) BIT 425 drivers/usb/cdns3/gadget.h #define USB_LPM_BRW BIT(4) BIT 429 drivers/usb/cdns3/gadget.h #define USB_IEN_CONIEN BIT(0) BIT 431 drivers/usb/cdns3/gadget.h #define USB_IEN_DISIEN BIT(1) BIT 433 drivers/usb/cdns3/gadget.h #define USB_IEN_UWRESIEN BIT(2) BIT 435 drivers/usb/cdns3/gadget.h #define USB_IEN_UHRESIEN BIT(3) BIT 437 drivers/usb/cdns3/gadget.h #define USB_IEN_U3ENTIEN BIT(4) BIT 439 drivers/usb/cdns3/gadget.h #define USB_IEN_U3EXTIEN BIT(5) BIT 441 drivers/usb/cdns3/gadget.h #define USB_IEN_U2ENTIEN BIT(6) BIT 443 drivers/usb/cdns3/gadget.h #define USB_IEN_U2EXTIEN BIT(7) BIT 445 drivers/usb/cdns3/gadget.h #define USB_IEN_U1ENTIEN BIT(8) BIT 447 drivers/usb/cdns3/gadget.h #define USB_IEN_U1EXTIEN BIT(9) BIT 449 drivers/usb/cdns3/gadget.h #define USB_IEN_ITPIEN BIT(10) BIT 451 drivers/usb/cdns3/gadget.h #define USB_IEN_WAKEIEN BIT(11) BIT 453 drivers/usb/cdns3/gadget.h #define USB_IEN_SPKTIEN BIT(12) BIT 455 drivers/usb/cdns3/gadget.h #define USB_IEN_CON2IEN BIT(16) BIT 457 drivers/usb/cdns3/gadget.h #define USB_IEN_DIS2IEN BIT(17) BIT 459 drivers/usb/cdns3/gadget.h #define USB_IEN_U2RESIEN BIT(18) BIT 461 drivers/usb/cdns3/gadget.h #define USB_IEN_L2ENTIEN BIT(20) BIT 463 drivers/usb/cdns3/gadget.h #define USB_IEN_L2EXTIEN BIT(21) BIT 465 drivers/usb/cdns3/gadget.h #define USB_IEN_L1ENTIEN BIT(24) BIT 467 drivers/usb/cdns3/gadget.h #define USB_IEN_L1EXTIEN BIT(25) BIT 469 drivers/usb/cdns3/gadget.h #define USB_IEN_CFGRESIEN BIT(26) BIT 471 drivers/usb/cdns3/gadget.h #define USB_IEN_UWRESSIEN BIT(28) BIT 473 drivers/usb/cdns3/gadget.h #define USB_IEN_UWRESEIEN BIT(29) BIT 482 drivers/usb/cdns3/gadget.h #define USB_ISTS_CONI BIT(0) BIT 484 drivers/usb/cdns3/gadget.h #define USB_ISTS_DISI BIT(1) BIT 486 drivers/usb/cdns3/gadget.h #define USB_ISTS_UWRESI BIT(2) BIT 488 drivers/usb/cdns3/gadget.h #define USB_ISTS_UHRESI BIT(3) BIT 490 drivers/usb/cdns3/gadget.h #define USB_ISTS_U3ENTI BIT(4) BIT 492 drivers/usb/cdns3/gadget.h #define USB_ISTS_U3EXTI BIT(5) BIT 494 drivers/usb/cdns3/gadget.h #define USB_ISTS_U2ENTI BIT(6) BIT 496 drivers/usb/cdns3/gadget.h #define USB_ISTS_U2EXTI BIT(7) BIT 498 drivers/usb/cdns3/gadget.h #define USB_ISTS_U1ENTI BIT(8) BIT 500 drivers/usb/cdns3/gadget.h #define USB_ISTS_U1EXTI BIT(9) BIT 502 drivers/usb/cdns3/gadget.h #define USB_ISTS_ITPI BIT(10) BIT 504 drivers/usb/cdns3/gadget.h #define USB_ISTS_WAKEI BIT(11) BIT 506 drivers/usb/cdns3/gadget.h #define USB_ISTS_SPKTI BIT(12) BIT 508 drivers/usb/cdns3/gadget.h #define USB_ISTS_CON2I BIT(16) BIT 510 drivers/usb/cdns3/gadget.h #define USB_ISTS_DIS2I BIT(17) BIT 512 drivers/usb/cdns3/gadget.h #define USB_ISTS_U2RESI BIT(18) BIT 514 drivers/usb/cdns3/gadget.h #define USB_ISTS_L2ENTI BIT(20) BIT 516 drivers/usb/cdns3/gadget.h #define USB_ISTS_L2EXTI BIT(21) BIT 518 drivers/usb/cdns3/gadget.h #define USB_ISTS_L1ENTI BIT(24) BIT 520 drivers/usb/cdns3/gadget.h #define USB_ISTS_L1EXTI BIT(25) BIT 522 drivers/usb/cdns3/gadget.h #define USB_ISTS_CFGRESI BIT(26) BIT 524 drivers/usb/cdns3/gadget.h #define USB_ISTS_UWRESSI BIT(28) BIT 526 drivers/usb/cdns3/gadget.h #define USB_ISTS_UWRESEI BIT(29) BIT 533 drivers/usb/cdns3/gadget.h #define EP_SEL_DIR BIT(7) BIT 544 drivers/usb/cdns3/gadget.h #define EP_CFG_ENABLE BIT(0) BIT 554 drivers/usb/cdns3/gadget.h #define EP_CFG_STREAM_EN BIT(3) BIT 556 drivers/usb/cdns3/gadget.h #define EP_CFG_TDL_CHK BIT(4) BIT 558 drivers/usb/cdns3/gadget.h #define EP_CFG_SID_CHK BIT(5) BIT 560 drivers/usb/cdns3/gadget.h #define EP_CFG_EPENDIAN BIT(7) BIT 576 drivers/usb/cdns3/gadget.h #define EP_CMD_EPRST BIT(0) BIT 578 drivers/usb/cdns3/gadget.h #define EP_CMD_SSTALL BIT(1) BIT 580 drivers/usb/cdns3/gadget.h #define EP_CMD_CSTALL BIT(2) BIT 582 drivers/usb/cdns3/gadget.h #define EP_CMD_ERDY BIT(3) BIT 584 drivers/usb/cdns3/gadget.h #define EP_CMD_REQ_CMPL BIT(5) BIT 586 drivers/usb/cdns3/gadget.h #define EP_CMD_DRDY BIT(6) BIT 588 drivers/usb/cdns3/gadget.h #define EP_CMD_DFLUSH BIT(7) BIT 594 drivers/usb/cdns3/gadget.h #define EP_CMD_STDL BIT(8) BIT 609 drivers/usb/cdns3/gadget.h #define EP_STS_SETUP BIT(0) BIT 611 drivers/usb/cdns3/gadget.h #define EP_STS_STALL(p) ((p) & BIT(1)) BIT 613 drivers/usb/cdns3/gadget.h #define EP_STS_IOC BIT(2) BIT 615 drivers/usb/cdns3/gadget.h #define EP_STS_ISP BIT(3) BIT 617 drivers/usb/cdns3/gadget.h #define EP_STS_DESCMIS BIT(4) BIT 619 drivers/usb/cdns3/gadget.h #define EP_STS_STREAMR BIT(5) BIT 621 drivers/usb/cdns3/gadget.h #define EP_STS_MD_EXIT BIT(6) BIT 623 drivers/usb/cdns3/gadget.h #define EP_STS_TRBERR BIT(7) BIT 625 drivers/usb/cdns3/gadget.h #define EP_STS_NRDY BIT(8) BIT 627 drivers/usb/cdns3/gadget.h #define EP_STS_DBUSY BIT(9) BIT 629 drivers/usb/cdns3/gadget.h #define EP_STS_BUFFEMPTY(p) ((p) & BIT(10)) BIT 631 drivers/usb/cdns3/gadget.h #define EP_STS_CCS(p) ((p) & BIT(11)) BIT 633 drivers/usb/cdns3/gadget.h #define EP_STS_PRIME BIT(12) BIT 635 drivers/usb/cdns3/gadget.h #define EP_STS_SIDERR BIT(13) BIT 637 drivers/usb/cdns3/gadget.h #define EP_STS_OUTSMM BIT(14) BIT 639 drivers/usb/cdns3/gadget.h #define EP_STS_ISOERR BIT(15) BIT 641 drivers/usb/cdns3/gadget.h #define EP_STS_HOSTPP(p) ((p) & BIT(16)) BIT 649 drivers/usb/cdns3/gadget.h #define EP_STS_IOT BIT(19) BIT 654 drivers/usb/cdns3/gadget.h #define EP_STS_OUTQ_VAL_MASK BIT(28) BIT 657 drivers/usb/cdns3/gadget.h #define EP_STS_STPWAIT BIT(31) BIT 666 drivers/usb/cdns3/gadget.h #define EP_STS_EN_SETUPEN BIT(0) BIT 668 drivers/usb/cdns3/gadget.h #define EP_STS_EN_DESCMISEN BIT(4) BIT 670 drivers/usb/cdns3/gadget.h #define EP_STS_EN_STREAMREN BIT(5) BIT 672 drivers/usb/cdns3/gadget.h #define EP_STS_EN_MD_EXITEN BIT(6) BIT 674 drivers/usb/cdns3/gadget.h #define EP_STS_EN_TRBERREN BIT(7) BIT 676 drivers/usb/cdns3/gadget.h #define EP_STS_EN_NRDYEN BIT(8) BIT 678 drivers/usb/cdns3/gadget.h #define EP_STS_EN_PRIMEEEN BIT(12) BIT 680 drivers/usb/cdns3/gadget.h #define EP_STS_EN_SIDERREN BIT(13) BIT 682 drivers/usb/cdns3/gadget.h #define EP_STS_EN_OUTSMMEN BIT(14) BIT 684 drivers/usb/cdns3/gadget.h #define EP_STS_EN_ISOERREN BIT(15) BIT 686 drivers/usb/cdns3/gadget.h #define EP_STS_EN_IOTEN BIT(19) BIT 688 drivers/usb/cdns3/gadget.h #define EP_STS_EN_STPWAITEN BIT(31) BIT 692 drivers/usb/cdns3/gadget.h #define DB_VALUE_EP0_OUT BIT(0) BIT 693 drivers/usb/cdns3/gadget.h #define DB_VALUE_EP0_IN BIT(16) BIT 697 drivers/usb/cdns3/gadget.h #define EP_IEN_EP_OUT0 BIT(0) BIT 698 drivers/usb/cdns3/gadget.h #define EP_IEN_EP_IN0 BIT(16) BIT 702 drivers/usb/cdns3/gadget.h #define EP_ISTS_EP_OUT0 BIT(0) BIT 703 drivers/usb/cdns3/gadget.h #define EP_ISTS_EP_IN0 BIT(16) BIT 707 drivers/usb/cdns3/gadget.h #define PUSB_PWR_PSO_EN BIT(0) BIT 709 drivers/usb/cdns3/gadget.h #define PUSB_PWR_PSO_DS BIT(1) BIT 715 drivers/usb/cdns3/gadget.h #define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8) BIT 720 drivers/usb/cdns3/gadget.h #define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9) BIT 722 drivers/usb/cdns3/gadget.h #define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30) BIT 724 drivers/usb/cdns3/gadget.h #define PUSB_PWR_FST_REG_ACCESS BIT(31) BIT 732 drivers/usb/cdns3/gadget.h #define USB_CONF2_DIS_TDL_TRB BIT(1) BIT 738 drivers/usb/cdns3/gadget.h #define USB_CONF2_EN_TDL_TRB BIT(2) BIT 832 drivers/usb/cdns3/gadget.h #define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24)) BIT 839 drivers/usb/cdns3/gadget.h #define DEV_U2PHY_ULPI(p) ((p) & BIT(25)) BIT 847 drivers/usb/cdns3/gadget.h #define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26)) BIT 853 drivers/usb/cdns3/gadget.h #define USB_CAP1_OTG_READY(p) ((p) & BIT(27)) BIT 860 drivers/usb/cdns3/gadget.h #define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28)) BIT 925 drivers/usb/cdns3/gadget.h #define DBG_LINK1_RXDET_BREAK_DIS BIT(16) BIT 933 drivers/usb/cdns3/gadget.h #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24) BIT 939 drivers/usb/cdns3/gadget.h #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25) BIT 945 drivers/usb/cdns3/gadget.h #define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26) BIT 951 drivers/usb/cdns3/gadget.h #define DBG_LINK1_LFPS_GEN_PING_SET BIT(27) BIT 1018 drivers/usb/cdns3/gadget.h #define TRB_CYCLE BIT(0) BIT 1022 drivers/usb/cdns3/gadget.h #define TRB_TOGGLE BIT(1) BIT 1032 drivers/usb/cdns3/gadget.h #define TRB_SP BIT(1) BIT 1035 drivers/usb/cdns3/gadget.h #define TRB_ISP BIT(2) BIT 1037 drivers/usb/cdns3/gadget.h #define TRB_FIFO_MODE BIT(3) BIT 1039 drivers/usb/cdns3/gadget.h #define TRB_CHAIN BIT(4) BIT 1041 drivers/usb/cdns3/gadget.h #define TRB_IOC BIT(5) BIT 1131 drivers/usb/cdns3/gadget.h #define EP_ENABLED BIT(0) BIT 1132 drivers/usb/cdns3/gadget.h #define EP_STALLED BIT(1) BIT 1133 drivers/usb/cdns3/gadget.h #define EP_STALL_PENDING BIT(2) BIT 1134 drivers/usb/cdns3/gadget.h #define EP_WEDGE BIT(3) BIT 1135 drivers/usb/cdns3/gadget.h #define EP_TRANSFER_STARTED BIT(4) BIT 1136 drivers/usb/cdns3/gadget.h #define EP_UPDATE_EP_TRBADDR BIT(5) BIT 1137 drivers/usb/cdns3/gadget.h #define EP_PENDING_REQUEST BIT(6) BIT 1138 drivers/usb/cdns3/gadget.h #define EP_RING_FULL BIT(7) BIT 1139 drivers/usb/cdns3/gadget.h #define EP_CLAIMED BIT(8) BIT 1140 drivers/usb/cdns3/gadget.h #define EP_DEFERRED_DRDY BIT(9) BIT 1141 drivers/usb/cdns3/gadget.h #define EP_QUIRK_ISO_OUT_EN BIT(10) BIT 1142 drivers/usb/cdns3/gadget.h #define EP_QUIRK_END_TRANSFER BIT(11) BIT 1143 drivers/usb/cdns3/gadget.h #define EP_QUIRK_EXTRA_BUF_DET BIT(12) BIT 1144 drivers/usb/cdns3/gadget.h #define EP_QUIRK_EXTRA_BUF_EN BIT(13) BIT 1205 drivers/usb/cdns3/gadget.h #define REQUEST_PENDING BIT(0) BIT 1206 drivers/usb/cdns3/gadget.h #define REQUEST_INTERNAL BIT(1) BIT 1207 drivers/usb/cdns3/gadget.h #define REQUEST_INTERNAL_CH BIT(2) BIT 1208 drivers/usb/cdns3/gadget.h #define REQUEST_ZLP BIT(3) BIT 1209 drivers/usb/cdns3/gadget.h #define REQUEST_UNALIGNED BIT(4) BIT 29 drivers/usb/chipidea/bits.h #define HCCPARAMS_LEN BIT(17) BIT 33 drivers/usb/chipidea/bits.h #define DCCPARAMS_DC BIT(7) BIT 34 drivers/usb/chipidea/bits.h #define DCCPARAMS_HC BIT(8) BIT 37 drivers/usb/chipidea/bits.h #define TESTMODE_FORCE BIT(0) BIT 40 drivers/usb/chipidea/bits.h #define USBCMD_RS BIT(0) BIT 41 drivers/usb/chipidea/bits.h #define USBCMD_RST BIT(1) BIT 42 drivers/usb/chipidea/bits.h #define USBCMD_SUTW BIT(13) BIT 43 drivers/usb/chipidea/bits.h #define USBCMD_ATDTW BIT(14) BIT 46 drivers/usb/chipidea/bits.h #define USBi_UI BIT(0) BIT 47 drivers/usb/chipidea/bits.h #define USBi_UEI BIT(1) BIT 48 drivers/usb/chipidea/bits.h #define USBi_PCI BIT(2) BIT 49 drivers/usb/chipidea/bits.h #define USBi_URI BIT(6) BIT 50 drivers/usb/chipidea/bits.h #define USBi_SLI BIT(8) BIT 53 drivers/usb/chipidea/bits.h #define DEVICEADDR_USBADRA BIT(24) BIT 66 drivers/usb/chipidea/bits.h #define PORTSC_CCS BIT(0) BIT 67 drivers/usb/chipidea/bits.h #define PORTSC_CSC BIT(1) BIT 68 drivers/usb/chipidea/bits.h #define PORTSC_PEC BIT(3) BIT 69 drivers/usb/chipidea/bits.h #define PORTSC_OCC BIT(5) BIT 70 drivers/usb/chipidea/bits.h #define PORTSC_FPR BIT(6) BIT 71 drivers/usb/chipidea/bits.h #define PORTSC_SUSP BIT(7) BIT 72 drivers/usb/chipidea/bits.h #define PORTSC_HSP BIT(9) BIT 73 drivers/usb/chipidea/bits.h #define PORTSC_PP BIT(12) BIT 75 drivers/usb/chipidea/bits.h #define PORTSC_WKCN BIT(20) BIT 76 drivers/usb/chipidea/bits.h #define PORTSC_PHCD(d) ((d) ? BIT(22) : BIT(23)) BIT 78 drivers/usb/chipidea/bits.h #define PORTSC_PFSC BIT(24) BIT 80 drivers/usb/chipidea/bits.h (u32)((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0)) BIT 81 drivers/usb/chipidea/bits.h #define PORTSC_PTW BIT(28) BIT 82 drivers/usb/chipidea/bits.h #define PORTSC_STS BIT(29) BIT 88 drivers/usb/chipidea/bits.h #define DEVLC_PFSC BIT(23) BIT 91 drivers/usb/chipidea/bits.h #define DEVLC_PTW BIT(27) BIT 92 drivers/usb/chipidea/bits.h #define DEVLC_STS BIT(28) BIT 102 drivers/usb/chipidea/bits.h #define OTGSC_IDPU BIT(5) BIT 103 drivers/usb/chipidea/bits.h #define OTGSC_HADP BIT(6) BIT 104 drivers/usb/chipidea/bits.h #define OTGSC_HABA BIT(7) BIT 105 drivers/usb/chipidea/bits.h #define OTGSC_ID BIT(8) BIT 106 drivers/usb/chipidea/bits.h #define OTGSC_AVV BIT(9) BIT 107 drivers/usb/chipidea/bits.h #define OTGSC_ASV BIT(10) BIT 108 drivers/usb/chipidea/bits.h #define OTGSC_BSV BIT(11) BIT 109 drivers/usb/chipidea/bits.h #define OTGSC_BSE BIT(12) BIT 110 drivers/usb/chipidea/bits.h #define OTGSC_IDIS BIT(16) BIT 111 drivers/usb/chipidea/bits.h #define OTGSC_AVVIS BIT(17) BIT 112 drivers/usb/chipidea/bits.h #define OTGSC_ASVIS BIT(18) BIT 113 drivers/usb/chipidea/bits.h #define OTGSC_BSVIS BIT(19) BIT 114 drivers/usb/chipidea/bits.h #define OTGSC_BSEIS BIT(20) BIT 115 drivers/usb/chipidea/bits.h #define OTGSC_1MSIS BIT(21) BIT 116 drivers/usb/chipidea/bits.h #define OTGSC_DPIS BIT(22) BIT 117 drivers/usb/chipidea/bits.h #define OTGSC_IDIE BIT(24) BIT 118 drivers/usb/chipidea/bits.h #define OTGSC_AVVIE BIT(25) BIT 119 drivers/usb/chipidea/bits.h #define OTGSC_ASVIE BIT(26) BIT 120 drivers/usb/chipidea/bits.h #define OTGSC_BSVIE BIT(27) BIT 121 drivers/usb/chipidea/bits.h #define OTGSC_BSEIE BIT(28) BIT 122 drivers/usb/chipidea/bits.h #define OTGSC_1MSIE BIT(29) BIT 123 drivers/usb/chipidea/bits.h #define OTGSC_DPIE BIT(30) BIT 134 drivers/usb/chipidea/bits.h #define USBMODE_SLOM BIT(3) BIT 135 drivers/usb/chipidea/bits.h #define USBMODE_CI_SDIS BIT(4) BIT 138 drivers/usb/chipidea/bits.h #define ENDPTCTRL_RXS BIT(0) BIT 140 drivers/usb/chipidea/bits.h #define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */ BIT 141 drivers/usb/chipidea/bits.h #define ENDPTCTRL_RXE BIT(7) BIT 142 drivers/usb/chipidea/bits.h #define ENDPTCTRL_TXS BIT(16) BIT 144 drivers/usb/chipidea/bits.h #define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */ BIT 145 drivers/usb/chipidea/bits.h #define ENDPTCTRL_TXE BIT(23) BIT 22 drivers/usb/chipidea/ci_hdrc_msm.c #define HS_PHY_TXFIFO_IDLE_FORCE_DIS BIT(4) BIT 25 drivers/usb/chipidea/ci_hdrc_msm.c #define HS_PHY_SESS_VLD_CTRL_EN BIT(7) BIT 26 drivers/usb/chipidea/ci_hdrc_msm.c #define HS_PHY_ULPI_TX_PKT_EN_CLR_FIX BIT(19) BIT 28 drivers/usb/chipidea/ci_hdrc_msm.c #define HSPHY_SESS_VLD_CTRL BIT(25) BIT 33 drivers/usb/chipidea/ci_hdrc_msm.c #define HS_PHY_DIG_CLAMP_N BIT(16) BIT 34 drivers/usb/chipidea/ci_hdrc_msm.c #define HS_PHY_POR_ASSERT BIT(0) BIT 105 drivers/usb/chipidea/udc.c hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n)); BIT 106 drivers/usb/chipidea/udc.c while (hw_read(ci, OP_ENDPTFLUSH, BIT(n))) BIT 108 drivers/usb/chipidea/udc.c } while (hw_read(ci, OP_ENDPTSTAT, BIT(n))); BIT 191 drivers/usb/chipidea/udc.c if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num))) BIT 194 drivers/usb/chipidea/udc.c hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n)); BIT 196 drivers/usb/chipidea/udc.c while (hw_read(ci, OP_ENDPTPRIME, BIT(n))) BIT 198 drivers/usb/chipidea/udc.c if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num))) BIT 253 drivers/usb/chipidea/udc.c return hw_test_and_clear(ci, OP_ENDPTCOMPLETE, BIT(n)); BIT 484 drivers/usb/chipidea/udc.c if (hw_read(ci, OP_ENDPTPRIME, BIT(n))) BIT 488 drivers/usb/chipidea/udc.c tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n)); BIT 565 drivers/usb/chipidea/udc.c if (!hw_read(ci, OP_ENDPTSTAT, BIT(n))) BIT 1213 drivers/usb/chipidea/udc.c hw_test_and_clear(ci, OP_ENDPTSETUPSTAT, BIT(0))) BIT 23 drivers/usb/chipidea/udc.h #define TD_TERMINATE BIT(0) BIT 28 drivers/usb/chipidea/udc.h #define TD_STATUS_TR_ERR BIT(3) BIT 29 drivers/usb/chipidea/udc.h #define TD_STATUS_DT_ERR BIT(5) BIT 30 drivers/usb/chipidea/udc.h #define TD_STATUS_HALTED BIT(6) BIT 31 drivers/usb/chipidea/udc.h #define TD_STATUS_ACTIVE BIT(7) BIT 33 drivers/usb/chipidea/udc.h #define TD_IOC BIT(15) BIT 46 drivers/usb/chipidea/udc.h #define QH_IOS BIT(15) BIT 48 drivers/usb/chipidea/udc.h #define QH_ZLT BIT(29) BIT 12 drivers/usb/chipidea/ulpi.c #define ULPI_WAKEUP BIT(31) BIT 13 drivers/usb/chipidea/ulpi.c #define ULPI_RUN BIT(30) BIT 14 drivers/usb/chipidea/ulpi.c #define ULPI_WRITE BIT(29) BIT 15 drivers/usb/chipidea/ulpi.c #define ULPI_SYNC_STATE BIT(27) BIT 15 drivers/usb/chipidea/usbmisc_imx.c #define MX25_BM_EXTERNAL_VBUS_DIVIDER BIT(23) BIT 23 drivers/usb/chipidea/usbmisc_imx.c #define MX25_OTG_PM_BIT BIT(24) BIT 24 drivers/usb/chipidea/usbmisc_imx.c #define MX25_OTG_PP_BIT BIT(11) BIT 25 drivers/usb/chipidea/usbmisc_imx.c #define MX25_OTG_OCPOL_BIT BIT(3) BIT 29 drivers/usb/chipidea/usbmisc_imx.c #define MX25_H1_PP_BIT BIT(18) BIT 30 drivers/usb/chipidea/usbmisc_imx.c #define MX25_H1_PM_BIT BIT(16) BIT 31 drivers/usb/chipidea/usbmisc_imx.c #define MX25_H1_IPPUE_UP_BIT BIT(7) BIT 32 drivers/usb/chipidea/usbmisc_imx.c #define MX25_H1_IPPUE_DOWN_BIT BIT(6) BIT 33 drivers/usb/chipidea/usbmisc_imx.c #define MX25_H1_TLL_BIT BIT(5) BIT 34 drivers/usb/chipidea/usbmisc_imx.c #define MX25_H1_USBTE_BIT BIT(4) BIT 35 drivers/usb/chipidea/usbmisc_imx.c #define MX25_H1_OCPOL_BIT BIT(2) BIT 37 drivers/usb/chipidea/usbmisc_imx.c #define MX27_H1_PM_BIT BIT(8) BIT 38 drivers/usb/chipidea/usbmisc_imx.c #define MX27_H2_PM_BIT BIT(16) BIT 39 drivers/usb/chipidea/usbmisc_imx.c #define MX27_OTG_PM_BIT BIT(24) BIT 45 drivers/usb/chipidea/usbmisc_imx.c #define MX53_USB_CTRL_1_H2_XCVR_CLK_SEL_ULPI BIT(2) BIT 47 drivers/usb/chipidea/usbmisc_imx.c #define MX53_USB_CTRL_1_H3_XCVR_CLK_SEL_ULPI BIT(6) BIT 51 drivers/usb/chipidea/usbmisc_imx.c #define MX53_USB_CLKONOFF_CTRL_H2_INT60CKOFF BIT(21) BIT 52 drivers/usb/chipidea/usbmisc_imx.c #define MX53_USB_CLKONOFF_CTRL_H3_INT60CKOFF BIT(22) BIT 53 drivers/usb/chipidea/usbmisc_imx.c #define MX53_BM_OVER_CUR_DIS_H1 BIT(5) BIT 54 drivers/usb/chipidea/usbmisc_imx.c #define MX53_BM_OVER_CUR_DIS_OTG BIT(8) BIT 55 drivers/usb/chipidea/usbmisc_imx.c #define MX53_BM_OVER_CUR_DIS_UHx BIT(30) BIT 56 drivers/usb/chipidea/usbmisc_imx.c #define MX53_USB_CTRL_1_UH2_ULPI_EN BIT(26) BIT 57 drivers/usb/chipidea/usbmisc_imx.c #define MX53_USB_CTRL_1_UH3_ULPI_EN BIT(27) BIT 58 drivers/usb/chipidea/usbmisc_imx.c #define MX53_USB_UHx_CTRL_WAKE_UP_EN BIT(7) BIT 59 drivers/usb/chipidea/usbmisc_imx.c #define MX53_USB_UHx_CTRL_ULPI_INT_EN BIT(8) BIT 63 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_NON_BURST_SETTING BIT(1) BIT 64 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_OVER_CUR_DIS BIT(7) BIT 65 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_OVER_CUR_POLARITY BIT(8) BIT 66 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_PWR_POLARITY BIT(9) BIT 67 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_WAKEUP_ENABLE BIT(10) BIT 68 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_UTMI_ON_CLOCK BIT(13) BIT 69 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_ID_WAKEUP BIT(16) BIT 70 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_VBUS_WAKEUP BIT(17) BIT 71 drivers/usb/chipidea/usbmisc_imx.c #define MX6SX_BM_DPDM_WAKEUP_EN BIT(29) BIT 72 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_WAKEUP_INTR BIT(31) BIT 76 drivers/usb/chipidea/usbmisc_imx.c #define MX6SX_BM_HSIC_AUTO_RESUME BIT(23) BIT 78 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_HSIC_DEV_CONN BIT(21) BIT 80 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_HSIC_EN BIT(12) BIT 82 drivers/usb/chipidea/usbmisc_imx.c #define MX6_BM_HSIC_CLK_ON BIT(11) BIT 93 drivers/usb/chipidea/usbmisc_imx.c #define VF610_OVER_CUR_DIS BIT(7) BIT 137 drivers/usb/class/cdc-acm.h #define NO_UNION_NORMAL BIT(0) BIT 138 drivers/usb/class/cdc-acm.h #define SINGLE_RX_URB BIT(1) BIT 139 drivers/usb/class/cdc-acm.h #define NO_CAP_LINE BIT(2) BIT 140 drivers/usb/class/cdc-acm.h #define NO_DATA_INTERFACE BIT(4) BIT 141 drivers/usb/class/cdc-acm.h #define IGNORE_DEVICE BIT(5) BIT 142 drivers/usb/class/cdc-acm.h #define QUIRK_CONTROL_LINE_STATE BIT(6) BIT 143 drivers/usb/class/cdc-acm.h #define CLEAR_HALT_CONDITIONS BIT(7) BIT 144 drivers/usb/class/cdc-acm.h #define SEND_ZERO_PACKET BIT(8) BIT 145 drivers/usb/class/cdc-acm.h #define DISABLE_ECHO BIT(9) BIT 430 drivers/usb/core/config.c i = maxp & (BIT(12) | BIT(11)); BIT 270 drivers/usb/dwc2/core.c pcgcctl |= BIT(17); BIT 273 drivers/usb/dwc2/core.c pcgcctl |= BIT(17); BIT 3573 drivers/usb/dwc2/gadget.c if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) BIT 3619 drivers/usb/dwc2/gadget.c if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) BIT 3793 drivers/usb/dwc2/gadget.c if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) BIT 44 drivers/usb/dwc2/hw.h #define GOTGCTL_CHIRPEN BIT(27) BIT 47 drivers/usb/dwc2/hw.h #define GOTGCTL_OTGVER BIT(20) BIT 48 drivers/usb/dwc2/hw.h #define GOTGCTL_BSESVLD BIT(19) BIT 49 drivers/usb/dwc2/hw.h #define GOTGCTL_ASESVLD BIT(18) BIT 50 drivers/usb/dwc2/hw.h #define GOTGCTL_DBNC_SHORT BIT(17) BIT 51 drivers/usb/dwc2/hw.h #define GOTGCTL_CONID_B BIT(16) BIT 52 drivers/usb/dwc2/hw.h #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15) BIT 53 drivers/usb/dwc2/hw.h #define GOTGCTL_DEVHNPEN BIT(11) BIT 54 drivers/usb/dwc2/hw.h #define GOTGCTL_HSTSETHNPEN BIT(10) BIT 55 drivers/usb/dwc2/hw.h #define GOTGCTL_HNPREQ BIT(9) BIT 56 drivers/usb/dwc2/hw.h #define GOTGCTL_HSTNEGSCS BIT(8) BIT 57 drivers/usb/dwc2/hw.h #define GOTGCTL_SESREQ BIT(1) BIT 58 drivers/usb/dwc2/hw.h #define GOTGCTL_SESREQSCS BIT(0) BIT 61 drivers/usb/dwc2/hw.h #define GOTGINT_DBNCE_DONE BIT(19) BIT 62 drivers/usb/dwc2/hw.h #define GOTGINT_A_DEV_TOUT_CHG BIT(18) BIT 63 drivers/usb/dwc2/hw.h #define GOTGINT_HST_NEG_DET BIT(17) BIT 64 drivers/usb/dwc2/hw.h #define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9) BIT 65 drivers/usb/dwc2/hw.h #define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8) BIT 66 drivers/usb/dwc2/hw.h #define GOTGINT_SES_END_DET BIT(2) BIT 69 drivers/usb/dwc2/hw.h #define GAHBCFG_AHB_SINGLE BIT(23) BIT 70 drivers/usb/dwc2/hw.h #define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22) BIT 71 drivers/usb/dwc2/hw.h #define GAHBCFG_REM_MEM_SUPP BIT(21) BIT 72 drivers/usb/dwc2/hw.h #define GAHBCFG_P_TXF_EMP_LVL BIT(8) BIT 73 drivers/usb/dwc2/hw.h #define GAHBCFG_NP_TXF_EMP_LVL BIT(7) BIT 74 drivers/usb/dwc2/hw.h #define GAHBCFG_DMA_EN BIT(5) BIT 82 drivers/usb/dwc2/hw.h #define GAHBCFG_GLBL_INTR_EN BIT(0) BIT 89 drivers/usb/dwc2/hw.h #define GUSBCFG_FORCEDEVMODE BIT(30) BIT 90 drivers/usb/dwc2/hw.h #define GUSBCFG_FORCEHOSTMODE BIT(29) BIT 91 drivers/usb/dwc2/hw.h #define GUSBCFG_TXENDDELAY BIT(28) BIT 92 drivers/usb/dwc2/hw.h #define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27) BIT 93 drivers/usb/dwc2/hw.h #define GUSBCFG_ICUSBCAP BIT(26) BIT 94 drivers/usb/dwc2/hw.h #define GUSBCFG_ULPI_INT_PROT_DIS BIT(25) BIT 95 drivers/usb/dwc2/hw.h #define GUSBCFG_INDICATORPASSTHROUGH BIT(24) BIT 96 drivers/usb/dwc2/hw.h #define GUSBCFG_INDICATORCOMPLEMENT BIT(23) BIT 97 drivers/usb/dwc2/hw.h #define GUSBCFG_TERMSELDLPULSE BIT(22) BIT 98 drivers/usb/dwc2/hw.h #define GUSBCFG_ULPI_INT_VBUS_IND BIT(21) BIT 99 drivers/usb/dwc2/hw.h #define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20) BIT 100 drivers/usb/dwc2/hw.h #define GUSBCFG_ULPI_CLK_SUSP_M BIT(19) BIT 101 drivers/usb/dwc2/hw.h #define GUSBCFG_ULPI_AUTO_RES BIT(18) BIT 102 drivers/usb/dwc2/hw.h #define GUSBCFG_ULPI_FS_LS BIT(17) BIT 103 drivers/usb/dwc2/hw.h #define GUSBCFG_OTG_UTMI_FS_SEL BIT(16) BIT 104 drivers/usb/dwc2/hw.h #define GUSBCFG_PHY_LP_CLK_SEL BIT(15) BIT 107 drivers/usb/dwc2/hw.h #define GUSBCFG_HNPCAP BIT(9) BIT 108 drivers/usb/dwc2/hw.h #define GUSBCFG_SRPCAP BIT(8) BIT 109 drivers/usb/dwc2/hw.h #define GUSBCFG_DDRSEL BIT(7) BIT 110 drivers/usb/dwc2/hw.h #define GUSBCFG_PHYSEL BIT(6) BIT 111 drivers/usb/dwc2/hw.h #define GUSBCFG_FSINTF BIT(5) BIT 112 drivers/usb/dwc2/hw.h #define GUSBCFG_ULPI_UTMI_SEL BIT(4) BIT 113 drivers/usb/dwc2/hw.h #define GUSBCFG_PHYIF16 BIT(3) BIT 121 drivers/usb/dwc2/hw.h #define GRSTCTL_AHBIDLE BIT(31) BIT 122 drivers/usb/dwc2/hw.h #define GRSTCTL_DMAREQ BIT(30) BIT 127 drivers/usb/dwc2/hw.h #define GRSTCTL_TXFFLSH BIT(5) BIT 128 drivers/usb/dwc2/hw.h #define GRSTCTL_RXFFLSH BIT(4) BIT 129 drivers/usb/dwc2/hw.h #define GRSTCTL_IN_TKNQ_FLSH BIT(3) BIT 130 drivers/usb/dwc2/hw.h #define GRSTCTL_FRMCNTRRST BIT(2) BIT 131 drivers/usb/dwc2/hw.h #define GRSTCTL_HSFTRST BIT(1) BIT 132 drivers/usb/dwc2/hw.h #define GRSTCTL_CSFTRST BIT(0) BIT 136 drivers/usb/dwc2/hw.h #define GINTSTS_WKUPINT BIT(31) BIT 137 drivers/usb/dwc2/hw.h #define GINTSTS_SESSREQINT BIT(30) BIT 138 drivers/usb/dwc2/hw.h #define GINTSTS_DISCONNINT BIT(29) BIT 139 drivers/usb/dwc2/hw.h #define GINTSTS_CONIDSTSCHNG BIT(28) BIT 140 drivers/usb/dwc2/hw.h #define GINTSTS_LPMTRANRCVD BIT(27) BIT 141 drivers/usb/dwc2/hw.h #define GINTSTS_PTXFEMP BIT(26) BIT 142 drivers/usb/dwc2/hw.h #define GINTSTS_HCHINT BIT(25) BIT 143 drivers/usb/dwc2/hw.h #define GINTSTS_PRTINT BIT(24) BIT 144 drivers/usb/dwc2/hw.h #define GINTSTS_RESETDET BIT(23) BIT 145 drivers/usb/dwc2/hw.h #define GINTSTS_FET_SUSP BIT(22) BIT 146 drivers/usb/dwc2/hw.h #define GINTSTS_INCOMPL_IP BIT(21) BIT 147 drivers/usb/dwc2/hw.h #define GINTSTS_INCOMPL_SOOUT BIT(21) BIT 148 drivers/usb/dwc2/hw.h #define GINTSTS_INCOMPL_SOIN BIT(20) BIT 149 drivers/usb/dwc2/hw.h #define GINTSTS_OEPINT BIT(19) BIT 150 drivers/usb/dwc2/hw.h #define GINTSTS_IEPINT BIT(18) BIT 151 drivers/usb/dwc2/hw.h #define GINTSTS_EPMIS BIT(17) BIT 152 drivers/usb/dwc2/hw.h #define GINTSTS_RESTOREDONE BIT(16) BIT 153 drivers/usb/dwc2/hw.h #define GINTSTS_EOPF BIT(15) BIT 154 drivers/usb/dwc2/hw.h #define GINTSTS_ISOUTDROP BIT(14) BIT 155 drivers/usb/dwc2/hw.h #define GINTSTS_ENUMDONE BIT(13) BIT 156 drivers/usb/dwc2/hw.h #define GINTSTS_USBRST BIT(12) BIT 157 drivers/usb/dwc2/hw.h #define GINTSTS_USBSUSP BIT(11) BIT 158 drivers/usb/dwc2/hw.h #define GINTSTS_ERLYSUSP BIT(10) BIT 159 drivers/usb/dwc2/hw.h #define GINTSTS_I2CINT BIT(9) BIT 160 drivers/usb/dwc2/hw.h #define GINTSTS_ULPI_CK_INT BIT(8) BIT 161 drivers/usb/dwc2/hw.h #define GINTSTS_GOUTNAKEFF BIT(7) BIT 162 drivers/usb/dwc2/hw.h #define GINTSTS_GINNAKEFF BIT(6) BIT 163 drivers/usb/dwc2/hw.h #define GINTSTS_NPTXFEMP BIT(5) BIT 164 drivers/usb/dwc2/hw.h #define GINTSTS_RXFLVL BIT(4) BIT 165 drivers/usb/dwc2/hw.h #define GINTSTS_SOF BIT(3) BIT 166 drivers/usb/dwc2/hw.h #define GINTSTS_OTGINT BIT(2) BIT 167 drivers/usb/dwc2/hw.h #define GINTSTS_MODEMIS BIT(1) BIT 168 drivers/usb/dwc2/hw.h #define GINTSTS_CURMODE_HOST BIT(0) BIT 212 drivers/usb/dwc2/hw.h #define GI2CCTL_BSYDNE BIT(31) BIT 213 drivers/usb/dwc2/hw.h #define GI2CCTL_RW BIT(30) BIT 214 drivers/usb/dwc2/hw.h #define GI2CCTL_I2CDATSE0 BIT(28) BIT 217 drivers/usb/dwc2/hw.h #define GI2CCTL_I2CSUSPCTL BIT(25) BIT 218 drivers/usb/dwc2/hw.h #define GI2CCTL_ACK BIT(24) BIT 219 drivers/usb/dwc2/hw.h #define GI2CCTL_I2CEN BIT(23) BIT 229 drivers/usb/dwc2/hw.h #define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16) BIT 237 drivers/usb/dwc2/hw.h #define GHWCFG2_OTG_ENABLE_IC_USB BIT(31) BIT 244 drivers/usb/dwc2/hw.h #define GHWCFG2_MULTI_PROC_INT BIT(20) BIT 245 drivers/usb/dwc2/hw.h #define GHWCFG2_DYNAMIC_FIFO BIT(19) BIT 246 drivers/usb/dwc2/hw.h #define GHWCFG2_PERIO_EP_SUPPORTED BIT(18) BIT 263 drivers/usb/dwc2/hw.h #define GHWCFG2_POINT2POINT BIT(5) BIT 283 drivers/usb/dwc2/hw.h #define GHWCFG3_OTG_LPM_EN BIT(15) BIT 284 drivers/usb/dwc2/hw.h #define GHWCFG3_BC_SUPPORT BIT(14) BIT 285 drivers/usb/dwc2/hw.h #define GHWCFG3_OTG_ENABLE_HSIC BIT(13) BIT 286 drivers/usb/dwc2/hw.h #define GHWCFG3_ADP_SUPP BIT(12) BIT 287 drivers/usb/dwc2/hw.h #define GHWCFG3_SYNCH_RESET_TYPE BIT(11) BIT 288 drivers/usb/dwc2/hw.h #define GHWCFG3_OPTIONAL_FEATURES BIT(10) BIT 289 drivers/usb/dwc2/hw.h #define GHWCFG3_VENDOR_CTRL_IF BIT(9) BIT 290 drivers/usb/dwc2/hw.h #define GHWCFG3_I2C BIT(8) BIT 291 drivers/usb/dwc2/hw.h #define GHWCFG3_OTG_FUNC BIT(7) BIT 298 drivers/usb/dwc2/hw.h #define GHWCFG4_DESC_DMA_DYN BIT(31) BIT 299 drivers/usb/dwc2/hw.h #define GHWCFG4_DESC_DMA BIT(30) BIT 302 drivers/usb/dwc2/hw.h #define GHWCFG4_DED_FIFO_EN BIT(25) BIT 304 drivers/usb/dwc2/hw.h #define GHWCFG4_SESSION_END_FILT_EN BIT(24) BIT 305 drivers/usb/dwc2/hw.h #define GHWCFG4_B_VALID_FILT_EN BIT(23) BIT 306 drivers/usb/dwc2/hw.h #define GHWCFG4_A_VALID_FILT_EN BIT(22) BIT 307 drivers/usb/dwc2/hw.h #define GHWCFG4_VBUS_VALID_FILT_EN BIT(21) BIT 308 drivers/usb/dwc2/hw.h #define GHWCFG4_IDDIG_FILT_EN BIT(20) BIT 316 drivers/usb/dwc2/hw.h #define GHWCFG4_ACG_SUPPORTED BIT(12) BIT 317 drivers/usb/dwc2/hw.h #define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11) BIT 318 drivers/usb/dwc2/hw.h #define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10) BIT 319 drivers/usb/dwc2/hw.h #define GHWCFG4_XHIBER BIT(7) BIT 320 drivers/usb/dwc2/hw.h #define GHWCFG4_HIBER BIT(6) BIT 321 drivers/usb/dwc2/hw.h #define GHWCFG4_MIN_AHB_FREQ BIT(5) BIT 322 drivers/usb/dwc2/hw.h #define GHWCFG4_POWER_OPTIMIZ BIT(4) BIT 327 drivers/usb/dwc2/hw.h #define GLPMCFG_INVSELHSIC BIT(31) BIT 328 drivers/usb/dwc2/hw.h #define GLPMCFG_HSICCON BIT(30) BIT 329 drivers/usb/dwc2/hw.h #define GLPMCFG_RSTRSLPSTS BIT(29) BIT 330 drivers/usb/dwc2/hw.h #define GLPMCFG_ENBESL BIT(28) BIT 333 drivers/usb/dwc2/hw.h #define GLPMCFG_SNDLPM BIT(24) BIT 336 drivers/usb/dwc2/hw.h #define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21) BIT 337 drivers/usb/dwc2/hw.h #define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22) BIT 340 drivers/usb/dwc2/hw.h #define GLPMCFG_L1RESUMEOK BIT(16) BIT 341 drivers/usb/dwc2/hw.h #define GLPMCFG_SLPSTS BIT(15) BIT 347 drivers/usb/dwc2/hw.h #define GLPMCFG_ENBLSLPM BIT(7) BIT 348 drivers/usb/dwc2/hw.h #define GLPMCFG_BREMOTEWAKE BIT(6) BIT 351 drivers/usb/dwc2/hw.h #define GLPMCFG_APPL1RES BIT(1) BIT 352 drivers/usb/dwc2/hw.h #define GLPMCFG_LPMCAP BIT(0) BIT 357 drivers/usb/dwc2/hw.h #define GPWRDN_ADP_INT BIT(23) BIT 358 drivers/usb/dwc2/hw.h #define GPWRDN_BSESSVLD BIT(22) BIT 359 drivers/usb/dwc2/hw.h #define GPWRDN_IDSTS BIT(21) BIT 362 drivers/usb/dwc2/hw.h #define GPWRDN_STS_CHGINT_MSK BIT(18) BIT 363 drivers/usb/dwc2/hw.h #define GPWRDN_STS_CHGINT BIT(17) BIT 364 drivers/usb/dwc2/hw.h #define GPWRDN_SRP_DET_MSK BIT(16) BIT 365 drivers/usb/dwc2/hw.h #define GPWRDN_SRP_DET BIT(15) BIT 366 drivers/usb/dwc2/hw.h #define GPWRDN_CONNECT_DET_MSK BIT(14) BIT 367 drivers/usb/dwc2/hw.h #define GPWRDN_CONNECT_DET BIT(13) BIT 368 drivers/usb/dwc2/hw.h #define GPWRDN_DISCONN_DET_MSK BIT(12) BIT 369 drivers/usb/dwc2/hw.h #define GPWRDN_DISCONN_DET BIT(11) BIT 370 drivers/usb/dwc2/hw.h #define GPWRDN_RST_DET_MSK BIT(10) BIT 371 drivers/usb/dwc2/hw.h #define GPWRDN_RST_DET BIT(9) BIT 372 drivers/usb/dwc2/hw.h #define GPWRDN_LNSTSCHG_MSK BIT(8) BIT 373 drivers/usb/dwc2/hw.h #define GPWRDN_LNSTSCHG BIT(7) BIT 374 drivers/usb/dwc2/hw.h #define GPWRDN_DIS_VBUS BIT(6) BIT 375 drivers/usb/dwc2/hw.h #define GPWRDN_PWRDNSWTCH BIT(5) BIT 376 drivers/usb/dwc2/hw.h #define GPWRDN_PWRDNRSTN BIT(4) BIT 377 drivers/usb/dwc2/hw.h #define GPWRDN_PWRDNCLMP BIT(3) BIT 378 drivers/usb/dwc2/hw.h #define GPWRDN_RESTORE BIT(2) BIT 379 drivers/usb/dwc2/hw.h #define GPWRDN_PMUACTV BIT(1) BIT 380 drivers/usb/dwc2/hw.h #define GPWRDN_PMUINTSEL BIT(0) BIT 391 drivers/usb/dwc2/hw.h #define ADPCTL_ADP_TMOUT_INT_MSK BIT(26) BIT 392 drivers/usb/dwc2/hw.h #define ADPCTL_ADP_SNS_INT_MSK BIT(25) BIT 393 drivers/usb/dwc2/hw.h #define ADPCTL_ADP_PRB_INT_MSK BIT(24) BIT 394 drivers/usb/dwc2/hw.h #define ADPCTL_ADP_TMOUT_INT BIT(23) BIT 395 drivers/usb/dwc2/hw.h #define ADPCTL_ADP_SNS_INT BIT(22) BIT 396 drivers/usb/dwc2/hw.h #define ADPCTL_ADP_PRB_INT BIT(21) BIT 397 drivers/usb/dwc2/hw.h #define ADPCTL_ADPENA BIT(20) BIT 398 drivers/usb/dwc2/hw.h #define ADPCTL_ADPRES BIT(19) BIT 399 drivers/usb/dwc2/hw.h #define ADPCTL_ENASNS BIT(18) BIT 400 drivers/usb/dwc2/hw.h #define ADPCTL_ENAPRB BIT(17) BIT 413 drivers/usb/dwc2/hw.h #define GREFCLK_REF_CLK_MODE BIT(14) BIT 418 drivers/usb/dwc2/hw.h #define GINTMSK2_WKUP_ALERT_INT_MSK BIT(0) BIT 421 drivers/usb/dwc2/hw.h #define GINTSTS2_WKUP_ALERT_INT BIT(0) BIT 439 drivers/usb/dwc2/hw.h #define DCFG_DESCDMA_EN BIT(23) BIT 444 drivers/usb/dwc2/hw.h #define DCFG_IPG_ISOC_SUPPORDED BIT(17) BIT 453 drivers/usb/dwc2/hw.h #define DCFG_NZ_STS_OUT_HSHK BIT(2) BIT 462 drivers/usb/dwc2/hw.h #define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19) BIT 463 drivers/usb/dwc2/hw.h #define DCTL_PWRONPRGDONE BIT(11) BIT 464 drivers/usb/dwc2/hw.h #define DCTL_CGOUTNAK BIT(10) BIT 465 drivers/usb/dwc2/hw.h #define DCTL_SGOUTNAK BIT(9) BIT 466 drivers/usb/dwc2/hw.h #define DCTL_CGNPINNAK BIT(8) BIT 467 drivers/usb/dwc2/hw.h #define DCTL_SGNPINNAK BIT(7) BIT 470 drivers/usb/dwc2/hw.h #define DCTL_GOUTNAKSTS BIT(3) BIT 471 drivers/usb/dwc2/hw.h #define DCTL_GNPINNAKSTS BIT(2) BIT 472 drivers/usb/dwc2/hw.h #define DCTL_SFTDISCON BIT(1) BIT 473 drivers/usb/dwc2/hw.h #define DCTL_RMTWKUPSIG BIT(0) BIT 480 drivers/usb/dwc2/hw.h #define DSTS_ERRATICERR BIT(3) BIT 487 drivers/usb/dwc2/hw.h #define DSTS_SUSPSTS BIT(0) BIT 490 drivers/usb/dwc2/hw.h #define DIEPMSK_NAKMSK BIT(13) BIT 491 drivers/usb/dwc2/hw.h #define DIEPMSK_BNAININTRMSK BIT(9) BIT 492 drivers/usb/dwc2/hw.h #define DIEPMSK_TXFIFOUNDRNMSK BIT(8) BIT 493 drivers/usb/dwc2/hw.h #define DIEPMSK_TXFIFOEMPTY BIT(7) BIT 494 drivers/usb/dwc2/hw.h #define DIEPMSK_INEPNAKEFFMSK BIT(6) BIT 495 drivers/usb/dwc2/hw.h #define DIEPMSK_INTKNEPMISMSK BIT(5) BIT 496 drivers/usb/dwc2/hw.h #define DIEPMSK_INTKNTXFEMPMSK BIT(4) BIT 497 drivers/usb/dwc2/hw.h #define DIEPMSK_TIMEOUTMSK BIT(3) BIT 498 drivers/usb/dwc2/hw.h #define DIEPMSK_AHBERRMSK BIT(2) BIT 499 drivers/usb/dwc2/hw.h #define DIEPMSK_EPDISBLDMSK BIT(1) BIT 500 drivers/usb/dwc2/hw.h #define DIEPMSK_XFERCOMPLMSK BIT(0) BIT 503 drivers/usb/dwc2/hw.h #define DOEPMSK_BNAMSK BIT(9) BIT 504 drivers/usb/dwc2/hw.h #define DOEPMSK_BACK2BACKSETUP BIT(6) BIT 505 drivers/usb/dwc2/hw.h #define DOEPMSK_STSPHSERCVDMSK BIT(5) BIT 506 drivers/usb/dwc2/hw.h #define DOEPMSK_OUTTKNEPDISMSK BIT(4) BIT 507 drivers/usb/dwc2/hw.h #define DOEPMSK_SETUPMSK BIT(3) BIT 508 drivers/usb/dwc2/hw.h #define DOEPMSK_AHBERRMSK BIT(2) BIT 509 drivers/usb/dwc2/hw.h #define DOEPMSK_EPDISBLDMSK BIT(1) BIT 510 drivers/usb/dwc2/hw.h #define DOEPMSK_XFERCOMPLMSK BIT(0) BIT 545 drivers/usb/dwc2/hw.h #define DXEPCTL_EPENA BIT(31) BIT 546 drivers/usb/dwc2/hw.h #define DXEPCTL_EPDIS BIT(30) BIT 547 drivers/usb/dwc2/hw.h #define DXEPCTL_SETD1PID BIT(29) BIT 548 drivers/usb/dwc2/hw.h #define DXEPCTL_SETODDFR BIT(29) BIT 549 drivers/usb/dwc2/hw.h #define DXEPCTL_SETD0PID BIT(28) BIT 550 drivers/usb/dwc2/hw.h #define DXEPCTL_SETEVENFR BIT(28) BIT 551 drivers/usb/dwc2/hw.h #define DXEPCTL_SNAK BIT(27) BIT 552 drivers/usb/dwc2/hw.h #define DXEPCTL_CNAK BIT(26) BIT 557 drivers/usb/dwc2/hw.h #define DXEPCTL_STALL BIT(21) BIT 558 drivers/usb/dwc2/hw.h #define DXEPCTL_SNP BIT(20) BIT 565 drivers/usb/dwc2/hw.h #define DXEPCTL_NAKSTS BIT(17) BIT 566 drivers/usb/dwc2/hw.h #define DXEPCTL_DPID BIT(16) BIT 567 drivers/usb/dwc2/hw.h #define DXEPCTL_EOFRNUM BIT(16) BIT 568 drivers/usb/dwc2/hw.h #define DXEPCTL_USBACTEP BIT(15) BIT 580 drivers/usb/dwc2/hw.h #define DXEPINT_SETUP_RCVD BIT(15) BIT 581 drivers/usb/dwc2/hw.h #define DXEPINT_NYETINTRPT BIT(14) BIT 582 drivers/usb/dwc2/hw.h #define DXEPINT_NAKINTRPT BIT(13) BIT 583 drivers/usb/dwc2/hw.h #define DXEPINT_BBLEERRINTRPT BIT(12) BIT 584 drivers/usb/dwc2/hw.h #define DXEPINT_PKTDRPSTS BIT(11) BIT 585 drivers/usb/dwc2/hw.h #define DXEPINT_BNAINTR BIT(9) BIT 586 drivers/usb/dwc2/hw.h #define DXEPINT_TXFIFOUNDRN BIT(8) BIT 587 drivers/usb/dwc2/hw.h #define DXEPINT_OUTPKTERR BIT(8) BIT 588 drivers/usb/dwc2/hw.h #define DXEPINT_TXFEMP BIT(7) BIT 589 drivers/usb/dwc2/hw.h #define DXEPINT_INEPNAKEFF BIT(6) BIT 590 drivers/usb/dwc2/hw.h #define DXEPINT_BACK2BACKSETUP BIT(6) BIT 591 drivers/usb/dwc2/hw.h #define DXEPINT_INTKNEPMIS BIT(5) BIT 592 drivers/usb/dwc2/hw.h #define DXEPINT_STSPHSERCVD BIT(5) BIT 593 drivers/usb/dwc2/hw.h #define DXEPINT_INTKNTXFEMP BIT(4) BIT 594 drivers/usb/dwc2/hw.h #define DXEPINT_OUTTKNEPDIS BIT(4) BIT 595 drivers/usb/dwc2/hw.h #define DXEPINT_TIMEOUT BIT(3) BIT 596 drivers/usb/dwc2/hw.h #define DXEPINT_SETUP BIT(3) BIT 597 drivers/usb/dwc2/hw.h #define DXEPINT_AHBERR BIT(2) BIT 598 drivers/usb/dwc2/hw.h #define DXEPINT_EPDISBLD BIT(1) BIT 599 drivers/usb/dwc2/hw.h #define DXEPINT_XFERCOMPL BIT(0) BIT 616 drivers/usb/dwc2/hw.h #define DOEPTSIZ0_PKTCNT BIT(19) BIT 643 drivers/usb/dwc2/hw.h #define PCGCTL_IF_DEV_MODE BIT(31) BIT 650 drivers/usb/dwc2/hw.h #define PCGCTL_MAX_TERMSEL BIT(19) BIT 653 drivers/usb/dwc2/hw.h #define PCGCTL_PORT_POWER BIT(16) BIT 656 drivers/usb/dwc2/hw.h #define PCGCTL_ESS_REG_RESTORED BIT(13) BIT 657 drivers/usb/dwc2/hw.h #define PCGCTL_EXTND_HIBER_SWITCH BIT(12) BIT 658 drivers/usb/dwc2/hw.h #define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11) BIT 659 drivers/usb/dwc2/hw.h #define PCGCTL_ENBL_EXTND_HIBER BIT(10) BIT 660 drivers/usb/dwc2/hw.h #define PCGCTL_RESTOREMODE BIT(9) BIT 661 drivers/usb/dwc2/hw.h #define PCGCTL_RESETAFTSUSP BIT(8) BIT 662 drivers/usb/dwc2/hw.h #define PCGCTL_DEEP_SLEEP BIT(7) BIT 663 drivers/usb/dwc2/hw.h #define PCGCTL_PHY_IN_SLEEP BIT(6) BIT 664 drivers/usb/dwc2/hw.h #define PCGCTL_ENBL_SLEEP_GATING BIT(5) BIT 665 drivers/usb/dwc2/hw.h #define PCGCTL_RSTPDWNMODULE BIT(3) BIT 666 drivers/usb/dwc2/hw.h #define PCGCTL_PWRCLMP BIT(2) BIT 667 drivers/usb/dwc2/hw.h #define PCGCTL_GATEHCLK BIT(1) BIT 668 drivers/usb/dwc2/hw.h #define PCGCTL_STOPPCLK BIT(0) BIT 672 drivers/usb/dwc2/hw.h #define PCGCCTL1_GATEEN BIT(0) BIT 679 drivers/usb/dwc2/hw.h #define HCFG_MODECHTIMEN BIT(31) BIT 680 drivers/usb/dwc2/hw.h #define HCFG_PERSCHEDENA BIT(26) BIT 685 drivers/usb/dwc2/hw.h #define HCFG_FRLISTEN_16 BIT(24) BIT 691 drivers/usb/dwc2/hw.h #define HCFG_DESCDMA BIT(23) BIT 694 drivers/usb/dwc2/hw.h #define HCFG_ENA32KHZ BIT(7) BIT 695 drivers/usb/dwc2/hw.h #define HCFG_FSLSSUPP BIT(2) BIT 705 drivers/usb/dwc2/hw.h #define HFIR_RLDCTRL BIT(16) BIT 715 drivers/usb/dwc2/hw.h #define TXSTS_QTOP_ODD BIT(31) BIT 720 drivers/usb/dwc2/hw.h #define TXSTS_QTOP_TERMINATE BIT(24) BIT 738 drivers/usb/dwc2/hw.h #define HPRT0_PWR BIT(12) BIT 741 drivers/usb/dwc2/hw.h #define HPRT0_RST BIT(8) BIT 742 drivers/usb/dwc2/hw.h #define HPRT0_SUSP BIT(7) BIT 743 drivers/usb/dwc2/hw.h #define HPRT0_RES BIT(6) BIT 744 drivers/usb/dwc2/hw.h #define HPRT0_OVRCURRCHG BIT(5) BIT 745 drivers/usb/dwc2/hw.h #define HPRT0_OVRCURRACT BIT(4) BIT 746 drivers/usb/dwc2/hw.h #define HPRT0_ENACHG BIT(3) BIT 747 drivers/usb/dwc2/hw.h #define HPRT0_ENA BIT(2) BIT 748 drivers/usb/dwc2/hw.h #define HPRT0_CONNDET BIT(1) BIT 749 drivers/usb/dwc2/hw.h #define HPRT0_CONNSTS BIT(0) BIT 752 drivers/usb/dwc2/hw.h #define HCCHAR_CHENA BIT(31) BIT 753 drivers/usb/dwc2/hw.h #define HCCHAR_CHDIS BIT(30) BIT 754 drivers/usb/dwc2/hw.h #define HCCHAR_ODDFRM BIT(29) BIT 761 drivers/usb/dwc2/hw.h #define HCCHAR_LSPDDEV BIT(17) BIT 762 drivers/usb/dwc2/hw.h #define HCCHAR_EPDIR BIT(15) BIT 769 drivers/usb/dwc2/hw.h #define HCSPLT_SPLTENA BIT(31) BIT 770 drivers/usb/dwc2/hw.h #define HCSPLT_COMPSPLT BIT(16) BIT 785 drivers/usb/dwc2/hw.h #define HCINTMSK_FRM_LIST_ROLL BIT(13) BIT 786 drivers/usb/dwc2/hw.h #define HCINTMSK_XCS_XACT BIT(12) BIT 787 drivers/usb/dwc2/hw.h #define HCINTMSK_BNA BIT(11) BIT 788 drivers/usb/dwc2/hw.h #define HCINTMSK_DATATGLERR BIT(10) BIT 789 drivers/usb/dwc2/hw.h #define HCINTMSK_FRMOVRUN BIT(9) BIT 790 drivers/usb/dwc2/hw.h #define HCINTMSK_BBLERR BIT(8) BIT 791 drivers/usb/dwc2/hw.h #define HCINTMSK_XACTERR BIT(7) BIT 792 drivers/usb/dwc2/hw.h #define HCINTMSK_NYET BIT(6) BIT 793 drivers/usb/dwc2/hw.h #define HCINTMSK_ACK BIT(5) BIT 794 drivers/usb/dwc2/hw.h #define HCINTMSK_NAK BIT(4) BIT 795 drivers/usb/dwc2/hw.h #define HCINTMSK_STALL BIT(3) BIT 796 drivers/usb/dwc2/hw.h #define HCINTMSK_AHBERR BIT(2) BIT 797 drivers/usb/dwc2/hw.h #define HCINTMSK_CHHLTD BIT(1) BIT 798 drivers/usb/dwc2/hw.h #define HCINTMSK_XFERCOMPL BIT(0) BIT 801 drivers/usb/dwc2/hw.h #define TSIZ_DOPNG BIT(31) BIT 841 drivers/usb/dwc2/hw.h #define HOST_DMA_A BIT(31) BIT 844 drivers/usb/dwc2/hw.h #define HOST_DMA_STS_PKTERR BIT(28) BIT 845 drivers/usb/dwc2/hw.h #define HOST_DMA_EOL BIT(26) BIT 846 drivers/usb/dwc2/hw.h #define HOST_DMA_IOC BIT(25) BIT 847 drivers/usb/dwc2/hw.h #define HOST_DMA_SUP BIT(24) BIT 848 drivers/usb/dwc2/hw.h #define HOST_DMA_ALT_QTD BIT(23) BIT 870 drivers/usb/dwc2/hw.h #define DEV_DMA_L BIT(27) BIT 871 drivers/usb/dwc2/hw.h #define DEV_DMA_SHORT BIT(26) BIT 872 drivers/usb/dwc2/hw.h #define DEV_DMA_IOC BIT(25) BIT 873 drivers/usb/dwc2/hw.h #define DEV_DMA_SR BIT(24) BIT 874 drivers/usb/dwc2/hw.h #define DEV_DMA_MTRF BIT(23) BIT 68 drivers/usb/dwc3/core.h #define DWC3_GEVNTCOUNT_EHB BIT(31) BIT 179 drivers/usb/dwc3/core.h #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ BIT 202 drivers/usb/dwc3/core.h #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) BIT 207 drivers/usb/dwc3/core.h #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) BIT 208 drivers/usb/dwc3/core.h #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) BIT 210 drivers/usb/dwc3/core.h #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) BIT 217 drivers/usb/dwc3/core.h #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26) BIT 218 drivers/usb/dwc3/core.h #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15) BIT 220 drivers/usb/dwc3/core.h #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10) BIT 226 drivers/usb/dwc3/core.h #define DWC3_GCTL_U2RSTECN BIT(16) BIT 239 drivers/usb/dwc3/core.h #define DWC3_GCTL_CORESOFTRESET BIT(11) BIT 240 drivers/usb/dwc3/core.h #define DWC3_GCTL_SOFITPSYNC BIT(10) BIT 243 drivers/usb/dwc3/core.h #define DWC3_GCTL_DISSCRAMBLE BIT(3) BIT 244 drivers/usb/dwc3/core.h #define DWC3_GCTL_U2EXIT_LFPS BIT(2) BIT 245 drivers/usb/dwc3/core.h #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) BIT 246 drivers/usb/dwc3/core.h #define DWC3_GCTL_DSBLCLKGTNG BIT(0) BIT 249 drivers/usb/dwc3/core.h #define DWC3_GUCTL_HSTINAUTORETRY BIT(14) BIT 252 drivers/usb/dwc3/core.h #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) BIT 253 drivers/usb/dwc3/core.h #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) BIT 254 drivers/usb/dwc3/core.h #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) BIT 257 drivers/usb/dwc3/core.h #define DWC3_GSTS_OTG_IP BIT(10) BIT 258 drivers/usb/dwc3/core.h #define DWC3_GSTS_BC_IP BIT(9) BIT 259 drivers/usb/dwc3/core.h #define DWC3_GSTS_ADP_IP BIT(8) BIT 260 drivers/usb/dwc3/core.h #define DWC3_GSTS_HOST_IP BIT(7) BIT 261 drivers/usb/dwc3/core.h #define DWC3_GSTS_DEVICE_IP BIT(6) BIT 262 drivers/usb/dwc3/core.h #define DWC3_GSTS_CSR_TIMEOUT BIT(5) BIT 263 drivers/usb/dwc3/core.h #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) BIT 269 drivers/usb/dwc3/core.h #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) BIT 270 drivers/usb/dwc3/core.h #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) BIT 271 drivers/usb/dwc3/core.h #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) BIT 272 drivers/usb/dwc3/core.h #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) BIT 273 drivers/usb/dwc3/core.h #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) BIT 284 drivers/usb/dwc3/core.h #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) BIT 285 drivers/usb/dwc3/core.h #define DWC3_GUSB2PHYACC_BUSY BIT(23) BIT 286 drivers/usb/dwc3/core.h #define DWC3_GUSB2PHYACC_WRITE BIT(22) BIT 292 drivers/usb/dwc3/core.h #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) BIT 293 drivers/usb/dwc3/core.h #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) BIT 294 drivers/usb/dwc3/core.h #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) BIT 295 drivers/usb/dwc3/core.h #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) BIT 296 drivers/usb/dwc3/core.h #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) BIT 300 drivers/usb/dwc3/core.h #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) BIT 301 drivers/usb/dwc3/core.h #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) BIT 302 drivers/usb/dwc3/core.h #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) BIT 303 drivers/usb/dwc3/core.h #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) BIT 308 drivers/usb/dwc3/core.h #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ BIT 318 drivers/usb/dwc3/core.h #define DWC3_GEVNTSIZ_INTMASK BIT(31) BIT 339 drivers/usb/dwc3/core.h #define DWC3_GHWPARAMS1_ENDBC BIT(31) BIT 360 drivers/usb/dwc3/core.h #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) BIT 361 drivers/usb/dwc3/core.h #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) BIT 362 drivers/usb/dwc3/core.h #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) BIT 363 drivers/usb/dwc3/core.h #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) BIT 364 drivers/usb/dwc3/core.h #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) BIT 365 drivers/usb/dwc3/core.h #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) BIT 372 drivers/usb/dwc3/core.h #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) BIT 376 drivers/usb/dwc3/core.h #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) BIT 386 drivers/usb/dwc3/core.h #define DWC3_DCFG_FULLSPEED BIT(0) BIT 392 drivers/usb/dwc3/core.h #define DWC3_DCFG_LPM_CAP BIT(22) BIT 395 drivers/usb/dwc3/core.h #define DWC3_DCTL_RUN_STOP BIT(31) BIT 396 drivers/usb/dwc3/core.h #define DWC3_DCTL_CSFTRST BIT(30) BIT 397 drivers/usb/dwc3/core.h #define DWC3_DCTL_LSFTRST BIT(29) BIT 402 drivers/usb/dwc3/core.h #define DWC3_DCTL_APPL1RES BIT(23) BIT 416 drivers/usb/dwc3/core.h #define DWC3_DCTL_KEEP_CONNECT BIT(19) BIT 417 drivers/usb/dwc3/core.h #define DWC3_DCTL_L1_HIBER_EN BIT(18) BIT 418 drivers/usb/dwc3/core.h #define DWC3_DCTL_CRS BIT(17) BIT 419 drivers/usb/dwc3/core.h #define DWC3_DCTL_CSS BIT(16) BIT 421 drivers/usb/dwc3/core.h #define DWC3_DCTL_INITU2ENA BIT(12) BIT 422 drivers/usb/dwc3/core.h #define DWC3_DCTL_ACCEPTU2ENA BIT(11) BIT 423 drivers/usb/dwc3/core.h #define DWC3_DCTL_INITU1ENA BIT(10) BIT 424 drivers/usb/dwc3/core.h #define DWC3_DCTL_ACCEPTU1ENA BIT(9) BIT 439 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) BIT 440 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) BIT 441 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) BIT 442 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_ERRTICERREN BIT(9) BIT 443 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_SOFEN BIT(7) BIT 444 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_EOPFEN BIT(6) BIT 445 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) BIT 446 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_WKUPEVTEN BIT(4) BIT 447 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_ULSTCNGEN BIT(3) BIT 448 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) BIT 449 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_USBRSTEN BIT(1) BIT 450 drivers/usb/dwc3/core.h #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) BIT 453 drivers/usb/dwc3/core.h #define DWC3_DSTS_DCNRD BIT(29) BIT 456 drivers/usb/dwc3/core.h #define DWC3_DSTS_PWRUPREQ BIT(24) BIT 459 drivers/usb/dwc3/core.h #define DWC3_DSTS_RSS BIT(25) BIT 460 drivers/usb/dwc3/core.h #define DWC3_DSTS_SSS BIT(24) BIT 462 drivers/usb/dwc3/core.h #define DWC3_DSTS_COREIDLE BIT(23) BIT 463 drivers/usb/dwc3/core.h #define DWC3_DSTS_DEVCTRLHLT BIT(22) BIT 468 drivers/usb/dwc3/core.h #define DWC3_DSTS_RXFIFOEMPTY BIT(17) BIT 478 drivers/usb/dwc3/core.h #define DWC3_DSTS_FULLSPEED BIT(0) BIT 496 drivers/usb/dwc3/core.h #define DWC3_DGCMD_CMDACT BIT(10) BIT 497 drivers/usb/dwc3/core.h #define DWC3_DGCMD_CMDIOC BIT(8) BIT 500 drivers/usb/dwc3/core.h #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) BIT 503 drivers/usb/dwc3/core.h #define DWC3_DGCMDPAR_TX_FIFO BIT(5) BIT 505 drivers/usb/dwc3/core.h #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) BIT 512 drivers/usb/dwc3/core.h #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) BIT 513 drivers/usb/dwc3/core.h #define DWC3_DEPCMD_CLEARPENDIN BIT(11) BIT 514 drivers/usb/dwc3/core.h #define DWC3_DEPCMD_CMDACT BIT(10) BIT 515 drivers/usb/dwc3/core.h #define DWC3_DEPCMD_CMDIOC BIT(8) BIT 533 drivers/usb/dwc3/core.h #define DWC3_DALEPENA_EP(n) BIT(n) BIT 546 drivers/usb/dwc3/core.h #define DWC3_OCFG_DISPWRCUTTOFF BIT(5) BIT 547 drivers/usb/dwc3/core.h #define DWC3_OCFG_HIBDISMASK BIT(4) BIT 548 drivers/usb/dwc3/core.h #define DWC3_OCFG_SFTRSTMASK BIT(3) BIT 549 drivers/usb/dwc3/core.h #define DWC3_OCFG_OTGVERSION BIT(2) BIT 550 drivers/usb/dwc3/core.h #define DWC3_OCFG_HNPCAP BIT(1) BIT 551 drivers/usb/dwc3/core.h #define DWC3_OCFG_SRPCAP BIT(0) BIT 554 drivers/usb/dwc3/core.h #define DWC3_OCTL_OTG3GOERR BIT(7) BIT 555 drivers/usb/dwc3/core.h #define DWC3_OCTL_PERIMODE BIT(6) BIT 556 drivers/usb/dwc3/core.h #define DWC3_OCTL_PRTPWRCTL BIT(5) BIT 557 drivers/usb/dwc3/core.h #define DWC3_OCTL_HNPREQ BIT(4) BIT 558 drivers/usb/dwc3/core.h #define DWC3_OCTL_SESREQ BIT(3) BIT 559 drivers/usb/dwc3/core.h #define DWC3_OCTL_TERMSELIDPULSE BIT(2) BIT 560 drivers/usb/dwc3/core.h #define DWC3_OCTL_DEVSETHNPEN BIT(1) BIT 561 drivers/usb/dwc3/core.h #define DWC3_OCTL_HSTSETHNPEN BIT(0) BIT 564 drivers/usb/dwc3/core.h #define DWC3_OEVT_DEVICEMODE BIT(31) BIT 565 drivers/usb/dwc3/core.h #define DWC3_OEVT_XHCIRUNSTPSET BIT(27) BIT 566 drivers/usb/dwc3/core.h #define DWC3_OEVT_DEVRUNSTPSET BIT(26) BIT 567 drivers/usb/dwc3/core.h #define DWC3_OEVT_HIBENTRY BIT(25) BIT 568 drivers/usb/dwc3/core.h #define DWC3_OEVT_CONIDSTSCHNG BIT(24) BIT 569 drivers/usb/dwc3/core.h #define DWC3_OEVT_HRRCONFNOTIF BIT(23) BIT 570 drivers/usb/dwc3/core.h #define DWC3_OEVT_HRRINITNOTIF BIT(22) BIT 571 drivers/usb/dwc3/core.h #define DWC3_OEVT_ADEVIDLE BIT(21) BIT 572 drivers/usb/dwc3/core.h #define DWC3_OEVT_ADEVBHOSTEND BIT(20) BIT 573 drivers/usb/dwc3/core.h #define DWC3_OEVT_ADEVHOST BIT(19) BIT 574 drivers/usb/dwc3/core.h #define DWC3_OEVT_ADEVHNPCHNG BIT(18) BIT 575 drivers/usb/dwc3/core.h #define DWC3_OEVT_ADEVSRPDET BIT(17) BIT 576 drivers/usb/dwc3/core.h #define DWC3_OEVT_ADEVSESSENDDET BIT(16) BIT 577 drivers/usb/dwc3/core.h #define DWC3_OEVT_BDEVBHOSTEND BIT(11) BIT 578 drivers/usb/dwc3/core.h #define DWC3_OEVT_BDEVHNPCHNG BIT(10) BIT 579 drivers/usb/dwc3/core.h #define DWC3_OEVT_BDEVSESSVLDDET BIT(9) BIT 580 drivers/usb/dwc3/core.h #define DWC3_OEVT_BDEVVBUSCHNG BIT(8) BIT 581 drivers/usb/dwc3/core.h #define DWC3_OEVT_BSESSVLD BIT(3) BIT 582 drivers/usb/dwc3/core.h #define DWC3_OEVT_HSTNEGSTS BIT(2) BIT 583 drivers/usb/dwc3/core.h #define DWC3_OEVT_SESREQSTS BIT(1) BIT 584 drivers/usb/dwc3/core.h #define DWC3_OEVT_ERROR BIT(0) BIT 587 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) BIT 588 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) BIT 589 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_HIBENTRYEN BIT(25) BIT 590 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) BIT 591 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) BIT 592 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) BIT 593 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_ADEVIDLEEN BIT(21) BIT 594 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) BIT 595 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_ADEVHOSTEN BIT(19) BIT 596 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) BIT 597 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) BIT 598 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) BIT 599 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) BIT 600 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) BIT 601 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) BIT 602 drivers/usb/dwc3/core.h #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) BIT 605 drivers/usb/dwc3/core.h #define DWC3_OSTS_DEVRUNSTP BIT(13) BIT 606 drivers/usb/dwc3/core.h #define DWC3_OSTS_XHCIRUNSTP BIT(12) BIT 607 drivers/usb/dwc3/core.h #define DWC3_OSTS_PERIPHERALSTATE BIT(4) BIT 608 drivers/usb/dwc3/core.h #define DWC3_OSTS_XHCIPRTPOWER BIT(3) BIT 609 drivers/usb/dwc3/core.h #define DWC3_OSTS_BSESVLD BIT(2) BIT 610 drivers/usb/dwc3/core.h #define DWC3_OSTS_VBUSVLD BIT(1) BIT 611 drivers/usb/dwc3/core.h #define DWC3_OSTS_CONIDSTS BIT(0) BIT 636 drivers/usb/dwc3/core.h #define DWC3_EVENT_PENDING BIT(0) BIT 643 drivers/usb/dwc3/core.h #define DWC3_EP_FLAG_STALLED BIT(0) BIT 644 drivers/usb/dwc3/core.h #define DWC3_EP_FLAG_WEDGED BIT(1) BIT 692 drivers/usb/dwc3/core.h #define DWC3_EP_ENABLED BIT(0) BIT 693 drivers/usb/dwc3/core.h #define DWC3_EP_STALL BIT(1) BIT 694 drivers/usb/dwc3/core.h #define DWC3_EP_WEDGE BIT(2) BIT 695 drivers/usb/dwc3/core.h #define DWC3_EP_TRANSFER_STARTED BIT(3) BIT 696 drivers/usb/dwc3/core.h #define DWC3_EP_END_TRANSFER_PENDING BIT(4) BIT 697 drivers/usb/dwc3/core.h #define DWC3_EP_PENDING_REQUEST BIT(5) BIT 698 drivers/usb/dwc3/core.h #define DWC3_EP_DELAY_START BIT(6) BIT 701 drivers/usb/dwc3/core.h #define DWC3_EP0_DIR_IN BIT(31) BIT 782 drivers/usb/dwc3/core.h #define DWC3_TRB_CTRL_HWO BIT(0) BIT 783 drivers/usb/dwc3/core.h #define DWC3_TRB_CTRL_LST BIT(1) BIT 784 drivers/usb/dwc3/core.h #define DWC3_TRB_CTRL_CHN BIT(2) BIT 785 drivers/usb/dwc3/core.h #define DWC3_TRB_CTRL_CSP BIT(3) BIT 787 drivers/usb/dwc3/core.h #define DWC3_TRB_CTRL_ISP_IMI BIT(10) BIT 788 drivers/usb/dwc3/core.h #define DWC3_TRB_CTRL_IOC BIT(11) BIT 1282 drivers/usb/dwc3/core.h #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) BIT 1285 drivers/usb/dwc3/core.h #define DEPEVT_STATUS_BUSERR BIT(0) BIT 1286 drivers/usb/dwc3/core.h #define DEPEVT_STATUS_SHORT BIT(1) BIT 1287 drivers/usb/dwc3/core.h #define DEPEVT_STATUS_IOC BIT(2) BIT 1288 drivers/usb/dwc3/core.h #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */ BIT 1289 drivers/usb/dwc3/core.h #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */ BIT 1388 drivers/usb/dwc3/core.h #define DWC3_HAS_PERIPHERAL BIT(0) BIT 1389 drivers/usb/dwc3/core.h #define DWC3_HAS_XHCI BIT(1) BIT 1390 drivers/usb/dwc3/core.h #define DWC3_HAS_OTG BIT(3) BIT 29 drivers/usb/dwc3/dwc3-keystone.c #define USBSS_IRQ_EOI_LINE(n) BIT(n) BIT 30 drivers/usb/dwc3/dwc3-keystone.c #define USBSS_IRQ_EVENT_ST BIT(0) BIT 31 drivers/usb/dwc3/dwc3-keystone.c #define USBSS_IRQ_COREIRQ_EN BIT(0) BIT 32 drivers/usb/dwc3/dwc3-keystone.c #define USBSS_IRQ_COREIRQ_CLR BIT(0) BIT 38 drivers/usb/dwc3/dwc3-meson-g12a.c #define U2P_R0_HOST_DEVICE BIT(0) BIT 39 drivers/usb/dwc3/dwc3-meson-g12a.c #define U2P_R0_POWER_OK BIT(1) BIT 40 drivers/usb/dwc3/dwc3-meson-g12a.c #define U2P_R0_HAST_MODE BIT(2) BIT 41 drivers/usb/dwc3/dwc3-meson-g12a.c #define U2P_R0_POWER_ON_RESET BIT(3) BIT 42 drivers/usb/dwc3/dwc3-meson-g12a.c #define U2P_R0_ID_PULLUP BIT(4) BIT 43 drivers/usb/dwc3/dwc3-meson-g12a.c #define U2P_R0_DRV_VBUS BIT(5) BIT 46 drivers/usb/dwc3/dwc3-meson-g12a.c #define U2P_R1_PHY_READY BIT(0) BIT 47 drivers/usb/dwc3/dwc3-meson-g12a.c #define U2P_R1_ID_DIG BIT(1) BIT 48 drivers/usb/dwc3/dwc3-meson-g12a.c #define U2P_R1_OTG_SESSION_VALID BIT(2) BIT 49 drivers/usb/dwc3/dwc3-meson-g12a.c #define U2P_R1_VBUS_VALID BIT(3) BIT 54 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) BIT 55 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) BIT 58 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R0_U2D_ACT BIT(31) BIT 61 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R1_U3H_BIGENDIAN_GS BIT(0) BIT 62 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R1_U3H_PME_ENABLE BIT(1) BIT 66 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16) BIT 67 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17) BIT 68 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18) BIT 77 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R3_P30_SSC_ENABLE BIT(0) BIT 80 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R3_P30_REF_SSP_EN BIT(13) BIT 83 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R4_P21_PORT_RESET_0 BIT(0) BIT 84 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R4_P21_SLEEP_M0 BIT(1) BIT 86 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R4_P21_ONLY BIT(4) BIT 89 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R5_ID_DIG_SYNC BIT(0) BIT 90 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R5_ID_DIG_REG BIT(1) BIT 92 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R5_ID_DIG_EN_0 BIT(4) BIT 93 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R5_ID_DIG_EN_1 BIT(5) BIT 94 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R5_ID_DIG_CURR BIT(6) BIT 95 drivers/usb/dwc3/dwc3-meson-g12a.c #define USB_R5_ID_DIG_IRQ BIT(7) BIT 73 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_SYSCONFIG_DMADISABLE BIT(16) BIT 76 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQ_EOI_LINE_NUMBER BIT(0) BIT 79 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQO_COREIRQ_ST BIT(0) BIT 82 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQMISC_DMADISABLECLR BIT(17) BIT 83 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQMISC_OEVT BIT(16) BIT 84 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQMISC_DRVVBUS_RISE BIT(13) BIT 85 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQMISC_CHRGVBUS_RISE BIT(12) BIT 86 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE BIT(11) BIT 87 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQMISC_IDPULLUP_RISE BIT(8) BIT 88 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQMISC_DRVVBUS_FALL BIT(5) BIT 89 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQMISC_CHRGVBUS_FALL BIT(4) BIT 90 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL BIT(3) BIT 91 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_IRQMISC_IDPULLUP_FALL BIT(0) BIT 94 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS BIT(5) BIT 95 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS BIT(4) BIT 96 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS BIT(3) BIT 97 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP BIT(0) BIT 100 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE BIT(31) BIT 101 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT BIT(9) BIT 102 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE BIT(8) BIT 103 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_CTRL_IDDIG BIT(4) BIT 104 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_CTRL_SESSEND BIT(3) BIT 105 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2) BIT 106 drivers/usb/dwc3/dwc3-omap.c #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1) BIT 27 drivers/usb/dwc3/dwc3-qcom.c #define UTMI_OTG_VBUS_VALID BIT(20) BIT 28 drivers/usb/dwc3/dwc3-qcom.c #define SW_SESSVLD_SEL BIT(28) BIT 31 drivers/usb/dwc3/dwc3-qcom.c #define LANE0_PWR_PRESENT BIT(24) BIT 34 drivers/usb/dwc3/dwc3-qcom.c #define PIPE_UTMI_CLK_SEL BIT(0) BIT 35 drivers/usb/dwc3/dwc3-qcom.c #define PIPE3_PHYSTATUS_SW BIT(3) BIT 36 drivers/usb/dwc3/dwc3-qcom.c #define PIPE_UTMI_CLK_DIS BIT(8) BIT 39 drivers/usb/dwc3/dwc3-qcom.c #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) BIT 40 drivers/usb/dwc3/dwc3-qcom.c #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) BIT 38 drivers/usb/dwc3/dwc3-st.c #define AUX_CLK_EN BIT(0) BIT 39 drivers/usb/dwc3/dwc3-st.c #define SW_PIPEW_RESET_N BIT(4) BIT 40 drivers/usb/dwc3/dwc3-st.c #define EXT_CFG_RESET_N BIT(8) BIT 45 drivers/usb/dwc3/dwc3-st.c #define XHCI_REVISION BIT(12) BIT 67 drivers/usb/dwc3/dwc3-st.c #define USB3_DEVICE_NOT_HOST BIT(0) BIT 68 drivers/usb/dwc3/dwc3-st.c #define USB3_FORCE_VBUSVALID BIT(1) BIT 69 drivers/usb/dwc3/dwc3-st.c #define USB3_DELAY_VBUSVALID BIT(2) BIT 70 drivers/usb/dwc3/dwc3-st.c #define USB3_SEL_FORCE_OPMODE BIT(4) BIT 72 drivers/usb/dwc3/dwc3-st.c #define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) BIT 73 drivers/usb/dwc3/dwc3-st.c #define USB3_FORCE_DPPULLDOWN2 BIT(9) BIT 74 drivers/usb/dwc3/dwc3-st.c #define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) BIT 75 drivers/usb/dwc3/dwc3-st.c #define USB3_FORCE_DMPULLDOWN2 BIT(11) BIT 3115 drivers/usb/dwc3/gadget.c unsigned int is_ss = evtinfo & BIT(4); BIT 24 drivers/usb/dwc3/gadget.h #define DWC3_DEPCFG_XFER_COMPLETE_EN BIT(8) BIT 25 drivers/usb/dwc3/gadget.h #define DWC3_DEPCFG_XFER_IN_PROGRESS_EN BIT(9) BIT 26 drivers/usb/dwc3/gadget.h #define DWC3_DEPCFG_XFER_NOT_READY_EN BIT(10) BIT 27 drivers/usb/dwc3/gadget.h #define DWC3_DEPCFG_FIFO_ERROR_EN BIT(11) BIT 28 drivers/usb/dwc3/gadget.h #define DWC3_DEPCFG_STREAM_EVENT_EN BIT(13) BIT 30 drivers/usb/dwc3/gadget.h #define DWC3_DEPCFG_STREAM_CAPABLE BIT(24) BIT 32 drivers/usb/dwc3/gadget.h #define DWC3_DEPCFG_BULK_BASED BIT(30) BIT 33 drivers/usb/dwc3/gadget.h #define DWC3_DEPCFG_FIFO_BASED BIT(31) BIT 42 drivers/usb/dwc3/gadget.h #define DWC3_DEPCFG_IGN_SEQ_NUM BIT(31) BIT 45 drivers/usb/dwc3/gadget.h #define DWC3_DEPCFG_ACTION_RESTORE BIT(30) BIT 37 drivers/usb/early/xhci-dbc.h #define CTRL_DBC_RUN BIT(0) BIT 38 drivers/usb/early/xhci-dbc.h #define CTRL_PORT_ENABLE BIT(1) BIT 39 drivers/usb/early/xhci-dbc.h #define CTRL_HALT_OUT_TR BIT(2) BIT 40 drivers/usb/early/xhci-dbc.h #define CTRL_HALT_IN_TR BIT(3) BIT 41 drivers/usb/early/xhci-dbc.h #define CTRL_DBC_RUN_CHANGE BIT(4) BIT 42 drivers/usb/early/xhci-dbc.h #define CTRL_DBC_ENABLE BIT(31) BIT 46 drivers/usb/early/xhci-dbc.h #define PORTSC_CONN_STATUS BIT(0) BIT 47 drivers/usb/early/xhci-dbc.h #define PORTSC_CONN_CHANGE BIT(17) BIT 48 drivers/usb/early/xhci-dbc.h #define PORTSC_RESET_CHANGE BIT(21) BIT 49 drivers/usb/early/xhci-dbc.h #define PORTSC_LINK_CHANGE BIT(22) BIT 50 drivers/usb/early/xhci-dbc.h #define PORTSC_CONFIG_CHANGE BIT(23) BIT 205 drivers/usb/early/xhci-dbc.h #define XDBC_FLAGS_INITIALIZED BIT(0) BIT 206 drivers/usb/early/xhci-dbc.h #define XDBC_FLAGS_IN_STALL BIT(1) BIT 207 drivers/usb/early/xhci-dbc.h #define XDBC_FLAGS_OUT_STALL BIT(2) BIT 208 drivers/usb/early/xhci-dbc.h #define XDBC_FLAGS_IN_PROCESS BIT(3) BIT 209 drivers/usb/early/xhci-dbc.h #define XDBC_FLAGS_OUT_PROCESS BIT(4) BIT 210 drivers/usb/early/xhci-dbc.h #define XDBC_FLAGS_CONFIGURED BIT(5) BIT 414 drivers/usb/gadget/function/f_eem.c if (header & BIT(15)) { BIT 424 drivers/usb/gadget/function/f_eem.c if (header & BIT(14)) BIT 442 drivers/usb/gadget/function/f_eem.c put_unaligned_le16(BIT(15) | BIT(11) | len, BIT 482 drivers/usb/gadget/function/f_eem.c if (header & BIT(14)) { BIT 1837 drivers/usb/gadget/udc/at91_udc.c ep->int_mask = BIT(i); BIT 813 drivers/usb/gadget/udc/bcm63xx_udc.c usb_dma_writel(udc, BIT(BCM63XX_NUM_IUDMA)-1, ENETDMA_GLB_IRQMASK_REG); BIT 850 drivers/usb/gadget/udc/bcm63xx_udc.c val = BIT(USBD_EVENT_IRQ_USB_RESET) | BIT 851 drivers/usb/gadget/udc/bcm63xx_udc.c BIT(USBD_EVENT_IRQ_SETUP) | BIT 852 drivers/usb/gadget/udc/bcm63xx_udc.c BIT(USBD_EVENT_IRQ_SETCFG) | BIT 853 drivers/usb/gadget/udc/bcm63xx_udc.c BIT(USBD_EVENT_IRQ_SETINTF) | BIT 854 drivers/usb/gadget/udc/bcm63xx_udc.c BIT(USBD_EVENT_IRQ_USB_LINK); BIT 872 drivers/usb/gadget/udc/bcm63xx_udc.c u32 val, portmask = BIT(udc->pd->port_no); BIT 912 drivers/usb/gadget/udc/bcm63xx_udc.c u32 val, portmask = BIT(udc->pd->port_no); BIT 1982 drivers/usb/gadget/udc/bcm63xx_udc.c if (stat & BIT(USBD_EVENT_IRQ_USB_LINK)) { BIT 1993 drivers/usb/gadget/udc/bcm63xx_udc.c if (stat & BIT(USBD_EVENT_IRQ_USB_RESET)) { BIT 2004 drivers/usb/gadget/udc/bcm63xx_udc.c if (stat & BIT(USBD_EVENT_IRQ_SETUP)) { BIT 2011 drivers/usb/gadget/udc/bcm63xx_udc.c if (stat & BIT(USBD_EVENT_IRQ_SETCFG)) { BIT 2016 drivers/usb/gadget/udc/bcm63xx_udc.c if (stat & BIT(USBD_EVENT_IRQ_SETINTF)) { BIT 47 drivers/usb/gadget/udc/gr_udc.h #define GR_EPCTRL_PI BIT(20) BIT 48 drivers/usb/gadget/udc/gr_udc.h #define GR_EPCTRL_CB BIT(19) BIT 49 drivers/usb/gadget/udc/gr_udc.h #define GR_EPCTRL_CS BIT(18) BIT 56 drivers/usb/gadget/udc/gr_udc.h #define GR_EPCTRL_EH BIT(2) BIT 57 drivers/usb/gadget/udc/gr_udc.h #define GR_EPCTRL_ED BIT(1) BIT 58 drivers/usb/gadget/udc/gr_udc.h #define GR_EPCTRL_EV BIT(0) BIT 60 drivers/usb/gadget/udc/gr_udc.h #define GR_DMACTRL_AE BIT(10) BIT 61 drivers/usb/gadget/udc/gr_udc.h #define GR_DMACTRL_AD BIT(3) BIT 62 drivers/usb/gadget/udc/gr_udc.h #define GR_DMACTRL_AI BIT(2) BIT 63 drivers/usb/gadget/udc/gr_udc.h #define GR_DMACTRL_IE BIT(1) BIT 64 drivers/usb/gadget/udc/gr_udc.h #define GR_DMACTRL_DA BIT(0) BIT 66 drivers/usb/gadget/udc/gr_udc.h #define GR_EPSTAT_PT BIT(29) BIT 67 drivers/usb/gadget/udc/gr_udc.h #define GR_EPSTAT_PR BIT(29) BIT 72 drivers/usb/gadget/udc/gr_udc.h #define GR_EPSTAT_B1 BIT(2) BIT 73 drivers/usb/gadget/udc/gr_udc.h #define GR_EPSTAT_B0 BIT(1) BIT 74 drivers/usb/gadget/udc/gr_udc.h #define GR_EPSTAT_BS BIT(0) BIT 76 drivers/usb/gadget/udc/gr_udc.h #define GR_CONTROL_SI BIT(31) BIT 77 drivers/usb/gadget/udc/gr_udc.h #define GR_CONTROL_UI BIT(30) BIT 78 drivers/usb/gadget/udc/gr_udc.h #define GR_CONTROL_VI BIT(29) BIT 79 drivers/usb/gadget/udc/gr_udc.h #define GR_CONTROL_SP BIT(28) BIT 80 drivers/usb/gadget/udc/gr_udc.h #define GR_CONTROL_FI BIT(27) BIT 81 drivers/usb/gadget/udc/gr_udc.h #define GR_CONTROL_EP BIT(14) BIT 82 drivers/usb/gadget/udc/gr_udc.h #define GR_CONTROL_DH BIT(13) BIT 83 drivers/usb/gadget/udc/gr_udc.h #define GR_CONTROL_RW BIT(12) BIT 86 drivers/usb/gadget/udc/gr_udc.h #define GR_CONTROL_TM BIT(8) BIT 89 drivers/usb/gadget/udc/gr_udc.h #define GR_CONTROL_SU BIT(0) BIT 95 drivers/usb/gadget/udc/gr_udc.h #define GR_STATUS_DM BIT(23) BIT 96 drivers/usb/gadget/udc/gr_udc.h #define GR_STATUS_SU BIT(17) BIT 97 drivers/usb/gadget/udc/gr_udc.h #define GR_STATUS_UR BIT(16) BIT 98 drivers/usb/gadget/udc/gr_udc.h #define GR_STATUS_VB BIT(15) BIT 99 drivers/usb/gadget/udc/gr_udc.h #define GR_STATUS_SP BIT(14) BIT 122 drivers/usb/gadget/udc/gr_udc.h #define GR_DESC_OUT_CTRL_SE BIT(17) BIT 123 drivers/usb/gadget/udc/gr_udc.h #define GR_DESC_OUT_CTRL_IE BIT(15) BIT 124 drivers/usb/gadget/udc/gr_udc.h #define GR_DESC_OUT_CTRL_NX BIT(14) BIT 125 drivers/usb/gadget/udc/gr_udc.h #define GR_DESC_OUT_CTRL_EN BIT(13) BIT 128 drivers/usb/gadget/udc/gr_udc.h #define GR_DESC_IN_CTRL_MO BIT(18) BIT 129 drivers/usb/gadget/udc/gr_udc.h #define GR_DESC_IN_CTRL_PI BIT(17) BIT 130 drivers/usb/gadget/udc/gr_udc.h #define GR_DESC_IN_CTRL_ML BIT(16) BIT 131 drivers/usb/gadget/udc/gr_udc.h #define GR_DESC_IN_CTRL_IE BIT(15) BIT 132 drivers/usb/gadget/udc/gr_udc.h #define GR_DESC_IN_CTRL_NX BIT(14) BIT 133 drivers/usb/gadget/udc/gr_udc.h #define GR_DESC_IN_CTRL_EN BIT(13) BIT 158 drivers/usb/gadget/udc/net2280.c #define valid_bit cpu_to_le32(BIT(VALID_BIT)) BIT 159 drivers/usb/gadget/udc/net2280.c #define dma_done_ie cpu_to_le32(BIT(DMA_DONE_INTERRUPT_ENABLE)) BIT 172 drivers/usb/gadget/udc/net2280.c tmp |= BIT(ep->num); BIT 174 drivers/usb/gadget/udc/net2280.c tmp |= BIT(ep_bit[ep->num]); BIT 242 drivers/usb/gadget/udc/net2280.c writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat); BIT 263 drivers/usb/gadget/udc/net2280.c writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE), BIT 282 drivers/usb/gadget/udc/net2280.c tmp |= BIT(ENDPOINT_ENABLE); BIT 288 drivers/usb/gadget/udc/net2280.c tmp |= BIT(IN_ENDPOINT_ENABLE); BIT 291 drivers/usb/gadget/udc/net2280.c tmp |= BIT(OUT_ENDPOINT_ENABLE); BIT 306 drivers/usb/gadget/udc/net2280.c writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); BIT 311 drivers/usb/gadget/udc/net2280.c writel(BIT(CLEAR_NAK_OUT_PACKETS) | BIT 312 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_NAK_OUT_PACKETS_MODE), &ep->regs->ep_rsp); BIT 323 drivers/usb/gadget/udc/net2280.c tmp = BIT(DATA_PACKET_RECEIVED_INTERRUPT_ENABLE) | BIT 324 drivers/usb/gadget/udc/net2280.c BIT(DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE); BIT 329 drivers/usb/gadget/udc/net2280.c tmp = BIT((8 + ep->num)); /* completion */ BIT 338 drivers/usb/gadget/udc/net2280.c tmp = BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE); BIT 393 drivers/usb/gadget/udc/net2280.c writel(BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) | BIT 394 drivers/usb/gadget/udc/net2280.c BIT(DMA_TRANSACTION_DONE_INTERRUPT) | BIT 395 drivers/usb/gadget/udc/net2280.c BIT(DMA_ABORT), BIT 399 drivers/usb/gadget/udc/net2280.c tmp &= ~BIT(ep->num); BIT 403 drivers/usb/gadget/udc/net2280.c tmp &= ~BIT((8 + ep->num)); /* completion */ BIT 412 drivers/usb/gadget/udc/net2280.c tmp = BIT(SET_NAK_OUT_PACKETS_MODE) | BIT 413 drivers/usb/gadget/udc/net2280.c BIT(SET_NAK_OUT_PACKETS) | BIT 414 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_EP_HIDE_STATUS_PHASE) | BIT 415 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_INTERRUPT_MODE); BIT 418 drivers/usb/gadget/udc/net2280.c tmp = BIT(CLEAR_NAK_OUT_PACKETS_MODE) | BIT 419 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_NAK_OUT_PACKETS) | BIT 420 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_EP_HIDE_STATUS_PHASE) | BIT 421 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_INTERRUPT_MODE); BIT 425 drivers/usb/gadget/udc/net2280.c tmp |= BIT(CLEAR_ENDPOINT_TOGGLE) | BIT 426 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_ENDPOINT_HALT); BIT 432 drivers/usb/gadget/udc/net2280.c tmp = BIT(FIFO_OVERFLOW) | BIT 433 drivers/usb/gadget/udc/net2280.c BIT(FIFO_UNDERFLOW); BIT 437 drivers/usb/gadget/udc/net2280.c writel(tmp | BIT(TIMEOUT) | BIT 438 drivers/usb/gadget/udc/net2280.c BIT(USB_STALL_SENT) | BIT 439 drivers/usb/gadget/udc/net2280.c BIT(USB_IN_NAK_SENT) | BIT 440 drivers/usb/gadget/udc/net2280.c BIT(USB_IN_ACK_RCVD) | BIT 441 drivers/usb/gadget/udc/net2280.c BIT(USB_OUT_PING_NAK_SENT) | BIT 442 drivers/usb/gadget/udc/net2280.c BIT(USB_OUT_ACK_SENT) | BIT 443 drivers/usb/gadget/udc/net2280.c BIT(FIFO_FLUSH) | BIT 444 drivers/usb/gadget/udc/net2280.c BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) | BIT 445 drivers/usb/gadget/udc/net2280.c BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) | BIT 446 drivers/usb/gadget/udc/net2280.c BIT(DATA_PACKET_RECEIVED_INTERRUPT) | BIT 447 drivers/usb/gadget/udc/net2280.c BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | BIT 448 drivers/usb/gadget/udc/net2280.c BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | BIT 449 drivers/usb/gadget/udc/net2280.c BIT(DATA_IN_TOKEN_INTERRUPT), BIT 469 drivers/usb/gadget/udc/net2280.c writel(BIT(DMA_ABORT_DONE_INTERRUPT) | BIT 470 drivers/usb/gadget/udc/net2280.c BIT(DMA_PAUSE_DONE_INTERRUPT) | BIT 471 drivers/usb/gadget/udc/net2280.c BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) | BIT 472 drivers/usb/gadget/udc/net2280.c BIT(DMA_TRANSACTION_DONE_INTERRUPT), BIT 484 drivers/usb/gadget/udc/net2280.c tmp &= ~BIT(ep_bit[ep->num]); BIT 489 drivers/usb/gadget/udc/net2280.c tmp &= ~BIT((8 + ep->num)); /* completion */ BIT 495 drivers/usb/gadget/udc/net2280.c writel(BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) | BIT 496 drivers/usb/gadget/udc/net2280.c BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) | BIT 497 drivers/usb/gadget/udc/net2280.c BIT(FIFO_OVERFLOW) | BIT 498 drivers/usb/gadget/udc/net2280.c BIT(DATA_PACKET_RECEIVED_INTERRUPT) | BIT 499 drivers/usb/gadget/udc/net2280.c BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | BIT 500 drivers/usb/gadget/udc/net2280.c BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | BIT 501 drivers/usb/gadget/udc/net2280.c BIT(DATA_IN_TOKEN_INTERRUPT), &ep->regs->ep_stat); BIT 677 drivers/usb/gadget/udc/net2280.c if (tmp & BIT(NAK_OUT_PACKETS)) { BIT 680 drivers/usb/gadget/udc/net2280.c writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); BIT 683 drivers/usb/gadget/udc/net2280.c writel(BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | BIT 684 drivers/usb/gadget/udc/net2280.c BIT(DATA_PACKET_RECEIVED_INTERRUPT), BIT 686 drivers/usb/gadget/udc/net2280.c writel(BIT(FIFO_FLUSH), statp); BIT 690 drivers/usb/gadget/udc/net2280.c if (tmp & BIT(DATA_OUT_PING_TOKEN_INTERRUPT) && BIT 696 drivers/usb/gadget/udc/net2280.c handshake(statp, BIT(USB_OUT_PING_NAK_SENT), BIT 697 drivers/usb/gadget/udc/net2280.c BIT(USB_OUT_PING_NAK_SENT), usec); BIT 723 drivers/usb/gadget/udc/net2280.c if ((tmp & BIT(NAK_OUT_PACKETS))) BIT 725 drivers/usb/gadget/udc/net2280.c else if ((tmp & BIT(FIFO_FULL))) { BIT 742 drivers/usb/gadget/udc/net2280.c if (count == 0 && (tmp & BIT(NAK_OUT_PACKETS)) == 0) BIT 788 drivers/usb/gadget/udc/net2280.c writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp); BIT 808 drivers/usb/gadget/udc/net2280.c dmacount |= BIT(DMA_DIRECTION); BIT 811 drivers/usb/gadget/udc/net2280.c dmacount |= BIT(END_OF_CHAIN); BIT 815 drivers/usb/gadget/udc/net2280.c dmacount |= BIT(VALID_BIT); BIT 816 drivers/usb/gadget/udc/net2280.c dmacount |= BIT(DMA_DONE_INTERRUPT_ENABLE); BIT 828 drivers/usb/gadget/udc/net2280.c BIT(DMA_CLEAR_COUNT_ENABLE) | BIT 831 drivers/usb/gadget/udc/net2280.c BIT(DMA_VALID_BIT_POLLING_ENABLE) | BIT 832 drivers/usb/gadget/udc/net2280.c BIT(DMA_VALID_BIT_ENABLE) | BIT 833 drivers/usb/gadget/udc/net2280.c BIT(DMA_SCATTER_GATHER_ENABLE) | BIT 835 drivers/usb/gadget/udc/net2280.c BIT(DMA_ENABLE); BIT 839 drivers/usb/gadget/udc/net2280.c handshake(&dma->dmactl, BIT(DMA_ENABLE), 0, 50); BIT 844 drivers/usb/gadget/udc/net2280.c writel(readl(&dma->dmactl) & ~BIT(DMA_ENABLE), &dma->dmactl); BIT 851 drivers/usb/gadget/udc/net2280.c unsigned int tmp = BIT(VALID_BIT) | (ep->is_in << DMA_DIRECTION); BIT 854 drivers/usb/gadget/udc/net2280.c tmp |= BIT(END_OF_CHAIN); BIT 861 drivers/usb/gadget/udc/net2280.c dmactl |= BIT(DMA_REQUEST_OUTSTANDING); BIT 867 drivers/usb/gadget/udc/net2280.c writel(BIT(DMA_START), &dma->dmastat); BIT 878 drivers/usb/gadget/udc/net2280.c WARN_ON(readl(&dma->dmactl) & BIT(DMA_ENABLE)); BIT 883 drivers/usb/gadget/udc/net2280.c BIT(NAK_OUT_PACKETS))) { BIT 884 drivers/usb/gadget/udc/net2280.c writel(BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT), BIT 897 drivers/usb/gadget/udc/net2280.c writel(BIT(DMA_DONE_INTERRUPT_ENABLE) | tmp, BIT 902 drivers/usb/gadget/udc/net2280.c writel(BIT(DMA_ENABLE), &dma->dmactl); BIT 903 drivers/usb/gadget/udc/net2280.c writel(BIT(DMA_START), &dma->dmastat); BIT 918 drivers/usb/gadget/udc/net2280.c tmp |= BIT(DMA_FIFO_VALIDATE); BIT 928 drivers/usb/gadget/udc/net2280.c req->td->dmacount |= cpu_to_le32(BIT(END_OF_CHAIN)); BIT 1043 drivers/usb/gadget/udc/net2280.c (readl(&ep->regs->ep_rsp) & BIT(CLEAR_ENDPOINT_HALT)))) { BIT 1065 drivers/usb/gadget/udc/net2280.c if ((s & BIT(FIFO_EMPTY)) == 0) { BIT 1087 drivers/usb/gadget/udc/net2280.c if (req && (s & BIT(NAK_OUT_PACKETS))) BIT 1088 drivers/usb/gadget/udc/net2280.c writel(BIT(CLEAR_NAK_OUT_PACKETS), BIT 1150 drivers/usb/gadget/udc/net2280.c if ((req_dma_count & BIT(VALID_BIT)) != 0) BIT 1176 drivers/usb/gadget/udc/net2280.c if ((ep_stat & BIT(NAK_OUT_PACKETS)) == 0) { BIT 1216 drivers/usb/gadget/udc/net2280.c writel(BIT(DMA_ABORT), &ep->dma->dmastat); BIT 1419 drivers/usb/gadget/udc/net2280.c avail = readl(&ep->regs->ep_avail) & (BIT(12) - 1); BIT 1445 drivers/usb/gadget/udc/net2280.c writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat); BIT 1494 drivers/usb/gadget/udc/net2280.c if (tmp & BIT(DEVICE_REMOTE_WAKEUP_ENABLE)) BIT 1495 drivers/usb/gadget/udc/net2280.c writel(BIT(GENERATE_RESUME), &dev->usb->usbstat); BIT 1515 drivers/usb/gadget/udc/net2280.c tmp |= BIT(SELF_POWERED_STATUS); BIT 1518 drivers/usb/gadget/udc/net2280.c tmp &= ~BIT(SELF_POWERED_STATUS); BIT 1542 drivers/usb/gadget/udc/net2280.c writel(tmp | BIT(USB_DETECT_ENABLE), &dev->usb->usbctl); BIT 1544 drivers/usb/gadget/udc/net2280.c writel(tmp & ~BIT(USB_DETECT_ENABLE), &dev->usb->usbctl); BIT 1695 drivers/usb/gadget/udc/net2280.c if (t1 & BIT(VBUS_PIN)) { BIT 1696 drivers/usb/gadget/udc/net2280.c if (t2 & BIT(HIGH_SPEED)) BIT 1731 drivers/usb/gadget/udc/net2280.c (t2 & BIT(CLEAR_NAK_OUT_PACKETS)) BIT 1733 drivers/usb/gadget/udc/net2280.c (t2 & BIT(CLEAR_EP_HIDE_STATUS_PHASE)) BIT 1735 drivers/usb/gadget/udc/net2280.c (t2 & BIT(CLEAR_EP_FORCE_CRC_ERROR)) BIT 1737 drivers/usb/gadget/udc/net2280.c (t2 & BIT(CLEAR_INTERRUPT_MODE)) BIT 1739 drivers/usb/gadget/udc/net2280.c (t2 & BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE)) BIT 1741 drivers/usb/gadget/udc/net2280.c (t2 & BIT(CLEAR_NAK_OUT_PACKETS_MODE)) BIT 1743 drivers/usb/gadget/udc/net2280.c (t2 & BIT(CLEAR_ENDPOINT_TOGGLE)) BIT 1745 drivers/usb/gadget/udc/net2280.c (t2 & BIT(CLEAR_ENDPOINT_HALT)) BIT 1972 drivers/usb/gadget/udc/net2280.c tmp_reg &= ~BIT(NON_CTRL_IN_TOLERATE_BAD_DIR); BIT 1975 drivers/usb/gadget/udc/net2280.c tmp_reg |= BIT(EP_INITIALIZED); BIT 1998 drivers/usb/gadget/udc/net2280.c tmp = ((0 << ENDPOINT_NUMBER) | BIT(ENDPOINT_DIRECTION) | BIT 2001 drivers/usb/gadget/udc/net2280.c BIT(OUT_ENDPOINT_ENABLE) | BIT(IN_ENDPOINT_ENABLE) : BIT 2002 drivers/usb/gadget/udc/net2280.c BIT(ENDPOINT_ENABLE))); BIT 2008 drivers/usb/gadget/udc/net2280.c tmp = ((0 << ENDPOINT_NUMBER) | BIT(ENDPOINT_ENABLE)); BIT 2025 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_ACK_ERROR_CODE) | 0); BIT 2035 drivers/usb/gadget/udc/net2280.c BIT(NON_CTRL_IN_TOLERATE_BAD_DIR) | 0); BIT 2039 drivers/usb/gadget/udc/net2280.c ~BIT(EP_INITIALIZED); BIT 2083 drivers/usb/gadget/udc/net2280.c writel(~(u32)BIT(SUSPEND_REQUEST_INTERRUPT), &dev->regs->irqstat1), BIT 2087 drivers/usb/gadget/udc/net2280.c BIT(PCI_ENABLE) | BIT 2088 drivers/usb/gadget/udc/net2280.c BIT(FIFO_SOFT_RESET) | BIT 2089 drivers/usb/gadget/udc/net2280.c BIT(USB_SOFT_RESET) | BIT 2090 drivers/usb/gadget/udc/net2280.c BIT(M8051_RESET); BIT 2122 drivers/usb/gadget/udc/net2280.c writel(BIT(DMA_ABORT), &dma->dmastat); BIT 2132 drivers/usb/gadget/udc/net2280.c BIT(PCI_ENABLE) | BIT 2133 drivers/usb/gadget/udc/net2280.c BIT(FIFO_SOFT_RESET) | BIT 2134 drivers/usb/gadget/udc/net2280.c BIT(USB_SOFT_RESET) | BIT 2135 drivers/usb/gadget/udc/net2280.c BIT(M8051_RESET); BIT 2242 drivers/usb/gadget/udc/net2280.c ~(BIT(U1_ENABLE) | BIT(U2_ENABLE) | BIT(LTM_ENABLE)); BIT 2291 drivers/usb/gadget/udc/net2280.c val |= BIT(RECOVERY_IDLE_TO_RECOVER_FMW); BIT 2314 drivers/usb/gadget/udc/net2280.c writel(BIT(CLEAR_EP_HIDE_STATUS_PHASE) | BIT 2315 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_NAK_OUT_PACKETS) | BIT 2316 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), BIT 2325 drivers/usb/gadget/udc/net2280.c writel(BIT(SET_TEST_MODE) | BIT 2326 drivers/usb/gadget/udc/net2280.c BIT(SET_ADDRESS) | BIT 2327 drivers/usb/gadget/udc/net2280.c BIT(DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP) | BIT 2328 drivers/usb/gadget/udc/net2280.c BIT(GET_DEVICE_STATUS) | BIT 2329 drivers/usb/gadget/udc/net2280.c BIT(GET_INTERFACE_STATUS), BIT 2331 drivers/usb/gadget/udc/net2280.c writel(BIT(USB_ROOT_PORT_WAKEUP_ENABLE) | BIT 2332 drivers/usb/gadget/udc/net2280.c BIT(SELF_POWERED_USB_DEVICE) | BIT 2333 drivers/usb/gadget/udc/net2280.c BIT(REMOTE_WAKEUP_SUPPORT) | BIT 2335 drivers/usb/gadget/udc/net2280.c BIT(SELF_POWERED_STATUS), BIT 2339 drivers/usb/gadget/udc/net2280.c writel(BIT(SETUP_PACKET_INTERRUPT_ENABLE) | BIT 2340 drivers/usb/gadget/udc/net2280.c BIT(ENDPOINT_0_INTERRUPT_ENABLE), BIT 2342 drivers/usb/gadget/udc/net2280.c writel(BIT(PCI_INTERRUPT_ENABLE) | BIT 2343 drivers/usb/gadget/udc/net2280.c BIT(PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE) | BIT 2344 drivers/usb/gadget/udc/net2280.c BIT(PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE) | BIT 2345 drivers/usb/gadget/udc/net2280.c BIT(PCI_RETRY_ABORT_INTERRUPT_ENABLE) | BIT 2346 drivers/usb/gadget/udc/net2280.c BIT(VBUS_INTERRUPT_ENABLE) | BIT 2347 drivers/usb/gadget/udc/net2280.c BIT(ROOT_PORT_RESET_INTERRUPT_ENABLE) | BIT 2348 drivers/usb/gadget/udc/net2280.c BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE), BIT 2359 drivers/usb/gadget/udc/net2280.c writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE) | BIT 2360 drivers/usb/gadget/udc/net2280.c BIT(SET_EP_HIDE_STATUS_PHASE), BIT 2369 drivers/usb/gadget/udc/net2280.c writel(BIT(SET_ISOCHRONOUS_DELAY) | BIT 2370 drivers/usb/gadget/udc/net2280.c BIT(SET_SEL) | BIT 2371 drivers/usb/gadget/udc/net2280.c BIT(SET_TEST_MODE) | BIT 2372 drivers/usb/gadget/udc/net2280.c BIT(SET_ADDRESS) | BIT 2373 drivers/usb/gadget/udc/net2280.c BIT(GET_INTERFACE_STATUS) | BIT 2374 drivers/usb/gadget/udc/net2280.c BIT(GET_DEVICE_STATUS), BIT 2377 drivers/usb/gadget/udc/net2280.c writel(BIT(USB_ROOT_PORT_WAKEUP_ENABLE) | BIT 2379 drivers/usb/gadget/udc/net2280.c BIT(DEVICE_REMOTE_WAKEUP_ENABLE), BIT 2383 drivers/usb/gadget/udc/net2280.c writel(BIT(SETUP_PACKET_INTERRUPT_ENABLE) | BIT 2384 drivers/usb/gadget/udc/net2280.c BIT(ENDPOINT_0_INTERRUPT_ENABLE), BIT 2386 drivers/usb/gadget/udc/net2280.c writel(BIT(PCI_INTERRUPT_ENABLE) | BIT 2387 drivers/usb/gadget/udc/net2280.c BIT(ROOT_PORT_RESET_INTERRUPT_ENABLE) | BIT 2388 drivers/usb/gadget/udc/net2280.c BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE) | BIT 2389 drivers/usb/gadget/udc/net2280.c BIT(VBUS_INTERRUPT_ENABLE), BIT 2533 drivers/usb/gadget/udc/net2280.c writel(t & ~BIT(NAK_OUT_PACKETS), &ep->regs->ep_stat); BIT 2551 drivers/usb/gadget/udc/net2280.c if (t & BIT(DATA_OUT_PING_TOKEN_INTERRUPT)) { BIT 2560 drivers/usb/gadget/udc/net2280.c } else if (t & BIT(DATA_IN_TOKEN_INTERRUPT)) { BIT 2571 drivers/usb/gadget/udc/net2280.c if (t & BIT(DATA_IN_TOKEN_INTERRUPT)) { BIT 2578 drivers/usb/gadget/udc/net2280.c } else if (((t & BIT(DATA_OUT_PING_TOKEN_INTERRUPT)) && BIT 2597 drivers/usb/gadget/udc/net2280.c if (t & BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT)) { BIT 2626 drivers/usb/gadget/udc/net2280.c if (likely(t & BIT(FIFO_EMPTY))) { BIT 2663 drivers/usb/gadget/udc/net2280.c writel(BIT(DMA_ABORT), &ep->dma->dmastat); BIT 2693 drivers/usb/gadget/udc/net2280.c } else if (t & BIT(DATA_PACKET_RECEIVED_INTERRUPT)) { BIT 2698 drivers/usb/gadget/udc/net2280.c } else if (t & BIT(DATA_PACKET_TRANSMITTED_INTERRUPT)) { BIT 2747 drivers/usb/gadget/udc/net2280.c if (t & BIT(DATA_PACKET_TRANSMITTED_INTERRUPT)) BIT 2787 drivers/usb/gadget/udc/net2280.c if (!(readl(&dev->usb->usbstat) & BIT(SUPER_SPEED_MODE))) { BIT 2855 drivers/usb/gadget/udc/net2280.c val |= BIT(SEQUENCE_NUMBER_RESET); BIT 2883 drivers/usb/gadget/udc/net2280.c status |= BIT(0); BIT 2897 drivers/usb/gadget/udc/net2280.c BIT(CLEAR_ENDPOINT_HALT); BIT 2917 drivers/usb/gadget/udc/net2280.c ~BIT(U1_ENABLE), BIT 2925 drivers/usb/gadget/udc/net2280.c ~BIT(U2_ENABLE), BIT 2933 drivers/usb/gadget/udc/net2280.c ~BIT(LTM_ENABLE), BIT 2945 drivers/usb/gadget/udc/net2280.c ~BIT(DEVICE_REMOTE_WAKEUP_ENABLE), BIT 2983 drivers/usb/gadget/udc/net2280.c BIT(U1_ENABLE), BIT 2991 drivers/usb/gadget/udc/net2280.c BIT(U2_ENABLE), BIT 2999 drivers/usb/gadget/udc/net2280.c BIT(LTM_ENABLE), BIT 3011 drivers/usb/gadget/udc/net2280.c BIT(DEVICE_REMOTE_WAKEUP_ENABLE), BIT 3075 drivers/usb/gadget/udc/net2280.c bit = BIT(ep_bit[index]); BIT 3095 drivers/usb/gadget/udc/net2280.c stat &= ~BIT(INTA_ASSERTED); BIT 3101 drivers/usb/gadget/udc/net2280.c if (unlikely(stat & BIT(SETUP_PACKET_INTERRUPT))) { BIT 3111 drivers/usb/gadget/udc/net2280.c if (val & BIT(SUPER_SPEED)) { BIT 3115 drivers/usb/gadget/udc/net2280.c } else if (val & BIT(HIGH_SPEED)) { BIT 3133 drivers/usb/gadget/udc/net2280.c stat &= ~BIT(ENDPOINT_0_INTERRUPT); BIT 3144 drivers/usb/gadget/udc/net2280.c tmp = BIT(FIFO_OVERFLOW) | BIT 3145 drivers/usb/gadget/udc/net2280.c BIT(FIFO_UNDERFLOW); BIT 3149 drivers/usb/gadget/udc/net2280.c writel(tmp | BIT(TIMEOUT) | BIT 3150 drivers/usb/gadget/udc/net2280.c BIT(USB_STALL_SENT) | BIT 3151 drivers/usb/gadget/udc/net2280.c BIT(USB_IN_NAK_SENT) | BIT 3152 drivers/usb/gadget/udc/net2280.c BIT(USB_IN_ACK_RCVD) | BIT 3153 drivers/usb/gadget/udc/net2280.c BIT(USB_OUT_PING_NAK_SENT) | BIT 3154 drivers/usb/gadget/udc/net2280.c BIT(USB_OUT_ACK_SENT) | BIT 3155 drivers/usb/gadget/udc/net2280.c BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) | BIT 3156 drivers/usb/gadget/udc/net2280.c BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) | BIT 3157 drivers/usb/gadget/udc/net2280.c BIT(DATA_PACKET_RECEIVED_INTERRUPT) | BIT 3158 drivers/usb/gadget/udc/net2280.c BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | BIT 3159 drivers/usb/gadget/udc/net2280.c BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | BIT 3160 drivers/usb/gadget/udc/net2280.c BIT(DATA_IN_TOKEN_INTERRUPT), BIT 3179 drivers/usb/gadget/udc/net2280.c writel(BIT(SETUP_PACKET_INTERRUPT), &dev->regs->irqstat0); BIT 3180 drivers/usb/gadget/udc/net2280.c stat ^= BIT(SETUP_PACKET_INTERRUPT); BIT 3189 drivers/usb/gadget/udc/net2280.c scratch = BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | BIT 3190 drivers/usb/gadget/udc/net2280.c BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | BIT 3191 drivers/usb/gadget/udc/net2280.c BIT(DATA_IN_TOKEN_INTERRUPT); BIT 3194 drivers/usb/gadget/udc/net2280.c scratch = BIT(DATA_PACKET_RECEIVED_INTERRUPT) | BIT 3195 drivers/usb/gadget/udc/net2280.c BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | BIT 3196 drivers/usb/gadget/udc/net2280.c BIT(DATA_IN_TOKEN_INTERRUPT); BIT 3221 drivers/usb/gadget/udc/net2280.c if (readl(&e->regs->ep_rsp) & BIT(SET_ENDPOINT_HALT)) BIT 3314 drivers/usb/gadget/udc/net2280.c u32 mask = (BIT(ENDPOINT_0_INTERRUPT) | BIT 3330 drivers/usb/gadget/udc/net2280.c t = BIT(num); BIT 3344 drivers/usb/gadget/udc/net2280.c #define DMA_INTERRUPTS (BIT(DMA_D_INTERRUPT) | \ BIT 3345 drivers/usb/gadget/udc/net2280.c BIT(DMA_C_INTERRUPT) | \ BIT 3346 drivers/usb/gadget/udc/net2280.c BIT(DMA_B_INTERRUPT) | \ BIT 3347 drivers/usb/gadget/udc/net2280.c BIT(DMA_A_INTERRUPT)) BIT 3349 drivers/usb/gadget/udc/net2280.c BIT(PCI_MASTER_ABORT_RECEIVED_INTERRUPT) | \ BIT 3350 drivers/usb/gadget/udc/net2280.c BIT(PCI_TARGET_ABORT_RECEIVED_INTERRUPT) | \ BIT 3351 drivers/usb/gadget/udc/net2280.c BIT(PCI_RETRY_ABORT_INTERRUPT)) BIT 3361 drivers/usb/gadget/udc/net2280.c tmp = BIT(VBUS_INTERRUPT) | BIT(ROOT_PORT_RESET_INTERRUPT); BIT 3362 drivers/usb/gadget/udc/net2280.c mask = BIT(SUPER_SPEED) | BIT(HIGH_SPEED) | BIT(FULL_SPEED); BIT 3379 drivers/usb/gadget/udc/net2280.c if ((stat & BIT(VBUS_INTERRUPT)) && BIT 3381 drivers/usb/gadget/udc/net2280.c BIT(VBUS_PIN)) == 0) { BIT 3385 drivers/usb/gadget/udc/net2280.c } else if ((stat & BIT(ROOT_PORT_RESET_INTERRUPT)) && BIT 3419 drivers/usb/gadget/udc/net2280.c tmp = BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT); BIT 3423 drivers/usb/gadget/udc/net2280.c if (stat & BIT(SUSPEND_REQUEST_INTERRUPT)) { BIT 3427 drivers/usb/gadget/udc/net2280.c stat &= ~BIT(SUSPEND_REQUEST_INTERRUPT); BIT 3443 drivers/usb/gadget/udc/net2280.c stat &= ~(BIT(CONTROL_STATUS_INTERRUPT) | BIT 3444 drivers/usb/gadget/udc/net2280.c BIT(SUSPEND_REQUEST_INTERRUPT) | BIT 3445 drivers/usb/gadget/udc/net2280.c BIT(RESUME_INTERRUPT) | BIT 3446 drivers/usb/gadget/udc/net2280.c BIT(SOF_INTERRUPT)); BIT 3448 drivers/usb/gadget/udc/net2280.c stat &= ~(BIT(CONTROL_STATUS_INTERRUPT) | BIT 3449 drivers/usb/gadget/udc/net2280.c BIT(RESUME_INTERRUPT) | BIT 3450 drivers/usb/gadget/udc/net2280.c BIT(SOF_DOWN_INTERRUPT) | BIT 3451 drivers/usb/gadget/udc/net2280.c BIT(SOF_INTERRUPT)); BIT 3464 drivers/usb/gadget/udc/net2280.c tmp = BIT(num); BIT 3483 drivers/usb/gadget/udc/net2280.c (tmp & BIT(DMA_TRANSACTION_DONE_INTERRUPT))) BIT 3487 drivers/usb/gadget/udc/net2280.c if (!(tmp & BIT(DMA_TRANSACTION_DONE_INTERRUPT))) { BIT 3538 drivers/usb/gadget/udc/net2280.c (!(readl(&dev->regs->irqstat0) & BIT(INTA_ASSERTED)))) BIT 3685 drivers/usb/gadget/udc/net2280.c dev->enhanced_mode = !!(usbstat & BIT(11)); BIT 3753 drivers/usb/gadget/udc/net2280.c writel(BIT(DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE) | BIT 3758 drivers/usb/gadget/udc/net2280.c BIT(DMA_READ_MULTIPLE_ENABLE) | BIT 3759 drivers/usb/gadget/udc/net2280.c BIT(DMA_READ_LINE_ENABLE), BIT 43 drivers/usb/gadget/udc/net2280.h #define PLX_LEGACY BIT(0) BIT 44 drivers/usb/gadget/udc/net2280.h #define PLX_2280 BIT(1) BIT 45 drivers/usb/gadget/udc/net2280.h #define PLX_SUPERSPEED BIT(2) BIT 46 drivers/usb/gadget/udc/net2280.h #define PLX_PCIE BIT(3) BIT 117 drivers/usb/gadget/udc/net2280.h writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) | BIT 118 drivers/usb/gadget/udc/net2280.h BIT(CLEAR_NAK_OUT_PACKETS) | BIT 119 drivers/usb/gadget/udc/net2280.h BIT(CLEAR_NAK_OUT_PACKETS_MODE), BIT 131 drivers/usb/gadget/udc/net2280.h writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp); BIT 190 drivers/usb/gadget/udc/net2280.h writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) | BIT 193 drivers/usb/gadget/udc/net2280.h BIT(SET_ENDPOINT_HALT), BIT 200 drivers/usb/gadget/udc/net2280.h writel(BIT(CLEAR_ENDPOINT_HALT) | BIT 201 drivers/usb/gadget/udc/net2280.h BIT(CLEAR_ENDPOINT_TOGGLE) | BIT 225 drivers/usb/gadget/udc/net2280.h #define DEFECT7374_FSM_WAITING_FOR_CONTROL_READ BIT(DEFECT7374_FSM_FIELD) BIT 252 drivers/usb/gadget/udc/net2280.h writel(BIT(GPIO3_LED_SELECT) | BIT 253 drivers/usb/gadget/udc/net2280.h BIT(GPIO3_OUTPUT_ENABLE) | BIT 254 drivers/usb/gadget/udc/net2280.h BIT(GPIO2_OUTPUT_ENABLE) | BIT 255 drivers/usb/gadget/udc/net2280.h BIT(GPIO1_OUTPUT_ENABLE) | BIT 256 drivers/usb/gadget/udc/net2280.h BIT(GPIO0_OUTPUT_ENABLE), BIT 267 drivers/usb/gadget/udc/net2280.h val |= BIT(GPIO0_DATA) | BIT(GPIO1_DATA); BIT 270 drivers/usb/gadget/udc/net2280.h val &= ~BIT(GPIO0_DATA); BIT 271 drivers/usb/gadget/udc/net2280.h val |= BIT(GPIO1_DATA); BIT 274 drivers/usb/gadget/udc/net2280.h val &= ~BIT(GPIO1_DATA); BIT 275 drivers/usb/gadget/udc/net2280.h val |= BIT(GPIO0_DATA); BIT 278 drivers/usb/gadget/udc/net2280.h val &= ~(BIT(GPIO1_DATA) | BIT(GPIO0_DATA)); BIT 345 drivers/usb/gadget/udc/net2280.h writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); BIT 355 drivers/usb/gadget/udc/net2280.h if ((tmp & BIT(NAK_OUT_PACKETS)) != 0) BIT 356 drivers/usb/gadget/udc/net2280.h writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp); BIT 72 drivers/usb/gadget/udc/renesas_usb3.c #define AXI_INT_DMAINT BIT(31) BIT 73 drivers/usb/gadget/udc/renesas_usb3.c #define AXI_INT_EPCINT BIT(30) BIT 81 drivers/usb/gadget/udc/renesas_usb3.c #define DMA_INT(n) BIT(n) BIT 84 drivers/usb/gadget/udc/renesas_usb3.c #define DMA_CON_PIPE_DIR BIT(15) /* 1: In Transfer */ BIT 89 drivers/usb/gadget/udc/renesas_usb3.c #define DMA_CON_PRD_EN BIT(0) BIT 92 drivers/usb/gadget/udc/renesas_usb3.c #define LCLKSEL_LSEL BIT(18) BIT 95 drivers/usb/gadget/udc/renesas_usb3.c #define USB_COM_CON_CONF BIT(24) BIT 96 drivers/usb/gadget/udc/renesas_usb3.c #define USB_COM_CON_PN_WDATAIF_NL BIT(23) BIT 97 drivers/usb/gadget/udc/renesas_usb3.c #define USB_COM_CON_PN_RDATAIF_NL BIT(22) BIT 98 drivers/usb/gadget/udc/renesas_usb3.c #define USB_COM_CON_PN_LSTTR_PP BIT(21) BIT 99 drivers/usb/gadget/udc/renesas_usb3.c #define USB_COM_CON_SPD_MODE BIT(17) BIT 100 drivers/usb/gadget/udc/renesas_usb3.c #define USB_COM_CON_EP0_EN BIT(16) BIT 105 drivers/usb/gadget/udc/renesas_usb3.c #define USB_COM_CON_RX_DETECTION BIT(1) BIT 106 drivers/usb/gadget/udc/renesas_usb3.c #define USB_COM_CON_PIPE_CLR BIT(0) BIT 109 drivers/usb/gadget/udc/renesas_usb3.c #define USB20_CON_B2_PUE BIT(31) BIT 110 drivers/usb/gadget/udc/renesas_usb3.c #define USB20_CON_B2_SUSPEND BIT(24) BIT 111 drivers/usb/gadget/udc/renesas_usb3.c #define USB20_CON_B2_CONNECT BIT(17) BIT 116 drivers/usb/gadget/udc/renesas_usb3.c #define USB20_CON_B2_TSTMOD_EN BIT(0) BIT 121 drivers/usb/gadget/udc/renesas_usb3.c #define USB30_CON_POW_SEL_IN_U3 BIT(26) BIT 123 drivers/usb/gadget/udc/renesas_usb3.c #define USB30_CON_POW_SEL_P2_TO_P0 BIT(25) BIT 124 drivers/usb/gadget/udc/renesas_usb3.c #define USB30_CON_POW_SEL_P0_TO_P3 BIT(24) BIT 126 drivers/usb/gadget/udc/renesas_usb3.c #define USB30_CON_B3_PLLWAKE BIT(23) BIT 127 drivers/usb/gadget/udc/renesas_usb3.c #define USB30_CON_B3_CONNECT BIT(17) BIT 128 drivers/usb/gadget/udc/renesas_usb3.c #define USB30_CON_B3_HOTRST_CMP BIT(1) BIT 131 drivers/usb/gadget/udc/renesas_usb3.c #define USB_STA_SPEED_MASK (BIT(2) | BIT(1)) BIT 132 drivers/usb/gadget/udc/renesas_usb3.c #define USB_STA_SPEED_HS BIT(2) BIT 133 drivers/usb/gadget/udc/renesas_usb3.c #define USB_STA_SPEED_FS BIT(1) BIT 135 drivers/usb/gadget/udc/renesas_usb3.c #define USB_STA_VBUS_STA BIT(0) BIT 138 drivers/usb/gadget/udc/renesas_usb3.c #define DRD_CON_PERI_CON BIT(24) BIT 139 drivers/usb/gadget/udc/renesas_usb3.c #define DRD_CON_VBOUT BIT(0) BIT 142 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_B3_PLLWKUP BIT(31) BIT 143 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_B3_LUPSUCS BIT(30) BIT 144 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_B3_DISABLE BIT(27) BIT 145 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_B3_WRMRST BIT(21) BIT 146 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_B3_HOTRST BIT(20) BIT 147 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_B2_USBRST BIT(12) BIT 148 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_B2_L1SPND BIT(11) BIT 149 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_B2_SPND BIT(9) BIT 150 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_B2_RSUM BIT(8) BIT 151 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_SPEED BIT(1) BIT 152 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_1_VBUS_CNG BIT(0) BIT 155 drivers/usb/gadget/udc/renesas_usb3.c #define USB_INT_2_PIPE(n) BIT(n) BIT 158 drivers/usb/gadget/udc/renesas_usb3.c #define USB_OTG_IDMON BIT(4) BIT 161 drivers/usb/gadget/udc/renesas_usb3.c #define P0_MOD_DIR BIT(6) BIT 164 drivers/usb/gadget/udc/renesas_usb3.c #define PX_CON_BYTE_EN_MASK (BIT(10) | BIT(9)) BIT 168 drivers/usb/gadget/udc/renesas_usb3.c #define PX_CON_SEND BIT(8) BIT 171 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_ST_RES_MASK (BIT(27) | BIT(26)) BIT 172 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_ST_RES_FORCE_STALL BIT(27) BIT 173 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_ST_RES_NORMAL BIT(26) BIT 175 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_OT_RES_MASK (BIT(25) | BIT(24)) BIT 176 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_OT_RES_FORCE_STALL BIT(25) BIT 177 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_OT_RES_NORMAL BIT(24) BIT 179 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_IN_RES_MASK (BIT(17) | BIT(16)) BIT 180 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_IN_RES_FORCE_STALL BIT(17) BIT 181 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_IN_RES_NORMAL BIT(16) BIT 183 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_RES_WEN BIT(7) BIT 184 drivers/usb/gadget/udc/renesas_usb3.c #define P0_CON_BCLR BIT(1) BIT 187 drivers/usb/gadget/udc/renesas_usb3.c #define PX_STA_BUFSTS BIT(0) BIT 190 drivers/usb/gadget/udc/renesas_usb3.c #define P0_INT_STSED BIT(18) BIT 191 drivers/usb/gadget/udc/renesas_usb3.c #define P0_INT_STSST BIT(17) BIT 192 drivers/usb/gadget/udc/renesas_usb3.c #define P0_INT_SETUP BIT(16) BIT 193 drivers/usb/gadget/udc/renesas_usb3.c #define P0_INT_RCVNL BIT(8) BIT 194 drivers/usb/gadget/udc/renesas_usb3.c #define P0_INT_ERDY BIT(7) BIT 195 drivers/usb/gadget/udc/renesas_usb3.c #define P0_INT_FLOW BIT(6) BIT 196 drivers/usb/gadget/udc/renesas_usb3.c #define P0_INT_STALL BIT(2) BIT 197 drivers/usb/gadget/udc/renesas_usb3.c #define P0_INT_NRDY BIT(1) BIT 198 drivers/usb/gadget/udc/renesas_usb3.c #define P0_INT_BFRDY BIT(0) BIT 202 drivers/usb/gadget/udc/renesas_usb3.c #define PN_MOD_DIR BIT(6) BIT 213 drivers/usb/gadget/udc/renesas_usb3.c #define PN_RAMMAP_RAMAREA_16KB BIT(31) BIT 214 drivers/usb/gadget/udc/renesas_usb3.c #define PN_RAMMAP_RAMAREA_8KB (BIT(30) | BIT(29)) BIT 215 drivers/usb/gadget/udc/renesas_usb3.c #define PN_RAMMAP_RAMAREA_4KB BIT(30) BIT 216 drivers/usb/gadget/udc/renesas_usb3.c #define PN_RAMMAP_RAMAREA_2KB BIT(29) BIT 233 drivers/usb/gadget/udc/renesas_usb3.c #define PN_CON_EN BIT(31) BIT 234 drivers/usb/gadget/udc/renesas_usb3.c #define PN_CON_DATAIF_EN BIT(30) BIT 235 drivers/usb/gadget/udc/renesas_usb3.c #define PN_CON_RES_MASK (BIT(17) | BIT(16)) BIT 236 drivers/usb/gadget/udc/renesas_usb3.c #define PN_CON_RES_FORCE_STALL BIT(17) BIT 237 drivers/usb/gadget/udc/renesas_usb3.c #define PN_CON_RES_NORMAL BIT(16) BIT 239 drivers/usb/gadget/udc/renesas_usb3.c #define PN_CON_LAST BIT(11) BIT 240 drivers/usb/gadget/udc/renesas_usb3.c #define PN_CON_RES_WEN BIT(7) BIT 241 drivers/usb/gadget/udc/renesas_usb3.c #define PN_CON_CLR BIT(0) BIT 244 drivers/usb/gadget/udc/renesas_usb3.c #define PN_INT_LSTTR BIT(4) BIT 245 drivers/usb/gadget/udc/renesas_usb3.c #define PN_INT_BFRDY BIT(0) BIT 248 drivers/usb/gadget/udc/renesas_usb3.c #define SSIFCMD_URES_U2 BIT(9) BIT 249 drivers/usb/gadget/udc/renesas_usb3.c #define SSIFCMD_URES_U1 BIT(8) BIT 250 drivers/usb/gadget/udc/renesas_usb3.c #define SSIFCMD_UDIR_U2 BIT(7) BIT 251 drivers/usb/gadget/udc/renesas_usb3.c #define SSIFCMD_UDIR_U1 BIT(6) BIT 252 drivers/usb/gadget/udc/renesas_usb3.c #define SSIFCMD_UREQ_U2 BIT(5) BIT 253 drivers/usb/gadget/udc/renesas_usb3.c #define SSIFCMD_UREQ_U1 BIT(4) BIT 274 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_E BIT(30) /* the end of chain */ BIT 275 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_U BIT(29) /* completion of transfer */ BIT 276 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_D BIT(28) /* Error occurred */ BIT 277 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_INT BIT(27) /* Interrupt occurred */ BIT 278 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_LST BIT(26) /* Last Packet */ BIT 279 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_B_INC BIT(24) BIT 281 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_MPS_16 BIT(21) BIT 282 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_MPS_32 BIT(22) BIT 283 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_MPS_64 (BIT(22) | BIT(21)) BIT 284 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_MPS_512 BIT(23) BIT 285 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_MPS_1024 (BIT(23) | BIT(21)) BIT 286 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_MPS_RESERVED (BIT(23) | BIT(22) | BIT(21)) BIT 743 drivers/usb/host/ehci-hcd.c ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG); BIT 341 drivers/usb/host/ehci-hub.c if (ehci->enabled_hrtimer_events & BIT(EHCI_HRTIMER_POLL_DEAD)) BIT 29 drivers/usb/host/ehci-orion.c #define USB_CMD_RUN BIT(0) BIT 30 drivers/usb/host/ehci-orion.c #define USB_CMD_RESET BIT(1) BIT 35 drivers/usb/host/ehci-orion.c #define USB_MODE_SDIS BIT(4) BIT 959 drivers/usb/host/ehci-q.c ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_DISABLE_ASYNC); BIT 1525 drivers/usb/host/ehci-q.c BIT(EHCI_HRTIMER_ASYNC_UNLINKS))) { BIT 510 drivers/usb/host/ehci-sched.c ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_DISABLE_PERIODIC); BIT 278 drivers/usb/host/ehci-timer.c if (!(ehci->enabled_hrtimer_events & BIT(EHCI_HRTIMER_FREE_ITDS))) { BIT 365 drivers/usb/host/ehci-timer.c BIT(EHCI_HRTIMER_IO_WATCHDOG))) BIT 1230 drivers/usb/host/fotg210-hcd.c BIT(FOTG210_HRTIMER_FREE_ITDS))) { BIT 1308 drivers/usb/host/fotg210-hcd.c BIT(FOTG210_HRTIMER_IO_WATCHDOG))) BIT 2891 drivers/usb/host/fotg210-hcd.c fotg210->enabled_hrtimer_events &= ~BIT(FOTG210_HRTIMER_DISABLE_ASYNC); BIT 3258 drivers/usb/host/fotg210-hcd.c BIT(FOTG210_HRTIMER_ASYNC_UNLINKS))) { BIT 3462 drivers/usb/host/fotg210-hcd.c ~BIT(FOTG210_HRTIMER_DISABLE_PERIODIC); BIT 5173 drivers/usb/host/fotg210-hcd.c ~BIT(FOTG210_HRTIMER_IAA_WATCHDOG); BIT 474 drivers/usb/host/max3421-hcd.c mode_lowspeed = BIT(MAX3421_MODE_LOWSPEED_BIT); BIT 475 drivers/usb/host/max3421-hcd.c mode_hubpre = BIT(MAX3421_MODE_HUBPRE_BIT); BIT 524 drivers/usb/host/max3421-hcd.c hctl = (BIT(rcvtog + MAX3421_HCTL_RCVTOG0_BIT) | BIT 525 drivers/usb/host/max3421-hcd.c BIT(sndtog + MAX3421_HCTL_SNDTOG0_BIT)); BIT 553 drivers/usb/host/max3421-hcd.c max3421_hcd->hien |= BIT(MAX3421_HI_RCVDAV_BIT); BIT 646 drivers/usb/host/max3421-hcd.c max3421_hcd->hien |= BIT(MAX3421_HI_HXFRDN_BIT); BIT 876 drivers/usb/host/max3421-hcd.c spi_wr8(hcd, MAX3421_REG_HIRQ, BIT(MAX3421_HI_RCVDAV_BIT)); BIT 926 drivers/usb/host/max3421-hcd.c BIT(sndtog + MAX3421_HCTL_SNDTOG0_BIT)); BIT 1051 drivers/usb/host/max3421-hcd.c max3421_hcd->hien &= ~(BIT(MAX3421_HI_HXFRDN_BIT) | BIT 1052 drivers/usb/host/max3421-hcd.c BIT(MAX3421_HI_RCVDAV_BIT)); BIT 1130 drivers/usb/host/max3421-hcd.c mode &= ~BIT(MAX3421_MODE_SOFKAENAB_BIT); BIT 1137 drivers/usb/host/max3421-hcd.c mode ^= BIT(MAX3421_MODE_LOWSPEED_BIT); BIT 1139 drivers/usb/host/max3421-hcd.c mode |= BIT(MAX3421_MODE_SOFKAENAB_BIT); BIT 1156 drivers/usb/host/max3421-hcd.c if (mode & BIT(MAX3421_MODE_LOWSPEED_BIT)) BIT 1242 drivers/usb/host/max3421-hcd.c hirq & ~(BIT(MAX3421_HI_SNDBAV_BIT) | BIT 1243 drivers/usb/host/max3421-hcd.c BIT(MAX3421_HI_RCVDAV_BIT))); BIT 1245 drivers/usb/host/max3421-hcd.c if (hirq & BIT(MAX3421_HI_FRAME_BIT)) { BIT 1251 drivers/usb/host/max3421-hcd.c if (hirq & BIT(MAX3421_HI_RCVDAV_BIT)) BIT 1254 drivers/usb/host/max3421-hcd.c if (hirq & BIT(MAX3421_HI_HXFRDN_BIT)) BIT 1257 drivers/usb/host/max3421-hcd.c if (hirq & BIT(MAX3421_HI_CONDET_BIT)) BIT 1267 drivers/usb/host/max3421-hcd.c if (hirq & BIT(MAX3421_HI_BUSEVENT_BIT)) { BIT 1277 drivers/usb/host/max3421-hcd.c if (hirq & BIT(MAX3421_HI_RWU_BIT)) BIT 1279 drivers/usb/host/max3421-hcd.c if (hirq & BIT(MAX3421_HI_SUSDN_BIT)) BIT 1324 drivers/usb/host/max3421-hcd.c spi_wr8(hcd, MAX3421_REG_USBCTL, BIT(MAX3421_USBCTL_CHIPRES_BIT)); BIT 1330 drivers/usb/host/max3421-hcd.c & BIT(MAX3421_USBIRQ_OSCOKIRQ_BIT)) BIT 1344 drivers/usb/host/max3421-hcd.c max3421_hcd->mode = (BIT(MAX3421_MODE_HOST_BIT) | BIT 1345 drivers/usb/host/max3421-hcd.c BIT(MAX3421_MODE_SOFKAENAB_BIT) | BIT 1346 drivers/usb/host/max3421-hcd.c BIT(MAX3421_MODE_DMPULLDN_BIT) | BIT 1347 drivers/usb/host/max3421-hcd.c BIT(MAX3421_MODE_DPPULLDN_BIT)); BIT 1352 drivers/usb/host/max3421-hcd.c spi_wr8(hcd, MAX3421_REG_HCTL, BIT(MAX3421_HCTL_FRMRST_BIT)); BIT 1355 drivers/usb/host/max3421-hcd.c spi_wr8(hcd, MAX3421_REG_HCTL, BIT(MAX3421_HCTL_SAMPLEBUS_BIT)); BIT 1359 drivers/usb/host/max3421-hcd.c max3421_hcd->hien = (BIT(MAX3421_HI_FRAME_BIT) | BIT 1360 drivers/usb/host/max3421-hcd.c BIT(MAX3421_HI_CONDET_BIT) | BIT 1361 drivers/usb/host/max3421-hcd.c BIT(MAX3421_HI_BUSEVENT_BIT)); BIT 1365 drivers/usb/host/max3421-hcd.c spi_wr8(hcd, MAX3421_REG_CPUCTL, BIT(MAX3421_CPUCTL_IE_BIT)); BIT 1404 drivers/usb/host/max3421-hcd.c (BIT(MAX3421_PINCTL_FDUPSPI_BIT) | /* full-duplex */ BIT 1405 drivers/usb/host/max3421-hcd.c BIT(MAX3421_PINCTL_INTLEVEL_BIT))); /* low-active irq */ BIT 1449 drivers/usb/host/max3421-hcd.c BIT(MAX3421_HCTL_BUSRST_BIT)); BIT 629 drivers/usb/host/pci-quirks.c return !(value & BIT(port_shift)); BIT 40 drivers/usb/host/xhci-dbgcap.h #define DBC_CTRL_DBC_RUN BIT(0) BIT 41 drivers/usb/host/xhci-dbgcap.h #define DBC_CTRL_PORT_ENABLE BIT(1) BIT 42 drivers/usb/host/xhci-dbgcap.h #define DBC_CTRL_HALT_OUT_TR BIT(2) BIT 43 drivers/usb/host/xhci-dbgcap.h #define DBC_CTRL_HALT_IN_TR BIT(3) BIT 44 drivers/usb/host/xhci-dbgcap.h #define DBC_CTRL_DBC_RUN_CHANGE BIT(4) BIT 45 drivers/usb/host/xhci-dbgcap.h #define DBC_CTRL_DBC_ENABLE BIT(31) BIT 59 drivers/usb/host/xhci-dbgcap.h #define DBC_PORTSC_CONN_STATUS BIT(0) BIT 60 drivers/usb/host/xhci-dbgcap.h #define DBC_PORTSC_PORT_ENABLED BIT(1) BIT 61 drivers/usb/host/xhci-dbgcap.h #define DBC_PORTSC_CONN_CHANGE BIT(17) BIT 62 drivers/usb/host/xhci-dbgcap.h #define DBC_PORTSC_RESET_CHANGE BIT(21) BIT 63 drivers/usb/host/xhci-dbgcap.h #define DBC_PORTSC_LINK_CHANGE BIT(22) BIT 64 drivers/usb/host/xhci-dbgcap.h #define DBC_PORTSC_CONFIG_CHANGE BIT(23) BIT 24 drivers/usb/host/xhci-histb.c #define BIT_UTMI_8_16 BIT(3) BIT 25 drivers/usb/host/xhci-histb.c #define BIT_UTMI_ULPI BIT(4) BIT 26 drivers/usb/host/xhci-histb.c #define BIT_FREECLK_EXIST BIT(30) BIT 30 drivers/usb/host/xhci-histb.c #define USB3_DEEMPHASIS0 BIT(1) BIT 31 drivers/usb/host/xhci-histb.c #define USB3_TX_MARGIN1 BIT(4) BIT 146 drivers/usb/host/xhci-hub.c psi |= BIT(14); BIT 26 drivers/usb/host/xhci-mtk.c #define CTRL0_IP_SW_RST BIT(0) BIT 29 drivers/usb/host/xhci-mtk.c #define CTRL1_IP_HOST_PDN BIT(0) BIT 32 drivers/usb/host/xhci-mtk.c #define CTRL2_IP_DEV_PDN BIT(0) BIT 35 drivers/usb/host/xhci-mtk.c #define STS1_IP_SLEEP_STS BIT(30) BIT 36 drivers/usb/host/xhci-mtk.c #define STS1_U3_MAC_RST BIT(16) BIT 37 drivers/usb/host/xhci-mtk.c #define STS1_XHCI_RST BIT(11) BIT 38 drivers/usb/host/xhci-mtk.c #define STS1_SYS125_RST BIT(10) BIT 39 drivers/usb/host/xhci-mtk.c #define STS1_REF_RST BIT(8) BIT 40 drivers/usb/host/xhci-mtk.c #define STS1_SYSPLL_STABLE BIT(0) BIT 47 drivers/usb/host/xhci-mtk.c #define CTRL_U3_PORT_HOST_SEL BIT(2) BIT 48 drivers/usb/host/xhci-mtk.c #define CTRL_U3_PORT_PDN BIT(1) BIT 49 drivers/usb/host/xhci-mtk.c #define CTRL_U3_PORT_DIS BIT(0) BIT 52 drivers/usb/host/xhci-mtk.c #define CTRL_U2_PORT_HOST_SEL BIT(2) BIT 53 drivers/usb/host/xhci-mtk.c #define CTRL_U2_PORT_PDN BIT(1) BIT 54 drivers/usb/host/xhci-mtk.c #define CTRL_U2_PORT_DIS BIT(0) BIT 57 drivers/usb/host/xhci-mtk.c #define CTRL_U2_FORCE_PLL_STB BIT(28) BIT 63 drivers/usb/host/xhci-mtk.c #define WC1_IS_EN BIT(25) BIT 64 drivers/usb/host/xhci-mtk.c #define WC1_IS_P BIT(6) /* polarity for ip sleep */ BIT 68 drivers/usb/host/xhci-mtk.c #define SSC_IP_SLEEP_EN BIT(4) BIT 69 drivers/usb/host/xhci-mtk.c #define SSC_SPM_INT_EN BIT(1) BIT 459 drivers/usb/host/xhci-pci.c writel(val | BIT(28), reg); BIT 72 drivers/usb/host/xhci-rcar.c #define RCAR_USB3_RX_POL_VAL BIT(21) BIT 73 drivers/usb/host/xhci-rcar.c #define RCAR_USB3_TX_POL_VAL BIT(4) BIT 76 drivers/usb/host/xhci-rcar.c #define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */ BIT 77 drivers/usb/host/xhci-rcar.c #define RCAR_XHCI_FIRMWARE_V3 BIT(1) /* FIRMWARE V3 */ BIT 35 drivers/usb/host/xhci-tegra.c #define XUSB_IO_SPACE_EN BIT(0) BIT 36 drivers/usb/host/xhci-tegra.c #define XUSB_MEM_SPACE_EN BIT(1) BIT 37 drivers/usb/host/xhci-tegra.c #define XUSB_BUS_MASTER_EN BIT(2) BIT 46 drivers/usb/host/xhci-tegra.c #define MBOX_DEST_FALC BIT(27) BIT 47 drivers/usb/host/xhci-tegra.c #define MBOX_DEST_PME BIT(28) BIT 48 drivers/usb/host/xhci-tegra.c #define MBOX_DEST_SMI BIT(29) BIT 49 drivers/usb/host/xhci-tegra.c #define MBOX_DEST_XHCI BIT(30) BIT 50 drivers/usb/host/xhci-tegra.c #define MBOX_INT_EN BIT(31) BIT 62 drivers/usb/host/xhci-tegra.c #define MBOX_SMI_INTR_FW_HANG BIT(1) BIT 63 drivers/usb/host/xhci-tegra.c #define MBOX_SMI_INTR_EN BIT(3) BIT 67 drivers/usb/host/xhci-tegra.c #define IPFS_EN_FPCI BIT(0) BIT 69 drivers/usb/host/xhci-tegra.c #define IPFS_IP_INT_MASK BIT(16) BIT 81 drivers/usb/host/xhci-tegra.c #define CPUCTL_STARTCPU BIT(1) BIT 82 drivers/usb/host/xhci-tegra.c #define CPUCTL_STATE_HALTED BIT(4) BIT 83 drivers/usb/host/xhci-tegra.c #define CPUCTL_STATE_STOPPED BIT(5) BIT 106 drivers/usb/host/xhci-tegra.c #define APMAP_BOOTPATH BIT(31) BIT 2910 drivers/usb/host/xhci.c __le32 le32 = cpu_to_le32(BIT(i)); BIT 5239 drivers/usb/host/xhci.c xhci->hcc_params &= ~BIT(0); BIT 1022 drivers/usb/host/xhci.h #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ BIT 388 drivers/usb/misc/usb251xb.c *fld |= BIT(port); BIT 435 drivers/usb/misc/usb251xb.c hub->conf_data1 |= BIT(7); BIT 438 drivers/usb/misc/usb251xb.c hub->conf_data1 &= ~BIT(2); BIT 440 drivers/usb/misc/usb251xb.c hub->conf_data1 &= ~BIT(1); BIT 442 drivers/usb/misc/usb251xb.c hub->conf_data1 |= BIT(1); BIT 444 drivers/usb/misc/usb251xb.c hub->conf_data1 &= ~BIT(7); BIT 447 drivers/usb/misc/usb251xb.c hub->conf_data1 |= BIT(2); BIT 451 drivers/usb/misc/usb251xb.c hub->conf_data1 |= BIT(5); BIT 454 drivers/usb/misc/usb251xb.c hub->conf_data1 |= BIT(4); BIT 456 drivers/usb/misc/usb251xb.c hub->conf_data1 &= ~BIT(4); BIT 459 drivers/usb/misc/usb251xb.c hub->conf_data1 |= BIT(3); BIT 462 drivers/usb/misc/usb251xb.c hub->conf_data1 |= BIT(0); BIT 464 drivers/usb/misc/usb251xb.c hub->conf_data1 &= ~BIT(0); BIT 468 drivers/usb/misc/usb251xb.c hub->conf_data2 |= BIT(7); BIT 473 drivers/usb/misc/usb251xb.c hub->conf_data2 &= ~BIT(5); BIT 474 drivers/usb/misc/usb251xb.c hub->conf_data2 &= ~BIT(4); BIT 477 drivers/usb/misc/usb251xb.c hub->conf_data2 &= ~BIT(5); BIT 478 drivers/usb/misc/usb251xb.c hub->conf_data2 |= BIT(4); BIT 481 drivers/usb/misc/usb251xb.c hub->conf_data2 |= BIT(5); BIT 482 drivers/usb/misc/usb251xb.c hub->conf_data2 |= BIT(4); BIT 485 drivers/usb/misc/usb251xb.c hub->conf_data2 |= BIT(5); BIT 486 drivers/usb/misc/usb251xb.c hub->conf_data2 &= ~BIT(4); BIT 491 drivers/usb/misc/usb251xb.c hub->conf_data2 |= BIT(3); BIT 495 drivers/usb/misc/usb251xb.c hub->conf_data3 |= BIT(3); BIT 498 drivers/usb/misc/usb251xb.c hub->conf_data3 &= ~BIT(1); BIT 501 drivers/usb/misc/usb251xb.c hub->conf_data3 |= BIT(0); BIT 57 drivers/usb/mtu3/mtu3.h #define MTU3_EP_ENABLED BIT(0) BIT 58 drivers/usb/mtu3/mtu3.h #define MTU3_EP_STALL BIT(1) BIT 59 drivers/usb/mtu3/mtu3.h #define MTU3_EP_WEDGE BIT(2) BIT 60 drivers/usb/mtu3/mtu3.h #define MTU3_EP_BUSY BIT(3) BIT 24 drivers/usb/mtu3/mtu3_host.c #define WC1_IS_EN BIT(25) BIT 25 drivers/usb/mtu3/mtu3_host.c #define WC1_IS_P BIT(6) /* polarity for ip sleep */ BIT 29 drivers/usb/mtu3/mtu3_host.c #define SSC_IP_SLEEP_EN BIT(4) BIT 30 drivers/usb/mtu3/mtu3_host.c #define SSC_SPM_INT_EN BIT(1) BIT 96 drivers/usb/mtu3/mtu3_hw_regs.h #define EP_CTRL_INTR BIT(5) BIT 97 drivers/usb/mtu3/mtu3_hw_regs.h #define MAC2_INTR BIT(4) BIT 98 drivers/usb/mtu3/mtu3_hw_regs.h #define DMA_INTR BIT(3) BIT 99 drivers/usb/mtu3/mtu3_hw_regs.h #define MAC3_INTR BIT(2) BIT 100 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_INTR BIT(1) BIT 101 drivers/usb/mtu3/mtu3_hw_regs.h #define BMU_INTR BIT(0) BIT 107 drivers/usb/mtu3/mtu3_hw_regs.h #define EPRISR(x) (BIT(16) << (x)) BIT 108 drivers/usb/mtu3/mtu3_hw_regs.h #define SETUPENDISR BIT(16) BIT 109 drivers/usb/mtu3/mtu3_hw_regs.h #define EPTISR(x) (BIT(0) << (x)) BIT 110 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0ISR BIT(0) BIT 113 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0_SENDSTALL BIT(25) BIT 114 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0_FIFOFULL BIT(23) BIT 115 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0_SENTSTALL BIT(22) BIT 116 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0_DPHTX BIT(20) BIT 117 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0_DATAEND BIT(19) BIT 118 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0_TXPKTRDY BIT(18) BIT 119 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0_SETUPPKTRDY BIT(17) BIT 120 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0_RXPKTRDY BIT(16) BIT 126 drivers/usb/mtu3/mtu3_hw_regs.h #define TX_DMAREQEN BIT(29) BIT 127 drivers/usb/mtu3/mtu3_hw_regs.h #define TX_FIFOFULL BIT(25) BIT 128 drivers/usb/mtu3/mtu3_hw_regs.h #define TX_FIFOEMPTY BIT(24) BIT 129 drivers/usb/mtu3/mtu3_hw_regs.h #define TX_SENTSTALL BIT(22) BIT 130 drivers/usb/mtu3/mtu3_hw_regs.h #define TX_SENDSTALL BIT(21) BIT 131 drivers/usb/mtu3/mtu3_hw_regs.h #define TX_TXPKTRDY BIT(16) BIT 167 drivers/usb/mtu3/mtu3_hw_regs.h #define RX_DMAREQEN BIT(29) BIT 168 drivers/usb/mtu3/mtu3_hw_regs.h #define RX_SENTSTALL BIT(22) BIT 169 drivers/usb/mtu3/mtu3_hw_regs.h #define RX_SENDSTALL BIT(21) BIT 170 drivers/usb/mtu3/mtu3_hw_regs.h #define RX_RXPKTRDY BIT(16) BIT 200 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_RX_CS_EN(x) (BIT(16) << (x)) BIT 201 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_TX_CS_EN(x) (BIT(0) << (x)) BIT 202 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_CS16B_EN BIT(0) BIT 205 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_TX_ZLP(x) (BIT(0) << (x)) BIT 208 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_RX_COZ(x) (BIT(16) << (x)) BIT 209 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_RX_ZLP(x) (BIT(0) << (x)) BIT 220 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_Q_ACTIVE BIT(15) BIT 221 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_Q_STOP BIT(2) BIT 222 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_Q_RESUME BIT(1) BIT 223 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_Q_START BIT(0) BIT 226 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_RX_DONE_INT(x) (BIT(16) << (x)) BIT 227 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_TX_DONE_INT(x) (BIT(0) << (x)) BIT 230 drivers/usb/mtu3/mtu3_hw_regs.h #define RXQ_ZLPERR_INT BIT(20) BIT 231 drivers/usb/mtu3/mtu3_hw_regs.h #define RXQ_LENERR_INT BIT(18) BIT 232 drivers/usb/mtu3/mtu3_hw_regs.h #define RXQ_CSERR_INT BIT(17) BIT 233 drivers/usb/mtu3/mtu3_hw_regs.h #define RXQ_EMPTY_INT BIT(16) BIT 234 drivers/usb/mtu3/mtu3_hw_regs.h #define TXQ_LENERR_INT BIT(2) BIT 235 drivers/usb/mtu3/mtu3_hw_regs.h #define TXQ_CSERR_INT BIT(1) BIT 236 drivers/usb/mtu3/mtu3_hw_regs.h #define TXQ_EMPTY_INT BIT(0) BIT 239 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_TX_LEN_ERR(x) (BIT(16) << (x)) BIT 240 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_TX_CS_ERR(x) (BIT(0) << (x)) BIT 243 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_RX_LEN_ERR(x) (BIT(16) << (x)) BIT 244 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_RX_CS_ERR(x) (BIT(0) << (x)) BIT 247 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_RX_ZLP_ERR(n) (BIT(16) << (n)) BIT 254 drivers/usb/mtu3/mtu3_hw_regs.h #define DMA_ADDR_36BIT BIT(31) BIT 255 drivers/usb/mtu3/mtu3_hw_regs.h #define VBUS_ON BIT(1) BIT 256 drivers/usb/mtu3/mtu3_hw_regs.h #define VBUS_FRC_EN BIT(0) BIT 272 drivers/usb/mtu3/mtu3_hw_regs.h #define HW_USB2_3_SEL BIT(18) BIT 273 drivers/usb/mtu3/mtu3_hw_regs.h #define SW_USB2_3_SEL_EN BIT(17) BIT 274 drivers/usb/mtu3/mtu3_hw_regs.h #define SW_USB2_3_SEL BIT(16) BIT 278 drivers/usb/mtu3/mtu3_hw_regs.h #define EP1_IN_RST BIT(17) BIT 279 drivers/usb/mtu3/mtu3_hw_regs.h #define EP1_OUT_RST BIT(1) BIT 280 drivers/usb/mtu3/mtu3_hw_regs.h #define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum)) BIT 281 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0_RST BIT(0) BIT 285 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_DEV_SPEED_CHG_INTR BIT(0) BIT 302 drivers/usb/mtu3/mtu3_hw_regs.h #define FORCE_POLLING_FAIL BIT(4) BIT 303 drivers/usb/mtu3/mtu3_hw_regs.h #define FORCE_RXDETECT_FAIL BIT(3) BIT 304 drivers/usb/mtu3/mtu3_hw_regs.h #define SOFT_U3_EXIT_EN BIT(2) BIT 305 drivers/usb/mtu3/mtu3_hw_regs.h #define COMPLIANCE_EN BIT(1) BIT 306 drivers/usb/mtu3/mtu3_hw_regs.h #define U1_GO_U2_EN BIT(0) BIT 309 drivers/usb/mtu3/mtu3_hw_regs.h #define USB3_EN BIT(0) BIT 316 drivers/usb/mtu3/mtu3_hw_regs.h #define U3_RESUME_INTR BIT(18) BIT 317 drivers/usb/mtu3/mtu3_hw_regs.h #define U3_LFPS_TMOUT_INTR BIT(17) BIT 318 drivers/usb/mtu3/mtu3_hw_regs.h #define VBUS_FALL_INTR BIT(16) BIT 319 drivers/usb/mtu3/mtu3_hw_regs.h #define VBUS_RISE_INTR BIT(15) BIT 320 drivers/usb/mtu3/mtu3_hw_regs.h #define RXDET_SUCCESS_INTR BIT(14) BIT 321 drivers/usb/mtu3/mtu3_hw_regs.h #define EXIT_U3_INTR BIT(13) BIT 322 drivers/usb/mtu3/mtu3_hw_regs.h #define EXIT_U2_INTR BIT(12) BIT 323 drivers/usb/mtu3/mtu3_hw_regs.h #define EXIT_U1_INTR BIT(11) BIT 324 drivers/usb/mtu3/mtu3_hw_regs.h #define ENTER_U3_INTR BIT(10) BIT 325 drivers/usb/mtu3/mtu3_hw_regs.h #define ENTER_U2_INTR BIT(9) BIT 326 drivers/usb/mtu3/mtu3_hw_regs.h #define ENTER_U1_INTR BIT(8) BIT 327 drivers/usb/mtu3/mtu3_hw_regs.h #define ENTER_U0_INTR BIT(7) BIT 328 drivers/usb/mtu3/mtu3_hw_regs.h #define RECOVERY_INTR BIT(6) BIT 329 drivers/usb/mtu3/mtu3_hw_regs.h #define WARM_RST_INTR BIT(5) BIT 330 drivers/usb/mtu3/mtu3_hw_regs.h #define HOT_RST_INTR BIT(4) BIT 331 drivers/usb/mtu3/mtu3_hw_regs.h #define LOOPBACK_INTR BIT(3) BIT 332 drivers/usb/mtu3/mtu3_hw_regs.h #define COMPLIANCE_INTR BIT(2) BIT 333 drivers/usb/mtu3/mtu3_hw_regs.h #define SS_DISABLE_INTR BIT(1) BIT 334 drivers/usb/mtu3/mtu3_hw_regs.h #define SS_INACTIVE_INTR BIT(0) BIT 337 drivers/usb/mtu3/mtu3_hw_regs.h #define SOFTCON_CLR_AUTO_EN BIT(0) BIT 355 drivers/usb/mtu3/mtu3_hw_regs.h #define SW_U2_ACCEPT_ENABLE BIT(9) BIT 356 drivers/usb/mtu3/mtu3_hw_regs.h #define SW_U1_ACCEPT_ENABLE BIT(8) BIT 357 drivers/usb/mtu3/mtu3_hw_regs.h #define UX_EXIT BIT(5) BIT 358 drivers/usb/mtu3/mtu3_hw_regs.h #define LGO_U3 BIT(4) BIT 359 drivers/usb/mtu3/mtu3_hw_regs.h #define LGO_U2 BIT(3) BIT 360 drivers/usb/mtu3/mtu3_hw_regs.h #define LGO_U1 BIT(2) BIT 361 drivers/usb/mtu3/mtu3_hw_regs.h #define SW_U2_REQUEST_ENABLE BIT(1) BIT 362 drivers/usb/mtu3/mtu3_hw_regs.h #define SW_U1_REQUEST_ENABLE BIT(0) BIT 365 drivers/usb/mtu3/mtu3_hw_regs.h #define CLR_LINK_ERR_CNT BIT(16) BIT 384 drivers/usb/mtu3/mtu3_hw_regs.h #define LPM_BESL_STALL BIT(14) BIT 385 drivers/usb/mtu3/mtu3_hw_regs.h #define LPM_BESLD_STALL BIT(13) BIT 386 drivers/usb/mtu3/mtu3_hw_regs.h #define LPM_RWP BIT(11) BIT 387 drivers/usb/mtu3/mtu3_hw_regs.h #define LPM_HRWE BIT(10) BIT 389 drivers/usb/mtu3/mtu3_hw_regs.h #define ISO_UPDATE BIT(7) BIT 390 drivers/usb/mtu3/mtu3_hw_regs.h #define SOFT_CONN BIT(6) BIT 391 drivers/usb/mtu3/mtu3_hw_regs.h #define HS_ENABLE BIT(5) BIT 392 drivers/usb/mtu3/mtu3_hw_regs.h #define RESUME BIT(2) BIT 393 drivers/usb/mtu3/mtu3_hw_regs.h #define SUSPENDM_ENABLE BIT(0) BIT 396 drivers/usb/mtu3/mtu3_hw_regs.h #define DC_HOSTREQ BIT(1) BIT 397 drivers/usb/mtu3/mtu3_hw_regs.h #define DC_SESSION BIT(0) BIT 400 drivers/usb/mtu3/mtu3_hw_regs.h #define U2U3_AUTO_SWITCH BIT(10) BIT 401 drivers/usb/mtu3/mtu3_hw_regs.h #define LPM_FORCE_STALL BIT(8) BIT 402 drivers/usb/mtu3/mtu3_hw_regs.h #define FIFO_ACCESS BIT(6) BIT 403 drivers/usb/mtu3/mtu3_hw_regs.h #define FORCE_FS BIT(5) BIT 404 drivers/usb/mtu3/mtu3_hw_regs.h #define FORCE_HS BIT(4) BIT 405 drivers/usb/mtu3/mtu3_hw_regs.h #define TEST_PACKET_MODE BIT(3) BIT 406 drivers/usb/mtu3/mtu3_hw_regs.h #define TEST_K_MODE BIT(2) BIT 407 drivers/usb/mtu3/mtu3_hw_regs.h #define TEST_J_MODE BIT(1) BIT 408 drivers/usb/mtu3/mtu3_hw_regs.h #define TEST_SE0_NAK_MODE BIT(0) BIT 412 drivers/usb/mtu3/mtu3_hw_regs.h #define LPM_RESUME_INTR BIT(9) BIT 413 drivers/usb/mtu3/mtu3_hw_regs.h #define LPM_INTR BIT(8) BIT 414 drivers/usb/mtu3/mtu3_hw_regs.h #define DISCONN_INTR BIT(5) BIT 415 drivers/usb/mtu3/mtu3_hw_regs.h #define CONN_INTR BIT(4) BIT 416 drivers/usb/mtu3/mtu3_hw_regs.h #define SOF_INTR BIT(3) BIT 417 drivers/usb/mtu3/mtu3_hw_regs.h #define RESET_INTR BIT(2) BIT 418 drivers/usb/mtu3/mtu3_hw_regs.h #define RESUME_INTR BIT(1) BIT 419 drivers/usb/mtu3/mtu3_hw_regs.h #define SUSPEND_INTR BIT(0) BIT 431 drivers/usb/mtu3/mtu3_hw_regs.h #define LPM_U3_ACK_EN BIT(0) BIT 464 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_IP_SW_RST BIT(0) BIT 467 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_IP_HOST_PDN BIT(0) BIT 470 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_IP_DEV_PDN BIT(0) BIT 473 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_IP_PCIE_PDN BIT(0) BIT 476 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_IP_SLEEP_STS BIT(30) BIT 477 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U3_MAC_RST_B_STS BIT(16) BIT 478 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_XHCI_RST_B_STS BIT(11) BIT 479 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_SYS125_RST_B_STS BIT(10) BIT 480 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_REF_RST_B_STS BIT(8) BIT 481 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_SYSPLL_STABLE BIT(0) BIT 484 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0) BIT 487 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_VBUS_VALID BIT(9) BIT 490 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_VBUS_INTR_CLR BIT(6) BIT 500 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_VBUS_CHG_INT_A_EN BIT(7) BIT 501 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_VBUS_CHG_INT_B_EN BIT(6) BIT 504 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U3_PORT_SSP_SPEED BIT(9) BIT 505 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U3_PORT_DUAL_MODE BIT(7) BIT 506 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U3_PORT_HOST_SEL BIT(2) BIT 507 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U3_PORT_PDN BIT(1) BIT 508 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U3_PORT_DIS BIT(0) BIT 511 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U2_PORT_RG_IDDIG BIT(12) BIT 512 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U2_PORT_FORCE_IDDIG BIT(11) BIT 513 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U2_PORT_VBUSVALID BIT(9) BIT 514 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U2_PORT_OTG_SEL BIT(7) BIT 515 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U2_PORT_HOST BIT(2) BIT 516 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U2_PORT_PDN BIT(1) BIT 517 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_U2_PORT_DIS BIT(0) BIT 521 drivers/usb/mtu3/mtu3_hw_regs.h #define SSUSB_DEV_SW_RST BIT(0) BIT 29 drivers/usb/mtu3/mtu3_qmu.c #define GPD_FLAGS_HWO BIT(0) BIT 30 drivers/usb/mtu3/mtu3_qmu.c #define GPD_FLAGS_BDP BIT(1) BIT 31 drivers/usb/mtu3/mtu3_qmu.c #define GPD_FLAGS_BPS BIT(2) BIT 32 drivers/usb/mtu3/mtu3_qmu.c #define GPD_FLAGS_ZLP BIT(6) BIT 33 drivers/usb/mtu3/mtu3_qmu.c #define GPD_FLAGS_IOC BIT(7) BIT 52 drivers/usb/mtu3/mtu3_qmu.c #define GPD_EXT_FLAG_ZLP BIT(29) BIT 15 drivers/usb/musb/davinci.h #define USBPHY_DATAPOL BIT(11) /* (dm355) switch D+/D- */ BIT 16 drivers/usb/musb/davinci.h #define USBPHY_PHYCLKGD BIT(8) BIT 17 drivers/usb/musb/davinci.h #define USBPHY_SESNDEN BIT(7) /* v(sess_end) comparator */ BIT 18 drivers/usb/musb/davinci.h #define USBPHY_VBDTCTEN BIT(6) /* v(bus) comparator */ BIT 19 drivers/usb/musb/davinci.h #define USBPHY_VBUSSENS BIT(5) /* (dm355,ro) is vbus > 0.5V */ BIT 20 drivers/usb/musb/davinci.h #define USBPHY_PHYPLLON BIT(4) /* override pll suspend */ BIT 21 drivers/usb/musb/davinci.h #define USBPHY_CLKO1SEL BIT(3) BIT 22 drivers/usb/musb/davinci.h #define USBPHY_OSCPDWN BIT(2) BIT 23 drivers/usb/musb/davinci.h #define USBPHY_OTGPDWN BIT(1) BIT 24 drivers/usb/musb/davinci.h #define USBPHY_PHYPDWN BIT(0) BIT 27 drivers/usb/musb/davinci.h #define DRVVBUS_FORCE BIT(2) BIT 28 drivers/usb/musb/davinci.h #define DRVVBUS_OVERRIDE BIT(1) BIT 1631 drivers/usb/musb/musb_core.c musb->int_tx &= ~BIT(0); BIT 141 drivers/usb/musb/musb_core.h #define MUSB_G_NO_SKB_RESERVE BIT(9) BIT 142 drivers/usb/musb/musb_core.h #define MUSB_DA8XX BIT(8) BIT 143 drivers/usb/musb/musb_core.h #define MUSB_PRESERVE_SESSION BIT(7) BIT 144 drivers/usb/musb/musb_core.h #define MUSB_DMA_UX500 BIT(6) BIT 145 drivers/usb/musb/musb_core.h #define MUSB_DMA_CPPI41 BIT(5) BIT 146 drivers/usb/musb/musb_core.h #define MUSB_DMA_CPPI BIT(4) BIT 147 drivers/usb/musb/musb_core.h #define MUSB_DMA_TUSB_OMAP BIT(3) BIT 148 drivers/usb/musb/musb_core.h #define MUSB_DMA_INVENTRA BIT(2) BIT 149 drivers/usb/musb/musb_core.h #define MUSB_IN_TUSB BIT(1) BIT 150 drivers/usb/musb/musb_core.h #define MUSB_INDEXED_EP BIT(0) BIT 26 drivers/usb/phy/phy-keystone.c #define PHY_REF_SSP_EN BIT(29) BIT 47 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_SFTRST BIT(31) BIT 48 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_CLKGATE BIT(30) BIT 49 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27) BIT 50 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) BIT 51 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) BIT 52 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23) BIT 53 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22) BIT 54 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21) BIT 55 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) BIT 56 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) BIT 57 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) BIT 58 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15) BIT 59 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) BIT 60 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) BIT 62 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18)) BIT 64 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_DEBUG_CLKGATE BIT(30) BIT 66 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_PLL_LOCK BIT(31) BIT 67 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_PLL_REG_ENABLE BIT(21) BIT 68 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_PLL_BYPASS BIT(16) BIT 69 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_PLL_POWER BIT(12) BIT 70 drivers/usb/phy/phy-mxs-usb.c #define BM_USBPHY_PLL_EN_USB_CLKS BIT(6) BIT 80 drivers/usb/phy/phy-mxs-usb.c #define ANADIG_USB1_CHRG_DETECT_EN_B BIT(20) BIT 81 drivers/usb/phy/phy-mxs-usb.c #define ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B BIT(19) BIT 82 drivers/usb/phy/phy-mxs-usb.c #define ANADIG_USB1_CHRG_DETECT_CHK_CONTACT BIT(18) BIT 85 drivers/usb/phy/phy-mxs-usb.c #define ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) BIT 88 drivers/usb/phy/phy-mxs-usb.c #define ANADIG_USB1_CHRG_DET_STAT_DM_STATE BIT(2) BIT 89 drivers/usb/phy/phy-mxs-usb.c #define ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED BIT(1) BIT 90 drivers/usb/phy/phy-mxs-usb.c #define ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT BIT(0) BIT 96 drivers/usb/phy/phy-mxs-usb.c #define ANADIG_USB1_LOOPBACK_UTMI_TESTSTART BIT(0) BIT 104 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12) BIT 105 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11) BIT 107 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) BIT 108 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3) BIT 110 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2) BIT 111 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5) BIT 112 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2) BIT 113 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5) BIT 115 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29) BIT 116 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28) BIT 117 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29) BIT 118 drivers/usb/phy/phy-mxs-usb.c #define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28) BIT 123 drivers/usb/phy/phy-mxs-usb.c #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0) BIT 130 drivers/usb/phy/phy-mxs-usb.c #define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1) BIT 136 drivers/usb/phy/phy-mxs-usb.c #define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2) BIT 144 drivers/usb/phy/phy-mxs-usb.c #define MXS_PHY_NEED_IP_FIX BIT(3) BIT 64 drivers/usb/phy/phy-twl6030-usb.c #define STS_USB_ID BIT(2) BIT 76 drivers/usb/phy/phy-twl6030-usb.c #define VBUS_DET BIT(2) BIT 27 drivers/usb/roles/intel-xhci-usb-role-switch.c #define SW_VBUS_VALID BIT(24) BIT 28 drivers/usb/roles/intel-xhci-usb-role-switch.c #define SW_IDPIN_EN BIT(21) BIT 29 drivers/usb/roles/intel-xhci-usb-role-switch.c #define SW_IDPIN BIT(20) BIT 30 drivers/usb/roles/intel-xhci-usb-role-switch.c #define SW_SWITCH_EN BIT(16) BIT 38 drivers/usb/roles/intel-xhci-usb-role-switch.c #define HOST_MODE BIT(29) BIT 176 drivers/usb/serial/ch341.c a |= BIT(7); BIT 415 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_CTS_HANDSHAKE BIT(3) BIT 416 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_DSR_HANDSHAKE BIT(4) BIT 417 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_DCD_HANDSHAKE BIT(5) BIT 418 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_DSR_SENSITIVITY BIT(6) BIT 426 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_AUTO_TRANSMIT BIT(0) BIT 427 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_AUTO_RECEIVE BIT(1) BIT 428 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_ERROR_CHAR BIT(2) BIT 429 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_NULL_STRIPPING BIT(3) BIT 430 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_BREAK_CHAR BIT(4) BIT 433 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_XOFF_CONTINUE BIT(31) BIT 447 drivers/usb/serial/cp210x.c #define CP210X_PIN_MODE_GPIO BIT(0) BIT 488 drivers/usb/serial/cp210x.c #define CP2105_GPIO0_TXLED_MODE BIT(0) BIT 489 drivers/usb/serial/cp210x.c #define CP2105_GPIO1_RXLED_MODE BIT(1) BIT 490 drivers/usb/serial/cp210x.c #define CP2105_GPIO1_RS485_MODE BIT(2) BIT 493 drivers/usb/serial/cp210x.c #define CP2104_GPIO0_TXLED_MODE BIT(0) BIT 494 drivers/usb/serial/cp210x.c #define CP2104_GPIO1_RXLED_MODE BIT(1) BIT 495 drivers/usb/serial/cp210x.c #define CP2104_GPIO2_RS485_MODE BIT(2) BIT 1359 drivers/usb/serial/cp210x.c if (priv->gpio_altfunc & BIT(offset)) BIT 1386 drivers/usb/serial/cp210x.c return !!(buf & BIT(gpio)); BIT 1397 drivers/usb/serial/cp210x.c buf.state = BIT(gpio); BIT 1401 drivers/usb/serial/cp210x.c buf.mask = BIT(gpio); BIT 1437 drivers/usb/serial/cp210x.c return priv->gpio_input & BIT(gpio); BIT 1451 drivers/usb/serial/cp210x.c if (priv->gpio_pushpull & BIT(gpio)) BIT 1457 drivers/usb/serial/cp210x.c priv->gpio_input |= BIT(gpio); BIT 1468 drivers/usb/serial/cp210x.c priv->gpio_input &= ~BIT(gpio); BIT 1483 drivers/usb/serial/cp210x.c (priv->gpio_pushpull & BIT(gpio))) BIT 1487 drivers/usb/serial/cp210x.c !(priv->gpio_pushpull & BIT(gpio))) BIT 1552 drivers/usb/serial/cp210x.c priv->gpio_altfunc |= BIT(0); BIT 1555 drivers/usb/serial/cp210x.c priv->gpio_altfunc |= BIT(1); BIT 1590 drivers/usb/serial/cp210x.c priv->gpio_altfunc |= BIT(0); BIT 1592 drivers/usb/serial/cp210x.c priv->gpio_altfunc |= BIT(1); BIT 1594 drivers/usb/serial/cp210x.c priv->gpio_altfunc |= BIT(2); BIT 1606 drivers/usb/serial/cp210x.c if (!(priv->gpio_pushpull & BIT(i)) && (gpio_latch & BIT(i))) BIT 1607 drivers/usb/serial/cp210x.c priv->gpio_input |= BIT(i); BIT 1698 drivers/usb/serial/cp210x.c if (!(priv->gpio_pushpull & BIT(i)) && (gpio_latch & BIT(i))) BIT 1699 drivers/usb/serial/cp210x.c priv->gpio_input |= BIT(i); BIT 59 drivers/usb/serial/f81232.c #define F81232_CLK_18_46_MHZ BIT(0) BIT 60 drivers/usb/serial/f81232.c #define F81232_CLK_24_MHZ BIT(1) BIT 61 drivers/usb/serial/f81232.c #define F81232_CLK_14_77_MHZ (BIT(1) | BIT(0)) BIT 94 drivers/usb/serial/f81534.c #define F81534_BUS_BUSY (BIT(0) | BIT(1)) BIT 95 drivers/usb/serial/f81534.c #define F81534_BUS_IDLE BIT(2) BIT 106 drivers/usb/serial/f81534.c #define F81534_PORT_CONF_RS485 BIT(0) BIT 107 drivers/usb/serial/f81534.c #define F81534_PORT_CONF_RS485_INVERT (BIT(0) | BIT(1)) BIT 109 drivers/usb/serial/f81534.c #define F81534_PORT_CONF_DISABLE_PORT BIT(3) BIT 110 drivers/usb/serial/f81534.c #define F81534_PORT_CONF_NOT_EXIST_PORT BIT(7) BIT 131 drivers/usb/serial/f81534.c #define F81534_UART_EN BIT(0) BIT 133 drivers/usb/serial/f81534.c #define F81534_CLK_18_46_MHZ BIT(1) BIT 134 drivers/usb/serial/f81534.c #define F81534_CLK_24_MHZ BIT(2) BIT 135 drivers/usb/serial/f81534.c #define F81534_CLK_14_77_MHZ (BIT(1) | BIT(2)) BIT 137 drivers/usb/serial/f81534.c #define F81534_CLK_TX_DELAY_1BIT BIT(3) BIT 138 drivers/usb/serial/f81534.c #define F81534_CLK_RS485_MODE BIT(4) BIT 139 drivers/usb/serial/f81534.c #define F81534_CLK_RS485_INVERT BIT(5) BIT 183 drivers/usb/serial/f81534.c { { { 0x2ae8, BIT(7) }, { 0x2a90, BIT(5) }, { 0x2a90, BIT(4) } } }, BIT 184 drivers/usb/serial/f81534.c { { { 0x2ae8, BIT(6) }, { 0x2ae8, BIT(0) }, { 0x2ae8, BIT(3) } } }, BIT 185 drivers/usb/serial/f81534.c { { { 0x2a90, BIT(0) }, { 0x2ae8, BIT(2) }, { 0x2a80, BIT(6) } } }, BIT 186 drivers/usb/serial/f81534.c { { { 0x2a90, BIT(3) }, { 0x2a90, BIT(2) }, { 0x2a90, BIT(1) } } }, BIT 1361 drivers/usb/serial/f81534.c value & BIT(i) ? pins->pin[i].reg_mask : 0); BIT 1838 drivers/usb/serial/ftdi_sio.c if (priv->gpio_altfunc & BIT(offset)) BIT 1903 drivers/usb/serial/ftdi_sio.c return !!(result & BIT(gpio)); BIT 1914 drivers/usb/serial/ftdi_sio.c priv->gpio_value |= BIT(gpio); BIT 1916 drivers/usb/serial/ftdi_sio.c priv->gpio_value &= ~BIT(gpio); BIT 1958 drivers/usb/serial/ftdi_sio.c return !(priv->gpio_output & BIT(gpio)); BIT 1969 drivers/usb/serial/ftdi_sio.c priv->gpio_output &= ~BIT(gpio); BIT 1986 drivers/usb/serial/ftdi_sio.c priv->gpio_output |= BIT(gpio); BIT 1988 drivers/usb/serial/ftdi_sio.c priv->gpio_value |= BIT(gpio); BIT 1990 drivers/usb/serial/ftdi_sio.c priv->gpio_value &= ~BIT(gpio); BIT 2062 drivers/usb/serial/ftdi_sio.c priv->gpio_altfunc &= ~BIT(i); BIT 2096 drivers/usb/serial/ftdi_sio.c priv->gpio_altfunc &= ~BIT(i); BIT 2131 drivers/usb/serial/ftdi_sio.c priv->gpio_altfunc &= ~BIT(i); BIT 149 drivers/usb/serial/mxuport.c #define MX_UPORT_2_PORT BIT(0) BIT 150 drivers/usb/serial/mxuport.c #define MX_UPORT_4_PORT BIT(1) BIT 151 drivers/usb/serial/mxuport.c #define MX_UPORT_8_PORT BIT(2) BIT 152 drivers/usb/serial/mxuport.c #define MX_UPORT_16_PORT BIT(3) BIT 563 drivers/usb/serial/option.c #define NCTRL(ifnum) ((BIT(ifnum) & 0xff) << 8) BIT 566 drivers/usb/serial/option.c #define RSVD(ifnum) ((BIT(ifnum) & 0xff) << 0) BIT 569 drivers/usb/serial/option.c #define NUMEP2 BIT(16) BIT 572 drivers/usb/serial/option.c #define ZLP BIT(17) BIT 31 drivers/usb/serial/pl2303.c #define PL2303_QUIRK_UART_STATE_IDX0 BIT(0) BIT 32 drivers/usb/serial/pl2303.c #define PL2303_QUIRK_LEGACY BIT(1) BIT 33 drivers/usb/serial/pl2303.c #define PL2303_QUIRK_ENDPOINT_HACK BIT(2) BIT 52 drivers/usb/storage/uas.c SUBMIT_STATUS_URB = BIT(1), BIT 53 drivers/usb/storage/uas.c ALLOC_DATA_IN_URB = BIT(2), BIT 54 drivers/usb/storage/uas.c SUBMIT_DATA_IN_URB = BIT(3), BIT 55 drivers/usb/storage/uas.c ALLOC_DATA_OUT_URB = BIT(4), BIT 56 drivers/usb/storage/uas.c SUBMIT_DATA_OUT_URB = BIT(5), BIT 57 drivers/usb/storage/uas.c ALLOC_CMD_URB = BIT(6), BIT 58 drivers/usb/storage/uas.c SUBMIT_CMD_URB = BIT(7), BIT 59 drivers/usb/storage/uas.c COMMAND_INFLIGHT = BIT(8), BIT 60 drivers/usb/storage/uas.c DATA_IN_URB_INFLIGHT = BIT(9), BIT 61 drivers/usb/storage/uas.c DATA_OUT_URB_INFLIGHT = BIT(10), BIT 62 drivers/usb/storage/uas.c COMMAND_ABORTED = BIT(11), BIT 63 drivers/usb/storage/uas.c IS_IN_WORK_LIST = BIT(12), BIT 28 drivers/usb/typec/altmodes/displayport.c #define DP_PIN_ASSIGN_GEN2_BR_MASK (BIT(DP_PIN_ASSIGN_A) | \ BIT 29 drivers/usb/typec/altmodes/displayport.c BIT(DP_PIN_ASSIGN_B)) BIT 32 drivers/usb/typec/altmodes/displayport.c #define DP_PIN_ASSIGN_DP_BR_MASK (BIT(DP_PIN_ASSIGN_C) | \ BIT 33 drivers/usb/typec/altmodes/displayport.c BIT(DP_PIN_ASSIGN_D) | \ BIT 34 drivers/usb/typec/altmodes/displayport.c BIT(DP_PIN_ASSIGN_E) | \ BIT 35 drivers/usb/typec/altmodes/displayport.c BIT(DP_PIN_ASSIGN_F)) BIT 38 drivers/usb/typec/altmodes/displayport.c #define DP_PIN_ASSIGN_DP_ONLY_MASK (BIT(DP_PIN_ASSIGN_A) | \ BIT 39 drivers/usb/typec/altmodes/displayport.c BIT(DP_PIN_ASSIGN_C) | \ BIT 40 drivers/usb/typec/altmodes/displayport.c BIT(DP_PIN_ASSIGN_E)) BIT 43 drivers/usb/typec/altmodes/displayport.c #define DP_PIN_ASSIGN_MULTI_FUNC_MASK (BIT(DP_PIN_ASSIGN_B) | \ BIT 44 drivers/usb/typec/altmodes/displayport.c BIT(DP_PIN_ASSIGN_D) | \ BIT 45 drivers/usb/typec/altmodes/displayport.c BIT(DP_PIN_ASSIGN_F)) BIT 423 drivers/usb/typec/altmodes/displayport.c conf = DP_CONF_SET_PIN_ASSIGN(BIT(ret)); BIT 13 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7) BIT 14 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6) BIT 15 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5) BIT 16 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4) BIT 17 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3) BIT 18 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2) BIT 19 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1) BIT 20 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES0_CC1_PD_EN BIT(0) BIT 22 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES1_POWERROLE BIT(7) BIT 23 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES1_SPECREV1 BIT(6) BIT 24 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES1_SPECREV0 BIT(5) BIT 25 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES1_DATAROLE BIT(4) BIT 26 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES1_AUTO_GCRC BIT(2) BIT 27 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES1_TXCC2_EN BIT(1) BIT 28 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_SWITCHES1_TXCC1_EN BIT(0) BIT 30 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MEASURE_MDAC5 BIT(7) BIT 31 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MEASURE_MDAC4 BIT(6) BIT 32 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MEASURE_MDAC3 BIT(5) BIT 33 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MEASURE_MDAC2 BIT(4) BIT 34 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MEASURE_MDAC1 BIT(3) BIT 35 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MEASURE_MDAC0 BIT(2) BIT 36 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MEASURE_VBUS BIT(1) BIT 37 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MEASURE_XXXX5 BIT(0) BIT 39 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL0_TX_FLUSH BIT(6) BIT 40 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL0_INT_MASK BIT(5) BIT 45 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL0_TX_START BIT(0) BIT 47 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL1_ENSOP2DB BIT(6) BIT 48 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL1_ENSOP1DB BIT(5) BIT 49 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL1_BIST_MODE2 BIT(4) BIT 50 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL1_RX_FLUSH BIT(2) BIT 51 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL1_ENSOP2 BIT(1) BIT 52 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL1_ENSOP1 BIT(0) BIT 54 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL2_MODE BIT(1) BIT 60 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL2_TOGGLE BIT(0) BIT 62 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL3_SEND_HARDRESET BIT(6) BIT 63 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL3_BIST_TMODE BIT(5) /* 302B Only */ BIT 64 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL3_AUTO_HARDRESET BIT(4) BIT 65 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL3_AUTO_SOFTRESET BIT(3) BIT 66 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL3_N_RETRIES BIT(1) BIT 71 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_CONTROL3_AUTO_RETRY BIT(0) BIT 73 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASK_VBUSOK BIT(7) BIT 74 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASK_ACTIVITY BIT(6) BIT 75 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASK_COMP_CHNG BIT(5) BIT 76 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASK_CRC_CHK BIT(4) BIT 77 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASK_ALERT BIT(3) BIT 78 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASK_WAKE BIT(2) BIT 79 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASK_COLLISION BIT(1) BIT 80 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASK_BC_LVL BIT(0) BIT 82 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_POWER_PWR BIT(0) BIT 88 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_RESET_PD_RESET BIT(1) BIT 89 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_RESET_SW_RESET BIT(0) BIT 91 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASKA_OCP_TEMP BIT(7) BIT 92 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASKA_TOGDONE BIT(6) BIT 93 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASKA_SOFTFAIL BIT(5) BIT 94 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASKA_RETRYFAIL BIT(4) BIT 95 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASKA_HARDSENT BIT(3) BIT 96 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASKA_TX_SUCCESS BIT(2) BIT 97 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASKA_SOFTRESET BIT(1) BIT 98 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASKA_HARDRESET BIT(0) BIT 100 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_MASKB_GCRCSENT BIT(0) BIT 102 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0A_SOFTFAIL BIT(5) BIT 103 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0A_RETRYFAIL BIT(4) BIT 104 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0A_POWER BIT(2) BIT 105 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0A_RX_SOFT_RESET BIT(1) BIT 106 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0A_RX_HARD_RESET BIT(0) BIT 108 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS1A_TOGSS BIT(3) BIT 117 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS1A_RXSOP2DB BIT(2) BIT 118 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS1A_RXSOP1DB BIT(1) BIT 119 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS1A_RXSOP BIT(0) BIT 121 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPTA_OCP_TEMP BIT(7) BIT 122 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPTA_TOGDONE BIT(6) BIT 123 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPTA_SOFTFAIL BIT(5) BIT 124 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPTA_RETRYFAIL BIT(4) BIT 125 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPTA_HARDSENT BIT(3) BIT 126 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPTA_TX_SUCCESS BIT(2) BIT 127 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPTA_SOFTRESET BIT(1) BIT 128 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPTA_HARDRESET BIT(0) BIT 130 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPTB_GCRCSENT BIT(0) BIT 132 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0_VBUSOK BIT(7) BIT 133 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0_ACTIVITY BIT(6) BIT 134 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0_COMP BIT(5) BIT 135 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0_CRC_CHK BIT(4) BIT 136 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0_ALERT BIT(3) BIT 137 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0_WAKE BIT(2) BIT 143 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0_BC_LVL1 BIT(1) BIT 144 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS0_BC_LVL0 BIT(0) BIT 146 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS1_RXSOP2 BIT(7) BIT 147 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS1_RXSOP1 BIT(6) BIT 148 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS1_RX_EMPTY BIT(5) BIT 149 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS1_RX_FULL BIT(4) BIT 150 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS1_TX_EMPTY BIT(3) BIT 151 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_STATUS1_TX_FULL BIT(2) BIT 153 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPT_VBUSOK BIT(7) BIT 154 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPT_ACTIVITY BIT(6) BIT 155 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPT_COMP_CHNG BIT(5) BIT 156 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPT_CRC_CHK BIT(4) BIT 157 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPT_ALERT BIT(3) BIT 158 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPT_WAKE BIT(2) BIT 159 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPT_COLLISION BIT(1) BIT 160 drivers/usb/typec/tcpm/fusb302_reg.h #define FUSB_REG_INTERRUPT_BC_LVL BIT(0) BIT 19 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_VBUS_DISCNCT BIT(11) BIT 20 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_RX_BUF_OVF BIT(10) BIT 21 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_FAULT BIT(9) BIT 22 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_V_ALARM_LO BIT(8) BIT 23 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_V_ALARM_HI BIT(7) BIT 24 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_TX_SUCCESS BIT(6) BIT 25 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_TX_DISCARDED BIT(5) BIT 26 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_TX_FAILED BIT(4) BIT 27 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_RX_HARD_RST BIT(3) BIT 28 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_RX_STATUS BIT(2) BIT 29 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_POWER_STATUS BIT(1) BIT 30 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ALERT_CC_STATUS BIT(0) BIT 38 drivers/usb/typec/tcpm/tcpci.h #define TCPC_TCPC_CTRL_ORIENTATION BIT(0) BIT 41 drivers/usb/typec/tcpm/tcpci.h #define TCPC_ROLE_CTRL_DRP BIT(6) BIT 59 drivers/usb/typec/tcpm/tcpci.h #define TCPC_POWER_CTRL_VCONN_ENABLE BIT(0) BIT 62 drivers/usb/typec/tcpm/tcpci.h #define TCPC_CC_STATUS_TOGGLING BIT(5) BIT 63 drivers/usb/typec/tcpm/tcpci.h #define TCPC_CC_STATUS_TERM BIT(4) BIT 70 drivers/usb/typec/tcpm/tcpci.h #define TCPC_POWER_STATUS_UNINIT BIT(6) BIT 71 drivers/usb/typec/tcpm/tcpci.h #define TCPC_POWER_STATUS_VBUS_DET BIT(3) BIT 72 drivers/usb/typec/tcpm/tcpci.h #define TCPC_POWER_STATUS_VBUS_PRES BIT(2) BIT 95 drivers/usb/typec/tcpm/tcpci.h #define TCPC_MSG_HDR_INFO_DATA_ROLE BIT(3) BIT 96 drivers/usb/typec/tcpm/tcpci.h #define TCPC_MSG_HDR_INFO_PWR_ROLE BIT(0) BIT 101 drivers/usb/typec/tcpm/tcpci.h #define TCPC_RX_DETECT_HARD_RESET BIT(5) BIT 102 drivers/usb/typec/tcpm/tcpci.h #define TCPC_RX_DETECT_SOP BIT(0) BIT 164 drivers/usb/typec/tcpm/tcpm.c #define TCPM_CC_EVENT BIT(0) BIT 165 drivers/usb/typec/tcpm/tcpm.c #define TCPM_VBUS_EVENT BIT(1) BIT 166 drivers/usb/typec/tcpm/tcpm.c #define TCPM_RESET_EVENT BIT(2) BIT 62 drivers/usb/typec/tcpm/wcove.c #define USBC_CONTROL2_UNATT_SNK BIT(0) BIT 63 drivers/usb/typec/tcpm/wcove.c #define USBC_CONTROL2_UNATT_SRC BIT(1) BIT 64 drivers/usb/typec/tcpm/wcove.c #define USBC_CONTROL2_DIS_ST BIT(2) BIT 66 drivers/usb/typec/tcpm/wcove.c #define USBC_CONTROL3_DET_DIS BIT(0) BIT 67 drivers/usb/typec/tcpm/wcove.c #define USBC_CONTROL3_PD_DIS BIT(1) BIT 68 drivers/usb/typec/tcpm/wcove.c #define USBC_CONTROL3_RESETPHY BIT(2) BIT 70 drivers/usb/typec/tcpm/wcove.c #define USBC_CC_CTRL_PU_EN BIT(0) BIT 71 drivers/usb/typec/tcpm/wcove.c #define USBC_CC_CTRL_VCONN_EN BIT(1) BIT 72 drivers/usb/typec/tcpm/wcove.c #define USBC_CC_CTRL_TX_EN BIT(2) BIT 73 drivers/usb/typec/tcpm/wcove.c #define USBC_CC_CTRL_PD_EN BIT(3) BIT 74 drivers/usb/typec/tcpm/wcove.c #define USBC_CC_CTRL_CDET_EN BIT(4) BIT 75 drivers/usb/typec/tcpm/wcove.c #define USBC_CC_CTRL_RDET_EN BIT(5) BIT 76 drivers/usb/typec/tcpm/wcove.c #define USBC_CC_CTRL_ADC_EN BIT(6) BIT 77 drivers/usb/typec/tcpm/wcove.c #define USBC_CC_CTRL_VBUSOK BIT(7) BIT 79 drivers/usb/typec/tcpm/wcove.c #define USBC_STATUS1_DET_ONGOING BIT(6) BIT 93 drivers/usb/typec/tcpm/wcove.c #define USBC_STATUS2_VBUS_REQ BIT(5) BIT 95 drivers/usb/typec/tcpm/wcove.c #define UCSC_CC_STATUS_SNK_RP BIT(0) BIT 96 drivers/usb/typec/tcpm/wcove.c #define UCSC_CC_STATUS_PWRDEFSNK BIT(1) BIT 97 drivers/usb/typec/tcpm/wcove.c #define UCSC_CC_STATUS_PWR_1P5A_SNK BIT(2) BIT 98 drivers/usb/typec/tcpm/wcove.c #define UCSC_CC_STATUS_PWR_3A_SNK BIT(3) BIT 99 drivers/usb/typec/tcpm/wcove.c #define UCSC_CC_STATUS_SRC_RP BIT(4) BIT 104 drivers/usb/typec/tcpm/wcove.c #define USBC_IRQ1_ADCDONE1 BIT(2) BIT 105 drivers/usb/typec/tcpm/wcove.c #define USBC_IRQ1_OVERTEMP BIT(1) BIT 106 drivers/usb/typec/tcpm/wcove.c #define USBC_IRQ1_SHORT BIT(0) BIT 108 drivers/usb/typec/tcpm/wcove.c #define USBC_IRQ2_CC_CHANGE BIT(7) BIT 109 drivers/usb/typec/tcpm/wcove.c #define USBC_IRQ2_RX_PD BIT(6) BIT 110 drivers/usb/typec/tcpm/wcove.c #define USBC_IRQ2_RX_HR BIT(5) BIT 111 drivers/usb/typec/tcpm/wcove.c #define USBC_IRQ2_RX_CR BIT(4) BIT 112 drivers/usb/typec/tcpm/wcove.c #define USBC_IRQ2_TX_SUCCESS BIT(3) BIT 113 drivers/usb/typec/tcpm/wcove.c #define USBC_IRQ2_TX_FAIL BIT(2) BIT 122 drivers/usb/typec/tcpm/wcove.c #define USBC_PDCFG2_SOP BIT(0) BIT 123 drivers/usb/typec/tcpm/wcove.c #define USBC_PDCFG2_SOP_P BIT(1) BIT 124 drivers/usb/typec/tcpm/wcove.c #define USBC_PDCFG2_SOP_PP BIT(2) BIT 125 drivers/usb/typec/tcpm/wcove.c #define USBC_PDCFG2_SOP_P_DEBUG BIT(3) BIT 126 drivers/usb/typec/tcpm/wcove.c #define USBC_PDCFG2_SOP_PP_DEBUG BIT(4) BIT 131 drivers/usb/typec/tcpm/wcove.c #define USBC_RXSTATUS_RXCLEAR BIT(0) BIT 132 drivers/usb/typec/tcpm/wcove.c #define USBC_RXSTATUS_RXDATA BIT(7) BIT 136 drivers/usb/typec/tcpm/wcove.c #define USBC_TXCMD_BUF_RDY BIT(0) BIT 137 drivers/usb/typec/tcpm/wcove.c #define USBC_TXCMD_START BIT(1) BIT 574 drivers/usb/typec/tcpm/wcove.c regmap_write(wcove->regmap, WCOVE_CHGRIRQ0, BIT(5)); BIT 34 drivers/usb/typec/tps6598x.c #define TPS_REG_INT_PLUG_EVENT BIT(3) BIT 37 drivers/usb/typec/tps6598x.c #define TPS_STATUS_PLUG_PRESENT BIT(0) BIT 38 drivers/usb/typec/tps6598x.c #define TPS_STATUS_ORIENTATION BIT(4) BIT 39 drivers/usb/typec/tps6598x.c #define TPS_STATUS_PORTROLE(s) (!!((s) & BIT(5))) BIT 40 drivers/usb/typec/tps6598x.c #define TPS_STATUS_DATAROLE(s) (!!((s) & BIT(6))) BIT 41 drivers/usb/typec/tps6598x.c #define TPS_STATUS_VCONN(s) (!!((s) & BIT(7))) BIT 57 drivers/usb/typec/tps6598x.c #define TPS_POWER_STATUS_SOURCESINK BIT(1) BIT 157 drivers/usb/typec/ucsi/displayport.c if (DP_CAP_UFP_D_PIN_ASSIGN(cap) & BIT(DP_PIN_ASSIGN_D)) BIT 162 drivers/usb/typec/ucsi/displayport.c if (DP_CAP_DFP_D_PIN_ASSIGN(cap) & BIT(DP_PIN_ASSIGN_D)) BIT 288 drivers/usb/typec/ucsi/displayport.c u8 all_assignments = BIT(DP_PIN_ASSIGN_C) | BIT(DP_PIN_ASSIGN_D) | BIT 289 drivers/usb/typec/ucsi/displayport.c BIT(DP_PIN_ASSIGN_E); BIT 50 drivers/usb/typec/ucsi/trace.c if (cci & BIT(29)) BIT 52 drivers/usb/typec/ucsi/trace.c if (cci & BIT(31)) BIT 56 drivers/usb/typec/ucsi/trace.c if (cci & BIT(29)) BIT 58 drivers/usb/typec/ucsi/trace.c if (cci & BIT(31)) BIT 58 drivers/usb/typec/ucsi/ucsi.h #define UCSI_UOR_ROLE_DFP BIT(0) BIT 59 drivers/usb/typec/ucsi/ucsi.h #define UCSI_UOR_ROLE_UFP BIT(1) BIT 60 drivers/usb/typec/ucsi/ucsi.h #define UCSI_UOR_ROLE_DRP BIT(2) BIT 211 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_CMD_COMPLETE BIT(0) BIT 212 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_EXT_PWR_SRC_CHANGE BIT(1) BIT 213 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_PWR_OPMODE_CHANGE BIT(2) BIT 214 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_CAP_CHANGE BIT(5) BIT 215 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_PWR_LEVEL_CHANGE BIT(6) BIT 216 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_PD_RESET_COMPLETE BIT(7) BIT 217 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_CAM_CHANGE BIT(8) BIT 218 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_BAT_STATUS_CHANGE BIT(9) BIT 219 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_PARTNER_CHANGE BIT(11) BIT 220 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_PWR_DIR_CHANGE BIT(12) BIT 221 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_CONNECTOR_CHANGE BIT(14) BIT 222 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ENABLE_NTFY_ERROR BIT(15) BIT 226 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ERROR_UNREGONIZED_CMD BIT(0) BIT 227 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ERROR_INVALID_CON_NUM BIT(1) BIT 228 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ERROR_INVALID_CMD_ARGUMENT BIT(2) BIT 229 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ERROR_INCOMPATIBLE_PARTNER BIT(3) BIT 230 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ERROR_CC_COMMUNICATION_ERR BIT(4) BIT 231 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ERROR_DEAD_BATTERY BIT(5) BIT 232 drivers/usb/typec/ucsi/ucsi.h #define UCSI_ERROR_CONTRACT_NEGOTIATION_FAIL BIT(6) BIT 237 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_ATTR_DISABLE_STATE BIT(0) BIT 238 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_ATTR_BATTERY_CHARGING BIT(1) BIT 239 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_ATTR_USB_PD BIT(2) BIT 240 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_ATTR_TYPEC_CURRENT BIT(6) BIT 241 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_ATTR_POWER_AC_SUPPLY BIT(8) BIT 242 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_ATTR_POWER_OTHER BIT(10) BIT 243 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_ATTR_POWER_VBUS BIT(14) BIT 246 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_SET_UOM BIT(0) BIT 247 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_SET_PDM BIT(1) BIT 248 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_ALT_MODE_DETAILS BIT(2) BIT 249 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_ALT_MODE_OVERRIDE BIT(3) BIT 250 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_PDO_DETAILS BIT(4) BIT 251 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_CABLE_DETAILS BIT(5) BIT 252 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_EXT_SUPPLY_NOTIFICATIONS BIT(6) BIT 253 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CAP_PD_RESET BIT(7) BIT 264 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONCAP_OPMODE_DFP BIT(0) BIT 265 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONCAP_OPMODE_UFP BIT(1) BIT 266 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONCAP_OPMODE_DRP BIT(2) BIT 267 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONCAP_OPMODE_AUDIO_ACCESSORY BIT(3) BIT 268 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONCAP_OPMODE_DEBUG_ACCESSORY BIT(4) BIT 269 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONCAP_OPMODE_USB2 BIT(5) BIT 270 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONCAP_OPMODE_USB3 BIT(6) BIT 271 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONCAP_OPMODE_ALT_MODE BIT(7) BIT 303 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_EXT_SUPPLY_CHANGE BIT(1) BIT 304 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_POWER_OPMODE_CHANGE BIT(2) BIT 305 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_PDOS_CHANGE BIT(5) BIT 306 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_POWER_LEVEL_CHANGE BIT(6) BIT 307 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_PD_RESET_COMPLETE BIT(7) BIT 308 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_CAM_CHANGE BIT(8) BIT 309 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_BC_CHANGE BIT(9) BIT 310 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_PARTNER_CHANGE BIT(11) BIT 311 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_POWER_DIR_CHANGE BIT(12) BIT 312 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_CONNECT_CHANGE BIT(14) BIT 313 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_ERROR BIT(15) BIT 324 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_PARTNER_FLAG_USB BIT(0) BIT 325 drivers/usb/typec/ucsi/ucsi.h #define UCSI_CONSTAT_PARTNER_FLAG_ALT_MODE BIT(1) BIT 32 drivers/usb/typec/ucsi/ucsi_ccg.c #define DEV_INT BIT(0) BIT 33 drivers/usb/typec/ucsi/ucsi_ccg.c #define PORT0_INT BIT(1) BIT 34 drivers/usb/typec/ucsi/ucsi_ccg.c #define PORT1_INT BIT(2) BIT 35 drivers/usb/typec/ucsi/ucsi_ccg.c #define UCSI_READ_INT BIT(7) BIT 56 drivers/usb/typec/ucsi/ucsi_ccg.c #define CCGX_RAB_UCSI_CONTROL_START BIT(0) BIT 57 drivers/usb/typec/ucsi/ucsi_ccg.c #define CCGX_RAB_UCSI_CONTROL_STOP BIT(1) BIT 62 drivers/usb/typec/ucsi/ucsi_ccg.c #define PDPORT_1 BIT(0) BIT 63 drivers/usb/typec/ucsi/ucsi_ccg.c #define PDPORT_2 BIT(1) BIT 65 drivers/usb/typec/ucsi/ucsi_ccg.c #define ASYNC_EVENT BIT(7) BIT 52 drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c writel_relaxed(BIT(CONTROL_FLUSH_SHIFT), ring + RING_CONTROL); BIT 395 drivers/video/backlight/lm3630a_bl.c ret |= BIT(sources[i]); BIT 416 drivers/video/backlight/lm3630a_bl.c led_sources = lm3630a_parse_led_sources(node, BIT(bank)); BIT 428 drivers/video/backlight/lm3630a_bl.c if (led_sources & BIT(LM3630A_SINK_0) || BIT 429 drivers/video/backlight/lm3630a_bl.c !(led_sources & BIT(LM3630A_SINK_1))) BIT 436 drivers/video/backlight/lm3630a_bl.c if (!(led_sources & BIT(LM3630A_SINK_0))) BIT 443 drivers/video/backlight/lm3630a_bl.c if (led_sources & BIT(LM3630A_SINK_1)) BIT 20 drivers/video/backlight/lp8788_bl.c #define LP8788_BL_EN BIT(0) BIT 21 drivers/video/backlight/lp8788_bl.c #define LP8788_BL_PWM_INPUT_EN BIT(5) BIT 27 drivers/video/backlight/pandora_bl.c #define PWM0_CLK_ENABLE BIT(0) BIT 28 drivers/video/backlight/pandora_bl.c #define PWM0_ENABLE BIT(2) BIT 19 drivers/video/backlight/pm8941-wled.c #define PM8941_WLED_REG_MOD_EN_BIT BIT(7) BIT 20 drivers/video/backlight/pm8941-wled.c #define PM8941_WLED_REG_MOD_EN_MASK BIT(7) BIT 24 drivers/video/backlight/pm8941-wled.c #define PM8941_WLED_REG_SYNC_LED1 BIT(0) BIT 25 drivers/video/backlight/pm8941-wled.c #define PM8941_WLED_REG_SYNC_LED2 BIT(1) BIT 26 drivers/video/backlight/pm8941-wled.c #define PM8941_WLED_REG_SYNC_LED3 BIT(2) BIT 47 drivers/video/backlight/pm8941-wled.c #define PM8941_WLED_REG_STR_MOD_MASK BIT(7) BIT 48 drivers/video/backlight/pm8941-wled.c #define PM8941_WLED_REG_STR_MOD_EN BIT(7) BIT 59 drivers/video/backlight/pm8941-wled.c #define PM8941_WLED_REG_STR_CABC_MASK BIT(7) BIT 60 drivers/video/backlight/pm8941-wled.c #define PM8941_WLED_REG_STR_CABC_EN BIT(7) BIT 149 drivers/video/backlight/pm8941-wled.c u8 all = (BIT(wled->cfg.num_strings) - 1) BIT 16 drivers/video/backlight/rave-sp-backlight.c #define RAVE_SP_BACKLIGHT_LCD_EN BIT(7) BIT 27 drivers/video/fbdev/clps711x-fb.c # define LCDCON_GSEN BIT(30) BIT 28 drivers/video/fbdev/clps711x-fb.c # define LCDCON_GSMD BIT(31) BIT 50 drivers/video/fbdev/clps711x-fb.c if (regno >= BIT(info->var.bits_per_pixel)) BIT 333 drivers/video/fbdev/clps711x-fb.c ret = fb_alloc_cmap(&info->cmap, BIT(CLPS711X_FB_BPP_MAX), 0); BIT 36 drivers/video/fbdev/da8xx-fb.c #define LCD_END_OF_FRAME1 BIT(9) BIT 37 drivers/video/fbdev/da8xx-fb.c #define LCD_END_OF_FRAME0 BIT(8) BIT 38 drivers/video/fbdev/da8xx-fb.c #define LCD_PL_LOAD_DONE BIT(6) BIT 39 drivers/video/fbdev/da8xx-fb.c #define LCD_FIFO_UNDERFLOW BIT(5) BIT 40 drivers/video/fbdev/da8xx-fb.c #define LCD_SYNC_LOST BIT(2) BIT 41 drivers/video/fbdev/da8xx-fb.c #define LCD_FRAME_DONE BIT(0) BIT 50 drivers/video/fbdev/da8xx-fb.c #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) BIT 51 drivers/video/fbdev/da8xx-fb.c #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) BIT 52 drivers/video/fbdev/da8xx-fb.c #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) BIT 53 drivers/video/fbdev/da8xx-fb.c #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) BIT 65 drivers/video/fbdev/da8xx-fb.c #define LCD_MONO_8BIT_MODE BIT(9) BIT 66 drivers/video/fbdev/da8xx-fb.c #define LCD_RASTER_ORDER BIT(8) BIT 67 drivers/video/fbdev/da8xx-fb.c #define LCD_TFT_MODE BIT(7) BIT 68 drivers/video/fbdev/da8xx-fb.c #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) BIT 69 drivers/video/fbdev/da8xx-fb.c #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) BIT 70 drivers/video/fbdev/da8xx-fb.c #define LCD_V1_PL_INT_ENA BIT(4) BIT 71 drivers/video/fbdev/da8xx-fb.c #define LCD_V2_PL_INT_ENA BIT(6) BIT 72 drivers/video/fbdev/da8xx-fb.c #define LCD_MONOCHROME_MODE BIT(1) BIT 73 drivers/video/fbdev/da8xx-fb.c #define LCD_RASTER_ENABLE BIT(0) BIT 74 drivers/video/fbdev/da8xx-fb.c #define LCD_TFT_ALT_ENABLE BIT(23) BIT 75 drivers/video/fbdev/da8xx-fb.c #define LCD_STN_565_ENABLE BIT(24) BIT 76 drivers/video/fbdev/da8xx-fb.c #define LCD_V2_DMA_CLK_EN BIT(2) BIT 77 drivers/video/fbdev/da8xx-fb.c #define LCD_V2_LIDD_CLK_EN BIT(1) BIT 78 drivers/video/fbdev/da8xx-fb.c #define LCD_V2_CORE_CLK_EN BIT(0) BIT 80 drivers/video/fbdev/da8xx-fb.c #define LCD_V2_TFT_24BPP_MODE BIT(25) BIT 81 drivers/video/fbdev/da8xx-fb.c #define LCD_V2_TFT_24BPP_UNPACK BIT(26) BIT 86 drivers/video/fbdev/da8xx-fb.c #define LCD_SYNC_CTRL BIT(25) BIT 87 drivers/video/fbdev/da8xx-fb.c #define LCD_SYNC_EDGE BIT(24) BIT 88 drivers/video/fbdev/da8xx-fb.c #define LCD_INVERT_PIXEL_CLOCK BIT(22) BIT 89 drivers/video/fbdev/da8xx-fb.c #define LCD_INVERT_LINE_CLOCK BIT(21) BIT 90 drivers/video/fbdev/da8xx-fb.c #define LCD_INVERT_FRAME_CLOCK BIT(20) BIT 116 drivers/video/fbdev/da8xx-fb.c #define LCD_CLK_MAIN_RESET BIT(3) BIT 872 drivers/video/fbdev/da8xx-fb.c if (stat & BIT(0)) { BIT 22 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R02_NCLK_RISING BIT(3) BIT 23 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R02_HSYNC_HIGH BIT(4) BIT 24 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R02_VSYNC_HIGH BIT(5) BIT 26 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R03_NSTANDBY BIT(0) BIT 27 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R03_EN_CP_CLK BIT(1) BIT 28 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R03_EN_VGL_PUMP BIT(2) BIT 29 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R03_EN_PWM BIT(3) BIT 30 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R03_DRIVING_CAP_100 BIT(4) BIT 31 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R03_EN_PRE_CHARGE BIT(6) BIT 32 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R03_SOFTWARE_CTL BIT(7) BIT 34 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R04_NFLIP_H BIT(0) BIT 35 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R04_NFLIP_V BIT(1) BIT 36 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R04_CP_CLK_FREQ_1H BIT(2) BIT 37 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c #define TPO_R04_VGL_FREQ_1H BIT(4) BIT 317 drivers/video/fbdev/omap2/omapfb/dss/pll.c (cinfo->mX[0] ? BIT(7) : 0) | BIT 318 drivers/video/fbdev/omap2/omapfb/dss/pll.c (cinfo->mX[1] ? BIT(8) : 0) | BIT 319 drivers/video/fbdev/omap2/omapfb/dss/pll.c (cinfo->mX[2] ? BIT(10) : 0) | BIT 320 drivers/video/fbdev/omap2/omapfb/dss/pll.c (cinfo->mX[3] ? BIT(11) : 0)); BIT 430 drivers/video/fbdev/ssd1307fb.c BIT(4) | (par->device_info->need_chargepump ? BIT(2) : 0)); BIT 788 drivers/video/fbdev/sstfb.c (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) ); BIT 816 drivers/video/fbdev/sstfb.c | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) ); BIT 795 drivers/video/fbdev/tdfxfb.c dacmode &= ~(BIT(1) | BIT(3)); BIT 804 drivers/video/fbdev/tdfxfb.c dacmode |= BIT(3); BIT 807 drivers/video/fbdev/tdfxfb.c dacmode |= BIT(1); BIT 810 drivers/video/fbdev/tdfxfb.c dacmode |= BIT(1) | BIT(3); BIT 923 drivers/video/fbdev/tdfxfb.c blitcmd |= BIT(14); BIT 929 drivers/video/fbdev/tdfxfb.c blitcmd |= BIT(15); BIT 984 drivers/video/fbdev/tdfxfb.c srcfmt = 0x400000 | BIT(20); BIT 184 drivers/video/fbdev/tridentfb.c #define DDC_SDA_TGUI BIT(0) BIT 185 drivers/video/fbdev/tridentfb.c #define DDC_SCL_TGUI BIT(1) BIT 186 drivers/video/fbdev/tridentfb.c #define DDC_SCL_DRIVE_TGUI BIT(2) BIT 187 drivers/video/fbdev/tridentfb.c #define DDC_SDA_DRIVE_TGUI BIT(3) BIT 223 drivers/video/fbdev/tridentfb.c #define DDC_SDA_IN BIT(0) BIT 224 drivers/video/fbdev/tridentfb.c #define DDC_SCL_OUT BIT(1) BIT 225 drivers/video/fbdev/tridentfb.c #define DDC_SDA_OUT BIT(3) BIT 226 drivers/video/fbdev/tridentfb.c #define DDC_SCL_IN BIT(6) BIT 146 drivers/video/hdmi.c ptr[0] |= BIT(4); BIT 150 drivers/video/hdmi.c ptr[0] |= BIT(3); BIT 153 drivers/video/hdmi.c ptr[0] |= BIT(2); BIT 164 drivers/video/hdmi.c ptr[2] |= BIT(7); BIT 444 drivers/video/hdmi.c ptr[4] |= BIT(7); BIT 508 drivers/virt/vboxguest/vboxguest_core.c u32 bitmask = BIT(bit); BIT 50 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED BIT(0) BIT 52 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_HGCM BIT(1) BIT 54 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_DISPLAY_CHANGE_REQUEST BIT(2) BIT 56 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_JUDGE_CREDENTIALS BIT(3) BIT 58 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_RESTORED BIT(4) BIT 60 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_SEAMLESS_MODE_CHANGE_REQUEST BIT(5) BIT 62 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_BALLOON_CHANGE_REQUEST BIT(6) BIT 64 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_STATISTICS_INTERVAL_CHANGE_REQUEST BIT(7) BIT 66 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_VRDP BIT(8) BIT 68 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_MOUSE_POSITION_CHANGED BIT(9) BIT 70 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_EVENT_CPU_HOTPLUG BIT(10) BIT 124 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_MOUSE_GUEST_CAN_ABSOLUTE BIT(0) BIT 129 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_MOUSE_HOST_WANTS_ABSOLUTE BIT(1) BIT 138 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_MOUSE_GUEST_NEEDS_HOST_CURSOR BIT(2) BIT 140 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_MOUSE_HOST_CANNOT_HWPOINTER BIT(3) BIT 142 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_MOUSE_NEW_PROTOCOL BIT(4) BIT 147 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_MOUSE_HOST_RECHECKS_NEEDS_HOST_CURSOR BIT(5) BIT 152 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_MOUSE_HOST_HAS_ABS_DEV BIT(6) BIT 181 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_HVF_HGCM_PHYS_PAGE_LIST BIT(0) BIT 198 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_GUEST_SUPPORTS_SEAMLESS BIT(0) BIT 200 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_GUEST_SUPPORTS_GUEST_HOST_WINDOW_MAPPING BIT(1) BIT 208 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_GUEST_SUPPORTS_GRAPHICS BIT(2) BIT 234 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_OSTYPE_X64 BIT(8) BIT 250 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_GUEST_INFO2_ADDITIONS_FEATURES_REQUESTOR_INFO BIT(0) BIT 378 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_HGCM_REQ_DONE BIT(0) BIT 379 drivers/virt/vboxguest/vmmdev.h #define VMMDEV_HGCM_REQ_CANCELLED BIT(1) BIT 21 drivers/w1/masters/mxc_w1.c # define MXC_W1_CONTROL_RDST BIT(3) BIT 22 drivers/w1/masters/mxc_w1.c # define MXC_W1_CONTROL_WR(x) BIT(5 - (x)) BIT 23 drivers/w1/masters/mxc_w1.c # define MXC_W1_CONTROL_PST BIT(6) BIT 24 drivers/w1/masters/mxc_w1.c # define MXC_W1_CONTROL_RPP BIT(7) BIT 27 drivers/w1/masters/mxc_w1.c # define MXC_W1_RESET_RST BIT(0) BIT 30 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_CTRL_STATUS_SINGLE BIT(7) BIT 31 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK BIT(6) BIT 32 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE BIT(5) BIT 33 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_CTRL_STATUS_GO BIT(4) BIT 34 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_CTRL_STATUS_PRESENCE BIT(3) BIT 35 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION BIT(2) BIT 36 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_CTRL_STATUS_DIR BIT(1) BIT 38 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_INT_STATUS_TXCOMPLETE BIT(2) BIT 39 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_INT_STATUS_RXCOMPLETE BIT(1) BIT 40 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_INT_STATUS_TIMEOUT BIT(0) BIT 42 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_SYSCONFIG_SOFTRESET BIT(1) BIT 43 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_SYSCONFIG_AUTOIDLE BIT(0) BIT 46 drivers/w1/masters/omap_hdq.c #define OMAP_HDQ_SYSSTATUS_RESETDONE BIT(0) BIT 17 drivers/w1/masters/sgi_w1.c #define MCR_RD_DATA BIT(0) BIT 18 drivers/w1/masters/sgi_w1.c #define MCR_DONE BIT(1) BIT 43 drivers/w1/slaves/w1_ds2405.c int bit2send = !!(dev_addr & BIT(bit_ctr)); BIT 48 drivers/w1/slaves/w1_ds2405.c if ((ret & (BIT(0) | BIT(1))) == BIT 49 drivers/w1/slaves/w1_ds2405.c (BIT(0) | BIT(1))) /* no devices found */ BIT 52 drivers/w1/slaves/w1_ds2405.c if (!!(ret & BIT(2)) != bit2send) BIT 47 drivers/watchdog/armada_37xx_wdt.c #define WDT_TIMER_SELECT_VAL BIT(CNTR_ID_WDOG) BIT 24 drivers/watchdog/asm9260_wdt.c #define BM_MOD_WDINT BIT(3) BIT 26 drivers/watchdog/asm9260_wdt.c #define BM_MOD_WDTOF BIT(2) BIT 28 drivers/watchdog/asm9260_wdt.c #define BM_MOD_WDRESET BIT(1) BIT 30 drivers/watchdog/asm9260_wdt.c #define BM_MOD_WDEN BIT(0) BIT 46 drivers/watchdog/aspeed_wdt.c #define WDT_CTRL_BOOT_SECONDARY BIT(7) BIT 50 drivers/watchdog/aspeed_wdt.c #define WDT_CTRL_1MHZ_CLK BIT(4) BIT 51 drivers/watchdog/aspeed_wdt.c #define WDT_CTRL_WDT_EXT BIT(3) BIT 52 drivers/watchdog/aspeed_wdt.c #define WDT_CTRL_WDT_INTR BIT(2) BIT 53 drivers/watchdog/aspeed_wdt.c #define WDT_CTRL_RESET_SYSTEM BIT(1) BIT 54 drivers/watchdog/aspeed_wdt.c #define WDT_CTRL_ENABLE BIT(0) BIT 56 drivers/watchdog/aspeed_wdt.c #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) BIT 58 drivers/watchdog/aspeed_wdt.c #define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0) BIT 85 drivers/watchdog/aspeed_wdt.c #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) BIT 88 drivers/watchdog/aspeed_wdt.c #define WDT_RESET_WIDTH_PUSH_PULL BIT(30) BIT 43 drivers/watchdog/ath79_wdt.c #define WDOG_CTRL_LAST_RESET BIT(31) BIT 22 drivers/watchdog/atlas7_wdt.c #define ATLAS7_WDT_CNT_EN (BIT(0) | BIT(1)) BIT 21 drivers/watchdog/digicolor_wdt.c #define TIMER_A_ENABLE_COUNT BIT(0) BIT 22 drivers/watchdog/digicolor_wdt.c #define TIMER_A_ENABLE_WATCHDOG BIT(1) BIT 398 drivers/watchdog/f71808e_wdt.c tmp &= ~(BIT(3) | BIT(0)); BIT 399 drivers/watchdog/f71808e_wdt.c tmp |= BIT(2); BIT 435 drivers/watchdog/f71808e_wdt.c wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE); BIT 498 drivers/watchdog/f71808e_wdt.c is_running = (superio_inb(watchdog.sioaddr, SIO_REG_ENABLE) & BIT(0)) BIT 500 drivers/watchdog/f71808e_wdt.c & BIT(F71808FG_FLAG_WD_EN)); BIT 706 drivers/watchdog/f71808e_wdt.c watchdog.caused_reboot = wdt_conf & BIT(F71808FG_FLAG_WDTMOUT_STS); BIT 29 drivers/watchdog/ftwdt010_wdt.c #define WDCR_CLOCK_5MHZ BIT(4) BIT 30 drivers/watchdog/ftwdt010_wdt.c #define WDCR_WDEXT BIT(3) BIT 31 drivers/watchdog/ftwdt010_wdt.c #define WDCR_WDINTR BIT(2) BIT 32 drivers/watchdog/ftwdt010_wdt.c #define WDCR_SYS_RST BIT(1) BIT 33 drivers/watchdog/ftwdt010_wdt.c #define WDCR_ENABLE BIT(0) BIT 226 drivers/watchdog/iTCO_wdt.c val |= BIT(0); BIT 228 drivers/watchdog/iTCO_wdt.c val &= ~BIT(0); BIT 52 drivers/watchdog/imgpdc_wdt.c #define PDC_WDT_CONFIG_ENABLE BIT(31) BIT 38 drivers/watchdog/imx2_wdt.c #define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */ BIT 39 drivers/watchdog/imx2_wdt.c #define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */ BIT 40 drivers/watchdog/imx2_wdt.c #define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */ BIT 41 drivers/watchdog/imx2_wdt.c #define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */ BIT 42 drivers/watchdog/imx2_wdt.c #define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */ BIT 49 drivers/watchdog/imx2_wdt.c #define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */ BIT 52 drivers/watchdog/imx2_wdt.c #define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */ BIT 53 drivers/watchdog/imx2_wdt.c #define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */ BIT 17 drivers/watchdog/imx7ulp_wdt.c #define WDOG_CS_CMD32EN BIT(13) BIT 18 drivers/watchdog/imx7ulp_wdt.c #define WDOG_CS_ULK BIT(11) BIT 19 drivers/watchdog/imx7ulp_wdt.c #define WDOG_CS_RCS BIT(10) BIT 20 drivers/watchdog/imx7ulp_wdt.c #define WDOG_CS_EN BIT(7) BIT 21 drivers/watchdog/imx7ulp_wdt.c #define WDOG_CS_UPDATE BIT(5) BIT 150 drivers/watchdog/imx7ulp_wdt.c val = BIT(13) | BIT(8) | BIT(5); BIT 22 drivers/watchdog/lantiq_wdt.c #define LTQ_XRX_RCU_RST_STAT_WDT BIT(31) BIT 42 drivers/watchdog/lantiq_wdt.c #define LTQ_WDT_CR_GEN BIT(31) /* enable bit */ BIT 50 drivers/watchdog/lantiq_wdt.c #define LTQ_WDT_SR_EN BIT(31) /* Enable */ BIT 22 drivers/watchdog/lpc18xx_wdt.c #define LPC18XX_WDT_MOD_WDEN BIT(0) BIT 23 drivers/watchdog/lpc18xx_wdt.c #define LPC18XX_WDT_MOD_WDRESET BIT(1) BIT 20 drivers/watchdog/menz69_wdt.c #define MEN_Z069_WTR_WDEN BIT(15) BIT 23 drivers/watchdog/meson_gxbb_wdt.c #define GXBB_WDT_CTRL_CLKDIV_EN BIT(25) BIT 24 drivers/watchdog/meson_gxbb_wdt.c #define GXBB_WDT_CTRL_CLK_EN BIT(24) BIT 25 drivers/watchdog/meson_gxbb_wdt.c #define GXBB_WDT_CTRL_EE_RESET BIT(21) BIT 26 drivers/watchdog/meson_gxbb_wdt.c #define GXBB_WDT_CTRL_EN BIT(18) BIT 27 drivers/watchdog/meson_gxbb_wdt.c #define GXBB_WDT_CTRL_DIV_MASK (BIT(18) - 1) BIT 29 drivers/watchdog/meson_gxbb_wdt.c #define GXBB_WDT_TCNT_SETUP_MASK (BIT(16) - 1) BIT 44 drivers/watchdog/meson_wdt.c .enable = BIT(22), BIT 50 drivers/watchdog/meson_wdt.c .enable = BIT(19), BIT 84 drivers/watchdog/mlx_wdt.c BIT(reg_data->bit)); BIT 93 drivers/watchdog/mlx_wdt.c ~BIT(reg_data->bit)); BIT 102 drivers/watchdog/mlx_wdt.c ~reg_data->mask, BIT(reg_data->bit), BIT 122 drivers/watchdog/mlx_wdt.c set_time = BIT(hw_timeout) / MLXREG_WDT_CLOCK_SCALE; BIT 220 drivers/watchdog/mpc8xxx_wdt.c .rsr_mask = BIT(3), /* RSR Bit SWRS */ BIT 228 drivers/watchdog/mpc8xxx_wdt.c .rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */ BIT 236 drivers/watchdog/mpc8xxx_wdt.c .rsr_mask = BIT(28), /* RSR Bit SWRS */ BIT 22 drivers/watchdog/mt7621_wdt.c #define WDT_RST_CAUSE BIT(1) BIT 30 drivers/watchdog/mt7621_wdt.c #define TMR1CTL_ENABLE BIT(7) BIT 31 drivers/watchdog/mt7621_wdt.c #define TMR1CTL_RESTART BIT(9) BIT 17 drivers/watchdog/nic7018_wdt.c #define WDT_CTRL_RESET_EN BIT(7) BIT 18 drivers/watchdog/nic7018_wdt.c #define WDT_RELOAD_PORT_EN BIT(7) BIT 17 drivers/watchdog/npcm_wdt.c #define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ BIT 18 drivers/watchdog/npcm_wdt.c #define NPCM_WTE BIT(7) /* Enable */ BIT 19 drivers/watchdog/npcm_wdt.c #define NPCM_WTIE BIT(6) /* Enable irq */ BIT 20 drivers/watchdog/npcm_wdt.c #define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */ BIT 21 drivers/watchdog/npcm_wdt.c #define NPCM_WTIF BIT(3) /* Interrupt flag*/ BIT 22 drivers/watchdog/npcm_wdt.c #define NPCM_WTRF BIT(2) /* Reset flag */ BIT 23 drivers/watchdog/npcm_wdt.c #define NPCM_WTRE BIT(1) /* Reset enable */ BIT 24 drivers/watchdog/npcm_wdt.c #define NPCM_WTR BIT(0) /* Reset counter */ BIT 38 drivers/watchdog/orion_wdt.c #define TIMER1_FIXED_ENABLE_BIT BIT(12) BIT 39 drivers/watchdog/orion_wdt.c #define WDT_AXP_FIXED_ENABLE_BIT BIT(10) BIT 40 drivers/watchdog/orion_wdt.c #define TIMER1_ENABLE_BIT BIT(2) BIT 43 drivers/watchdog/orion_wdt.c #define WDT_A370_EXPIRED BIT(31) BIT 44 drivers/watchdog/orion_wdt.c #define TIMER1_STATUS_BIT BIT(8) BIT 422 drivers/watchdog/orion_wdt.c .rstout_enable_bit = BIT(1), BIT 423 drivers/watchdog/orion_wdt.c .wdt_enable_bit = BIT(4), BIT 432 drivers/watchdog/orion_wdt.c .rstout_enable_bit = BIT(8), BIT 433 drivers/watchdog/orion_wdt.c .wdt_enable_bit = BIT(8), BIT 442 drivers/watchdog/orion_wdt.c .rstout_enable_bit = BIT(8), BIT 443 drivers/watchdog/orion_wdt.c .wdt_enable_bit = BIT(8), BIT 452 drivers/watchdog/orion_wdt.c .rstout_enable_bit = BIT(8), BIT 453 drivers/watchdog/orion_wdt.c .rstout_mask_bit = BIT(10), BIT 454 drivers/watchdog/orion_wdt.c .wdt_enable_bit = BIT(8), BIT 463 drivers/watchdog/orion_wdt.c .rstout_enable_bit = BIT(8), BIT 464 drivers/watchdog/orion_wdt.c .rstout_mask_bit = BIT(10), BIT 465 drivers/watchdog/orion_wdt.c .wdt_enable_bit = BIT(8), BIT 32 drivers/watchdog/pic32-dmt.c #define DMT_ON BIT(15) BIT 33 drivers/watchdog/pic32-dmt.c #define DMT_STEP1_KEY BIT(6) BIT 34 drivers/watchdog/pic32-dmt.c #define DMT_STEP2_KEY BIT(3) BIT 35 drivers/watchdog/pic32-dmt.c #define DMTSTAT_WINOPN BIT(0) BIT 36 drivers/watchdog/pic32-dmt.c #define DMTSTAT_EVENT BIT(5) BIT 37 drivers/watchdog/pic32-dmt.c #define DMTSTAT_BAD2 BIT(6) BIT 38 drivers/watchdog/pic32-dmt.c #define DMTSTAT_BAD1 BIT(7) BIT 41 drivers/watchdog/pic32-dmt.c #define RESETCON_DMT_TIMEOUT BIT(5) BIT 26 drivers/watchdog/pic32-wdt.c #define WDTCON_WIN_EN BIT(0) BIT 31 drivers/watchdog/pic32-wdt.c #define WDTCON_ON BIT(15) BIT 35 drivers/watchdog/pic32-wdt.c #define RESETCON_TIMEOUT_IDLE BIT(2) BIT 36 drivers/watchdog/pic32-wdt.c #define RESETCON_TIMEOUT_SLEEP BIT(3) BIT 37 drivers/watchdog/pic32-wdt.c #define RESETCON_WDT_TIMEOUT BIT(4) BIT 90 drivers/watchdog/pic32-wdt.c terminal = BIT(ps); BIT 13 drivers/watchdog/pm8916_wdt.c #define PMIC_WD_BARK_STS_BIT BIT(6) BIT 24 drivers/watchdog/pm8916_wdt.c #define S2_RESET_EN_BIT BIT(7) BIT 27 drivers/watchdog/pm8916_wdt.c #define WATCHDOG_PET_BIT BIT(0) BIT 24 drivers/watchdog/qcom-wdt.c #define QCOM_WDT_ENABLE BIT(0) BIT 25 drivers/watchdog/qcom-wdt.c #define QCOM_WDT_ENABLE_IRQ BIT(1) BIT 23 drivers/watchdog/renesas_wdt.c #define RWTCSRA_WOVF BIT(4) BIT 24 drivers/watchdog/renesas_wdt.c #define RWTCSRA_WRFLG BIT(5) BIT 25 drivers/watchdog/renesas_wdt.c #define RWTCSRA_TME BIT(7) BIT 23 drivers/watchdog/rt2880_wdt.c #define WDT_RST_CAUSE BIT(1) BIT 31 drivers/watchdog/rt2880_wdt.c #define TMRSTAT_TMR1RST BIT(5) BIT 33 drivers/watchdog/rt2880_wdt.c #define TMR1CTL_ENABLE BIT(7) BIT 25 drivers/watchdog/rtd119x_wdt.c #define RTD119X_TCWTR_WDCLR BIT(0) BIT 23 drivers/watchdog/rza_wdt.c #define WTSCR_WT BIT(6) BIT 24 drivers/watchdog/rza_wdt.c #define WTSCR_TME BIT(5) BIT 32 drivers/watchdog/rza_wdt.c #define WRCSR_RSTE BIT(6) BIT 491 drivers/watchdog/s3c2410_wdt.c else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) BIT 72 drivers/watchdog/sbsa_gwdt.c #define SBSA_GWDT_WCS_EN BIT(0) BIT 73 drivers/watchdog/sbsa_gwdt.c #define SBSA_GWDT_WCS_WS0 BIT(1) BIT 74 drivers/watchdog/sbsa_gwdt.c #define SBSA_GWDT_WCS_WS1 BIT(2) BIT 19 drivers/watchdog/sp5100_tco.h #define SP5100_WDT_START_STOP_BIT BIT(0) BIT 20 drivers/watchdog/sp5100_tco.h #define SP5100_WDT_FIRED BIT(1) BIT 21 drivers/watchdog/sp5100_tco.h #define SP5100_WDT_ACTION_RESET BIT(2) BIT 22 drivers/watchdog/sp5100_tco.h #define SP5100_WDT_DISABLED BIT(3) BIT 23 drivers/watchdog/sp5100_tco.h #define SP5100_WDT_TRIGGER_BIT BIT(7) BIT 43 drivers/watchdog/sp5100_tco.h #define SP5100_PCI_WATCHDOG_DECODE_EN BIT(3) BIT 45 drivers/watchdog/sp5100_tco.h #define SP5100_PM_WATCHDOG_DISABLE ((u8)BIT(0)) BIT 56 drivers/watchdog/sp5100_tco.h #define SB800_PCI_WATCHDOG_DECODE_EN BIT(0) BIT 57 drivers/watchdog/sp5100_tco.h #define SB800_PM_WATCHDOG_DISABLE ((u8)BIT(1)) BIT 59 drivers/watchdog/sp5100_tco.h #define SB800_ACPI_MMIO_DECODE_EN BIT(0) BIT 60 drivers/watchdog/sp5100_tco.h #define SB800_ACPI_MMIO_SEL BIT(1) BIT 70 drivers/watchdog/sp5100_tco.h #define EFCH_PM_DECODEEN_WDT_TMREN BIT(7) BIT 82 drivers/watchdog/sp5100_tco.h #define EFCH_PM_ISACONTROL_MMIOEN BIT(1) BIT 33 drivers/watchdog/sprd_wdt.c #define SPRD_WDT_INT_EN_BIT BIT(0) BIT 34 drivers/watchdog/sprd_wdt.c #define SPRD_WDT_CNT_EN_BIT BIT(1) BIT 35 drivers/watchdog/sprd_wdt.c #define SPRD_WDT_NEW_VER_EN BIT(2) BIT 36 drivers/watchdog/sprd_wdt.c #define SPRD_WDT_RST_EN_BIT BIT(3) BIT 39 drivers/watchdog/sprd_wdt.c #define SPRD_WDT_INT_CLEAR_BIT BIT(0) BIT 40 drivers/watchdog/sprd_wdt.c #define SPRD_WDT_RST_CLEAR_BIT BIT(3) BIT 43 drivers/watchdog/sprd_wdt.c #define SPRD_WDT_INT_RAW_BIT BIT(0) BIT 44 drivers/watchdog/sprd_wdt.c #define SPRD_WDT_RST_RAW_BIT BIT(3) BIT 45 drivers/watchdog/sprd_wdt.c #define SPRD_WDT_LD_BUSY_BIT BIT(4) BIT 53 drivers/watchdog/st_lpc_wdt.c .enable_mask = BIT(19), BIT 39 drivers/watchdog/stm32_iwdg.c #define PR_MIN BIT(PR_SHIFT) BIT 46 drivers/watchdog/stm32_iwdg.c #define SR_PVU BIT(0) /* Watchdog prescaler value update */ BIT 47 drivers/watchdog/stm32_iwdg.c #define SR_RVU BIT(1) /* Watchdog counter reload value update */ BIT 15 drivers/watchdog/stpmic1_wdt.c #define WDT_START BIT(0) BIT 16 drivers/watchdog/stpmic1_wdt.c #define WDT_PING BIT(1) BIT 17 drivers/watchdog/stpmic1_wdt.c #define WDT_START_MASK BIT(0) BIT 18 drivers/watchdog/stpmic1_wdt.c #define WDT_PING_MASK BIT(1) BIT 37 drivers/watchdog/tangox_wdt.c #define WD_CONFIG_XTAL_IN BIT(0) BIT 38 drivers/watchdog/tangox_wdt.c #define WD_CONFIG_DISABLE BIT(31) BIT 31 drivers/watchdog/uniphier_wdt.c #define WDTCTRL_STATUS BIT(8) BIT 32 drivers/watchdog/uniphier_wdt.c #define WDTCTRL_CLEAR BIT(1) BIT 33 drivers/watchdog/uniphier_wdt.c #define WDTCTRL_ENABLE BIT(0) BIT 46 drivers/watchdog/zx2967_wdt.c #define ZX2967_WDT_FLAG_REBOOT_MON BIT(0) BIT 30 fs/debugfs/internal.h #define DEBUGFS_FSDATA_IS_REAL_FOPS_BIT BIT(0) BIT 311 fs/erofs/erofs_fs.h BUILD_BUG_ON(BIT(Z_EROFS_VLE_DI_CLUSTER_TYPE_BITS) < BIT 170 fs/erofs/zdata.c const unsigned int clusterpages = BIT(pcl->clusterbits); BIT 217 fs/erofs/zdata.c const unsigned int clusterpages = BIT(pcl->clusterbits); BIT 252 fs/erofs/zdata.c const unsigned int clusterpages = BIT(pcl->clusterbits); BIT 280 fs/erofs/zdata.c const unsigned int clusterpages = BIT(pcl->clusterbits); BIT 760 fs/erofs/zdata.c const unsigned int clusterpages = BIT(pcl->clusterbits); BIT 1243 fs/erofs/zdata.c clusterpages = BIT(pcl->clusterbits); BIT 178 fs/fscache/operation.c if (unlikely(!(flags & BIT(FSCACHE_OBJECT_IS_LIVE)))) { BIT 187 fs/fscache/operation.c } else if (flags & BIT(FSCACHE_OBJECT_IS_AVAILABLE)) { BIT 209 fs/fscache/operation.c } else if (flags & BIT(FSCACHE_OBJECT_IS_LOOKED_UP)) { BIT 217 fs/fscache/operation.c } else if (flags & BIT(FSCACHE_OBJECT_KILLED_BY_CACHE)) { BIT 265 fs/fscache/operation.c if (unlikely(!(flags & BIT(FSCACHE_OBJECT_IS_LIVE)))) { BIT 274 fs/fscache/operation.c } else if (flags & BIT(FSCACHE_OBJECT_IS_AVAILABLE)) { BIT 292 fs/fscache/operation.c } else if (flags & BIT(FSCACHE_OBJECT_IS_LOOKED_UP)) { BIT 299 fs/fscache/operation.c } else if (flags & BIT(FSCACHE_OBJECT_KILLED_BY_CACHE)) { BIT 165 fs/gfs2/aops.c BIT(BH_Dirty)|BIT(BH_Uptodate)); BIT 84 fs/gfs2/bmap.c create_empty_buffers(page, BIT(inode->i_blkbits), BIT 85 fs/gfs2/bmap.c BIT(BH_Uptodate)); BIT 1342 fs/gfs2/bmap.c bh.b_size = BIT(inode->i_blkbits + (create ? 0 : 5)); BIT 351 fs/gfs2/dir.c hsize = BIT(ip->i_depth); BIT 822 fs/gfs2/dir.c unsigned int hsize = BIT(ip->i_depth); BIT 934 fs/gfs2/dir.c gfs2_assert(sdp, dip->i_entries < BIT(16)); BIT 1043 fs/gfs2/dir.c len = BIT(dip->i_depth - be16_to_cpu(oleaf->lf_depth)); BIT 1163 fs/gfs2/dir.c hsize = BIT(dip->i_depth); BIT 1540 fs/gfs2/dir.c hsize = BIT(dip->i_depth); BIT 1559 fs/gfs2/dir.c len = BIT(dip->i_depth - depth); BIT 2109 fs/gfs2/dir.c hsize = BIT(dip->i_depth); BIT 2122 fs/gfs2/dir.c len = BIT(dip->i_depth - be16_to_cpu(leaf->lf_depth)); BIT 70 fs/gfs2/glock.c #define GFS2_GL_HASH_SIZE BIT(GFS2_GL_HASH_SHIFT) BIT 83 fs/gfs2/inode.h if (size & (BIT(inode->i_blkbits) - 1)) BIT 61 fs/gfs2/ops_fstype.c gt->gt_max_readahead = BIT(18); BIT 296 fs/gfs2/ops_fstype.c sdp->sd_fsb2bb = BIT(sdp->sd_fsb2bb_shift); BIT 314 fs/gfs2/ops_fstype.c hash_blocks = DIV_ROUND_UP(sizeof(u64) * BIT(GFS2_DIR_MAX_DEPTH), BIT 1084 fs/gfs2/ops_fstype.c sdp->sd_fsb2bb = BIT(sdp->sd_fsb2bb_shift); BIT 75 fs/gfs2/quota.c #define GFS2_QD_HASH_SIZE BIT(GFS2_QD_HASH_SHIFT) BIT 384 fs/gfs2/quota.c bh_map.b_size = BIT(ip->i_inode.i_blkbits); BIT 108 fs/gfs2/super.c if (gfs2_check_internal_file_size(jd->jd_inode, 8 << 20, BIT(30))) BIT 625 fs/nfs/callback_proc.c if (args->craa_type_mask & BIT(RCA4_TYPE_MASK_RDATA_DLG)) BIT 627 fs/nfs/callback_proc.c if (args->craa_type_mask & BIT(RCA4_TYPE_MASK_WDATA_DLG)) BIT 632 fs/nfs/callback_proc.c if (args->craa_type_mask & BIT(RCA4_TYPE_MASK_FILE_LAYOUT)) BIT 994 fs/nfs/delegation.c return (clp->cl_state & (BIT(NFS4CLNT_CHECK_LEASE) | BIT 995 fs/nfs/delegation.c BIT(NFS4CLNT_LEASE_EXPIRED) | BIT 996 fs/nfs/delegation.c BIT(NFS4CLNT_SESSION_RESET))) != 0; BIT 77 fs/nfs/nfstrace.h { BIT(NFS_INO_ADVISE_RDPLUS), "ADVISE_RDPLUS" }, \ BIT 78 fs/nfs/nfstrace.h { BIT(NFS_INO_STALE), "STALE" }, \ BIT 79 fs/nfs/nfstrace.h { BIT(NFS_INO_ACL_LRU_SET), "ACL_LRU_SET" }, \ BIT 80 fs/nfs/nfstrace.h { BIT(NFS_INO_INVALIDATING), "INVALIDATING" }, \ BIT 81 fs/nfs/nfstrace.h { BIT(NFS_INO_FSCACHE), "FSCACHE" }, \ BIT 82 fs/nfs/nfstrace.h { BIT(NFS_INO_FSCACHE_LOCK), "FSCACHE_LOCK" }, \ BIT 83 fs/nfs/nfstrace.h { BIT(NFS_INO_LAYOUTCOMMIT), "NEED_LAYOUTCOMMIT" }, \ BIT 84 fs/nfs/nfstrace.h { BIT(NFS_INO_LAYOUTCOMMITTING), "LAYOUTCOMMIT" }, \ BIT 85 fs/nfs/nfstrace.h { BIT(NFS_INO_LAYOUTSTATS), "LAYOUTSTATS" }, \ BIT 86 fs/nfs/nfstrace.h { BIT(NFS_INO_ODIRECT), "ODIRECT" }) BIT 35 fs/nilfs2/btnode.c bh = nilfs_grab_buffer(inode, btnc, blocknr, BIT(BH_NILFS_Node)); BIT 64 fs/nilfs2/btnode.c bh = nilfs_grab_buffer(inode, btnc, blocknr, BIT(BH_NILFS_Node)); BIT 350 fs/nilfs2/inode.c ii->i_state = BIT(NILFS_I_NEW); BIT 549 fs/nilfs2/inode.c NILFS_I(inode)->i_state = BIT(NILFS_I_GCINODE); BIT 115 fs/nilfs2/nilfs.h (BIT(NILFS_DAT_INO) | BIT(NILFS_CPFILE_INO) | \ BIT 116 fs/nilfs2/nilfs.h BIT(NILFS_SUFILE_INO) | BIT(NILFS_IFILE_INO) | \ BIT 117 fs/nilfs2/nilfs.h BIT(NILFS_ATIME_INO) | BIT(NILFS_SKETCH_INO)) BIT 119 fs/nilfs2/nilfs.h #define NILFS_SYS_INO_BITS (BIT(NILFS_ROOT_INO) | NILFS_MDT_INO_BITS) BIT 124 fs/nilfs2/nilfs.h ((ino) < NILFS_FIRST_INO(sb) && (NILFS_MDT_INO_BITS & BIT(ino))) BIT 126 fs/nilfs2/nilfs.h ((ino) >= NILFS_FIRST_INO(sb) || (NILFS_SYS_INO_BITS & BIT(ino))) BIT 25 fs/nilfs2/page.c (BIT(BH_Uptodate) | BIT(BH_Mapped) | BIT(BH_NILFS_Node) | \ BIT 26 fs/nilfs2/page.c BIT(BH_NILFS_Volatile) | BIT(BH_NILFS_Checked)) BIT 79 fs/nilfs2/page.c (BIT(BH_Uptodate) | BIT(BH_Dirty) | BIT(BH_Mapped) | BIT 80 fs/nilfs2/page.c BIT(BH_Async_Write) | BIT(BH_NILFS_Volatile) | BIT 81 fs/nilfs2/page.c BIT(BH_NILFS_Checked) | BIT(BH_NILFS_Redirected)); BIT 118 fs/nilfs2/page.c bits = sbh->b_state & (BIT(BH_Uptodate) | BIT(BH_Mapped)); BIT 124 fs/nilfs2/page.c if (bits & BIT(BH_Uptodate)) BIT 128 fs/nilfs2/page.c if (bits & BIT(BH_Mapped)) BIT 209 fs/nilfs2/page.c mask |= BIT(BH_Dirty); BIT 404 fs/nilfs2/page.c (BIT(BH_Uptodate) | BIT(BH_Dirty) | BIT(BH_Mapped) | BIT 405 fs/nilfs2/page.c BIT(BH_Async_Write) | BIT(BH_NILFS_Volatile) | BIT 406 fs/nilfs2/page.c BIT(BH_NILFS_Checked) | BIT(BH_NILFS_Redirected)); BIT 1850 fs/nilfs2/segment.c const unsigned long set_bits = BIT(BH_Uptodate); BIT 1852 fs/nilfs2/segment.c (BIT(BH_Dirty) | BIT(BH_Async_Write) | BIT 1853 fs/nilfs2/segment.c BIT(BH_Delay) | BIT(BH_NILFS_Volatile) | BIT 1854 fs/nilfs2/segment.c BIT(BH_NILFS_Redirected)); BIT 2126 fs/nilfs2/segment.c if (!(sci->sc_flush_request & BIT(bn))) { BIT 2129 fs/nilfs2/segment.c sci->sc_flush_request |= BIT(bn); BIT 2312 fs/nilfs2/segment.c #define FLUSH_DAT_BIT BIT(NILFS_DAT_INO) /* DAT only */ BIT 439 fs/nilfs2/sufile.c if (su->su_flags == cpu_to_le32(BIT(NILFS_SEGMENT_USAGE_DIRTY)) && BIT 450 fs/nilfs2/sufile.c su->su_flags = cpu_to_le32(BIT(NILFS_SEGMENT_USAGE_DIRTY)); BIT 688 fs/nilfs2/sufile.c ~BIT(NILFS_SEGMENT_USAGE_ERROR)) || BIT 855 fs/nilfs2/sufile.c ~BIT(NILFS_SEGMENT_USAGE_ACTIVE); BIT 858 fs/nilfs2/sufile.c BIT(NILFS_SEGMENT_USAGE_ACTIVE); BIT 946 fs/nilfs2/sufile.c ~BIT(NILFS_SEGMENT_USAGE_ACTIVE); BIT 86 include/asm-generic/bitops/lock.h return !!(old & BIT(7)); BIT 12 include/clocksource/arm_arch_timer.h #define ARCH_TIMER_TYPE_CP15 BIT(0) BIT 13 include/clocksource/arm_arch_timer.h #define ARCH_TIMER_TYPE_MEM BIT(1) BIT 85 include/drm/drm_atomic_helper.h #define DRM_PLANE_COMMIT_ACTIVE_ONLY BIT(0) BIT 86 include/drm/drm_atomic_helper.h #define DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET BIT(1) BIT 88 include/drm/drm_color_mgmt.h DRM_COLOR_LUT_EQUAL_CHANNELS = BIT(0), BIT 96 include/drm/drm_color_mgmt.h DRM_COLOR_LUT_NON_DECREASING = BIT(1), BIT 331 include/drm/drm_connector.h DRM_BUS_FLAG_DE_LOW = BIT(0), BIT 332 include/drm/drm_connector.h DRM_BUS_FLAG_DE_HIGH = BIT(1), BIT 333 include/drm/drm_connector.h DRM_BUS_FLAG_PIXDATA_POSEDGE = BIT(2), BIT 334 include/drm/drm_connector.h DRM_BUS_FLAG_PIXDATA_NEGEDGE = BIT(3), BIT 339 include/drm/drm_connector.h DRM_BUS_FLAG_DATA_MSB_TO_LSB = BIT(4), BIT 340 include/drm/drm_connector.h DRM_BUS_FLAG_DATA_LSB_TO_MSB = BIT(5), BIT 341 include/drm/drm_connector.h DRM_BUS_FLAG_SYNC_POSEDGE = BIT(6), BIT 342 include/drm/drm_connector.h DRM_BUS_FLAG_SYNC_NEGEDGE = BIT(7), BIT 347 include/drm/drm_connector.h DRM_BUS_FLAG_SHARP_SIGNALS = BIT(8), BIT 930 include/drm/drm_dp_helper.h # define DP_BCAPS_REPEATER_PRESENT BIT(1) BIT 931 include/drm/drm_dp_helper.h # define DP_BCAPS_HDCP_CAPABLE BIT(0) BIT 933 include/drm/drm_dp_helper.h # define DP_BSTATUS_REAUTH_REQ BIT(3) BIT 934 include/drm/drm_dp_helper.h # define DP_BSTATUS_LINK_FAILURE BIT(2) BIT 935 include/drm/drm_dp_helper.h # define DP_BSTATUS_R0_PRIME_READY BIT(1) BIT 936 include/drm/drm_dp_helper.h # define DP_BSTATUS_READY BIT(0) BIT 986 include/drm/drm_dp_helper.h #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) BIT 987 include/drm/drm_dp_helper.h #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) BIT 988 include/drm/drm_dp_helper.h #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) BIT 989 include/drm/drm_dp_helper.h #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) BIT 990 include/drm/drm_dp_helper.h #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) BIT 1449 include/drm/drm_dp_helper.h return desc->quirks & BIT(quirk); BIT 57 include/drm/drm_drv.h DRIVER_GEM = BIT(0), BIT 63 include/drm/drm_drv.h DRIVER_MODESET = BIT(1), BIT 70 include/drm/drm_drv.h DRIVER_RENDER = BIT(3), BIT 80 include/drm/drm_drv.h DRIVER_ATOMIC = BIT(4), BIT 87 include/drm/drm_drv.h DRIVER_SYNCOBJ = BIT(5), BIT 94 include/drm/drm_drv.h DRIVER_SYNCOBJ_TIMELINE = BIT(6), BIT 104 include/drm/drm_drv.h DRIVER_USE_AGP = BIT(25), BIT 110 include/drm/drm_drv.h DRIVER_LEGACY = BIT(26), BIT 117 include/drm/drm_drv.h DRIVER_PCI_DMA = BIT(27), BIT 125 include/drm/drm_drv.h DRIVER_SG = BIT(28), BIT 133 include/drm/drm_drv.h DRIVER_HAVE_DMA = BIT(29), BIT 143 include/drm/drm_drv.h DRIVER_HAVE_IRQ = BIT(30), BIT 150 include/drm/drm_drv.h DRIVER_KMS_LEGACY_CONTEXT = BIT(31), BIT 26 include/drm/drm_hdcp.h #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3)) BIT 27 include/drm/drm_hdcp.h #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7)) BIT 39 include/drm/drm_hdcp.h #define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6) BIT 40 include/drm/drm_hdcp.h #define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5) BIT 108 include/drm/drm_hdcp.h #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0)) BIT 109 include/drm/drm_hdcp.h #define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1)) BIT 113 include/drm/drm_hdcp.h #define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0)) BIT 116 include/drm/drm_hdcp.h #define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1)) BIT 117 include/drm/drm_hdcp.h #define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2)) BIT 118 include/drm/drm_hdcp.h #define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3)) BIT 120 include/drm/drm_hdcp.h #define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0)) BIT 239 include/drm/drm_hdcp.h #define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2) BIT 247 include/drm/drm_hdcp.h #define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2)) BIT 248 include/drm/drm_hdcp.h #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) BIT 87 include/drm/drm_ioctl.h DRM_AUTH = BIT(0), BIT 99 include/drm/drm_ioctl.h DRM_MASTER = BIT(1), BIT 110 include/drm/drm_ioctl.h DRM_ROOT_ONLY = BIT(2), BIT 121 include/drm/drm_ioctl.h DRM_UNLOCKED = BIT(4), BIT 131 include/drm/drm_ioctl.h DRM_RENDER_ALLOW = BIT(5), BIT 18 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MSG_REQ_ACK BIT(0) BIT 20 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MSG_USE_LPM BIT(1) BIT 111 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_VIDEO BIT(0) BIT 113 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_VIDEO_BURST BIT(1) BIT 115 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) BIT 117 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) BIT 119 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_VIDEO_HSE BIT(4) BIT 121 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_VIDEO_HFP BIT(5) BIT 123 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_VIDEO_HBP BIT(6) BIT 125 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_VIDEO_HSA BIT(7) BIT 127 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) BIT 129 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_EOT_PACKET BIT(9) BIT 131 include/drm/drm_mipi_dsi.h #define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) BIT 133 include/drm/drm_mipi_dsi.h #define MIPI_DSI_MODE_LPM BIT(11) BIT 121 include/drm/drm_mm.h DRM_MM_INSERT_ONCE = BIT(31), BIT 89 include/drm/drm_modeset_lock.h #define DRM_MODESET_ACQUIRE_INTERRUPTIBLE BIT(0) BIT 58 include/linux/alcor_pci.h #define AU6621_DMA_ENABLE BIT(0) BIT 94 include/linux/alcor_pci.h #define AU6601_MS_CARD_WP BIT(3) BIT 95 include/linux/alcor_pci.h #define AU6601_SD_CARD_WP BIT(0) BIT 102 include/linux/alcor_pci.h #define AU6601_XD_CARD BIT(4) BIT 104 include/linux/alcor_pci.h #define AU6601_MS_CARD BIT(3) BIT 105 include/linux/alcor_pci.h #define AU6601_SD_CARD BIT(0) BIT 111 include/linux/alcor_pci.h #define AU6601_DETECT_EN BIT(7) BIT 112 include/linux/alcor_pci.h #define AU6601_MS_DETECTED BIT(3) BIT 113 include/linux/alcor_pci.h #define AU6601_SD_DETECTED BIT(0) BIT 117 include/linux/alcor_pci.h #define AU6601_BUF_CTRL_RESET BIT(7) BIT 118 include/linux/alcor_pci.h #define AU6601_RESET_DATA BIT(3) BIT 119 include/linux/alcor_pci.h #define AU6601_RESET_CMD BIT(0) BIT 143 include/linux/alcor_pci.h #define AU6601_DATA_WRITE BIT(7) BIT 144 include/linux/alcor_pci.h #define AU6601_DATA_DMA_MODE BIT(6) BIT 145 include/linux/alcor_pci.h #define AU6601_DATA_START_XFER BIT(0) BIT 148 include/linux/alcor_pci.h #define AU6601_BUS_STAT_CMD BIT(15) BIT 152 include/linux/alcor_pci.h #define AU6601_BUS_STAT_DAT3 BIT(3) BIT 153 include/linux/alcor_pci.h #define AU6601_BUS_STAT_DAT2 BIT(2) BIT 154 include/linux/alcor_pci.h #define AU6601_BUS_STAT_DAT1 BIT(1) BIT 155 include/linux/alcor_pci.h #define AU6601_BUS_STAT_DAT0 BIT(0) BIT 160 include/linux/alcor_pci.h #define AU6601_OPT_NCRC_16_CLK BIT(4) BIT 161 include/linux/alcor_pci.h #define AU6601_OPT_CMD_NWT BIT(3) BIT 162 include/linux/alcor_pci.h #define AU6601_OPT_STOP_CLK BIT(2) BIT 163 include/linux/alcor_pci.h #define AU6601_OPT_DDR_MODE BIT(1) BIT 164 include/linux/alcor_pci.h #define AU6601_OPT_SD_18V BIT(0) BIT 175 include/linux/alcor_pci.h #define AU6601_INT_DATA_END_BIT_ERR BIT(22) BIT 176 include/linux/alcor_pci.h #define AU6601_INT_DATA_CRC_ERR BIT(21) BIT 177 include/linux/alcor_pci.h #define AU6601_INT_DATA_TIMEOUT_ERR BIT(20) BIT 178 include/linux/alcor_pci.h #define AU6601_INT_CMD_INDEX_ERR BIT(19) BIT 179 include/linux/alcor_pci.h #define AU6601_INT_CMD_END_BIT_ERR BIT(18) BIT 180 include/linux/alcor_pci.h #define AU6601_INT_CMD_CRC_ERR BIT(17) BIT 181 include/linux/alcor_pci.h #define AU6601_INT_CMD_TIMEOUT_ERR BIT(16) BIT 182 include/linux/alcor_pci.h #define AU6601_INT_ERROR BIT(15) BIT 183 include/linux/alcor_pci.h #define AU6601_INT_OVER_CURRENT_ERR BIT(8) BIT 184 include/linux/alcor_pci.h #define AU6601_INT_CARD_INSERT BIT(7) BIT 185 include/linux/alcor_pci.h #define AU6601_INT_CARD_REMOVE BIT(6) BIT 186 include/linux/alcor_pci.h #define AU6601_INT_READ_BUF_RDY BIT(5) BIT 187 include/linux/alcor_pci.h #define AU6601_INT_WRITE_BUF_RDY BIT(4) BIT 188 include/linux/alcor_pci.h #define AU6601_INT_DMA_END BIT(3) BIT 189 include/linux/alcor_pci.h #define AU6601_INT_DATA_END BIT(1) BIT 190 include/linux/alcor_pci.h #define AU6601_INT_CMD_END BIT(0) BIT 226 include/linux/alcor_pci.h #define AU6601_MS_XFER_INT_TIMEOUT_CHK BIT(2) BIT 227 include/linux/alcor_pci.h #define AU6601_MS_XFER_DMA_ENABLE BIT(1) BIT 228 include/linux/alcor_pci.h #define AU6601_MS_XFER_START BIT(0) BIT 234 include/linux/alcor_pci.h #define AU6601_MS_INT_OVER_CURRENT_ERROR BIT(23) BIT 235 include/linux/alcor_pci.h #define AU6601_MS_INT_DATA_CRC_ERROR BIT(21) BIT 236 include/linux/alcor_pci.h #define AU6601_MS_INT_INT_TIMEOUT BIT(20) BIT 237 include/linux/alcor_pci.h #define AU6601_MS_INT_INT_RESP_ERROR BIT(19) BIT 238 include/linux/alcor_pci.h #define AU6601_MS_INT_CED_ERROR BIT(18) BIT 239 include/linux/alcor_pci.h #define AU6601_MS_INT_TPC_TIMEOUT BIT(16) BIT 240 include/linux/alcor_pci.h #define AU6601_MS_INT_ERROR BIT(15) BIT 241 include/linux/alcor_pci.h #define AU6601_MS_INT_CARD_INSERT BIT(7) BIT 242 include/linux/alcor_pci.h #define AU6601_MS_INT_CARD_REMOVE BIT(6) BIT 243 include/linux/alcor_pci.h #define AU6601_MS_INT_BUF_READ_RDY BIT(5) BIT 244 include/linux/alcor_pci.h #define AU6601_MS_INT_BUF_WRITE_RDY BIT(4) BIT 245 include/linux/alcor_pci.h #define AU6601_MS_INT_DMA_END BIT(3) BIT 246 include/linux/alcor_pci.h #define AU6601_MS_INT_TPC_END BIT(1) BIT 38 include/linux/amba/pl080.h #define PL080_CONFIG_M2_BE BIT(2) BIT 39 include/linux/amba/pl080.h #define PL080_CONFIG_M1_BE BIT(1) BIT 40 include/linux/amba/pl080.h #define PL080_CONFIG_ENABLE BIT(0) BIT 72 include/linux/amba/pl080.h #define PL080_LLI_LM_AHB2 BIT(0) BIT 74 include/linux/amba/pl080.h #define PL080_CONTROL_TC_IRQ_EN BIT(31) BIT 77 include/linux/amba/pl080.h #define PL080_CONTROL_PROT_CACHE BIT(30) BIT 78 include/linux/amba/pl080.h #define PL080_CONTROL_PROT_BUFF BIT(29) BIT 79 include/linux/amba/pl080.h #define PL080_CONTROL_PROT_SYS BIT(28) BIT 80 include/linux/amba/pl080.h #define PL080_CONTROL_DST_INCR BIT(27) BIT 81 include/linux/amba/pl080.h #define PL080_CONTROL_SRC_INCR BIT(26) BIT 82 include/linux/amba/pl080.h #define PL080_CONTROL_DST_AHB2 BIT(25) BIT 83 include/linux/amba/pl080.h #define PL080_CONTROL_SRC_AHB2 BIT(24) BIT 109 include/linux/amba/pl080.h #define PL080N_CONFIG_ITPROT BIT(20) BIT 110 include/linux/amba/pl080.h #define PL080N_CONFIG_SECPROT BIT(19) BIT 111 include/linux/amba/pl080.h #define PL080_CONFIG_HALT BIT(18) BIT 112 include/linux/amba/pl080.h #define PL080_CONFIG_ACTIVE BIT(17) /* RO */ BIT 113 include/linux/amba/pl080.h #define PL080_CONFIG_LOCK BIT(16) BIT 114 include/linux/amba/pl080.h #define PL080_CONFIG_TC_IRQ_MASK BIT(15) BIT 115 include/linux/amba/pl080.h #define PL080_CONFIG_ERR_IRQ_MASK BIT(14) BIT 122 include/linux/amba/pl080.h #define PL080_CONFIG_ENABLE BIT(0) BIT 133 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_TC_MSK BIT(31) BIT 138 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_PROT3 BIT(21) BIT 139 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_PROT2 BIT(20) BIT 140 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_PROT1 BIT(19) BIT 143 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_ABT BIT(15) BIT 148 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_MODE BIT(7) BIT 154 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_SRC_SEL BIT(2) BIT 155 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_DST_SEL BIT(1) BIT 156 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_EN BIT(0) BIT 173 include/linux/amba/pl080.h #define FTDMAC020_CH_CFG_BUSY BIT(8) BIT 174 include/linux/amba/pl080.h #define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2) BIT 175 include/linux/amba/pl080.h #define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1) BIT 176 include/linux/amba/pl080.h #define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0) BIT 179 include/linux/amba/pl080.h #define FTDMAC020_LLI_TC_MSK BIT(28) BIT 188 include/linux/amba/pl080.h #define FTDMAC020_LLI_SRC_SEL BIT(17) BIT 189 include/linux/amba/pl080.h #define FTDMAC020_LLI_DST_SEL BIT(16) BIT 195 include/linux/amba/pl080.h #define FTDMAC020_CFG_BUSY BIT(8) BIT 196 include/linux/amba/pl080.h #define FTDMAC020_CFG_INT_ABT_MSK BIT(2) BIT 197 include/linux/amba/pl080.h #define FTDMAC020_CFG_INT_ERR_MSK BIT(1) BIT 198 include/linux/amba/pl080.h #define FTDMAC020_CFG_INT_TC_MSK BIT(0) BIT 930 include/linux/ata.h return id[ATA_ID_SATA_CAPABILITY_2] & BIT(6); BIT 935 include/linux/ata.h return id[ATA_ID_SATA_CAPABILITY_2] & BIT(5); BIT 940 include/linux/ata.h return id[ATA_ID_SATA_CAPABILITY] & BIT(12); BIT 122 include/linux/audit.h #define AUDIT_TTY_ENABLE BIT(0) BIT 123 include/linux/audit.h #define AUDIT_TTY_LOG_PASSWD BIT(1) BIT 75 include/linux/avf/virtchnl.h VIRTCHNL_LINK_SPEED_100MB = BIT(VIRTCHNL_LINK_SPEED_100MB_SHIFT), BIT 76 include/linux/avf/virtchnl.h VIRTCHNL_LINK_SPEED_1GB = BIT(VIRTCHNL_LINK_SPEED_1000MB_SHIFT), BIT 77 include/linux/avf/virtchnl.h VIRTCHNL_LINK_SPEED_10GB = BIT(VIRTCHNL_LINK_SPEED_10GB_SHIFT), BIT 78 include/linux/avf/virtchnl.h VIRTCHNL_LINK_SPEED_40GB = BIT(VIRTCHNL_LINK_SPEED_40GB_SHIFT), BIT 79 include/linux/avf/virtchnl.h VIRTCHNL_LINK_SPEED_20GB = BIT(VIRTCHNL_LINK_SPEED_20GB_SHIFT), BIT 80 include/linux/avf/virtchnl.h VIRTCHNL_LINK_SPEED_25GB = BIT(VIRTCHNL_LINK_SPEED_25GB_SHIFT), BIT 81 include/linux/avf/virtchnl.h VIRTCHNL_LINK_SPEED_2_5GB = BIT(VIRTCHNL_LINK_SPEED_2_5GB_SHIFT), BIT 82 include/linux/avf/virtchnl.h VIRTCHNL_LINK_SPEED_5GB = BIT(VIRTCHNL_LINK_SPEED_5GB_SHIFT), BIT 102 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */ BIT 103 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */ BIT 104 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ BIT 105 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ BIT 106 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ BIT 107 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ BIT 512 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ BIT 513 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ BIT 514 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */ BIT 515 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */ BIT 516 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */ BIT 517 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */ BIT 518 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */ BIT 519 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */ BIT 520 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */ BIT 521 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ BIT 522 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ BIT 523 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ BIT 524 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */ BIT 525 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ BIT 526 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ BIT 537 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_5357_EXTPA BIT(14) BIT 538 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15) BIT 539 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_5357_NFLASH BIT(16) BIT 540 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18) BIT 541 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19) BIT 543 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_LPLDO_PU BIT(0) BIT 544 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1) BIT 545 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_PMU_BG_PU BIT(2) BIT 546 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3) BIT 547 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_CBUCK_PFM_PU BIT(4) BIT 548 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_CLDO_PU BIT(5) BIT 549 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_LPLDO2_LVM BIT(6) BIT 550 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_WL_PMU_PU BIT(7) BIT 551 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_LNLDO_PU BIT(8) BIT 552 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_LDO3P3_PU BIT(9) BIT 553 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_OTP_PU BIT(10) BIT 554 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_XTAL_PU BIT(11) BIT 555 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_WL_PWRSW_PU BIT(12) BIT 556 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_LQ_AVAIL BIT(13) BIT 557 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_LOGIC_RET BIT(14) BIT 558 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_MEM_SLEEP BIT(15) BIT 559 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_MACPHY_RET BIT(16) BIT 560 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_WL_CORE_READY BIT(17) BIT 561 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_ILP_REQ BIT(18) BIT 562 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_ALP_AVAIL BIT(19) BIT 563 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_MISC_PWRSW_PU BIT(20) BIT 564 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21) BIT 565 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_RX_PWRSW_PU BIT(22) BIT 566 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_RADIO_PU BIT(23) BIT 567 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_VCO_LDO_PU BIT(24) BIT 568 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_AFE_LDO_PU BIT(25) BIT 569 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_RX_LDO_PU BIT(26) BIT 570 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_TX_LDO_PU BIT(27) BIT 571 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_HT_AVAIL BIT(28) BIT 572 include/linux/bcma/bcma_driver_chipcommon.h #define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29) BIT 382 include/linux/bio.h BIOSET_NEED_BVECS = BIT(0), BIT 383 include/linux/bio.h BIOSET_NEED_RESCUER = BIT(1), BIT 452 include/linux/bpf.h #define BPF_MAP_CAN_READ BIT(0) BIT 453 include/linux/bpf.h #define BPF_MAP_CAN_WRITE BIT(1) BIT 155 include/linux/brcmphy.h #define BCM_LED_MULTICOLOR_IN_PHASE BIT(8) BIT 14 include/linux/cacheinfo.h CACHE_TYPE_INST = BIT(0), BIT 15 include/linux/cacheinfo.h CACHE_TYPE_DATA = BIT(1), BIT 17 include/linux/cacheinfo.h CACHE_TYPE_UNIFIED = BIT(2), BIT 60 include/linux/cacheinfo.h #define CACHE_WRITE_THROUGH BIT(0) BIT 61 include/linux/cacheinfo.h #define CACHE_WRITE_BACK BIT(1) BIT 64 include/linux/cacheinfo.h #define CACHE_READ_ALLOCATE BIT(2) BIT 65 include/linux/cacheinfo.h #define CACHE_WRITE_ALLOCATE BIT(3) BIT 68 include/linux/cacheinfo.h #define CACHE_ID BIT(4) BIT 19 include/linux/clk-provider.h #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ BIT 20 include/linux/clk-provider.h #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ BIT 21 include/linux/clk-provider.h #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ BIT 22 include/linux/clk-provider.h #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ BIT 25 include/linux/clk-provider.h #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ BIT 26 include/linux/clk-provider.h #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ BIT 27 include/linux/clk-provider.h #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ BIT 28 include/linux/clk-provider.h #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ BIT 29 include/linux/clk-provider.h #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ BIT 30 include/linux/clk-provider.h #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ BIT 32 include/linux/clk-provider.h #define CLK_OPS_PARENT_ENABLE BIT(12) BIT 34 include/linux/clk-provider.h #define CLK_DUTY_CYCLE_PARENT BIT(13) BIT 384 include/linux/clk-provider.h #define CLK_GATE_SET_TO_DISABLE BIT(0) BIT 385 include/linux/clk-provider.h #define CLK_GATE_HIWORD_MASK BIT(1) BIT 386 include/linux/clk-provider.h #define CLK_GATE_BIG_ENDIAN BIT(2) BIT 459 include/linux/clk-provider.h #define CLK_DIVIDER_ONE_BASED BIT(0) BIT 460 include/linux/clk-provider.h #define CLK_DIVIDER_POWER_OF_TWO BIT(1) BIT 461 include/linux/clk-provider.h #define CLK_DIVIDER_ALLOW_ZERO BIT(2) BIT 462 include/linux/clk-provider.h #define CLK_DIVIDER_HIWORD_MASK BIT(3) BIT 463 include/linux/clk-provider.h #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) BIT 464 include/linux/clk-provider.h #define CLK_DIVIDER_READ_ONLY BIT(5) BIT 465 include/linux/clk-provider.h #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) BIT 466 include/linux/clk-provider.h #define CLK_DIVIDER_BIG_ENDIAN BIT(7) BIT 548 include/linux/clk-provider.h #define CLK_MUX_INDEX_ONE BIT(0) BIT 549 include/linux/clk-provider.h #define CLK_MUX_INDEX_BIT BIT(1) BIT 550 include/linux/clk-provider.h #define CLK_MUX_HIWORD_MASK BIT(2) BIT 551 include/linux/clk-provider.h #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ BIT 552 include/linux/clk-provider.h #define CLK_MUX_ROUND_CLOSEST BIT(4) BIT 553 include/linux/clk-provider.h #define CLK_MUX_BIG_ENDIAN BIT(5) BIT 659 include/linux/clk-provider.h #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) BIT 660 include/linux/clk-provider.h #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) BIT 708 include/linux/clk-provider.h #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) BIT 709 include/linux/clk-provider.h #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) BIT 710 include/linux/clk-provider.h #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) BIT 39 include/linux/clk.h #define PRE_RATE_CHANGE BIT(0) BIT 40 include/linux/clk.h #define POST_RATE_CHANGE BIT(1) BIT 41 include/linux/clk.h #define ABORT_RATE_CHANGE BIT(2) BIT 28 include/linux/clk/analogbits-wrpll-cln28hpc.h #define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT) BIT 30 include/linux/clk/analogbits-wrpll-cln28hpc.h #define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT) BIT 32 include/linux/clk/analogbits-wrpll-cln28hpc.h #define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT) BIT 34 include/linux/clk/analogbits-wrpll-cln28hpc.h #define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT) BIT 116 include/linux/clk/at91_pmc.h #define AT91_PMC_H32MXDIV BIT(24) BIT 159 include/linux/clk/at91_pmc.h #define AT91_PMC_FSTT(n) BIT(n) BIT 160 include/linux/clk/at91_pmc.h #define AT91_PMC_RTTAL BIT(16) BIT 161 include/linux/clk/at91_pmc.h #define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */ BIT 162 include/linux/clk/at91_pmc.h #define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */ BIT 163 include/linux/clk/at91_pmc.h #define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */ BIT 164 include/linux/clk/at91_pmc.h #define AT91_PMC_LPM BIT(20) /* Low-power Mode */ BIT 165 include/linux/clk/at91_pmc.h #define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */ BIT 166 include/linux/clk/at91_pmc.h #define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */ BIT 292 include/linux/clk/ti.h #define TI_CLK_DPLL_HAS_FREQSEL BIT(0) BIT 293 include/linux/clk/ti.h #define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1) BIT 294 include/linux/clk/ti.h #define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) BIT 295 include/linux/clk/ti.h #define TI_CLK_ERRATA_I810 BIT(3) BIT 296 include/linux/clk/ti.h #define TI_CLK_CLKCTRL_COMPAT BIT(4) BIT 297 include/linux/clk/ti.h #define TI_CLK_DEVICE_TYPE_GP BIT(5) BIT 245 include/linux/cper.h #define CPER_ARM_VALID_MPIDR BIT(0) BIT 246 include/linux/cper.h #define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1) BIT 247 include/linux/cper.h #define CPER_ARM_VALID_RUNNING_STATE BIT(2) BIT 248 include/linux/cper.h #define CPER_ARM_VALID_VENDOR_INFO BIT(3) BIT 250 include/linux/cper.h #define CPER_ARM_INFO_VALID_MULTI_ERR BIT(0) BIT 251 include/linux/cper.h #define CPER_ARM_INFO_VALID_FLAGS BIT(1) BIT 252 include/linux/cper.h #define CPER_ARM_INFO_VALID_ERR_INFO BIT(2) BIT 253 include/linux/cper.h #define CPER_ARM_INFO_VALID_VIRT_ADDR BIT(3) BIT 254 include/linux/cper.h #define CPER_ARM_INFO_VALID_PHYSICAL_ADDR BIT(4) BIT 256 include/linux/cper.h #define CPER_ARM_INFO_FLAGS_FIRST BIT(0) BIT 257 include/linux/cper.h #define CPER_ARM_INFO_FLAGS_LAST BIT(1) BIT 258 include/linux/cper.h #define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2) BIT 259 include/linux/cper.h #define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3) BIT 267 include/linux/cper.h #define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0) BIT 268 include/linux/cper.h #define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1) BIT 269 include/linux/cper.h #define CPER_ARM_ERR_VALID_LEVEL BIT(2) BIT 270 include/linux/cper.h #define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3) BIT 271 include/linux/cper.h #define CPER_ARM_ERR_VALID_CORRECTED BIT(4) BIT 272 include/linux/cper.h #define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5) BIT 273 include/linux/cper.h #define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6) BIT 274 include/linux/cper.h #define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7) BIT 275 include/linux/cper.h #define CPER_ARM_ERR_VALID_TIME_OUT BIT(8) BIT 276 include/linux/cper.h #define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9) BIT 277 include/linux/cper.h #define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10) BIT 278 include/linux/cper.h #define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11) BIT 374 include/linux/cpufreq.h #define CPUFREQ_STICKY BIT(0) BIT 377 include/linux/cpufreq.h #define CPUFREQ_CONST_LOOPS BIT(1) BIT 380 include/linux/cpufreq.h #define CPUFREQ_PM_NO_WARN BIT(2) BIT 388 include/linux/cpufreq.h #define CPUFREQ_HAVE_GOVERNOR_PER_POLICY BIT(3) BIT 395 include/linux/cpufreq.h #define CPUFREQ_ASYNC_NOTIFICATION BIT(4) BIT 404 include/linux/cpufreq.h #define CPUFREQ_NEED_INITIAL_FREQ_CHECK BIT(5) BIT 410 include/linux/cpufreq.h #define CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING BIT(6) BIT 416 include/linux/cpufreq.h #define CPUFREQ_IS_COOLING_DEV BIT(7) BIT 72 include/linux/cpuidle.h #define CPUIDLE_FLAG_POLLING BIT(0) /* polling state */ BIT 73 include/linux/cpuidle.h #define CPUIDLE_FLAG_COUPLED BIT(1) /* state applies to multiple cpus */ BIT 74 include/linux/cpuidle.h #define CPUIDLE_FLAG_TIMER_STOP BIT(2) /* timer is stopped on this state */ BIT 1084 include/linux/device.h #define DL_FLAG_STATELESS BIT(0) BIT 1085 include/linux/device.h #define DL_FLAG_AUTOREMOVE_CONSUMER BIT(1) BIT 1086 include/linux/device.h #define DL_FLAG_PM_RUNTIME BIT(2) BIT 1087 include/linux/device.h #define DL_FLAG_RPM_ACTIVE BIT(3) BIT 1088 include/linux/device.h #define DL_FLAG_AUTOREMOVE_SUPPLIER BIT(4) BIT 1089 include/linux/device.h #define DL_FLAG_AUTOPROBE_CONSUMER BIT(5) BIT 1090 include/linux/device.h #define DL_FLAG_MANAGED BIT(6) BIT 7 include/linux/dma/mxs-dma.h #define MXS_DMA_CTRL_WAIT4END BIT(31) BIT 8 include/linux/dma/mxs-dma.h #define MXS_DMA_CTRL_WAIT4RDY BIT(30) BIT 91 include/linux/edac.h #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) BIT 92 include/linux/edac.h #define DEV_FLAG_X1 BIT(DEV_X1) BIT 93 include/linux/edac.h #define DEV_FLAG_X2 BIT(DEV_X2) BIT 94 include/linux/edac.h #define DEV_FLAG_X4 BIT(DEV_X4) BIT 95 include/linux/edac.h #define DEV_FLAG_X8 BIT(DEV_X8) BIT 96 include/linux/edac.h #define DEV_FLAG_X16 BIT(DEV_X16) BIT 97 include/linux/edac.h #define DEV_FLAG_X32 BIT(DEV_X32) BIT 98 include/linux/edac.h #define DEV_FLAG_X64 BIT(DEV_X64) BIT 217 include/linux/edac.h #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) BIT 218 include/linux/edac.h #define MEM_FLAG_RESERVED BIT(MEM_RESERVED) BIT 219 include/linux/edac.h #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) BIT 220 include/linux/edac.h #define MEM_FLAG_FPM BIT(MEM_FPM) BIT 221 include/linux/edac.h #define MEM_FLAG_EDO BIT(MEM_EDO) BIT 222 include/linux/edac.h #define MEM_FLAG_BEDO BIT(MEM_BEDO) BIT 223 include/linux/edac.h #define MEM_FLAG_SDR BIT(MEM_SDR) BIT 224 include/linux/edac.h #define MEM_FLAG_RDR BIT(MEM_RDR) BIT 225 include/linux/edac.h #define MEM_FLAG_DDR BIT(MEM_DDR) BIT 226 include/linux/edac.h #define MEM_FLAG_RDDR BIT(MEM_RDDR) BIT 227 include/linux/edac.h #define MEM_FLAG_RMBS BIT(MEM_RMBS) BIT 228 include/linux/edac.h #define MEM_FLAG_DDR2 BIT(MEM_DDR2) BIT 229 include/linux/edac.h #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) BIT 230 include/linux/edac.h #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) BIT 231 include/linux/edac.h #define MEM_FLAG_XDR BIT(MEM_XDR) BIT 232 include/linux/edac.h #define MEM_FLAG_DDR3 BIT(MEM_DDR3) BIT 233 include/linux/edac.h #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) BIT 234 include/linux/edac.h #define MEM_FLAG_DDR4 BIT(MEM_DDR4) BIT 235 include/linux/edac.h #define MEM_FLAG_RDDR4 BIT(MEM_RDDR4) BIT 236 include/linux/edac.h #define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4) BIT 237 include/linux/edac.h #define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM) BIT 265 include/linux/edac.h #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) BIT 266 include/linux/edac.h #define EDAC_FLAG_NONE BIT(EDAC_NONE) BIT 267 include/linux/edac.h #define EDAC_FLAG_PARITY BIT(EDAC_PARITY) BIT 268 include/linux/edac.h #define EDAC_FLAG_EC BIT(EDAC_EC) BIT 269 include/linux/edac.h #define EDAC_FLAG_SECDED BIT(EDAC_SECDED) BIT 270 include/linux/edac.h #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) BIT 271 include/linux/edac.h #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) BIT 272 include/linux/edac.h #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) BIT 273 include/linux/edac.h #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) BIT 301 include/linux/edac.h #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) BIT 302 include/linux/edac.h #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) BIT 303 include/linux/edac.h #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) BIT 304 include/linux/edac.h #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) BIT 305 include/linux/edac.h #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) BIT 306 include/linux/edac.h #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) BIT 307 include/linux/edac.h #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) BIT 308 include/linux/edac.h #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) BIT 26 include/linux/extcon.h #define EXTCON_TYPE_USB BIT(0) /* USB connector */ BIT 27 include/linux/extcon.h #define EXTCON_TYPE_CHG BIT(1) /* Charger connector */ BIT 28 include/linux/extcon.h #define EXTCON_TYPE_JACK BIT(2) /* Jack connector */ BIT 29 include/linux/extcon.h #define EXTCON_TYPE_DISP BIT(3) /* Display connector */ BIT 30 include/linux/extcon.h #define EXTCON_TYPE_MISC BIT(4) /* Miscellaneous connector */ BIT 593 include/linux/filter.h #define BPF_RI_F_RF_NO_DIRECT BIT(0) /* no napi_direct on return_frame */ BIT 1108 include/linux/filter.h #define BPF_ANC BIT(15) BIT 56 include/linux/firmware/xlnx-zynqmp.h #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) BIT 71 include/linux/fpga/fpga-mgr.h #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) BIT 72 include/linux/fpga/fpga-mgr.h #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) BIT 73 include/linux/fpga/fpga-mgr.h #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) BIT 74 include/linux/fpga/fpga-mgr.h #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) BIT 75 include/linux/fpga/fpga-mgr.h #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4) BIT 140 include/linux/fpga/fpga-mgr.h #define FPGA_MGR_STATUS_OPERATION_ERR BIT(0) BIT 141 include/linux/fpga/fpga-mgr.h #define FPGA_MGR_STATUS_CRC_ERR BIT(1) BIT 142 include/linux/fpga/fpga-mgr.h #define FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR BIT(2) BIT 143 include/linux/fpga/fpga-mgr.h #define FPGA_MGR_STATUS_IP_PROTOCOL_ERR BIT(3) BIT 144 include/linux/fpga/fpga-mgr.h #define FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR BIT(4) BIT 38 include/linux/gpio/consumer.h #define GPIOD_FLAGS_BIT_DIR_SET BIT(0) BIT 39 include/linux/gpio/consumer.h #define GPIOD_FLAGS_BIT_DIR_OUT BIT(1) BIT 40 include/linux/gpio/consumer.h #define GPIOD_FLAGS_BIT_DIR_VAL BIT(2) BIT 41 include/linux/gpio/consumer.h #define GPIOD_FLAGS_BIT_OPEN_DRAIN BIT(3) BIT 42 include/linux/gpio/consumer.h #define GPIOD_FLAGS_BIT_NONEXCLUSIVE BIT(4) BIT 624 include/linux/gpio/consumer.h #define ACPI_GPIO_QUIRK_NO_IO_RESTRICTION BIT(0) BIT 631 include/linux/gpio/consumer.h #define ACPI_GPIO_QUIRK_ONLY_GPIOIO BIT(1) BIT 564 include/linux/gpio/driver.h #define BGPIOF_BIG_ENDIAN BIT(0) BIT 565 include/linux/gpio/driver.h #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ BIT 566 include/linux/gpio/driver.h #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ BIT 567 include/linux/gpio/driver.h #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) BIT 568 include/linux/gpio/driver.h #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ BIT 569 include/linux/gpio/driver.h #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ BIT 18 include/linux/greybus/connection.h #define GB_CONNECTION_FLAG_CSD BIT(0) BIT 19 include/linux/greybus/connection.h #define GB_CONNECTION_FLAG_NO_FLOWCTRL BIT(1) BIT 20 include/linux/greybus/connection.h #define GB_CONNECTION_FLAG_OFFLOADED BIT(2) BIT 21 include/linux/greybus/connection.h #define GB_CONNECTION_FLAG_CDSI1 BIT(3) BIT 22 include/linux/greybus/connection.h #define GB_CONNECTION_FLAG_CONTROL BIT(4) BIT 23 include/linux/greybus/connection.h #define GB_CONNECTION_FLAG_HIGH_PRIO BIT(5) BIT 23 include/linux/greybus/greybus_id.h #define GREYBUS_ID_MATCH_VENDOR BIT(0) BIT 24 include/linux/greybus/greybus_id.h #define GREYBUS_ID_MATCH_PRODUCT BIT(1) BIT 25 include/linux/greybus/greybus_id.h #define GREYBUS_ID_MATCH_CLASS BIT(2) BIT 92 include/linux/greybus/greybus_manifest.h GREYBUS_INTERFACE_FEATURE_TIMESYNC = BIT(0), BIT 849 include/linux/greybus/greybus_protocols.h #define GB_SPI_FLAG_HALF_DUPLEX BIT(0) /* can't do full duplex */ BIT 850 include/linux/greybus/greybus_protocols.h #define GB_SPI_FLAG_NO_RX BIT(1) /* can't do buffer read */ BIT 851 include/linux/greybus/greybus_protocols.h #define GB_SPI_FLAG_NO_TX BIT(2) /* can't do buffer write */ BIT 1827 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_S8 BIT(0) BIT 1828 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_U8 BIT(1) BIT 1829 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_S16_LE BIT(2) BIT 1830 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_S16_BE BIT(3) BIT 1831 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_U16_LE BIT(4) BIT 1832 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_U16_BE BIT(5) BIT 1833 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_S24_LE BIT(6) BIT 1834 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_S24_BE BIT(7) BIT 1835 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_U24_LE BIT(8) BIT 1836 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_U24_BE BIT(9) BIT 1837 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_S32_LE BIT(10) BIT 1838 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_S32_BE BIT(11) BIT 1839 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_U32_LE BIT(12) BIT 1840 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_FMT_U32_BE BIT(13) BIT 1843 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_5512 BIT(0) BIT 1844 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_8000 BIT(1) BIT 1845 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_11025 BIT(2) BIT 1846 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_16000 BIT(3) BIT 1847 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_22050 BIT(4) BIT 1848 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_32000 BIT(5) BIT 1849 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_44100 BIT(6) BIT 1850 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_48000 BIT(7) BIT 1851 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_64000 BIT(8) BIT 1852 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_88200 BIT(9) BIT 1853 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_96000 BIT(10) BIT 1854 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_176400 BIT(11) BIT 1855 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_PCM_RATE_192000 BIT(12) BIT 1860 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_CTL_ELEM_ACCESS_READ BIT(0) BIT 1861 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_CTL_ELEM_ACCESS_WRITE BIT(1) BIT 1879 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_ACCESS_READ BIT(0) BIT 1880 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_ACCESS_WRITE BIT(1) BIT 1881 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_ACCESS_VOLATILE BIT(2) BIT 1882 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_ACCESS_TIMESTAMP BIT(3) BIT 1883 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_ACCESS_TLV_READ BIT(4) BIT 1884 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_ACCESS_TLV_WRITE BIT(5) BIT 1885 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_ACCESS_TLV_COMMAND BIT(6) BIT 1886 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_ACCESS_INACTIVE BIT(7) BIT 1887 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_ACCESS_LOCK BIT(8) BIT 1888 include/linux/greybus/greybus_protocols.h #define GB_AUDIO_ACCESS_OWNER BIT(9) BIT 23 include/linux/greybus/interface.h #define GB_INTERFACE_QUIRK_NO_CPORT_FEATURES BIT(0) BIT 24 include/linux/greybus/interface.h #define GB_INTERFACE_QUIRK_NO_INIT_STATUS BIT(1) BIT 25 include/linux/greybus/interface.h #define GB_INTERFACE_QUIRK_NO_GMP_IDS BIT(2) BIT 26 include/linux/greybus/interface.h #define GB_INTERFACE_QUIRK_FORCED_DISABLE BIT(3) BIT 27 include/linux/greybus/interface.h #define GB_INTERFACE_QUIRK_LEGACY_MODE_SWITCH BIT(4) BIT 28 include/linux/greybus/interface.h #define GB_INTERFACE_QUIRK_NO_BUNDLE_ACTIVATE BIT(5) BIT 29 include/linux/greybus/interface.h #define GB_INTERFACE_QUIRK_NO_PM BIT(6) BIT 64 include/linux/greybus/operation.h #define GB_OPERATION_FLAG_INCOMING BIT(0) BIT 65 include/linux/greybus/operation.h #define GB_OPERATION_FLAG_UNIDIRECTIONAL BIT(1) BIT 66 include/linux/greybus/operation.h #define GB_OPERATION_FLAG_SHORT_RESPONSE BIT(2) BIT 67 include/linux/greybus/operation.h #define GB_OPERATION_FLAG_CORE BIT(3) BIT 17 include/linux/greybus/svc.h #define GB_SVC_CPORT_FLAG_E2EFC BIT(0) BIT 18 include/linux/greybus/svc.h #define GB_SVC_CPORT_FLAG_CSD_N BIT(1) BIT 19 include/linux/greybus/svc.h #define GB_SVC_CPORT_FLAG_CSV_N BIT(2) BIT 314 include/linux/hid.h #define HID_CONNECT_HIDINPUT BIT(0) BIT 315 include/linux/hid.h #define HID_CONNECT_HIDINPUT_FORCE BIT(1) BIT 316 include/linux/hid.h #define HID_CONNECT_HIDRAW BIT(2) BIT 317 include/linux/hid.h #define HID_CONNECT_HIDDEV BIT(3) BIT 318 include/linux/hid.h #define HID_CONNECT_HIDDEV_FORCE BIT(4) BIT 319 include/linux/hid.h #define HID_CONNECT_FF BIT(5) BIT 320 include/linux/hid.h #define HID_CONNECT_DRIVER BIT(6) BIT 333 include/linux/hid.h #define HID_QUIRK_INVERT BIT(0) BIT 334 include/linux/hid.h #define HID_QUIRK_NOTOUCH BIT(1) BIT 335 include/linux/hid.h #define HID_QUIRK_IGNORE BIT(2) BIT 336 include/linux/hid.h #define HID_QUIRK_NOGET BIT(3) BIT 337 include/linux/hid.h #define HID_QUIRK_HIDDEV_FORCE BIT(4) BIT 338 include/linux/hid.h #define HID_QUIRK_BADPAD BIT(5) BIT 339 include/linux/hid.h #define HID_QUIRK_MULTI_INPUT BIT(6) BIT 340 include/linux/hid.h #define HID_QUIRK_HIDINPUT_FORCE BIT(7) BIT 343 include/linux/hid.h #define HID_QUIRK_ALWAYS_POLL BIT(10) BIT 344 include/linux/hid.h #define HID_QUIRK_INPUT_PER_APP BIT(11) BIT 345 include/linux/hid.h #define HID_QUIRK_SKIP_OUTPUT_REPORTS BIT(16) BIT 346 include/linux/hid.h #define HID_QUIRK_SKIP_OUTPUT_REPORT_ID BIT(17) BIT 347 include/linux/hid.h #define HID_QUIRK_NO_OUTPUT_REPORTS_ON_INTR_EP BIT(18) BIT 348 include/linux/hid.h #define HID_QUIRK_HAVE_SPECIAL_DRIVER BIT(19) BIT 349 include/linux/hid.h #define HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE BIT(20) BIT 350 include/linux/hid.h #define HID_QUIRK_FULLSPEED_INTERVAL BIT(28) BIT 351 include/linux/hid.h #define HID_QUIRK_NO_INIT_REPORTS BIT(29) BIT 352 include/linux/hid.h #define HID_QUIRK_NO_IGNORE BIT(30) BIT 353 include/linux/hid.h #define HID_QUIRK_NO_INPUT_SYNC BIT(31) BIT 510 include/linux/hid.h #define HID_CLAIMED_INPUT BIT(0) BIT 511 include/linux/hid.h #define HID_CLAIMED_HIDDEV BIT(1) BIT 512 include/linux/hid.h #define HID_CLAIMED_HIDRAW BIT(2) BIT 513 include/linux/hid.h #define HID_CLAIMED_DRIVER BIT(3) BIT 515 include/linux/hid.h #define HID_STAT_ADDED BIT(0) BIT 516 include/linux/hid.h #define HID_STAT_PARSED BIT(1) BIT 517 include/linux/hid.h #define HID_STAT_DUP_DETECTED BIT(2) BIT 518 include/linux/hid.h #define HID_STAT_REPROBED BIT(3) BIT 639 include/linux/hid.h #define HID_SCAN_FLAG_MT_WIN_8 BIT(0) BIT 640 include/linux/hid.h #define HID_SCAN_FLAG_VENDOR_SPECIFIC BIT(1) BIT 641 include/linux/hid.h #define HID_SCAN_FLAG_GD_POINTER BIT(2) BIT 48 include/linux/hwmon.h #define HWMON_C_TEMP_RESET_HISTORY BIT(hwmon_chip_temp_reset_history) BIT 49 include/linux/hwmon.h #define HWMON_C_IN_RESET_HISTORY BIT(hwmon_chip_in_reset_history) BIT 50 include/linux/hwmon.h #define HWMON_C_CURR_RESET_HISTORY BIT(hwmon_chip_curr_reset_history) BIT 51 include/linux/hwmon.h #define HWMON_C_POWER_RESET_HISTORY BIT(hwmon_chip_power_reset_history) BIT 52 include/linux/hwmon.h #define HWMON_C_REGISTER_TZ BIT(hwmon_chip_register_tz) BIT 53 include/linux/hwmon.h #define HWMON_C_UPDATE_INTERVAL BIT(hwmon_chip_update_interval) BIT 54 include/linux/hwmon.h #define HWMON_C_ALARMS BIT(hwmon_chip_alarms) BIT 55 include/linux/hwmon.h #define HWMON_C_SAMPLES BIT(hwmon_chip_samples) BIT 56 include/linux/hwmon.h #define HWMON_C_CURR_SAMPLES BIT(hwmon_chip_curr_samples) BIT 57 include/linux/hwmon.h #define HWMON_C_IN_SAMPLES BIT(hwmon_chip_in_samples) BIT 58 include/linux/hwmon.h #define HWMON_C_POWER_SAMPLES BIT(hwmon_chip_power_samples) BIT 59 include/linux/hwmon.h #define HWMON_C_TEMP_SAMPLES BIT(hwmon_chip_temp_samples) BIT 88 include/linux/hwmon.h #define HWMON_T_INPUT BIT(hwmon_temp_input) BIT 89 include/linux/hwmon.h #define HWMON_T_TYPE BIT(hwmon_temp_type) BIT 90 include/linux/hwmon.h #define HWMON_T_LCRIT BIT(hwmon_temp_lcrit) BIT 91 include/linux/hwmon.h #define HWMON_T_LCRIT_HYST BIT(hwmon_temp_lcrit_hyst) BIT 92 include/linux/hwmon.h #define HWMON_T_MIN BIT(hwmon_temp_min) BIT 93 include/linux/hwmon.h #define HWMON_T_MIN_HYST BIT(hwmon_temp_min_hyst) BIT 94 include/linux/hwmon.h #define HWMON_T_MAX BIT(hwmon_temp_max) BIT 95 include/linux/hwmon.h #define HWMON_T_MAX_HYST BIT(hwmon_temp_max_hyst) BIT 96 include/linux/hwmon.h #define HWMON_T_CRIT BIT(hwmon_temp_crit) BIT 97 include/linux/hwmon.h #define HWMON_T_CRIT_HYST BIT(hwmon_temp_crit_hyst) BIT 98 include/linux/hwmon.h #define HWMON_T_EMERGENCY BIT(hwmon_temp_emergency) BIT 99 include/linux/hwmon.h #define HWMON_T_EMERGENCY_HYST BIT(hwmon_temp_emergency_hyst) BIT 100 include/linux/hwmon.h #define HWMON_T_ALARM BIT(hwmon_temp_alarm) BIT 101 include/linux/hwmon.h #define HWMON_T_MIN_ALARM BIT(hwmon_temp_min_alarm) BIT 102 include/linux/hwmon.h #define HWMON_T_MAX_ALARM BIT(hwmon_temp_max_alarm) BIT 103 include/linux/hwmon.h #define HWMON_T_CRIT_ALARM BIT(hwmon_temp_crit_alarm) BIT 104 include/linux/hwmon.h #define HWMON_T_LCRIT_ALARM BIT(hwmon_temp_lcrit_alarm) BIT 105 include/linux/hwmon.h #define HWMON_T_EMERGENCY_ALARM BIT(hwmon_temp_emergency_alarm) BIT 106 include/linux/hwmon.h #define HWMON_T_FAULT BIT(hwmon_temp_fault) BIT 107 include/linux/hwmon.h #define HWMON_T_OFFSET BIT(hwmon_temp_offset) BIT 108 include/linux/hwmon.h #define HWMON_T_LABEL BIT(hwmon_temp_label) BIT 109 include/linux/hwmon.h #define HWMON_T_LOWEST BIT(hwmon_temp_lowest) BIT 110 include/linux/hwmon.h #define HWMON_T_HIGHEST BIT(hwmon_temp_highest) BIT 111 include/linux/hwmon.h #define HWMON_T_RESET_HISTORY BIT(hwmon_temp_reset_history) BIT 132 include/linux/hwmon.h #define HWMON_I_INPUT BIT(hwmon_in_input) BIT 133 include/linux/hwmon.h #define HWMON_I_MIN BIT(hwmon_in_min) BIT 134 include/linux/hwmon.h #define HWMON_I_MAX BIT(hwmon_in_max) BIT 135 include/linux/hwmon.h #define HWMON_I_LCRIT BIT(hwmon_in_lcrit) BIT 136 include/linux/hwmon.h #define HWMON_I_CRIT BIT(hwmon_in_crit) BIT 137 include/linux/hwmon.h #define HWMON_I_AVERAGE BIT(hwmon_in_average) BIT 138 include/linux/hwmon.h #define HWMON_I_LOWEST BIT(hwmon_in_lowest) BIT 139 include/linux/hwmon.h #define HWMON_I_HIGHEST BIT(hwmon_in_highest) BIT 140 include/linux/hwmon.h #define HWMON_I_RESET_HISTORY BIT(hwmon_in_reset_history) BIT 141 include/linux/hwmon.h #define HWMON_I_LABEL BIT(hwmon_in_label) BIT 142 include/linux/hwmon.h #define HWMON_I_ALARM BIT(hwmon_in_alarm) BIT 143 include/linux/hwmon.h #define HWMON_I_MIN_ALARM BIT(hwmon_in_min_alarm) BIT 144 include/linux/hwmon.h #define HWMON_I_MAX_ALARM BIT(hwmon_in_max_alarm) BIT 145 include/linux/hwmon.h #define HWMON_I_LCRIT_ALARM BIT(hwmon_in_lcrit_alarm) BIT 146 include/linux/hwmon.h #define HWMON_I_CRIT_ALARM BIT(hwmon_in_crit_alarm) BIT 147 include/linux/hwmon.h #define HWMON_I_ENABLE BIT(hwmon_in_enable) BIT 167 include/linux/hwmon.h #define HWMON_C_INPUT BIT(hwmon_curr_input) BIT 168 include/linux/hwmon.h #define HWMON_C_MIN BIT(hwmon_curr_min) BIT 169 include/linux/hwmon.h #define HWMON_C_MAX BIT(hwmon_curr_max) BIT 170 include/linux/hwmon.h #define HWMON_C_LCRIT BIT(hwmon_curr_lcrit) BIT 171 include/linux/hwmon.h #define HWMON_C_CRIT BIT(hwmon_curr_crit) BIT 172 include/linux/hwmon.h #define HWMON_C_AVERAGE BIT(hwmon_curr_average) BIT 173 include/linux/hwmon.h #define HWMON_C_LOWEST BIT(hwmon_curr_lowest) BIT 174 include/linux/hwmon.h #define HWMON_C_HIGHEST BIT(hwmon_curr_highest) BIT 175 include/linux/hwmon.h #define HWMON_C_RESET_HISTORY BIT(hwmon_curr_reset_history) BIT 176 include/linux/hwmon.h #define HWMON_C_LABEL BIT(hwmon_curr_label) BIT 177 include/linux/hwmon.h #define HWMON_C_ALARM BIT(hwmon_curr_alarm) BIT 178 include/linux/hwmon.h #define HWMON_C_MIN_ALARM BIT(hwmon_curr_min_alarm) BIT 179 include/linux/hwmon.h #define HWMON_C_MAX_ALARM BIT(hwmon_curr_max_alarm) BIT 180 include/linux/hwmon.h #define HWMON_C_LCRIT_ALARM BIT(hwmon_curr_lcrit_alarm) BIT 181 include/linux/hwmon.h #define HWMON_C_CRIT_ALARM BIT(hwmon_curr_crit_alarm) BIT 214 include/linux/hwmon.h #define HWMON_P_AVERAGE BIT(hwmon_power_average) BIT 215 include/linux/hwmon.h #define HWMON_P_AVERAGE_INTERVAL BIT(hwmon_power_average_interval) BIT 216 include/linux/hwmon.h #define HWMON_P_AVERAGE_INTERVAL_MAX BIT(hwmon_power_average_interval_max) BIT 217 include/linux/hwmon.h #define HWMON_P_AVERAGE_INTERVAL_MIN BIT(hwmon_power_average_interval_min) BIT 218 include/linux/hwmon.h #define HWMON_P_AVERAGE_HIGHEST BIT(hwmon_power_average_highest) BIT 219 include/linux/hwmon.h #define HWMON_P_AVERAGE_LOWEST BIT(hwmon_power_average_lowest) BIT 220 include/linux/hwmon.h #define HWMON_P_AVERAGE_MAX BIT(hwmon_power_average_max) BIT 221 include/linux/hwmon.h #define HWMON_P_AVERAGE_MIN BIT(hwmon_power_average_min) BIT 222 include/linux/hwmon.h #define HWMON_P_INPUT BIT(hwmon_power_input) BIT 223 include/linux/hwmon.h #define HWMON_P_INPUT_HIGHEST BIT(hwmon_power_input_highest) BIT 224 include/linux/hwmon.h #define HWMON_P_INPUT_LOWEST BIT(hwmon_power_input_lowest) BIT 225 include/linux/hwmon.h #define HWMON_P_RESET_HISTORY BIT(hwmon_power_reset_history) BIT 226 include/linux/hwmon.h #define HWMON_P_ACCURACY BIT(hwmon_power_accuracy) BIT 227 include/linux/hwmon.h #define HWMON_P_CAP BIT(hwmon_power_cap) BIT 228 include/linux/hwmon.h #define HWMON_P_CAP_HYST BIT(hwmon_power_cap_hyst) BIT 229 include/linux/hwmon.h #define HWMON_P_CAP_MAX BIT(hwmon_power_cap_max) BIT 230 include/linux/hwmon.h #define HWMON_P_CAP_MIN BIT(hwmon_power_cap_min) BIT 231 include/linux/hwmon.h #define HWMON_P_MIN BIT(hwmon_power_min) BIT 232 include/linux/hwmon.h #define HWMON_P_MAX BIT(hwmon_power_max) BIT 233 include/linux/hwmon.h #define HWMON_P_LCRIT BIT(hwmon_power_lcrit) BIT 234 include/linux/hwmon.h #define HWMON_P_CRIT BIT(hwmon_power_crit) BIT 235 include/linux/hwmon.h #define HWMON_P_LABEL BIT(hwmon_power_label) BIT 236 include/linux/hwmon.h #define HWMON_P_ALARM BIT(hwmon_power_alarm) BIT 237 include/linux/hwmon.h #define HWMON_P_CAP_ALARM BIT(hwmon_power_cap_alarm) BIT 238 include/linux/hwmon.h #define HWMON_P_MIN_ALARM BIT(hwmon_power_min_alarm) BIT 239 include/linux/hwmon.h #define HWMON_P_MAX_ALARM BIT(hwmon_power_max_alarm) BIT 240 include/linux/hwmon.h #define HWMON_P_LCRIT_ALARM BIT(hwmon_power_lcrit_alarm) BIT 241 include/linux/hwmon.h #define HWMON_P_CRIT_ALARM BIT(hwmon_power_crit_alarm) BIT 248 include/linux/hwmon.h #define HWMON_E_INPUT BIT(hwmon_energy_input) BIT 249 include/linux/hwmon.h #define HWMON_E_LABEL BIT(hwmon_energy_label) BIT 262 include/linux/hwmon.h #define HWMON_H_INPUT BIT(hwmon_humidity_input) BIT 263 include/linux/hwmon.h #define HWMON_H_LABEL BIT(hwmon_humidity_label) BIT 264 include/linux/hwmon.h #define HWMON_H_MIN BIT(hwmon_humidity_min) BIT 265 include/linux/hwmon.h #define HWMON_H_MIN_HYST BIT(hwmon_humidity_min_hyst) BIT 266 include/linux/hwmon.h #define HWMON_H_MAX BIT(hwmon_humidity_max) BIT 267 include/linux/hwmon.h #define HWMON_H_MAX_HYST BIT(hwmon_humidity_max_hyst) BIT 268 include/linux/hwmon.h #define HWMON_H_ALARM BIT(hwmon_humidity_alarm) BIT 269 include/linux/hwmon.h #define HWMON_H_FAULT BIT(hwmon_humidity_fault) BIT 285 include/linux/hwmon.h #define HWMON_F_INPUT BIT(hwmon_fan_input) BIT 286 include/linux/hwmon.h #define HWMON_F_LABEL BIT(hwmon_fan_label) BIT 287 include/linux/hwmon.h #define HWMON_F_MIN BIT(hwmon_fan_min) BIT 288 include/linux/hwmon.h #define HWMON_F_MAX BIT(hwmon_fan_max) BIT 289 include/linux/hwmon.h #define HWMON_F_DIV BIT(hwmon_fan_div) BIT 290 include/linux/hwmon.h #define HWMON_F_PULSES BIT(hwmon_fan_pulses) BIT 291 include/linux/hwmon.h #define HWMON_F_TARGET BIT(hwmon_fan_target) BIT 292 include/linux/hwmon.h #define HWMON_F_ALARM BIT(hwmon_fan_alarm) BIT 293 include/linux/hwmon.h #define HWMON_F_MIN_ALARM BIT(hwmon_fan_min_alarm) BIT 294 include/linux/hwmon.h #define HWMON_F_MAX_ALARM BIT(hwmon_fan_max_alarm) BIT 295 include/linux/hwmon.h #define HWMON_F_FAULT BIT(hwmon_fan_fault) BIT 304 include/linux/hwmon.h #define HWMON_PWM_INPUT BIT(hwmon_pwm_input) BIT 305 include/linux/hwmon.h #define HWMON_PWM_ENABLE BIT(hwmon_pwm_enable) BIT 306 include/linux/hwmon.h #define HWMON_PWM_MODE BIT(hwmon_pwm_mode) BIT 307 include/linux/hwmon.h #define HWMON_PWM_FREQ BIT(hwmon_pwm_freq) BIT 42 include/linux/i2c-mux.h #define I2C_MUX_LOCKED BIT(0) BIT 43 include/linux/i2c-mux.h #define I2C_MUX_ARBITRATOR BIT(1) BIT 44 include/linux/i2c-mux.h #define I2C_MUX_GATE BIT(2) BIT 664 include/linux/i2c.h #define I2C_AQ_COMB BIT(0) BIT 666 include/linux/i2c.h #define I2C_AQ_COMB_WRITE_FIRST BIT(1) BIT 668 include/linux/i2c.h #define I2C_AQ_COMB_READ_SECOND BIT(2) BIT 670 include/linux/i2c.h #define I2C_AQ_COMB_SAME_ADDR BIT(3) BIT 675 include/linux/i2c.h #define I2C_AQ_NO_CLK_STRETCH BIT(4) BIT 677 include/linux/i2c.h #define I2C_AQ_NO_ZERO_LEN_READ BIT(5) BIT 678 include/linux/i2c.h #define I2C_AQ_NO_ZERO_LEN_WRITE BIT(6) BIT 743 include/linux/i2c.h #define I2C_LOCK_ROOT_ADAPTER BIT(0) BIT 744 include/linux/i2c.h #define I2C_LOCK_SEGMENT BIT(1) BIT 15 include/linux/i3c/ccc.h #define I3C_CCC_DIRECT BIT(7) BIT 51 include/linux/i3c/ccc.h #define I3C_CCC_EVENT_SIR BIT(0) BIT 52 include/linux/i3c/ccc.h #define I3C_CCC_EVENT_MR BIT(1) BIT 53 include/linux/i3c/ccc.h #define I3C_CCC_EVENT_HJ BIT(3) BIT 201 include/linux/i3c/ccc.h #define I3C_CCC_STATUS_PROTOCOL_ERROR BIT(5) BIT 285 include/linux/i3c/ccc.h #define I3C_CCC_HDR_MODE(mode) BIT(mode) BIT 324 include/linux/i3c/ccc.h #define I3C_CCC_GETXTIME_SYNC_MODE BIT(0) BIT 325 include/linux/i3c/ccc.h #define I3C_CCC_GETXTIME_ASYNC_MODE(x) BIT((x) + 1) BIT 326 include/linux/i3c/ccc.h #define I3C_CCC_GETXTIME_OVERFLOW BIT(7) BIT 89 include/linux/i3c/device.h #define I3C_BCR_HDR_CAP BIT(5) BIT 90 include/linux/i3c/device.h #define I3C_BCR_BRIDGE BIT(4) BIT 91 include/linux/i3c/device.h #define I3C_BCR_OFFLINE_CAP BIT(3) BIT 92 include/linux/i3c/device.h #define I3C_BCR_IBI_PAYLOAD BIT(2) BIT 93 include/linux/i3c/device.h #define I3C_BCR_IBI_REQ_CAP BIT(1) BIT 94 include/linux/i3c/device.h #define I3C_BCR_MAX_DATA_SPEED_LIM BIT(0) BIT 49 include/linux/i3c/master.h #define I3C_LVR_I2C_FM_MODE BIT(4) BIT 256 include/linux/ide.h IDE_SFLAG_SET_GEOMETRY = BIT(0), BIT 257 include/linux/ide.h IDE_SFLAG_RECALIBRATE = BIT(1), BIT 258 include/linux/ide.h IDE_SFLAG_SET_MULTMODE = BIT(2), BIT 270 include/linux/ide.h IDE_VALID_ERROR = BIT(1), BIT 272 include/linux/ide.h IDE_VALID_NSECT = BIT(2), BIT 273 include/linux/ide.h IDE_VALID_LBAL = BIT(3), BIT 274 include/linux/ide.h IDE_VALID_LBAM = BIT(4), BIT 275 include/linux/ide.h IDE_VALID_LBAH = BIT(5), BIT 276 include/linux/ide.h IDE_VALID_DEVICE = BIT(6), BIT 292 include/linux/ide.h IDE_TFLAG_LBA48 = BIT(0), BIT 293 include/linux/ide.h IDE_TFLAG_WRITE = BIT(1), BIT 294 include/linux/ide.h IDE_TFLAG_CUSTOM_HANDLER = BIT(2), BIT 295 include/linux/ide.h IDE_TFLAG_DMA_PIO_FALLBACK = BIT(3), BIT 297 include/linux/ide.h IDE_TFLAG_IO_16BIT = BIT(4), BIT 299 include/linux/ide.h IDE_TFLAG_DYN = BIT(5), BIT 300 include/linux/ide.h IDE_TFLAG_FS = BIT(6), BIT 301 include/linux/ide.h IDE_TFLAG_MULTI_PIO = BIT(7), BIT 302 include/linux/ide.h IDE_TFLAG_SET_XFER = BIT(8), BIT 306 include/linux/ide.h IDE_FTFLAG_FLAGGED = BIT(0), BIT 307 include/linux/ide.h IDE_FTFLAG_SET_IN_FLAGS = BIT(1), BIT 308 include/linux/ide.h IDE_FTFLAG_OUT_DATA = BIT(2), BIT 309 include/linux/ide.h IDE_FTFLAG_IN_DATA = BIT(3), BIT 360 include/linux/ide.h PC_FLAG_ABORT = BIT(0), BIT 361 include/linux/ide.h PC_FLAG_SUPPRESS_ERROR = BIT(1), BIT 362 include/linux/ide.h PC_FLAG_WAIT_FOR_DSC = BIT(2), BIT 363 include/linux/ide.h PC_FLAG_DMA_OK = BIT(3), BIT 364 include/linux/ide.h PC_FLAG_DMA_IN_PROGRESS = BIT(4), BIT 365 include/linux/ide.h PC_FLAG_DMA_ERROR = BIT(5), BIT 366 include/linux/ide.h PC_FLAG_WRITING = BIT(6), BIT 420 include/linux/ide.h IDE_AFLAG_DRQ_INTERRUPT = BIT(0), BIT 424 include/linux/ide.h IDE_AFLAG_NO_EJECT = BIT(1), BIT 426 include/linux/ide.h IDE_AFLAG_PRE_ATAPI12 = BIT(2), BIT 428 include/linux/ide.h IDE_AFLAG_TOCADDR_AS_BCD = BIT(3), BIT 430 include/linux/ide.h IDE_AFLAG_TOCTRACKS_AS_BCD = BIT(4), BIT 432 include/linux/ide.h IDE_AFLAG_TOC_VALID = BIT(6), BIT 434 include/linux/ide.h IDE_AFLAG_DOOR_LOCKED = BIT(7), BIT 436 include/linux/ide.h IDE_AFLAG_NO_SPEED_SELECT = BIT(8), BIT 437 include/linux/ide.h IDE_AFLAG_VERTOS_300_SSD = BIT(9), BIT 438 include/linux/ide.h IDE_AFLAG_VERTOS_600_ESD = BIT(10), BIT 439 include/linux/ide.h IDE_AFLAG_SANYO_3CD = BIT(11), BIT 440 include/linux/ide.h IDE_AFLAG_FULL_CAPS_PAGE = BIT(12), BIT 441 include/linux/ide.h IDE_AFLAG_PLAY_AUDIO_OK = BIT(13), BIT 442 include/linux/ide.h IDE_AFLAG_LE_SPEED_FIELDS = BIT(14), BIT 446 include/linux/ide.h IDE_AFLAG_CLIK_DRIVE = BIT(15), BIT 448 include/linux/ide.h IDE_AFLAG_ZIP_DRIVE = BIT(16), BIT 450 include/linux/ide.h IDE_AFLAG_SRFP = BIT(17), BIT 453 include/linux/ide.h IDE_AFLAG_IGNORE_DSC = BIT(18), BIT 455 include/linux/ide.h IDE_AFLAG_ADDRESS_VALID = BIT(19), BIT 457 include/linux/ide.h IDE_AFLAG_BUSY = BIT(20), BIT 459 include/linux/ide.h IDE_AFLAG_DETECT_BS = BIT(21), BIT 461 include/linux/ide.h IDE_AFLAG_FILEMARK = BIT(22), BIT 463 include/linux/ide.h IDE_AFLAG_MEDIUM_PRESENT = BIT(23), BIT 465 include/linux/ide.h IDE_AFLAG_NO_AUTOCLOSE = BIT(24), BIT 471 include/linux/ide.h IDE_DFLAG_KEEP_SETTINGS = BIT(0), BIT 473 include/linux/ide.h IDE_DFLAG_USING_DMA = BIT(1), BIT 475 include/linux/ide.h IDE_DFLAG_UNMASK = BIT(2), BIT 477 include/linux/ide.h IDE_DFLAG_NOFLUSH = BIT(3), BIT 479 include/linux/ide.h IDE_DFLAG_DSC_OVERLAP = BIT(4), BIT 481 include/linux/ide.h IDE_DFLAG_NICE1 = BIT(5), BIT 483 include/linux/ide.h IDE_DFLAG_PRESENT = BIT(6), BIT 485 include/linux/ide.h IDE_DFLAG_NOHPA = BIT(7), BIT 487 include/linux/ide.h IDE_DFLAG_ID_READ = BIT(8), BIT 488 include/linux/ide.h IDE_DFLAG_NOPROBE = BIT(9), BIT 490 include/linux/ide.h IDE_DFLAG_REMOVABLE = BIT(10), BIT 492 include/linux/ide.h IDE_DFLAG_ATTACH = BIT(11), BIT 493 include/linux/ide.h IDE_DFLAG_FORCED_GEOM = BIT(12), BIT 495 include/linux/ide.h IDE_DFLAG_NO_UNMASK = BIT(13), BIT 497 include/linux/ide.h IDE_DFLAG_NO_IO_32BIT = BIT(14), BIT 499 include/linux/ide.h IDE_DFLAG_DOORLOCKING = BIT(15), BIT 501 include/linux/ide.h IDE_DFLAG_NODMA = BIT(16), BIT 503 include/linux/ide.h IDE_DFLAG_BLOCKED = BIT(17), BIT 505 include/linux/ide.h IDE_DFLAG_SLEEPING = BIT(18), BIT 506 include/linux/ide.h IDE_DFLAG_POST_RESET = BIT(19), BIT 507 include/linux/ide.h IDE_DFLAG_UDMA33_WARNED = BIT(20), BIT 508 include/linux/ide.h IDE_DFLAG_LBA48 = BIT(21), BIT 510 include/linux/ide.h IDE_DFLAG_WCACHE = BIT(22), BIT 512 include/linux/ide.h IDE_DFLAG_NOWERR = BIT(23), BIT 514 include/linux/ide.h IDE_DFLAG_DMA_PIO_RETRY = BIT(24), BIT 515 include/linux/ide.h IDE_DFLAG_LBA = BIT(25), BIT 517 include/linux/ide.h IDE_DFLAG_NO_UNLOAD = BIT(26), BIT 519 include/linux/ide.h IDE_DFLAG_PARKED = BIT(27), BIT 520 include/linux/ide.h IDE_DFLAG_MEDIA_CHANGED = BIT(28), BIT 522 include/linux/ide.h IDE_DFLAG_WP = BIT(29), BIT 523 include/linux/ide.h IDE_DFLAG_FORMAT_IN_PROGRESS = BIT(30), BIT 524 include/linux/ide.h IDE_DFLAG_NIEN_QUIRK = BIT(31), BIT 712 include/linux/ide.h IDE_PFLAG_PROBING = BIT(0), BIT 865 include/linux/ide.h #define DS_SYNC BIT(0) BIT 1003 include/linux/ide.h IDE_DBG_FUNC = BIT(0), BIT 1005 include/linux/ide.h IDE_DBG_SENSE = BIT(1), BIT 1007 include/linux/ide.h IDE_DBG_PC = BIT(2), BIT 1009 include/linux/ide.h IDE_DBG_RQ = BIT(3), BIT 1011 include/linux/ide.h IDE_DBG_PROBE = BIT(4), BIT 1174 include/linux/ide.h REQ_IDETAPE_PC1 = BIT(0), /* packet command (first stage) */ BIT 1175 include/linux/ide.h REQ_IDETAPE_PC2 = BIT(1), /* packet command (second stage) */ BIT 1176 include/linux/ide.h REQ_IDETAPE_READ = BIT(2), BIT 1177 include/linux/ide.h REQ_IDETAPE_WRITE = BIT(3), BIT 1267 include/linux/ide.h IDE_HFLAG_ISA_PORTS = BIT(0), BIT 1269 include/linux/ide.h IDE_HFLAG_SINGLE = BIT(1), BIT 1271 include/linux/ide.h IDE_HFLAG_PIO_NO_BLACKLIST = BIT(2), BIT 1273 include/linux/ide.h IDE_HFLAG_QD_2ND_PORT = BIT(3), BIT 1275 include/linux/ide.h IDE_HFLAG_ABUSE_PREFETCH = BIT(4), BIT 1277 include/linux/ide.h IDE_HFLAG_ABUSE_FAST_DEVSEL = BIT(5), BIT 1279 include/linux/ide.h IDE_HFLAG_ABUSE_DMA_MODES = BIT(6), BIT 1284 include/linux/ide.h IDE_HFLAG_SET_PIO_MODE_KEEP_DMA = BIT(7), BIT 1286 include/linux/ide.h IDE_HFLAG_POST_SET_MODE = BIT(8), BIT 1288 include/linux/ide.h IDE_HFLAG_NO_SET_MODE = BIT(9), BIT 1290 include/linux/ide.h IDE_HFLAG_TRUST_BIOS_FOR_DMA = BIT(10), BIT 1292 include/linux/ide.h IDE_HFLAG_CS5520 = BIT(11), BIT 1294 include/linux/ide.h IDE_HFLAG_NO_ATAPI_DMA = BIT(12), BIT 1296 include/linux/ide.h IDE_HFLAG_NON_BOOTABLE = BIT(13), BIT 1298 include/linux/ide.h IDE_HFLAG_NO_DMA = BIT(14), BIT 1300 include/linux/ide.h IDE_HFLAG_NO_AUTODMA = BIT(15), BIT 1302 include/linux/ide.h IDE_HFLAG_MMIO = BIT(16), BIT 1304 include/linux/ide.h IDE_HFLAG_NO_LBA48 = BIT(17), BIT 1306 include/linux/ide.h IDE_HFLAG_NO_LBA48_DMA = BIT(18), BIT 1308 include/linux/ide.h IDE_HFLAG_ERROR_STOPS_FIFO = BIT(19), BIT 1310 include/linux/ide.h IDE_HFLAG_SERIALIZE = BIT(20), BIT 1312 include/linux/ide.h IDE_HFLAG_DTC2278 = BIT(21), BIT 1314 include/linux/ide.h IDE_HFLAG_4DRIVES = BIT(22), BIT 1316 include/linux/ide.h IDE_HFLAG_TRM290 = BIT(23), BIT 1318 include/linux/ide.h IDE_HFLAG_IO_32BIT = BIT(24), BIT 1320 include/linux/ide.h IDE_HFLAG_UNMASK_IRQS = BIT(25), BIT 1321 include/linux/ide.h IDE_HFLAG_BROKEN_ALTSTATUS = BIT(26), BIT 1323 include/linux/ide.h IDE_HFLAG_SERIALIZE_DMA = BIT(27), BIT 1325 include/linux/ide.h IDE_HFLAG_CLEAR_SIMPLEX = BIT(28), BIT 1327 include/linux/ide.h IDE_HFLAG_NO_DSC = BIT(29), BIT 1329 include/linux/ide.h IDE_HFLAG_NO_IO_32BIT = BIT(30), BIT 1331 include/linux/ide.h IDE_HFLAG_NO_UNMASK_IRQS = BIT(31), BIT 1539 include/linux/ide.h IDE_TIMING_SETUP = BIT(0), BIT 1540 include/linux/ide.h IDE_TIMING_ACT8B = BIT(1), BIT 1541 include/linux/ide.h IDE_TIMING_REC8B = BIT(2), BIT 1542 include/linux/ide.h IDE_TIMING_CYC8B = BIT(3), BIT 1545 include/linux/ide.h IDE_TIMING_ACTIVE = BIT(4), BIT 1546 include/linux/ide.h IDE_TIMING_RECOVER = BIT(5), BIT 1547 include/linux/ide.h IDE_TIMING_CYCLE = BIT(6), BIT 1548 include/linux/ide.h IDE_TIMING_UDMA = BIT(7), BIT 827 include/linux/ieee80211.h #define WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT BIT(0) BIT 828 include/linux/ieee80211.h #define WLAN_EID_CHAN_SWITCH_PARAM_INITIATOR BIT(1) BIT 829 include/linux/ieee80211.h #define WLAN_EID_CHAN_SWITCH_PARAM_REASON BIT(2) BIT 895 include/linux/ieee80211.h #define IEEE80211_ADDBA_EXT_NO_FRAG BIT(0) BIT 1249 include/linux/ieee80211.h #define IEEE80211_P2P_OPPPS_ENABLE_BIT BIT(7) BIT 2016 include/linux/ieee80211.h (BIT(5) | BIT(6)) BIT 2739 include/linux/ieee80211.h #define WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING BIT(2) BIT 2744 include/linux/ieee80211.h #define WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT BIT(6) BIT 2747 include/linux/ieee80211.h #define WLAN_EXT_CAPA4_TDLS_BUFFER_STA BIT(4) BIT 2748 include/linux/ieee80211.h #define WLAN_EXT_CAPA4_TDLS_PEER_PSM BIT(5) BIT 2749 include/linux/ieee80211.h #define WLAN_EXT_CAPA4_TDLS_CHAN_SWITCH BIT(6) BIT 2754 include/linux/ieee80211.h #define WLAN_EXT_CAPA4_INTERWORKING_ENABLED BIT(7) BIT 2760 include/linux/ieee80211.h #define WLAN_EXT_CAPA5_TDLS_ENABLED BIT(5) BIT 2761 include/linux/ieee80211.h #define WLAN_EXT_CAPA5_TDLS_PROHIBITED BIT(6) BIT 2762 include/linux/ieee80211.h #define WLAN_EXT_CAPA5_TDLS_CH_SW_PROHIBITED BIT(7) BIT 2764 include/linux/ieee80211.h #define WLAN_EXT_CAPA8_TDLS_WIDE_BW_ENABLED BIT(5) BIT 2765 include/linux/ieee80211.h #define WLAN_EXT_CAPA8_OPMODE_NOTIF BIT(6) BIT 2768 include/linux/ieee80211.h #define WLAN_EXT_CAPA8_MAX_MSDU_IN_AMSDU_LSB BIT(7) BIT 2769 include/linux/ieee80211.h #define WLAN_EXT_CAPA9_MAX_MSDU_IN_AMSDU_MSB BIT(0) BIT 2775 include/linux/ieee80211.h #define WLAN_EXT_CAPA9_FTM_INITIATOR BIT(7) BIT 2778 include/linux/ieee80211.h #define WLAN_EXT_CAPA10_TWT_REQUESTER_SUPPORT BIT(5) BIT 2779 include/linux/ieee80211.h #define WLAN_EXT_CAPA10_TWT_RESPONDER_SUPPORT BIT(6) BIT 2786 include/linux/ieee80211.h #define WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT BIT(7) BIT 2789 include/linux/ieee80211.h #define WLAN_EXT_CAPA11_EMA_SUPPORT BIT(1) BIT 2795 include/linux/ieee80211.h #define WLAN_BSS_COEX_INFORMATION_REQUEST BIT(0) BIT 2944 include/linux/ieee80211.h WLAN_IDLE_OPTIONS_PROTECTED_KEEP_ALIVE = BIT(0), BIT 32 include/linux/if_bridge.h #define BR_HAIRPIN_MODE BIT(0) BIT 33 include/linux/if_bridge.h #define BR_BPDU_GUARD BIT(1) BIT 34 include/linux/if_bridge.h #define BR_ROOT_BLOCK BIT(2) BIT 35 include/linux/if_bridge.h #define BR_MULTICAST_FAST_LEAVE BIT(3) BIT 36 include/linux/if_bridge.h #define BR_ADMIN_COST BIT(4) BIT 37 include/linux/if_bridge.h #define BR_LEARNING BIT(5) BIT 38 include/linux/if_bridge.h #define BR_FLOOD BIT(6) BIT 40 include/linux/if_bridge.h #define BR_PROMISC BIT(7) BIT 41 include/linux/if_bridge.h #define BR_PROXYARP BIT(8) BIT 42 include/linux/if_bridge.h #define BR_LEARNING_SYNC BIT(9) BIT 43 include/linux/if_bridge.h #define BR_PROXYARP_WIFI BIT(10) BIT 44 include/linux/if_bridge.h #define BR_MCAST_FLOOD BIT(11) BIT 45 include/linux/if_bridge.h #define BR_MULTICAST_TO_UNICAST BIT(12) BIT 46 include/linux/if_bridge.h #define BR_VLAN_TUNNEL BIT(13) BIT 47 include/linux/if_bridge.h #define BR_BCAST_FLOOD BIT(14) BIT 48 include/linux/if_bridge.h #define BR_NEIGH_SUPPRESS BIT(15) BIT 49 include/linux/if_bridge.h #define BR_ISOLATED BIT(16) BIT 142 include/linux/iio/adc/ad_sigma_delta.h .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 143 include/linux/iio/adc/ad_sigma_delta.h BIT(IIO_CHAN_INFO_OFFSET), \ BIT 144 include/linux/iio/adc/ad_sigma_delta.h .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 160 include/linux/iio/adc/ad_sigma_delta.h BIT(IIO_CHAN_INFO_SAMP_FREQ)) BIT 166 include/linux/iio/adc/ad_sigma_delta.h BIT(IIO_CHAN_INFO_SAMP_FREQ)) BIT 172 include/linux/iio/adc/ad_sigma_delta.h BIT(IIO_CHAN_INFO_SAMP_FREQ)) BIT 182 include/linux/iio/adc/ad_sigma_delta.h BIT(IIO_CHAN_INFO_SAMP_FREQ)) BIT 188 include/linux/iio/adc/ad_sigma_delta.h BIT(IIO_CHAN_INFO_SAMP_FREQ)) BIT 16 include/linux/iio/buffer_impl.h #define INDIO_BUFFER_FLAG_FIXED_WATERMARK BIT(0) BIT 55 include/linux/iio/common/st_sensors.h .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ BIT 281 include/linux/iio/iio.h return (chan->info_mask_separate & BIT(type)) | BIT 282 include/linux/iio/iio.h (chan->info_mask_shared_by_type & BIT(type)) | BIT 283 include/linux/iio/iio.h (chan->info_mask_shared_by_dir & BIT(type)) | BIT 284 include/linux/iio/iio.h (chan->info_mask_shared_by_all & BIT(type)); BIT 298 include/linux/iio/iio.h return (chan->info_mask_separate_available & BIT(type)) | BIT 299 include/linux/iio/iio.h (chan->info_mask_shared_by_type_available & BIT(type)) | BIT 300 include/linux/iio/iio.h (chan->info_mask_shared_by_dir_available & BIT(type)) | BIT 301 include/linux/iio/iio.h (chan->info_mask_shared_by_all_available & BIT(type)); BIT 169 include/linux/iio/imu/adis.h .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 170 include/linux/iio/imu/adis.h BIT(IIO_CHAN_INFO_SCALE), \ BIT 192 include/linux/iio/imu/adis.h .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 193 include/linux/iio/imu/adis.h BIT(IIO_CHAN_INFO_SCALE) | \ BIT 194 include/linux/iio/imu/adis.h BIT(IIO_CHAN_INFO_OFFSET), \ BIT 210 include/linux/iio/imu/adis.h .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT 212 include/linux/iio/imu/adis.h .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT 87 include/linux/io-pgtable.h #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) BIT 88 include/linux/io-pgtable.h #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) BIT 89 include/linux/io-pgtable.h #define IO_PGTABLE_QUIRK_TLBI_ON_MAP BIT(2) BIT 90 include/linux/io-pgtable.h #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) BIT 91 include/linux/io-pgtable.h #define IO_PGTABLE_QUIRK_NON_STRICT BIT(4) BIT 143 include/linux/ioport.h IORES_MAP_SYSTEM_RAM = BIT(0), BIT 144 include/linux/ioport.h IORES_MAP_ENCRYPTED = BIT(1), BIT 16 include/linux/irq_work.h #define IRQ_WORK_PENDING BIT(0) BIT 17 include/linux/irq_work.h #define IRQ_WORK_BUSY BIT(1) BIT 20 include/linux/irq_work.h #define IRQ_WORK_LAZY BIT(2) BIT 19 include/linux/jz4740-adc.h #define JZ_ADC_CONFIG_SPZZ BIT(31) BIT 20 include/linux/jz4740-adc.h #define JZ_ADC_CONFIG_EX_IN BIT(30) BIT 22 include/linux/jz4740-adc.h #define JZ_ADC_CONFIG_DMA_ENABLE BIT(15) BIT 26 include/linux/jz4740-adc.h #define JZ_ADC_CONFIG_BAT_MB BIT(4) BIT 139 include/linux/kvm_host.h #define KVM_REQUEST_NO_WAKEUP BIT(8) BIT 140 include/linux/kvm_host.h #define KVM_REQUEST_WAIT BIT(9) BIT 32 include/linux/leds-lp3952.h #define LP3952_PATRN_LOOP BIT(1) BIT 33 include/linux/leds-lp3952.h #define LP3952_PATRN_GEN_EN BIT(2) BIT 34 include/linux/leds-lp3952.h #define LP3952_INT_B00ST_LDR BIT(2) BIT 35 include/linux/leds-lp3952.h #define LP3952_ACTIVE_MODE BIT(6) BIT 17 include/linux/leds-ti-lmu-common.h #define LMU_11BIT_LSB_MASK (BIT(0) | BIT(1) | BIT(2)) BIT 65 include/linux/leds.h #define LED_SUSPENDED BIT(0) BIT 66 include/linux/leds.h #define LED_UNREGISTERING BIT(1) BIT 68 include/linux/leds.h #define LED_CORE_SUSPENDRESUME BIT(16) BIT 69 include/linux/leds.h #define LED_SYSFS_DISABLE BIT(17) BIT 70 include/linux/leds.h #define LED_DEV_CAP_FLASH BIT(18) BIT 71 include/linux/leds.h #define LED_HW_PLUGGABLE BIT(19) BIT 72 include/linux/leds.h #define LED_PANIC_INDICATOR BIT(20) BIT 73 include/linux/leds.h #define LED_BRIGHT_HW_CHANGED BIT(21) BIT 74 include/linux/leds.h #define LED_RETAIN_AT_SHUTDOWN BIT(22) BIT 75 include/linux/leds.h #define LED_INIT_DEFAULT_TRIGGER BIT(23) BIT 26 include/linux/libps2.h #define PS2_FLAG_ACK BIT(0) /* Waiting for ACK/NAK */ BIT 27 include/linux/libps2.h #define PS2_FLAG_CMD BIT(1) /* Waiting for a command to finish */ BIT 28 include/linux/libps2.h #define PS2_FLAG_CMD1 BIT(2) /* Waiting for the first byte of command response */ BIT 29 include/linux/libps2.h #define PS2_FLAG_WAITID BIT(3) /* Command executing is GET ID */ BIT 30 include/linux/libps2.h #define PS2_FLAG_NAK BIT(4) /* Last transmission was NAKed */ BIT 31 include/linux/libps2.h #define PS2_FLAG_ACK_CMD BIT(5) /* Waiting to ACK the command (first) byte */ BIT 2103 include/linux/lsm_hooks.h #define LSM_FLAG_LEGACY_MAJOR BIT(0) BIT 2104 include/linux/lsm_hooks.h #define LSM_FLAG_EXCLUSIVE BIT(1) BIT 26 include/linux/mailbox/brcm-message.h #define BRCM_SBA_CMD_TYPE_A BIT(0) BIT 27 include/linux/mailbox/brcm-message.h #define BRCM_SBA_CMD_TYPE_B BIT(1) BIT 28 include/linux/mailbox/brcm-message.h #define BRCM_SBA_CMD_TYPE_C BIT(2) BIT 29 include/linux/mailbox/brcm-message.h #define BRCM_SBA_CMD_HAS_RESP BIT(3) BIT 30 include/linux/mailbox/brcm-message.h #define BRCM_SBA_CMD_HAS_OUTPUT BIT(4) BIT 19 include/linux/mailbox/mtk-cmdq-mailbox.h #define CMDQ_WFE_UPDATE BIT(31) BIT 20 include/linux/mailbox/mtk-cmdq-mailbox.h #define CMDQ_WFE_WAIT BIT(15) BIT 61 include/linux/mfd/88pm80x.h #define PM800_ONKEY_STS1 BIT(0) BIT 62 include/linux/mfd/88pm80x.h #define PM800_EXTON_STS1 BIT(1) BIT 63 include/linux/mfd/88pm80x.h #define PM800_CHG_STS1 BIT(2) BIT 64 include/linux/mfd/88pm80x.h #define PM800_BAT_STS1 BIT(3) BIT 65 include/linux/mfd/88pm80x.h #define PM800_VBUS_STS1 BIT(4) BIT 66 include/linux/mfd/88pm80x.h #define PM800_LDO_PGOOD_STS1 BIT(5) BIT 67 include/linux/mfd/88pm80x.h #define PM800_BUCK_PGOOD_STS1 BIT(6) BIT 70 include/linux/mfd/88pm80x.h #define PM800_RTC_ALARM_STS2 BIT(0) BIT 76 include/linux/mfd/88pm80x.h #define PM800_WAKEUP2_INV_INT BIT(0) BIT 77 include/linux/mfd/88pm80x.h #define PM800_WAKEUP2_INT_CLEAR BIT(1) BIT 78 include/linux/mfd/88pm80x.h #define PM800_WAKEUP2_INT_MASK BIT(2) BIT 90 include/linux/mfd/88pm80x.h #define PM800_GPIO0_VAL BIT(0) BIT 92 include/linux/mfd/88pm80x.h #define PM800_GPIO1_VAL BIT(4) BIT 96 include/linux/mfd/88pm80x.h #define PM800_GPIO2_VAL BIT(0) BIT 98 include/linux/mfd/88pm80x.h #define PM800_GPIO3_VAL BIT(4) BIT 104 include/linux/mfd/88pm80x.h #define PM800_GPIO4_VAL BIT(0) BIT 108 include/linux/mfd/88pm80x.h #define PM800_HEADSET_DET_EN BIT(7) BIT 109 include/linux/mfd/88pm80x.h #define PM800_HSDET_SLP BIT(1) BIT 124 include/linux/mfd/88pm80x.h #define PM800_ALARM1_EN BIT(0) BIT 125 include/linux/mfd/88pm80x.h #define PM800_ALARM_WAKEUP BIT(4) BIT 126 include/linux/mfd/88pm80x.h #define PM800_ALARM BIT(5) BIT 127 include/linux/mfd/88pm80x.h #define PM800_RTC1_USE_XO BIT(7) BIT 141 include/linux/mfd/88pm80x.h #define PM800_MEAS_EN1_VBAT BIT(2) BIT 143 include/linux/mfd/88pm80x.h #define PM800_MEAS_EN2_RFTMP BIT(0) BIT 144 include/linux/mfd/88pm80x.h #define PM800_MEAS_GP0_EN BIT(2) BIT 145 include/linux/mfd/88pm80x.h #define PM800_MEAS_GP1_EN BIT(3) BIT 146 include/linux/mfd/88pm80x.h #define PM800_MEAS_GP2_EN BIT(4) BIT 147 include/linux/mfd/88pm80x.h #define PM800_MEAS_GP3_EN BIT(5) BIT 148 include/linux/mfd/88pm80x.h #define PM800_MEAS_GP4_EN BIT(6) BIT 152 include/linux/mfd/88pm80x.h #define PM800_GPADC_MISC_GPFSM_EN BIT(0) BIT 163 include/linux/mfd/88pm80x.h #define PM800_GPADC_GP_BIAS_EN0 BIT(0) BIT 164 include/linux/mfd/88pm80x.h #define PM800_GPADC_GP_BIAS_EN1 BIT(1) BIT 165 include/linux/mfd/88pm80x.h #define PM800_GPADC_GP_BIAS_EN2 BIT(2) BIT 166 include/linux/mfd/88pm80x.h #define PM800_GPADC_GP_BIAS_EN3 BIT(3) BIT 169 include/linux/mfd/88pm80x.h #define PM800_BIAS_OUT_GP0 BIT(0) BIT 170 include/linux/mfd/88pm80x.h #define PM800_BIAS_OUT_GP1 BIT(1) BIT 171 include/linux/mfd/88pm80x.h #define PM800_BIAS_OUT_GP2 BIT(2) BIT 172 include/linux/mfd/88pm80x.h #define PM800_BIAS_OUT_GP3 BIT(3) BIT 223 include/linux/mfd/88pm80x.h #define PM805_INT1_HP1_SHRT BIT(0) BIT 224 include/linux/mfd/88pm80x.h #define PM805_INT1_HP2_SHRT BIT(1) BIT 225 include/linux/mfd/88pm80x.h #define PM805_INT1_MIC_CONFLICT BIT(2) BIT 226 include/linux/mfd/88pm80x.h #define PM805_INT1_CLIP_FAULT BIT(3) BIT 227 include/linux/mfd/88pm80x.h #define PM805_INT1_LDO_OFF BIT(4) BIT 228 include/linux/mfd/88pm80x.h #define PM805_INT1_SRC_DPLL_LOCK BIT(5) BIT 232 include/linux/mfd/88pm80x.h #define PM805_INT2_MIC_DET BIT(0) BIT 233 include/linux/mfd/88pm80x.h #define PM805_INT2_SHRT_BTN_DET BIT(1) BIT 234 include/linux/mfd/88pm80x.h #define PM805_INT2_VOLM_BTN_DET BIT(2) BIT 235 include/linux/mfd/88pm80x.h #define PM805_INT2_VOLP_BTN_DET BIT(3) BIT 236 include/linux/mfd/88pm80x.h #define PM805_INT2_RAW_PLL_FAULT BIT(4) BIT 237 include/linux/mfd/88pm80x.h #define PM805_INT2_FINE_PLL_FAULT BIT(5) BIT 241 include/linux/mfd/88pm80x.h #define PM805_SHRT_BTN_DET BIT(1) BIT 247 include/linux/mfd/88pm80x.h #define PM805_MIC_DET_EN_MIC_DET BIT(0) BIT 83 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_TURNONSTATUS_PORNVBAT BIT(0) BIT 84 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1) BIT 85 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2) BIT 86 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_TURNONSTATUS_RTCALARM BIT(3) BIT 87 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_TURNONSTATUS_MAINCHDET BIT(4) BIT 88 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_TURNONSTATUS_VBUSDET BIT(5) BIT 89 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6) BIT 91 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0) BIT 92 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2) BIT 97 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0) BIT 98 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1) BIT 99 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2) BIT 100 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3) BIT 101 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4) BIT 102 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5) BIT 103 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6) BIT 104 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7) BIT 106 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL1_SWOFF BIT(0) BIT 107 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL1_SWRESET4500N BIT(1) BIT 108 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2) BIT 110 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0) BIT 111 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1) BIT 112 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2) BIT 113 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3) BIT 114 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4) BIT 115 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5) BIT 116 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6) BIT 117 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7) BIT 119 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0) BIT 120 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL3_RESETAUDN BIT(1) BIT 121 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL3_RESETDENCN BIT(2) BIT 122 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_STW4500CTRL3_THSDENA BIT(3) BIT 124 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0) BIT 125 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1) BIT 126 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4) BIT 131 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_LOWBAT_LOWBATENA BIT(0) BIT 147 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2) BIT 166 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2) BIT 167 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3) BIT 168 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4) BIT 169 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5) BIT 170 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6) BIT 171 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7) BIT 175 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2) BIT 176 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3) BIT 177 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4) BIT 178 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5) BIT 179 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6) BIT 180 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7) BIT 182 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0) BIT 183 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1) BIT 184 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKCTRL_USBCLKENA BIT(2) BIT 186 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0) BIT 187 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1) BIT 188 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2) BIT 194 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4) BIT 196 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2) BIT 197 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3) BIT 198 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4) BIT 200 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2) BIT 201 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3) BIT 202 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4) BIT 204 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2) BIT 205 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3) BIT 206 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4) BIT 208 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2) BIT 209 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3) BIT 210 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4) BIT 212 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2) BIT 213 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3) BIT 214 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4) BIT 216 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2) BIT 217 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3) BIT 218 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4) BIT 220 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2) BIT 221 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3) BIT 222 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4) BIT 224 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2) BIT 225 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3) BIT 226 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4) BIT 228 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0) BIT 229 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1) BIT 230 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2) BIT 231 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3) BIT 232 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4) BIT 233 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5) BIT 237 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SWATCTRL_UPDATERF BIT(0) BIT 238 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SWATCTRL_SWATENABLE BIT(1) BIT 241 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_SWATCTRL_SWATBIT5 BIT(6) BIT 243 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0) BIT 244 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1) BIT 245 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2) BIT 246 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3) BIT 247 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4) BIT 248 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5) BIT 249 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6) BIT 250 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7) BIT 252 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0) BIT 253 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1) BIT 254 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2) BIT 255 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3) BIT 256 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4) BIT 257 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5) BIT 258 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6) BIT 259 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7) BIT 261 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0) BIT 262 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1) BIT 263 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2) BIT 264 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3) BIT 266 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4) BIT 267 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5) BIT 268 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6) BIT 269 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7) BIT 272 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0) BIT 273 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1) BIT 274 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2) BIT 275 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3) BIT 276 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4) BIT 277 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5) BIT 278 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6) BIT 280 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0) BIT 281 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1) BIT 282 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2) BIT 283 include/linux/mfd/abx500/ab8500-sysctrl.h #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3) BIT 175 include/linux/mfd/as3722.h #define AS3722_LDO_ILIMIT_MASK BIT(7) BIT 176 include/linux/mfd/as3722.h #define AS3722_LDO_ILIMIT_BIT BIT(7) BIT 193 include/linux/mfd/as3722.h #define AS3722_LDO0_CTRL BIT(0) BIT 194 include/linux/mfd/as3722.h #define AS3722_LDO1_CTRL BIT(1) BIT 195 include/linux/mfd/as3722.h #define AS3722_LDO2_CTRL BIT(2) BIT 196 include/linux/mfd/as3722.h #define AS3722_LDO3_CTRL BIT(3) BIT 197 include/linux/mfd/as3722.h #define AS3722_LDO4_CTRL BIT(4) BIT 198 include/linux/mfd/as3722.h #define AS3722_LDO5_CTRL BIT(5) BIT 199 include/linux/mfd/as3722.h #define AS3722_LDO6_CTRL BIT(6) BIT 200 include/linux/mfd/as3722.h #define AS3722_LDO7_CTRL BIT(7) BIT 201 include/linux/mfd/as3722.h #define AS3722_LDO9_CTRL BIT(1) BIT 202 include/linux/mfd/as3722.h #define AS3722_LDO10_CTRL BIT(2) BIT 203 include/linux/mfd/as3722.h #define AS3722_LDO11_CTRL BIT(3) BIT 219 include/linux/mfd/as3722.h #define AS3722_SDn_CTRL(n) BIT(n) BIT 221 include/linux/mfd/as3722.h #define AS3722_SD0_MODE_FAST BIT(4) BIT 222 include/linux/mfd/as3722.h #define AS3722_SD1_MODE_FAST BIT(4) BIT 223 include/linux/mfd/as3722.h #define AS3722_SD2_MODE_FAST BIT(2) BIT 224 include/linux/mfd/as3722.h #define AS3722_SD3_MODE_FAST BIT(6) BIT 225 include/linux/mfd/as3722.h #define AS3722_SD4_MODE_FAST BIT(2) BIT 226 include/linux/mfd/as3722.h #define AS3722_SD5_MODE_FAST BIT(2) BIT 227 include/linux/mfd/as3722.h #define AS3722_SD6_MODE_FAST BIT(4) BIT 229 include/linux/mfd/as3722.h #define AS3722_POWER_OFF BIT(1) BIT 231 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK1_LID BIT(0) BIT 232 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK1_ACOK BIT(1) BIT 233 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK1_ENABLE1 BIT(2) BIT 234 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0 BIT(3) BIT 235 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK1_ONKEY_LONG BIT(4) BIT 236 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK1_ONKEY BIT(5) BIT 237 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK1_OVTMP BIT(6) BIT 238 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK1_LOWBAT BIT(7) BIT 240 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK2_SD0_LV BIT(0) BIT 241 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK2_SD1_LV BIT(1) BIT 242 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK2_SD2345_LV BIT(2) BIT 243 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK2_PWM1_OV_PROT BIT(3) BIT 244 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK2_PWM2_OV_PROT BIT(4) BIT 245 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK2_ENABLE2 BIT(5) BIT 246 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK2_SD6_LV BIT(6) BIT 247 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK2_RTC_REP BIT(7) BIT 249 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK3_RTC_ALARM BIT(0) BIT 250 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK3_GPIO1 BIT(1) BIT 251 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK3_GPIO2 BIT(2) BIT 252 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK3_GPIO3 BIT(3) BIT 253 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK3_GPIO4 BIT(4) BIT 254 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK3_GPIO5 BIT(5) BIT 255 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK3_WATCHDOG BIT(6) BIT 256 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK3_ENABLE3 BIT(7) BIT 258 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN BIT(0) BIT 259 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN BIT(1) BIT 260 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN BIT(2) BIT 261 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM BIT(3) BIT 262 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM BIT(4) BIT 263 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM BIT(5) BIT 264 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6 BIT(6) BIT 265 include/linux/mfd/as3722.h #define AS3722_INTERRUPT_MASK4_ADC BIT(7) BIT 267 include/linux/mfd/as3722.h #define AS3722_ADC1_INTERVAL_TIME BIT(0) BIT 268 include/linux/mfd/as3722.h #define AS3722_ADC1_INT_MODE_ON BIT(1) BIT 269 include/linux/mfd/as3722.h #define AS3722_ADC_BUF_ON BIT(2) BIT 270 include/linux/mfd/as3722.h #define AS3722_ADC1_LOW_VOLTAGE_RANGE BIT(5) BIT 271 include/linux/mfd/as3722.h #define AS3722_ADC1_INTEVAL_SCAN BIT(6) BIT 272 include/linux/mfd/as3722.h #define AS3722_ADC1_INT_MASK BIT(7) BIT 277 include/linux/mfd/as3722.h #define AS3722_ADC0_CONV_START BIT(7) BIT 278 include/linux/mfd/as3722.h #define AS3722_ADC0_CONV_NOTREADY BIT(7) BIT 281 include/linux/mfd/as3722.h #define AS3722_ADC1_CONV_START BIT(7) BIT 282 include/linux/mfd/as3722.h #define AS3722_ADC1_CONV_NOTREADY BIT(7) BIT 285 include/linux/mfd/as3722.h #define AS3722_CTRL_SEQU1_AC_OK_PWR_ON BIT(0) BIT 299 include/linux/mfd/as3722.h #define AS3722_GPIO_INV BIT(7) BIT 317 include/linux/mfd/as3722.h #define AS3722_GPIOn_SIGNAL(n) BIT(n) BIT 319 include/linux/mfd/as3722.h #define AS3722_I2C_PULL_UP BIT(4) BIT 320 include/linux/mfd/as3722.h #define AS3722_INT_PULL_UP BIT(5) BIT 322 include/linux/mfd/as3722.h #define AS3722_RTC_REP_WAKEUP_EN BIT(0) BIT 323 include/linux/mfd/as3722.h #define AS3722_RTC_ALARM_WAKEUP_EN BIT(1) BIT 324 include/linux/mfd/as3722.h #define AS3722_RTC_ON BIT(2) BIT 325 include/linux/mfd/as3722.h #define AS3722_RTC_IRQMODE BIT(3) BIT 326 include/linux/mfd/as3722.h #define AS3722_RTC_CLK32K_OUT_EN BIT(5) BIT 329 include/linux/mfd/as3722.h #define AS3722_WATCHDOG_ON BIT(0) BIT 330 include/linux/mfd/as3722.h #define AS3722_WATCHDOG_SW_SIG BIT(0) BIT 336 include/linux/mfd/as3722.h #define AS3722_FUSE7_SD0_LOW_VOLTAGE BIT(4) BIT 17 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_HSPOL BIT(0) BIT 18 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_VSPOL BIT(1) BIT 19 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_VSPDLYS BIT(2) BIT 20 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_VSPDLYE BIT(3) BIT 21 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_DISPPOL BIT(4) BIT 22 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_DITHER BIT(6) BIT 23 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_DISPDLY BIT(7) BIT 25 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_PP BIT(10) BIT 26 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_VSPSU BIT(12) BIT 27 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_VSPHO BIT(13) BIT 38 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_CLKPOL BIT(0) BIT 39 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_CLKSEL BIT(2) BIT 40 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_CLKPWMSEL BIT(3) BIT 41 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_CGDIS(i) BIT(8 + (i)) BIT 46 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_PIXEL_CLK BIT(0) BIT 47 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_SYNC BIT(1) BIT 48 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_DISP BIT(2) BIT 49 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_PWM BIT(3) BIT 50 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_SIP BIT(4) BIT 52 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_SOF BIT(0) BIT 53 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_SYNCDIS BIT(1) BIT 54 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_FIFOERR BIT(4) BIT 55 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_LAYER_STATUS(x) BIT((x) + 8) BIT 37 include/linux/mfd/bd9571mwv.h #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0 BIT(0) BIT 38 include/linux/mfd/bd9571mwv.h #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1 BIT(1) BIT 39 include/linux/mfd/bd9571mwv.h #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0C BIT(2) BIT 40 include/linux/mfd/bd9571mwv.h #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1C BIT(3) BIT 82 include/linux/mfd/bd9571mwv.h #define BD9571MWV_INT_INTREQ_MD1_INT BIT(0) BIT 83 include/linux/mfd/bd9571mwv.h #define BD9571MWV_INT_INTREQ_MD2_E1_INT BIT(1) BIT 84 include/linux/mfd/bd9571mwv.h #define BD9571MWV_INT_INTREQ_MD2_E2_INT BIT(2) BIT 85 include/linux/mfd/bd9571mwv.h #define BD9571MWV_INT_INTREQ_PROT_ERR_INT BIT(3) BIT 86 include/linux/mfd/bd9571mwv.h #define BD9571MWV_INT_INTREQ_GP_INT BIT(4) BIT 87 include/linux/mfd/bd9571mwv.h #define BD9571MWV_INT_INTREQ_128H_OF_INT BIT(5) BIT 88 include/linux/mfd/bd9571mwv.h #define BD9571MWV_INT_INTREQ_WDT_OF_INT BIT(6) BIT 89 include/linux/mfd/bd9571mwv.h #define BD9571MWV_INT_INTREQ_BKUP_TRG_INT BIT(7) BIT 17 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP0_PLL_MASTER_LOCK BIT(4) BIT 81 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP1_HPIBYTEAD BIT(16) BIT 82 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP1_HPIENA BIT(15) BIT 88 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP1_TBCLKSYNC BIT(12) BIT 102 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_PHYCLKGD BIT(17) BIT 103 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_VBUSSENSE BIT(16) BIT 104 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_RESET BIT(15) BIT 111 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_USB1PHYCLKMUX BIT(12) BIT 112 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_USB2PHYCLKMUX BIT(11) BIT 113 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_PHYPWRDN BIT(10) BIT 114 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_OTGPWRDN BIT(9) BIT 115 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_DATPOL BIT(8) BIT 116 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_USB1SUSPENDM BIT(7) BIT 117 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_PHY_PLLON BIT(6) BIT 118 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_SESENDEN BIT(5) BIT 119 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP2_VBDTCTEN BIT(4) BIT 133 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP3_RMII_SEL BIT(8) BIT 134 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP3_UPP_TX_CLKSRC BIT(6) BIT 135 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5) BIT 136 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP3_ASYNC3_CLKSRC BIT(4) BIT 137 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP3_PRUEVTSEL BIT(3) BIT 138 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP3_DIV45PENA BIT(2) BIT 139 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP3_EMA_CLKSRC BIT(1) BIT 142 include/linux/mfd/da8xx-cfgchip.h #define CFGCHIP4_AMUTECLR0 BIT(0) BIT 158 include/linux/mfd/da9062/registers.h #define DA9062AA_WRITE_MODE_MASK BIT(6) BIT 160 include/linux/mfd/da9062/registers.h #define DA9062AA_REVERT_MASK BIT(7) BIT 166 include/linux/mfd/da9062/registers.h #define DA9062AA_DVC_BUSY_MASK BIT(2) BIT 172 include/linux/mfd/da9062/registers.h #define DA9062AA_GPI1_MASK BIT(1) BIT 174 include/linux/mfd/da9062/registers.h #define DA9062AA_GPI2_MASK BIT(2) BIT 176 include/linux/mfd/da9062/registers.h #define DA9062AA_GPI3_MASK BIT(3) BIT 178 include/linux/mfd/da9062/registers.h #define DA9062AA_GPI4_MASK BIT(4) BIT 184 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO2_ILIM_MASK BIT(1) BIT 186 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO3_ILIM_MASK BIT(2) BIT 188 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO4_ILIM_MASK BIT(3) BIT 194 include/linux/mfd/da9062/registers.h #define DA9062AA_POR_MASK BIT(1) BIT 196 include/linux/mfd/da9062/registers.h #define DA9062AA_VDD_FAULT_MASK BIT(2) BIT 198 include/linux/mfd/da9062/registers.h #define DA9062AA_VDD_START_MASK BIT(3) BIT 200 include/linux/mfd/da9062/registers.h #define DA9062AA_TEMP_CRIT_MASK BIT(4) BIT 202 include/linux/mfd/da9062/registers.h #define DA9062AA_KEY_RESET_MASK BIT(5) BIT 204 include/linux/mfd/da9062/registers.h #define DA9062AA_NSHUTDOWN_MASK BIT(6) BIT 206 include/linux/mfd/da9062/registers.h #define DA9062AA_WAIT_SHUT_MASK BIT(7) BIT 212 include/linux/mfd/da9062/registers.h #define DA9062AA_E_ALARM_MASK BIT(1) BIT 214 include/linux/mfd/da9062/registers.h #define DA9062AA_E_TICK_MASK BIT(2) BIT 216 include/linux/mfd/da9062/registers.h #define DA9062AA_E_WDG_WARN_MASK BIT(3) BIT 218 include/linux/mfd/da9062/registers.h #define DA9062AA_E_SEQ_RDY_MASK BIT(4) BIT 220 include/linux/mfd/da9062/registers.h #define DA9062AA_EVENTS_B_MASK BIT(5) BIT 222 include/linux/mfd/da9062/registers.h #define DA9062AA_EVENTS_C_MASK BIT(6) BIT 226 include/linux/mfd/da9062/registers.h #define DA9062AA_E_TEMP_MASK BIT(1) BIT 228 include/linux/mfd/da9062/registers.h #define DA9062AA_E_LDO_LIM_MASK BIT(3) BIT 230 include/linux/mfd/da9062/registers.h #define DA9062AA_E_DVC_RDY_MASK BIT(5) BIT 232 include/linux/mfd/da9062/registers.h #define DA9062AA_E_VDD_WARN_MASK BIT(7) BIT 238 include/linux/mfd/da9062/registers.h #define DA9062AA_E_GPI1_MASK BIT(1) BIT 240 include/linux/mfd/da9062/registers.h #define DA9062AA_E_GPI2_MASK BIT(2) BIT 242 include/linux/mfd/da9062/registers.h #define DA9062AA_E_GPI3_MASK BIT(3) BIT 244 include/linux/mfd/da9062/registers.h #define DA9062AA_E_GPI4_MASK BIT(4) BIT 250 include/linux/mfd/da9062/registers.h #define DA9062AA_M_ALARM_MASK BIT(1) BIT 252 include/linux/mfd/da9062/registers.h #define DA9062AA_M_TICK_MASK BIT(2) BIT 254 include/linux/mfd/da9062/registers.h #define DA9062AA_M_WDG_WARN_MASK BIT(3) BIT 256 include/linux/mfd/da9062/registers.h #define DA9062AA_M_SEQ_RDY_MASK BIT(4) BIT 260 include/linux/mfd/da9062/registers.h #define DA9062AA_M_TEMP_MASK BIT(1) BIT 262 include/linux/mfd/da9062/registers.h #define DA9062AA_M_LDO_LIM_MASK BIT(3) BIT 264 include/linux/mfd/da9062/registers.h #define DA9062AA_M_DVC_RDY_MASK BIT(5) BIT 266 include/linux/mfd/da9062/registers.h #define DA9062AA_M_VDD_WARN_MASK BIT(7) BIT 272 include/linux/mfd/da9062/registers.h #define DA9062AA_M_GPI1_MASK BIT(1) BIT 274 include/linux/mfd/da9062/registers.h #define DA9062AA_M_GPI2_MASK BIT(2) BIT 276 include/linux/mfd/da9062/registers.h #define DA9062AA_M_GPI3_MASK BIT(3) BIT 278 include/linux/mfd/da9062/registers.h #define DA9062AA_M_GPI4_MASK BIT(4) BIT 284 include/linux/mfd/da9062/registers.h #define DA9062AA_POWER_EN_MASK BIT(1) BIT 286 include/linux/mfd/da9062/registers.h #define DA9062AA_POWER1_EN_MASK BIT(2) BIT 288 include/linux/mfd/da9062/registers.h #define DA9062AA_STANDBY_MASK BIT(3) BIT 290 include/linux/mfd/da9062/registers.h #define DA9062AA_M_SYSTEM_EN_MASK BIT(4) BIT 292 include/linux/mfd/da9062/registers.h #define DA9062AA_M_POWER_EN_MASK BIT(5) BIT 294 include/linux/mfd/da9062/registers.h #define DA9062AA_M_POWER1_EN_MASK BIT(6) BIT 298 include/linux/mfd/da9062/registers.h #define DA9062AA_WATCHDOG_PD_MASK BIT(1) BIT 300 include/linux/mfd/da9062/registers.h #define DA9062AA_FREEZE_EN_MASK BIT(2) BIT 302 include/linux/mfd/da9062/registers.h #define DA9062AA_NRES_MODE_MASK BIT(3) BIT 304 include/linux/mfd/da9062/registers.h #define DA9062AA_NONKEY_LOCK_MASK BIT(4) BIT 308 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK_SLOWSTART_MASK BIT(7) BIT 314 include/linux/mfd/da9062/registers.h #define DA9062AA_AUTO_BOOT_MASK BIT(3) BIT 316 include/linux/mfd/da9062/registers.h #define DA9062AA_OTPREAD_EN_MASK BIT(4) BIT 320 include/linux/mfd/da9062/registers.h #define DA9062AA_DEF_SUPPLY_MASK BIT(7) BIT 330 include/linux/mfd/da9062/registers.h #define DA9062AA_RTC_MODE_SD_MASK BIT(1) BIT 332 include/linux/mfd/da9062/registers.h #define DA9062AA_RTC_EN_MASK BIT(2) BIT 334 include/linux/mfd/da9062/registers.h #define DA9062AA_V_LOCK_MASK BIT(7) BIT 340 include/linux/mfd/da9062/registers.h #define DA9062AA_SHUTDOWN_MASK BIT(1) BIT 342 include/linux/mfd/da9062/registers.h #define DA9062AA_WAKE_UP_MASK BIT(2) BIT 348 include/linux/mfd/da9062/registers.h #define DA9062AA_PMIF_DIS_MASK BIT(2) BIT 350 include/linux/mfd/da9062/registers.h #define DA9062AA_CLDR_PAUSE_MASK BIT(4) BIT 352 include/linux/mfd/da9062/registers.h #define DA9062AA_BBAT_DIS_MASK BIT(5) BIT 354 include/linux/mfd/da9062/registers.h #define DA9062AA_OUT32K_PAUSE_MASK BIT(6) BIT 356 include/linux/mfd/da9062/registers.h #define DA9062AA_PMCONT_DIS_MASK BIT(7) BIT 362 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO0_TYPE_MASK BIT(2) BIT 364 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO0_WEN_MASK BIT(3) BIT 368 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO1_TYPE_MASK BIT(6) BIT 370 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO1_WEN_MASK BIT(7) BIT 376 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO2_TYPE_MASK BIT(2) BIT 378 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO2_WEN_MASK BIT(3) BIT 382 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO3_TYPE_MASK BIT(6) BIT 384 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO3_WEN_MASK BIT(7) BIT 390 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO4_TYPE_MASK BIT(2) BIT 392 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO4_WEN_MASK BIT(3) BIT 398 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO1_WKUP_MODE_MASK BIT(1) BIT 400 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO2_WKUP_MODE_MASK BIT(2) BIT 402 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO3_WKUP_MODE_MASK BIT(3) BIT 404 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO4_WKUP_MODE_MASK BIT(4) BIT 410 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO1_MODE_MASK BIT(1) BIT 412 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO2_MODE_MASK BIT(2) BIT 414 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO3_MODE_MASK BIT(3) BIT 416 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO4_MODE_MASK BIT(4) BIT 438 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK2_CONF_MASK BIT(3) BIT 448 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK1_CONF_MASK BIT(3) BIT 458 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK4_CONF_MASK BIT(3) BIT 468 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK3_CONF_MASK BIT(3) BIT 478 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO1_PD_DIS_MASK BIT(3) BIT 482 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO1_CONF_MASK BIT(7) BIT 490 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO2_PD_DIS_MASK BIT(3) BIT 494 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO2_CONF_MASK BIT(7) BIT 502 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO3_PD_DIS_MASK BIT(3) BIT 506 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO3_CONF_MASK BIT(7) BIT 514 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO4_PD_DIS_MASK BIT(3) BIT 518 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO4_CONF_MASK BIT(7) BIT 524 include/linux/mfd/da9062/registers.h #define DA9062AA_VBUCK2_SEL_MASK BIT(1) BIT 526 include/linux/mfd/da9062/registers.h #define DA9062AA_VBUCK4_SEL_MASK BIT(2) BIT 528 include/linux/mfd/da9062/registers.h #define DA9062AA_VBUCK3_SEL_MASK BIT(3) BIT 530 include/linux/mfd/da9062/registers.h #define DA9062AA_VLDO1_SEL_MASK BIT(4) BIT 532 include/linux/mfd/da9062/registers.h #define DA9062AA_VLDO2_SEL_MASK BIT(5) BIT 534 include/linux/mfd/da9062/registers.h #define DA9062AA_VLDO3_SEL_MASK BIT(6) BIT 536 include/linux/mfd/da9062/registers.h #define DA9062AA_VLDO4_SEL_MASK BIT(7) BIT 542 include/linux/mfd/da9062/registers.h #define DA9062AA_RTC_READ_MASK BIT(7) BIT 564 include/linux/mfd/da9062/registers.h #define DA9062AA_MONITOR_MASK BIT(6) BIT 588 include/linux/mfd/da9062/registers.h #define DA9062AA_TICK_TYPE_MASK BIT(4) BIT 590 include/linux/mfd/da9062/registers.h #define DA9062AA_TICK_WAKE_MASK BIT(5) BIT 596 include/linux/mfd/da9062/registers.h #define DA9062AA_ALARM_ON_MASK BIT(6) BIT 598 include/linux/mfd/da9062/registers.h #define DA9062AA_TICK_ON_MASK BIT(7) BIT 708 include/linux/mfd/da9062/registers.h #define DA9062AA_WAIT_MODE_MASK BIT(4) BIT 710 include/linux/mfd/da9062/registers.h #define DA9062AA_TIME_OUT_MASK BIT(5) BIT 718 include/linux/mfd/da9062/registers.h #define DA9062AA_CRYSTAL_MASK BIT(3) BIT 720 include/linux/mfd/da9062/registers.h #define DA9062AA_DELAY_MODE_MASK BIT(4) BIT 722 include/linux/mfd/da9062/registers.h #define DA9062AA_OUT_CLOCK_MASK BIT(5) BIT 724 include/linux/mfd/da9062/registers.h #define DA9062AA_RTC_CLOCK_MASK BIT(6) BIT 726 include/linux/mfd/da9062/registers.h #define DA9062AA_EN_32KOUT_MASK BIT(7) BIT 750 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK2_PD_DIS_MASK BIT(5) BIT 756 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK1_PD_DIS_MASK BIT(5) BIT 762 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK4_VTTR_EN_MASK BIT(3) BIT 764 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK4_VTT_EN_MASK BIT(4) BIT 766 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK4_PD_DIS_MASK BIT(5) BIT 772 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK3_PD_DIS_MASK BIT(5) BIT 780 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK2_SL_A_MASK BIT(7) BIT 786 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK1_SL_A_MASK BIT(7) BIT 792 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK4_SL_A_MASK BIT(7) BIT 798 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK3_SL_A_MASK BIT(7) BIT 807 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO1_SL_A_MASK BIT(7) BIT 813 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO2_SL_A_MASK BIT(7) BIT 819 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO3_SL_A_MASK BIT(7) BIT 825 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO4_SL_A_MASK BIT(7) BIT 831 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK2_SL_B_MASK BIT(7) BIT 837 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK1_SL_B_MASK BIT(7) BIT 843 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK4_SL_B_MASK BIT(7) BIT 849 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK3_SL_B_MASK BIT(7) BIT 855 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO1_SL_B_MASK BIT(7) BIT 861 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO2_SL_B_MASK BIT(7) BIT 867 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO3_SL_B_MASK BIT(7) BIT 873 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO4_SL_B_MASK BIT(7) BIT 889 include/linux/mfd/da9062/registers.h #define DA9062AA_PM_O_TYPE_MASK BIT(2) BIT 891 include/linux/mfd/da9062/registers.h #define DA9062AA_IRQ_TYPE_MASK BIT(3) BIT 893 include/linux/mfd/da9062/registers.h #define DA9062AA_PM_IF_V_MASK BIT(4) BIT 895 include/linux/mfd/da9062/registers.h #define DA9062AA_PM_IF_FMP_MASK BIT(5) BIT 897 include/linux/mfd/da9062/registers.h #define DA9062AA_PM_IF_HSM_MASK BIT(6) BIT 907 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK_ACTV_DISCHRG_MASK BIT(2) BIT 909 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK1_CLK_INV_MASK BIT(3) BIT 911 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK4_CLK_INV_MASK BIT(4) BIT 913 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK3_CLK_INV_MASK BIT(6) BIT 919 include/linux/mfd/da9062/registers.h #define DA9062AA_NIRQ_MODE_MASK BIT(1) BIT 921 include/linux/mfd/da9062/registers.h #define DA9062AA_SYSTEM_EN_RD_MASK BIT(2) BIT 923 include/linux/mfd/da9062/registers.h #define DA9062AA_FORCE_RESET_MASK BIT(5) BIT 929 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK2_AUTO_MASK BIT(1) BIT 931 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK4_AUTO_MASK BIT(2) BIT 933 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK3_AUTO_MASK BIT(4) BIT 939 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO2_AUTO_MASK BIT(1) BIT 941 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO3_AUTO_MASK BIT(2) BIT 943 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO4_AUTO_MASK BIT(3) BIT 947 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK1_2_MERGE_MASK BIT(3) BIT 949 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK2_OD_MASK BIT(5) BIT 951 include/linux/mfd/da9062/registers.h #define DA9062AA_BUCK1_OD_MASK BIT(6) BIT 957 include/linux/mfd/da9062/registers.h #define DA9062AA_nONKEY_SD_MASK BIT(2) BIT 959 include/linux/mfd/da9062/registers.h #define DA9062AA_WATCHDOG_SD_MASK BIT(3) BIT 961 include/linux/mfd/da9062/registers.h #define DA9062AA_KEY_SD_MODE_MASK BIT(4) BIT 963 include/linux/mfd/da9062/registers.h #define DA9062AA_HOST_SD_MODE_MASK BIT(5) BIT 965 include/linux/mfd/da9062/registers.h #define DA9062AA_INT_SD_MODE_MASK BIT(6) BIT 967 include/linux/mfd/da9062/registers.h #define DA9062AA_LDO_SD_MASK BIT(7) BIT 977 include/linux/mfd/da9062/registers.h #define DA9062AA_TWOWIRE_TO_MASK BIT(6) BIT 979 include/linux/mfd/da9062/registers.h #define DA9062AA_IF_RESET_MASK BIT(7) BIT 985 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO1_PUPD_MASK BIT(1) BIT 987 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO2_PUPD_MASK BIT(2) BIT 989 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO3_PUPD_MASK BIT(3) BIT 991 include/linux/mfd/da9062/registers.h #define DA9062AA_GPIO4_PUPD_MASK BIT(4) BIT 995 include/linux/mfd/da9062/registers.h #define DA9062AA_NSHUTDOWN_PU_MASK BIT(1) BIT 997 include/linux/mfd/da9062/registers.h #define DA9062AA_WDG_MODE_MASK BIT(3) BIT 160 include/linux/mfd/da9150/registers.h #define DA9150_WRITE_MODE_MASK BIT(6) BIT 162 include/linux/mfd/da9150/registers.h #define DA9150_REVERT_MASK BIT(7) BIT 172 include/linux/mfd/da9150/registers.h #define DA9150_VFAULT_STAT_MASK BIT(0) BIT 174 include/linux/mfd/da9150/registers.h #define DA9150_TFAULT_STAT_MASK BIT(1) BIT 178 include/linux/mfd/da9150/registers.h #define DA9150_VDD33_STAT_MASK BIT(0) BIT 180 include/linux/mfd/da9150/registers.h #define DA9150_VDD33_SLEEP_MASK BIT(1) BIT 182 include/linux/mfd/da9150/registers.h #define DA9150_LFOSC_STAT_MASK BIT(7) BIT 186 include/linux/mfd/da9150/registers.h #define DA9150_GPIOA_STAT_MASK BIT(0) BIT 188 include/linux/mfd/da9150/registers.h #define DA9150_GPIOB_STAT_MASK BIT(1) BIT 190 include/linux/mfd/da9150/registers.h #define DA9150_GPIOC_STAT_MASK BIT(2) BIT 192 include/linux/mfd/da9150/registers.h #define DA9150_GPIOD_STAT_MASK BIT(3) BIT 198 include/linux/mfd/da9150/registers.h #define DA9150_DTYPE_DT_USB_OTG BIT(0) BIT 213 include/linux/mfd/da9150/registers.h #define DA9150_SESS_VLD_MASK BIT(0) BIT 215 include/linux/mfd/da9150/registers.h #define DA9150_ID_ERR_MASK BIT(1) BIT 217 include/linux/mfd/da9150/registers.h #define DA9150_PT_CHG_MASK BIT(2) BIT 227 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_STAT_WAIT BIT(0) BIT 230 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_TRED_MASK BIT(3) BIT 238 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_OT_MASK BIT(7) BIT 244 include/linux/mfd/da9150/registers.h #define DA9150_CHG_STAT_SUSP BIT(0) BIT 258 include/linux/mfd/da9150/registers.h #define DA9150_CHG_IEND_STAT_MASK BIT(7) BIT 270 include/linux/mfd/da9150/registers.h #define DA9150_CHG_TIME_MASK BIT(1) BIT 272 include/linux/mfd/da9150/registers.h #define DA9150_CHG_TRED_MASK BIT(2) BIT 277 include/linux/mfd/da9150/registers.h #define DA9150_EBS_STAT_MASK BIT(6) BIT 279 include/linux/mfd/da9150/registers.h #define DA9150_CHG_BAT_REMOVED_MASK BIT(7) BIT 283 include/linux/mfd/da9150/registers.h #define DA9150_TEMP_FAULT_MASK BIT(0) BIT 285 include/linux/mfd/da9150/registers.h #define DA9150_VSYS_FAULT_MASK BIT(1) BIT 287 include/linux/mfd/da9150/registers.h #define DA9150_START_FAULT_MASK BIT(2) BIT 289 include/linux/mfd/da9150/registers.h #define DA9150_EXT_FAULT_MASK BIT(3) BIT 291 include/linux/mfd/da9150/registers.h #define DA9150_POR_FAULT_MASK BIT(4) BIT 295 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_FAULT_MASK BIT(0) BIT 297 include/linux/mfd/da9150/registers.h #define DA9150_OTG_FAULT_MASK BIT(1) BIT 301 include/linux/mfd/da9150/registers.h #define DA9150_E_VBUS_MASK BIT(0) BIT 303 include/linux/mfd/da9150/registers.h #define DA9150_E_CHG_MASK BIT(1) BIT 305 include/linux/mfd/da9150/registers.h #define DA9150_E_TCLASS_MASK BIT(2) BIT 307 include/linux/mfd/da9150/registers.h #define DA9150_E_TJUNC_MASK BIT(3) BIT 309 include/linux/mfd/da9150/registers.h #define DA9150_E_VFAULT_MASK BIT(4) BIT 311 include/linux/mfd/da9150/registers.h #define DA9150_EVENTS_H_MASK BIT(5) BIT 313 include/linux/mfd/da9150/registers.h #define DA9150_EVENTS_G_MASK BIT(6) BIT 315 include/linux/mfd/da9150/registers.h #define DA9150_EVENTS_F_MASK BIT(7) BIT 319 include/linux/mfd/da9150/registers.h #define DA9150_E_CONF_MASK BIT(0) BIT 321 include/linux/mfd/da9150/registers.h #define DA9150_E_DAT_MASK BIT(1) BIT 323 include/linux/mfd/da9150/registers.h #define DA9150_E_DTYPE_MASK BIT(3) BIT 325 include/linux/mfd/da9150/registers.h #define DA9150_E_ID_MASK BIT(4) BIT 327 include/linux/mfd/da9150/registers.h #define DA9150_E_ADP_MASK BIT(5) BIT 329 include/linux/mfd/da9150/registers.h #define DA9150_E_SESS_END_MASK BIT(6) BIT 331 include/linux/mfd/da9150/registers.h #define DA9150_E_SESS_VLD_MASK BIT(7) BIT 335 include/linux/mfd/da9150/registers.h #define DA9150_E_FG_MASK BIT(0) BIT 337 include/linux/mfd/da9150/registers.h #define DA9150_E_GP_MASK BIT(1) BIT 339 include/linux/mfd/da9150/registers.h #define DA9150_E_TBAT_MASK BIT(2) BIT 341 include/linux/mfd/da9150/registers.h #define DA9150_E_GPIOA_MASK BIT(3) BIT 343 include/linux/mfd/da9150/registers.h #define DA9150_E_GPIOB_MASK BIT(4) BIT 345 include/linux/mfd/da9150/registers.h #define DA9150_E_GPIOC_MASK BIT(5) BIT 347 include/linux/mfd/da9150/registers.h #define DA9150_E_GPIOD_MASK BIT(6) BIT 349 include/linux/mfd/da9150/registers.h #define DA9150_E_GPADC_MASK BIT(7) BIT 353 include/linux/mfd/da9150/registers.h #define DA9150_E_WKUP_MASK BIT(0) BIT 357 include/linux/mfd/da9150/registers.h #define DA9150_M_VBUS_MASK BIT(0) BIT 359 include/linux/mfd/da9150/registers.h #define DA9150_M_CHG_MASK BIT(1) BIT 361 include/linux/mfd/da9150/registers.h #define DA9150_M_TJUNC_MASK BIT(3) BIT 363 include/linux/mfd/da9150/registers.h #define DA9150_M_VFAULT_MASK BIT(4) BIT 367 include/linux/mfd/da9150/registers.h #define DA9150_M_CONF_MASK BIT(0) BIT 369 include/linux/mfd/da9150/registers.h #define DA9150_M_DAT_MASK BIT(1) BIT 371 include/linux/mfd/da9150/registers.h #define DA9150_M_DTYPE_MASK BIT(3) BIT 373 include/linux/mfd/da9150/registers.h #define DA9150_M_ID_MASK BIT(4) BIT 375 include/linux/mfd/da9150/registers.h #define DA9150_M_ADP_MASK BIT(5) BIT 377 include/linux/mfd/da9150/registers.h #define DA9150_M_SESS_END_MASK BIT(6) BIT 379 include/linux/mfd/da9150/registers.h #define DA9150_M_SESS_VLD_MASK BIT(7) BIT 383 include/linux/mfd/da9150/registers.h #define DA9150_M_FG_MASK BIT(0) BIT 385 include/linux/mfd/da9150/registers.h #define DA9150_M_GP_MASK BIT(1) BIT 387 include/linux/mfd/da9150/registers.h #define DA9150_M_TBAT_MASK BIT(2) BIT 389 include/linux/mfd/da9150/registers.h #define DA9150_M_GPIOA_MASK BIT(3) BIT 391 include/linux/mfd/da9150/registers.h #define DA9150_M_GPIOB_MASK BIT(4) BIT 393 include/linux/mfd/da9150/registers.h #define DA9150_M_GPIOC_MASK BIT(5) BIT 395 include/linux/mfd/da9150/registers.h #define DA9150_M_GPIOD_MASK BIT(6) BIT 397 include/linux/mfd/da9150/registers.h #define DA9150_M_GPADC_MASK BIT(7) BIT 401 include/linux/mfd/da9150/registers.h #define DA9150_M_WKUP_MASK BIT(0) BIT 407 include/linux/mfd/da9150/registers.h #define DA9150_WRITE_MODE_MASK BIT(6) BIT 409 include/linux/mfd/da9150/registers.h #define DA9150_REVERT_MASK BIT(7) BIT 419 include/linux/mfd/da9150/registers.h #define DA9150_PS_WAIT_EN_MASK BIT(6) BIT 421 include/linux/mfd/da9150/registers.h #define DA9150_PS_DISABLE_DIRECT_MASK BIT(7) BIT 429 include/linux/mfd/da9150/registers.h #define DA9150_VFAULT_EN_MASK BIT(7) BIT 437 include/linux/mfd/da9150/registers.h #define DA9150_LFOSC_EXT_MASK BIT(0) BIT 439 include/linux/mfd/da9150/registers.h #define DA9150_VDD33_DWN_MASK BIT(1) BIT 441 include/linux/mfd/da9150/registers.h #define DA9150_WKUP_PM_EN_MASK BIT(2) BIT 445 include/linux/mfd/da9150/registers.h #define DA9150_WKUP_CLK32K_EN_MASK BIT(5) BIT 447 include/linux/mfd/da9150/registers.h #define DA9150_DISABLE_DEL_MASK BIT(7) BIT 451 include/linux/mfd/da9150/registers.h #define DA9150_PM_SPKSUP_DIS_MASK BIT(0) BIT 453 include/linux/mfd/da9150/registers.h #define DA9150_PM_MERGE_MASK BIT(1) BIT 455 include/linux/mfd/da9150/registers.h #define DA9150_PM_SR_OFF_MASK BIT(2) BIT 457 include/linux/mfd/da9150/registers.h #define DA9150_PM_TIMEOUT_EN_MASK BIT(3) BIT 461 include/linux/mfd/da9150/registers.h #define DA9150_PM_OUT_DLY_SEL_MASK BIT(7) BIT 465 include/linux/mfd/da9150/registers.h #define DA9150_VDD33_SL_MASK BIT(0) BIT 469 include/linux/mfd/da9150/registers.h #define DA9150_VDD33_EN_MASK BIT(3) BIT 471 include/linux/mfd/da9150/registers.h #define DA9150_GPI_LPM_MASK BIT(6) BIT 473 include/linux/mfd/da9150/registers.h #define DA9150_PM_IF_LPM_MASK BIT(7) BIT 477 include/linux/mfd/da9150/registers.h #define DA9150_LPM_MASK BIT(0) BIT 479 include/linux/mfd/da9150/registers.h #define DA9150_RESET_MASK BIT(1) BIT 481 include/linux/mfd/da9150/registers.h #define DA9150_RESET_USRCONF_EN_MASK BIT(2) BIT 485 include/linux/mfd/da9150/registers.h #define DA9150_DISABLE_MASK BIT(0) BIT 491 include/linux/mfd/da9150/registers.h #define DA9150_GPIOA_PIN_GPO_OD BIT(0) BIT 493 include/linux/mfd/da9150/registers.h #define DA9150_GPIOA_TYPE_MASK BIT(3) BIT 497 include/linux/mfd/da9150/registers.h #define DA9150_GPIOB_PIN_GPO_OD BIT(4) BIT 499 include/linux/mfd/da9150/registers.h #define DA9150_GPIOB_TYPE_MASK BIT(7) BIT 505 include/linux/mfd/da9150/registers.h #define DA9150_GPIOC_PIN_GPO_OD BIT(0) BIT 507 include/linux/mfd/da9150/registers.h #define DA9150_GPIOC_TYPE_MASK BIT(3) BIT 511 include/linux/mfd/da9150/registers.h #define DA9150_GPIOD_PIN_GPO_OD BIT(4) BIT 513 include/linux/mfd/da9150/registers.h #define DA9150_GPIOD_TYPE_MASK BIT(7) BIT 517 include/linux/mfd/da9150/registers.h #define DA9150_GPIOA_MODE_MASK BIT(0) BIT 519 include/linux/mfd/da9150/registers.h #define DA9150_GPIOB_MODE_MASK BIT(1) BIT 521 include/linux/mfd/da9150/registers.h #define DA9150_GPIOC_MODE_MASK BIT(2) BIT 523 include/linux/mfd/da9150/registers.h #define DA9150_GPIOD_MODE_MASK BIT(3) BIT 525 include/linux/mfd/da9150/registers.h #define DA9150_GPIOA_CONT_MASK BIT(4) BIT 527 include/linux/mfd/da9150/registers.h #define DA9150_GPIOB_CONT_MASK BIT(5) BIT 529 include/linux/mfd/da9150/registers.h #define DA9150_GPIOC_CONT_MASK BIT(6) BIT 531 include/linux/mfd/da9150/registers.h #define DA9150_GPIOD_CONT_MASK BIT(7) BIT 537 include/linux/mfd/da9150/registers.h #define DA9150_WAKE_MODE_MASK BIT(2) BIT 539 include/linux/mfd/da9150/registers.h #define DA9150_WAKE_CONT_MASK BIT(3) BIT 541 include/linux/mfd/da9150/registers.h #define DA9150_WAKE_DLY_MASK BIT(4) BIT 545 include/linux/mfd/da9150/registers.h #define DA9150_GPIOA_ANAEN_MASK BIT(0) BIT 547 include/linux/mfd/da9150/registers.h #define DA9150_GPIOB_ANAEN_MASK BIT(1) BIT 549 include/linux/mfd/da9150/registers.h #define DA9150_GPIOC_ANAEN_MASK BIT(2) BIT 551 include/linux/mfd/da9150/registers.h #define DA9150_GPIOD_ANAEN_MASK BIT(3) BIT 561 include/linux/mfd/da9150/registers.h #define DA9150_CHGBL_DBL_MASK BIT(2) BIT 565 include/linux/mfd/da9150/registers.h #define DA9150_CHGBL_FLKR_MASK BIT(5) BIT 573 include/linux/mfd/da9150/registers.h #define DA9150_GPIOA_PUPD_MASK BIT(0) BIT 575 include/linux/mfd/da9150/registers.h #define DA9150_GPIOB_PUPD_MASK BIT(1) BIT 577 include/linux/mfd/da9150/registers.h #define DA9150_GPIOC_PUPD_MASK BIT(2) BIT 579 include/linux/mfd/da9150/registers.h #define DA9150_GPIOD_PUPD_MASK BIT(3) BIT 584 include/linux/mfd/da9150/registers.h #define DA9150_LPM_EN_MASK BIT(7) BIT 588 include/linux/mfd/da9150/registers.h #define DA9150_GPI_V_MASK BIT(0) BIT 590 include/linux/mfd/da9150/registers.h #define DA9150_VDDIO_INT_MASK BIT(1) BIT 594 include/linux/mfd/da9150/registers.h #define DA9150_FAULT_TYPE_MASK BIT(6) BIT 596 include/linux/mfd/da9150/registers.h #define DA9150_NIRQ_PUPD_MASK BIT(7) BIT 600 include/linux/mfd/da9150/registers.h #define DA9150_GPADC_EN_MASK BIT(0) BIT 610 include/linux/mfd/da9150/registers.h #define DA9150_GPADC_RUN_MASK BIT(0) BIT 619 include/linux/mfd/da9150/registers.h #define DA9150_WRITE_MODE_MASK BIT(6) BIT 621 include/linux/mfd/da9150/registers.h #define DA9150_REVERT_MASK BIT(7) BIT 625 include/linux/mfd/da9150/registers.h #define DA9150_PC_DONE_MASK BIT(3) BIT 633 include/linux/mfd/da9150/registers.h #define DA9150_NIRQ_VDD_MASK BIT(1) BIT 635 include/linux/mfd/da9150/registers.h #define DA9150_NIRQ_PIN_MASK BIT(2) BIT 637 include/linux/mfd/da9150/registers.h #define DA9150_NIRQ_TYPE_MASK BIT(3) BIT 639 include/linux/mfd/da9150/registers.h #define DA9150_PM_IF_V_MASK BIT(4) BIT 641 include/linux/mfd/da9150/registers.h #define DA9150_PM_IF_FMP_MASK BIT(5) BIT 643 include/linux/mfd/da9150/registers.h #define DA9150_PM_IF_HSM_MASK BIT(6) BIT 647 include/linux/mfd/da9150/registers.h #define DA9150_NIRQ_MODE_MASK BIT(1) BIT 655 include/linux/mfd/da9150/registers.h #define DA9150_DCD_STAT_MASK BIT(0) BIT 661 include/linux/mfd/da9150/registers.h #define DA9150_DP_STAT_MASK BIT(5) BIT 663 include/linux/mfd/da9150/registers.h #define DA9150_DM_STAT_MASK BIT(6) BIT 667 include/linux/mfd/da9150/registers.h #define DA9150_DP_COMP_MASK BIT(1) BIT 669 include/linux/mfd/da9150/registers.h #define DA9150_DM_COMP_MASK BIT(2) BIT 671 include/linux/mfd/da9150/registers.h #define DA9150_ADP_SNS_COMP_MASK BIT(3) BIT 673 include/linux/mfd/da9150/registers.h #define DA9150_ADP_PRB_COMP_MASK BIT(4) BIT 675 include/linux/mfd/da9150/registers.h #define DA9150_ID_COMP_MASK BIT(5) BIT 679 include/linux/mfd/da9150/registers.h #define DA9150_AID_DAT_MASK BIT(0) BIT 681 include/linux/mfd/da9150/registers.h #define DA9150_AID_ID_MASK BIT(1) BIT 683 include/linux/mfd/da9150/registers.h #define DA9150_AID_TRIG_MASK BIT(2) BIT 688 include/linux/mfd/da9150/registers.h #define DA9150_VB_MODE_VB_SESS BIT(0) BIT 691 include/linux/mfd/da9150/registers.h #define DA9150_TADP_PRB_MASK BIT(2) BIT 693 include/linux/mfd/da9150/registers.h #define DA9150_DAT_RPD_EXT_MASK BIT(5) BIT 695 include/linux/mfd/da9150/registers.h #define DA9150_CONF_RPD_MASK BIT(6) BIT 697 include/linux/mfd/da9150/registers.h #define DA9150_CONF_SRP_MASK BIT(7) BIT 703 include/linux/mfd/da9150/registers.h #define DA9150_AID_EXT_POL_MASK BIT(2) BIT 709 include/linux/mfd/da9150/registers.h #define DA9150_CONF_DBP_MASK BIT(5) BIT 715 include/linux/mfd/da9150/registers.h #define DA9150_CONF_GPIOA_MASK BIT(5) BIT 717 include/linux/mfd/da9150/registers.h #define DA9150_CONF_GPIOB_MASK BIT(6) BIT 719 include/linux/mfd/da9150/registers.h #define DA9150_AID_VB_MASK BIT(7) BIT 727 include/linux/mfd/da9150/registers.h #define DA9150_AID_CR_DIS_MASK BIT(7) BIT 733 include/linux/mfd/da9150/registers.h #define DA9150_AID_UNCLAMP_MASK BIT(5) BIT 741 include/linux/mfd/da9150/registers.h #define DA9150_DAT_SWP_MASK BIT(6) BIT 743 include/linux/mfd/da9150/registers.h #define DA9150_DAT_CLAMP_EXT_MASK BIT(7) BIT 749 include/linux/mfd/da9150/registers.h #define DA9150_RID_CONV_MASK BIT(3) BIT 766 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_MODE_CHG BIT(0) BIT 771 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_SUSP_MASK BIT(4) BIT 773 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_PWM_MASK BIT(5) BIT 775 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_ISO_MASK BIT(6) BIT 777 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_LDO_MASK BIT(7) BIT 783 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_IMAX_MASK BIT(5) BIT 791 include/linux/mfd/da9150/registers.h #define DA9150_VBUS_FAULT_DIS_MASK BIT(6) BIT 793 include/linux/mfd/da9150/registers.h #define DA9150_OTG_FAULT_DIS_MASK BIT(7) BIT 797 include/linux/mfd/da9150/registers.h #define DA9150_CHG_EN_MASK BIT(0) BIT 815 include/linux/mfd/da9150/registers.h #define DA9150_CHG_TCTR_MODE_MASK BIT(4) BIT 829 include/linux/mfd/da9150/registers.h #define DA9150_TBAT_TQA_EN_MASK BIT(6) BIT 831 include/linux/mfd/da9150/registers.h #define DA9150_TBAT_TDP_EN_MASK BIT(7) BIT 861 include/linux/mfd/da9150/registers.h #define DA9150_CHG_LPM_MASK BIT(5) BIT 863 include/linux/mfd/da9150/registers.h #define DA9150_CHG_NBLO_MASK BIT(6) BIT 865 include/linux/mfd/da9150/registers.h #define DA9150_EBS_EN_MASK BIT(7) BIT 899 include/linux/mfd/da9150/registers.h #define DA9150_WRITE_MODE_MASK BIT(6) BIT 901 include/linux/mfd/da9150/registers.h #define DA9150_REVERT_MASK BIT(7) BIT 907 include/linux/mfd/da9150/registers.h #define DA9150_WRITE_MODE_MASK BIT(6) BIT 909 include/linux/mfd/da9150/registers.h #define DA9150_REVERT_MASK BIT(7) BIT 915 include/linux/mfd/da9150/registers.h #define DA9150_WRITE_MODE_MASK BIT(6) BIT 917 include/linux/mfd/da9150/registers.h #define DA9150_REVERT_MASK BIT(7) BIT 923 include/linux/mfd/da9150/registers.h #define DA9150_WRITE_MODE_MASK BIT(6) BIT 925 include/linux/mfd/da9150/registers.h #define DA9150_REVERT_MASK BIT(7) BIT 931 include/linux/mfd/da9150/registers.h #define DA9150_CORE_LOCKUP_MASK BIT(2) BIT 935 include/linux/mfd/da9150/registers.h #define DA9150_CORE_RESET_MASK BIT(0) BIT 937 include/linux/mfd/da9150/registers.h #define DA9150_CORE_STOP_MASK BIT(1) BIT 943 include/linux/mfd/da9150/registers.h #define DA9150_WDT_AUTO_START_MASK BIT(2) BIT 945 include/linux/mfd/da9150/registers.h #define DA9150_WDT_AUTO_LOCK_MASK BIT(3) BIT 947 include/linux/mfd/da9150/registers.h #define DA9150_WDT_HLT_NO_CLK_MASK BIT(4) BIT 955 include/linux/mfd/da9150/registers.h #define DA9150_BOOTLD_EN_MASK BIT(0) BIT 957 include/linux/mfd/da9150/registers.h #define DA9150_CORE_EN_MASK BIT(2) BIT 961 include/linux/mfd/da9150/registers.h #define DA9150_DEEP_SLEEP_EN_MASK BIT(7) BIT 993 include/linux/mfd/da9150/registers.h #define DA9150_FW_FWDL_ERR_MASK BIT(7) BIT 997 include/linux/mfd/da9150/registers.h #define DA9150_FW_FWDL_EN_MASK BIT(0) BIT 999 include/linux/mfd/da9150/registers.h #define DA9150_FG_QIF_EN_MASK BIT(1) BIT 1033 include/linux/mfd/da9150/registers.h #define DA9150_GPADC_CEN_MASK BIT(0) BIT 1043 include/linux/mfd/da9150/registers.h #define DA9150_GPADC_CRUN_MASK BIT(0) BIT 1049 include/linux/mfd/da9150/registers.h #define DA9150_CC_EN_MASK BIT(0) BIT 1055 include/linux/mfd/da9150/registers.h #define DA9150_CC_ENDLESS_MODE_MASK BIT(7) BIT 1081 include/linux/mfd/da9150/registers.h #define DA9150_TAUX_EN_MASK BIT(0) BIT 1083 include/linux/mfd/da9150/registers.h #define DA9150_TAUX_MOD_MASK BIT(1) BIT 1085 include/linux/mfd/da9150/registers.h #define DA9150_TAUX_UPDATE_MASK BIT(2) BIT 1121 include/linux/mfd/da9150/registers.h #define DA9150_BIF_ISRC_EN_MASK BIT(0) BIT 1125 include/linux/mfd/da9150/registers.h #define DA9150_TBAT_EN_MASK BIT(0) BIT 1127 include/linux/mfd/da9150/registers.h #define DA9150_TBAT_SW1_MASK BIT(1) BIT 1129 include/linux/mfd/da9150/registers.h #define DA9150_TBAT_SW2_MASK BIT(2) BIT 1133 include/linux/mfd/da9150/registers.h #define DA9150_TBAT_SW_FRC_MASK BIT(0) BIT 1135 include/linux/mfd/da9150/registers.h #define DA9150_TBAT_STAT_SW1_MASK BIT(1) BIT 1137 include/linux/mfd/da9150/registers.h #define DA9150_TBAT_STAT_SW2_MASK BIT(2) BIT 1139 include/linux/mfd/da9150/registers.h #define DA9150_TBAT_HIGH_CURR_MASK BIT(3) BIT 1147 include/linux/mfd/da9150/registers.h #define DA9150_TBAT_RES_DIS_MASK BIT(0) BIT 39 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_RSTADC BIT(0) BIT 40 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_RSTDAC BIT(1) BIT 41 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4) BIT 42 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5) BIT 43 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6) BIT 44 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7) BIT 45 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_RFIFOEN BIT(8) BIT 46 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_RFIFOCL BIT(9) BIT 47 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10) BIT 48 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_WFIFOEN BIT(12) BIT 49 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_WFIFOCL BIT(13) BIT 50 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14) BIT 54 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_INT_RDRDY_MASK BIT(0) BIT 55 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_INT_RERROVF_MASK BIT(1) BIT 56 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_INT_RERRUDR_MASK BIT(2) BIT 57 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_INT_WDREQ_MASK BIT(3) BIT 58 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4) BIT 59 include/linux/mfd/davinci_voicecodec.h #define DAVINCI_VC_INT_WERRUDR_MASK BIT(5) BIT 20 include/linux/mfd/db8500-prcmu.h #define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3) BIT 23 include/linux/mfd/db8500-prcmu.h #define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0) BIT 24 include/linux/mfd/db8500-prcmu.h #define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1) BIT 25 include/linux/mfd/db8500-prcmu.h #define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2) BIT 461 include/linux/mfd/db8500-prcmu.h #define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0) BIT 462 include/linux/mfd/db8500-prcmu.h #define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1) BIT 34 include/linux/mfd/dbx500-prcmu.h #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) BIT 30 include/linux/mfd/dm355evm_msp.h # define MSP_STATUS_BAD_OFFSET BIT(0) BIT 31 include/linux/mfd/dm355evm_msp.h # define MSP_STATUS_BAD_COMMAND BIT(1) BIT 32 include/linux/mfd/dm355evm_msp.h # define MSP_STATUS_POWER_ERROR BIT(2) BIT 33 include/linux/mfd/dm355evm_msp.h # define MSP_STATUS_RXBUF_OVERRUN BIT(3) BIT 35 include/linux/mfd/dm355evm_msp.h # define MSP_RESET_DC5 BIT(0) BIT 36 include/linux/mfd/dm355evm_msp.h # define MSP_RESET_TVP5154 BIT(2) BIT 37 include/linux/mfd/dm355evm_msp.h # define MSP_RESET_IMAGER BIT(3) BIT 38 include/linux/mfd/dm355evm_msp.h # define MSP_RESET_ETHERNET BIT(4) BIT 39 include/linux/mfd/dm355evm_msp.h # define MSP_RESET_SYS BIT(5) BIT 40 include/linux/mfd/dm355evm_msp.h # define MSP_RESET_AIC33 BIT(7) BIT 45 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH1_SW6_1 BIT(0) BIT 46 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH1_SW6_2 BIT(1) BIT 47 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH1_SW6_3 BIT(2) BIT 48 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH1_SW6_4 BIT(3) BIT 49 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH1_J1 BIT(4) /* NTSC/PAL */ BIT 50 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH1_MSP_INT BIT(5) /* active low */ BIT 52 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH2_SW10 BIT(3) BIT 53 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH2_SW11 BIT(4) BIT 54 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH2_SW12 BIT(5) BIT 55 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH2_SW13 BIT(6) BIT 56 include/linux/mfd/dm355evm_msp.h # define MSP_SWITCH2_SW14 BIT(7) BIT 58 include/linux/mfd/dm355evm_msp.h # define MSP_SDMMC_0_WP BIT(1) BIT 59 include/linux/mfd/dm355evm_msp.h # define MSP_SDMMC_0_CD BIT(2) /* active low */ BIT 60 include/linux/mfd/dm355evm_msp.h # define MSP_SDMMC_1_WP BIT(3) BIT 61 include/linux/mfd/dm355evm_msp.h # define MSP_SDMMC_1_CD BIT(4) /* active low */ BIT 64 include/linux/mfd/dm355evm_msp.h # define MSP_VIDEO_IMAGER BIT(7) /* low == tvp5146 */ BIT 43 include/linux/mfd/hi655x-pmic.h #define RESERVE_INT_MASK BIT(RESERVE_INT) BIT 44 include/linux/mfd/hi655x-pmic.h #define PWRON_D20R_INT_MASK BIT(PWRON_D20R_INT) BIT 45 include/linux/mfd/hi655x-pmic.h #define PWRON_D20F_INT_MASK BIT(PWRON_D20F_INT) BIT 46 include/linux/mfd/hi655x-pmic.h #define PWRON_D4SR_INT_MASK BIT(PWRON_D4SR_INT) BIT 47 include/linux/mfd/hi655x-pmic.h #define VSYS_6P0_D200UR_INT_MASK BIT(VSYS_6P0_D200UR_INT) BIT 48 include/linux/mfd/hi655x-pmic.h #define VSYS_UV_D3R_INT_MASK BIT(VSYS_UV_D3R_INT) BIT 49 include/linux/mfd/hi655x-pmic.h #define VSYS_2P5_R_INT_MASK BIT(VSYS_2P5_R_INT) BIT 50 include/linux/mfd/hi655x-pmic.h #define OTMP_D1R_INT_MASK BIT(OTMP_D1R_INT) BIT 32 include/linux/mfd/imx25-tsadc.h #define MX25_TGCR_PDBEN BIT(24) BIT 33 include/linux/mfd/imx25-tsadc.h #define MX25_TGCR_PDEN BIT(23) BIT 36 include/linux/mfd/imx25-tsadc.h #define MX25_TGCR_INTREFEN BIT(10) BIT 40 include/linux/mfd/imx25-tsadc.h #define MX25_TGCR_STLC BIT(5) BIT 41 include/linux/mfd/imx25-tsadc.h #define MX25_TGCR_SLPC BIT(4) BIT 42 include/linux/mfd/imx25-tsadc.h #define MX25_TGCR_FUNC_RST BIT(2) BIT 43 include/linux/mfd/imx25-tsadc.h #define MX25_TGCR_TSC_RST BIT(1) BIT 44 include/linux/mfd/imx25-tsadc.h #define MX25_TGCR_CLK_EN BIT(0) BIT 47 include/linux/mfd/imx25-tsadc.h #define MX25_TGSR_SLP_INT BIT(2) BIT 48 include/linux/mfd/imx25-tsadc.h #define MX25_TGSR_GCQ_INT BIT(1) BIT 49 include/linux/mfd/imx25-tsadc.h #define MX25_TGSR_TCQ_INT BIT(0) BIT 61 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CR_PDCFG_LEVEL BIT(19) BIT 62 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CR_PDMSK BIT(18) BIT 63 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CR_FRST BIT(17) BIT 64 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CR_QRST BIT(16) BIT 71 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CR_RPT BIT(3) BIT 72 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CR_FQS BIT(2) BIT 79 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_SR_FDRY BIT(15) BIT 80 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_SR_FULL BIT(14) BIT 81 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_SR_EMPT BIT(13) BIT 83 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_SR_FRR BIT(6) BIT 84 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_SR_FUR BIT(5) BIT 85 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_SR_FOR BIT(4) BIT 86 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_SR_EOQ BIT(1) BIT 87 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_SR_PD BIT(0) BIT 90 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_FDRY_DMA BIT(31) BIT 91 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_FER_DMA BIT(22) BIT 92 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_FUR_DMA BIT(21) BIT 93 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_FOR_DMA BIT(20) BIT 94 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_EOQ_DMA BIT(17) BIT 95 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_PD_DMA BIT(16) BIT 96 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_FDRY_IRQ BIT(15) BIT 97 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_FER_IRQ BIT(6) BIT 98 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_FUR_IRQ BIT(5) BIT 99 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_FOR_IRQ BIT(4) BIT 100 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_EOQ_IRQ BIT(1) BIT 101 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_MR_PD_IRQ BIT(0) BIT 44 include/linux/mfd/ingenic-tcu.h #define TCU_TCSR_PWM_SD BIT(9) /* 0: Shutdown gracefully 1: abruptly */ BIT 45 include/linux/mfd/ingenic-tcu.h #define TCU_TCSR_PWM_INITL_HIGH BIT(8) /* Sets the initial output level */ BIT 46 include/linux/mfd/ingenic-tcu.h #define TCU_TCSR_PWM_EN BIT(7) /* PWM pin output enable */ BIT 48 include/linux/mfd/ingenic-tcu.h #define TCU_WDT_TCER_TCEN BIT(0) /* Watchdog timer enable */ BIT 51 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_LVL1_PWRBTN BIT(0) /* power button */ BIT 52 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_LVL1_TMU BIT(1) /* time management unit */ BIT 53 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_LVL1_THRM BIT(2) /* thermal */ BIT 54 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_LVL1_BCU BIT(3) /* burst control unit */ BIT 55 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_LVL1_ADC BIT(4) /* ADC */ BIT 56 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_LVL1_CHGR BIT(5) /* charger */ BIT 57 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_LVL1_GPIO BIT(6) /* GPIO */ BIT 58 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_LVL1_CRIT BIT(7) /* critical event */ BIT 61 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_PBIRQ_PBTN BIT(0) BIT 62 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_PBIRQ_UBTN BIT(1) BIT 65 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_ADCIRQ_BATTEMP BIT(2) BIT 66 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_ADCIRQ_SYSTEMP BIT(3) BIT 67 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_ADCIRQ_BATTID BIT(4) BIT 68 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_ADCIRQ_VIBATT BIT(5) BIT 69 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_ADCIRQ_CCTICK BIT(7) BIT 72 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_CHGRIRQ_BAT0ALRT BIT(4) BIT 73 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_CHGRIRQ_BAT1ALRT BIT(5) BIT 74 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_CHGRIRQ_BATCRIT BIT(6) BIT 76 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_CHGRIRQ_VBUSDET BIT(0) BIT 77 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_CHGRIRQ_DCDET BIT(1) BIT 78 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_CHGRIRQ_BATTDET BIT(2) BIT 79 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_CHGRIRQ_USBIDDET BIT(3) BIT 76 include/linux/mfd/lp873x.h #define LP873X_BUCK0_CTRL_1_BUCK0_FPWM BIT(3) BIT 77 include/linux/mfd/lp873x.h #define LP873X_BUCK0_CTRL_1_BUCK0_RDIS_EN BIT(2) BIT 78 include/linux/mfd/lp873x.h #define LP873X_BUCK0_CTRL_1_BUCK0_EN_PIN_CTRL BIT(1) BIT 79 include/linux/mfd/lp873x.h #define LP873X_BUCK0_CTRL_1_BUCK0_EN BIT(0) BIT 84 include/linux/mfd/lp873x.h #define LP873X_BUCK1_CTRL_1_BUCK1_FPWM BIT(3) BIT 85 include/linux/mfd/lp873x.h #define LP873X_BUCK1_CTRL_1_BUCK1_RDIS_EN BIT(2) BIT 86 include/linux/mfd/lp873x.h #define LP873X_BUCK1_CTRL_1_BUCK1_EN_PIN_CTRL BIT(1) BIT 87 include/linux/mfd/lp873x.h #define LP873X_BUCK1_CTRL_1_BUCK1_EN BIT(0) BIT 96 include/linux/mfd/lp873x.h #define LP873X_LDO0_CTRL_LDO0_RDIS_EN BIT(2) BIT 97 include/linux/mfd/lp873x.h #define LP873X_LDO0_CTRL_LDO0_EN_PIN_CTRL BIT(1) BIT 98 include/linux/mfd/lp873x.h #define LP873X_LDO0_CTRL_LDO0_EN BIT(0) BIT 100 include/linux/mfd/lp873x.h #define LP873X_LDO1_CTRL_LDO1_RDIS_EN BIT(2) BIT 101 include/linux/mfd/lp873x.h #define LP873X_LDO1_CTRL_LDO1_EN_PIN_CTRL BIT(1) BIT 102 include/linux/mfd/lp873x.h #define LP873X_LDO1_CTRL_LDO1_EN BIT(0) BIT 126 include/linux/mfd/lp873x.h #define LP873X_GPO_CTRL_GPO2_OD BIT(6) BIT 127 include/linux/mfd/lp873x.h #define LP873X_GPO_CTRL_GPO2_EN_PIN_CTRL BIT(5) BIT 128 include/linux/mfd/lp873x.h #define LP873X_GPO_CTRL_GPO2_EN BIT(4) BIT 129 include/linux/mfd/lp873x.h #define LP873X_GPO_CTRL_GPO_OD BIT(2) BIT 130 include/linux/mfd/lp873x.h #define LP873X_GPO_CTRL_GPO_EN_PIN_CTRL BIT(1) BIT 131 include/linux/mfd/lp873x.h #define LP873X_GPO_CTRL_GPO_EN BIT(0) BIT 133 include/linux/mfd/lp873x.h #define LP873X_CONFIG_SU_DELAY_SEL BIT(6) BIT 134 include/linux/mfd/lp873x.h #define LP873X_CONFIG_SD_DELAY_SEL BIT(5) BIT 135 include/linux/mfd/lp873x.h #define LP873X_CONFIG_CLKIN_PIN_SEL BIT(4) BIT 136 include/linux/mfd/lp873x.h #define LP873X_CONFIG_CLKIN_PD BIT(3) BIT 137 include/linux/mfd/lp873x.h #define LP873X_CONFIG_EN_PD BIT(2) BIT 138 include/linux/mfd/lp873x.h #define LP873X_CONFIG_TDIE_WARN_LEVEL BIT(1) BIT 139 include/linux/mfd/lp873x.h #define LP873X_EN_SPREAD_SPEC BIT(0) BIT 141 include/linux/mfd/lp873x.h #define LP873X_PLL_CTRL_EN_PLL BIT(6) BIT 144 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL1_PGOOD_POL BIT(7) BIT 145 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL1_PGOOD_OD BIT(6) BIT 146 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL1_PGOOD_WINDOW_LDO BIT(5) BIT 147 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL1_PGOOD_WINDOWN_BUCK BIT(4) BIT 148 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL1_PGOOD_EN_PGOOD_LDO1 BIT(3) BIT 149 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL1_PGOOD_EN_PGOOD_LDO0 BIT(2) BIT 150 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL1_PGOOD_EN_PGOOD_BUCK1 BIT(1) BIT 151 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL1_PGOOD_EN_PGOOD_BUCK0 BIT(0) BIT 153 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL2_EN_PGOOD_TWARN BIT(2) BIT 154 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL2_EN_PG_FAULT_GATE BIT(1) BIT 155 include/linux/mfd/lp873x.h #define LP873X_PGOOD_CTRL2_PGOOD_MODE BIT(0) BIT 157 include/linux/mfd/lp873x.h #define LP873X_PG_FAULT_PG_FAULT_LDO1 BIT(3) BIT 158 include/linux/mfd/lp873x.h #define LP873X_PG_FAULT_PG_FAULT_LDO0 BIT(2) BIT 159 include/linux/mfd/lp873x.h #define LP873X_PG_FAULT_PG_FAULT_BUCK1 BIT(1) BIT 160 include/linux/mfd/lp873x.h #define LP873X_PG_FAULT_PG_FAULT_BUCK0 BIT(0) BIT 162 include/linux/mfd/lp873x.h #define LP873X_RESET_SW_RESET BIT(0) BIT 164 include/linux/mfd/lp873x.h #define LP873X_INT_TOP_1_PGOOD_INT BIT(7) BIT 165 include/linux/mfd/lp873x.h #define LP873X_INT_TOP_1_LDO_INT BIT(6) BIT 166 include/linux/mfd/lp873x.h #define LP873X_INT_TOP_1_BUCK_INT BIT(5) BIT 167 include/linux/mfd/lp873x.h #define LP873X_INT_TOP_1_SYNC_CLK_INT BIT(4) BIT 168 include/linux/mfd/lp873x.h #define LP873X_INT_TOP_1_TDIE_SD_INT BIT(3) BIT 169 include/linux/mfd/lp873x.h #define LP873X_INT_TOP_1_TDIE_WARN_INT BIT(2) BIT 170 include/linux/mfd/lp873x.h #define LP873X_INT_TOP_1_OVP_INT BIT(1) BIT 171 include/linux/mfd/lp873x.h #define LP873X_INT_TOP_1_I_MEAS_INT BIT(0) BIT 173 include/linux/mfd/lp873x.h #define LP873X_INT_TOP_2_RESET_REG_INT BIT(0) BIT 175 include/linux/mfd/lp873x.h #define LP873X_INT_BUCK_BUCK1_PG_INT BIT(6) BIT 176 include/linux/mfd/lp873x.h #define LP873X_INT_BUCK_BUCK1_SC_INT BIT(5) BIT 177 include/linux/mfd/lp873x.h #define LP873X_INT_BUCK_BUCK1_ILIM_INT BIT(4) BIT 178 include/linux/mfd/lp873x.h #define LP873X_INT_BUCK_BUCK0_PG_INT BIT(2) BIT 179 include/linux/mfd/lp873x.h #define LP873X_INT_BUCK_BUCK0_SC_INT BIT(1) BIT 180 include/linux/mfd/lp873x.h #define LP873X_INT_BUCK_BUCK0_ILIM_INT BIT(0) BIT 182 include/linux/mfd/lp873x.h #define LP873X_INT_LDO_LDO1_PG_INT BIT(6) BIT 183 include/linux/mfd/lp873x.h #define LP873X_INT_LDO_LDO1_SC_INT BIT(5) BIT 184 include/linux/mfd/lp873x.h #define LP873X_INT_LDO_LDO1_ILIM_INT BIT(4) BIT 185 include/linux/mfd/lp873x.h #define LP873X_INT_LDO_LDO0_PG_INT BIT(2) BIT 186 include/linux/mfd/lp873x.h #define LP873X_INT_LDO_LDO0_SC_INT BIT(1) BIT 187 include/linux/mfd/lp873x.h #define LP873X_INT_LDO_LDO0_ILIM_INT BIT(0) BIT 189 include/linux/mfd/lp873x.h #define LP873X_TOP_STAT_PGOOD_STAT BIT(7) BIT 190 include/linux/mfd/lp873x.h #define LP873X_TOP_STAT_SYNC_CLK_STAT BIT(4) BIT 191 include/linux/mfd/lp873x.h #define LP873X_TOP_STAT_TDIE_SD_STAT BIT(3) BIT 192 include/linux/mfd/lp873x.h #define LP873X_TOP_STAT_TDIE_WARN_STAT BIT(2) BIT 193 include/linux/mfd/lp873x.h #define LP873X_TOP_STAT_OVP_STAT BIT(1) BIT 195 include/linux/mfd/lp873x.h #define LP873X_BUCK_STAT_BUCK1_STAT BIT(7) BIT 196 include/linux/mfd/lp873x.h #define LP873X_BUCK_STAT_BUCK1_PG_STAT BIT(6) BIT 197 include/linux/mfd/lp873x.h #define LP873X_BUCK_STAT_BUCK1_ILIM_STAT BIT(4) BIT 198 include/linux/mfd/lp873x.h #define LP873X_BUCK_STAT_BUCK0_STAT BIT(3) BIT 199 include/linux/mfd/lp873x.h #define LP873X_BUCK_STAT_BUCK0_PG_STAT BIT(2) BIT 200 include/linux/mfd/lp873x.h #define LP873X_BUCK_STAT_BUCK0_ILIM_STAT BIT(0) BIT 202 include/linux/mfd/lp873x.h #define LP873X_LDO_STAT_LDO1_STAT BIT(7) BIT 203 include/linux/mfd/lp873x.h #define LP873X_LDO_STAT_LDO1_PG_STAT BIT(6) BIT 204 include/linux/mfd/lp873x.h #define LP873X_LDO_STAT_LDO1_ILIM_STAT BIT(4) BIT 205 include/linux/mfd/lp873x.h #define LP873X_LDO_STAT_LDO0_STAT BIT(3) BIT 206 include/linux/mfd/lp873x.h #define LP873X_LDO_STAT_LDO0_PG_STAT BIT(2) BIT 207 include/linux/mfd/lp873x.h #define LP873X_LDO_STAT_LDO0_ILIM_STAT BIT(0) BIT 209 include/linux/mfd/lp873x.h #define LP873X_TOP_MASK_1_PGOOD_INT_MASK BIT(7) BIT 210 include/linux/mfd/lp873x.h #define LP873X_TOP_MASK_1_SYNC_CLK_MASK BIT(4) BIT 211 include/linux/mfd/lp873x.h #define LP873X_TOP_MASK_1_TDIE_WARN_MASK BIT(2) BIT 212 include/linux/mfd/lp873x.h #define LP873X_TOP_MASK_1_I_MEAS_MASK BIT(0) BIT 214 include/linux/mfd/lp873x.h #define LP873X_TOP_MASK_2_RESET_REG_MASK BIT(0) BIT 216 include/linux/mfd/lp873x.h #define LP873X_BUCK_MASK_BUCK1_PGF_MASK BIT(7) BIT 217 include/linux/mfd/lp873x.h #define LP873X_BUCK_MASK_BUCK1_PGR_MASK BIT(6) BIT 218 include/linux/mfd/lp873x.h #define LP873X_BUCK_MASK_BUCK1_ILIM_MASK BIT(4) BIT 219 include/linux/mfd/lp873x.h #define LP873X_BUCK_MASK_BUCK0_PGF_MASK BIT(3) BIT 220 include/linux/mfd/lp873x.h #define LP873X_BUCK_MASK_BUCK0_PGR_MASK BIT(2) BIT 221 include/linux/mfd/lp873x.h #define LP873X_BUCK_MASK_BUCK0_ILIM_MASK BIT(0) BIT 223 include/linux/mfd/lp873x.h #define LP873X_LDO_MASK_LDO1_PGF_MASK BIT(7) BIT 224 include/linux/mfd/lp873x.h #define LP873X_LDO_MASK_LDO1_PGR_MASK BIT(6) BIT 225 include/linux/mfd/lp873x.h #define LP873X_LDO_MASK_LDO1_ILIM_MASK BIT(4) BIT 226 include/linux/mfd/lp873x.h #define LP873X_LDO_MASK_LDO0_PGF_MASK BIT(3) BIT 227 include/linux/mfd/lp873x.h #define LP873X_LDO_MASK_LDO0_PGR_MASK BIT(2) BIT 228 include/linux/mfd/lp873x.h #define LP873X_LDO_MASK_LDO0_ILIM_MASK BIT(0) BIT 230 include/linux/mfd/lp873x.h #define LP873X_SEL_I_LOAD_CURRENT_BUCK_SELECT BIT(0) BIT 232 include/linux/mfd/lp873x.h #define LP873X_I_LOAD_2_BUCK_LOAD_CURRENT BIT(0) BIT 96 include/linux/mfd/lp87565.h #define LP87565_BUCK_CTRL_1_EN BIT(7) BIT 97 include/linux/mfd/lp87565.h #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6) BIT 100 include/linux/mfd/lp87565.h #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3) BIT 101 include/linux/mfd/lp87565.h #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2) BIT 102 include/linux/mfd/lp87565.h #define LP87565_BUCK_CTRL_1_FPWM BIT(1) BIT 104 include/linux/mfd/lp87565.h #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0) BIT 118 include/linux/mfd/lp87565.h #define LP87565_RESET_SW_RESET BIT(0) BIT 120 include/linux/mfd/lp87565.h #define LP87565_CONFIG_DOUBLE_DELAY BIT(7) BIT 121 include/linux/mfd/lp87565.h #define LP87565_CONFIG_CLKIN_PD BIT(6) BIT 122 include/linux/mfd/lp87565.h #define LP87565_CONFIG_EN4_PD BIT(5) BIT 123 include/linux/mfd/lp87565.h #define LP87565_CONFIG_EN3_PD BIT(4) BIT 124 include/linux/mfd/lp87565.h #define LP87565_CONFIG_TDIE_WARN_LEVEL BIT(3) BIT 125 include/linux/mfd/lp87565.h #define LP87565_CONFIG_EN2_PD BIT(2) BIT 126 include/linux/mfd/lp87565.h #define LP87565_CONFIG_EN1_PD BIT(1) BIT 128 include/linux/mfd/lp87565.h #define LP87565_INT_GPIO BIT(7) BIT 129 include/linux/mfd/lp87565.h #define LP87565_INT_BUCK23 BIT(6) BIT 130 include/linux/mfd/lp87565.h #define LP87565_INT_BUCK01 BIT(5) BIT 131 include/linux/mfd/lp87565.h #define LP87565_NO_SYNC_CLK BIT(4) BIT 132 include/linux/mfd/lp87565.h #define LP87565_TDIE_SD BIT(3) BIT 133 include/linux/mfd/lp87565.h #define LP87565_TDIE_WARN BIT(2) BIT 134 include/linux/mfd/lp87565.h #define LP87565_INT_OVP BIT(1) BIT 135 include/linux/mfd/lp87565.h #define LP87565_I_LOAD_READY BIT(0) BIT 137 include/linux/mfd/lp87565.h #define LP87565_INT_TOP2_RESET_REG BIT(0) BIT 139 include/linux/mfd/lp87565.h #define LP87565_BUCK1_PG_INT BIT(6) BIT 140 include/linux/mfd/lp87565.h #define LP87565_BUCK1_SC_INT BIT(5) BIT 141 include/linux/mfd/lp87565.h #define LP87565_BUCK1_ILIM_INT BIT(4) BIT 142 include/linux/mfd/lp87565.h #define LP87565_BUCK0_PG_INT BIT(2) BIT 143 include/linux/mfd/lp87565.h #define LP87565_BUCK0_SC_INT BIT(1) BIT 144 include/linux/mfd/lp87565.h #define LP87565_BUCK0_ILIM_INT BIT(0) BIT 146 include/linux/mfd/lp87565.h #define LP87565_BUCK3_PG_INT BIT(6) BIT 147 include/linux/mfd/lp87565.h #define LP87565_BUCK3_SC_INT BIT(5) BIT 148 include/linux/mfd/lp87565.h #define LP87565_BUCK3_ILIM_INT BIT(4) BIT 149 include/linux/mfd/lp87565.h #define LP87565_BUCK2_PG_INT BIT(2) BIT 150 include/linux/mfd/lp87565.h #define LP87565_BUCK2_SC_INT BIT(1) BIT 151 include/linux/mfd/lp87565.h #define LP87565_BUCK2_ILIM_INT BIT(0) BIT 153 include/linux/mfd/lp87565.h #define LP87565_SYNC_CLK_STAT BIT(4) BIT 154 include/linux/mfd/lp87565.h #define LP87565_TDIE_SD_STAT BIT(3) BIT 155 include/linux/mfd/lp87565.h #define LP87565_TDIE_WARN_STAT BIT(2) BIT 156 include/linux/mfd/lp87565.h #define LP87565_OVP_STAT BIT(1) BIT 158 include/linux/mfd/lp87565.h #define LP87565_BUCK1_STAT BIT(7) BIT 159 include/linux/mfd/lp87565.h #define LP87565_BUCK1_PG_STAT BIT(6) BIT 160 include/linux/mfd/lp87565.h #define LP87565_BUCK1_ILIM_STAT BIT(4) BIT 161 include/linux/mfd/lp87565.h #define LP87565_BUCK0_STAT BIT(3) BIT 162 include/linux/mfd/lp87565.h #define LP87565_BUCK0_PG_STAT BIT(2) BIT 163 include/linux/mfd/lp87565.h #define LP87565_BUCK0_ILIM_STAT BIT(0) BIT 165 include/linux/mfd/lp87565.h #define LP87565_BUCK3_STAT BIT(7) BIT 166 include/linux/mfd/lp87565.h #define LP87565_BUCK3_PG_STAT BIT(6) BIT 167 include/linux/mfd/lp87565.h #define LP87565_BUCK3_ILIM_STAT BIT(4) BIT 168 include/linux/mfd/lp87565.h #define LP87565_BUCK2_STAT BIT(3) BIT 169 include/linux/mfd/lp87565.h #define LP87565_BUCK2_PG_STAT BIT(2) BIT 170 include/linux/mfd/lp87565.h #define LP87565_BUCK2_ILIM_STAT BIT(0) BIT 172 include/linux/mfd/lp87565.h #define LPL87565_GPIO_MASK BIT(7) BIT 173 include/linux/mfd/lp87565.h #define LPL87565_SYNC_CLK_MASK BIT(4) BIT 174 include/linux/mfd/lp87565.h #define LPL87565_TDIE_WARN_MASK BIT(2) BIT 175 include/linux/mfd/lp87565.h #define LPL87565_I_LOAD_READY_MASK BIT(0) BIT 177 include/linux/mfd/lp87565.h #define LPL87565_RESET_REG_MASK BIT(0) BIT 179 include/linux/mfd/lp87565.h #define LPL87565_BUCK1_PG_MASK BIT(6) BIT 180 include/linux/mfd/lp87565.h #define LPL87565_BUCK1_ILIM_MASK BIT(4) BIT 181 include/linux/mfd/lp87565.h #define LPL87565_BUCK0_PG_MASK BIT(2) BIT 182 include/linux/mfd/lp87565.h #define LPL87565_BUCK0_ILIM_MASK BIT(0) BIT 184 include/linux/mfd/lp87565.h #define LPL87565_BUCK3_PG_MASK BIT(6) BIT 185 include/linux/mfd/lp87565.h #define LPL87565_BUCK3_ILIM_MASK BIT(4) BIT 186 include/linux/mfd/lp87565.h #define LPL87565_BUCK2_PG_MASK BIT(2) BIT 187 include/linux/mfd/lp87565.h #define LPL87565_BUCK2_ILIM_MASK BIT(0) BIT 199 include/linux/mfd/lp87565.h #define LP87565_HALF_DAY BIT(7) BIT 200 include/linux/mfd/lp87565.h #define LP87565_EN_PG0_NINT BIT(6) BIT 201 include/linux/mfd/lp87565.h #define LP87565_PGOOD_SET_DELAY BIT(5) BIT 202 include/linux/mfd/lp87565.h #define LP87565_EN_PGFLT_STAT BIT(4) BIT 203 include/linux/mfd/lp87565.h #define LP87565_PGOOD_WINDOW BIT(2) BIT 204 include/linux/mfd/lp87565.h #define LP87565_PGOOD_OD BIT(1) BIT 205 include/linux/mfd/lp87565.h #define LP87565_PGOOD_POL BIT(0) BIT 207 include/linux/mfd/lp87565.h #define LP87565_PG3_FLT BIT(3) BIT 208 include/linux/mfd/lp87565.h #define LP87565_PG2_FLT BIT(2) BIT 209 include/linux/mfd/lp87565.h #define LP87565_PG1_FLT BIT(1) BIT 210 include/linux/mfd/lp87565.h #define LP87565_PG0_FLT BIT(0) BIT 215 include/linux/mfd/lp87565.h #define LP87565_EN_SPREAD_SPEC BIT(7) BIT 216 include/linux/mfd/lp87565.h #define LP87565_EN_PIN_CTRL_GPIO3 BIT(6) BIT 217 include/linux/mfd/lp87565.h #define LP87565_EN_PIN_SELECT_GPIO3 BIT(5) BIT 218 include/linux/mfd/lp87565.h #define LP87565_EN_PIN_CTRL_GPIO2 BIT(4) BIT 219 include/linux/mfd/lp87565.h #define LP87565_EN_PIN_SELECT_GPIO2 BIT(3) BIT 220 include/linux/mfd/lp87565.h #define LP87565_GPIO3_SEL BIT(2) BIT 221 include/linux/mfd/lp87565.h #define LP87565_GPIO2_SEL BIT(1) BIT 222 include/linux/mfd/lp87565.h #define LP87565_GPIO1_SEL BIT(0) BIT 224 include/linux/mfd/lp87565.h #define LP87565_GOIO3_OD BIT(6) BIT 225 include/linux/mfd/lp87565.h #define LP87565_GOIO2_OD BIT(5) BIT 226 include/linux/mfd/lp87565.h #define LP87565_GOIO1_OD BIT(4) BIT 227 include/linux/mfd/lp87565.h #define LP87565_GOIO3_DIR BIT(2) BIT 228 include/linux/mfd/lp87565.h #define LP87565_GOIO2_DIR BIT(1) BIT 229 include/linux/mfd/lp87565.h #define LP87565_GOIO1_DIR BIT(0) BIT 231 include/linux/mfd/lp87565.h #define LP87565_GOIO3_IN BIT(2) BIT 232 include/linux/mfd/lp87565.h #define LP87565_GOIO2_IN BIT(1) BIT 233 include/linux/mfd/lp87565.h #define LP87565_GOIO1_IN BIT(0) BIT 235 include/linux/mfd/lp87565.h #define LP87565_GOIO3_OUT BIT(2) BIT 236 include/linux/mfd/lp87565.h #define LP87565_GOIO2_OUT BIT(1) BIT 237 include/linux/mfd/lp87565.h #define LP87565_GOIO1_OUT BIT(0) BIT 96 include/linux/mfd/max14577-private.h #define MAX14577_INT1_ADC_MASK BIT(0) BIT 97 include/linux/mfd/max14577-private.h #define MAX14577_INT1_ADCLOW_MASK BIT(1) BIT 98 include/linux/mfd/max14577-private.h #define MAX14577_INT1_ADCERR_MASK BIT(2) BIT 99 include/linux/mfd/max14577-private.h #define MAX77836_INT1_ADC1K_MASK BIT(3) BIT 101 include/linux/mfd/max14577-private.h #define MAX14577_INT2_CHGTYP_MASK BIT(0) BIT 102 include/linux/mfd/max14577-private.h #define MAX14577_INT2_CHGDETRUN_MASK BIT(1) BIT 103 include/linux/mfd/max14577-private.h #define MAX14577_INT2_DCDTMR_MASK BIT(2) BIT 104 include/linux/mfd/max14577-private.h #define MAX14577_INT2_DBCHG_MASK BIT(3) BIT 105 include/linux/mfd/max14577-private.h #define MAX14577_INT2_VBVOLT_MASK BIT(4) BIT 106 include/linux/mfd/max14577-private.h #define MAX77836_INT2_VIDRM_MASK BIT(5) BIT 108 include/linux/mfd/max14577-private.h #define MAX14577_INT3_EOC_MASK BIT(0) BIT 109 include/linux/mfd/max14577-private.h #define MAX14577_INT3_CGMBC_MASK BIT(1) BIT 110 include/linux/mfd/max14577-private.h #define MAX14577_INT3_OVP_MASK BIT(2) BIT 111 include/linux/mfd/max14577-private.h #define MAX14577_INT3_MBCCHGERR_MASK BIT(3) BIT 125 include/linux/mfd/max14577-private.h #define STATUS1_ADCLOW_MASK BIT(STATUS1_ADCLOW_SHIFT) BIT 126 include/linux/mfd/max14577-private.h #define STATUS1_ADCERR_MASK BIT(STATUS1_ADCERR_SHIFT) BIT 127 include/linux/mfd/max14577-private.h #define MAX77836_STATUS1_ADC1K_MASK BIT(MAX77836_STATUS1_ADC1K_SHIFT) BIT 138 include/linux/mfd/max14577-private.h #define STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT) BIT 139 include/linux/mfd/max14577-private.h #define STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT) BIT 140 include/linux/mfd/max14577-private.h #define MAX14577_STATUS2_DBCHG_MASK BIT(MAX14577_STATUS2_DBCHG_SHIFT) BIT 141 include/linux/mfd/max14577-private.h #define MAX77836_STATUS2_DXOVP_MASK BIT(MAX77836_STATUS2_DXOVP_SHIFT) BIT 142 include/linux/mfd/max14577-private.h #define STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT) BIT 143 include/linux/mfd/max14577-private.h #define MAX77836_STATUS2_VIDRM_MASK BIT(MAX77836_STATUS2_VIDRM_SHIFT) BIT 152 include/linux/mfd/max14577-private.h #define MICEN_MASK BIT(MICEN_SHIFT) BIT 153 include/linux/mfd/max14577-private.h #define IDBEN_MASK BIT(IDBEN_SHIFT) BIT 173 include/linux/mfd/max14577-private.h #define CTRL2_LOWPWR_MASK BIT(CTRL2_LOWPWR_SHIFT) BIT 174 include/linux/mfd/max14577-private.h #define CTRL2_ADCEN_MASK BIT(CTRL2_ADCEN_SHIFT) BIT 175 include/linux/mfd/max14577-private.h #define CTRL2_CPEN_MASK BIT(CTRL2_CPEN_SHIFT) BIT 176 include/linux/mfd/max14577-private.h #define CTRL2_SFOUTASRT_MASK BIT(CTRL2_SFOUTASRT_SHIFT) BIT 177 include/linux/mfd/max14577-private.h #define CTRL2_SFOUTORD_MASK BIT(CTRL2_SFOUTORD_SHIFT) BIT 178 include/linux/mfd/max14577-private.h #define CTRL2_ACCDET_MASK BIT(CTRL2_ACCDET_SHIFT) BIT 179 include/linux/mfd/max14577-private.h #define CTRL2_USBCPINT_MASK BIT(CTRL2_USBCPINT_SHIFT) BIT 180 include/linux/mfd/max14577-private.h #define CTRL2_RCPS_MASK BIT(CTRL2_RCPS_SHIFT) BIT 232 include/linux/mfd/max14577-private.h #define CDETCTRL1_CHGDETEN_MASK BIT(CDETCTRL1_CHGDETEN_SHIFT) BIT 233 include/linux/mfd/max14577-private.h #define CDETCTRL1_CHGTYPMAN_MASK BIT(CDETCTRL1_CHGTYPMAN_SHIFT) BIT 234 include/linux/mfd/max14577-private.h #define CDETCTRL1_DCDEN_MASK BIT(CDETCTRL1_DCDEN_SHIFT) BIT 235 include/linux/mfd/max14577-private.h #define CDETCTRL1_DCD2SCT_MASK BIT(CDETCTRL1_DCD2SCT_SHIFT) BIT 236 include/linux/mfd/max14577-private.h #define MAX14577_CDETCTRL1_DCHKTM_MASK BIT(MAX14577_CDETCTRL1_DCHKTM_SHIFT) BIT 237 include/linux/mfd/max14577-private.h #define MAX77836_CDETCTRL1_CDDLY_MASK BIT(MAX77836_CDETCTRL1_CDDLY_SHIFT) BIT 238 include/linux/mfd/max14577-private.h #define MAX14577_CDETCTRL1_DBEXIT_MASK BIT(MAX14577_CDETCTRL1_DBEXIT_SHIFT) BIT 239 include/linux/mfd/max14577-private.h #define MAX77836_CDETCTRL1_DCDCPL_MASK BIT(MAX77836_CDETCTRL1_DCDCPL_SHIFT) BIT 240 include/linux/mfd/max14577-private.h #define CDETCTRL1_DBIDLE_MASK BIT(CDETCTRL1_DBIDLE_SHIFT) BIT 241 include/linux/mfd/max14577-private.h #define CDETCTRL1_CDPDET_MASK BIT(CDETCTRL1_CDPDET_SHIFT) BIT 249 include/linux/mfd/max14577-private.h #define CHGCTRL2_MBCHOSTEN_MASK BIT(CHGCTRL2_MBCHOSTEN_SHIFT) BIT 251 include/linux/mfd/max14577-private.h #define CHGCTRL2_VCHGR_RC_MASK BIT(CHGCTRL2_VCHGR_RC_SHIFT) BIT 261 include/linux/mfd/max14577-private.h #define CHGCTRL4_MBCICHWRCL_MASK BIT(CHGCTRL4_MBCICHWRCL_SHIFT) BIT 269 include/linux/mfd/max14577-private.h #define CHGCTRL6_AUTOSTOP_MASK BIT(CHGCTRL6_AUTOSTOP_SHIFT) BIT 340 include/linux/mfd/max14577-private.h #define MAX77836_INTSRC_MASK_TOP_INT_MASK BIT(MAX77836_INTSRC_MASK_TOP_INT_SHIFT) BIT 341 include/linux/mfd/max14577-private.h #define MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK BIT(MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT) BIT 346 include/linux/mfd/max14577-private.h #define MAX77836_TOPSYS_INT_T120C_MASK BIT(MAX77836_TOPSYS_INT_T120C_SHIFT) BIT 347 include/linux/mfd/max14577-private.h #define MAX77836_TOPSYS_INT_T140C_MASK BIT(MAX77836_TOPSYS_INT_T140C_SHIFT) BIT 362 include/linux/mfd/max14577-private.h #define MAX77836_CNFG2_LDO_OVCLMPEN_MASK BIT(MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT) BIT 363 include/linux/mfd/max14577-private.h #define MAX77836_CNFG2_LDO_ALPMEN_MASK BIT(MAX77836_CNFG2_LDO_ALPMEN_SHIFT) BIT 365 include/linux/mfd/max14577-private.h #define MAX77836_CNFG2_LDO_POK_MASK BIT(MAX77836_CNFG2_LDO_POK_SHIFT) BIT 366 include/linux/mfd/max14577-private.h #define MAX77836_CNFG2_LDO_ADE_MASK BIT(MAX77836_CNFG2_LDO_ADE_SHIFT) BIT 367 include/linux/mfd/max14577-private.h #define MAX77836_CNFG2_LDO_SS_MASK BIT(MAX77836_CNFG2_LDO_SS_SHIFT) BIT 74 include/linux/mfd/max77620.h #define MAX77620_TRACK4_MASK BIT(5) BIT 157 include/linux/mfd/max77620.h #define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1) BIT 158 include/linux/mfd/max77620.h #define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2) BIT 170 include/linux/mfd/max77620.h #define MAX77620_SD_CFG1_ADE_MASK BIT(3) BIT 172 include/linux/mfd/max77620.h #define MAX77620_SD_CFG1_ADE_ENABLE BIT(3) BIT 177 include/linux/mfd/max77620.h #define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2) BIT 179 include/linux/mfd/max77620.h #define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2) BIT 180 include/linux/mfd/max77620.h #define MAX20024_SD_CFG1_MPOK_MASK BIT(1) BIT 181 include/linux/mfd/max77620.h #define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0) BIT 183 include/linux/mfd/max77620.h #define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0) BIT 188 include/linux/mfd/max77620.h #define MAX20024_LDO_CFG2_MPOK_MASK BIT(2) BIT 189 include/linux/mfd/max77620.h #define MAX77620_LDO_CFG2_ADE_MASK BIT(1) BIT 191 include/linux/mfd/max77620.h #define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1) BIT 192 include/linux/mfd/max77620.h #define MAX77620_LDO_CFG2_SS_MASK BIT(0) BIT 193 include/linux/mfd/max77620.h #define MAX77620_LDO_CFG2_SS_FAST BIT(0) BIT 196 include/linux/mfd/max77620.h #define MAX77620_IRQ_TOP_GLBL_MASK BIT(7) BIT 197 include/linux/mfd/max77620.h #define MAX77620_IRQ_TOP_SD_MASK BIT(6) BIT 198 include/linux/mfd/max77620.h #define MAX77620_IRQ_TOP_LDO_MASK BIT(5) BIT 199 include/linux/mfd/max77620.h #define MAX77620_IRQ_TOP_GPIO_MASK BIT(4) BIT 200 include/linux/mfd/max77620.h #define MAX77620_IRQ_TOP_RTC_MASK BIT(3) BIT 201 include/linux/mfd/max77620.h #define MAX77620_IRQ_TOP_32K_MASK BIT(2) BIT 202 include/linux/mfd/max77620.h #define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1) BIT 204 include/linux/mfd/max77620.h #define MAX77620_IRQ_LBM_MASK BIT(3) BIT 205 include/linux/mfd/max77620.h #define MAX77620_IRQ_TJALRM1_MASK BIT(2) BIT 206 include/linux/mfd/max77620.h #define MAX77620_IRQ_TJALRM2_MASK BIT(1) BIT 211 include/linux/mfd/max77620.h #define MAX77620_CNFG_GPIO_DRV_MASK BIT(0) BIT 212 include/linux/mfd/max77620.h #define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0) BIT 214 include/linux/mfd/max77620.h #define MAX77620_CNFG_GPIO_DIR_MASK BIT(1) BIT 215 include/linux/mfd/max77620.h #define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1) BIT 217 include/linux/mfd/max77620.h #define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2) BIT 218 include/linux/mfd/max77620.h #define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3) BIT 219 include/linux/mfd/max77620.h #define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3) BIT 222 include/linux/mfd/max77620.h #define MAX77620_CNFG_GPIO_INT_FALLING BIT(4) BIT 223 include/linux/mfd/max77620.h #define MAX77620_CNFG_GPIO_INT_RISING BIT(5) BIT 230 include/linux/mfd/max77620.h #define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0) BIT 231 include/linux/mfd/max77620.h #define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1) BIT 232 include/linux/mfd/max77620.h #define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2) BIT 233 include/linux/mfd/max77620.h #define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3) BIT 234 include/linux/mfd/max77620.h #define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4) BIT 235 include/linux/mfd/max77620.h #define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5) BIT 236 include/linux/mfd/max77620.h #define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6) BIT 237 include/linux/mfd/max77620.h #define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7) BIT 239 include/linux/mfd/max77620.h #define MAX77620_CNFG1_32K_OUT0_EN BIT(2) BIT 241 include/linux/mfd/max77620.h #define MAX77620_ONOFFCNFG1_SFT_RST BIT(7) BIT 244 include/linux/mfd/max77620.h #define MAX77620_ONOFFCNFG1_SLPEN BIT(2) BIT 245 include/linux/mfd/max77620.h #define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1) BIT 248 include/linux/mfd/max77620.h #define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7) BIT 249 include/linux/mfd/max77620.h #define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6) BIT 250 include/linux/mfd/max77620.h #define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5) BIT 251 include/linux/mfd/max77620.h #define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2) BIT 252 include/linux/mfd/max77620.h #define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0) BIT 254 include/linux/mfd/max77620.h #define MAX77620_GLBLM_MASK BIT(0) BIT 257 include/linux/mfd/max77620.h #define MAX77620_WDTOFFC BIT(4) BIT 258 include/linux/mfd/max77620.h #define MAX77620_WDTSLPC BIT(3) BIT 259 include/linux/mfd/max77620.h #define MAX77620_WDTEN BIT(2) BIT 267 include/linux/mfd/max77620.h #define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7) BIT 268 include/linux/mfd/max77620.h #define MAX77620_CNFGGLBL1_MPPLD BIT(6) BIT 269 include/linux/mfd/max77620.h #define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4)) BIT 271 include/linux/mfd/max77620.h #define MAX77620_CNFGGLBL1_LBRSTEN BIT(0) BIT 274 include/linux/mfd/max77620.h #define MAX77620_CNFGBBC_ENABLE BIT(0) BIT 279 include/linux/mfd/max77620.h #define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5) BIT 405 include/linux/mfd/max77686-private.h #define MAX77686_INT1_PWRONF_MSK BIT(0) BIT 406 include/linux/mfd/max77686-private.h #define MAX77686_INT1_PWRONR_MSK BIT(1) BIT 407 include/linux/mfd/max77686-private.h #define MAX77686_INT1_JIGONBF_MSK BIT(2) BIT 408 include/linux/mfd/max77686-private.h #define MAX77686_INT1_JIGONBR_MSK BIT(3) BIT 409 include/linux/mfd/max77686-private.h #define MAX77686_INT1_ACOKBF_MSK BIT(4) BIT 410 include/linux/mfd/max77686-private.h #define MAX77686_INT1_ACOKBR_MSK BIT(5) BIT 411 include/linux/mfd/max77686-private.h #define MAX77686_INT1_ONKEY1S_MSK BIT(6) BIT 412 include/linux/mfd/max77686-private.h #define MAX77686_INT1_MRSTB_MSK BIT(7) BIT 414 include/linux/mfd/max77686-private.h #define MAX77686_INT2_140C_MSK BIT(0) BIT 415 include/linux/mfd/max77686-private.h #define MAX77686_INT2_120C_MSK BIT(1) BIT 417 include/linux/mfd/max77686-private.h #define MAX77686_RTCINT_RTC60S_MSK BIT(0) BIT 418 include/linux/mfd/max77686-private.h #define MAX77686_RTCINT_RTCA1_MSK BIT(1) BIT 419 include/linux/mfd/max77686-private.h #define MAX77686_RTCINT_RTCA2_MSK BIT(2) BIT 420 include/linux/mfd/max77686-private.h #define MAX77686_RTCINT_SMPL_MSK BIT(3) BIT 421 include/linux/mfd/max77686-private.h #define MAX77686_RTCINT_RTC1S_MSK BIT(4) BIT 422 include/linux/mfd/max77686-private.h #define MAX77686_RTCINT_WTSR_MSK BIT(5) BIT 124 include/linux/mfd/max77693-private.h #define FLASH_STATUS_FLASH_ON BIT(3) BIT 125 include/linux/mfd/max77693-private.h #define FLASH_STATUS_TORCH_ON BIT(2) BIT 128 include/linux/mfd/max77693-private.h #define FLASH_INT_FLED2_OPEN BIT(0) BIT 129 include/linux/mfd/max77693-private.h #define FLASH_INT_FLED2_SHORT BIT(1) BIT 130 include/linux/mfd/max77693-private.h #define FLASH_INT_FLED1_OPEN BIT(2) BIT 131 include/linux/mfd/max77693-private.h #define FLASH_INT_FLED1_SHORT BIT(3) BIT 132 include/linux/mfd/max77693-private.h #define FLASH_INT_OVER_CURRENT BIT(4) BIT 157 include/linux/mfd/max77693-private.h #define CHG_INT_OK_BYP_MASK BIT(CHG_INT_OK_BYP_SHIFT) BIT 158 include/linux/mfd/max77693-private.h #define CHG_INT_OK_BAT_MASK BIT(CHG_INT_OK_BAT_SHIFT) BIT 159 include/linux/mfd/max77693-private.h #define CHG_INT_OK_CHG_MASK BIT(CHG_INT_OK_CHG_SHIFT) BIT 160 include/linux/mfd/max77693-private.h #define CHG_INT_OK_CHGIN_MASK BIT(CHG_INT_OK_CHGIN_SHIFT) BIT 161 include/linux/mfd/max77693-private.h #define CHG_INT_OK_DETBAT_MASK BIT(CHG_INT_OK_DETBAT_SHIFT) BIT 173 include/linux/mfd/max77693-private.h #define CHG_DETAILS_01_TREG_MASK BIT(7) BIT 218 include/linux/mfd/max77693-private.h #define CHG_CNFG_01_PQEN_MAKS BIT(CHG_CNFG_01_PQEN_SHIFT) BIT 305 include/linux/mfd/max77693-private.h #define MAX77693_STATUS1_ADCLOW_MASK BIT(MAX77693_STATUS1_ADCLOW_SHIFT) BIT 306 include/linux/mfd/max77693-private.h #define MAX77693_STATUS1_ADCERR_MASK BIT(MAX77693_STATUS1_ADCERR_SHIFT) BIT 307 include/linux/mfd/max77693-private.h #define MAX77693_STATUS1_ADC1K_MASK BIT(MAX77693_STATUS1_ADC1K_SHIFT) BIT 316 include/linux/mfd/max77693-private.h #define MAX77693_STATUS2_CHGDETRUN_MASK BIT(MAX77693_STATUS2_CHGDETRUN_SHIFT) BIT 317 include/linux/mfd/max77693-private.h #define MAX77693_STATUS2_DCDTMR_MASK BIT(MAX77693_STATUS2_DCDTMR_SHIFT) BIT 318 include/linux/mfd/max77693-private.h #define MAX77693_STATUS2_DXOVP_MASK BIT(MAX77693_STATUS2_DXOVP_SHIFT) BIT 319 include/linux/mfd/max77693-private.h #define MAX77693_STATUS2_VBVOLT_MASK BIT(MAX77693_STATUS2_VBVOLT_SHIFT) BIT 320 include/linux/mfd/max77693-private.h #define MAX77693_STATUS2_VIDRM_MASK BIT(MAX77693_STATUS2_VIDRM_SHIFT) BIT 323 include/linux/mfd/max77693-private.h #define MAX77693_STATUS3_OVP_MASK BIT(MAX77693_STATUS3_OVP_SHIFT) BIT 369 include/linux/mfd/max77693-private.h #define MAX77693_CONTROL2_LOWPWR_MASK BIT(MAX77693_CONTROL2_LOWPWR_SHIFT) BIT 370 include/linux/mfd/max77693-private.h #define MAX77693_CONTROL2_ADCEN_MASK BIT(MAX77693_CONTROL2_ADCEN_SHIFT) BIT 371 include/linux/mfd/max77693-private.h #define MAX77693_CONTROL2_CPEN_MASK BIT(MAX77693_CONTROL2_CPEN_SHIFT) BIT 372 include/linux/mfd/max77693-private.h #define MAX77693_CONTROL2_SFOUTASRT_MASK BIT(MAX77693_CONTROL2_SFOUTASRT_SHIFT) BIT 373 include/linux/mfd/max77693-private.h #define MAX77693_CONTROL2_SFOUTORD_MASK BIT(MAX77693_CONTROL2_SFOUTORD_SHIFT) BIT 374 include/linux/mfd/max77693-private.h #define MAX77693_CONTROL2_ACCDET_MASK BIT(MAX77693_CONTROL2_ACCDET_SHIFT) BIT 375 include/linux/mfd/max77693-private.h #define MAX77693_CONTROL2_USBCPINT_MASK BIT(MAX77693_CONTROL2_USBCPINT_SHIFT) BIT 376 include/linux/mfd/max77693-private.h #define MAX77693_CONTROL2_RCPS_MASK BIT(MAX77693_CONTROL2_RCPS_SHIFT) BIT 428 include/linux/mfd/max77693-private.h #define SRC_IRQ_CHARGER BIT(0) BIT 429 include/linux/mfd/max77693-private.h #define SRC_IRQ_TOP BIT(1) BIT 430 include/linux/mfd/max77693-private.h #define SRC_IRQ_FLASH BIT(2) BIT 431 include/linux/mfd/max77693-private.h #define SRC_IRQ_MUIC BIT(3) BIT 435 include/linux/mfd/max77693-private.h #define LED_IRQ_FLED2_OPEN BIT(0) BIT 436 include/linux/mfd/max77693-private.h #define LED_IRQ_FLED2_SHORT BIT(1) BIT 437 include/linux/mfd/max77693-private.h #define LED_IRQ_FLED1_OPEN BIT(2) BIT 438 include/linux/mfd/max77693-private.h #define LED_IRQ_FLED1_SHORT BIT(3) BIT 439 include/linux/mfd/max77693-private.h #define LED_IRQ_MAX_FLASH BIT(4) BIT 441 include/linux/mfd/max77693-private.h #define TOPSYS_IRQ_T120C_INT BIT(0) BIT 442 include/linux/mfd/max77693-private.h #define TOPSYS_IRQ_T140C_INT BIT(1) BIT 443 include/linux/mfd/max77693-private.h #define TOPSYS_IRQ_LOWSYS_INT BIT(3) BIT 445 include/linux/mfd/max77693-private.h #define CHG_IRQ_BYP_I BIT(0) BIT 446 include/linux/mfd/max77693-private.h #define CHG_IRQ_THM_I BIT(2) BIT 447 include/linux/mfd/max77693-private.h #define CHG_IRQ_BAT_I BIT(3) BIT 448 include/linux/mfd/max77693-private.h #define CHG_IRQ_CHG_I BIT(4) BIT 449 include/linux/mfd/max77693-private.h #define CHG_IRQ_CHGIN_I BIT(6) BIT 451 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT1_ADC BIT(0) BIT 452 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT1_ADC_LOW BIT(1) BIT 453 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT1_ADC_ERR BIT(2) BIT 454 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT1_ADC1K BIT(3) BIT 456 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT2_CHGTYP BIT(0) BIT 457 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT2_CHGDETREUN BIT(1) BIT 458 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT2_DCDTMR BIT(2) BIT 459 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT2_DXOVP BIT(3) BIT 460 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT2_VBVOLT BIT(4) BIT 461 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT2_VIDRM BIT(5) BIT 463 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT3_EOC BIT(0) BIT 464 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT3_CGMBC BIT(1) BIT 465 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT3_OVP BIT(2) BIT 466 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3) BIT 467 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT3_CHG_ENABLED BIT(4) BIT 468 include/linux/mfd/max77693-private.h #define MUIC_IRQ_INT3_BAT_DET BIT(5) BIT 183 include/linux/mfd/max77843-private.h #define MAX77843_SYS_IRQ_SYSUVLO_INT BIT(0) BIT 184 include/linux/mfd/max77843-private.h #define MAX77843_SYS_IRQ_SYSOVLO_INT BIT(1) BIT 185 include/linux/mfd/max77843-private.h #define MAX77843_SYS_IRQ_TSHDN_INT BIT(2) BIT 186 include/linux/mfd/max77843-private.h #define MAX77843_SYS_IRQ_TM_INT BIT(3) BIT 190 include/linux/mfd/max77843-private.h #define MAX77843_MAINCTRL1_BIASEN_MASK BIT(MAINCTRL1_BIASEN_SHIFT) BIT 197 include/linux/mfd/max77843-private.h #define MAX77843_MCONFIG_MODE_MASK BIT(MCONFIG_MODE_SHIFT) BIT 198 include/linux/mfd/max77843-private.h #define MAX77843_MCONFIG_MEN_MASK BIT(MCONFIG_MEN_SHIFT) BIT 202 include/linux/mfd/max77843-private.h #define MAX77843_CHG_BYP_I BIT(0) BIT 203 include/linux/mfd/max77843-private.h #define MAX77843_CHG_BATP_I BIT(2) BIT 204 include/linux/mfd/max77843-private.h #define MAX77843_CHG_BAT_I BIT(3) BIT 205 include/linux/mfd/max77843-private.h #define MAX77843_CHG_CHG_I BIT(4) BIT 206 include/linux/mfd/max77843-private.h #define MAX77843_CHG_WCIN_I BIT(5) BIT 207 include/linux/mfd/max77843-private.h #define MAX77843_CHG_CHGIN_I BIT(6) BIT 208 include/linux/mfd/max77843-private.h #define MAX77843_CHG_AICL_I BIT(7) BIT 211 include/linux/mfd/max77843-private.h #define MAX77843_CHG_BYP_OK BIT(0) BIT 212 include/linux/mfd/max77843-private.h #define MAX77843_CHG_BATP_OK BIT(2) BIT 213 include/linux/mfd/max77843-private.h #define MAX77843_CHG_BAT_OK BIT(3) BIT 214 include/linux/mfd/max77843-private.h #define MAX77843_CHG_CHG_OK BIT(4) BIT 215 include/linux/mfd/max77843-private.h #define MAX77843_CHG_WCIN_OK BIT(5) BIT 216 include/linux/mfd/max77843-private.h #define MAX77843_CHG_CHGIN_OK BIT(6) BIT 217 include/linux/mfd/max77843-private.h #define MAX77843_CHG_AICL_OK BIT(7) BIT 220 include/linux/mfd/max77843-private.h #define MAX77843_CHG_BAT_DTLS BIT(0) BIT 285 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_ADC BIT(0) BIT 286 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_ADCERROR BIT(2) BIT 287 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_ADC1K BIT(3) BIT 289 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CHGTYP BIT(0) BIT 290 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CHGDETRUN BIT(1) BIT 291 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_DCDTMR BIT(2) BIT 292 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_DXOVP BIT(3) BIT 293 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_VBVOLT BIT(4) BIT 295 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_VBADC BIT(0) BIT 296 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_VDNMON BIT(1) BIT 297 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_DNRES BIT(2) BIT 298 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_MPNACK BIT(3) BIT 299 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_MRXBUFOW BIT(4) BIT 300 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_MRXTRF BIT(5) BIT 301 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_MRXPERR BIT(6) BIT 302 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_MRXRDY BIT(7) BIT 310 include/linux/mfd/max77843-private.h #define MAX77843_INTSRCMASK_CHGR_MASK BIT(MAX77843_INTSRCMASK_CHGR) BIT 311 include/linux/mfd/max77843-private.h #define MAX77843_INTSRCMASK_SYS_MASK BIT(MAX77843_INTSRCMASK_SYS) BIT 312 include/linux/mfd/max77843-private.h #define MAX77843_INTSRCMASK_FG_MASK BIT(MAX77843_INTSRCMASK_FG) BIT 313 include/linux/mfd/max77843-private.h #define MAX77843_INTSRCMASK_MUIC_MASK BIT(MAX77843_INTSRCMASK_MUIC) BIT 334 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(MAX77843_MUIC_STATUS1_ADCERROR_SHIFT) BIT 335 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(MAX77843_MUIC_STATUS1_ADC1K_SHIFT) BIT 337 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT) BIT 338 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(MAX77843_MUIC_STATUS2_DCDTMR_SHIFT) BIT 339 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(MAX77843_MUIC_STATUS2_DXOVP_SHIFT) BIT 340 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(MAX77843_MUIC_STATUS2_VBVOLT_SHIFT) BIT 342 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(MAX77843_MUIC_STATUS3_VDNMON_SHIFT) BIT 343 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(MAX77843_MUIC_STATUS3_DNRES_SHIFT) BIT 344 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(MAX77843_MUIC_STATUS3_MPNACK_SHIFT) BIT 365 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(MAX77843_MUIC_CONTROL1_IDBEN_SHIFT) BIT 366 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CONTROL1_NOBCCOMP_MASK BIT(MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT) BIT 367 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT) BIT 368 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(MAX77843_MUIC_CONTROL2_ADCEN_SHIFT) BIT 369 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(MAX77843_MUIC_CONTROL2_CPEN_SHIFT) BIT 370 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT) BIT 371 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT) BIT 372 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(MAX77843_MUIC_CONTROL2_RCPS_SHIFT) BIT 375 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) BIT 376 include/linux/mfd/max77843-private.h #define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT) BIT 427 include/linux/mfd/max77843-private.h BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT) BIT 429 include/linux/mfd/max77843-private.h BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT) BIT 25 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE BIT(23) BIT 26 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE BIT(22) BIT 27 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX28_YNNSW /* YM */ BIT(21) BIT 28 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX28_YPNSW /* YP */ BIT(20) BIT 29 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX28_YPPSW /* YP */ BIT(19) BIT 30 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX28_XNNSW /* XM */ BIT(18) BIT 31 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX28_XNPSW /* XM */ BIT(17) BIT 32 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX28_XPPSW /* XP */ BIT(16) BIT 34 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE BIT(20) BIT 35 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX23_YM BIT(19) BIT 36 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX23_XM BIT(18) BIT 37 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX23_YP BIT(17) BIT 38 include/linux/mfd/mxs-lradc.h # define LRADC_CTRL0_MX23_XP BIT(16) BIT 52 include/linux/mfd/mxs-lradc.h #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN BIT(24) BIT 57 include/linux/mfd/mxs-lradc.h #define LRADC_CTRL1_TOUCH_DETECT_IRQ BIT(8) BIT 58 include/linux/mfd/mxs-lradc.h #define LRADC_CTRL1_LRADC_IRQ(n) BIT(n) BIT 65 include/linux/mfd/mxs-lradc.h #define LRADC_CTRL2_TEMPSENSE_PWD BIT(15) BIT 68 include/linux/mfd/mxs-lradc.h #define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0) BIT 71 include/linux/mfd/mxs-lradc.h #define LRADC_CH_ACCUMULATE BIT(29) BIT 85 include/linux/mfd/mxs-lradc.h #define LRADC_DELAY_KICK BIT(20) BIT 134 include/linux/mfd/mxs-lradc.h #define CHAN_MASK_TOUCHBUTTON (BIT(1) | BIT(0)) BIT 44 include/linux/mfd/palmas.h #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0) BIT 195 include/linux/mfd/rk808.h #define RK818_H5V_EN BIT(0) BIT 196 include/linux/mfd/rk808.h #define RK818_REF_RDY_CTRL BIT(1) BIT 267 include/linux/mfd/rk808.h #define RK805_IRQ_PWRON_RISE_MSK BIT(0) BIT 268 include/linux/mfd/rk808.h #define RK805_IRQ_VB_LOW_MSK BIT(1) BIT 269 include/linux/mfd/rk808.h #define RK805_IRQ_PWRON_MSK BIT(2) BIT 270 include/linux/mfd/rk808.h #define RK805_IRQ_PWRON_LP_MSK BIT(3) BIT 271 include/linux/mfd/rk808.h #define RK805_IRQ_HOTDIE_MSK BIT(4) BIT 272 include/linux/mfd/rk808.h #define RK805_IRQ_RTC_ALARM_MSK BIT(5) BIT 273 include/linux/mfd/rk808.h #define RK805_IRQ_RTC_PERIOD_MSK BIT(6) BIT 274 include/linux/mfd/rk808.h #define RK805_IRQ_PWRON_FALL_MSK BIT(7) BIT 276 include/linux/mfd/rk808.h #define RK805_PWR_RISE_INT_STATUS BIT(0) BIT 277 include/linux/mfd/rk808.h #define RK805_VB_LOW_INT_STATUS BIT(1) BIT 278 include/linux/mfd/rk808.h #define RK805_PWRON_INT_STATUS BIT(2) BIT 279 include/linux/mfd/rk808.h #define RK805_PWRON_LP_INT_STATUS BIT(3) BIT 280 include/linux/mfd/rk808.h #define RK805_HOTDIE_INT_STATUS BIT(4) BIT 281 include/linux/mfd/rk808.h #define RK805_ALARM_INT_STATUS BIT(5) BIT 282 include/linux/mfd/rk808.h #define RK805_PERIOD_INT_STATUS BIT(6) BIT 283 include/linux/mfd/rk808.h #define RK805_PWR_FALL_INT_STATUS BIT(7) BIT 304 include/linux/mfd/rk808.h #define RK808_IRQ_VOUT_LO_MSK BIT(0) BIT 305 include/linux/mfd/rk808.h #define RK808_IRQ_VB_LO_MSK BIT(1) BIT 306 include/linux/mfd/rk808.h #define RK808_IRQ_PWRON_MSK BIT(2) BIT 307 include/linux/mfd/rk808.h #define RK808_IRQ_PWRON_LP_MSK BIT(3) BIT 308 include/linux/mfd/rk808.h #define RK808_IRQ_HOTDIE_MSK BIT(4) BIT 309 include/linux/mfd/rk808.h #define RK808_IRQ_RTC_ALARM_MSK BIT(5) BIT 310 include/linux/mfd/rk808.h #define RK808_IRQ_RTC_PERIOD_MSK BIT(6) BIT 311 include/linux/mfd/rk808.h #define RK808_IRQ_PLUG_IN_INT_MSK BIT(0) BIT 312 include/linux/mfd/rk808.h #define RK808_IRQ_PLUG_OUT_INT_MSK BIT(1) BIT 332 include/linux/mfd/rk808.h #define RK818_IRQ_VOUT_LO_MSK BIT(0) BIT 333 include/linux/mfd/rk808.h #define RK818_IRQ_VB_LO_MSK BIT(1) BIT 334 include/linux/mfd/rk808.h #define RK818_IRQ_PWRON_MSK BIT(2) BIT 335 include/linux/mfd/rk808.h #define RK818_IRQ_PWRON_LP_MSK BIT(3) BIT 336 include/linux/mfd/rk808.h #define RK818_IRQ_HOTDIE_MSK BIT(4) BIT 337 include/linux/mfd/rk808.h #define RK818_IRQ_RTC_ALARM_MSK BIT(5) BIT 338 include/linux/mfd/rk808.h #define RK818_IRQ_RTC_PERIOD_MSK BIT(6) BIT 339 include/linux/mfd/rk808.h #define RK818_IRQ_USB_OV_MSK BIT(7) BIT 340 include/linux/mfd/rk808.h #define RK818_IRQ_PLUG_IN_MSK BIT(0) BIT 341 include/linux/mfd/rk808.h #define RK818_IRQ_PLUG_OUT_MSK BIT(1) BIT 342 include/linux/mfd/rk808.h #define RK818_IRQ_CHG_OK_MSK BIT(2) BIT 343 include/linux/mfd/rk808.h #define RK818_IRQ_CHG_TE_MSK BIT(3) BIT 344 include/linux/mfd/rk808.h #define RK818_IRQ_CHG_TS1_MSK BIT(4) BIT 345 include/linux/mfd/rk808.h #define RK818_IRQ_TS2_MSK BIT(5) BIT 346 include/linux/mfd/rk808.h #define RK818_IRQ_CHG_CVTLIM_MSK BIT(6) BIT 347 include/linux/mfd/rk808.h #define RK818_IRQ_DISCHG_ILIM_MSK BIT(7) BIT 373 include/linux/mfd/rk808.h #define SWITCH2_EN BIT(6) BIT 374 include/linux/mfd/rk808.h #define SWITCH1_EN BIT(5) BIT 375 include/linux/mfd/rk808.h #define DEV_OFF_RST BIT(3) BIT 376 include/linux/mfd/rk808.h #define DEV_OFF BIT(0) BIT 377 include/linux/mfd/rk808.h #define RTC_STOP BIT(0) BIT 379 include/linux/mfd/rk808.h #define VB_LO_ACT BIT(4) BIT 382 include/linux/mfd/rk808.h #define VOUT_LO_INT BIT(0) BIT 383 include/linux/mfd/rk808.h #define CLK32KOUT2_EN BIT(0) BIT 391 include/linux/mfd/rk808.h #define PWM_MODE_MSK BIT(7) BIT 392 include/linux/mfd/rk808.h #define FPWM_MODE BIT(7) BIT 514 include/linux/mfd/rk808.h #define RK817_RTC_CTRL_RSV4 BIT(4) BIT 517 include/linux/mfd/rk808.h #define RK817_BUCK3_FB_RES_MSK BIT(6) BIT 518 include/linux/mfd/rk808.h #define RK817_BUCK3_FB_RES_INTER BIT(6) BIT 536 include/linux/mfd/rk808.h #define RK817_TSD_TEMP_MSK BIT(6) BIT 538 include/linux/mfd/rk808.h #define RK817_TSD_160 BIT(6) BIT 540 include/linux/mfd/rk808.h #define RK817_CLK32KOUT2_EN BIT(7) BIT 555 include/linux/mfd/rk808.h #define RK817_SLPPOL_MSK BIT(5) BIT 556 include/linux/mfd/rk808.h #define RK817_SLPPOL_H BIT(5) BIT 560 include/linux/mfd/rk808.h #define RK817_INT_POL_MSK BIT(1) BIT 561 include/linux/mfd/rk808.h #define RK817_INT_POL_H BIT(1) BIT 211 include/linux/mfd/rn5t618.h #define RN5T618_REPCNT_REPWRON BIT(0) BIT 212 include/linux/mfd/rn5t618.h #define RN5T618_SLPCNT_SWPWROFF BIT(0) BIT 213 include/linux/mfd/rn5t618.h #define RN5T618_WATCHDOG_WDOGEN BIT(2) BIT 214 include/linux/mfd/rn5t618.h #define RN5T618_WATCHDOG_WDOGTIM_M (BIT(0) | BIT(1)) BIT 216 include/linux/mfd/rn5t618.h #define RN5T618_PWRIRQ_IR_WDOG BIT(6) BIT 179 include/linux/mfd/samsung/s2mps11.h #define S2MPS11_CTRL1_PWRHOLD_MASK BIT(4) BIT 175 include/linux/mfd/samsung/s2mps13.h #define S2MPS13_REG_WRSTBI_MASK BIT(5) BIT 238 include/linux/mfd/sta2x11-mfd.h #define SCTL_SCPLLCTL_AUDIO_PLL_PD BIT(1) BIT 239 include/linux/mfd/sta2x11-mfd.h #define SCTL_SCPLLCTL_FRAC_CONTROL BIT(3) BIT 240 include/linux/mfd/sta2x11-mfd.h #define SCTL_SCPLLCTL_STRB_BYPASS BIT(6) BIT 241 include/linux/mfd/sta2x11-mfd.h #define SCTL_SCPLLCTL_STRB_INPUT BIT(8) BIT 26 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_ARROK BIT(4) BIT 27 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_CMPOK BIT(3) BIT 33 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_CNTSTRT BIT(2) BIT 34 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_ENABLE BIT(0) BIT 37 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_ENC BIT(24) BIT 38 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_COUNTMODE BIT(23) BIT 39 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_WAVPOL BIT(21) BIT 35 include/linux/mfd/stm32-timers.h #define TIM_CR1_CEN BIT(0) /* Counter Enable */ BIT 36 include/linux/mfd/stm32-timers.h #define TIM_CR1_DIR BIT(4) /* Counter Direction */ BIT 37 include/linux/mfd/stm32-timers.h #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ BIT 38 include/linux/mfd/stm32-timers.h #define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ BIT 40 include/linux/mfd/stm32-timers.h #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ BIT 41 include/linux/mfd/stm32-timers.h #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ BIT 42 include/linux/mfd/stm32-timers.h #define TIM_DIER_UIE BIT(0) /* Update interrupt */ BIT 43 include/linux/mfd/stm32-timers.h #define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ BIT 44 include/linux/mfd/stm32-timers.h #define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ BIT 45 include/linux/mfd/stm32-timers.h #define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ BIT 46 include/linux/mfd/stm32-timers.h #define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */ BIT 47 include/linux/mfd/stm32-timers.h #define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */ BIT 48 include/linux/mfd/stm32-timers.h #define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ BIT 49 include/linux/mfd/stm32-timers.h #define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ BIT 50 include/linux/mfd/stm32-timers.h #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ BIT 51 include/linux/mfd/stm32-timers.h #define TIM_EGR_UG BIT(0) /* Update Generation */ BIT 52 include/linux/mfd/stm32-timers.h #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ BIT 53 include/linux/mfd/stm32-timers.h #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ BIT 54 include/linux/mfd/stm32-timers.h #define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */ BIT 56 include/linux/mfd/stm32-timers.h #define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */ BIT 58 include/linux/mfd/stm32-timers.h #define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */ BIT 59 include/linux/mfd/stm32-timers.h #define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ BIT 60 include/linux/mfd/stm32-timers.h #define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ BIT 61 include/linux/mfd/stm32-timers.h #define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ BIT 62 include/linux/mfd/stm32-timers.h #define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ BIT 63 include/linux/mfd/stm32-timers.h #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ BIT 64 include/linux/mfd/stm32-timers.h #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ BIT 65 include/linux/mfd/stm32-timers.h #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ BIT 66 include/linux/mfd/stm32-timers.h #define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ BIT 67 include/linux/mfd/stm32-timers.h #define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ BIT 68 include/linux/mfd/stm32-timers.h #define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ BIT 69 include/linux/mfd/stm32-timers.h #define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ BIT 70 include/linux/mfd/stm32-timers.h #define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ BIT 71 include/linux/mfd/stm32-timers.h #define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ BIT 72 include/linux/mfd/stm32-timers.h #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) BIT 73 include/linux/mfd/stm32-timers.h #define TIM_BDTR_BKE BIT(12) /* Break input enable */ BIT 74 include/linux/mfd/stm32-timers.h #define TIM_BDTR_BKP BIT(13) /* Break input polarity */ BIT 75 include/linux/mfd/stm32-timers.h #define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */ BIT 76 include/linux/mfd/stm32-timers.h #define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ BIT 77 include/linux/mfd/stm32-timers.h #define TIM_BDTR_BKF (BIT(16) | BIT(17) | BIT(18) | BIT(19)) BIT 78 include/linux/mfd/stm32-timers.h #define TIM_BDTR_BK2F (BIT(20) | BIT(21) | BIT(22) | BIT(23)) BIT 79 include/linux/mfd/stm32-timers.h #define TIM_BDTR_BK2E BIT(24) /* Break 2 input enable */ BIT 80 include/linux/mfd/stm32-timers.h #define TIM_BDTR_BK2P BIT(25) /* Break 2 input polarity */ BIT 66 include/linux/mfd/stmfx.h #define STMFX_REG_SYS_CTRL_GPIO_EN BIT(0) BIT 67 include/linux/mfd/stmfx.h #define STMFX_REG_SYS_CTRL_TS_EN BIT(1) BIT 68 include/linux/mfd/stmfx.h #define STMFX_REG_SYS_CTRL_IDD_EN BIT(2) BIT 69 include/linux/mfd/stmfx.h #define STMFX_REG_SYS_CTRL_ALTGPIO_EN BIT(3) BIT 70 include/linux/mfd/stmfx.h #define STMFX_REG_SYS_CTRL_SWRST BIT(7) BIT 73 include/linux/mfd/stmfx.h #define STMFX_REG_IRQ_OUT_PIN_TYPE BIT(0) /* 0-OD 1-PP */ BIT 74 include/linux/mfd/stmfx.h #define STMFX_REG_IRQ_OUT_PIN_POL BIT(1) /* 0-active LOW 1-active HIGH */ BIT 90 include/linux/mfd/stmfx.h STMFX_FUNC_GPIO = BIT(0), /* GPIO[15:0] */ BIT 91 include/linux/mfd/stmfx.h STMFX_FUNC_ALTGPIO_LOW = BIT(1), /* aGPIO[3:0] */ BIT 92 include/linux/mfd/stmfx.h STMFX_FUNC_ALTGPIO_HIGH = BIT(2), /* aGPIO[7:4] */ BIT 93 include/linux/mfd/stmfx.h STMFX_FUNC_TS = BIT(3), BIT 94 include/linux/mfd/stmfx.h STMFX_FUNC_IDD = BIT(4), BIT 105 include/linux/mfd/stpmic1.h #define LDO_ENABLE_MASK BIT(0) BIT 106 include/linux/mfd/stpmic1.h #define BUCK_ENABLE_MASK BIT(0) BIT 108 include/linux/mfd/stpmic1.h #define BUCK_HPLP_ENABLE_MASK BIT(1) BIT 111 include/linux/mfd/stpmic1.h #define STDBY_ENABLE_MASK BIT(0) BIT 122 include/linux/mfd/stpmic1.h #define BUCK1_PULL_DOWN_MASK BIT(0) BIT 124 include/linux/mfd/stpmic1.h #define BUCK2_PULL_DOWN_MASK BIT(2) BIT 126 include/linux/mfd/stpmic1.h #define BUCK3_PULL_DOWN_MASK BIT(4) BIT 128 include/linux/mfd/stpmic1.h #define BUCK4_PULL_DOWN_MASK BIT(6) BIT 131 include/linux/mfd/stpmic1.h #define LDO1_PULL_DOWN_MASK BIT(0) BIT 133 include/linux/mfd/stpmic1.h #define LDO2_PULL_DOWN_MASK BIT(2) BIT 135 include/linux/mfd/stpmic1.h #define LDO3_PULL_DOWN_MASK BIT(4) BIT 137 include/linux/mfd/stpmic1.h #define LDO4_PULL_DOWN_MASK BIT(6) BIT 139 include/linux/mfd/stpmic1.h #define LDO5_PULL_DOWN_MASK BIT(0) BIT 141 include/linux/mfd/stpmic1.h #define LDO6_PULL_DOWN_MASK BIT(2) BIT 143 include/linux/mfd/stpmic1.h #define VREF_DDR_PULL_DOWN_MASK BIT(4) BIT 148 include/linux/mfd/stpmic1.h #define LDO_BYPASS_MASK BIT(7) BIT 154 include/linux/mfd/stpmic1.h #define ICC_EVENT_ENABLED BIT(4) BIT 155 include/linux/mfd/stpmic1.h #define PWRCTRL_POLARITY_HIGH BIT(3) BIT 156 include/linux/mfd/stpmic1.h #define PWRCTRL_PIN_VALID BIT(2) BIT 157 include/linux/mfd/stpmic1.h #define RESTART_REQUEST_ENABLED BIT(1) BIT 158 include/linux/mfd/stpmic1.h #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0) BIT 164 include/linux/mfd/stpmic1.h #define WAKEUP_DETECTOR_DISABLED BIT(4) BIT 165 include/linux/mfd/stpmic1.h #define PWRCTRL_PD_ACTIVE BIT(3) BIT 166 include/linux/mfd/stpmic1.h #define PWRCTRL_PU_ACTIVE BIT(2) BIT 167 include/linux/mfd/stpmic1.h #define WAKEUP_PD_ACTIVE BIT(1) BIT 168 include/linux/mfd/stpmic1.h #define PONKEY_PU_INACTIVE BIT(0) BIT 174 include/linux/mfd/stpmic1.h #define SWIN_DETECTOR_ENABLED BIT(7) BIT 175 include/linux/mfd/stpmic1.h #define SWOUT_DETECTOR_ENABLED BIT(6) BIT 176 include/linux/mfd/stpmic1.h #define VINLOW_ENABLED BIT(0) BIT 182 include/linux/mfd/stpmic1.h #define BOOST_OVP_DISABLED BIT(7) BIT 183 include/linux/mfd/stpmic1.h #define VBUS_OTG_DETECTION_DISABLED BIT(6) BIT 184 include/linux/mfd/stpmic1.h #define SW_OUT_DISCHARGE BIT(5) BIT 185 include/linux/mfd/stpmic1.h #define VBUS_OTG_DISCHARGE BIT(4) BIT 186 include/linux/mfd/stpmic1.h #define OCP_LIMIT_HIGH BIT(3) BIT 187 include/linux/mfd/stpmic1.h #define SWIN_SWOUT_ENABLED BIT(2) BIT 188 include/linux/mfd/stpmic1.h #define USBSW_OTG_SWITCH_ENABLED BIT(1) BIT 189 include/linux/mfd/stpmic1.h #define BOOST_ENABLED BIT(0) BIT 194 include/linux/mfd/stpmic1.h #define PONKEY_PWR_OFF BIT(7) BIT 195 include/linux/mfd/stpmic1.h #define PONKEY_CC_FLAG_CLEAR BIT(6) BIT 13 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY_MODE BIT(23) BIT 14 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL0_ADC_CLK_SELECT BIT(22) BIT 22 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE_EN BIT(9) BIT 23 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL1_TOUCH_PAN_CALI_EN BIT(6) BIT 24 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL1_TP_DUAL_EN BIT(5) BIT 25 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL1_TP_MODE_EN BIT(4) BIT 26 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL1_TP_ADC_SELECT BIT(3) BIT 31 include/linux/mfd/sun4i-gpadc.h #define SUN6I_GPADC_CTRL1_TOUCH_PAN_CALI_EN BIT(7) BIT 32 include/linux/mfd/sun4i-gpadc.h #define SUN6I_GPADC_CTRL1_TP_DUAL_EN BIT(6) BIT 33 include/linux/mfd/sun4i-gpadc.h #define SUN6I_GPADC_CTRL1_TP_MODE_EN BIT(5) BIT 34 include/linux/mfd/sun4i-gpadc.h #define SUN6I_GPADC_CTRL1_TP_ADC_SELECT BIT(4) BIT 35 include/linux/mfd/sun4i-gpadc.h #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x)) BIT 39 include/linux/mfd/sun4i-gpadc.h #define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8) BIT 40 include/linux/mfd/sun4i-gpadc.h #define SUN8I_GPADC_CTRL1_GPADC_CALI_EN BIT(7) BIT 46 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL2_PRE_MEA_EN BIT(24) BIT 51 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL3_FILTER_EN BIT(2) BIT 56 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_TPR_TEMP_ENABLE BIT(16) BIT 61 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN BIT(18) BIT 62 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOC_TP_OVERRUN_IRQ_EN BIT(17) BIT 63 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN BIT(16) BIT 64 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOC_TP_DATA_XY_CHANGE BIT(13) BIT 66 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOC_TP_DATA_DRQ_EN BIT(7) BIT 67 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH BIT(4) BIT 68 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN BIT(1) BIT 69 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN BIT(0) BIT 73 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING BIT(18) BIT 74 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOS_FIFO_OVERRUN_PENDING BIT(17) BIT 75 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOS_FIFO_DATA_PENDING BIT(16) BIT 76 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOS_TP_IDLE_FLG BIT(2) BIT 77 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING BIT(1) BIT 78 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING BIT(0) BIT 97 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_RCB(x) BIT(x) BIT 100 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_DBPUC BIT(8) BIT 101 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_DBPDC BIT(9) BIT 102 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_VDDIOMSEL BIT(16) BIT 105 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_EBI_IOSR BIT(17) BIT 106 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_DDR_IOSR BIT(18) BIT 107 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_NFD0_SELECT BIT(24) BIT 108 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_DDR_MP_EN BIT(25) BIT 111 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_USBPUCR_PUON BIT(30) BIT 16 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_RCB BIT(0) BIT 19 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_UNADD BIT(0) BIT 20 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_MISADD BIT(1) BIT 29 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_MST(n) BIT(16 + (n)) BIT 30 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SVMST(n) BIT(24 + (n)) BIT 39 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_EBI_CS(n) BIT(x) BIT 43 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_EBI_DBPUC BIT(0) BIT 49 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SMC_WSEN BIT(7) BIT 53 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SMC_BAT BIT(12) BIT 57 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SMC_DPR BIT(15) BIT 75 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_DBW_16 BIT(4) BIT 90 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_NB BIT(4) BIT 103 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_SRCB BIT(0) BIT 106 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_LPCB BIT(0) BIT 112 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_RES BIT(0) BIT 135 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_BFC_BAAEN BIT(16) BIT 136 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_BFC_BFOEH BIT(17) BIT 137 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_BFC_MUXEN BIT(18) BIT 138 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_BFC_RDYEN BIT(19) BIT 35 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_SMC_MODE_READMODE_MASK BIT(0) BIT 38 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_SMC_MODE_WRITEMODE_MASK BIT(1) BIT 45 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_SMC_MODE_BAT_MASK BIT(8) BIT 56 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED BIT(20) BIT 57 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_SMC_MODE_PMEN BIT(24) BIT 66 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_HSMC_TIMINGS_OCMS BIT(12) BIT 68 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_HSMC_TIMINGS_NFSEL BIT(31) BIT 16 include/linux/mfd/syscon/atmel-st.h #define AT91_ST_WDRST BIT(0) /* Watchdog Timer Restart */ BIT 23 include/linux/mfd/syscon/atmel-st.h #define AT91_ST_RSTEN BIT(16) /* Reset Enable */ BIT 24 include/linux/mfd/syscon/atmel-st.h #define AT91_ST_EXTEN BIT(17) /* External Signal Assertion Enable */ BIT 30 include/linux/mfd/syscon/atmel-st.h #define AT91_ST_PITS BIT(0) /* Period Interval Timer Status */ BIT 31 include/linux/mfd/syscon/atmel-st.h #define AT91_ST_WDOVF BIT(1) /* Watchdog Overflow */ BIT 32 include/linux/mfd/syscon/atmel-st.h #define AT91_ST_RTTINC BIT(2) /* Real-time Timer Increment */ BIT 33 include/linux/mfd/syscon/atmel-st.h #define AT91_ST_ALMS BIT(3) /* Alarm Status */ BIT 69 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7) BIT 71 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7) BIT 72 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6) BIT 74 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6) BIT 75 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5) BIT 77 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5) BIT 78 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4) BIT 80 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4) BIT 81 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3) BIT 83 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3) BIT 84 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK BIT(2) BIT 86 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2 BIT(2) BIT 87 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK BIT(1) BIT 89 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3 BIT(1) BIT 90 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK BIT(0) BIT 92 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0) BIT 95 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_PCIE_SW_RST BIT(29) BIT 96 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28) BIT 97 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27) BIT 98 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26) BIT 99 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25) BIT 100 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_DPI_OFF BIT(24) BIT 101 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_EXC_MON_MASK BIT(22) BIT 103 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_EXC_MON_SLVE BIT(22) BIT 104 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21) BIT 106 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21) BIT 107 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20) BIT 109 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) BIT 110 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19) BIT 112 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) BIT 113 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_PCIE_TEST_PD BIT(18) BIT 114 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17) BIT 116 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17) BIT 117 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16) BIT 118 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_USB_EXP_MODE BIT(15) BIT 119 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_PCIE_INT BIT(14) BIT 120 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13) BIT 122 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13) BIT 123 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_GINT BIT(12) BIT 128 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_ACT_CS3 BIT(9) BIT 130 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_ACT_CS2 BIT(6) BIT 132 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_ACT_CS1 BIT(3) BIT 134 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR1_ACT_CS0 BIT(0) BIT 150 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_BGREF_RRMODE_MASK BIT(15) BIT 152 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR BIT(15) BIT 153 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_DI1_VS_POLARITY_MASK BIT(10) BIT 155 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L BIT(10) BIT 156 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_DI0_VS_POLARITY_MASK BIT(9) BIT 158 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L BIT(9) BIT 159 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK BIT(8) BIT 161 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA BIT(8) BIT 162 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK BIT(7) BIT 164 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT BIT(7) BIT 165 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK BIT(6) BIT 167 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA BIT(6) BIT 168 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK BIT(5) BIT 170 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT BIT(5) BIT 171 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR2_SPLIT_MODE_EN BIT(4) BIT 185 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_BCH_WR_CACHE_CTL BIT(28) BIT 186 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_BCH_RD_CACHE_CTL BIT(27) BIT 187 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL BIT(26) BIT 188 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL BIT(25) BIT 191 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_CORE3_DBG_ACK_EN BIT(16) BIT 192 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_CORE2_DBG_ACK_EN BIT(15) BIT 193 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_CORE1_DBG_ACK_EN BIT(14) BIT 194 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_CORE0_DBG_ACK_EN BIT(13) BIT 195 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_TZASC2_BOOT_LOCK BIT(12) BIT 196 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_TZASC1_BOOT_LOCK BIT(11) BIT 197 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR3_IPU_DIAG_MASK BIT(10) BIT 221 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_VDOA_WR_CACHE_SEL BIT(31) BIT 222 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_VDOA_RD_CACHE_SEL BIT(30) BIT 223 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_VDOA_WR_CACHE_VAL BIT(29) BIT 224 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_VDOA_RD_CACHE_VAL BIT(28) BIT 225 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_PCIE_WR_CACHE_SEL BIT(27) BIT 226 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_PCIE_RD_CACHE_SEL BIT(26) BIT 227 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_PCIE_WR_CACHE_VAL BIT(25) BIT 228 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_PCIE_RD_CACHE_VAL BIT(24) BIT 229 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19) BIT 230 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_CAN2_STOP_ACK BIT(18) BIT 231 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_CAN1_STOP_ACK BIT(17) BIT 232 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_ENET_STOP_ACK BIT(16) BIT 235 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_VPU_WR_CACHE_SEL BIT(7) BIT 236 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_VPU_RD_CACHE_SEL BIT(6) BIT 237 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL BIT(3) BIT 238 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK BIT(2) BIT 239 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_IPU_WR_CACHE_CTL BIT(1) BIT 240 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) BIT 242 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) BIT 243 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR5_SATA_SW_PD BIT(10) BIT 244 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR5_SATA_SW_RST BIT(11) BIT 270 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR9_TZASC2_BYP BIT(1) BIT 271 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR9_TZASC1_BYP BIT(0) BIT 273 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR10_LOCK_DBG_EN BIT(29) BIT 274 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR10_LOCK_DBG_CLK_EN BIT(28) BIT 275 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR10_LOCK_SEC_ERR_RESP BIT(27) BIT 277 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN BIT(20) BIT 280 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR10_DBG_EN BIT(13) BIT 281 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR10_DBG_CLK_EN BIT(12) BIT 282 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR10_SEC_ERR_RESP_MASK BIT(11) BIT 284 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR10_SEC_ERR_RESP_SLVE BIT(11) BIT 286 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4) BIT 298 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27) BIT 299 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) BIT 300 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) BIT 301 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) BIT 303 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) BIT 306 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) BIT 307 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) BIT 308 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28) BIT 309 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR13_ENET_STOP_REQ BIT(27) BIT 331 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR13_SATA_SPD_MODE_MASK BIT(15) BIT 333 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR13_SATA_SPD_MODE_3P0G BIT(15) BIT 334 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR13_SATA_MPLL_SS_EN BIT(14) BIT 392 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1) BIT 393 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0) BIT 434 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6SX_GPR5_PCIE_BTNRST_RESET BIT(19) BIT 448 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30) BIT 449 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h #define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16) BIT 44 include/linux/mfd/syscon/imx7-iomuxc-gpr.h #define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5) BIT 46 include/linux/mfd/syscon/imx7-iomuxc-gpr.h #define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31) BIT 17 include/linux/mfd/ti-lmu-register.h #define LM3631_LCD_EN_MASK BIT(1) BIT 18 include/linux/mfd/ti-lmu-register.h #define LM3631_BL_EN_MASK BIT(0) BIT 24 include/linux/mfd/ti-lmu-register.h #define LM3631_BL_CHANNEL_MASK BIT(3) BIT 26 include/linux/mfd/ti-lmu-register.h #define LM3631_BL_SINGLE_CHANNEL BIT(3) BIT 27 include/linux/mfd/ti-lmu-register.h #define LM3631_MAP_MASK BIT(5) BIT 31 include/linux/mfd/ti-lmu-register.h #define LM3631_MODE_MASK (BIT(1) | BIT(2) | BIT(3)) BIT 32 include/linux/mfd/ti-lmu-register.h #define LM3631_DEFAULT_MODE (BIT(1) | BIT(3)) BIT 39 include/linux/mfd/ti-lmu-register.h #define LM3631_EN_OREF_MASK BIT(0) BIT 40 include/linux/mfd/ti-lmu-register.h #define LM3631_EN_VNEG_MASK BIT(1) BIT 41 include/linux/mfd/ti-lmu-register.h #define LM3631_EN_VPOS_MASK BIT(2) BIT 44 include/linux/mfd/ti-lmu-register.h #define LM3631_EN_CONT_MASK BIT(0) BIT 47 include/linux/mfd/ti-lmu-register.h #define LM3631_VOUT_CONT_MASK (BIT(6) | BIT(7)) BIT 68 include/linux/mfd/ti-lmu-register.h #define LM3632_OVP_MASK (BIT(5) | BIT(6) | BIT(7)) BIT 69 include/linux/mfd/ti-lmu-register.h #define LM3632_OVP_25V BIT(6) BIT 72 include/linux/mfd/ti-lmu-register.h #define LM3632_SWFREQ_MASK BIT(7) BIT 73 include/linux/mfd/ti-lmu-register.h #define LM3632_SWFREQ_1MHZ BIT(7) BIT 79 include/linux/mfd/ti-lmu-register.h #define LM3632_PWM_MASK BIT(6) BIT 81 include/linux/mfd/ti-lmu-register.h #define LM3632_PWM_MODE BIT(6) BIT 84 include/linux/mfd/ti-lmu-register.h #define LM3632_BL_EN_MASK BIT(0) BIT 85 include/linux/mfd/ti-lmu-register.h #define LM3632_BL_CHANNEL_MASK (BIT(3) | BIT(4)) BIT 86 include/linux/mfd/ti-lmu-register.h #define LM3632_BL_SINGLE_CHANNEL BIT(4) BIT 87 include/linux/mfd/ti-lmu-register.h #define LM3632_BL_DUAL_CHANNEL BIT(3) BIT 90 include/linux/mfd/ti-lmu-register.h #define LM3632_EXT_EN_MASK BIT(0) BIT 91 include/linux/mfd/ti-lmu-register.h #define LM3632_EN_VNEG_MASK BIT(1) BIT 92 include/linux/mfd/ti-lmu-register.h #define LM3632_EN_VPOS_MASK BIT(2) BIT 103 include/linux/mfd/ti-lmu-register.h #define LM3633_HVLED1_CFG_MASK BIT(0) BIT 104 include/linux/mfd/ti-lmu-register.h #define LM3633_HVLED2_CFG_MASK BIT(1) BIT 105 include/linux/mfd/ti-lmu-register.h #define LM3633_HVLED3_CFG_MASK BIT(2) BIT 131 include/linux/mfd/ti-lmu-register.h #define LM3633_LED_EXPONENTIAL BIT(1) BIT 145 include/linux/mfd/ti-lmu-register.h #define LM3633_OVP_MASK (BIT(1) | BIT(2)) BIT 149 include/linux/mfd/ti-lmu-register.h #define LM3633_PWM_A_MASK BIT(0) BIT 150 include/linux/mfd/ti-lmu-register.h #define LM3633_PWM_B_MASK BIT(1) BIT 179 include/linux/mfd/ti-lmu-register.h #define LM3695_BL_CHANNEL_MASK BIT(3) BIT 181 include/linux/mfd/ti-lmu-register.h #define LM3695_BL_SINGLE_CHANNEL BIT(3) BIT 182 include/linux/mfd/ti-lmu-register.h #define LM3695_BRT_RW_MASK BIT(2) BIT 183 include/linux/mfd/ti-lmu-register.h #define LM3695_BL_EN_MASK BIT(0) BIT 199 include/linux/mfd/ti-lmu-register.h #define LM36274_EXT_EN_MASK BIT(0) BIT 200 include/linux/mfd/ti-lmu-register.h #define LM36274_EN_VNEG_MASK BIT(1) BIT 201 include/linux/mfd/ti-lmu-register.h #define LM36274_EN_VPOS_MASK BIT(2) BIT 47 include/linux/mfd/ti_am335x_tscadc.h #define IRQWKUP_ENB BIT(0) BIT 57 include/linux/mfd/ti_am335x_tscadc.h #define IRQENB_HW_PEN BIT(0) BIT 58 include/linux/mfd/ti_am335x_tscadc.h #define IRQENB_EOS BIT(1) BIT 59 include/linux/mfd/ti_am335x_tscadc.h #define IRQENB_FIFO0THRES BIT(2) BIT 60 include/linux/mfd/ti_am335x_tscadc.h #define IRQENB_FIFO0OVRRUN BIT(3) BIT 61 include/linux/mfd/ti_am335x_tscadc.h #define IRQENB_FIFO0UNDRFLW BIT(4) BIT 62 include/linux/mfd/ti_am335x_tscadc.h #define IRQENB_FIFO1THRES BIT(5) BIT 63 include/linux/mfd/ti_am335x_tscadc.h #define IRQENB_FIFO1OVRRUN BIT(6) BIT 64 include/linux/mfd/ti_am335x_tscadc.h #define IRQENB_FIFO1UNDRFLW BIT(7) BIT 65 include/linux/mfd/ti_am335x_tscadc.h #define IRQENB_PENUP BIT(9) BIT 75 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_XPP BIT(5) BIT 76 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_XNN BIT(6) BIT 77 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_YPP BIT(7) BIT 78 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_YNN BIT(8) BIT 79 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_XNP BIT(9) BIT 80 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_YPN BIT(10) BIT 90 include/linux/mfd/ti_am335x_tscadc.h #define STEPCONFIG_FIFO1 BIT(26) BIT 121 include/linux/mfd/ti_am335x_tscadc.h #define CNTRLREG_TSCSSENB BIT(0) BIT 122 include/linux/mfd/ti_am335x_tscadc.h #define CNTRLREG_STEPID BIT(1) BIT 123 include/linux/mfd/ti_am335x_tscadc.h #define CNTRLREG_STEPCONFIGWRT BIT(2) BIT 124 include/linux/mfd/ti_am335x_tscadc.h #define CNTRLREG_POWERDOWN BIT(4) BIT 130 include/linux/mfd/ti_am335x_tscadc.h #define CNTRLREG_TSCENB BIT(7) BIT 137 include/linux/mfd/ti_am335x_tscadc.h #define DMA_FIFO0 BIT(0) BIT 138 include/linux/mfd/ti_am335x_tscadc.h #define DMA_FIFO1 BIT(1) BIT 141 include/linux/mfd/ti_am335x_tscadc.h #define SEQ_STATUS BIT(5) BIT 43 include/linux/mfd/tmio.h #define TMIO_MMC_BLKSZ_2BYTES BIT(1) BIT 47 include/linux/mfd/tmio.h #define TMIO_MMC_SDIO_IRQ BIT(2) BIT 50 include/linux/mfd/tmio.h #define TMIO_MMC_MIN_RCAR2 BIT(3) BIT 56 include/linux/mfd/tmio.h #define TMIO_MMC_HAS_IDLE_WAIT BIT(4) BIT 64 include/linux/mfd/tmio.h #define TMIO_MMC_HAVE_CMD12_CTRL BIT(7) BIT 67 include/linux/mfd/tmio.h #define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8) BIT 72 include/linux/mfd/tmio.h #define TMIO_MMC_32BIT_DATA_PORT BIT(9) BIT 77 include/linux/mfd/tmio.h #define TMIO_MMC_CLK_ACTUAL BIT(10) BIT 80 include/linux/mfd/tmio.h #define TMIO_MMC_HAVE_CBSY BIT(11) BIT 83 include/linux/mfd/tmio.h #define TMIO_MMC_HAVE_4TAP_HS400 BIT(13) BIT 23 include/linux/mfd/tps6507x.h #define TPS6507X_CHG_USB BIT(7) BIT 24 include/linux/mfd/tps6507x.h #define TPS6507X_CHG_AC BIT(6) BIT 25 include/linux/mfd/tps6507x.h #define TPS6507X_CHG_USB_PW_ENABLE BIT(5) BIT 26 include/linux/mfd/tps6507x.h #define TPS6507X_CHG_AC_PW_ENABLE BIT(4) BIT 27 include/linux/mfd/tps6507x.h #define TPS6507X_CHG_AC_CURRENT BIT(2) BIT 28 include/linux/mfd/tps6507x.h #define TPS6507X_CHG_USB_CURRENT BIT(0) BIT 31 include/linux/mfd/tps6507x.h #define TPS6507X_REG_MASK_AC_USB BIT(7) BIT 32 include/linux/mfd/tps6507x.h #define TPS6507X_REG_MASK_TSC BIT(6) BIT 33 include/linux/mfd/tps6507x.h #define TPS6507X_REG_MASK_PB_IN BIT(5) BIT 34 include/linux/mfd/tps6507x.h #define TPS6507X_REG_TSC_INT BIT(3) BIT 35 include/linux/mfd/tps6507x.h #define TPS6507X_REG_PB_IN_INT BIT(2) BIT 36 include/linux/mfd/tps6507x.h #define TPS6507X_REG_AC_USB_APPLIED BIT(1) BIT 37 include/linux/mfd/tps6507x.h #define TPS6507X_REG_AC_USB_REMOVED BIT(0) BIT 42 include/linux/mfd/tps6507x.h #define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4) BIT 43 include/linux/mfd/tps6507x.h #define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3) BIT 44 include/linux/mfd/tps6507x.h #define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2) BIT 45 include/linux/mfd/tps6507x.h #define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1) BIT 46 include/linux/mfd/tps6507x.h #define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0) BIT 53 include/linux/mfd/tps6507x.h #define TPS6507X_ADCONFIG_AD_ENABLE BIT(7) BIT 54 include/linux/mfd/tps6507x.h #define TPS6507X_ADCONFIG_START_CONVERSION BIT(6) BIT 55 include/linux/mfd/tps6507x.h #define TPS6507X_ADCONFIG_CONVERSION_DONE BIT(5) BIT 56 include/linux/mfd/tps6507x.h #define TPS6507X_ADCONFIG_VREF_ENABLE BIT(4) BIT 86 include/linux/mfd/tps6507x.h #define TPS6507X_REG_ADRESULT_2_MASK (BIT(1) | BIT(0)) BIT 93 include/linux/mfd/tps6507x.h #define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4) BIT 94 include/linux/mfd/tps6507x.h #define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3) BIT 95 include/linux/mfd/tps6507x.h #define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2) BIT 96 include/linux/mfd/tps6507x.h #define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1) BIT 97 include/linux/mfd/tps6507x.h #define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0) BIT 104 include/linux/mfd/tps6507x.h #define TPS6507X_DEFDCDC1_DCDC1_EXT_ADJ_EN BIT(7) BIT 82 include/linux/mfd/tps65086.h #define TPS65086_IRQ_DIETEMP_MASK BIT(0) BIT 83 include/linux/mfd/tps65086.h #define TPS65086_IRQ_SHUTDN_MASK BIT(3) BIT 84 include/linux/mfd/tps65086.h #define TPS65086_IRQ_FAULT_MASK BIT(7) BIT 138 include/linux/mfd/tps65090.h return regmap_update_bits(tps->rmap, reg, BIT(bit_num), ~0u); BIT 146 include/linux/mfd/tps65090.h return regmap_update_bits(tps->rmap, reg, BIT(bit_num), 0u); BIT 69 include/linux/mfd/tps65217.h #define TPS65217_PPATH_ACSINK_ENABLE BIT(7) BIT 70 include/linux/mfd/tps65217.h #define TPS65217_PPATH_USBSINK_ENABLE BIT(6) BIT 71 include/linux/mfd/tps65217.h #define TPS65217_PPATH_AC_PW_ENABLE BIT(5) BIT 72 include/linux/mfd/tps65217.h #define TPS65217_PPATH_USB_PW_ENABLE BIT(4) BIT 76 include/linux/mfd/tps65217.h #define TPS65217_INT_PBM BIT(6) BIT 77 include/linux/mfd/tps65217.h #define TPS65217_INT_ACM BIT(5) BIT 78 include/linux/mfd/tps65217.h #define TPS65217_INT_USBM BIT(4) BIT 79 include/linux/mfd/tps65217.h #define TPS65217_INT_PBI BIT(2) BIT 80 include/linux/mfd/tps65217.h #define TPS65217_INT_ACI BIT(1) BIT 81 include/linux/mfd/tps65217.h #define TPS65217_INT_USBI BIT(0) BIT 86 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG0_TREG BIT(7) BIT 87 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG0_DPPM BIT(6) BIT 88 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG0_TSUSP BIT(5) BIT 89 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG0_TERMI BIT(4) BIT 90 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG0_ACTIVE BIT(3) BIT 91 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG0_CHGTOUT BIT(2) BIT 92 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1) BIT 93 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG0_BATTEMP BIT(0) BIT 96 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5) BIT 97 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4) BIT 98 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG1_RESET BIT(3) BIT 99 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG1_TERM BIT(2) BIT 100 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG1_SUSP BIT(1) BIT 101 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG1_CHG_EN BIT(0) BIT 103 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG2_DYNTMR BIT(7) BIT 104 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG2_VPREGHG BIT(6) BIT 109 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG2_PCHRGT BIT(3) BIT 111 include/linux/mfd/tps65217.h #define TPS65217_CHGCONFIG2_TRANGE BIT(0) BIT 113 include/linux/mfd/tps65217.h #define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3) BIT 114 include/linux/mfd/tps65217.h #define TPS65217_WLEDCTRL1_ISEL BIT(2) BIT 121 include/linux/mfd/tps65217.h #define TPS65217_STATUS_OFF BIT(7) BIT 122 include/linux/mfd/tps65217.h #define TPS65217_STATUS_ACPWR BIT(3) BIT 123 include/linux/mfd/tps65217.h #define TPS65217_STATUS_USBPWR BIT(2) BIT 124 include/linux/mfd/tps65217.h #define TPS65217_STATUS_PB BIT(0) BIT 128 include/linux/mfd/tps65217.h #define TPS65217_PGOOD_LDO3_PG BIT(6) BIT 129 include/linux/mfd/tps65217.h #define TPS65217_PGOOD_LDO4_PG BIT(5) BIT 130 include/linux/mfd/tps65217.h #define TPS65217_PGOOD_DC1_PG BIT(4) BIT 131 include/linux/mfd/tps65217.h #define TPS65217_PGOOD_DC2_PG BIT(3) BIT 132 include/linux/mfd/tps65217.h #define TPS65217_PGOOD_DC3_PG BIT(2) BIT 133 include/linux/mfd/tps65217.h #define TPS65217_PGOOD_LDO1_PG BIT(1) BIT 134 include/linux/mfd/tps65217.h #define TPS65217_PGOOD_LDO2_PG BIT(0) BIT 136 include/linux/mfd/tps65217.h #define TPS65217_DEFPG_LDO1PGM BIT(3) BIT 137 include/linux/mfd/tps65217.h #define TPS65217_DEFPG_LDO2PGM BIT(2) BIT 140 include/linux/mfd/tps65217.h #define TPS65217_DEFDCDCX_XADJX BIT(7) BIT 143 include/linux/mfd/tps65217.h #define TPS65217_DEFSLEW_GO BIT(7) BIT 144 include/linux/mfd/tps65217.h #define TPS65217_DEFSLEW_GODSBL BIT(6) BIT 145 include/linux/mfd/tps65217.h #define TPS65217_DEFSLEW_PFM_EN1 BIT(5) BIT 146 include/linux/mfd/tps65217.h #define TPS65217_DEFSLEW_PFM_EN2 BIT(4) BIT 147 include/linux/mfd/tps65217.h #define TPS65217_DEFSLEW_PFM_EN3 BIT(3) BIT 152 include/linux/mfd/tps65217.h #define TPS65217_DEFLDO2_TRACK BIT(6) BIT 155 include/linux/mfd/tps65217.h #define TPS65217_DEFLDO3_LDO3_EN BIT(5) BIT 158 include/linux/mfd/tps65217.h #define TPS65217_DEFLDO4_LDO4_EN BIT(5) BIT 161 include/linux/mfd/tps65217.h #define TPS65217_ENABLE_LS1_EN BIT(6) BIT 162 include/linux/mfd/tps65217.h #define TPS65217_ENABLE_LS2_EN BIT(5) BIT 163 include/linux/mfd/tps65217.h #define TPS65217_ENABLE_DC1_EN BIT(4) BIT 164 include/linux/mfd/tps65217.h #define TPS65217_ENABLE_DC2_EN BIT(3) BIT 165 include/linux/mfd/tps65217.h #define TPS65217_ENABLE_DC3_EN BIT(2) BIT 166 include/linux/mfd/tps65217.h #define TPS65217_ENABLE_LDO1_EN BIT(1) BIT 167 include/linux/mfd/tps65217.h #define TPS65217_ENABLE_LDO2_EN BIT(0) BIT 169 include/linux/mfd/tps65217.h #define TPS65217_DEFUVLO_UVLOHYS BIT(2) BIT 190 include/linux/mfd/tps65217.h #define TPS65217_SEQ6_SEQUP BIT(2) BIT 191 include/linux/mfd/tps65217.h #define TPS65217_SEQ6_SEQDWN BIT(1) BIT 192 include/linux/mfd/tps65217.h #define TPS65217_SEQ6_INSTDWN BIT(0) BIT 71 include/linux/mfd/tps65218.h #define TPS65218_INT1_VPRG BIT(5) BIT 72 include/linux/mfd/tps65218.h #define TPS65218_INT1_AC BIT(4) BIT 73 include/linux/mfd/tps65218.h #define TPS65218_INT1_PB BIT(3) BIT 74 include/linux/mfd/tps65218.h #define TPS65218_INT1_HOT BIT(2) BIT 75 include/linux/mfd/tps65218.h #define TPS65218_INT1_CC_AQC BIT(1) BIT 76 include/linux/mfd/tps65218.h #define TPS65218_INT1_PRGC BIT(0) BIT 78 include/linux/mfd/tps65218.h #define TPS65218_INT2_LS3_F BIT(5) BIT 79 include/linux/mfd/tps65218.h #define TPS65218_INT2_LS2_F BIT(4) BIT 80 include/linux/mfd/tps65218.h #define TPS65218_INT2_LS1_F BIT(3) BIT 81 include/linux/mfd/tps65218.h #define TPS65218_INT2_LS3_I BIT(2) BIT 82 include/linux/mfd/tps65218.h #define TPS65218_INT2_LS2_I BIT(1) BIT 83 include/linux/mfd/tps65218.h #define TPS65218_INT2_LS1_I BIT(0) BIT 85 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK1_VPRG BIT(5) BIT 86 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK1_AC BIT(4) BIT 87 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK1_PB BIT(3) BIT 88 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK1_HOT BIT(2) BIT 89 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK1_CC_AQC BIT(1) BIT 90 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK1_PRGC BIT(0) BIT 92 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK2_LS3_F BIT(5) BIT 93 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK2_LS2_F BIT(4) BIT 94 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK2_LS1_F BIT(3) BIT 95 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK2_LS3_I BIT(2) BIT 96 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK2_LS2_I BIT(1) BIT 97 include/linux/mfd/tps65218.h #define TPS65218_INT_MASK2_LS1_I BIT(0) BIT 99 include/linux/mfd/tps65218.h #define TPS65218_STATUS_FSEAL BIT(7) BIT 100 include/linux/mfd/tps65218.h #define TPS65218_STATUS_EE BIT(6) BIT 101 include/linux/mfd/tps65218.h #define TPS65218_STATUS_AC_STATE BIT(5) BIT 102 include/linux/mfd/tps65218.h #define TPS65218_STATUS_PB_STATE BIT(4) BIT 106 include/linux/mfd/tps65218.h #define TPS65218_CONTROL_OFFNPFO BIT(1) BIT 107 include/linux/mfd/tps65218.h #define TPS65218_CONTROL_CC_AQ BIT(0) BIT 109 include/linux/mfd/tps65218.h #define TPS65218_FLAG_GPO3_FLG BIT(7) BIT 110 include/linux/mfd/tps65218.h #define TPS65218_FLAG_GPO2_FLG BIT(6) BIT 111 include/linux/mfd/tps65218.h #define TPS65218_FLAG_GPO1_FLG BIT(5) BIT 112 include/linux/mfd/tps65218.h #define TPS65218_FLAG_LDO1_FLG BIT(4) BIT 113 include/linux/mfd/tps65218.h #define TPS65218_FLAG_DC4_FLG BIT(3) BIT 114 include/linux/mfd/tps65218.h #define TPS65218_FLAG_DC3_FLG BIT(2) BIT 115 include/linux/mfd/tps65218.h #define TPS65218_FLAG_DC2_FLG BIT(1) BIT 116 include/linux/mfd/tps65218.h #define TPS65218_FLAG_DC1_FLG BIT(0) BIT 118 include/linux/mfd/tps65218.h #define TPS65218_ENABLE1_DC6_EN BIT(5) BIT 119 include/linux/mfd/tps65218.h #define TPS65218_ENABLE1_DC5_EN BIT(4) BIT 120 include/linux/mfd/tps65218.h #define TPS65218_ENABLE1_DC4_EN BIT(3) BIT 121 include/linux/mfd/tps65218.h #define TPS65218_ENABLE1_DC3_EN BIT(2) BIT 122 include/linux/mfd/tps65218.h #define TPS65218_ENABLE1_DC2_EN BIT(1) BIT 123 include/linux/mfd/tps65218.h #define TPS65218_ENABLE1_DC1_EN BIT(0) BIT 125 include/linux/mfd/tps65218.h #define TPS65218_ENABLE2_GPIO3 BIT(6) BIT 126 include/linux/mfd/tps65218.h #define TPS65218_ENABLE2_GPIO2 BIT(5) BIT 127 include/linux/mfd/tps65218.h #define TPS65218_ENABLE2_GPIO1 BIT(4) BIT 128 include/linux/mfd/tps65218.h #define TPS65218_ENABLE2_LS3_EN BIT(3) BIT 129 include/linux/mfd/tps65218.h #define TPS65218_ENABLE2_LS2_EN BIT(2) BIT 130 include/linux/mfd/tps65218.h #define TPS65218_ENABLE2_LS1_EN BIT(1) BIT 131 include/linux/mfd/tps65218.h #define TPS65218_ENABLE2_LDO1_EN BIT(0) BIT 134 include/linux/mfd/tps65218.h #define TPS65218_CONFIG1_TRST BIT(7) BIT 135 include/linux/mfd/tps65218.h #define TPS65218_CONFIG1_GPO2_BUF BIT(6) BIT 136 include/linux/mfd/tps65218.h #define TPS65218_CONFIG1_IO1_SEL BIT(5) BIT 138 include/linux/mfd/tps65218.h #define TPS65218_CONFIG1_STRICT BIT(2) BIT 145 include/linux/mfd/tps65218.h #define TPS65218_CONFIG2_DC12_RST BIT(7) BIT 146 include/linux/mfd/tps65218.h #define TPS65218_CONFIG2_UVLOHYS BIT(6) BIT 150 include/linux/mfd/tps65218.h #define TPS65218_CONFIG3_LS3NPFO BIT(5) BIT 151 include/linux/mfd/tps65218.h #define TPS65218_CONFIG3_LS2NPFO BIT(4) BIT 152 include/linux/mfd/tps65218.h #define TPS65218_CONFIG3_LS1NPFO BIT(3) BIT 153 include/linux/mfd/tps65218.h #define TPS65218_CONFIG3_LS3DCHRG BIT(2) BIT 154 include/linux/mfd/tps65218.h #define TPS65218_CONFIG3_LS2DCHRG BIT(1) BIT 155 include/linux/mfd/tps65218.h #define TPS65218_CONFIG3_LS1DCHRG BIT(0) BIT 157 include/linux/mfd/tps65218.h #define TPS65218_CONTROL_DCDC1_PFM BIT(7) BIT 160 include/linux/mfd/tps65218.h #define TPS65218_CONTROL_DCDC2_PFM BIT(7) BIT 163 include/linux/mfd/tps65218.h #define TPS65218_CONTROL_DCDC3_PFM BIT(7) BIT 166 include/linux/mfd/tps65218.h #define TPS65218_CONTROL_DCDC4_PFM BIT(7) BIT 169 include/linux/mfd/tps65218.h #define TPS65218_SLEW_RATE_GO BIT(7) BIT 170 include/linux/mfd/tps65218.h #define TPS65218_SLEW_RATE_GODSBL BIT(6) BIT 175 include/linux/mfd/tps65218.h #define TPS65218_SEQ1_DLY8 BIT(7) BIT 176 include/linux/mfd/tps65218.h #define TPS65218_SEQ1_DLY7 BIT(6) BIT 177 include/linux/mfd/tps65218.h #define TPS65218_SEQ1_DLY6 BIT(5) BIT 178 include/linux/mfd/tps65218.h #define TPS65218_SEQ1_DLY5 BIT(4) BIT 179 include/linux/mfd/tps65218.h #define TPS65218_SEQ1_DLY4 BIT(3) BIT 180 include/linux/mfd/tps65218.h #define TPS65218_SEQ1_DLY3 BIT(2) BIT 181 include/linux/mfd/tps65218.h #define TPS65218_SEQ1_DLY2 BIT(1) BIT 182 include/linux/mfd/tps65218.h #define TPS65218_SEQ1_DLY1 BIT(0) BIT 184 include/linux/mfd/tps65218.h #define TPS65218_SEQ2_DLYFCTR BIT(7) BIT 185 include/linux/mfd/tps65218.h #define TPS65218_SEQ2_DLY9 BIT(0) BIT 805 include/linux/mfd/tps65910.h #define TPS65910_GPIO_DEB BIT(2) BIT 806 include/linux/mfd/tps65910.h #define TPS65910_GPIO_PUEN BIT(3) BIT 807 include/linux/mfd/tps65910.h #define TPS65910_GPIO_CFG BIT(2) BIT 808 include/linux/mfd/tps65910.h #define TPS65910_GPIO_STS BIT(1) BIT 809 include/linux/mfd/tps65910.h #define TPS65910_GPIO_SET BIT(0) BIT 129 include/linux/mfd/tps65912.h #define TPS65912_INT_STS_PWRHOLD_F BIT(0) BIT 130 include/linux/mfd/tps65912.h #define TPS65912_INT_STS_VMON BIT(1) BIT 131 include/linux/mfd/tps65912.h #define TPS65912_INT_STS_PWRON BIT(2) BIT 132 include/linux/mfd/tps65912.h #define TPS65912_INT_STS_PWRON_LP BIT(3) BIT 133 include/linux/mfd/tps65912.h #define TPS65912_INT_STS_PWRHOLD_R BIT(4) BIT 134 include/linux/mfd/tps65912.h #define TPS65912_INT_STS_HOTDIE BIT(5) BIT 135 include/linux/mfd/tps65912.h #define TPS65912_INT_STS_GPIO1_R BIT(6) BIT 136 include/linux/mfd/tps65912.h #define TPS65912_INT_STS_GPIO1_F BIT(7) BIT 139 include/linux/mfd/tps65912.h #define TPS65912_INT_STS2_GPIO2_R BIT(0) BIT 140 include/linux/mfd/tps65912.h #define TPS65912_INT_STS2_GPIO2_F BIT(1) BIT 141 include/linux/mfd/tps65912.h #define TPS65912_INT_STS2_GPIO3_R BIT(2) BIT 142 include/linux/mfd/tps65912.h #define TPS65912_INT_STS2_GPIO3_F BIT(3) BIT 143 include/linux/mfd/tps65912.h #define TPS65912_INT_STS2_GPIO4_R BIT(4) BIT 144 include/linux/mfd/tps65912.h #define TPS65912_INT_STS2_GPIO4_F BIT(5) BIT 145 include/linux/mfd/tps65912.h #define TPS65912_INT_STS2_GPIO5_R BIT(6) BIT 146 include/linux/mfd/tps65912.h #define TPS65912_INT_STS2_GPIO5_F BIT(7) BIT 149 include/linux/mfd/tps65912.h #define TPS65912_INT_STS3_PGOOD_DCDC1 BIT(0) BIT 150 include/linux/mfd/tps65912.h #define TPS65912_INT_STS3_PGOOD_DCDC2 BIT(1) BIT 151 include/linux/mfd/tps65912.h #define TPS65912_INT_STS3_PGOOD_DCDC3 BIT(2) BIT 152 include/linux/mfd/tps65912.h #define TPS65912_INT_STS3_PGOOD_DCDC4 BIT(3) BIT 153 include/linux/mfd/tps65912.h #define TPS65912_INT_STS3_PGOOD_LDO1 BIT(4) BIT 154 include/linux/mfd/tps65912.h #define TPS65912_INT_STS3_PGOOD_LDO2 BIT(5) BIT 155 include/linux/mfd/tps65912.h #define TPS65912_INT_STS3_PGOOD_LDO3 BIT(6) BIT 156 include/linux/mfd/tps65912.h #define TPS65912_INT_STS3_PGOOD_LDO4 BIT(7) BIT 159 include/linux/mfd/tps65912.h #define TPS65912_INT_STS4_PGOOD_LDO5 BIT(0) BIT 160 include/linux/mfd/tps65912.h #define TPS65912_INT_STS4_PGOOD_LDO6 BIT(1) BIT 161 include/linux/mfd/tps65912.h #define TPS65912_INT_STS4_PGOOD_LDO7 BIT(2) BIT 162 include/linux/mfd/tps65912.h #define TPS65912_INT_STS4_PGOOD_LDO8 BIT(3) BIT 163 include/linux/mfd/tps65912.h #define TPS65912_INT_STS4_PGOOD_LDO9 BIT(4) BIT 164 include/linux/mfd/tps65912.h #define TPS65912_INT_STS4_PGOOD_LDO10 BIT(5) BIT 234 include/linux/mfd/twl.h #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0) BIT 235 include/linux/mfd/twl.h #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1) BIT 236 include/linux/mfd/twl.h #define TWL4030_SIH_CTRL_COR_MASK BIT(2) BIT 307 include/linux/mfd/twl.h #define I2C_SCL_CTRL_PU BIT(0) BIT 308 include/linux/mfd/twl.h #define I2C_SDA_CTRL_PU BIT(2) BIT 309 include/linux/mfd/twl.h #define SR_I2C_SCL_CTRL_PU BIT(4) BIT 310 include/linux/mfd/twl.h #define SR_I2C_SDA_CTRL_PU BIT(6) BIT 755 include/linux/mfd/twl.h #define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */ BIT 756 include/linux/mfd/twl.h #define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */ BIT 757 include/linux/mfd/twl.h #define TWL5031 BIT(2) /* twl5031 has different registers */ BIT 758 include/linux/mfd/twl.h #define TWL6030_CLASS BIT(3) /* TWL6030 class */ BIT 759 include/linux/mfd/twl.h #define TWL6032_SUBCLASS BIT(4) /* TWL6032 has changed registers */ BIT 760 include/linux/mfd/twl.h #define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible BIT 125 include/linux/mfd/wl1273-core.h #define WL1273_MODE_RX BIT(0) BIT 126 include/linux/mfd/wl1273-core.h #define WL1273_MODE_TX BIT(1) BIT 127 include/linux/mfd/wl1273-core.h #define WL1273_MODE_OFF BIT(2) BIT 128 include/linux/mfd/wl1273-core.h #define WL1273_MODE_SUSPENDED BIT(3) BIT 130 include/linux/mfd/wl1273-core.h #define WL1273_RADIO_CHILD BIT(0) BIT 131 include/linux/mfd/wl1273-core.h #define WL1273_CODEC_CHILD BIT(1) BIT 145 include/linux/mfd/wl1273-core.h #define WL1273_AUDIO_ENABLE_I2S BIT(0) BIT 146 include/linux/mfd/wl1273-core.h #define WL1273_AUDIO_ENABLE_ANALOG BIT(1) BIT 210 include/linux/mfd/wl1273-core.h #define WL1273_FR_EVENT BIT(0) BIT 211 include/linux/mfd/wl1273-core.h #define WL1273_BL_EVENT BIT(1) BIT 212 include/linux/mfd/wl1273-core.h #define WL1273_RDS_EVENT BIT(2) BIT 213 include/linux/mfd/wl1273-core.h #define WL1273_BBLK_EVENT BIT(3) BIT 214 include/linux/mfd/wl1273-core.h #define WL1273_LSYNC_EVENT BIT(4) BIT 215 include/linux/mfd/wl1273-core.h #define WL1273_LEV_EVENT BIT(5) BIT 216 include/linux/mfd/wl1273-core.h #define WL1273_IFFR_EVENT BIT(6) BIT 217 include/linux/mfd/wl1273-core.h #define WL1273_PI_EVENT BIT(7) BIT 218 include/linux/mfd/wl1273-core.h #define WL1273_PD_EVENT BIT(8) BIT 219 include/linux/mfd/wl1273-core.h #define WL1273_STIC_EVENT BIT(9) BIT 220 include/linux/mfd/wl1273-core.h #define WL1273_MAL_EVENT BIT(10) BIT 221 include/linux/mfd/wl1273-core.h #define WL1273_POW_ENB_EVENT BIT(11) BIT 222 include/linux/mfd/wl1273-core.h #define WL1273_SCAN_OVER_EVENT BIT(12) BIT 223 include/linux/mfd/wl1273-core.h #define WL1273_ERROR_EVENT BIT(13) BIT 139 include/linux/mlx4/cq.h #define MLX4_MAX_CQ_PERIOD (BIT(16) - 1) BIT 140 include/linux/mlx4/cq.h #define MLX4_MAX_CQ_COUNT (BIT(16) - 1) BIT 133 include/linux/mlx5/cq.h #define MLX5_MAX_CQ_PERIOD (BIT(__mlx5_bit_sz(cqc, cq_period)) - 1) BIT 134 include/linux/mlx5/cq.h #define MLX5_MAX_CQ_COUNT (BIT(__mlx5_bit_sz(cqc, cq_max_count)) - 1) BIT 601 include/linux/mlx5/driver.h MLX5_INTERFACE_STATE_UP = BIT(0), BIT 48 include/linux/mlx5/fs.h MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT = BIT(0), BIT 49 include/linux/mlx5/fs.h MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1), BIT 50 include/linux/mlx5/fs.h MLX5_FLOW_TABLE_TERMINATION = BIT(2), BIT 95 include/linux/mlx5/fs.h FLOW_CONTEXT_HAS_TAG = BIT(0), BIT 112 include/linux/mlx5/fs.h MLX5_FLOW_DEST_VPORT_VHCA_ID = BIT(0), BIT 113 include/linux/mlx5/fs.h MLX5_FLOW_DEST_VPORT_REFORMAT_ID = BIT(1), BIT 195 include/linux/mlx5/fs.h FLOW_ACT_NO_APPEND = BIT(0), BIT 10215 include/linux/mlx5/mlx5_ifc.h MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc), BIT 515 include/linux/mlx5/mlx5_ifc_fpga.h MLX5_FPGA_IPSEC_CAP_NO_TRAILER = BIT(0), BIT 525 include/linux/mlx5/mlx5_ifc_fpga.h MLX5_FPGA_IPSEC_SA_ESN_EN = BIT(0), BIT 526 include/linux/mlx5/mlx5_ifc_fpga.h MLX5_FPGA_IPSEC_SA_ESN_OVERLAP = BIT(1), BIT 527 include/linux/mlx5/mlx5_ifc_fpga.h MLX5_FPGA_IPSEC_SA_IPV6 = BIT(2), BIT 528 include/linux/mlx5/mlx5_ifc_fpga.h MLX5_FPGA_IPSEC_SA_DIR_SX = BIT(3), BIT 529 include/linux/mlx5/mlx5_ifc_fpga.h MLX5_FPGA_IPSEC_SA_SPI_EN = BIT(4), BIT 530 include/linux/mlx5/mlx5_ifc_fpga.h MLX5_FPGA_IPSEC_SA_SA_VALID = BIT(5), BIT 531 include/linux/mlx5/mlx5_ifc_fpga.h MLX5_FPGA_IPSEC_SA_IP_ESP = BIT(6), BIT 532 include/linux/mlx5/mlx5_ifc_fpga.h MLX5_FPGA_IPSEC_SA_IP_AH = BIT(7), BIT 301 include/linux/mm.h #define VM_HIGH_ARCH_0 BIT(VM_HIGH_ARCH_BIT_0) BIT 302 include/linux/mm.h #define VM_HIGH_ARCH_1 BIT(VM_HIGH_ARCH_BIT_1) BIT 303 include/linux/mm.h #define VM_HIGH_ARCH_2 BIT(VM_HIGH_ARCH_BIT_2) BIT 304 include/linux/mm.h #define VM_HIGH_ARCH_3 BIT(VM_HIGH_ARCH_BIT_3) BIT 305 include/linux/mm.h #define VM_HIGH_ARCH_4 BIT(VM_HIGH_ARCH_BIT_4) BIT 127 include/linux/mmc/card.h #define MMC_DISCARD_FEATURE BIT(0) /* CMD38 feature */ BIT 126 include/linux/mmc/core.h #define MMC_DATA_WRITE BIT(8) BIT 127 include/linux/mmc/core.h #define MMC_DATA_READ BIT(9) BIT 129 include/linux/mmc/core.h #define MMC_DATA_QBR BIT(10) /* CQE queue barrier*/ BIT 130 include/linux/mmc/core.h #define MMC_DATA_PRIO BIT(11) /* CQE high priority */ BIT 131 include/linux/mmc/core.h #define MMC_DATA_REL_WR BIT(12) /* Reliable write */ BIT 132 include/linux/mmc/core.h #define MMC_DATA_DAT_TAG BIT(13) /* Tag request */ BIT 133 include/linux/mmc/core.h #define MMC_DATA_FORCED_PRG BIT(14) /* Forced programming */ BIT 362 include/linux/mmc/mmc.h #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */ BIT 370 include/linux/mmc/mmc.h #define EXT_CSD_SEC_ER_EN BIT(0) BIT 371 include/linux/mmc/mmc.h #define EXT_CSD_SEC_BD_BLK_EN BIT(2) BIT 372 include/linux/mmc/mmc.h #define EXT_CSD_SEC_GB_CL_EN BIT(4) BIT 373 include/linux/mmc/mmc.h #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */ BIT 388 include/linux/mmc/mmc.h #define EXT_CSD_PACKED_EVENT_EN BIT(3) BIT 393 include/linux/mmc/mmc.h #define EXT_CSD_URGENT_BKOPS BIT(0) BIT 394 include/linux/mmc/mmc.h #define EXT_CSD_DYNCAP_NEEDED BIT(1) BIT 395 include/linux/mmc/mmc.h #define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2) BIT 396 include/linux/mmc/mmc.h #define EXT_CSD_PACKED_FAILURE BIT(3) BIT 398 include/linux/mmc/mmc.h #define EXT_CSD_PACKED_GENERIC_ERROR BIT(0) BIT 399 include/linux/mmc/mmc.h #define EXT_CSD_PACKED_INDEXED_ERROR BIT(1) BIT 415 include/linux/mmc/mmc.h #define EXT_CSD_CMDQ_MODE_ENABLED BIT(0) BIT 417 include/linux/mmc/mmc.h #define EXT_CSD_CMDQ_SUPPORTED BIT(0) BIT 107 include/linux/mroute_base.h MFC_STATIC = BIT(0), BIT 108 include/linux/mroute_base.h MFC_OFFLOAD = BIT(1), BIT 227 include/linux/mtd/cfi.h #define CFI_POLL_STATUS_REG BIT(0) BIT 228 include/linux/mtd/cfi.h #define CFI_POLL_DQ BIT(1) BIT 16 include/linux/mtd/onfi.h #define ONFI_VERSION_1_0 BIT(1) BIT 17 include/linux/mtd/onfi.h #define ONFI_VERSION_2_0 BIT(2) BIT 18 include/linux/mtd/onfi.h #define ONFI_VERSION_2_1 BIT(3) BIT 19 include/linux/mtd/onfi.h #define ONFI_VERSION_2_2 BIT(4) BIT 20 include/linux/mtd/onfi.h #define ONFI_VERSION_2_3 BIT(5) BIT 21 include/linux/mtd/onfi.h #define ONFI_VERSION_3_0 BIT(6) BIT 22 include/linux/mtd/onfi.h #define ONFI_VERSION_3_1 BIT(7) BIT 23 include/linux/mtd/onfi.h #define ONFI_VERSION_3_2 BIT(8) BIT 24 include/linux/mtd/onfi.h #define ONFI_VERSION_4_0 BIT(9) BIT 46 include/linux/mtd/onfi.h #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3) BIT 118 include/linux/mtd/rawnand.h #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) BIT 119 include/linux/mtd/rawnand.h #define NAND_ECC_MAXIMIZE BIT(1) BIT 125 include/linux/mtd/rawnand.h #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2) BIT 107 include/linux/mtd/spi-nor.h #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ BIT 108 include/linux/mtd/spi-nor.h #define XSR_RDY BIT(7) /* Ready */ BIT 124 include/linux/mtd/spi-nor.h #define SR_WIP BIT(0) /* Write in progress */ BIT 125 include/linux/mtd/spi-nor.h #define SR_WEL BIT(1) /* Write enable latch */ BIT 127 include/linux/mtd/spi-nor.h #define SR_BP0 BIT(2) /* Block protect 0 */ BIT 128 include/linux/mtd/spi-nor.h #define SR_BP1 BIT(3) /* Block protect 1 */ BIT 129 include/linux/mtd/spi-nor.h #define SR_BP2 BIT(4) /* Block protect 2 */ BIT 130 include/linux/mtd/spi-nor.h #define SR_TB BIT(5) /* Top/Bottom protect */ BIT 131 include/linux/mtd/spi-nor.h #define SR_SRWD BIT(7) /* SR write protect */ BIT 133 include/linux/mtd/spi-nor.h #define SR_E_ERR BIT(5) BIT 134 include/linux/mtd/spi-nor.h #define SR_P_ERR BIT(6) BIT 136 include/linux/mtd/spi-nor.h #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ BIT 139 include/linux/mtd/spi-nor.h #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ BIT 142 include/linux/mtd/spi-nor.h #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ BIT 143 include/linux/mtd/spi-nor.h #define FSR_E_ERR BIT(5) /* Erase operation status */ BIT 144 include/linux/mtd/spi-nor.h #define FSR_P_ERR BIT(4) /* Program operation status */ BIT 145 include/linux/mtd/spi-nor.h #define FSR_PT_ERR BIT(1) /* Protection error bit */ BIT 148 include/linux/mtd/spi-nor.h #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ BIT 151 include/linux/mtd/spi-nor.h #define SR2_QUAD_EN_BIT7 BIT(7) BIT 172 include/linux/mtd/spi-nor.h #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ BIT 237 include/linux/mtd/spi-nor.h SNOR_F_USE_FSR = BIT(0), BIT 238 include/linux/mtd/spi-nor.h SNOR_F_HAS_SR_TB = BIT(1), BIT 239 include/linux/mtd/spi-nor.h SNOR_F_NO_OP_CHIP_ERASE = BIT(2), BIT 240 include/linux/mtd/spi-nor.h SNOR_F_READY_XSR_RDY = BIT(3), BIT 241 include/linux/mtd/spi-nor.h SNOR_F_USE_CLSR = BIT(4), BIT 242 include/linux/mtd/spi-nor.h SNOR_F_BROKEN_RESET = BIT(5), BIT 243 include/linux/mtd/spi-nor.h SNOR_F_4B_OPCODES = BIT(6), BIT 244 include/linux/mtd/spi-nor.h SNOR_F_HAS_4BAIT = BIT(7), BIT 245 include/linux/mtd/spi-nor.h SNOR_F_HAS_LOCK = BIT(8), BIT 306 include/linux/mtd/spi-nor.h #define SNOR_LAST_REGION BIT(4) BIT 307 include/linux/mtd/spi-nor.h #define SNOR_OVERLAID_REGION BIT(5) BIT 353 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ BIT(0) BIT 354 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_FAST BIT(1) BIT 355 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) BIT 358 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_1_1_2 BIT(3) BIT 359 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_1_2_2 BIT(4) BIT 360 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_2_2_2 BIT(5) BIT 361 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) BIT 364 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_1_1_4 BIT(7) BIT 365 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_1_4_4 BIT(8) BIT 366 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_4_4_4 BIT(9) BIT 367 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) BIT 370 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_1_1_8 BIT(11) BIT 371 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_1_8_8 BIT(12) BIT 372 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_8_8_8 BIT(13) BIT 373 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) BIT 385 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_PP BIT(16) BIT 388 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_PP_1_1_4 BIT(17) BIT 389 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_PP_1_4_4 BIT(18) BIT 390 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_PP_4_4_4 BIT(19) BIT 393 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_PP_1_1_8 BIT(20) BIT 394 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_PP_1_8_8 BIT(21) BIT 395 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_PP_8_8_8 BIT(22) BIT 155 include/linux/mtd/spinand.h #define CFG_OTP_ENABLE BIT(6) BIT 156 include/linux/mtd/spinand.h #define CFG_ECC_ENABLE BIT(4) BIT 157 include/linux/mtd/spinand.h #define CFG_QUAD_ENABLE BIT(0) BIT 161 include/linux/mtd/spinand.h #define STATUS_BUSY BIT(0) BIT 162 include/linux/mtd/spinand.h #define STATUS_ERASE_FAILED BIT(2) BIT 163 include/linux/mtd/spinand.h #define STATUS_PROG_FAILED BIT(3) BIT 272 include/linux/mtd/spinand.h #define SPINAND_HAS_QE_BIT BIT(0) BIT 356 include/linux/netdevice.h NAPIF_STATE_SCHED = BIT(NAPI_STATE_SCHED), BIT 357 include/linux/netdevice.h NAPIF_STATE_MISSED = BIT(NAPI_STATE_MISSED), BIT 358 include/linux/netdevice.h NAPIF_STATE_DISABLE = BIT(NAPI_STATE_DISABLE), BIT 359 include/linux/netdevice.h NAPIF_STATE_NPSVC = BIT(NAPI_STATE_NPSVC), BIT 360 include/linux/netdevice.h NAPIF_STATE_HASHED = BIT(NAPI_STATE_HASHED), BIT 361 include/linux/netdevice.h NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL), BIT 362 include/linux/netdevice.h NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL), BIT 214 include/linux/nfs_fs.h #define NFS_INO_INVALID_DATA BIT(1) /* cached data is invalid */ BIT 215 include/linux/nfs_fs.h #define NFS_INO_INVALID_ATIME BIT(2) /* cached atime is invalid */ BIT 216 include/linux/nfs_fs.h #define NFS_INO_INVALID_ACCESS BIT(3) /* cached access cred invalid */ BIT 217 include/linux/nfs_fs.h #define NFS_INO_INVALID_ACL BIT(4) /* cached acls are invalid */ BIT 218 include/linux/nfs_fs.h #define NFS_INO_REVAL_PAGECACHE BIT(5) /* must revalidate pagecache */ BIT 219 include/linux/nfs_fs.h #define NFS_INO_REVAL_FORCED BIT(6) /* force revalidation ignoring a delegation */ BIT 220 include/linux/nfs_fs.h #define NFS_INO_INVALID_LABEL BIT(7) /* cached label is invalid */ BIT 221 include/linux/nfs_fs.h #define NFS_INO_INVALID_CHANGE BIT(8) /* cached change is invalid */ BIT 222 include/linux/nfs_fs.h #define NFS_INO_INVALID_CTIME BIT(9) /* cached ctime is invalid */ BIT 223 include/linux/nfs_fs.h #define NFS_INO_INVALID_MTIME BIT(10) /* cached mtime is invalid */ BIT 224 include/linux/nfs_fs.h #define NFS_INO_INVALID_SIZE BIT(11) /* cached size is invalid */ BIT 225 include/linux/nfs_fs.h #define NFS_INO_INVALID_OTHER BIT(12) /* other attrs are invalid */ BIT 227 include/linux/nfs_fs.h BIT(13) /* Deferred cache invalidation */ BIT 22 include/linux/olpc-ec.h #define EC_SCI_SRC_GAME BIT(0) BIT 23 include/linux/olpc-ec.h #define EC_SCI_SRC_BATTERY BIT(1) BIT 24 include/linux/olpc-ec.h #define EC_SCI_SRC_BATSOC BIT(2) BIT 25 include/linux/olpc-ec.h #define EC_SCI_SRC_BATERR BIT(3) BIT 26 include/linux/olpc-ec.h #define EC_SCI_SRC_EBOOK BIT(4) /* XO-1 only */ BIT 27 include/linux/olpc-ec.h #define EC_SCI_SRC_WLAN BIT(5) /* XO-1 only */ BIT 28 include/linux/olpc-ec.h #define EC_SCI_SRC_ACPWR BIT(6) BIT 29 include/linux/olpc-ec.h #define EC_SCI_SRC_BATCRIT BIT(7) BIT 30 include/linux/olpc-ec.h #define EC_SCI_SRC_GPWAKE BIT(8) /* XO-1.5 only */ BIT 107 include/linux/omap-dma.h #define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0) BIT 108 include/linux/omap-dma.h #define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1) BIT 109 include/linux/omap-dma.h #define DMA_ERRATA_i378 BIT(0x2) BIT 110 include/linux/omap-dma.h #define DMA_ERRATA_i541 BIT(0x3) BIT 111 include/linux/omap-dma.h #define DMA_ERRATA_i88 BIT(0x4) BIT 112 include/linux/omap-dma.h #define DMA_ERRATA_3_3 BIT(0x5) BIT 113 include/linux/omap-dma.h #define DMA_ROMCODE_BUG BIT(0x6) BIT 116 include/linux/omap-dma.h #define DMA_LINKED_LCH BIT(0x0) BIT 117 include/linux/omap-dma.h #define GLOBAL_PRIORITY BIT(0x1) BIT 118 include/linux/omap-dma.h #define RESERVE_CHANNEL BIT(0x2) BIT 119 include/linux/omap-dma.h #define IS_CSSA_32 BIT(0x3) BIT 120 include/linux/omap-dma.h #define IS_CDSA_32 BIT(0x4) BIT 121 include/linux/omap-dma.h #define IS_RW_PRIORITY BIT(0x5) BIT 122 include/linux/omap-dma.h #define ENABLE_1510_MODE BIT(0x6) BIT 123 include/linux/omap-dma.h #define SRC_PORT BIT(0x7) BIT 124 include/linux/omap-dma.h #define DST_PORT BIT(0x8) BIT 125 include/linux/omap-dma.h #define SRC_INDEX BIT(0x9) BIT 126 include/linux/omap-dma.h #define DST_INDEX BIT(0xa) BIT 127 include/linux/omap-dma.h #define IS_BURST_ONLY4 BIT(0xb) BIT 128 include/linux/omap-dma.h #define CLEAR_CSR_ON_READ BIT(0xc) BIT 129 include/linux/omap-dma.h #define IS_WORD_16 BIT(0xd) BIT 130 include/linux/omap-dma.h #define ENABLE_16XX_MODE BIT(0xe) BIT 131 include/linux/omap-dma.h #define HS_CHANNELS_RESERVED BIT(0xf) BIT 132 include/linux/omap-dma.h #define DMA_ENGINE_HANDLE_IRQ BIT(0x10) BIT 11 include/linux/packing.h #define QUIRK_MSB_ON_THE_RIGHT BIT(0) BIT 12 include/linux/packing.h #define QUIRK_LITTLE_ENDIAN BIT(1) BIT 13 include/linux/packing.h #define QUIRK_LSW32_IS_FIRST BIT(2) BIT 542 include/linux/perf_event.h #define PERF_EV_CAP_SOFTWARE BIT(0) BIT 543 include/linux/perf_event.h #define PERF_EV_CAP_READ_ACTIVE_PKG BIT(1) BIT 41 include/linux/phy/omap_control_phy.h #define OMAP_CTRL_DEV_PHY_PD BIT(0) BIT 43 include/linux/phy/omap_control_phy.h #define OMAP_CTRL_DEV_AVALID BIT(0) BIT 44 include/linux/phy/omap_control_phy.h #define OMAP_CTRL_DEV_BVALID BIT(1) BIT 45 include/linux/phy/omap_control_phy.h #define OMAP_CTRL_DEV_VBUSVALID BIT(2) BIT 46 include/linux/phy/omap_control_phy.h #define OMAP_CTRL_DEV_SESSEND BIT(3) BIT 47 include/linux/phy/omap_control_phy.h #define OMAP_CTRL_DEV_IDDIG BIT(4) BIT 61 include/linux/phy/omap_control_phy.h #define OMAP_CTRL_USB2_PHY_PD BIT(28) BIT 63 include/linux/phy/omap_control_phy.h #define AM437X_CTRL_USB2_PHY_PD BIT(0) BIT 64 include/linux/phy/omap_control_phy.h #define AM437X_CTRL_USB2_OTG_PD BIT(1) BIT 65 include/linux/phy/omap_control_phy.h #define AM437X_CTRL_USB2_OTGVDET_EN BIT(19) BIT 66 include/linux/phy/omap_control_phy.h #define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20) BIT 60 include/linux/phy/omap_usb.h #define OMAP_DEV_PHY_PD BIT(0) BIT 61 include/linux/phy/omap_usb.h #define OMAP_USB2_PHY_PD BIT(28) BIT 63 include/linux/phy/omap_usb.h #define AM437X_USB2_PHY_PD BIT(0) BIT 64 include/linux/phy/omap_usb.h #define AM437X_USB2_OTG_PD BIT(1) BIT 65 include/linux/phy/omap_usb.h #define AM437X_USB2_OTGVDET_EN BIT(19) BIT 66 include/linux/phy/omap_usb.h #define AM437X_USB2_OTGSESSEND_EN BIT(20) BIT 15 include/linux/phylink.h MLO_PAUSE_ASYM = BIT(0), BIT 16 include/linux/phylink.h MLO_PAUSE_SYM = BIT(1), BIT 17 include/linux/phylink.h MLO_PAUSE_RX = BIT(2), BIT 18 include/linux/phylink.h MLO_PAUSE_TX = BIT(3), BIT 20 include/linux/phylink.h MLO_PAUSE_AN = BIT(4), BIT 31 include/linux/platform_data/cros_ec_commands.h #define EC_VER_MASK(version) BIT(version) BIT 60 include/linux/platform_data/cros_ec_commands.h #define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ BIT 61 include/linux/platform_data/cros_ec_commands.h #define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ BIT 62 include/linux/platform_data/cros_ec_commands.h #define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ BIT 63 include/linux/platform_data/cros_ec_commands.h #define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ BIT 64 include/linux/platform_data/cros_ec_commands.h #define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ BIT 65 include/linux/platform_data/cros_ec_commands.h #define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ BIT 66 include/linux/platform_data/cros_ec_commands.h #define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ BIT 124 include/linux/platform_data/cros_ec_commands.h #define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) BIT 125 include/linux/platform_data/cros_ec_commands.h #define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) BIT 300 include/linux/platform_data/cros_ec_commands.h #define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK BIT(0) BIT 301 include/linux/platform_data/cros_ec_commands.h #define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK BIT(1) BIT 1097 include/linux/platform_data/cros_ec_commands.h EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ BIT 1129 include/linux/platform_data/cros_ec_commands.h #define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0) BIT 1288 include/linux/platform_data/cros_ec_commands.h #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) BIT 1289 include/linux/platform_data/cros_ec_commands.h #define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32) BIT 1336 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_INFO_ERASE_TO_0 BIT(0) BIT 1345 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_INFO_SELECT_REQUIRED BIT(1) BIT 1524 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) BIT 1529 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_RO_NOW BIT(1) BIT 1531 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_ALL_NOW BIT(2) BIT 1533 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) BIT 1535 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) BIT 1541 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5) BIT 1543 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) BIT 1545 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) BIT 1547 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_RW_NOW BIT(8) BIT 1549 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) BIT 1551 include/linux/platform_data/cros_ec_commands.h #define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) BIT 2106 include/linux/platform_data/cros_ec_commands.h #define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */ BIT 2107 include/linux/platform_data/cros_ec_commands.h #define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ BIT 2447 include/linux/platform_data/cros_ec_commands.h #define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0) BIT 2450 include/linux/platform_data/cros_ec_commands.h #define MOTIONSENSE_SENSOR_FLAG_PRESENT BIT(0) BIT 2456 include/linux/platform_data/cros_ec_commands.h #define MOTIONSENSE_SENSOR_FLAG_FLUSH BIT(0) BIT 2457 include/linux/platform_data/cros_ec_commands.h #define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP BIT(1) BIT 2458 include/linux/platform_data/cros_ec_commands.h #define MOTIONSENSE_SENSOR_FLAG_WAKEUP BIT(2) BIT 2459 include/linux/platform_data/cros_ec_commands.h #define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3) BIT 2460 include/linux/platform_data/cros_ec_commands.h #define MOTIONSENSE_SENSOR_FLAG_ODR BIT(4) BIT 2473 include/linux/platform_data/cros_ec_commands.h #define MOTION_SENSE_SET_OFFSET BIT(0) BIT 2476 include/linux/platform_data/cros_ec_commands.h #define MOTION_SENSE_DEFAULT_SCALE BIT(15) BIT 2794 include/linux/platform_data/cros_ec_commands.h EC_POWER_BUTTON_ENABLE_PULSE = BIT(0), BIT 3220 include/linux/platform_data/cros_ec_commands.h EC_MKBP_VALID_SCAN_PERIOD = BIT(0), BIT 3221 include/linux/platform_data/cros_ec_commands.h EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), BIT 3222 include/linux/platform_data/cros_ec_commands.h EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), BIT 3223 include/linux/platform_data/cros_ec_commands.h EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), BIT 3224 include/linux/platform_data/cros_ec_commands.h EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), BIT 3225 include/linux/platform_data/cros_ec_commands.h EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), BIT 3226 include/linux/platform_data/cros_ec_commands.h EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), BIT 3280 include/linux/platform_data/cros_ec_commands.h EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), BIT 3334 include/linux/platform_data/cros_ec_commands.h #define EC_MKBP_HAS_MORE_EVENTS BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) BIT 3337 include/linux/platform_data/cros_ec_commands.h #define EC_MKBP_EVENT_TYPE_MASK (BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1) BIT 3475 include/linux/platform_data/cros_ec_commands.h #define EC_MKBP_FP_ENROLL BIT(27) BIT 3476 include/linux/platform_data/cros_ec_commands.h #define EC_MKBP_FP_MATCH BIT(28) BIT 3477 include/linux/platform_data/cros_ec_commands.h #define EC_MKBP_FP_FINGER_DOWN BIT(29) BIT 3478 include/linux/platform_data/cros_ec_commands.h #define EC_MKBP_FP_FINGER_UP BIT(30) BIT 3479 include/linux/platform_data/cros_ec_commands.h #define EC_MKBP_FP_IMAGE_READY BIT(31) BIT 3827 include/linux/platform_data/cros_ec_commands.h #define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) BIT 3898 include/linux/platform_data/cros_ec_commands.h #define EC_I2C_FLAG_READ BIT(15) BIT 3903 include/linux/platform_data/cros_ec_commands.h #define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ BIT 3904 include/linux/platform_data/cros_ec_commands.h #define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ BIT 3934 include/linux/platform_data/cros_ec_commands.h #define EC_HANG_START_ON_POWER_PRESS BIT(0) BIT 3937 include/linux/platform_data/cros_ec_commands.h #define EC_HANG_START_ON_LID_CLOSE BIT(1) BIT 3940 include/linux/platform_data/cros_ec_commands.h #define EC_HANG_START_ON_LID_OPEN BIT(2) BIT 3943 include/linux/platform_data/cros_ec_commands.h #define EC_HANG_START_ON_RESUME BIT(3) BIT 3948 include/linux/platform_data/cros_ec_commands.h #define EC_HANG_STOP_ON_POWER_RELEASE BIT(8) BIT 3951 include/linux/platform_data/cros_ec_commands.h #define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) BIT 3954 include/linux/platform_data/cros_ec_commands.h #define EC_HANG_STOP_ON_SUSPEND BIT(10) BIT 3962 include/linux/platform_data/cros_ec_commands.h #define EC_HANG_START_NOW BIT(30) BIT 3969 include/linux/platform_data/cros_ec_commands.h #define EC_HANG_STOP_NOW BIT(31) BIT 4228 include/linux/platform_data/cros_ec_commands.h #define EC_DEVICE_EVENT_MASK(event_code) BIT(event_code % 32) BIT 4464 include/linux/platform_data/cros_ec_commands.h EC_MKBP_CEC_SEND_OK = BIT(0), BIT 4466 include/linux/platform_data/cros_ec_commands.h EC_MKBP_CEC_SEND_FAILED = BIT(1), BIT 4580 include/linux/platform_data/cros_ec_commands.h #define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ BIT 4581 include/linux/platform_data/cros_ec_commands.h #define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ BIT 4582 include/linux/platform_data/cros_ec_commands.h #define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ BIT 4656 include/linux/platform_data/cros_ec_commands.h #define EC_STATUS_HIBERNATING BIT(0) BIT 4665 include/linux/platform_data/cros_ec_commands.h #define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ BIT 4666 include/linux/platform_data/cros_ec_commands.h #define PD_STATUS_IN_RW BIT(1) /* Running RW image */ BIT 4667 include/linux/platform_data/cros_ec_commands.h #define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */ BIT 4668 include/linux/platform_data/cros_ec_commands.h #define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ BIT 4669 include/linux/platform_data/cros_ec_commands.h #define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ BIT 4670 include/linux/platform_data/cros_ec_commands.h #define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ BIT 4671 include/linux/platform_data/cros_ec_commands.h #define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ BIT 4685 include/linux/platform_data/cros_ec_commands.h #define PD_EVENT_UPDATE_DEVICE BIT(0) BIT 4686 include/linux/platform_data/cros_ec_commands.h #define PD_EVENT_POWER_CHANGE BIT(1) BIT 4687 include/linux/platform_data/cros_ec_commands.h #define PD_EVENT_IDENTITY_RECEIVED BIT(2) BIT 4688 include/linux/platform_data/cros_ec_commands.h #define PD_EVENT_DATA_SWAP BIT(3) BIT 4731 include/linux/platform_data/cros_ec_commands.h #define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ BIT 4732 include/linux/platform_data/cros_ec_commands.h #define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ BIT 4733 include/linux/platform_data/cros_ec_commands.h #define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */ BIT 4735 include/linux/platform_data/cros_ec_commands.h #define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ BIT 4736 include/linux/platform_data/cros_ec_commands.h #define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ BIT 4737 include/linux/platform_data/cros_ec_commands.h #define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ BIT 4738 include/linux/platform_data/cros_ec_commands.h #define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ BIT 4739 include/linux/platform_data/cros_ec_commands.h #define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ BIT 4740 include/linux/platform_data/cros_ec_commands.h #define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ BIT 4741 include/linux/platform_data/cros_ec_commands.h #define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6) /* Partner externally powerd */ BIT 4954 include/linux/platform_data/cros_ec_commands.h #define CHARGE_FLAGS_DUAL_ROLE BIT(15) BIT 4956 include/linux/platform_data/cros_ec_commands.h #define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) BIT 4958 include/linux/platform_data/cros_ec_commands.h #define CHARGE_FLAGS_OVERRIDE BIT(13) BIT 5055 include/linux/platform_data/cros_ec_commands.h #define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ BIT 5056 include/linux/platform_data/cros_ec_commands.h #define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ BIT 5057 include/linux/platform_data/cros_ec_commands.h #define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ BIT 5058 include/linux/platform_data/cros_ec_commands.h #define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ BIT 5059 include/linux/platform_data/cros_ec_commands.h #define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ BIT 5150 include/linux/platform_data/cros_ec_commands.h #define CBI_GET_RELOAD BIT(0) BIT 5165 include/linux/platform_data/cros_ec_commands.h #define CBI_SET_NO_SYNC BIT(0) BIT 5166 include/linux/platform_data/cros_ec_commands.h #define CBI_SET_INIT BIT(1) BIT 5306 include/linux/platform_data/cros_ec_commands.h #define FP_MODE_DEEPSLEEP BIT(0) BIT 5308 include/linux/platform_data/cros_ec_commands.h #define FP_MODE_FINGER_DOWN BIT(1) BIT 5310 include/linux/platform_data/cros_ec_commands.h #define FP_MODE_FINGER_UP BIT(2) BIT 5312 include/linux/platform_data/cros_ec_commands.h #define FP_MODE_CAPTURE BIT(3) BIT 5314 include/linux/platform_data/cros_ec_commands.h #define FP_MODE_ENROLL_SESSION BIT(4) BIT 5316 include/linux/platform_data/cros_ec_commands.h #define FP_MODE_ENROLL_IMAGE BIT(5) BIT 5318 include/linux/platform_data/cros_ec_commands.h #define FP_MODE_MATCH BIT(6) BIT 5320 include/linux/platform_data/cros_ec_commands.h #define FP_MODE_RESET_SENSOR BIT(7) BIT 5322 include/linux/platform_data/cros_ec_commands.h #define FP_MODE_DONT_CHANGE BIT(31) BIT 5376 include/linux/platform_data/cros_ec_commands.h #define FP_ERROR_NO_IRQ BIT(12) BIT 5378 include/linux/platform_data/cros_ec_commands.h #define FP_ERROR_SPI_COMM BIT(13) BIT 5380 include/linux/platform_data/cros_ec_commands.h #define FP_ERROR_BAD_HWID BIT(14) BIT 5382 include/linux/platform_data/cros_ec_commands.h #define FP_ERROR_INIT_FAIL BIT(15) BIT 5489 include/linux/platform_data/cros_ec_commands.h #define FPSTATS_CAPTURE_INV BIT(0) BIT 5490 include/linux/platform_data/cros_ec_commands.h #define FPSTATS_MATCHING_INV BIT(1) BIT 5519 include/linux/platform_data/cros_ec_commands.h #define FP_ENC_STATUS_SEED_SET BIT(0) BIT 59 include/linux/platform_data/dma-dw.h #define CHAN_PROTCTL_PRIVILEGED BIT(0) BIT 60 include/linux/platform_data/dma-dw.h #define CHAN_PROTCTL_BUFFERABLE BIT(1) BIT 61 include/linux/platform_data/dma-dw.h #define CHAN_PROTCTL_CACHEABLE BIT(2) BIT 9 include/linux/platform_data/dma-s3c24xx.h #define S3C24XX_DMA_CHANREQ(src, chan) ((BIT(3) | src) << chan * 4) BIT 24 include/linux/platform_data/hsmmc-omap.h #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) BIT 25 include/linux/platform_data/hsmmc-omap.h #define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1) BIT 26 include/linux/platform_data/hsmmc-omap.h #define OMAP_HSMMC_SWAKEUP_MISSING BIT(2) BIT 21 include/linux/platform_data/i2c-omap.h #define OMAP_I2C_FLAG_NO_FIFO BIT(0) BIT 22 include/linux/platform_data/i2c-omap.h #define OMAP_I2C_FLAG_SIMPLE_CLOCK BIT(1) BIT 23 include/linux/platform_data/i2c-omap.h #define OMAP_I2C_FLAG_16BIT_DATA_REG BIT(2) BIT 24 include/linux/platform_data/i2c-omap.h #define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5) BIT 25 include/linux/platform_data/i2c-omap.h #define OMAP_I2C_FLAG_FORCE_19200_INT_CLK BIT(6) BIT 28 include/linux/platform_data/i2c-omap.h #define OMAP_I2C_FLAG_BUS_SHIFT_1 BIT(7) BIT 29 include/linux/platform_data/i2c-omap.h #define OMAP_I2C_FLAG_BUS_SHIFT_2 BIT(8) BIT 40 include/linux/platform_data/lp855x.h #define LP8555_PWM_STANDBY BIT(7) BIT 41 include/linux/platform_data/lp855x.h #define LP8555_PWM_FILTER BIT(6) BIT 42 include/linux/platform_data/lp855x.h #define LP8555_RELOAD_EPROM BIT(3) /* use it if EPROMs should be reset BIT 44 include/linux/platform_data/lp855x.h #define LP8555_OFF_OPENLEDS BIT(2) BIT 56 include/linux/platform_data/lp855x.h #define LP8556_FAST_CONFIG BIT(7) /* use it if EPROMs should be maintained BIT 60 include/linux/platform_data/lp855x.h #define LP8557_PWM_STANDBY BIT(7) BIT 61 include/linux/platform_data/lp855x.h #define LP8557_PWM_FILTER BIT(6) BIT 62 include/linux/platform_data/lp855x.h #define LP8557_RELOAD_EPROM BIT(3) /* use it if EPROMs should be reset BIT 64 include/linux/platform_data/lp855x.h #define LP8557_OFF_OPENLEDS BIT(2) BIT 28 include/linux/platform_data/media/omap1_camera.h #define OMAP1_CAMERA_LCLK_RISING BIT(0) BIT 29 include/linux/platform_data/media/omap1_camera.h #define OMAP1_CAMERA_RST_LOW BIT(1) BIT 30 include/linux/platform_data/media/omap1_camera.h #define OMAP1_CAMERA_RST_HIGH BIT(2) BIT 38 include/linux/platform_data/mlxreg.h #define MLXREG_CORE_WD_FEATURE_NOWAYOUT BIT(0) BIT 39 include/linux/platform_data/mlxreg.h #define MLXREG_CORE_WD_FEATURE_START_AT_BOOT BIT(1) BIT 20 include/linux/platform_data/mtd-davinci-aemif.h #define ACR_EW_MASK BIT(30) BIT 21 include/linux/platform_data/mtd-davinci-aemif.h #define ACR_SS_MASK BIT(31) BIT 32 include/linux/platform_data/pm33xx.h #define WFI_FLAG_FLUSH_CACHE BIT(0) BIT 33 include/linux/platform_data/pm33xx.h #define WFI_FLAG_SELF_REFRESH BIT(1) BIT 34 include/linux/platform_data/pm33xx.h #define WFI_FLAG_SAVE_EMIF BIT(2) BIT 35 include/linux/platform_data/pm33xx.h #define WFI_FLAG_WAKE_M3 BIT(3) BIT 36 include/linux/platform_data/pm33xx.h #define WFI_FLAG_RTC_ONLY BIT(4) BIT 52 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_CLKDM_NOAUTO BIT(21) BIT 53 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_FORCE_MSTANDBY BIT(20) BIT 54 include/linux/platform_data/ti-sysc.h #define SYSC_MODULE_QUIRK_AESS BIT(19) BIT 55 include/linux/platform_data/ti-sysc.h #define SYSC_MODULE_QUIRK_SGX BIT(18) BIT 56 include/linux/platform_data/ti-sysc.h #define SYSC_MODULE_QUIRK_HDQ1W BIT(17) BIT 57 include/linux/platform_data/ti-sysc.h #define SYSC_MODULE_QUIRK_I2C BIT(16) BIT 58 include/linux/platform_data/ti-sysc.h #define SYSC_MODULE_QUIRK_WDT BIT(15) BIT 59 include/linux/platform_data/ti-sysc.h #define SYSS_QUIRK_RESETDONE_INVERTED BIT(14) BIT 60 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13) BIT 61 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12) BIT 62 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_SWSUP_SIDLE BIT(11) BIT 63 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10) BIT 64 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_LEGACY_IDLE BIT(9) BIT 65 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_RESET_STATUS BIT(8) BIT 66 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_NO_IDLE BIT(7) BIT 67 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) BIT 68 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) BIT 69 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4) BIT 70 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3) BIT 71 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_16BIT BIT(2) BIT 72 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_UNCACHED BIT(1) BIT 73 include/linux/platform_data/ti-sysc.h #define SYSC_QUIRK_USE_CLOCKACT BIT(0) BIT 15 include/linux/platform_data/wilco-ec.h #define WILCO_EC_FLAG_NO_RESPONSE BIT(0) /* EC does not respond */ BIT 26 include/linux/platform_data/x86/pmc_atom.h #define BIT_FD_GMM BIT(3) BIT 27 include/linux/platform_data/x86/pmc_atom.h #define BIT_FD_ISH BIT(4) BIT 32 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPC_CLOCK_RUN BIT(4) BIT 33 include/linux/platform_data/x86/pmc_atom.h #define BIT_SHARED_IRQ_GPSC BIT(5) BIT 34 include/linux/platform_data/x86/pmc_atom.h #define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18) BIT 35 include/linux/platform_data/x86/pmc_atom.h #define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19) BIT 36 include/linux/platform_data/x86/pmc_atom.h #define BIT_SHARED_IRQ_GPSS BIT(20) BIT 56 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_GBE BIT(0) BIT 57 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_SATA BIT(1) BIT 58 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_HDA BIT(2) BIT 59 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_SEC BIT(3) BIT 60 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_PCIE BIT(4) BIT 61 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_LPSS BIT(5) BIT 62 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_LPE BIT(6) BIT 63 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_DFX BIT(7) BIT 64 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_USH_CTRL BIT(8) BIT 65 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_USH_SUS BIT(9) BIT 66 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_USH_VCCS BIT(10) BIT 67 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_USH_VCCA BIT(11) BIT 68 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_OTG_CTRL BIT(12) BIT 69 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_OTG_VCCS BIT(13) BIT 70 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_OTG_VCCA_CLK BIT(14) BIT 71 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_OTG_VCCA BIT(15) BIT 72 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_USB BIT(16) BIT 73 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_USB_SUS BIT(17) BIT 76 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_UFS BIT(7) BIT 77 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_UXD BIT(11) BIT 78 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_UXD_FD BIT(12) BIT 79 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_UX_ENG BIT(15) BIT 80 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_USB_SUS BIT(16) BIT 81 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_GMM BIT(17) BIT 82 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_ISH BIT(18) BIT 83 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_DFX_MASTER BIT(26) BIT 84 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27) BIT 85 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_DFX_CLUSTER2 BIT(28) BIT 86 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_DFX_CLUSTER3 BIT(29) BIT 87 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_DFX_CLUSTER4 BIT(30) BIT 88 include/linux/platform_data/x86/pmc_atom.h #define PMC_PSS_BIT_CHT_DFX_CLUSTER5 BIT(31) BIT 93 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS1_F0_DMA BIT(0) BIT 94 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS1_F1_PWM1 BIT(1) BIT 95 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS1_F2_PWM2 BIT(2) BIT 96 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS1_F3_HSUART1 BIT(3) BIT 97 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS1_F4_HSUART2 BIT(4) BIT 98 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS1_F5_SPI BIT(5) BIT 99 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS1_F6_XXX BIT(6) BIT 100 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS1_F7_XXX BIT(7) BIT 101 include/linux/platform_data/x86/pmc_atom.h #define BIT_SCC_EMMC BIT(8) BIT 102 include/linux/platform_data/x86/pmc_atom.h #define BIT_SCC_SDIO BIT(9) BIT 103 include/linux/platform_data/x86/pmc_atom.h #define BIT_SCC_SDCARD BIT(10) BIT 104 include/linux/platform_data/x86/pmc_atom.h #define BIT_SCC_MIPI BIT(11) BIT 105 include/linux/platform_data/x86/pmc_atom.h #define BIT_HDA BIT(12) BIT 106 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPE BIT(13) BIT 107 include/linux/platform_data/x86/pmc_atom.h #define BIT_OTG BIT(14) BIT 108 include/linux/platform_data/x86/pmc_atom.h #define BIT_USH BIT(15) BIT 109 include/linux/platform_data/x86/pmc_atom.h #define BIT_GBE BIT(16) BIT 110 include/linux/platform_data/x86/pmc_atom.h #define BIT_SATA BIT(17) BIT 111 include/linux/platform_data/x86/pmc_atom.h #define BIT_USB_EHCI BIT(18) BIT 112 include/linux/platform_data/x86/pmc_atom.h #define BIT_SEC BIT(19) BIT 113 include/linux/platform_data/x86/pmc_atom.h #define BIT_PCIE_PORT0 BIT(20) BIT 114 include/linux/platform_data/x86/pmc_atom.h #define BIT_PCIE_PORT1 BIT(21) BIT 115 include/linux/platform_data/x86/pmc_atom.h #define BIT_PCIE_PORT2 BIT(22) BIT 116 include/linux/platform_data/x86/pmc_atom.h #define BIT_PCIE_PORT3 BIT(23) BIT 117 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS2_F0_DMA BIT(24) BIT 118 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS2_F1_I2C1 BIT(25) BIT 119 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS2_F2_I2C2 BIT(26) BIT 120 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS2_F3_I2C3 BIT(27) BIT 121 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS2_F4_I2C4 BIT(28) BIT 122 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS2_F5_I2C5 BIT(29) BIT 123 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS2_F6_I2C6 BIT(30) BIT 124 include/linux/platform_data/x86/pmc_atom.h #define BIT_LPSS2_F7_I2C7 BIT(31) BIT 127 include/linux/platform_data/x86/pmc_atom.h #define BIT_SMB BIT(0) BIT 128 include/linux/platform_data/x86/pmc_atom.h #define BIT_OTG_SS_PHY BIT(1) BIT 129 include/linux/platform_data/x86/pmc_atom.h #define BIT_USH_SS_PHY BIT(2) BIT 130 include/linux/platform_data/x86/pmc_atom.h #define BIT_DFX BIT(3) BIT 133 include/linux/platform_data/x86/pmc_atom.h #define BIT_STS_GMM BIT(1) BIT 134 include/linux/platform_data/x86/pmc_atom.h #define BIT_STS_ISH BIT(2) BIT 568 include/linux/pm.h #define DPM_FLAG_NEVER_SKIP BIT(0) BIT 569 include/linux/pm.h #define DPM_FLAG_SMART_PREPARE BIT(1) BIT 570 include/linux/pm.h #define DPM_FLAG_SMART_SUSPEND BIT(2) BIT 571 include/linux/pm.h #define DPM_FLAG_LEAVE_SUSPENDED BIT(3) BIT 65 include/linux/power/smartreflex.h #define SRCONFIG_SRENABLE BIT(11) BIT 66 include/linux/power/smartreflex.h #define SRCONFIG_SENENABLE BIT(10) BIT 67 include/linux/power/smartreflex.h #define SRCONFIG_ERRGEN_EN BIT(9) BIT 68 include/linux/power/smartreflex.h #define SRCONFIG_MINMAXAVG_EN BIT(8) BIT 69 include/linux/power/smartreflex.h #define SRCONFIG_DELAYCTRL BIT(2) BIT 90 include/linux/power/smartreflex.h #define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31) BIT 91 include/linux/power/smartreflex.h #define ERRCONFIG_VPBOUNDINTST_V1 BIT(30) BIT 92 include/linux/power/smartreflex.h #define ERRCONFIG_MCUACCUMINTEN BIT(29) BIT 93 include/linux/power/smartreflex.h #define ERRCONFIG_MCUACCUMINTST BIT(28) BIT 94 include/linux/power/smartreflex.h #define ERRCONFIG_MCUVALIDINTEN BIT(27) BIT 95 include/linux/power/smartreflex.h #define ERRCONFIG_MCUVALIDINTST BIT(26) BIT 96 include/linux/power/smartreflex.h #define ERRCONFIG_MCUBOUNDINTEN BIT(25) BIT 97 include/linux/power/smartreflex.h #define ERRCONFIG_MCUBOUNDINTST BIT(24) BIT 98 include/linux/power/smartreflex.h #define ERRCONFIG_MCUDISACKINTEN BIT(23) BIT 99 include/linux/power/smartreflex.h #define ERRCONFIG_VPBOUNDINTST_V2 BIT(23) BIT 100 include/linux/power/smartreflex.h #define ERRCONFIG_MCUDISACKINTST BIT(22) BIT 101 include/linux/power/smartreflex.h #define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22) BIT 109 include/linux/power/smartreflex.h #define IRQSTATUS_MCUACCUMINT BIT(3) BIT 110 include/linux/power/smartreflex.h #define IRQSTATUS_MCVALIDINT BIT(2) BIT 111 include/linux/power/smartreflex.h #define IRQSTATUS_MCBOUNDSINT BIT(1) BIT 112 include/linux/power/smartreflex.h #define IRQSTATUS_MCUDISABLEACKINT BIT(0) BIT 115 include/linux/power/smartreflex.h #define IRQENABLE_MCUACCUMINT BIT(3) BIT 116 include/linux/power/smartreflex.h #define IRQENABLE_MCUVALIDINT BIT(2) BIT 117 include/linux/power/smartreflex.h #define IRQENABLE_MCUBOUNDSINT BIT(1) BIT 118 include/linux/power/smartreflex.h #define IRQENABLE_MCUDISABLEACKINT BIT(0) BIT 363 include/linux/property.h #define FWNODE_GRAPH_ENDPOINT_NEXT BIT(0) BIT 364 include/linux/property.h #define FWNODE_GRAPH_DEVICE_DISABLED BIT(1) BIT 194 include/linux/pstore.h #define PSTORE_FLAGS_DMESG BIT(0) BIT 195 include/linux/pstore.h #define PSTORE_FLAGS_CONSOLE BIT(1) BIT 196 include/linux/pstore.h #define PSTORE_FLAGS_FTRACE BIT(2) BIT 197 include/linux/pstore.h #define PSTORE_FLAGS_PMSG BIT(3) BIT 220 include/linux/pstore.h #define TS_CPU_MASK (BIT(TS_CPU_SHIFT) - 1) BIT 24 include/linux/pstore_ram.h #define PRZ_FLAG_NO_LOCK BIT(0) BIT 29 include/linux/pstore_ram.h #define PRZ_FLAG_ZAP_OLD BIT(1) BIT 126 include/linux/pstore_ram.h #define RAMOOPS_FLAG_FTRACE_PER_CPU BIT(0) BIT 82 include/linux/qcom-geni-se.h #define FORCE_DEFAULT BIT(0) BIT 85 include/linux/qcom-geni-se.h #define M_GENI_CMD_ACTIVE BIT(0) BIT 86 include/linux/qcom-geni-se.h #define S_GENI_CMD_ACTIVE BIT(12) BIT 89 include/linux/qcom-geni-se.h #define SER_CLK_EN BIT(0) BIT 101 include/linux/qcom-geni-se.h #define GENI_DMA_MODE_EN BIT(0) BIT 109 include/linux/qcom-geni-se.h #define M_GENI_CMD_CANCEL BIT(2) BIT 110 include/linux/qcom-geni-se.h #define M_GENI_CMD_ABORT BIT(1) BIT 111 include/linux/qcom-geni-se.h #define M_GENI_DISABLE BIT(0) BIT 119 include/linux/qcom-geni-se.h #define S_GENI_CMD_CANCEL BIT(2) BIT 120 include/linux/qcom-geni-se.h #define S_GENI_CMD_ABORT BIT(1) BIT 121 include/linux/qcom-geni-se.h #define S_GENI_DISABLE BIT(0) BIT 124 include/linux/qcom-geni-se.h #define M_CMD_DONE_EN BIT(0) BIT 125 include/linux/qcom-geni-se.h #define M_CMD_OVERRUN_EN BIT(1) BIT 126 include/linux/qcom-geni-se.h #define M_ILLEGAL_CMD_EN BIT(2) BIT 127 include/linux/qcom-geni-se.h #define M_CMD_FAILURE_EN BIT(3) BIT 128 include/linux/qcom-geni-se.h #define M_CMD_CANCEL_EN BIT(4) BIT 129 include/linux/qcom-geni-se.h #define M_CMD_ABORT_EN BIT(5) BIT 130 include/linux/qcom-geni-se.h #define M_TIMESTAMP_EN BIT(6) BIT 131 include/linux/qcom-geni-se.h #define M_RX_IRQ_EN BIT(7) BIT 132 include/linux/qcom-geni-se.h #define M_GP_SYNC_IRQ_0_EN BIT(8) BIT 133 include/linux/qcom-geni-se.h #define M_GP_IRQ_0_EN BIT(9) BIT 134 include/linux/qcom-geni-se.h #define M_GP_IRQ_1_EN BIT(10) BIT 135 include/linux/qcom-geni-se.h #define M_GP_IRQ_2_EN BIT(11) BIT 136 include/linux/qcom-geni-se.h #define M_GP_IRQ_3_EN BIT(12) BIT 137 include/linux/qcom-geni-se.h #define M_GP_IRQ_4_EN BIT(13) BIT 138 include/linux/qcom-geni-se.h #define M_GP_IRQ_5_EN BIT(14) BIT 139 include/linux/qcom-geni-se.h #define M_IO_DATA_DEASSERT_EN BIT(22) BIT 140 include/linux/qcom-geni-se.h #define M_IO_DATA_ASSERT_EN BIT(23) BIT 141 include/linux/qcom-geni-se.h #define M_RX_FIFO_RD_ERR_EN BIT(24) BIT 142 include/linux/qcom-geni-se.h #define M_RX_FIFO_WR_ERR_EN BIT(25) BIT 143 include/linux/qcom-geni-se.h #define M_RX_FIFO_WATERMARK_EN BIT(26) BIT 144 include/linux/qcom-geni-se.h #define M_RX_FIFO_LAST_EN BIT(27) BIT 145 include/linux/qcom-geni-se.h #define M_TX_FIFO_RD_ERR_EN BIT(28) BIT 146 include/linux/qcom-geni-se.h #define M_TX_FIFO_WR_ERR_EN BIT(29) BIT 147 include/linux/qcom-geni-se.h #define M_TX_FIFO_WATERMARK_EN BIT(30) BIT 148 include/linux/qcom-geni-se.h #define M_SEC_IRQ_EN BIT(31) BIT 156 include/linux/qcom-geni-se.h #define S_CMD_DONE_EN BIT(0) BIT 157 include/linux/qcom-geni-se.h #define S_CMD_OVERRUN_EN BIT(1) BIT 158 include/linux/qcom-geni-se.h #define S_ILLEGAL_CMD_EN BIT(2) BIT 159 include/linux/qcom-geni-se.h #define S_CMD_FAILURE_EN BIT(3) BIT 160 include/linux/qcom-geni-se.h #define S_CMD_CANCEL_EN BIT(4) BIT 161 include/linux/qcom-geni-se.h #define S_CMD_ABORT_EN BIT(5) BIT 162 include/linux/qcom-geni-se.h #define S_GP_SYNC_IRQ_0_EN BIT(8) BIT 163 include/linux/qcom-geni-se.h #define S_GP_IRQ_0_EN BIT(9) BIT 164 include/linux/qcom-geni-se.h #define S_GP_IRQ_1_EN BIT(10) BIT 165 include/linux/qcom-geni-se.h #define S_GP_IRQ_2_EN BIT(11) BIT 166 include/linux/qcom-geni-se.h #define S_GP_IRQ_3_EN BIT(12) BIT 167 include/linux/qcom-geni-se.h #define S_GP_IRQ_4_EN BIT(13) BIT 168 include/linux/qcom-geni-se.h #define S_GP_IRQ_5_EN BIT(14) BIT 169 include/linux/qcom-geni-se.h #define S_IO_DATA_DEASSERT_EN BIT(22) BIT 170 include/linux/qcom-geni-se.h #define S_IO_DATA_ASSERT_EN BIT(23) BIT 171 include/linux/qcom-geni-se.h #define S_RX_FIFO_RD_ERR_EN BIT(24) BIT 172 include/linux/qcom-geni-se.h #define S_RX_FIFO_WR_ERR_EN BIT(25) BIT 173 include/linux/qcom-geni-se.h #define S_RX_FIFO_WATERMARK_EN BIT(26) BIT 174 include/linux/qcom-geni-se.h #define S_RX_FIFO_LAST_EN BIT(27) BIT 185 include/linux/qcom-geni-se.h #define RX_LAST BIT(31) BIT 191 include/linux/qcom-geni-se.h #define IO2_DATA_IN BIT(1) BIT 192 include/linux/qcom-geni-se.h #define RX_DATA_IN BIT(0) BIT 195 include/linux/qcom-geni-se.h #define TX_DMA_DONE BIT(0) BIT 196 include/linux/qcom-geni-se.h #define TX_EOT BIT(1) BIT 197 include/linux/qcom-geni-se.h #define TX_SBE BIT(2) BIT 198 include/linux/qcom-geni-se.h #define TX_RESET_DONE BIT(3) BIT 201 include/linux/qcom-geni-se.h #define RX_DMA_DONE BIT(0) BIT 202 include/linux/qcom-geni-se.h #define RX_EOT BIT(1) BIT 203 include/linux/qcom-geni-se.h #define RX_SBE BIT(2) BIT 204 include/linux/qcom-geni-se.h #define RX_RESET_DONE BIT(3) BIT 205 include/linux/qcom-geni-se.h #define RX_FLUSH_DONE BIT(4) BIT 207 include/linux/qcom-geni-se.h #define RX_GENI_CANCEL_IRQ BIT(11) BIT 164 include/linux/qed/common_hsi.h #define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS) BIT 269 include/linux/qed/common_hsi.h #define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) BIT 270 include/linux/qed/common_hsi.h #define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) BIT 271 include/linux/qed/common_hsi.h #define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) BIT 272 include/linux/qed/common_hsi.h #define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) BIT 273 include/linux/qed/common_hsi.h #define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) BIT 274 include/linux/qed/common_hsi.h #define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) BIT 275 include/linux/qed/common_hsi.h #define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) BIT 276 include/linux/qed/common_hsi.h #define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) BIT 277 include/linux/qed/common_hsi.h #define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) BIT 278 include/linux/qed/common_hsi.h #define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) BIT 279 include/linux/qed/common_hsi.h #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) BIT 280 include/linux/qed/common_hsi.h #define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) BIT 281 include/linux/qed/common_hsi.h #define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) BIT 294 include/linux/qed/common_hsi.h #define DQ_UCM_ETH_PMD_TX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) BIT 295 include/linux/qed/common_hsi.h #define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) BIT 296 include/linux/qed/common_hsi.h #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) BIT 297 include/linux/qed/common_hsi.h #define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) BIT 298 include/linux/qed/common_hsi.h #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF3) BIT 299 include/linux/qed/common_hsi.h #define DQ_UCM_TOE_SLOW_PATH_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) BIT 300 include/linux/qed/common_hsi.h #define DQ_UCM_TOE_DQ_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) BIT 312 include/linux/qed/common_hsi.h #define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) BIT 313 include/linux/qed/common_hsi.h #define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2) BIT 314 include/linux/qed/common_hsi.h #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) BIT 315 include/linux/qed/common_hsi.h #define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) BIT 316 include/linux/qed/common_hsi.h #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) BIT 317 include/linux/qed/common_hsi.h #define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) BIT 318 include/linux/qed/common_hsi.h #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) BIT 319 include/linux/qed/common_hsi.h #define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) BIT 381 include/linux/qed/common_hsi.h #define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1)) BIT 383 include/linux/qed/common_hsi.h #define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1)) BIT 385 include/linux/qed/common_hsi.h #define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1)) BIT 387 include/linux/qed/common_hsi.h #define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1)) BIT 169 include/linux/qed/qed_if.h #define QED_EEE_1G_ADV BIT(0) BIT 170 include/linux/qed/qed_if.h #define QED_EEE_10G_ADV BIT(1) BIT 680 include/linux/qed/qed_if.h QED_LM_FIBRE_BIT = BIT(0), BIT 681 include/linux/qed/qed_if.h QED_LM_Autoneg_BIT = BIT(1), BIT 682 include/linux/qed/qed_if.h QED_LM_Asym_Pause_BIT = BIT(2), BIT 683 include/linux/qed/qed_if.h QED_LM_Pause_BIT = BIT(3), BIT 684 include/linux/qed/qed_if.h QED_LM_1000baseT_Full_BIT = BIT(4), BIT 685 include/linux/qed/qed_if.h QED_LM_10000baseT_Full_BIT = BIT(5), BIT 686 include/linux/qed/qed_if.h QED_LM_10000baseKR_Full_BIT = BIT(6), BIT 687 include/linux/qed/qed_if.h QED_LM_20000baseKR2_Full_BIT = BIT(7), BIT 688 include/linux/qed/qed_if.h QED_LM_25000baseKR_Full_BIT = BIT(8), BIT 689 include/linux/qed/qed_if.h QED_LM_40000baseLR4_Full_BIT = BIT(9), BIT 690 include/linux/qed/qed_if.h QED_LM_50000baseKR2_Full_BIT = BIT(10), BIT 691 include/linux/qed/qed_if.h QED_LM_100000baseKR4_Full_BIT = BIT(11), BIT 692 include/linux/qed/qed_if.h QED_LM_TP_BIT = BIT(12), BIT 693 include/linux/qed/qed_if.h QED_LM_Backplane_BIT = BIT(13), BIT 694 include/linux/qed/qed_if.h QED_LM_1000baseKX_Full_BIT = BIT(14), BIT 695 include/linux/qed/qed_if.h QED_LM_10000baseKX4_Full_BIT = BIT(15), BIT 696 include/linux/qed/qed_if.h QED_LM_10000baseR_FEC_BIT = BIT(16), BIT 697 include/linux/qed/qed_if.h QED_LM_40000baseKR4_Full_BIT = BIT(17), BIT 698 include/linux/qed/qed_if.h QED_LM_40000baseCR4_Full_BIT = BIT(18), BIT 699 include/linux/qed/qed_if.h QED_LM_40000baseSR4_Full_BIT = BIT(19), BIT 700 include/linux/qed/qed_if.h QED_LM_25000baseCR_Full_BIT = BIT(20), BIT 701 include/linux/qed/qed_if.h QED_LM_25000baseSR_Full_BIT = BIT(21), BIT 702 include/linux/qed/qed_if.h QED_LM_50000baseCR2_Full_BIT = BIT(22), BIT 703 include/linux/qed/qed_if.h QED_LM_100000baseSR4_Full_BIT = BIT(23), BIT 704 include/linux/qed/qed_if.h QED_LM_100000baseCR4_Full_BIT = BIT(24), BIT 705 include/linux/qed/qed_if.h QED_LM_100000baseLR4_ER4_Full_BIT = BIT(25), BIT 706 include/linux/qed/qed_if.h QED_LM_50000baseSR2_Full_BIT = BIT(26), BIT 707 include/linux/qed/qed_if.h QED_LM_1000baseX_Full_BIT = BIT(27), BIT 708 include/linux/qed/qed_if.h QED_LM_10000baseCR_Full_BIT = BIT(28), BIT 709 include/linux/qed/qed_if.h QED_LM_10000baseSR_Full_BIT = BIT(29), BIT 710 include/linux/qed/qed_if.h QED_LM_10000baseLR_Full_BIT = BIT(30), BIT 711 include/linux/qed/qed_if.h QED_LM_10000baseLRM_Full_BIT = BIT(31), BIT 718 include/linux/qed/qed_if.h #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) BIT 719 include/linux/qed/qed_if.h #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) BIT 720 include/linux/qed/qed_if.h #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) BIT 721 include/linux/qed/qed_if.h #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) BIT 722 include/linux/qed/qed_if.h #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) BIT 723 include/linux/qed/qed_if.h #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5) BIT 728 include/linux/qed/qed_if.h #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) BIT 729 include/linux/qed/qed_if.h #define QED_LINK_PAUSE_RX_ENABLE BIT(1) BIT 730 include/linux/qed/qed_if.h #define QED_LINK_PAUSE_TX_ENABLE BIT(2) BIT 732 include/linux/qed/qed_if.h #define QED_LINK_LOOPBACK_NONE BIT(0) BIT 733 include/linux/qed/qed_if.h #define QED_LINK_LOOPBACK_INT_PHY BIT(1) BIT 734 include/linux/qed/qed_if.h #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) BIT 735 include/linux/qed/qed_if.h #define QED_LINK_LOOPBACK_EXT BIT(3) BIT 736 include/linux/qed/qed_if.h #define QED_LINK_LOOPBACK_MAC BIT(4) BIT 791 include/linux/qed/qed_if.h #define QED_TLV_IP_CSUM BIT(0) BIT 792 include/linux/qed/qed_if.h #define QED_TLV_LSO BIT(1) BIT 132 include/linux/qed/qed_iscsi_if.h #define QED_ISCSI_CONN_HD_EN BIT(0) BIT 133 include/linux/qed/qed_iscsi_if.h #define QED_ISCSI_CONN_DD_EN BIT(1) BIT 134 include/linux/qed/qed_iscsi_if.h #define QED_ISCSI_CONN_INITIAL_R2T BIT(2) BIT 135 include/linux/qed/qed_iscsi_if.h #define QED_ISCSI_CONN_IMMEDIATE_DATA BIT(3) BIT 50 include/linux/qed/storage_common.h #define BDQ_MAX_EXTERNAL_RING_SIZE BIT(15) BIT 13 include/linux/ratelimit.h #define RATELIMIT_MSG_ON_RELEASE BIT(0) BIT 1147 include/linux/regmap.h .mask = BIT((_id) % (_reg_bits)), \ BIT 133 include/linux/regulator/consumer.h #define REGULATOR_ERROR_UNDER_VOLTAGE BIT(1) BIT 134 include/linux/regulator/consumer.h #define REGULATOR_ERROR_OVER_CURRENT BIT(2) BIT 135 include/linux/regulator/consumer.h #define REGULATOR_ERROR_REGULATION_OUT BIT(3) BIT 136 include/linux/regulator/consumer.h #define REGULATOR_ERROR_FAIL BIT(4) BIT 137 include/linux/regulator/consumer.h #define REGULATOR_ERROR_OVER_TEMP BIT(5) BIT 356 include/linux/rhashtable.h ((unsigned long)*bkt & ~BIT(0) ?: BIT 396 include/linux/rhashtable.h rcu_assign_pointer(*p, (void *)((unsigned long)obj | BIT(0))); BIT 68 include/linux/rmi.h #define RMI_F11_DISABLE_ABS_REPORT BIT(0) BIT 131 include/linux/rtc/ds1685.h #define RTC_HRS_AMPM_MASK BIT(7) /* Mask for the AM/PM bit */ BIT 149 include/linux/rtc/ds1685.h #define RTC_CTRL_A_UIP BIT(7) /* Update In Progress */ BIT 150 include/linux/rtc/ds1685.h #define RTC_CTRL_A_DV2 BIT(6) /* Countdown Chain */ BIT 151 include/linux/rtc/ds1685.h #define RTC_CTRL_A_DV1 BIT(5) /* Oscillator Enable */ BIT 152 include/linux/rtc/ds1685.h #define RTC_CTRL_A_DV0 BIT(4) /* Bank Select */ BIT 153 include/linux/rtc/ds1685.h #define RTC_CTRL_A_RS2 BIT(2) /* Rate-Selection Bit 2 */ BIT 154 include/linux/rtc/ds1685.h #define RTC_CTRL_A_RS3 BIT(3) /* Rate-Selection Bit 3 */ BIT 155 include/linux/rtc/ds1685.h #define RTC_CTRL_A_RS1 BIT(1) /* Rate-Selection Bit 1 */ BIT 156 include/linux/rtc/ds1685.h #define RTC_CTRL_A_RS0 BIT(0) /* Rate-Selection Bit 0 */ BIT 162 include/linux/rtc/ds1685.h #define RTC_CTRL_B_SET BIT(7) /* SET Bit */ BIT 163 include/linux/rtc/ds1685.h #define RTC_CTRL_B_PIE BIT(6) /* Periodic-Interrupt Enable */ BIT 164 include/linux/rtc/ds1685.h #define RTC_CTRL_B_AIE BIT(5) /* Alarm-Interrupt Enable */ BIT 165 include/linux/rtc/ds1685.h #define RTC_CTRL_B_UIE BIT(4) /* Update-Ended Interrupt-Enable */ BIT 166 include/linux/rtc/ds1685.h #define RTC_CTRL_B_SQWE BIT(3) /* Square-Wave Enable */ BIT 167 include/linux/rtc/ds1685.h #define RTC_CTRL_B_DM BIT(2) /* Data Mode */ BIT 168 include/linux/rtc/ds1685.h #define RTC_CTRL_B_2412 BIT(1) /* 12-Hr/24-Hr Mode */ BIT 169 include/linux/rtc/ds1685.h #define RTC_CTRL_B_DSE BIT(0) /* Daylight Savings Enable */ BIT 179 include/linux/rtc/ds1685.h #define RTC_CTRL_C_IRQF BIT(7) /* Interrupt-Request Flag */ BIT 180 include/linux/rtc/ds1685.h #define RTC_CTRL_C_PF BIT(6) /* Periodic-Interrupt Flag */ BIT 181 include/linux/rtc/ds1685.h #define RTC_CTRL_C_AF BIT(5) /* Alarm-Interrupt Flag */ BIT 182 include/linux/rtc/ds1685.h #define RTC_CTRL_C_UF BIT(4) /* Update-Ended Interrupt Flag */ BIT 192 include/linux/rtc/ds1685.h #define RTC_CTRL_D_VRT BIT(7) /* Valid RAM and Time */ BIT 206 include/linux/rtc/ds1685.h #define RTC_CTRL_4A_VRT2 BIT(7) /* Auxillary Battery Status */ BIT 207 include/linux/rtc/ds1685.h #define RTC_CTRL_4A_INCR BIT(6) /* Increment-in-Progress Status */ BIT 208 include/linux/rtc/ds1685.h #define RTC_CTRL_4A_PAB BIT(3) /* Power-Active Bar Control */ BIT 209 include/linux/rtc/ds1685.h #define RTC_CTRL_4A_RF BIT(2) /* RAM-Clear Flag */ BIT 210 include/linux/rtc/ds1685.h #define RTC_CTRL_4A_WF BIT(1) /* Wake-Up Alarm Flag */ BIT 211 include/linux/rtc/ds1685.h #define RTC_CTRL_4A_KF BIT(0) /* Kickstart Flag */ BIT 213 include/linux/rtc/ds1685.h #define RTC_CTRL_4A_BME BIT(5) /* Burst-Mode Enable */ BIT 221 include/linux/rtc/ds1685.h #define RTC_CTRL_4B_ABE BIT(7) /* Auxillary Battery Enable */ BIT 222 include/linux/rtc/ds1685.h #define RTC_CTRL_4B_E32K BIT(6) /* Enable 32.768Hz on SQW Pin */ BIT 223 include/linux/rtc/ds1685.h #define RTC_CTRL_4B_CS BIT(5) /* Crystal Select */ BIT 224 include/linux/rtc/ds1685.h #define RTC_CTRL_4B_RCE BIT(4) /* RAM Clear-Enable */ BIT 225 include/linux/rtc/ds1685.h #define RTC_CTRL_4B_PRS BIT(3) /* PAB Reset-Select */ BIT 226 include/linux/rtc/ds1685.h #define RTC_CTRL_4B_RIE BIT(2) /* RAM Clear-Interrupt Enable */ BIT 227 include/linux/rtc/ds1685.h #define RTC_CTRL_4B_WIE BIT(1) /* Wake-Up Alarm-Interrupt Enable */ BIT 228 include/linux/rtc/ds1685.h #define RTC_CTRL_4B_KSE BIT(0) /* Kickstart Interrupt-Enable */ BIT 584 include/linux/rtsx_pci.h #define LTR_TX_EN_MASK BIT(7) BIT 585 include/linux/rtsx_pci.h #define LTR_TX_EN_1 BIT(7) BIT 587 include/linux/rtsx_pci.h #define LTR_LATENCY_MODE_MASK BIT(6) BIT 589 include/linux/rtsx_pci.h #define LTR_LATENCY_MODE_SW BIT(6) BIT 638 include/linux/rtsx_pci.h #define L1OFF_MBIAS2_EN_5250 BIT(7) BIT 651 include/linux/rtsx_pci.h #define FORCE_CLKREQ_DELINK_MASK BIT(7) BIT 1098 include/linux/rtsx_pci.h #define ASPM_L1_1_EN_MASK BIT(3) BIT 1099 include/linux/rtsx_pci.h #define ASPM_L1_2_EN_MASK BIT(2) BIT 1100 include/linux/rtsx_pci.h #define PM_L1_1_EN_MASK BIT(1) BIT 1101 include/linux/rtsx_pci.h #define PM_L1_2_EN_MASK BIT(0) BIT 1103 include/linux/rtsx_pci.h #define ASPM_L1_1_EN BIT(0) BIT 1104 include/linux/rtsx_pci.h #define ASPM_L1_2_EN BIT(1) BIT 1105 include/linux/rtsx_pci.h #define PM_L1_1_EN BIT(2) BIT 1106 include/linux/rtsx_pci.h #define PM_L1_2_EN BIT(3) BIT 1107 include/linux/rtsx_pci.h #define LTR_L1SS_PWR_GATE_EN BIT(4) BIT 1108 include/linux/rtsx_pci.h #define L1_SNOOZE_TEST_EN BIT(5) BIT 1109 include/linux/rtsx_pci.h #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6) BIT 132 include/linux/scmi_protocol.h #define SCMI_POWER_STATE_ID_MASK (BIT(28) - 1) BIT 134 include/linux/scmi_protocol.h ((((type) & BIT(0)) << SCMI_POWER_STATE_TYPE_SHIFT) | \ BIT 64 include/linux/security.h #define CAP_OPT_NOAUDIT BIT(1) BIT 66 include/linux/security.h #define CAP_OPT_INSETID BIT(2) BIT 156 include/linux/serial_core.h #define UPQ_NO_TXEN_TEST BIT(0) BIT 14 include/linux/serial_sci.h #define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */ BIT 15 include/linux/serial_sci.h #define SCSCR_RIE BIT(6) /* Receive Interrupt Enable */ BIT 16 include/linux/serial_sci.h #define SCSCR_TE BIT(5) /* Transmit Enable */ BIT 17 include/linux/serial_sci.h #define SCSCR_RE BIT(4) /* Receive Enable */ BIT 18 include/linux/serial_sci.h #define SCSCR_REIE BIT(3) /* Receive Error Interrupt Enable @ */ BIT 19 include/linux/serial_sci.h #define SCSCR_TOIE BIT(2) /* Timeout Interrupt Enable @ */ BIT 20 include/linux/serial_sci.h #define SCSCR_CKE1 BIT(1) /* Clock Enable 1 */ BIT 21 include/linux/serial_sci.h #define SCSCR_CKE0 BIT(0) /* Clock Enable 0 */ BIT 340 include/linux/sfp.h SFP_OPTIONS_HIGH_POWER_LEVEL = BIT(13), BIT 341 include/linux/sfp.h SFP_OPTIONS_PAGING_A2 = BIT(12), BIT 342 include/linux/sfp.h SFP_OPTIONS_RETIMER = BIT(11), BIT 343 include/linux/sfp.h SFP_OPTIONS_COOLED_XCVR = BIT(10), BIT 344 include/linux/sfp.h SFP_OPTIONS_POWER_DECL = BIT(9), BIT 345 include/linux/sfp.h SFP_OPTIONS_RX_LINEAR_OUT = BIT(8), BIT 346 include/linux/sfp.h SFP_OPTIONS_RX_DECISION_THRESH = BIT(7), BIT 347 include/linux/sfp.h SFP_OPTIONS_TUNABLE_TX = BIT(6), BIT 348 include/linux/sfp.h SFP_OPTIONS_RATE_SELECT = BIT(5), BIT 349 include/linux/sfp.h SFP_OPTIONS_TX_DISABLE = BIT(4), BIT 350 include/linux/sfp.h SFP_OPTIONS_TX_FAULT = BIT(3), BIT 351 include/linux/sfp.h SFP_OPTIONS_LOS_INVERTED = BIT(2), BIT 352 include/linux/sfp.h SFP_OPTIONS_LOS_NORMAL = BIT(1), BIT 353 include/linux/sfp.h SFP_DIAGMON_DDM = BIT(6), BIT 354 include/linux/sfp.h SFP_DIAGMON_INT_CAL = BIT(5), BIT 355 include/linux/sfp.h SFP_DIAGMON_EXT_CAL = BIT(4), BIT 356 include/linux/sfp.h SFP_DIAGMON_RXPWR_AVG = BIT(3), BIT 357 include/linux/sfp.h SFP_DIAGMON_ADDRMODE = BIT(2), BIT 358 include/linux/sfp.h SFP_ENHOPTS_ALARMWARN = BIT(7), BIT 359 include/linux/sfp.h SFP_ENHOPTS_SOFT_TX_DISABLE = BIT(6), BIT 360 include/linux/sfp.h SFP_ENHOPTS_SOFT_TX_FAULT = BIT(5), BIT 361 include/linux/sfp.h SFP_ENHOPTS_SOFT_RX_LOS = BIT(4), BIT 362 include/linux/sfp.h SFP_ENHOPTS_SOFT_RATE_SELECT = BIT(3), BIT 363 include/linux/sfp.h SFP_ENHOPTS_APP_SELECT_SFF8079 = BIT(2), BIT 364 include/linux/sfp.h SFP_ENHOPTS_SOFT_RATE_SFF8431 = BIT(1), BIT 432 include/linux/sfp.h SFP_ALARM0_TEMP_HIGH = BIT(7), BIT 433 include/linux/sfp.h SFP_ALARM0_TEMP_LOW = BIT(6), BIT 434 include/linux/sfp.h SFP_ALARM0_VCC_HIGH = BIT(5), BIT 435 include/linux/sfp.h SFP_ALARM0_VCC_LOW = BIT(4), BIT 436 include/linux/sfp.h SFP_ALARM0_TX_BIAS_HIGH = BIT(3), BIT 437 include/linux/sfp.h SFP_ALARM0_TX_BIAS_LOW = BIT(2), BIT 438 include/linux/sfp.h SFP_ALARM0_TXPWR_HIGH = BIT(1), BIT 439 include/linux/sfp.h SFP_ALARM0_TXPWR_LOW = BIT(0), BIT 442 include/linux/sfp.h SFP_ALARM1_RXPWR_HIGH = BIT(7), BIT 443 include/linux/sfp.h SFP_ALARM1_RXPWR_LOW = BIT(6), BIT 446 include/linux/sfp.h SFP_WARN0_TEMP_HIGH = BIT(7), BIT 447 include/linux/sfp.h SFP_WARN0_TEMP_LOW = BIT(6), BIT 448 include/linux/sfp.h SFP_WARN0_VCC_HIGH = BIT(5), BIT 449 include/linux/sfp.h SFP_WARN0_VCC_LOW = BIT(4), BIT 450 include/linux/sfp.h SFP_WARN0_TX_BIAS_HIGH = BIT(3), BIT 451 include/linux/sfp.h SFP_WARN0_TX_BIAS_LOW = BIT(2), BIT 452 include/linux/sfp.h SFP_WARN0_TXPWR_HIGH = BIT(1), BIT 453 include/linux/sfp.h SFP_WARN0_TXPWR_LOW = BIT(0), BIT 456 include/linux/sfp.h SFP_WARN1_RXPWR_HIGH = BIT(7), BIT 457 include/linux/sfp.h SFP_WARN1_RXPWR_LOW = BIT(6), BIT 68 include/linux/sh_clk.h #define CLK_ENABLE_ON_INIT BIT(0) BIT 70 include/linux/sh_clk.h #define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */ BIT 71 include/linux/sh_clk.h #define CLK_ENABLE_REG_16BIT BIT(2) BIT 72 include/linux/sh_clk.h #define CLK_ENABLE_REG_8BIT BIT(3) BIT 74 include/linux/sh_clk.h #define CLK_MASK_DIV_ON_DISABLE BIT(4) BIT 34 include/linux/smsc911x.h #define SMSC911X_USE_16BIT (BIT(0)) BIT 35 include/linux/smsc911x.h #define SMSC911X_USE_32BIT (BIT(1)) BIT 36 include/linux/smsc911x.h #define SMSC911X_FORCE_INTERNAL_PHY (BIT(2)) BIT 37 include/linux/smsc911x.h #define SMSC911X_FORCE_EXTERNAL_PHY (BIT(3)) BIT 38 include/linux/smsc911x.h #define SMSC911X_SAVE_MAC_ADDRESS (BIT(4)) BIT 48 include/linux/smsc911x.h #define SMSC911X_SWAP_FIFO (BIT(5)) BIT 5 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) BIT 6 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) BIT 7 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) BIT 8 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6) BIT 9 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9) BIT 10 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) BIT 11 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12) BIT 12 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13) BIT 13 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) BIT 14 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15) BIT 15 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16) BIT 16 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) BIT 17 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18) BIT 18 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19) BIT 19 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20) BIT 20 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) BIT 21 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) BIT 22 include/linux/soc/mediatek/infracfg.h #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) BIT 24 include/linux/soc/mediatek/infracfg.h #define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) BIT 25 include/linux/soc/mediatek/infracfg.h #define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) BIT 26 include/linux/soc/mediatek/infracfg.h #define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) BIT 28 include/linux/soc/mediatek/infracfg.h #define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) BIT 29 include/linux/soc/mediatek/infracfg.h #define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) BIT 30 include/linux/soc/mediatek/infracfg.h #define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ BIT 31 include/linux/soc/mediatek/infracfg.h BIT(28)) BIT 32 include/linux/soc/mediatek/infracfg.h #define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ BIT 33 include/linux/soc/mediatek/infracfg.h BIT(7) | BIT(8)) BIT 9 include/linux/soc/qcom/mdt_loader.h #define QCOM_MDT_RELOCATABLE BIT(27) BIT 38 include/linux/soc/samsung/exynos-regs-pmu.h #define S5P_USE_DELAYED_RESET_ASSERTION BIT(12) BIT 158 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS_L2_USE_RETENTION BIT(4) BIT 357 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5_USE_RETENTION BIT(4) BIT 488 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3) BIT 492 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_UFS BIT(8) BIT 493 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_ATB_KFC BIT(13) BIT 494 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_ATB_ISP_ARM BIT(19) BIT 495 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_EMULATION BIT(31) BIT 503 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_KFC_CORE_RESET0 BIT(8) BIT 504 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_KFC_ETM_RESET0 BIT(20) BIT 615 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5_USE_STANDBYWFI_ARM_CORE0 BIT(16) BIT 617 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5_USE_STANDBYWFE_ARM_CORE0 BIT(24) BIT 618 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5_USE_STANDBYWFE_ARM_CORE1 BIT(25) BIT 620 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_ARM_USE_STANDBY_WFI0 BIT(4) BIT 621 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_ARM_USE_STANDBY_WFI1 BIT(5) BIT 622 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_ARM_USE_STANDBY_WFI2 BIT(6) BIT 623 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_ARM_USE_STANDBY_WFI3 BIT(7) BIT 624 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_KFC_USE_STANDBY_WFI0 BIT(8) BIT 625 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_KFC_USE_STANDBY_WFI1 BIT(9) BIT 626 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_KFC_USE_STANDBY_WFI2 BIT(10) BIT 627 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_KFC_USE_STANDBY_WFI3 BIT(11) BIT 628 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_ARM_USE_STANDBY_WFE0 BIT(16) BIT 629 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_ARM_USE_STANDBY_WFE1 BIT(17) BIT 630 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_ARM_USE_STANDBY_WFE2 BIT(18) BIT 631 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_ARM_USE_STANDBY_WFE3 BIT(19) BIT 632 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_KFC_USE_STANDBY_WFE0 BIT(20) BIT 633 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_KFC_USE_STANDBY_WFE1 BIT(21) BIT 634 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_KFC_USE_STANDBY_WFE2 BIT(22) BIT 635 include/linux/soc/samsung/exynos-regs-pmu.h #define EXYNOS5420_KFC_USE_STANDBY_WFE3 BIT(23) BIT 25 include/linux/soc/ti/knav_dma.h #define MASK(x) (BIT(x) - 1) BIT 28 include/linux/soc/ti/knav_dma.h #define KNAV_DMA_DESC_PS_INFO_IN_SOP BIT(22) BIT 35 include/linux/soc/ti/knav_dma.h #define KNAV_DMA_DESC_HAS_EPIB BIT(31) BIT 248 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0) BIT 250 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1) BIT 252 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2) BIT 254 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3) BIT 256 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4) BIT 258 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5) BIT 321 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0) BIT 322 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1) BIT 323 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2) BIT 324 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3) BIT 325 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4) BIT 326 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5) BIT 327 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6) BIT 328 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7) BIT 329 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8) BIT 330 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14) BIT 340 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9) BIT 341 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10) BIT 342 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11) BIT 343 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12) BIT 344 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13) BIT 372 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9) BIT 373 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10) BIT 374 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11) BIT 375 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12) BIT 402 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0) BIT 403 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1) BIT 404 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2) BIT 405 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3) BIT 406 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4) BIT 407 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5) BIT 408 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6) BIT 409 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7) BIT 410 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8) BIT 411 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9) BIT 412 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10) BIT 413 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11) BIT 414 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12) BIT 415 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13) BIT 416 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14) BIT 417 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15) BIT 418 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16) BIT 419 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17) BIT 420 include/linux/soc/ti/ti_sci_protocol.h #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18) BIT 63 include/linux/soundwire/sdw.h #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0) BIT 64 include/linux/soundwire/sdw.h #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1) BIT 68 include/linux/soundwire/sdw.h #define SDW_BLOCK_PACKG_PER_PORT BIT(0) BIT 69 include/linux/soundwire/sdw.h #define SDW_BLOCK_PACKG_PER_CH BIT(1) BIT 43 include/linux/soundwire/sdw_registers.h #define SDW_DP0_INT_TEST_FAIL BIT(0) BIT 44 include/linux/soundwire/sdw_registers.h #define SDW_DP0_INT_PORT_READY BIT(1) BIT 45 include/linux/soundwire/sdw_registers.h #define SDW_DP0_INT_BRA_FAILURE BIT(2) BIT 46 include/linux/soundwire/sdw_registers.h #define SDW_DP0_INT_IMPDEF1 BIT(5) BIT 47 include/linux/soundwire/sdw_registers.h #define SDW_DP0_INT_IMPDEF2 BIT(6) BIT 48 include/linux/soundwire/sdw_registers.h #define SDW_DP0_INT_IMPDEF3 BIT(7) BIT 51 include/linux/soundwire/sdw_registers.h #define SDW_DP0_PORTCTRL_NXTINVBANK BIT(4) BIT 66 include/linux/soundwire/sdw_registers.h #define SDW_SCP_INT1_PARITY BIT(0) BIT 67 include/linux/soundwire/sdw_registers.h #define SDW_SCP_INT1_BUS_CLASH BIT(1) BIT 68 include/linux/soundwire/sdw_registers.h #define SDW_SCP_INT1_IMPL_DEF BIT(2) BIT 69 include/linux/soundwire/sdw_registers.h #define SDW_SCP_INT1_SCP2_CASCADE BIT(7) BIT 73 include/linux/soundwire/sdw_registers.h #define SDW_SCP_INTSTAT2_SCP3_CASCADE BIT(7) BIT 86 include/linux/soundwire/sdw_registers.h #define SDW_SCP_CTRL_CLK_STP_NOW BIT(1) BIT 87 include/linux/soundwire/sdw_registers.h #define SDW_SCP_CTRL_FORCE_RESET BIT(7) BIT 90 include/linux/soundwire/sdw_registers.h #define SDW_SCP_STAT_CLK_STP_NF BIT(0) BIT 91 include/linux/soundwire/sdw_registers.h #define SDW_SCP_STAT_HPHY_NOK BIT(5) BIT 92 include/linux/soundwire/sdw_registers.h #define SDW_SCP_STAT_CURR_BANK BIT(6) BIT 95 include/linux/soundwire/sdw_registers.h #define SDW_SCP_SYSTEMCTRL_CLK_STP_PREP BIT(0) BIT 96 include/linux/soundwire/sdw_registers.h #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE BIT(2) BIT 97 include/linux/soundwire/sdw_registers.h #define SDW_SCP_SYSTEMCTRL_WAKE_UP_EN BIT(3) BIT 98 include/linux/soundwire/sdw_registers.h #define SDW_SCP_SYSTEMCTRL_HIGH_PHY BIT(4) BIT 101 include/linux/soundwire/sdw_registers.h #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1 BIT(2) BIT 131 include/linux/soundwire/sdw_registers.h #define SDW_DPN_INT_TEST_FAIL BIT(0) BIT 132 include/linux/soundwire/sdw_registers.h #define SDW_DPN_INT_PORT_READY BIT(1) BIT 133 include/linux/soundwire/sdw_registers.h #define SDW_DPN_INT_IMPDEF1 BIT(5) BIT 134 include/linux/soundwire/sdw_registers.h #define SDW_DPN_INT_IMPDEF2 BIT(6) BIT 135 include/linux/soundwire/sdw_registers.h #define SDW_DPN_INT_IMPDEF3 BIT(7) BIT 139 include/linux/soundwire/sdw_registers.h #define SDW_DPN_PORTCTRL_NXTINVBANK BIT(4) BIT 452 include/linux/spi/spi.h #define SPI_BPW_MASK(bits) BIT((bits) - 1) BIT 461 include/linux/spi/spi.h #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* can't do full duplex */ BIT 462 include/linux/spi/spi.h #define SPI_CONTROLLER_NO_RX BIT(1) /* can't do buffer read */ BIT 463 include/linux/spi/spi.h #define SPI_CONTROLLER_NO_TX BIT(2) /* can't do buffer write */ BIT 464 include/linux/spi/spi.h #define SPI_CONTROLLER_MUST_RX BIT(3) /* requires rx */ BIT 465 include/linux/spi/spi.h #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */ BIT 467 include/linux/spi/spi.h #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ BIT 111 include/linux/sunrpc/rpc_rdma.h RPCRDMA_CMP_F_SND_W_INV_OK = BIT(0), BIT 213 include/linux/suspend.h #define PM_SUSPEND_FLAG_FW_SUSPEND BIT(0) BIT 214 include/linux/suspend.h #define PM_SUSPEND_FLAG_FW_RESUME BIT(1) BIT 215 include/linux/suspend.h #define PM_SUSPEND_FLAG_NO_PLATFORM BIT(2) BIT 16 include/linux/switchtec.h #define SWITCHTEC_EVENT_OCCURRED BIT(0) BIT 17 include/linux/switchtec.h #define SWITCHTEC_EVENT_CLEAR BIT(0) BIT 18 include/linux/switchtec.h #define SWITCHTEC_EVENT_EN_LOG BIT(1) BIT 19 include/linux/switchtec.h #define SWITCHTEC_EVENT_EN_CLI BIT(2) BIT 20 include/linux/switchtec.h #define SWITCHTEC_EVENT_EN_IRQ BIT(3) BIT 21 include/linux/switchtec.h #define SWITCHTEC_EVENT_FATAL BIT(4) BIT 23 include/linux/switchtec.h #define SWITCHTEC_DMA_MRPC_EN BIT(0) BIT 23 include/linux/tee_drv.h #define TEE_SHM_MAPPED BIT(0) /* Memory mapped by the kernel */ BIT 24 include/linux/tee_drv.h #define TEE_SHM_DMA_BUF BIT(1) /* Memory with dma-buf handle */ BIT 25 include/linux/tee_drv.h #define TEE_SHM_EXT_DMA_BUF BIT(2) /* Memory with dma-buf handle */ BIT 26 include/linux/tee_drv.h #define TEE_SHM_REGISTER BIT(3) /* Memory registered in secure world */ BIT 27 include/linux/tee_drv.h #define TEE_SHM_USER_MAPPED BIT(4) /* Memory mapped in user space */ BIT 28 include/linux/tee_drv.h #define TEE_SHM_POOL BIT(5) /* Memory allocated from pool */ BIT 504 include/linux/thunderbolt.h #define RING_FLAG_NO_SUSPEND BIT(0) BIT 506 include/linux/thunderbolt.h #define RING_FLAG_FRAME BIT(1) BIT 508 include/linux/thunderbolt.h #define RING_FLAG_E2E BIT(2) BIT 56 include/linux/tpm.h TPM_OPS_AUTO_STARTUP = BIT(0), BIT 156 include/linux/trace_events.h #define TRACE_RECORD_CMDLINE BIT(0) BIT 157 include/linux/trace_events.h #define TRACE_RECORD_TGID BIT(1) BIT 51 include/linux/ulpi/regs.h #define ULPI_FUNC_CTRL_XCVRSEL BIT(0) BIT 57 include/linux/ulpi/regs.h #define ULPI_FUNC_CTRL_TERMSELECT BIT(2) BIT 58 include/linux/ulpi/regs.h #define ULPI_FUNC_CTRL_OPMODE BIT(3) BIT 64 include/linux/ulpi/regs.h #define ULPI_FUNC_CTRL_RESET BIT(5) BIT 65 include/linux/ulpi/regs.h #define ULPI_FUNC_CTRL_SUSPENDM BIT(6) BIT 68 include/linux/ulpi/regs.h #define ULPI_IFC_CTRL_6_PIN_SERIAL_MODE BIT(0) BIT 69 include/linux/ulpi/regs.h #define ULPI_IFC_CTRL_3_PIN_SERIAL_MODE BIT(1) BIT 70 include/linux/ulpi/regs.h #define ULPI_IFC_CTRL_CARKITMODE BIT(2) BIT 71 include/linux/ulpi/regs.h #define ULPI_IFC_CTRL_CLOCKSUSPENDM BIT(3) BIT 72 include/linux/ulpi/regs.h #define ULPI_IFC_CTRL_AUTORESUME BIT(4) BIT 73 include/linux/ulpi/regs.h #define ULPI_IFC_CTRL_EXTERNAL_VBUS BIT(5) BIT 74 include/linux/ulpi/regs.h #define ULPI_IFC_CTRL_PASSTHRU BIT(6) BIT 75 include/linux/ulpi/regs.h #define ULPI_IFC_CTRL_PROTECT_IFC_DISABLE BIT(7) BIT 78 include/linux/ulpi/regs.h #define ULPI_OTG_CTRL_ID_PULLUP BIT(0) BIT 79 include/linux/ulpi/regs.h #define ULPI_OTG_CTRL_DP_PULLDOWN BIT(1) BIT 80 include/linux/ulpi/regs.h #define ULPI_OTG_CTRL_DM_PULLDOWN BIT(2) BIT 81 include/linux/ulpi/regs.h #define ULPI_OTG_CTRL_DISCHRGVBUS BIT(3) BIT 82 include/linux/ulpi/regs.h #define ULPI_OTG_CTRL_CHRGVBUS BIT(4) BIT 83 include/linux/ulpi/regs.h #define ULPI_OTG_CTRL_DRVVBUS BIT(5) BIT 84 include/linux/ulpi/regs.h #define ULPI_OTG_CTRL_DRVVBUS_EXT BIT(6) BIT 85 include/linux/ulpi/regs.h #define ULPI_OTG_CTRL_EXTVBUSIND BIT(7) BIT 92 include/linux/ulpi/regs.h #define ULPI_INT_HOST_DISCONNECT BIT(0) BIT 93 include/linux/ulpi/regs.h #define ULPI_INT_VBUS_VALID BIT(1) BIT 94 include/linux/ulpi/regs.h #define ULPI_INT_SESS_VALID BIT(2) BIT 95 include/linux/ulpi/regs.h #define ULPI_INT_SESS_END BIT(3) BIT 96 include/linux/ulpi/regs.h #define ULPI_INT_IDGRD BIT(4) BIT 99 include/linux/ulpi/regs.h #define ULPI_DEBUG_LINESTATE0 BIT(0) BIT 100 include/linux/ulpi/regs.h #define ULPI_DEBUG_LINESTATE1 BIT(1) BIT 103 include/linux/ulpi/regs.h #define ULPI_CARKIT_CTRL_CARKITPWR BIT(0) BIT 104 include/linux/ulpi/regs.h #define ULPI_CARKIT_CTRL_IDGNDDRV BIT(1) BIT 105 include/linux/ulpi/regs.h #define ULPI_CARKIT_CTRL_TXDEN BIT(2) BIT 106 include/linux/ulpi/regs.h #define ULPI_CARKIT_CTRL_RXDEN BIT(3) BIT 107 include/linux/ulpi/regs.h #define ULPI_CARKIT_CTRL_SPKLEFTEN BIT(4) BIT 108 include/linux/ulpi/regs.h #define ULPI_CARKIT_CTRL_SPKRIGHTEN BIT(5) BIT 109 include/linux/ulpi/regs.h #define ULPI_CARKIT_CTRL_MICEN BIT(6) BIT 112 include/linux/ulpi/regs.h #define ULPI_CARKIT_INT_EN_IDFLOAT_RISE BIT(0) BIT 113 include/linux/ulpi/regs.h #define ULPI_CARKIT_INT_EN_IDFLOAT_FALL BIT(1) BIT 114 include/linux/ulpi/regs.h #define ULPI_CARKIT_INT_EN_CARINTDET BIT(2) BIT 115 include/linux/ulpi/regs.h #define ULPI_CARKIT_INT_EN_DP_RISE BIT(3) BIT 116 include/linux/ulpi/regs.h #define ULPI_CARKIT_INT_EN_DP_FALL BIT(4) BIT 121 include/linux/ulpi/regs.h #define ULPI_CARKIT_INT_IDFLOAT BIT(0) BIT 122 include/linux/ulpi/regs.h #define ULPI_CARKIT_INT_CARINTDET BIT(1) BIT 123 include/linux/ulpi/regs.h #define ULPI_CARKIT_INT_DP BIT(2) BIT 126 include/linux/ulpi/regs.h #define ULPI_CARKIT_PLS_CTRL_TXPLSEN BIT(0) BIT 127 include/linux/ulpi/regs.h #define ULPI_CARKIT_PLS_CTRL_RXPLSEN BIT(1) BIT 128 include/linux/ulpi/regs.h #define ULPI_CARKIT_PLS_CTRL_SPKRLEFT_BIASEN BIT(2) BIT 129 include/linux/ulpi/regs.h #define ULPI_CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN BIT(3) BIT 494 include/linux/usb.h #define USB_PORT_QUIRK_OLD_SCHEME BIT(0) BIT 497 include/linux/usb.h #define USB_PORT_QUIRK_FAST_ENUM BIT(1) BIT 43 include/linux/usb/chipidea.h #define CI_HDRC_REGS_SHARED BIT(0) BIT 44 include/linux/usb/chipidea.h #define CI_HDRC_DISABLE_DEVICE_STREAMING BIT(1) BIT 45 include/linux/usb/chipidea.h #define CI_HDRC_SUPPORTS_RUNTIME_PM BIT(2) BIT 46 include/linux/usb/chipidea.h #define CI_HDRC_DISABLE_HOST_STREAMING BIT(3) BIT 53 include/linux/usb/chipidea.h #define CI_HDRC_DUAL_ROLE_NOT_OTG BIT(4) BIT 54 include/linux/usb/chipidea.h #define CI_HDRC_IMX28_WRITE_FIX BIT(5) BIT 55 include/linux/usb/chipidea.h #define CI_HDRC_FORCE_FULLSPEED BIT(6) BIT 56 include/linux/usb/chipidea.h #define CI_HDRC_TURN_VBUS_EARLY_ON BIT(7) BIT 57 include/linux/usb/chipidea.h #define CI_HDRC_SET_NON_ZERO_TTHA BIT(8) BIT 58 include/linux/usb/chipidea.h #define CI_HDRC_OVERRIDE_AHB_BURST BIT(9) BIT 59 include/linux/usb/chipidea.h #define CI_HDRC_OVERRIDE_TX_BURST BIT(10) BIT 60 include/linux/usb/chipidea.h #define CI_HDRC_OVERRIDE_RX_BURST BIT(11) BIT 61 include/linux/usb/chipidea.h #define CI_HDRC_OVERRIDE_PHY_CONTROL BIT(12) /* Glue layer manages phy */ BIT 62 include/linux/usb/chipidea.h #define CI_HDRC_REQUIRES_ALIGNED_DMA BIT(13) BIT 63 include/linux/usb/chipidea.h #define CI_HDRC_IMX_IS_HSIC BIT(14) BIT 64 include/linux/usb/chipidea.h #define CI_HDRC_PMQOS BIT(15) BIT 77 include/linux/usb/pd.h #define PD_HEADER_EXT_HDR BIT(15) BIT 82 include/linux/usb/pd.h #define PD_HEADER_PWR_ROLE BIT(8) BIT 85 include/linux/usb/pd.h #define PD_HEADER_DATA_ROLE BIT(5) BIT 141 include/linux/usb/pd.h #define PD_EXT_HDR_CHUNKED BIT(15) BIT 144 include/linux/usb/pd.h #define PD_EXT_HDR_REQ_CHUNK BIT(10) BIT 221 include/linux/usb/pd.h #define PDO_FIXED_DUAL_ROLE BIT(29) /* Power role swap supported */ BIT 222 include/linux/usb/pd.h #define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported (Source) */ BIT 223 include/linux/usb/pd.h #define PDO_FIXED_HIGHER_CAP BIT(28) /* Requires more than vSafe5V (Sink) */ BIT 224 include/linux/usb/pd.h #define PDO_FIXED_EXTPOWER BIT(27) /* Externally powered */ BIT 225 include/linux/usb/pd.h #define PDO_FIXED_USB_COMM BIT(26) /* USB communications capable */ BIT 226 include/linux/usb/pd.h #define PDO_FIXED_DATA_SWAP BIT(25) /* Data role swap supported */ BIT 347 include/linux/usb/pd.h #define RDO_GIVE_BACK BIT(27) /* Supports reduced operating current */ BIT 348 include/linux/usb/pd.h #define RDO_CAP_MISMATCH BIT(26) /* Not satisfied by source caps */ BIT 349 include/linux/usb/pd.h #define RDO_USB_COMM BIT(25) /* USB communications capable */ BIT 350 include/linux/usb/pd.h #define RDO_NO_SUSPEND BIT(24) /* USB Suspend not supported */ BIT 19 include/linux/usb/pd_ado.h #define USB_PD_ADO_TYPE_BATT_STATUS_CHANGE BIT(1) BIT 20 include/linux/usb/pd_ado.h #define USB_PD_ADO_TYPE_OCP BIT(2) BIT 21 include/linux/usb/pd_ado.h #define USB_PD_ADO_TYPE_OTP BIT(3) BIT 22 include/linux/usb/pd_ado.h #define USB_PD_ADO_TYPE_OP_COND_CHANGE BIT(4) BIT 23 include/linux/usb/pd_ado.h #define USB_PD_ADO_TYPE_SRC_INPUT_CHANGE BIT(5) BIT 24 include/linux/usb/pd_ado.h #define USB_PD_ADO_TYPE_OVP BIT(6) BIT 22 include/linux/usb/pd_ext_sdb.h #define USB_PD_EXT_SDB_EVENT_OCP BIT(1) BIT 23 include/linux/usb/pd_ext_sdb.h #define USB_PD_EXT_SDB_EVENT_OTP BIT(2) BIT 24 include/linux/usb/pd_ext_sdb.h #define USB_PD_EXT_SDB_EVENT_OVP BIT(3) BIT 25 include/linux/usb/pd_ext_sdb.h #define USB_PD_EXT_SDB_EVENT_CF_CV_MODE BIT(4) BIT 12 include/linux/usb/quirks.h #define USB_QUIRK_STRING_FETCH_255 BIT(0) BIT 15 include/linux/usb/quirks.h #define USB_QUIRK_RESET_RESUME BIT(1) BIT 18 include/linux/usb/quirks.h #define USB_QUIRK_NO_SET_INTF BIT(2) BIT 21 include/linux/usb/quirks.h #define USB_QUIRK_CONFIG_INTF_STRINGS BIT(3) BIT 24 include/linux/usb/quirks.h #define USB_QUIRK_RESET BIT(4) BIT 28 include/linux/usb/quirks.h #define USB_QUIRK_HONOR_BNUMINTERFACES BIT(5) BIT 32 include/linux/usb/quirks.h #define USB_QUIRK_DELAY_INIT BIT(6) BIT 43 include/linux/usb/quirks.h #define USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL BIT(7) BIT 46 include/linux/usb/quirks.h #define USB_QUIRK_DEVICE_QUALIFIER BIT(8) BIT 49 include/linux/usb/quirks.h #define USB_QUIRK_IGNORE_REMOTE_WAKEUP BIT(9) BIT 52 include/linux/usb/quirks.h #define USB_QUIRK_NO_LPM BIT(10) BIT 58 include/linux/usb/quirks.h #define USB_QUIRK_LINEAR_FRAME_INTR_BINTERVAL BIT(11) BIT 64 include/linux/usb/quirks.h #define USB_QUIRK_DISCONNECT_SUSPEND BIT(12) BIT 67 include/linux/usb/quirks.h #define USB_QUIRK_DELAY_CTRL_MSG BIT(13) BIT 70 include/linux/usb/quirks.h #define USB_QUIRK_HUB_SLOW_RESET BIT(14) BIT 73 include/linux/usb/quirks.h #define USB_QUIRK_ENDPOINT_BLACKLIST BIT(15) BIT 89 include/linux/usb/tcpm.h #define TCPC_MUX_USB_ENABLED BIT(0) /* USB enabled */ BIT 90 include/linux/usb/tcpm.h #define TCPC_MUX_DP_ENABLED BIT(1) /* DP enabled */ BIT 91 include/linux/usb/tcpm.h #define TCPC_MUX_POLARITY_INVERTED BIT(2) /* Polarity inverted */ BIT 70 include/linux/usb/typec_dp.h #define DP_CAP_DP_SIGNALING BIT(2) /* Always set */ BIT 71 include/linux/usb/typec_dp.h #define DP_CAP_GEN2 BIT(3) /* Reserved after v1.0b */ BIT 72 include/linux/usb/typec_dp.h #define DP_CAP_RECEPTACLE BIT(6) BIT 73 include/linux/usb/typec_dp.h #define DP_CAP_USB BIT(7) BIT 83 include/linux/usb/typec_dp.h #define DP_STATUS_POWER_LOW BIT(2) BIT 84 include/linux/usb/typec_dp.h #define DP_STATUS_ENABLED BIT(3) BIT 85 include/linux/usb/typec_dp.h #define DP_STATUS_PREFER_MULTI_FUNC BIT(4) BIT 86 include/linux/usb/typec_dp.h #define DP_STATUS_SWITCH_TO_USB BIT(5) BIT 87 include/linux/usb/typec_dp.h #define DP_STATUS_EXIT_DP_MODE BIT(6) BIT 88 include/linux/usb/typec_dp.h #define DP_STATUS_HPD_STATE BIT(7) /* 0 = HPD_Low, 1 = HPD_High */ BIT 89 include/linux/usb/typec_dp.h #define DP_STATUS_IRQ_HPD BIT(8) BIT 93 include/linux/usb/typec_dp.h #define DP_CONF_UFP_U_AS_DFP_D BIT(0) BIT 94 include/linux/usb/typec_dp.h #define DP_CONF_UFP_U_AS_UFP_D BIT(1) BIT 95 include/linux/usb/typec_dp.h #define DP_CONF_SIGNALING_DP BIT(2) BIT 96 include/linux/usb/typec_dp.h #define DP_CONF_SIGNALING_GEN_2 BIT(3) /* Reserved after v1.0b */ BIT 48 include/linux/usb/usb338x.h BIT(IN_ENDPOINT_ENABLE)) BIT 50 include/linux/usb/usb338x.h BIT(OUT_ENDPOINT_ENABLE)) BIT 117 include/linux/vfio.h #define VFIO_IOMMU_NOTIFY_DMA_UNMAP BIT(0) BIT 120 include/linux/vfio.h #define VFIO_GROUP_NOTIFY_SET_KVM BIT(0) BIT 29 include/linux/vmw_vmci_defs.h #define VMCI_STATUS_INT_ON BIT(0) BIT 32 include/linux/vmw_vmci_defs.h #define VMCI_CONTROL_RESET BIT(0) BIT 33 include/linux/vmw_vmci_defs.h #define VMCI_CONTROL_INT_ENABLE BIT(1) BIT 34 include/linux/vmw_vmci_defs.h #define VMCI_CONTROL_INT_DISABLE BIT(2) BIT 37 include/linux/vmw_vmci_defs.h #define VMCI_CAPS_HYPERCALL BIT(0) BIT 38 include/linux/vmw_vmci_defs.h #define VMCI_CAPS_GUESTCALL BIT(1) BIT 39 include/linux/vmw_vmci_defs.h #define VMCI_CAPS_DATAGRAM BIT(2) BIT 40 include/linux/vmw_vmci_defs.h #define VMCI_CAPS_NOTIFICATIONS BIT(3) BIT 41 include/linux/vmw_vmci_defs.h #define VMCI_CAPS_PPN64 BIT(4) BIT 44 include/linux/vmw_vmci_defs.h #define VMCI_ICR_DATAGRAM BIT(0) BIT 45 include/linux/vmw_vmci_defs.h #define VMCI_ICR_NOTIFICATION BIT(1) BIT 48 include/linux/vmw_vmci_defs.h #define VMCI_IMR_DATAGRAM BIT(0) BIT 49 include/linux/vmw_vmci_defs.h #define VMCI_IMR_NOTIFICATION BIT(1) BIT 468 include/linux/vmw_vmci_defs.h #define VMCI_FLAG_WELLKNOWN_DG_HND BIT(0) BIT 469 include/linux/vmw_vmci_defs.h #define VMCI_FLAG_ANYCID_DG_HND BIT(1) BIT 470 include/linux/vmw_vmci_defs.h #define VMCI_FLAG_DG_DELAYED_CB BIT(2) BIT 699 include/linux/vmw_vmci_defs.h #define VMCI_FLAG_DELAYED_CB BIT(0) BIT 16 include/media/davinci/vpbe_venc.h #define VENC_END_OF_FRAME BIT(0) BIT 17 include/media/davinci/vpbe_venc.h #define VENC_FIRST_FIELD BIT(1) BIT 18 include/media/davinci/vpbe_venc.h #define VENC_SECOND_FIELD BIT(2) BIT 101 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_FMT_BT601 BIT(0) BIT 102 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_FMT_BT656 BIT(1) BIT 104 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_FMT_VIP2 BIT(2) BIT 108 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_RES_8BIT BIT(3) BIT 109 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_RES_10BIT BIT(4) BIT 113 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_VBIRAW_DISABLED BIT(5) BIT 114 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_VBIRAW_ENABLED BIT(6) BIT 118 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_ANCDATA_DISABLED BIT(7) BIT 119 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_ANCDATA_ENABLED BIT(8) BIT 123 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_TASKBIT_ZERO BIT(9) BIT 124 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_TASKBIT_ONE BIT(10) BIT 128 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_ACTIVE_COMPOSITE BIT(11) BIT 129 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_ACTIVE_HORIZONTAL BIT(12) BIT 133 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_VALID_NORMAL BIT(13) BIT 134 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_VALID_ANDACTIVE BIT(14) BIT 138 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_HRESETW_NORMAL BIT(15) BIT 139 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_HRESETW_PIXCLK BIT(16) BIT 143 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_CLKGATE_NONE BIT(17) BIT 144 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_CLKGATE_VALID BIT(18) BIT 149 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_DCMODE_DWORDS BIT(19) BIT 150 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_DCMODE_BYTES BIT(20) BIT 154 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_IDID0S_NORMAL BIT(21) BIT 155 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_IDID0S_LINECNT BIT(22) BIT 159 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_VIPCLAMP_ENABLED BIT(23) BIT 160 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_VIPCLAMP_DISABLED BIT(24) BIT 145 include/media/dvb_frontend.h DVBFE_ALGO_HW = BIT(0), BIT 146 include/media/dvb_frontend.h DVBFE_ALGO_SW = BIT(1), BIT 147 include/media/dvb_frontend.h DVBFE_ALGO_CUSTOM = BIT(2), BIT 148 include/media/dvb_frontend.h DVBFE_ALGO_RECOVERY = BIT(31), BIT 174 include/media/dvb_frontend.h DVBFE_ALGO_SEARCH_SUCCESS = BIT(0), BIT 175 include/media/dvb_frontend.h DVBFE_ALGO_SEARCH_ASLEEP = BIT(1), BIT 176 include/media/dvb_frontend.h DVBFE_ALGO_SEARCH_FAILED = BIT(2), BIT 177 include/media/dvb_frontend.h DVBFE_ALGO_SEARCH_INVALID = BIT(3), BIT 178 include/media/dvb_frontend.h DVBFE_ALGO_SEARCH_AGAIN = BIT(4), BIT 179 include/media/dvb_frontend.h DVBFE_ALGO_SEARCH_ERROR = BIT(31), BIT 22 include/media/i2c/mt9t112.h #define MT9T112_FLAG_PCLK_RISING_EDGE BIT(0) BIT 316 include/media/soc_camera.h #define SOCAM_DATAWIDTH(x) BIT((x) - 1) BIT 21 include/media/v4l2-mediabus.h #define V4L2_MBUS_MASTER BIT(0) BIT 22 include/media/v4l2-mediabus.h #define V4L2_MBUS_SLAVE BIT(1) BIT 29 include/media/v4l2-mediabus.h #define V4L2_MBUS_HSYNC_ACTIVE_HIGH BIT(2) BIT 30 include/media/v4l2-mediabus.h #define V4L2_MBUS_HSYNC_ACTIVE_LOW BIT(3) BIT 31 include/media/v4l2-mediabus.h #define V4L2_MBUS_VSYNC_ACTIVE_HIGH BIT(4) BIT 32 include/media/v4l2-mediabus.h #define V4L2_MBUS_VSYNC_ACTIVE_LOW BIT(5) BIT 33 include/media/v4l2-mediabus.h #define V4L2_MBUS_PCLK_SAMPLE_RISING BIT(6) BIT 34 include/media/v4l2-mediabus.h #define V4L2_MBUS_PCLK_SAMPLE_FALLING BIT(7) BIT 35 include/media/v4l2-mediabus.h #define V4L2_MBUS_DATA_ACTIVE_HIGH BIT(8) BIT 36 include/media/v4l2-mediabus.h #define V4L2_MBUS_DATA_ACTIVE_LOW BIT(9) BIT 38 include/media/v4l2-mediabus.h #define V4L2_MBUS_FIELD_EVEN_HIGH BIT(10) BIT 40 include/media/v4l2-mediabus.h #define V4L2_MBUS_FIELD_EVEN_LOW BIT(11) BIT 42 include/media/v4l2-mediabus.h #define V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH BIT(12) BIT 43 include/media/v4l2-mediabus.h #define V4L2_MBUS_VIDEO_SOG_ACTIVE_LOW BIT(13) BIT 44 include/media/v4l2-mediabus.h #define V4L2_MBUS_DATA_ENABLE_HIGH BIT(14) BIT 45 include/media/v4l2-mediabus.h #define V4L2_MBUS_DATA_ENABLE_LOW BIT(15) BIT 49 include/media/v4l2-mediabus.h #define V4L2_MBUS_CSI2_1_LANE BIT(0) BIT 50 include/media/v4l2-mediabus.h #define V4L2_MBUS_CSI2_2_LANE BIT(1) BIT 51 include/media/v4l2-mediabus.h #define V4L2_MBUS_CSI2_3_LANE BIT(2) BIT 52 include/media/v4l2-mediabus.h #define V4L2_MBUS_CSI2_4_LANE BIT(3) BIT 54 include/media/v4l2-mediabus.h #define V4L2_MBUS_CSI2_CHANNEL_0 BIT(4) BIT 55 include/media/v4l2-mediabus.h #define V4L2_MBUS_CSI2_CHANNEL_1 BIT(5) BIT 56 include/media/v4l2-mediabus.h #define V4L2_MBUS_CSI2_CHANNEL_2 BIT(6) BIT 57 include/media/v4l2-mediabus.h #define V4L2_MBUS_CSI2_CHANNEL_3 BIT(7) BIT 59 include/media/v4l2-mediabus.h #define V4L2_MBUS_CSI2_CONTINUOUS_CLOCK BIT(8) BIT 60 include/media/v4l2-mediabus.h #define V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK BIT(9) BIT 322 include/media/v4l2-subdev.h V4L2_MBUS_FRAME_DESC_FL_LEN_MAX = BIT(0), BIT 323 include/media/v4l2-subdev.h V4L2_MBUS_FRAME_DESC_FL_BLOB = BIT(1), BIT 198 include/media/videobuf2-core.h VB2_MMAP = BIT(0), BIT 199 include/media/videobuf2-core.h VB2_USERPTR = BIT(1), BIT 200 include/media/videobuf2-core.h VB2_READ = BIT(2), BIT 201 include/media/videobuf2-core.h VB2_WRITE = BIT(3), BIT 202 include/media/videobuf2-core.h VB2_DMABUF = BIT(4), BIT 20 include/media/vsp1.h #define VSP1_DU_STATUS_COMPLETE BIT(0) BIT 21 include/media/vsp1.h #define VSP1_DU_STATUS_WRITEBACK BIT(1) BIT 306 include/net/bluetooth/bluetooth.h #define HCI_REQ_START BIT(0) BIT 307 include/net/bluetooth/bluetooth.h #define HCI_REQ_SKB BIT(1) BIT 1479 include/net/bluetooth/hci_core.h #define HCI_MGMT_VAR_LEN BIT(0) BIT 1480 include/net/bluetooth/hci_core.h #define HCI_MGMT_NO_HDEV BIT(1) BIT 1481 include/net/bluetooth/hci_core.h #define HCI_MGMT_UNTRUSTED BIT(2) BIT 1482 include/net/bluetooth/hci_core.h #define HCI_MGMT_UNCONFIGURED BIT(3) BIT 1503 include/net/bluetooth/hci_core.h #define DISCOV_TYPE_BREDR (BIT(BDADDR_BREDR)) BIT 1504 include/net/bluetooth/hci_core.h #define DISCOV_TYPE_LE (BIT(BDADDR_LE_PUBLIC) | \ BIT 1505 include/net/bluetooth/hci_core.h BIT(BDADDR_LE_RANDOM)) BIT 1506 include/net/bluetooth/hci_core.h #define DISCOV_TYPE_INTERLEAVED (BIT(BDADDR_BREDR) | \ BIT 1507 include/net/bluetooth/hci_core.h BIT(BDADDR_LE_PUBLIC) | \ BIT 1508 include/net/bluetooth/hci_core.h BIT(BDADDR_LE_RANDOM)) BIT 558 include/net/bluetooth/mgmt.h #define MGMT_ADV_FLAG_CONNECTABLE BIT(0) BIT 559 include/net/bluetooth/mgmt.h #define MGMT_ADV_FLAG_DISCOV BIT(1) BIT 560 include/net/bluetooth/mgmt.h #define MGMT_ADV_FLAG_LIMITED_DISCOV BIT(2) BIT 561 include/net/bluetooth/mgmt.h #define MGMT_ADV_FLAG_MANAGED_FLAGS BIT(3) BIT 562 include/net/bluetooth/mgmt.h #define MGMT_ADV_FLAG_TX_POWER BIT(4) BIT 563 include/net/bluetooth/mgmt.h #define MGMT_ADV_FLAG_APPEARANCE BIT(5) BIT 564 include/net/bluetooth/mgmt.h #define MGMT_ADV_FLAG_LOCAL_NAME BIT(6) BIT 565 include/net/bluetooth/mgmt.h #define MGMT_ADV_FLAG_SEC_1M BIT(7) BIT 566 include/net/bluetooth/mgmt.h #define MGMT_ADV_FLAG_SEC_2M BIT(8) BIT 567 include/net/bluetooth/mgmt.h #define MGMT_ADV_FLAG_SEC_CODED BIT(9) BIT 20 include/net/bond_options.h BOND_OPTFLAG_NOSLAVES = BIT(0), BIT 21 include/net/bond_options.h BOND_OPTFLAG_IFDOWN = BIT(1), BIT 22 include/net/bond_options.h BOND_OPTFLAG_RAWVAL = BIT(2) BIT 30 include/net/bond_options.h BOND_VALFLAG_DEFAULT = BIT(0), BIT 31 include/net/bond_options.h BOND_VALFLAG_MIN = BIT(1), BIT 32 include/net/bond_options.h BOND_VALFLAG_MAX = BIT(2) BIT 443 include/net/cfg80211.h if (data->types_mask & BIT(iftype)) BIT 777 include/net/cfg80211.h SURVEY_INFO_NOISE_DBM = BIT(0), BIT 778 include/net/cfg80211.h SURVEY_INFO_IN_USE = BIT(1), BIT 779 include/net/cfg80211.h SURVEY_INFO_TIME = BIT(2), BIT 780 include/net/cfg80211.h SURVEY_INFO_TIME_BUSY = BIT(3), BIT 781 include/net/cfg80211.h SURVEY_INFO_TIME_EXT_BUSY = BIT(4), BIT 782 include/net/cfg80211.h SURVEY_INFO_TIME_RX = BIT(5), BIT 783 include/net/cfg80211.h SURVEY_INFO_TIME_TX = BIT(6), BIT 784 include/net/cfg80211.h SURVEY_INFO_TIME_SCAN = BIT(7), BIT 785 include/net/cfg80211.h SURVEY_INFO_TIME_BSS_RX = BIT(8), BIT 955 include/net/cfg80211.h AP_SETTINGS_EXTERNAL_AUTH_SUPPORT = BIT(0), BIT 1086 include/net/cfg80211.h STATION_PARAM_APPLY_UAPSD = BIT(0), BIT 1087 include/net/cfg80211.h STATION_PARAM_APPLY_CAPABILITY = BIT(1), BIT 1088 include/net/cfg80211.h STATION_PARAM_APPLY_PLINK_STATE = BIT(2), BIT 1089 include/net/cfg80211.h STATION_PARAM_APPLY_STA_TXPOWER = BIT(3), BIT 1263 include/net/cfg80211.h RATE_INFO_FLAGS_MCS = BIT(0), BIT 1264 include/net/cfg80211.h RATE_INFO_FLAGS_VHT_MCS = BIT(1), BIT 1265 include/net/cfg80211.h RATE_INFO_FLAGS_SHORT_GI = BIT(2), BIT 1266 include/net/cfg80211.h RATE_INFO_FLAGS_DMG = BIT(3), BIT 1267 include/net/cfg80211.h RATE_INFO_FLAGS_HE_MCS = BIT(4), BIT 1268 include/net/cfg80211.h RATE_INFO_FLAGS_EDMG = BIT(5), BIT 1593 include/net/cfg80211.h MPATH_INFO_FRAME_QLEN = BIT(0), BIT 1594 include/net/cfg80211.h MPATH_INFO_SN = BIT(1), BIT 1595 include/net/cfg80211.h MPATH_INFO_METRIC = BIT(2), BIT 1596 include/net/cfg80211.h MPATH_INFO_EXPTIME = BIT(3), BIT 1597 include/net/cfg80211.h MPATH_INFO_DISCOVERY_TIMEOUT = BIT(4), BIT 1598 include/net/cfg80211.h MPATH_INFO_DISCOVERY_RETRIES = BIT(5), BIT 1599 include/net/cfg80211.h MPATH_INFO_FLAGS = BIT(6), BIT 1600 include/net/cfg80211.h MPATH_INFO_HOP_COUNT = BIT(7), BIT 1601 include/net/cfg80211.h MPATH_INFO_PATH_CHANGE = BIT(8), BIT 2297 include/net/cfg80211.h ASSOC_REQ_DISABLE_HT = BIT(0), BIT 2298 include/net/cfg80211.h ASSOC_REQ_DISABLE_VHT = BIT(1), BIT 2299 include/net/cfg80211.h ASSOC_REQ_USE_RRM = BIT(2), BIT 2300 include/net/cfg80211.h CONNECT_REQ_EXTERNAL_AUTH_SUPPORT = BIT(3), BIT 2574 include/net/cfg80211.h UPDATE_ASSOC_IES = BIT(0), BIT 2575 include/net/cfg80211.h UPDATE_FILS_ERP_INFO = BIT(1), BIT 2576 include/net/cfg80211.h UPDATE_AUTH_TYPE = BIT(2), BIT 2923 include/net/cfg80211.h CFG80211_NAN_CONF_CHANGED_PREF = BIT(0), BIT 2924 include/net/cfg80211.h CFG80211_NAN_CONF_CHANGED_BANDS = BIT(1), BIT 4004 include/net/cfg80211.h WIPHY_FLAG_NETNS_OK = BIT(3), BIT 4005 include/net/cfg80211.h WIPHY_FLAG_PS_ON_BY_DEFAULT = BIT(4), BIT 4006 include/net/cfg80211.h WIPHY_FLAG_4ADDR_AP = BIT(5), BIT 4007 include/net/cfg80211.h WIPHY_FLAG_4ADDR_STATION = BIT(6), BIT 4008 include/net/cfg80211.h WIPHY_FLAG_CONTROL_PORT_PROTOCOL = BIT(7), BIT 4009 include/net/cfg80211.h WIPHY_FLAG_IBSS_RSN = BIT(8), BIT 4010 include/net/cfg80211.h WIPHY_FLAG_MESH_AUTH = BIT(10), BIT 4013 include/net/cfg80211.h WIPHY_FLAG_SUPPORTS_FW_ROAM = BIT(13), BIT 4014 include/net/cfg80211.h WIPHY_FLAG_AP_UAPSD = BIT(14), BIT 4015 include/net/cfg80211.h WIPHY_FLAG_SUPPORTS_TDLS = BIT(15), BIT 4016 include/net/cfg80211.h WIPHY_FLAG_TDLS_EXTERNAL_SETUP = BIT(16), BIT 4017 include/net/cfg80211.h WIPHY_FLAG_HAVE_AP_SME = BIT(17), BIT 4018 include/net/cfg80211.h WIPHY_FLAG_REPORTS_OBSS = BIT(18), BIT 4019 include/net/cfg80211.h WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD = BIT(19), BIT 4020 include/net/cfg80211.h WIPHY_FLAG_OFFCHAN_TX = BIT(20), BIT 4021 include/net/cfg80211.h WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL = BIT(21), BIT 4022 include/net/cfg80211.h WIPHY_FLAG_SUPPORTS_5_10_MHZ = BIT(22), BIT 4023 include/net/cfg80211.h WIPHY_FLAG_HAS_CHANNEL_SWITCH = BIT(23), BIT 4024 include/net/cfg80211.h WIPHY_FLAG_HAS_STATIC_WEP = BIT(24), BIT 4176 include/net/cfg80211.h WIPHY_WOWLAN_ANY = BIT(0), BIT 4177 include/net/cfg80211.h WIPHY_WOWLAN_MAGIC_PKT = BIT(1), BIT 4178 include/net/cfg80211.h WIPHY_WOWLAN_DISCONNECT = BIT(2), BIT 4179 include/net/cfg80211.h WIPHY_WOWLAN_SUPPORTS_GTK_REKEY = BIT(3), BIT 4180 include/net/cfg80211.h WIPHY_WOWLAN_GTK_REKEY_FAILURE = BIT(4), BIT 4181 include/net/cfg80211.h WIPHY_WOWLAN_EAP_IDENTITY_REQ = BIT(5), BIT 4182 include/net/cfg80211.h WIPHY_WOWLAN_4WAY_HANDSHAKE = BIT(6), BIT 4183 include/net/cfg80211.h WIPHY_WOWLAN_RFKILL_RELEASE = BIT(7), BIT 4184 include/net/cfg80211.h WIPHY_WOWLAN_NET_DETECT = BIT(8), BIT 4247 include/net/cfg80211.h WIPHY_VENDOR_CMD_NEED_WDEV = BIT(0), BIT 4248 include/net/cfg80211.h WIPHY_VENDOR_CMD_NEED_NETDEV = BIT(1), BIT 4249 include/net/cfg80211.h WIPHY_VENDOR_CMD_NEED_RUNNING = BIT(2), BIT 4261 include/net/cfg80211.h STA_OPMODE_MAX_BW_CHANGED = BIT(0), BIT 4262 include/net/cfg80211.h STA_OPMODE_SMPS_MODE_CHANGED = BIT(1), BIT 4263 include/net/cfg80211.h STA_OPMODE_N_SS_CHANGED = BIT(2), BIT 7317 include/net/cfg80211.h *ft_byte |= BIT(ftidx % 8); BIT 7336 include/net/cfg80211.h return (ft_byte & BIT(ftidx % 8)) != 0; BIT 171 include/net/cfg802154.h WPAN_PHY_FLAG_TXPOWER = BIT(1), BIT 172 include/net/cfg802154.h WPAN_PHY_FLAG_CCA_ED_LEVEL = BIT(2), BIT 173 include/net/cfg802154.h WPAN_PHY_FLAG_CCA_MODE = BIT(3), BIT 532 include/net/devlink.h #define DEVLINK_TRAP_METADATA_TYPE_F_IN_PORT BIT(0) BIT 315 include/net/dsa.h mask |= BIT(p); BIT 21 include/net/flow_dissector.h #define FLOW_DIS_IS_FRAGMENT BIT(0) BIT 22 include/net/flow_dissector.h #define FLOW_DIS_FIRST_FRAG BIT(1) BIT 23 include/net/flow_dissector.h #define FLOW_DIS_ENCAPSULATION BIT(2) BIT 259 include/net/flow_dissector.h #define FLOW_DISSECTOR_F_PARSE_1ST_FRAG BIT(0) BIT 260 include/net/flow_dissector.h #define FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL BIT(1) BIT 261 include/net/flow_dissector.h #define FLOW_DISSECTOR_F_STOP_AT_ENCAP BIT(2) BIT 125 include/net/genetlink.h GENL_DONT_VALIDATE_STRICT = BIT(0), BIT 126 include/net/genetlink.h GENL_DONT_VALIDATE_DUMP = BIT(1), BIT 127 include/net/genetlink.h GENL_DONT_VALIDATE_DUMP_STRICT = BIT(2), BIT 257 include/net/ieee802154_netdev.h IEEE802154_LLSEC_PARAM_ENABLED = BIT(0), BIT 258 include/net/ieee802154_netdev.h IEEE802154_LLSEC_PARAM_FRAME_COUNTER = BIT(1), BIT 259 include/net/ieee802154_netdev.h IEEE802154_LLSEC_PARAM_OUT_LEVEL = BIT(2), BIT 260 include/net/ieee802154_netdev.h IEEE802154_LLSEC_PARAM_OUT_KEY = BIT(3), BIT 261 include/net/ieee802154_netdev.h IEEE802154_LLSEC_PARAM_KEY_SOURCE = BIT(4), BIT 262 include/net/ieee802154_netdev.h IEEE802154_LLSEC_PARAM_PAN_ID = BIT(5), BIT 263 include/net/ieee802154_netdev.h IEEE802154_LLSEC_PARAM_HWADDR = BIT(6), BIT 264 include/net/ieee802154_netdev.h IEEE802154_LLSEC_PARAM_COORD_HWADDR = BIT(7), BIT 265 include/net/ieee802154_netdev.h IEEE802154_LLSEC_PARAM_COORD_SHORTADDR = BIT(8), BIT 35 include/net/inet_frag.h INET_FRAG_FIRST_IN = BIT(0), BIT 36 include/net/inet_frag.h INET_FRAG_LAST_IN = BIT(1), BIT 37 include/net/inet_frag.h INET_FRAG_COMPLETE = BIT(2), BIT 38 include/net/inet_frag.h INET_FRAG_HASH_DEAD = BIT(3), BIT 245 include/net/inet_sock.h #define IP_CMSG_PKTINFO BIT(0) BIT 246 include/net/inet_sock.h #define IP_CMSG_TTL BIT(1) BIT 247 include/net/inet_sock.h #define IP_CMSG_TOS BIT(2) BIT 248 include/net/inet_sock.h #define IP_CMSG_RECVOPTS BIT(3) BIT 249 include/net/inet_sock.h #define IP_CMSG_RETOPTS BIT(4) BIT 250 include/net/inet_sock.h #define IP_CMSG_PASSSEC BIT(5) BIT 251 include/net/inet_sock.h #define IP_CMSG_ORIGDSTADDR BIT(6) BIT 252 include/net/inet_sock.h #define IP_CMSG_CHECKSUM BIT(7) BIT 253 include/net/inet_sock.h #define IP_CMSG_RECVFRAGSIZE BIT(8) BIT 48 include/net/ip.h #define IPSKB_FORWARDED BIT(0) BIT 49 include/net/ip.h #define IPSKB_XFRM_TUNNEL_SIZE BIT(1) BIT 50 include/net/ip.h #define IPSKB_XFRM_TRANSFORMED BIT(2) BIT 51 include/net/ip.h #define IPSKB_FRAG_COMPLETE BIT(3) BIT 52 include/net/ip.h #define IPSKB_REROUTED BIT(4) BIT 53 include/net/ip.h #define IPSKB_DOREDIRECT BIT(5) BIT 54 include/net/ip.h #define IPSKB_FRAG_PMTU BIT(6) BIT 55 include/net/ip.h #define IPSKB_L3SLAVE BIT(7) BIT 358 include/net/ip6_fib.h #define RT6_TABLE_HAS_DFLT_ROUTER BIT(0) BIT 15 include/net/lwtunnel.h #define LWTUNNEL_STATE_OUTPUT_REDIRECT BIT(0) BIT 16 include/net/lwtunnel.h #define LWTUNNEL_STATE_INPUT_REDIRECT BIT(1) BIT 17 include/net/lwtunnel.h #define LWTUNNEL_STATE_XMIT_REDIRECT BIT(2) BIT 138 include/net/mac80211.h IEEE80211_MAX_QUEUE_MAP = BIT(IEEE80211_MAX_QUEUES) - 1, BIT 201 include/net/mac80211.h IEEE80211_CHANCTX_CHANGE_WIDTH = BIT(0), BIT 202 include/net/mac80211.h IEEE80211_CHANCTX_CHANGE_RX_CHAINS = BIT(1), BIT 203 include/net/mac80211.h IEEE80211_CHANCTX_CHANGE_RADAR = BIT(2), BIT 204 include/net/mac80211.h IEEE80211_CHANCTX_CHANGE_CHANNEL = BIT(3), BIT 205 include/net/mac80211.h IEEE80211_CHANCTX_CHANGE_MIN_WIDTH = BIT(4), BIT 773 include/net/mac80211.h IEEE80211_TX_CTL_REQ_TX_STATUS = BIT(0), BIT 774 include/net/mac80211.h IEEE80211_TX_CTL_ASSIGN_SEQ = BIT(1), BIT 775 include/net/mac80211.h IEEE80211_TX_CTL_NO_ACK = BIT(2), BIT 776 include/net/mac80211.h IEEE80211_TX_CTL_CLEAR_PS_FILT = BIT(3), BIT 777 include/net/mac80211.h IEEE80211_TX_CTL_FIRST_FRAGMENT = BIT(4), BIT 778 include/net/mac80211.h IEEE80211_TX_CTL_SEND_AFTER_DTIM = BIT(5), BIT 779 include/net/mac80211.h IEEE80211_TX_CTL_AMPDU = BIT(6), BIT 780 include/net/mac80211.h IEEE80211_TX_CTL_INJECTED = BIT(7), BIT 781 include/net/mac80211.h IEEE80211_TX_STAT_TX_FILTERED = BIT(8), BIT 782 include/net/mac80211.h IEEE80211_TX_STAT_ACK = BIT(9), BIT 783 include/net/mac80211.h IEEE80211_TX_STAT_AMPDU = BIT(10), BIT 784 include/net/mac80211.h IEEE80211_TX_STAT_AMPDU_NO_BACK = BIT(11), BIT 785 include/net/mac80211.h IEEE80211_TX_CTL_RATE_CTRL_PROBE = BIT(12), BIT 786 include/net/mac80211.h IEEE80211_TX_INTFL_OFFCHAN_TX_OK = BIT(13), BIT 787 include/net/mac80211.h IEEE80211_TX_INTFL_NEED_TXPROCESSING = BIT(14), BIT 788 include/net/mac80211.h IEEE80211_TX_INTFL_RETRIED = BIT(15), BIT 789 include/net/mac80211.h IEEE80211_TX_INTFL_DONT_ENCRYPT = BIT(16), BIT 790 include/net/mac80211.h IEEE80211_TX_CTL_NO_PS_BUFFER = BIT(17), BIT 791 include/net/mac80211.h IEEE80211_TX_CTL_MORE_FRAMES = BIT(18), BIT 792 include/net/mac80211.h IEEE80211_TX_INTFL_RETRANSMISSION = BIT(19), BIT 793 include/net/mac80211.h IEEE80211_TX_INTFL_MLME_CONN_TX = BIT(20), BIT 794 include/net/mac80211.h IEEE80211_TX_INTFL_NL80211_FRAME_TX = BIT(21), BIT 795 include/net/mac80211.h IEEE80211_TX_CTL_LDPC = BIT(22), BIT 796 include/net/mac80211.h IEEE80211_TX_CTL_STBC = BIT(23) | BIT(24), BIT 797 include/net/mac80211.h IEEE80211_TX_CTL_TX_OFFCHAN = BIT(25), BIT 798 include/net/mac80211.h IEEE80211_TX_INTFL_TKIP_MIC_FAILURE = BIT(26), BIT 799 include/net/mac80211.h IEEE80211_TX_CTL_NO_CCK_RATE = BIT(27), BIT 800 include/net/mac80211.h IEEE80211_TX_STATUS_EOSP = BIT(28), BIT 801 include/net/mac80211.h IEEE80211_TX_CTL_USE_MINRATE = BIT(29), BIT 802 include/net/mac80211.h IEEE80211_TX_CTL_DONTFRAG = BIT(30), BIT 803 include/net/mac80211.h IEEE80211_TX_STAT_NOACK_TRANSMITTED = BIT(31), BIT 823 include/net/mac80211.h IEEE80211_TX_CTRL_PORT_CTRL_PROTO = BIT(0), BIT 824 include/net/mac80211.h IEEE80211_TX_CTRL_PS_RESPONSE = BIT(1), BIT 825 include/net/mac80211.h IEEE80211_TX_CTRL_RATE_INJECT = BIT(2), BIT 826 include/net/mac80211.h IEEE80211_TX_CTRL_AMSDU = BIT(3), BIT 827 include/net/mac80211.h IEEE80211_TX_CTRL_FAST_XMIT = BIT(4), BIT 828 include/net/mac80211.h IEEE80211_TX_CTRL_SKIP_MPATH_LOOKUP = BIT(5), BIT 870 include/net/mac80211.h IEEE80211_TX_RC_USE_RTS_CTS = BIT(0), BIT 871 include/net/mac80211.h IEEE80211_TX_RC_USE_CTS_PROTECT = BIT(1), BIT 872 include/net/mac80211.h IEEE80211_TX_RC_USE_SHORT_PREAMBLE = BIT(2), BIT 875 include/net/mac80211.h IEEE80211_TX_RC_MCS = BIT(3), BIT 876 include/net/mac80211.h IEEE80211_TX_RC_GREEN_FIELD = BIT(4), BIT 877 include/net/mac80211.h IEEE80211_TX_RC_40_MHZ_WIDTH = BIT(5), BIT 878 include/net/mac80211.h IEEE80211_TX_RC_DUP_DATA = BIT(6), BIT 879 include/net/mac80211.h IEEE80211_TX_RC_SHORT_GI = BIT(7), BIT 880 include/net/mac80211.h IEEE80211_TX_RC_VHT_MCS = BIT(8), BIT 881 include/net/mac80211.h IEEE80211_TX_RC_80_MHZ_WIDTH = BIT(9), BIT 882 include/net/mac80211.h IEEE80211_TX_RC_160_MHZ_WIDTH = BIT(10), BIT 1236 include/net/mac80211.h RX_FLAG_MMIC_ERROR = BIT(0), BIT 1237 include/net/mac80211.h RX_FLAG_DECRYPTED = BIT(1), BIT 1238 include/net/mac80211.h RX_FLAG_MACTIME_PLCP_START = BIT(2), BIT 1239 include/net/mac80211.h RX_FLAG_MMIC_STRIPPED = BIT(3), BIT 1240 include/net/mac80211.h RX_FLAG_IV_STRIPPED = BIT(4), BIT 1241 include/net/mac80211.h RX_FLAG_FAILED_FCS_CRC = BIT(5), BIT 1242 include/net/mac80211.h RX_FLAG_FAILED_PLCP_CRC = BIT(6), BIT 1243 include/net/mac80211.h RX_FLAG_MACTIME_START = BIT(7), BIT 1244 include/net/mac80211.h RX_FLAG_NO_SIGNAL_VAL = BIT(8), BIT 1245 include/net/mac80211.h RX_FLAG_AMPDU_DETAILS = BIT(9), BIT 1246 include/net/mac80211.h RX_FLAG_PN_VALIDATED = BIT(10), BIT 1247 include/net/mac80211.h RX_FLAG_DUP_VALIDATED = BIT(11), BIT 1248 include/net/mac80211.h RX_FLAG_AMPDU_LAST_KNOWN = BIT(12), BIT 1249 include/net/mac80211.h RX_FLAG_AMPDU_IS_LAST = BIT(13), BIT 1250 include/net/mac80211.h RX_FLAG_AMPDU_DELIM_CRC_ERROR = BIT(14), BIT 1251 include/net/mac80211.h RX_FLAG_AMPDU_DELIM_CRC_KNOWN = BIT(15), BIT 1252 include/net/mac80211.h RX_FLAG_MACTIME_END = BIT(16), BIT 1253 include/net/mac80211.h RX_FLAG_ONLY_MONITOR = BIT(17), BIT 1254 include/net/mac80211.h RX_FLAG_SKIP_MONITOR = BIT(18), BIT 1255 include/net/mac80211.h RX_FLAG_AMSDU_MORE = BIT(19), BIT 1256 include/net/mac80211.h RX_FLAG_RADIOTAP_VENDOR_DATA = BIT(20), BIT 1257 include/net/mac80211.h RX_FLAG_MIC_STRIPPED = BIT(21), BIT 1258 include/net/mac80211.h RX_FLAG_ALLOW_SAME_PN = BIT(22), BIT 1259 include/net/mac80211.h RX_FLAG_ICV_STRIPPED = BIT(23), BIT 1260 include/net/mac80211.h RX_FLAG_AMPDU_EOF_BIT = BIT(24), BIT 1261 include/net/mac80211.h RX_FLAG_AMPDU_EOF_BIT_KNOWN = BIT(25), BIT 1262 include/net/mac80211.h RX_FLAG_RADIOTAP_HE = BIT(26), BIT 1263 include/net/mac80211.h RX_FLAG_RADIOTAP_HE_MU = BIT(27), BIT 1264 include/net/mac80211.h RX_FLAG_RADIOTAP_LSIG = BIT(28), BIT 1265 include/net/mac80211.h RX_FLAG_NO_PSDU = BIT(29), BIT 1282 include/net/mac80211.h RX_ENC_FLAG_SHORTPRE = BIT(0), BIT 1283 include/net/mac80211.h RX_ENC_FLAG_SHORT_GI = BIT(2), BIT 1284 include/net/mac80211.h RX_ENC_FLAG_HT_GF = BIT(3), BIT 1285 include/net/mac80211.h RX_ENC_FLAG_STBC_MASK = BIT(4) | BIT(5), BIT 1286 include/net/mac80211.h RX_ENC_FLAG_LDPC = BIT(6), BIT 1287 include/net/mac80211.h RX_ENC_FLAG_BF = BIT(7), BIT 1441 include/net/mac80211.h IEEE80211_CONF_CHANGE_SMPS = BIT(1), BIT 1442 include/net/mac80211.h IEEE80211_CONF_CHANGE_LISTEN_INTERVAL = BIT(2), BIT 1443 include/net/mac80211.h IEEE80211_CONF_CHANGE_MONITOR = BIT(3), BIT 1444 include/net/mac80211.h IEEE80211_CONF_CHANGE_PS = BIT(4), BIT 1445 include/net/mac80211.h IEEE80211_CONF_CHANGE_POWER = BIT(5), BIT 1446 include/net/mac80211.h IEEE80211_CONF_CHANGE_CHANNEL = BIT(6), BIT 1447 include/net/mac80211.h IEEE80211_CONF_CHANGE_RETRY_LIMITS = BIT(7), BIT 1448 include/net/mac80211.h IEEE80211_CONF_CHANGE_IDLE = BIT(8), BIT 1565 include/net/mac80211.h IEEE80211_VIF_BEACON_FILTER = BIT(0), BIT 1566 include/net/mac80211.h IEEE80211_VIF_SUPPORTS_CQM_RSSI = BIT(1), BIT 1567 include/net/mac80211.h IEEE80211_VIF_SUPPORTS_UAPSD = BIT(2), BIT 1568 include/net/mac80211.h IEEE80211_VIF_GET_NOA_UPDATE = BIT(3), BIT 1718 include/net/mac80211.h IEEE80211_KEY_FLAG_GENERATE_IV_MGMT = BIT(0), BIT 1719 include/net/mac80211.h IEEE80211_KEY_FLAG_GENERATE_IV = BIT(1), BIT 1720 include/net/mac80211.h IEEE80211_KEY_FLAG_GENERATE_MMIC = BIT(2), BIT 1721 include/net/mac80211.h IEEE80211_KEY_FLAG_PAIRWISE = BIT(3), BIT 1722 include/net/mac80211.h IEEE80211_KEY_FLAG_SW_MGMT_TX = BIT(4), BIT 1723 include/net/mac80211.h IEEE80211_KEY_FLAG_PUT_IV_SPACE = BIT(5), BIT 1724 include/net/mac80211.h IEEE80211_KEY_FLAG_RX_MGMT = BIT(6), BIT 1725 include/net/mac80211.h IEEE80211_KEY_FLAG_RESERVE_TAILROOM = BIT(7), BIT 1726 include/net/mac80211.h IEEE80211_KEY_FLAG_PUT_MIC_SPACE = BIT(8), BIT 1727 include/net/mac80211.h IEEE80211_KEY_FLAG_NO_AUTO_TX = BIT(9), BIT 1728 include/net/mac80211.h IEEE80211_KEY_FLAG_GENERATE_MMIE = BIT(10), BIT 3175 include/net/mac80211.h IEEE80211_RC_BW_CHANGED = BIT(0), BIT 3176 include/net/mac80211.h IEEE80211_RC_SMPS_CHANGED = BIT(1), BIT 3177 include/net/mac80211.h IEEE80211_RC_SUPP_RATES_CHANGED = BIT(2), BIT 3178 include/net/mac80211.h IEEE80211_RC_NSS_CHANGED = BIT(3), BIT 4131 include/net/mac80211.h IEEE80211_TPT_LEDTRIG_FL_RADIO = BIT(0), BIT 4132 include/net/mac80211.h IEEE80211_TPT_LEDTRIG_FL_WORK = BIT(1), BIT 4133 include/net/mac80211.h IEEE80211_TPT_LEDTRIG_FL_CONNECTED = BIT(2), BIT 5233 include/net/mac80211.h IEEE80211_IFACE_ITER_RESUME_ALL = BIT(0), BIT 5234 include/net/mac80211.h IEEE80211_IFACE_ITER_ACTIVE = BIT(1), BIT 5930 include/net/mac80211.h RATE_CTRL_CAPA_VHT_EXT_NSS_BW = BIT(0), BIT 5971 include/net/mac80211.h return (sta == NULL || sta->supp_rates[band] & BIT(index)); BIT 35 include/net/mac802154.h IEEE802154_AFILT_SADDR_CHANGED = BIT(0), BIT 36 include/net/mac802154.h IEEE802154_AFILT_IEEEADDR_CHANGED = BIT(1), BIT 37 include/net/mac802154.h IEEE802154_AFILT_PANID_CHANGED = BIT(2), BIT 38 include/net/mac802154.h IEEE802154_AFILT_PANC_CHANGED = BIT(3), BIT 119 include/net/mac802154.h IEEE802154_HW_TX_OMIT_CKSUM = BIT(0), BIT 120 include/net/mac802154.h IEEE802154_HW_LBT = BIT(1), BIT 121 include/net/mac802154.h IEEE802154_HW_CSMA_PARAMS = BIT(2), BIT 122 include/net/mac802154.h IEEE802154_HW_FRAME_RETRIES = BIT(3), BIT 123 include/net/mac802154.h IEEE802154_HW_AFILT = BIT(4), BIT 124 include/net/mac802154.h IEEE802154_HW_PROMISCUOUS = BIT(5), BIT 125 include/net/mac802154.h IEEE802154_HW_RX_OMIT_CKSUM = BIT(6), BIT 126 include/net/mac802154.h IEEE802154_HW_RX_DROP_BAD_CKSUM = BIT(7), BIT 413 include/net/netlink.h NL_VALIDATE_TRAILING = BIT(0), BIT 414 include/net/netlink.h NL_VALIDATE_MAXTYPE = BIT(1), BIT 415 include/net/netlink.h NL_VALIDATE_UNSPEC = BIT(2), BIT 416 include/net/netlink.h NL_VALIDATE_STRICT_ATTRS = BIT(3), BIT 417 include/net/netlink.h NL_VALIDATE_NESTED = BIT(4), BIT 171 include/net/regulatory.h REGULATORY_CUSTOM_REG = BIT(0), BIT 172 include/net/regulatory.h REGULATORY_STRICT_REG = BIT(1), BIT 173 include/net/regulatory.h REGULATORY_DISABLE_BEACON_HINTS = BIT(2), BIT 174 include/net/regulatory.h REGULATORY_COUNTRY_IE_FOLLOW_POWER = BIT(3), BIT 175 include/net/regulatory.h REGULATORY_COUNTRY_IE_IGNORE = BIT(4), BIT 176 include/net/regulatory.h REGULATORY_ENABLE_RELAX_NO_IR = BIT(5), BIT 177 include/net/regulatory.h REGULATORY_IGNORE_STALE_KICKOFF = BIT(6), BIT 178 include/net/regulatory.h REGULATORY_WIPHY_SELF_MANAGED = BIT(7), BIT 15 include/net/switchdev.h #define SWITCHDEV_F_NO_RECURSE BIT(0) BIT 16 include/net/switchdev.h #define SWITCHDEV_F_SKIP_EOPNOTSUPP BIT(1) BIT 17 include/net/switchdev.h #define SWITCHDEV_F_DEFER BIT(2) BIT 27 include/net/tc_act/tc_ctinfo.h CTINFO_MODE_DSCP = BIT(0), BIT 28 include/net/tc_act/tc_ctinfo.h CTINFO_MODE_CPMARK = BIT(1) BIT 28 include/net/vxlan.h #define VXLAN_HF_VNI cpu_to_be32(BIT(27)) BIT 59 include/net/vxlan.h #define VXLAN_HF_RCO cpu_to_be32(BIT(21)) BIT 109 include/net/vxlan.h #define VXLAN_HF_GBP cpu_to_be32(BIT(31)) BIT 119 include/net/vxlan.h #define VXLAN_GBP_DONT_LEARN (BIT(6) << 16) BIT 120 include/net/vxlan.h #define VXLAN_GBP_POLICY_APPLIED (BIT(3) << 16) BIT 168 include/net/vxlan.h #define VXLAN_HF_VER cpu_to_be32(BIT(29) | BIT(28)) BIT 169 include/net/vxlan.h #define VXLAN_HF_NP cpu_to_be32(BIT(26)) BIT 170 include/net/vxlan.h #define VXLAN_HF_OAM cpu_to_be32(BIT(24)) BIT 65 include/rdma/ib_hdrs.h #define IB_BTH_REQ_ACK BIT(31) BIT 66 include/rdma/ib_hdrs.h #define IB_BTH_SOLICITED BIT(23) BIT 67 include/rdma/ib_hdrs.h #define IB_BTH_MIG_REQ BIT(22) BIT 79 include/rdma/ib_hdrs.h #define IB_FECN_SMASK BIT(IB_FECN_SHIFT) BIT 82 include/rdma/ib_hdrs.h #define IB_BECN_SMASK BIT(IB_BECN_SHIFT) BIT 308 include/rdma/ib_mad.h #define OPA_CLASS_PORT_INFO_PR_SUPPORT BIT(26) BIT 113 include/rdma/ib_sa.h #define IB_SA_CAP_MASK2_SENDONLY_FULL_MEM_SUPPORT BIT(12) BIT 3368 include/rdma/ib_verbs.h RDMA_CREATE_AH_SLEEPABLE = BIT(0), BIT 3473 include/rdma/ib_verbs.h RDMA_DESTROY_AH_SLEEPABLE = BIT(0), BIT 465 include/rdma/rdmavt_qp.h #define RVT_QPN_MAX BIT(24) BIT 14 include/soc/at91/atmel-secumod.h #define AT91_SECUMOD_RAMRDY_READY BIT(0) BIT 26 include/soc/at91/atmel-sfr.h #define AT91_SFR_CCFG_EBI_DBPUC BIT(8) BIT 27 include/soc/at91/atmel-sfr.h #define AT91_SFR_CCFG_EBI_DBPDC BIT(9) BIT 28 include/soc/at91/atmel-sfr.h #define AT91_SFR_CCFG_EBI_DRIVE BIT(17) BIT 29 include/soc/at91/atmel-sfr.h #define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24) BIT 30 include/soc/at91/atmel-sfr.h #define AT91_SFR_CCFG_DDR_MP_EN BIT(25) BIT 32 include/soc/at91/atmel-sfr.h #define AT91_SFR_OHCIICR_RES(x) BIT(x) BIT 33 include/soc/at91/atmel-sfr.h #define AT91_SFR_OHCIICR_ARIE BIT(4) BIT 34 include/soc/at91/atmel-sfr.h #define AT91_SFR_OHCIICR_APPSTART BIT(5) BIT 35 include/soc/at91/atmel-sfr.h #define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) BIT 36 include/soc/at91/atmel-sfr.h #define AT91_SFR_OHCIICR_UDPPUDIS BIT(23) BIT 39 include/soc/at91/atmel-sfr.h #define AT91_SFR_OHCIISR_RIS(x) BIT(x) BIT 43 include/soc/at91/atmel-sfr.h #define AT91_SFR_UTMISWAP_PORT(x) BIT(x) BIT 45 include/soc/at91/atmel-sfr.h #define AT91_SFR_LS_VALUE(x) BIT(x) BIT 46 include/soc/at91/atmel-sfr.h #define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16) BIT 48 include/soc/at91/atmel-sfr.h #define AT91_SFR_WPMR_WPEN BIT(0) BIT 179 include/soc/fsl/dpaa2-global.h #define DPAA2_CSCN_STATE_CG BIT(0) BIT 89 include/soc/fsl/qman.h #define QM_FD_FORMAT_SG BIT(31) BIT 90 include/soc/fsl/qman.h #define QM_FD_FORMAT_LONG BIT(30) BIT 91 include/soc/fsl/qman.h #define QM_FD_FORMAT_COMPOUND BIT(29) BIT 198 include/soc/fsl/qman.h #define QM_SG_FIN BIT(30) BIT 199 include/soc/fsl/qman.h #define QM_SG_EXT BIT(31) BIT 16 include/soc/mediatek/smi.h #define MTK_SMI_MMU_EN(port) BIT(port) BIT 85 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31) BIT 86 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30) BIT 87 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29) BIT 88 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_DIV4 BIT(28) BIT 89 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27) BIT 99 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15) BIT 100 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14) BIT 101 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13) BIT 102 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12) BIT 109 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18) BIT 110 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17) BIT 111 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_ROT_DIR BIT(16) BIT 112 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15) BIT 113 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14) BIT 117 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5) BIT 118 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_PWD_TX BIT(4) BIT 119 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_PWD_RX BIT(3) BIT 120 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2) BIT 121 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_HALF_RATE BIT(1) BIT 122 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0) BIT 124 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30) BIT 125 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29) BIT 126 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28) BIT 127 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27) BIT 128 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26) BIT 129 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25) BIT 130 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24) BIT 134 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15) BIT 135 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14) BIT 136 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13) BIT 137 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12) BIT 138 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11) BIT 139 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10) BIT 143 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4) BIT 144 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3) BIT 145 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2) BIT 146 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1) BIT 147 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0) BIT 155 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18) BIT 156 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17) BIT 157 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16) BIT 158 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15) BIT 159 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_RST_FB_N BIT(14) BIT 160 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13) BIT 161 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_FORCE_LO BIT(12) BIT 162 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_FORCE_HI BIT(11) BIT 163 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10) BIT 164 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_FORCE_CP BIT(9) BIT 165 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8) BIT 181 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23) BIT 185 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19) BIT 192 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7) BIT 193 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6) BIT 197 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12) BIT 198 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11) BIT 199 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10) BIT 200 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9) BIT 204 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0) BIT 218 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0) BIT 220 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31) BIT 221 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30) BIT 234 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2) BIT 235 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1) BIT 236 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0) BIT 244 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_PWD_ENA BIT(13) BIT 245 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_RUN_CAL BIT(12) BIT 252 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4) BIT 256 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_STATUS_BUSY BIT(12) BIT 257 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7) BIT 269 include/soc/mscc/ocelot_hsio.h #define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0) BIT 271 include/soc/mscc/ocelot_hsio.h #define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0) BIT 285 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4) BIT 289 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0) BIT 291 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27) BIT 298 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14) BIT 299 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13) BIT 300 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12) BIT 301 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11) BIT 302 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10) BIT 303 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9) BIT 322 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9) BIT 323 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8) BIT 330 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_IDLE BIT(9) BIT 331 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8) BIT 332 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7) BIT 333 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6) BIT 337 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3) BIT 338 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2) BIT 339 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1) BIT 340 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_ENALI BIT(0) BIT 342 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31) BIT 343 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21) BIT 344 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18) BIT 345 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17) BIT 346 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16) BIT 350 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12) BIT 351 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11) BIT 352 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10) BIT 353 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9) BIT 354 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8) BIT 355 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_HRATE BIT(7) BIT 356 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0) BIT 358 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22) BIT 359 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21) BIT 363 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7) BIT 364 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6) BIT 365 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5) BIT 366 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3) BIT 368 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12) BIT 369 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11) BIT 370 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10) BIT 374 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31) BIT 375 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23) BIT 382 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4) BIT 383 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3) BIT 384 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2) BIT 385 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0) BIT 393 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3) BIT 394 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2) BIT 395 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1) BIT 396 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0) BIT 404 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3) BIT 405 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2) BIT 406 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1) BIT 407 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0) BIT 409 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20) BIT 422 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10) BIT 423 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9) BIT 424 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8) BIT 425 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5) BIT 426 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4) BIT 427 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3) BIT 428 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2) BIT 429 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_LANE_RST BIT(0) BIT 431 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7) BIT 432 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6) BIT 433 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5) BIT 434 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3) BIT 435 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2) BIT 436 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1) BIT 437 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0) BIT 439 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0) BIT 441 include/soc/mscc/ocelot_hsio.h #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31) BIT 442 include/soc/mscc/ocelot_hsio.h #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30) BIT 449 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7) BIT 450 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6) BIT 457 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31) BIT 458 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23) BIT 465 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4) BIT 466 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3) BIT 467 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2) BIT 468 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0) BIT 476 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3) BIT 477 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2) BIT 478 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1) BIT 479 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0) BIT 487 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3) BIT 488 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2) BIT 489 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1) BIT 490 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0) BIT 492 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20) BIT 508 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10) BIT 509 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9) BIT 510 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8) BIT 511 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7) BIT 512 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6) BIT 513 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5) BIT 514 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4) BIT 515 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3) BIT 516 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2) BIT 517 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_LANE_RST BIT(0) BIT 534 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8) BIT 535 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7) BIT 536 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6) BIT 537 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5) BIT 538 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3) BIT 539 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2) BIT 540 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1) BIT 541 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0) BIT 543 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0) BIT 557 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4) BIT 561 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0) BIT 566 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28) BIT 591 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6) BIT 592 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5) BIT 593 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4) BIT 594 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3) BIT 595 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2) BIT 596 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1) BIT 597 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0) BIT 608 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7) BIT 609 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6) BIT 610 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5) BIT 611 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4) BIT 612 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3) BIT 613 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2) BIT 614 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1) BIT 615 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0) BIT 677 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_IDLE BIT(31) BIT 678 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30) BIT 679 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_POL BIT(29) BIT 686 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17) BIT 687 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16) BIT 691 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_R_COR BIT(10) BIT 692 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9) BIT 693 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_SR_H BIT(8) BIT 706 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8) BIT 707 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7) BIT 708 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6) BIT 712 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3) BIT 713 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2) BIT 714 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1) BIT 715 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_SER_CFG_SER_ENALI BIT(0) BIT 717 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17) BIT 718 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16) BIT 719 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15) BIT 720 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14) BIT 721 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13) BIT 722 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12) BIT 726 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8) BIT 727 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7) BIT 728 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6) BIT 729 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5) BIT 730 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4) BIT 731 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_HRATE BIT(3) BIT 732 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_QRATE BIT(2) BIT 739 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15) BIT 740 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14) BIT 744 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5) BIT 745 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4) BIT 746 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3) BIT 747 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2) BIT 748 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1) BIT 749 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0) BIT 751 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5) BIT 752 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4) BIT 753 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3) BIT 754 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2) BIT 755 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1) BIT 756 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0) BIT 764 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8) BIT 765 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7) BIT 766 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6) BIT 767 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5) BIT 768 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4) BIT 769 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3) BIT 770 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2) BIT 771 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1) BIT 772 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0) BIT 786 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2) BIT 787 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1) BIT 788 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0) BIT 790 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10) BIT 791 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9) BIT 792 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8) BIT 814 include/soc/mscc/ocelot_hsio.h #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31) BIT 815 include/soc/mscc/ocelot_hsio.h #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30) BIT 819 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6) BIT 820 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_CFG_DEV1G_9_MODE BIT(5) BIT 821 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_CFG_DEV1G_6_MODE BIT(4) BIT 822 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_CFG_DEV1G_5_MODE BIT(3) BIT 823 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_CFG_DEV1G_4_MODE BIT(2) BIT 824 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_CFG_PCIE_ENA BIT(1) BIT 825 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_CFG_QSGMII_ENA BIT(0) BIT 827 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3) BIT 828 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2) BIT 829 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1) BIT 830 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0) BIT 835 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_QSGMII_STAT_SYNC BIT(0) BIT 840 include/soc/mscc/ocelot_hsio.h #define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0) BIT 842 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5) BIT 843 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4) BIT 844 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3) BIT 845 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2) BIT 846 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1) BIT 847 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0) BIT 855 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8) BIT 54 include/sound/dmaengine_pcm.h #define SND_DMAENGINE_PCM_DAI_FLAG_PACK BIT(0) BIT 91 include/sound/dmaengine_pcm.h #define SND_DMAENGINE_PCM_FLAG_COMPAT BIT(0) BIT 96 include/sound/dmaengine_pcm.h #define SND_DMAENGINE_PCM_FLAG_NO_DT BIT(1) BIT 101 include/sound/dmaengine_pcm.h #define SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX BIT(3) BIT 286 include/sound/hda_register.h #define GTSCC_TSCCD_SHIFT BIT(31) BIT 740 include/sound/soc-dapm.h #define SND_SOC_DAPM_DIR_TO_EP(x) BIT(x) BIT 40 include/sound/sof/dai-intel.h #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0) BIT 42 include/sound/sof/dai-intel.h #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1) BIT 44 include/sound/sof/dai-intel.h #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2) BIT 46 include/sound/sof/dai-intel.h #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3) BIT 48 include/sound/sof/dai-intel.h #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4) BIT 50 include/sound/sof/dai-intel.h #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) BIT 24 include/sound/sof/info.h #define SOF_IPC_INFO_BUILD BIT(0) BIT 25 include/sound/sof/info.h #define SOF_IPC_INFO_LOCKS BIT(1) BIT 26 include/sound/sof/info.h #define SOF_IPC_INFO_LOCKSV BIT(2) BIT 27 include/sound/sof/info.h #define SOF_IPC_INFO_GDB BIT(3) BIT 103 include/uapi/linux/psci.h #define PSCI_1_0_OS_INITIATED BIT(0) BIT 12 include/vdso/datapage.h #define VDSO_HRES (BIT(CLOCK_REALTIME) | \ BIT 13 include/vdso/datapage.h BIT(CLOCK_MONOTONIC) | \ BIT 14 include/vdso/datapage.h BIT(CLOCK_BOOTTIME) | \ BIT 15 include/vdso/datapage.h BIT(CLOCK_TAI)) BIT 16 include/vdso/datapage.h #define VDSO_COARSE (BIT(CLOCK_REALTIME_COARSE) | \ BIT 17 include/vdso/datapage.h BIT(CLOCK_MONOTONIC_COARSE)) BIT 18 include/vdso/datapage.h #define VDSO_RAW (BIT(CLOCK_MONOTONIC_RAW)) BIT 15 include/video/display_timing.h DISPLAY_FLAGS_HSYNC_LOW = BIT(0), BIT 16 include/video/display_timing.h DISPLAY_FLAGS_HSYNC_HIGH = BIT(1), BIT 17 include/video/display_timing.h DISPLAY_FLAGS_VSYNC_LOW = BIT(2), BIT 18 include/video/display_timing.h DISPLAY_FLAGS_VSYNC_HIGH = BIT(3), BIT 21 include/video/display_timing.h DISPLAY_FLAGS_DE_LOW = BIT(4), BIT 22 include/video/display_timing.h DISPLAY_FLAGS_DE_HIGH = BIT(5), BIT 24 include/video/display_timing.h DISPLAY_FLAGS_PIXDATA_POSEDGE = BIT(6), BIT 26 include/video/display_timing.h DISPLAY_FLAGS_PIXDATA_NEGEDGE = BIT(7), BIT 27 include/video/display_timing.h DISPLAY_FLAGS_INTERLACED = BIT(8), BIT 28 include/video/display_timing.h DISPLAY_FLAGS_DOUBLESCAN = BIT(9), BIT 29 include/video/display_timing.h DISPLAY_FLAGS_DOUBLECLK = BIT(10), BIT 31 include/video/display_timing.h DISPLAY_FLAGS_SYNC_POSEDGE = BIT(11), BIT 33 include/video/display_timing.h DISPLAY_FLAGS_SYNC_NEGEDGE = BIT(12), BIT 82 include/video/sstfb.h # define PCI_EN_INIT_WR BIT(0) BIT 83 include/video/sstfb.h # define PCI_EN_FIFO_WR BIT(1) BIT 84 include/video/sstfb.h # define PCI_REMAP_DAC BIT(2) BIT 90 include/video/sstfb.h # define STATUS_FBI_BUSY BIT(7) BIT 92 include/video/sstfb.h # define EN_CLIPPING BIT(0) /* enable clipping */ BIT 93 include/video/sstfb.h # define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */ BIT 94 include/video/sstfb.h # define EN_ALPHA_WRITE BIT(10) BIT 95 include/video/sstfb.h # define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */ BIT 104 include/video/sstfb.h # define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/ BIT 105 include/video/sstfb.h # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */ BIT 106 include/video/sstfb.h # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */ BIT 107 include/video/sstfb.h # define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */ BIT 108 include/video/sstfb.h # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */ BIT 109 include/video/sstfb.h # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */ BIT 117 include/video/sstfb.h # define SLOW_PCI_READS BIT(0) /* 2 ws */ BIT 118 include/video/sstfb.h # define LFB_READ_AHEAD BIT(1) BIT 122 include/video/sstfb.h # define DIS_VGA_PASSTHROUGH BIT(0) BIT 123 include/video/sstfb.h # define FBI_RESET BIT(1) BIT 124 include/video/sstfb.h # define FIFO_RESET BIT(2) BIT 128 include/video/sstfb.h # define SLOW_PCI_WRITES BIT(1) /* 1 ws */ BIT 129 include/video/sstfb.h # define EN_LFB_READ BIT(3) BIT 131 include/video/sstfb.h # define VIDEO_RESET BIT(8) BIT 132 include/video/sstfb.h # define EN_BLANKING BIT(12) BIT 133 include/video/sstfb.h # define EN_DATA_OE BIT(13) BIT 134 include/video/sstfb.h # define EN_BLANK_OE BIT(14) BIT 135 include/video/sstfb.h # define EN_HVSYNC_OE BIT(15) BIT 136 include/video/sstfb.h # define EN_DCLK_OE BIT(16) BIT 138 include/video/sstfb.h # define SEL_INPUT_VCLK_SLAVE BIT(17) BIT 142 include/video/sstfb.h # define EN_24BPP BIT(22) BIT 147 include/video/sstfb.h # define EN_FAST_RAS_READ BIT(5) BIT 148 include/video/sstfb.h # define EN_DRAM_OE BIT(6) BIT 149 include/video/sstfb.h # define EN_FAST_RD_AHEAD_WR BIT(7) BIT 154 include/video/sstfb.h # define EN_RD_AHEAD_FIFO BIT(21) BIT 155 include/video/sstfb.h # define EN_DRAM_REFRESH BIT(22) BIT 159 include/video/sstfb.h # define DISABLE_TEXTURE BIT(6) BIT 164 include/video/sstfb.h # define DAC_READ_CMD BIT(11) /* set read dacreg mode */ BIT 167 include/video/sstfb.h # define HDOUBLESCAN BIT(20) BIT 168 include/video/sstfb.h # define VDOUBLESCAN BIT(21) BIT 169 include/video/sstfb.h # define HSYNC_HIGH BIT(23) BIT 170 include/video/sstfb.h # define VSYNC_HIGH BIT(24) BIT 171 include/video/sstfb.h # define INTERLACE BIT(26) BIT 197 include/video/sstfb.h # define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */ BIT 209 include/video/sstfb.h # define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */ BIT 210 include/video/sstfb.h # define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */ BIT 211 include/video/sstfb.h # define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */ BIT 216 include/video/sstfb.h # define DACREG_CC_CLKA BIT(7) /* clk A controlled by regs */ BIT 218 include/video/sstfb.h # define DACREG_CC_CLKB BIT(3) /* clk B controlled by regs */ BIT 236 include/video/sstfb.h # define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */ BIT 249 include/video/sstfb.h # define DACREG_ICS_CLK0 BIT(5) BIT 91 include/video/tdfx.h #define AUTOINC_DSTX BIT(10) BIT 92 include/video/tdfx.h #define AUTOINC_DSTY BIT(11) BIT 98 include/video/tdfx.h #define STATUS_RETRACE BIT(6) BIT 99 include/video/tdfx.h #define STATUS_BUSY BIT(9) BIT 100 include/video/tdfx.h #define MISCINIT1_CLUT_INV BIT(0) BIT 101 include/video/tdfx.h #define MISCINIT1_2DBLOCK_DIS BIT(15) BIT 102 include/video/tdfx.h #define DRAMINIT0_SGRAM_NUM BIT(26) BIT 103 include/video/tdfx.h #define DRAMINIT0_SGRAM_TYPE BIT(27) BIT 104 include/video/tdfx.h #define DRAMINIT0_SGRAM_TYPE_MASK (BIT(27) | BIT(28) | BIT(29)) BIT 106 include/video/tdfx.h #define DRAMINIT1_MEM_SDRAM BIT(30) BIT 107 include/video/tdfx.h #define VGAINIT0_VGA_DISABLE BIT(0) BIT 108 include/video/tdfx.h #define VGAINIT0_EXT_TIMING BIT(1) BIT 109 include/video/tdfx.h #define VGAINIT0_8BIT_DAC BIT(2) BIT 110 include/video/tdfx.h #define VGAINIT0_EXT_ENABLE BIT(6) BIT 111 include/video/tdfx.h #define VGAINIT0_WAKEUP_3C3 BIT(8) BIT 112 include/video/tdfx.h #define VGAINIT0_LEGACY_DISABLE BIT(9) BIT 113 include/video/tdfx.h #define VGAINIT0_ALT_READBACK BIT(10) BIT 114 include/video/tdfx.h #define VGAINIT0_FAST_BLINK BIT(11) BIT 115 include/video/tdfx.h #define VGAINIT0_EXTSHIFTOUT BIT(12) BIT 116 include/video/tdfx.h #define VGAINIT0_DECODE_3C6 BIT(13) BIT 117 include/video/tdfx.h #define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22) BIT 119 include/video/tdfx.h #define VIDCFG_VIDPROC_ENABLE BIT(0) BIT 120 include/video/tdfx.h #define VIDCFG_CURS_X11 BIT(1) BIT 121 include/video/tdfx.h #define VIDCFG_INTERLACE BIT(3) BIT 122 include/video/tdfx.h #define VIDCFG_HALF_MODE BIT(4) BIT 123 include/video/tdfx.h #define VIDCFG_DESK_ENABLE BIT(7) BIT 124 include/video/tdfx.h #define VIDCFG_CLUT_BYPASS BIT(10) BIT 125 include/video/tdfx.h #define VIDCFG_2X BIT(26) BIT 126 include/video/tdfx.h #define VIDCFG_HWCURSOR_ENABLE BIT(27) BIT 128 include/video/tdfx.h #define DACMODE_2X BIT(0) BIT 19 kernel/bpf/lpm_trie.c #define LPM_TREE_NODE_FLAG_IM BIT(0) BIT 404 kernel/cgroup/rdma.c *enables |= BIT(index); BIT 26 kernel/locking/test-ww_mutex.c #define TEST_MTX_SPIN BIT(0) BIT 27 kernel/locking/test-ww_mutex.c #define TEST_MTX_TRY BIT(1) BIT 28 kernel/locking/test-ww_mutex.c #define TEST_MTX_CTX BIT(2) BIT 29 kernel/locking/test-ww_mutex.c #define __TEST_MTX_LAST BIT(3) BIT 519 kernel/locking/test-ww_mutex.c #define STRESS_INORDER BIT(0) BIT 520 kernel/locking/test-ww_mutex.c #define STRESS_REORDER BIT(1) BIT 521 kernel/locking/test-ww_mutex.c #define STRESS_ONE BIT(2) BIT 109 kernel/printk/printk.c DEVKMSG_LOG_MASK_ON = BIT(__DEVKMSG_LOG_BIT_ON), BIT 110 kernel/printk/printk.c DEVKMSG_LOG_MASK_OFF = BIT(__DEVKMSG_LOG_BIT_OFF), BIT 111 kernel/printk/printk.c DEVKMSG_LOG_MASK_LOCK = BIT(__DEVKMSG_LOG_BIT_LOCK), BIT 3391 kernel/rcu/tree.c rnp->grpmask = BIT(rnp->grpnum); BIT 134 kernel/rcu/tree.h #define leaf_node_cpu_bit(rnp, cpu) (BIT((cpu) - (rnp)->grplo)) BIT 2210 kernel/sched/sched.h #define NOHZ_BALANCE_KICK BIT(NOHZ_BALANCE_KICK_BIT) BIT 2211 kernel/sched/sched.h #define NOHZ_STATS_KICK BIT(NOHZ_STATS_KICK_BIT) BIT 287 kernel/time/tick-sched.c prev = atomic_fetch_or(BIT(bit), dep); BIT 303 kernel/time/tick-sched.c atomic_andnot(BIT(bit), &tick_dep_mask); BIT 317 kernel/time/tick-sched.c prev = atomic_fetch_or(BIT(bit), &ts->tick_dep_mask); BIT 336 kernel/time/tick-sched.c atomic_andnot(BIT(bit), &ts->tick_dep_mask); BIT 354 kernel/time/tick-sched.c atomic_andnot(BIT(bit), &tsk->tick_dep_mask); BIT 368 kernel/time/tick-sched.c atomic_andnot(BIT(bit), &sig->tick_dep_mask); BIT 657 kernel/time/tick-sched.c return local_softirq_pending() & BIT(TIMER_SOFTIRQ); BIT 363 kernel/trace/trace_probe.h #define TPARG_FL_RETURN BIT(0) BIT 364 kernel/trace/trace_probe.h #define TPARG_FL_KERNEL BIT(1) BIT 365 kernel/trace/trace_probe.h #define TPARG_FL_FENTRY BIT(2) BIT 22 lib/math/prime_numbers.c BIT(2) | BIT 23 lib/math/prime_numbers.c BIT(3) | BIT 24 lib/math/prime_numbers.c BIT(5) | BIT 25 lib/math/prime_numbers.c BIT(7) | BIT 26 lib/math/prime_numbers.c BIT(11) | BIT 27 lib/math/prime_numbers.c BIT(13) | BIT 28 lib/math/prime_numbers.c BIT(17) | BIT 29 lib/math/prime_numbers.c BIT(19) | BIT 30 lib/math/prime_numbers.c BIT(23) | BIT 31 lib/math/prime_numbers.c BIT(29) | BIT 32 lib/math/prime_numbers.c BIT(31) | BIT 33 lib/math/prime_numbers.c BIT(37) | BIT 34 lib/math/prime_numbers.c BIT(41) | BIT 35 lib/math/prime_numbers.c BIT(43) | BIT 36 lib/math/prime_numbers.c BIT(47) | BIT 37 lib/math/prime_numbers.c BIT(53) | BIT 38 lib/math/prime_numbers.c BIT(59) | BIT 39 lib/math/prime_numbers.c BIT(61) BIT 47 lib/math/prime_numbers.c BIT(2) | BIT 48 lib/math/prime_numbers.c BIT(3) | BIT 49 lib/math/prime_numbers.c BIT(5) | BIT 50 lib/math/prime_numbers.c BIT(7) | BIT 51 lib/math/prime_numbers.c BIT(11) | BIT 52 lib/math/prime_numbers.c BIT(13) | BIT 53 lib/math/prime_numbers.c BIT(17) | BIT 54 lib/math/prime_numbers.c BIT(19) | BIT 55 lib/math/prime_numbers.c BIT(23) | BIT 56 lib/math/prime_numbers.c BIT(29) | BIT 57 lib/math/prime_numbers.c BIT(31) BIT 317 lib/sbitmap.c byte |= (word & (BIT(bits) - 1)) << byte_bits; BIT 52 lib/test_bpf.c #define FLAG_NO_DATA BIT(0) BIT 53 lib/test_bpf.c #define FLAG_EXPECTED_FAIL BIT(1) BIT 54 lib/test_bpf.c #define FLAG_SKB_FRAG BIT(2) BIT 57 lib/test_bpf.c CLASSIC = BIT(6), /* Old BPF instructions only. */ BIT 58 lib/test_bpf.c INTERNAL = BIT(7), /* Extended instruction set. */ BIT 46 lib/test_parman.c #define TEST_PARMAN_PRIO_COUNT BIT(TEST_PARMAN_PRIO_SHIFT) BIT 52 lib/test_parman.c #define TEST_PARMAN_ITEM_COUNT BIT(TEST_PARMAN_ITEM_SHIFT) BIT 56 lib/test_parman.c #define TEST_PARMAN_BASE_COUNT BIT(TEST_PARMAN_BASE_SHIFT) BIT 58 lib/test_parman.c #define TEST_PARMAN_RESIZE_STEP_COUNT BIT(TEST_PARMAN_RESIZE_STEP_SHIFT) BIT 61 lib/test_parman.c #define TEST_PARMAN_BULK_MAX_COUNT BIT(TEST_PARMAN_BULK_MAX_SHIFT) BIT 3793 mm/memcontrol.c #define LRU_ALL_FILE (BIT(LRU_INACTIVE_FILE) | BIT(LRU_ACTIVE_FILE)) BIT 3794 mm/memcontrol.c #define LRU_ALL_ANON (BIT(LRU_INACTIVE_ANON) | BIT(LRU_ACTIVE_ANON)) BIT 3807 mm/memcontrol.c if (!(BIT(lru) & lru_mask)) BIT 3821 mm/memcontrol.c if (!(BIT(lru) & lru_mask)) BIT 3839 mm/memcontrol.c { "unevictable", BIT(LRU_UNEVICTABLE) }, BIT 1732 mm/zsmalloc.c free_obj |= BIT(HANDLE_PIN_BIT); BIT 2047 mm/zsmalloc.c new_obj |= BIT(HANDLE_PIN_BIT); BIT 358 net/batman-adv/bat_iv_ogm.c if (forw_packet->direct_link_flags & BIT(packet_num) && BIT 603 net/batman-adv/bat_iv_ogm.c new_direct_link_flag = BIT(forw_packet_aggr->num_packets); BIT 110 net/batman-adv/bat_v_elp.c if (!(sinfo.filled & BIT(NL80211_STA_INFO_EXPECTED_THROUGHPUT))) BIT 40 net/batman-adv/log.h BATADV_DBG_BATMAN = BIT(0), BIT 43 net/batman-adv/log.h BATADV_DBG_ROUTES = BIT(1), BIT 46 net/batman-adv/log.h BATADV_DBG_TT = BIT(2), BIT 49 net/batman-adv/log.h BATADV_DBG_BLA = BIT(3), BIT 52 net/batman-adv/log.h BATADV_DBG_DAT = BIT(4), BIT 55 net/batman-adv/log.h BATADV_DBG_NC = BIT(5), BIT 58 net/batman-adv/log.h BATADV_DBG_MCAST = BIT(6), BIT 61 net/batman-adv/log.h BATADV_DBG_TP_METER = BIT(7), BIT 71 net/batman-adv/netlink.c BATADV_FLAG_NEED_MESH = BIT(0), BIT 78 net/batman-adv/netlink.c BATADV_FLAG_NEED_HARDIF = BIT(1), BIT 85 net/batman-adv/netlink.c BATADV_FLAG_NEED_VLAN = BIT(2), BIT 98 net/batman-adv/types.h BATADV_FULL_DUPLEX = BIT(0), BIT 105 net/batman-adv/types.h BATADV_WARNING_DEFAULT = BIT(1), BIT 152 net/batman-adv/types.h BATADV_HARDIF_WIFI_WEXT_DIRECT = BIT(0), BIT 155 net/batman-adv/types.h BATADV_HARDIF_WIFI_CFG80211_DIRECT = BIT(1), BIT 160 net/batman-adv/types.h BATADV_HARDIF_WIFI_WEXT_INDIRECT = BIT(2), BIT 166 net/batman-adv/types.h BATADV_HARDIF_WIFI_CFG80211_INDIRECT = BIT(3), BIT 2446 net/batman-adv/types.h BATADV_TVLV_HANDLER_OGM_CIFNOTFND = BIT(1), BIT 2453 net/batman-adv/types.h BATADV_TVLV_HANDLER_OGM_CALLED = BIT(2), BIT 558 net/bluetooth/bnep/core.c u32 valid_flags = BIT(BNEP_SETUP_RESPONSE); BIT 676 net/bluetooth/bnep/core.c u32 valid_flags = BIT(BNEP_SETUP_RESPONSE); BIT 59 net/bluetooth/bnep/sock.c __u32 supp_feat = BIT(BNEP_SETUP_RESPONSE); BIT 334 net/bluetooth/cmtp/capi.c if (session->flags & BIT(CMTP_LOOPBACK)) { BIT 78 net/bluetooth/cmtp/core.c u32 valid_flags = BIT(CMTP_LOOPBACK); BIT 316 net/bluetooth/cmtp/core.c if (!(session->flags & BIT(CMTP_LOOPBACK))) BIT 332 net/bluetooth/cmtp/core.c u32 valid_flags = BIT(CMTP_LOOPBACK); BIT 392 net/bluetooth/cmtp/core.c if (!(session->flags & BIT(CMTP_LOOPBACK))) { BIT 1580 net/bluetooth/hci_core.c hdev->flags &= BIT(HCI_RAW); BIT 1772 net/bluetooth/hci_core.c hdev->flags &= BIT(HCI_RAW); BIT 2076 net/bluetooth/hci_core.c flags &= ~BIT(HCI_UP); BIT 2114 net/bluetooth/hci_core.c flags = hdev->flags & ~BIT(HCI_UP); BIT 932 net/bluetooth/hidp/core.c session->flags = req->flags & BIT(HIDP_BLUETOOTH_VENDOR_ID); BIT 1350 net/bluetooth/hidp/core.c u32 valid_flags = BIT(HIDP_VIRTUAL_CABLE_UNPLUG) | BIT 1351 net/bluetooth/hidp/core.c BIT(HIDP_BOOT_PROTOCOL_MODE); BIT 1394 net/bluetooth/hidp/core.c u32 valid_flags = BIT(HIDP_VIRTUAL_CABLE_UNPLUG); BIT 1404 net/bluetooth/hidp/core.c if (req->flags & BIT(HIDP_VIRTUAL_CABLE_UNPLUG)) BIT 6169 net/bluetooth/mgmt.c case BIT(BDADDR_BREDR): BIT 6176 net/bluetooth/mgmt.c case (BIT(BDADDR_LE_PUBLIC) | BIT(BDADDR_LE_RANDOM)): BIT 6205 net/bluetooth/mgmt.c case BIT(BDADDR_BREDR): BIT 6220 net/bluetooth/mgmt.c case (BIT(BDADDR_LE_PUBLIC) | BIT(BDADDR_LE_RANDOM)): BIT 245 net/bridge/br.c bool on = !!(bm->optval & BIT(opt_id)); BIT 38 net/bridge/br_private.h BR_GROUPFWD_STP = BIT(0), BIT 39 net/bridge/br_private.h BR_GROUPFWD_MACPAUSE = BIT(1), BIT 40 net/bridge/br_private.h BR_GROUPFWD_LACP = BIT(2), BIT 105 net/bridge/br_private.h BR_VLFLAG_PER_PORT_STATS = BIT(0), BIT 106 net/bridge/br_private.h BR_VLFLAG_ADDED_BY_SWITCHDEV = BIT(1), BIT 200 net/bridge/br_private.h #define MDB_PG_FLAGS_PERMANENT BIT(0) BIT 201 net/bridge/br_private.h #define MDB_PG_FLAGS_OFFLOAD BIT(1) BIT 202 net/bridge/br_private.h #define MDB_PG_FLAGS_FAST_LEAVE BIT(2) BIT 164 net/can/j1939/j1939-priv.h #define J1939_ECU_LOCAL_SRC BIT(0) BIT 165 net/can/j1939/j1939-priv.h #define J1939_ECU_LOCAL_DST BIT(1) BIT 292 net/can/j1939/j1939-priv.h #define J1939_SOCK_BOUND BIT(0) BIT 293 net/can/j1939/j1939-priv.h #define J1939_SOCK_CONNECTED BIT(1) BIT 294 net/can/j1939/j1939-priv.h #define J1939_SOCK_PROMISC BIT(2) BIT 295 net/can/j1939/j1939-priv.h #define J1939_SOCK_ERRQUEUE BIT(3) BIT 377 net/core/devlink.c #define DEVLINK_NL_FLAG_NEED_DEVLINK BIT(0) BIT 378 net/core/devlink.c #define DEVLINK_NL_FLAG_NEED_PORT BIT(1) BIT 379 net/core/devlink.c #define DEVLINK_NL_FLAG_NEED_SB BIT(2) BIT 385 net/core/devlink.c #define DEVLINK_NL_FLAG_NO_LOCK BIT(3) BIT 3383 net/core/devlink.c if (param->supported_cmodes == BIT(DEVLINK_PARAM_CMODE_DRIVERINIT)) BIT 2938 net/core/ethtool.c BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS); BIT 2953 net/core/ethtool.c BIT(FLOW_DISSECTOR_KEY_PORTS); BIT 2961 net/core/ethtool.c BIT(FLOW_DISSECTOR_KEY_IP); BIT 2990 net/core/ethtool.c BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS); BIT 3005 net/core/ethtool.c BIT(FLOW_DISSECTOR_KEY_PORTS); BIT 3013 net/core/ethtool.c BIT(FLOW_DISSECTOR_KEY_IP); BIT 3036 net/core/ethtool.c match->dissector.used_keys |= BIT(FLOW_DISSECTOR_KEY_BASIC); BIT 3069 net/core/ethtool.c BIT(FLOW_DISSECTOR_KEY_VLAN); BIT 3084 net/core/ethtool.c BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS); BIT 28 net/dsa/tag_gswip.c #define GSWIP_TX_CRCGEN_DIS BIT(7) BIT 40 net/dsa/tag_gswip.c #define GSWIP_TX_PORT_MAP_EN BIT(7) BIT 41 net/dsa/tag_gswip.c #define GSWIP_TX_PORT_MAP_SEL BIT(6) BIT 42 net/dsa/tag_gswip.c #define GSWIP_TX_LRN_DIS BIT(5) BIT 43 net/dsa/tag_gswip.c #define GSWIP_TX_CLASS_EN BIT(4) BIT 48 net/dsa/tag_gswip.c #define GSWIP_TX_DPID_EN BIT(0) BIT 76 net/dsa/tag_gswip.c gswip_tag[3] = BIT(dp->index + GSWIP_TX_PORT_MAP_SHIFT) & GSWIP_TX_PORT_MAP_MASK; BIT 89 net/dsa/tag_ksz.c #define KSZ8795_TAIL_TAG_OVERRIDE BIT(6) BIT 90 net/dsa/tag_ksz.c #define KSZ8795_TAIL_TAG_LOOKUP BIT(7) BIT 153 net/dsa/tag_ksz.c #define KSZ9477_TAIL_TAG_OVERRIDE BIT(9) BIT 154 net/dsa/tag_ksz.c #define KSZ9477_TAIL_TAG_LOOKUP BIT(10) BIT 172 net/dsa/tag_ksz.c *tag = BIT(dp->index); BIT 208 net/dsa/tag_ksz.c #define KSZ9893_TAIL_TAG_OVERRIDE BIT(5) BIT 209 net/dsa/tag_ksz.c #define KSZ9893_TAIL_TAG_LOOKUP BIT(6) BIT 227 net/dsa/tag_ksz.c *tag = BIT(dp->index); BIT 34 net/dsa/tag_lan9303.c # define LAN9303_TAG_TX_USE_ALR BIT(3) BIT 35 net/dsa/tag_lan9303.c # define LAN9303_TAG_TX_STP_OVERRIDE BIT(4) BIT 36 net/dsa/tag_lan9303.c # define LAN9303_TAG_RX_IGMP BIT(3) BIT 37 net/dsa/tag_lan9303.c # define LAN9303_TAG_RX_STP BIT(4) BIT 18 net/dsa/tag_mtk.c #define MTK_HDR_XMIT_SA_DIS BIT(6) BIT 19 net/dsa/tag_qca.c #define QCA_HDR_RECV_FRAME_IS_TAGGED BIT(3) BIT 28 net/dsa/tag_qca.c #define QCA_HDR_XMIT_FROM_CPU BIT(7) BIT 46 net/dsa/tag_qca.c QCA_HDR_XMIT_FROM_CPU | BIT(dp->index); BIT 844 net/ieee802154/nl-mac.c if ((frames & BIT(IEEE802154_FC_TYPE_MAC_CMD)) && BIT 855 net/ieee802154/nl-mac.c commands[7] >= BIT(IEEE802154_CMD_GTS_REQ + 1)) BIT 927 net/ieee802154/nl-mac.c if (key->key->frame_types & BIT(IEEE802154_FC_TYPE_MAC_CMD)) { BIT 930 net/ieee802154/nl802154.c !(rdev->wpan_phy.supported.iftypes & BIT(type))) BIT 979 net/ieee802154/nl802154.c !(rdev->wpan_phy.supported.channels[page] & BIT(channel))) BIT 1000 net/ieee802154/nl802154.c !(rdev->wpan_phy.supported.cca_modes & BIT(cca.mode))) BIT 1009 net/ieee802154/nl802154.c !(rdev->wpan_phy.supported.cca_opts & BIT(cca.opt))) BIT 1473 net/ieee802154/nl802154.c if (key->key->frame_types & BIT(NL802154_FRAME_CMD)) { BIT 1574 net/ieee802154/nl802154.c if (key.frame_types > BIT(NL802154_FRAME_MAX) || BIT 1575 net/ieee802154/nl802154.c ((key.frame_types & BIT(NL802154_FRAME_CMD)) && BIT 1587 net/ieee802154/nl802154.c commands[7] > BIT(NL802154_CMD_FRAME_MAX)) BIT 33 net/ipv4/fou.c #define FOU_F_REMCSUM_NOPARTIAL BIT(0) BIT 2821 net/ipv4/route.c metrics[RTAX_LOCK - 1] |= BIT(RTAX_MTU); BIT 39 net/ipv4/syncookies.c #define TS_OPT_SACK BIT(4) BIT 40 net/ipv4/syncookies.c #define TS_OPT_ECN BIT(5) BIT 44 net/ipv6/anycast.c #define IN6_ADDR_HSIZE BIT(IN6_ADDR_HSIZE_SHIFT) BIT 65 net/ipv6/calipso.c #define CALIPSO_CACHE_BUCKETS BIT(CALIPSO_CACHE_BUCKETBITS) BIT 140 net/mac80211/agg-rx.c if (ba_rx_bitmap & BIT(i)) BIT 1210 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_AUTHENTICATED) && BIT 1211 net/mac80211/cfg.c set & BIT(NL80211_STA_FLAG_AUTHENTICATED) && BIT 1218 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_ASSOCIATED) && BIT 1219 net/mac80211/cfg.c set & BIT(NL80211_STA_FLAG_ASSOCIATED) && BIT 1234 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_AUTHORIZED)) { BIT 1235 net/mac80211/cfg.c if (set & BIT(NL80211_STA_FLAG_AUTHORIZED)) BIT 1245 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_ASSOCIATED) && BIT 1246 net/mac80211/cfg.c !(set & BIT(NL80211_STA_FLAG_ASSOCIATED)) && BIT 1253 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_AUTHENTICATED) && BIT 1254 net/mac80211/cfg.c !(set & BIT(NL80211_STA_FLAG_AUTHENTICATED)) && BIT 1350 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_AUTHENTICATED)) BIT 1351 net/mac80211/cfg.c mask |= BIT(NL80211_STA_FLAG_ASSOCIATED); BIT 1352 net/mac80211/cfg.c if (set & BIT(NL80211_STA_FLAG_AUTHENTICATED)) BIT 1353 net/mac80211/cfg.c set |= BIT(NL80211_STA_FLAG_ASSOCIATED); BIT 1360 net/mac80211/cfg.c if (set & BIT(NL80211_STA_FLAG_AUTHORIZED)) { BIT 1361 net/mac80211/cfg.c set |= BIT(NL80211_STA_FLAG_AUTHENTICATED) | BIT 1362 net/mac80211/cfg.c BIT(NL80211_STA_FLAG_ASSOCIATED); BIT 1363 net/mac80211/cfg.c mask |= BIT(NL80211_STA_FLAG_AUTHENTICATED) | BIT 1364 net/mac80211/cfg.c BIT(NL80211_STA_FLAG_ASSOCIATED); BIT 1368 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_WME) && BIT 1370 net/mac80211/cfg.c sta->sta.wme = set & BIT(NL80211_STA_FLAG_WME); BIT 1375 net/mac80211/cfg.c !((mask & BIT(NL80211_STA_FLAG_ASSOCIATED)) && BIT 1376 net/mac80211/cfg.c (set & BIT(NL80211_STA_FLAG_ASSOCIATED)))) { BIT 1382 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_SHORT_PREAMBLE)) { BIT 1383 net/mac80211/cfg.c if (set & BIT(NL80211_STA_FLAG_SHORT_PREAMBLE)) BIT 1389 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_MFP)) { BIT 1390 net/mac80211/cfg.c sta->sta.mfp = !!(set & BIT(NL80211_STA_FLAG_MFP)); BIT 1391 net/mac80211/cfg.c if (set & BIT(NL80211_STA_FLAG_MFP)) BIT 1397 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_TDLS_PEER)) { BIT 1398 net/mac80211/cfg.c if (set & BIT(NL80211_STA_FLAG_TDLS_PEER)) BIT 1518 net/mac80211/cfg.c set & BIT(NL80211_STA_FLAG_ASSOCIATED)) { BIT 1551 net/mac80211/cfg.c if (params->sta_flags_set & BIT(NL80211_STA_FLAG_TDLS_PEER) && BIT 1560 net/mac80211/cfg.c if (params->sta_flags_set & BIT(NL80211_STA_FLAG_TDLS_PEER)) BIT 1709 net/mac80211/cfg.c params->sta_flags_mask & BIT(NL80211_STA_FLAG_AUTHORIZED)) { BIT 3716 net/mac80211/cfg.c if (!(sdata->wmm_acm & BIT(up))) BIT 3846 net/mac80211/cfg.c if (!(txqstats->filled & BIT(NL80211_TXQ_STATS_BACKLOG_BYTES))) { BIT 3847 net/mac80211/cfg.c txqstats->filled |= BIT(NL80211_TXQ_STATS_BACKLOG_BYTES); BIT 3851 net/mac80211/cfg.c if (!(txqstats->filled & BIT(NL80211_TXQ_STATS_BACKLOG_PACKETS))) { BIT 3852 net/mac80211/cfg.c txqstats->filled |= BIT(NL80211_TXQ_STATS_BACKLOG_PACKETS); BIT 3856 net/mac80211/cfg.c if (!(txqstats->filled & BIT(NL80211_TXQ_STATS_FLOWS))) { BIT 3857 net/mac80211/cfg.c txqstats->filled |= BIT(NL80211_TXQ_STATS_FLOWS); BIT 3861 net/mac80211/cfg.c if (!(txqstats->filled & BIT(NL80211_TXQ_STATS_DROPS))) { BIT 3862 net/mac80211/cfg.c txqstats->filled |= BIT(NL80211_TXQ_STATS_DROPS); BIT 3866 net/mac80211/cfg.c if (!(txqstats->filled & BIT(NL80211_TXQ_STATS_ECN_MARKS))) { BIT 3867 net/mac80211/cfg.c txqstats->filled |= BIT(NL80211_TXQ_STATS_ECN_MARKS); BIT 3871 net/mac80211/cfg.c if (!(txqstats->filled & BIT(NL80211_TXQ_STATS_OVERLIMIT))) { BIT 3872 net/mac80211/cfg.c txqstats->filled |= BIT(NL80211_TXQ_STATS_OVERLIMIT); BIT 3876 net/mac80211/cfg.c if (!(txqstats->filled & BIT(NL80211_TXQ_STATS_COLLISIONS))) { BIT 3877 net/mac80211/cfg.c txqstats->filled |= BIT(NL80211_TXQ_STATS_COLLISIONS); BIT 3881 net/mac80211/cfg.c if (!(txqstats->filled & BIT(NL80211_TXQ_STATS_TX_BYTES))) { BIT 3882 net/mac80211/cfg.c txqstats->filled |= BIT(NL80211_TXQ_STATS_TX_BYTES); BIT 3886 net/mac80211/cfg.c if (!(txqstats->filled & BIT(NL80211_TXQ_STATS_TX_PACKETS))) { BIT 3887 net/mac80211/cfg.c txqstats->filled |= BIT(NL80211_TXQ_STATS_TX_PACKETS); BIT 3915 net/mac80211/cfg.c txqstats->filled |= BIT(NL80211_TXQ_STATS_BACKLOG_PACKETS) | BIT 3916 net/mac80211/cfg.c BIT(NL80211_TXQ_STATS_BACKLOG_BYTES) | BIT 3917 net/mac80211/cfg.c BIT(NL80211_TXQ_STATS_OVERLIMIT) | BIT 3918 net/mac80211/cfg.c BIT(NL80211_TXQ_STATS_OVERMEMORY) | BIT 3919 net/mac80211/cfg.c BIT(NL80211_TXQ_STATS_COLLISIONS) | BIT 3920 net/mac80211/cfg.c BIT(NL80211_TXQ_STATS_MAX_FLOWS); BIT 1576 net/mac80211/chan.c radar_detect_width = BIT(chandef->width); BIT 387 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(0)), "RX LDPC"); BIT 388 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(1)), "HT20/HT40"); BIT 389 net/mac80211/debugfs_sta.c PRINT_HT_CAP(!(htc->cap & BIT(1)), "HT20"); BIT 395 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(4)), "RX Greenfield"); BIT 396 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(5)), "RX HT20 SGI"); BIT 397 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(6)), "RX HT40 SGI"); BIT 398 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(7)), "TX STBC"); BIT 405 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(10)), "HT Delayed Block Ack"); BIT 407 net/mac80211/debugfs_sta.c PRINT_HT_CAP(!(htc->cap & BIT(11)), "Max AMSDU length: " BIT 409 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(11)), "Max AMSDU length: " BIT 418 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(12)), "DSSS/CCK HT40"); BIT 419 net/mac80211/debugfs_sta.c PRINT_HT_CAP(!(htc->cap & BIT(12)), "No DSSS/CCK HT40"); BIT 423 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(14)), "40 MHz Intolerant"); BIT 425 net/mac80211/debugfs_sta.c PRINT_HT_CAP((htc->cap & BIT(15)), "L-SIG TXOP protection"); BIT 107 net/mac80211/ibss.c rates |= BIT(i); BIT 117 net/mac80211/ibss.c if (!(rates & BIT(ri))) BIT 120 net/mac80211/ibss.c if (basic_rates & BIT(ri)) BIT 161 net/mac80211/ibss.c if (!(rates & BIT(ri))) BIT 164 net/mac80211/ibss.c if (basic_rates & BIT(ri)) BIT 464 net/mac80211/ibss.c basic_rates |= BIT(j); BIT 1777 net/mac80211/ibss.c radar_detect_width = BIT(params->chandef.width); BIT 1807 net/mac80211/ibss.c sdata->u.ibss.basic_rates &= ~BIT(i); BIT 139 net/mac80211/ieee80211_i.h IEEE80211_BSS_CORRUPT_BEACON = BIT(0), BIT 140 net/mac80211/ieee80211_i.h IEEE80211_BSS_CORRUPT_PROBE_RESP = BIT(1) BIT 155 net/mac80211/ieee80211_i.h IEEE80211_BSS_VALID_WMM = BIT(1), BIT 156 net/mac80211/ieee80211_i.h IEEE80211_BSS_VALID_RATES = BIT(2), BIT 157 net/mac80211/ieee80211_i.h IEEE80211_BSS_VALID_ERP = BIT(3) BIT 165 net/mac80211/ieee80211_i.h #define IEEE80211_TX_NO_SEQNO BIT(0) BIT 166 net/mac80211/ieee80211_i.h #define IEEE80211_TX_UNICAST BIT(1) BIT 167 net/mac80211/ieee80211_i.h #define IEEE80211_TX_PS_BUFFERED BIT(2) BIT 198 net/mac80211/ieee80211_i.h IEEE80211_RX_AMSDU = BIT(3), BIT 199 net/mac80211/ieee80211_i.h IEEE80211_RX_MALFORMED_ACTION_FRM = BIT(4), BIT 200 net/mac80211/ieee80211_i.h IEEE80211_RX_DEFERRED_RELEASE = BIT(5), BIT 214 net/mac80211/ieee80211_i.h IEEE80211_RX_CMNTR = BIT(0), BIT 215 net/mac80211/ieee80211_i.h IEEE80211_RX_BEACON_REPORTED = BIT(1), BIT 352 net/mac80211/ieee80211_i.h IEEE80211_STA_CONNECTION_POLL = BIT(1), BIT 353 net/mac80211/ieee80211_i.h IEEE80211_STA_CONTROL_PORT = BIT(2), BIT 354 net/mac80211/ieee80211_i.h IEEE80211_STA_DISABLE_HT = BIT(4), BIT 355 net/mac80211/ieee80211_i.h IEEE80211_STA_MFP_ENABLED = BIT(6), BIT 356 net/mac80211/ieee80211_i.h IEEE80211_STA_UAPSD_ENABLED = BIT(7), BIT 357 net/mac80211/ieee80211_i.h IEEE80211_STA_NULLFUNC_ACKED = BIT(8), BIT 358 net/mac80211/ieee80211_i.h IEEE80211_STA_RESET_SIGNAL_AVE = BIT(9), BIT 359 net/mac80211/ieee80211_i.h IEEE80211_STA_DISABLE_40MHZ = BIT(10), BIT 360 net/mac80211/ieee80211_i.h IEEE80211_STA_DISABLE_VHT = BIT(11), BIT 361 net/mac80211/ieee80211_i.h IEEE80211_STA_DISABLE_80P80MHZ = BIT(12), BIT 362 net/mac80211/ieee80211_i.h IEEE80211_STA_DISABLE_160MHZ = BIT(13), BIT 363 net/mac80211/ieee80211_i.h IEEE80211_STA_DISABLE_WMM = BIT(14), BIT 364 net/mac80211/ieee80211_i.h IEEE80211_STA_ENABLE_RRM = BIT(15), BIT 365 net/mac80211/ieee80211_i.h IEEE80211_STA_DISABLE_HE = BIT(16), BIT 746 net/mac80211/ieee80211_i.h IEEE80211_SDATA_ALLMULTI = BIT(0), BIT 747 net/mac80211/ieee80211_i.h IEEE80211_SDATA_OPERATING_GMODE = BIT(2), BIT 748 net/mac80211/ieee80211_i.h IEEE80211_SDATA_DONT_BRIDGE_PACKETS = BIT(3), BIT 749 net/mac80211/ieee80211_i.h IEEE80211_SDATA_DISCONNECT_RESUME = BIT(4), BIT 750 net/mac80211/ieee80211_i.h IEEE80211_SDATA_IN_DRIVER = BIT(5), BIT 2107 net/mac80211/ieee80211_i.h IEEE80211_PROBE_FLAG_DIRECTED = BIT(0), BIT 2108 net/mac80211/ieee80211_i.h IEEE80211_PROBE_FLAG_MIN_CONTENT = BIT(1), BIT 2109 net/mac80211/ieee80211_i.h IEEE80211_PROBE_FLAG_RANDOM_SN = BIT(2), BIT 35 net/mac80211/key.h KEY_FLAG_UPLOADED_TO_HARDWARE = BIT(0), BIT 36 net/mac80211/key.h KEY_FLAG_TAINTED = BIT(1), BIT 37 net/mac80211/key.h KEY_FLAG_CIPHER_SCHEME = BIT(2), BIT 412 net/mac80211/main.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 413 net/mac80211/main.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 414 net/mac80211/main.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 415 net/mac80211/main.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4), BIT 419 net/mac80211/main.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 420 net/mac80211/main.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4), BIT 424 net/mac80211/main.c .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 425 net/mac80211/main.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 426 net/mac80211/main.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 427 net/mac80211/main.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 428 net/mac80211/main.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 429 net/mac80211/main.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 430 net/mac80211/main.c BIT(IEEE80211_STYPE_ACTION >> 4), BIT 435 net/mac80211/main.c .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 436 net/mac80211/main.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 437 net/mac80211/main.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 438 net/mac80211/main.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 439 net/mac80211/main.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 440 net/mac80211/main.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 441 net/mac80211/main.c BIT(IEEE80211_STYPE_ACTION >> 4), BIT 445 net/mac80211/main.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 446 net/mac80211/main.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4), BIT 450 net/mac80211/main.c .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | BIT 451 net/mac80211/main.c BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | BIT 452 net/mac80211/main.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | BIT 453 net/mac80211/main.c BIT(IEEE80211_STYPE_DISASSOC >> 4) | BIT 454 net/mac80211/main.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 455 net/mac80211/main.c BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT 456 net/mac80211/main.c BIT(IEEE80211_STYPE_ACTION >> 4), BIT 460 net/mac80211/main.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 461 net/mac80211/main.c BIT(IEEE80211_STYPE_AUTH >> 4) | BIT 462 net/mac80211/main.c BIT(IEEE80211_STYPE_DEAUTH >> 4), BIT 466 net/mac80211/main.c .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | BIT 467 net/mac80211/main.c BIT(IEEE80211_STYPE_PROBE_REQ >> 4), BIT 888 net/mac80211/main.c BIT(NL80211_IFTYPE_NAN) && BIT 912 net/mac80211/main.c if (local->hw.wiphy->interface_modes & BIT(NL80211_IFTYPE_WDS)) BIT 995 net/mac80211/main.c if (local->hw.wiphy->interface_modes & BIT(NL80211_IFTYPE_AP) && BIT 997 net/mac80211/main.c hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP_VLAN); BIT 998 net/mac80211/main.c hw->wiphy->software_iftypes |= BIT(NL80211_IFTYPE_AP_VLAN); BIT 1002 net/mac80211/main.c hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_MONITOR); BIT 1003 net/mac80211/main.c hw->wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR); BIT 1013 net/mac80211/main.c if ((c->limits[j].types & BIT(NL80211_IFTYPE_ADHOC)) && BIT 1031 net/mac80211/main.c local->hw.wiphy->interface_modes &= ~BIT(NL80211_IFTYPE_MESH_POINT); BIT 1036 net/mac80211/main.c if (local->hw.wiphy->interface_modes & BIT(NL80211_IFTYPE_MESH_POINT)) BIT 1242 net/mac80211/main.c local->sband_allocated |= BIT(band); BIT 1255 net/mac80211/main.c if (local->hw.wiphy->interface_modes & BIT(NL80211_IFTYPE_STATION) && BIT 1387 net/mac80211/main.c if (!(local->sband_allocated & BIT(band))) BIT 1469 net/mac80211/mesh.c changed |= BIT(bit); BIT 37 net/mac80211/mesh.h MESH_PATH_ACTIVE = BIT(0), BIT 38 net/mac80211/mesh.h MESH_PATH_RESOLVING = BIT(1), BIT 39 net/mac80211/mesh.h MESH_PATH_SN_VALID = BIT(2), BIT 40 net/mac80211/mesh.h MESH_PATH_FIXED = BIT(3), BIT 41 net/mac80211/mesh.h MESH_PATH_RESOLVED = BIT(4), BIT 42 net/mac80211/mesh.h MESH_PATH_REQ_QUEUED = BIT(5), BIT 43 net/mac80211/mesh.h MESH_PATH_DELETED = BIT(6), BIT 116 net/mac80211/mesh_plink.c erp_rates |= BIT(i); BIT 686 net/mac80211/mlme.c rates |= BIT(i); BIT 769 net/mac80211/mlme.c if (BIT(i) & rates) { BIT 784 net/mac80211/mlme.c if (BIT(i) & rates) { BIT 1880 net/mac80211/mlme.c if (!(sdata->wmm_acm & BIT(7 - 2 * non_acm_ac))) BIT 1981 net/mac80211/mlme.c sdata->wmm_acm |= BIT(1) | BIT(2); /* BK/- */ BIT 1991 net/mac80211/mlme.c sdata->wmm_acm |= BIT(4) | BIT(5); /* CL/VI */ BIT 2001 net/mac80211/mlme.c sdata->wmm_acm |= BIT(6) | BIT(7); /* VO/NC */ BIT 2012 net/mac80211/mlme.c sdata->wmm_acm |= BIT(0) | BIT(3); /* BE/EE */ BIT 3144 net/mac80211/mlme.c *rates |= BIT(j); BIT 3146 net/mac80211/mlme.c *basic_rates |= BIT(j); BIT 3561 net/mac80211/mlme.c capab_info, status_code, (u16)(aid & ~(BIT(15) | BIT(14)))); BIT 4976 net/mac80211/mlme.c basic_rates = BIT(min_rate_index); BIT 337 net/mac80211/rate.c if (!(rate_mask & BIT(i))) BIT 439 net/mac80211/rate.c if (mcs_mask[i] & BIT(j)) { BIT 452 net/mac80211/rate.c if (mcs_mask[i] & BIT(j)) { BIT 475 net/mac80211/rate.c if (vht_mask[i] & BIT(j)) { BIT 489 net/mac80211/rate.c if (vht_mask[i] & BIT(j)) { BIT 611 net/mac80211/rate.c if (!(basic_rates & BIT(i))) BIT 737 net/mac80211/rate.c *mask &= ~BIT(i); BIT 255 net/mac80211/rc80211_minstrel_ht.c mask = BIT(9); BIT 258 net/mac80211/rc80211_minstrel_ht.c mask = BIT(6); BIT 260 net/mac80211/rc80211_minstrel_ht.c mask = BIT(9); BIT 321 net/mac80211/rc80211_minstrel_ht.c if ((mi->supported[group] & BIT(idx + 4)) && BIT 733 net/mac80211/rc80211_minstrel_ht.c if (!(mi->supported[group] & BIT(i))) BIT 1216 net/mac80211/rc80211_minstrel_ht.c if (!(mi->supported[sample_group] & BIT(sample_idx))) BIT 1373 net/mac80211/rc80211_minstrel_ht.c mi->cck_supported |= BIT(i); BIT 1375 net/mac80211/rc80211_minstrel_ht.c mi->cck_supported_short |= BIT(i); BIT 59 net/mac80211/rc80211_minstrel_ht_debugfs.c if (!(mi->supported[i] & BIT(j))) BIT 206 net/mac80211/rc80211_minstrel_ht_debugfs.c if (!(mi->supported[i] & BIT(j))) BIT 341 net/mac80211/rx.c it_present_val = BIT(IEEE80211_RADIOTAP_FLAGS) | BIT 342 net/mac80211/rx.c BIT(IEEE80211_RADIOTAP_CHANNEL) | BIT 343 net/mac80211/rx.c BIT(IEEE80211_RADIOTAP_RX_FLAGS); BIT 346 net/mac80211/rx.c it_present_val |= BIT(IEEE80211_RADIOTAP_ANTENNA); BIT 350 net/mac80211/rx.c BIT(IEEE80211_RADIOTAP_EXT) | BIT 351 net/mac80211/rx.c BIT(IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE); BIT 354 net/mac80211/rx.c it_present_val = BIT(IEEE80211_RADIOTAP_ANTENNA) | BIT 355 net/mac80211/rx.c BIT(IEEE80211_RADIOTAP_DBM_ANTSIGNAL); BIT 359 net/mac80211/rx.c it_present_val |= BIT(IEEE80211_RADIOTAP_VENDOR_NAMESPACE) | BIT 360 net/mac80211/rx.c BIT(IEEE80211_RADIOTAP_EXT); BIT 1801 net/mac80211/rx.c if (!(status->chains & BIT(i))) BIT 3863 net/mac80211/rx.c BIT(rate_idx)); BIT 3883 net/mac80211/rx.c BIT(rate_idx)); BIT 4248 net/mac80211/rx.c if (!(status->chains & BIT(i))) BIT 327 net/mac80211/scan.c bands_used |= BIT(req->channels[i]->band); BIT 345 net/mac80211/scan.c bands_used |= BIT(req->channels[i]->band); BIT 680 net/mac80211/scan.c if (bands_counted & BIT(req->channels[i]->band)) BIT 682 net/mac80211/scan.c bands_counted |= BIT(req->channels[i]->band); BIT 1253 net/mac80211/scan.c bands_used |= BIT(i); BIT 442 net/mac80211/sta_info.c sta->sta.supp_rates[i] |= BIT(r); BIT 748 net/mac80211/sta_info.c return BIT(6) | BIT(7); BIT 750 net/mac80211/sta_info.c return BIT(4) | BIT(5); BIT 752 net/mac80211/sta_info.c return BIT(0) | BIT(3); BIT 754 net/mac80211/sta_info.c return BIT(1) | BIT(2); BIT 797 net/mac80211/sta_info.c if (ignore_for_tim == BIT(IEEE80211_NUM_ACS) - 1) BIT 801 net/mac80211/sta_info.c ignore_for_tim = BIT(IEEE80211_NUM_ACS) - 1; BIT 1441 net/mac80211/sta_info.c drv_allow_buffered_frames(local, sta, BIT(tid), 1, BIT 1465 net/mac80211/sta_info.c if (tids & BIT(0)) BIT 1582 net/mac80211/sta_info.c BIT(find_highest_prio_tid(driver_release_tids)); BIT 1648 net/mac80211/sta_info.c tids |= BIT(skb->priority); BIT 1743 net/mac80211/sta_info.c !(driver_release_tids & BIT(tid)) || BIT 1762 net/mac80211/sta_info.c if (ignore_for_response == BIT(IEEE80211_NUM_ACS) - 1) BIT 2124 net/mac80211/sta_info.c if (!(tidstats->filled & BIT(NL80211_TID_STATS_RX_MSDU))) { BIT 2132 net/mac80211/sta_info.c tidstats->filled |= BIT(NL80211_TID_STATS_RX_MSDU); BIT 2135 net/mac80211/sta_info.c if (!(tidstats->filled & BIT(NL80211_TID_STATS_TX_MSDU))) { BIT 2136 net/mac80211/sta_info.c tidstats->filled |= BIT(NL80211_TID_STATS_TX_MSDU); BIT 2140 net/mac80211/sta_info.c if (!(tidstats->filled & BIT(NL80211_TID_STATS_TX_MSDU_RETRIES)) && BIT 2142 net/mac80211/sta_info.c tidstats->filled |= BIT(NL80211_TID_STATS_TX_MSDU_RETRIES); BIT 2146 net/mac80211/sta_info.c if (!(tidstats->filled & BIT(NL80211_TID_STATS_TX_MSDU_FAILED)) && BIT 2148 net/mac80211/sta_info.c tidstats->filled |= BIT(NL80211_TID_STATS_TX_MSDU_FAILED); BIT 2156 net/mac80211/sta_info.c tidstats->filled |= BIT(NL80211_TID_STATS_TXQ_STATS); BIT 2392 net/mac80211/sta_info.c sinfo->sta_flags.mask = BIT(NL80211_STA_FLAG_AUTHORIZED) | BIT 2393 net/mac80211/sta_info.c BIT(NL80211_STA_FLAG_SHORT_PREAMBLE) | BIT 2394 net/mac80211/sta_info.c BIT(NL80211_STA_FLAG_WME) | BIT 2395 net/mac80211/sta_info.c BIT(NL80211_STA_FLAG_MFP) | BIT 2396 net/mac80211/sta_info.c BIT(NL80211_STA_FLAG_AUTHENTICATED) | BIT 2397 net/mac80211/sta_info.c BIT(NL80211_STA_FLAG_ASSOCIATED) | BIT 2398 net/mac80211/sta_info.c BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 2400 net/mac80211/sta_info.c sinfo->sta_flags.set |= BIT(NL80211_STA_FLAG_AUTHORIZED); BIT 2402 net/mac80211/sta_info.c sinfo->sta_flags.set |= BIT(NL80211_STA_FLAG_SHORT_PREAMBLE); BIT 2404 net/mac80211/sta_info.c sinfo->sta_flags.set |= BIT(NL80211_STA_FLAG_WME); BIT 2406 net/mac80211/sta_info.c sinfo->sta_flags.set |= BIT(NL80211_STA_FLAG_MFP); BIT 2408 net/mac80211/sta_info.c sinfo->sta_flags.set |= BIT(NL80211_STA_FLAG_AUTHENTICATED); BIT 2410 net/mac80211/sta_info.c sinfo->sta_flags.set |= BIT(NL80211_STA_FLAG_ASSOCIATED); BIT 2412 net/mac80211/sta_info.c sinfo->sta_flags.set |= BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 129 net/mac80211/sta_info.h #define AIRTIME_USE_TX BIT(0) BIT 130 net/mac80211/sta_info.h #define AIRTIME_USE_RX BIT(1) BIT 150 net/mac80211/tx.c if (tx->sdata->vif.bss_conf.basic_rates & BIT(i)) BIT 1652 net/mac80211/tx.c ~BIT(IEEE80211_QUEUE_STOP_REASON_OFFCHANNEL)) { BIT 5013 net/mac80211/tx.c queues = BIT(sdata->vif.hw_queue[ieee802_1d_to_ac[tid]]); BIT 654 net/mac80211/util.c queues |= BIT(sdata->vif.hw_queue[ac]); BIT 656 net/mac80211/util.c queues |= BIT(sdata->vif.cab_queue); BIT 659 net/mac80211/util.c queues = BIT(local->hw.queues) - 1; BIT 1664 net/mac80211/util.c if ((BIT(i) & rate_mask) == 0) BIT 1846 net/mac80211/util.c if (bands_used & BIT(i)) { BIT 1911 net/mac80211/util.c ie, ie_len, BIT(chan->band), BIT 1970 net/mac80211/util.c supp_rates |= BIT(j); BIT 1972 net/mac80211/util.c *basic_rates |= BIT(j); BIT 3091 net/mac80211/util.c *rates |= BIT(j); BIT 3134 net/mac80211/util.c if (need_basic && basic_rates & BIT(i)) BIT 3183 net/mac80211/util.c if (need_basic && basic_rates & BIT(i)) BIT 3594 net/mac80211/util.c if (!cs || !(cs->iftype & BIT(iftype))) BIT 3707 net/mac80211/util.c u32 next_offset = BIT(31) - 1; BIT 3721 net/mac80211/util.c data->absent |= BIT(i); BIT 3824 net/mac80211/util.c radar_detect |= BIT(sdata->reserved_chandef.width); BIT 3835 net/mac80211/util.c radar_detect |= BIT(sdata->vif.bss_conf.chandef.width); BIT 89 net/mac80211/wme.c while (sdata->wmm_acm & BIT(skb->priority)) { BIT 262 net/mac80211/wme.c sdata->noack_map & BIT(tid)) { BIT 565 net/mac802154/llsec.c if (!(key_entry->key->frame_types & BIT(hdr->fc.type))) BIT 1019 net/mac802154/llsec.c if (!(seclevel.sec_levels & BIT(hdr.sec.level)) && BIT 112 net/mac802154/main.c phy->supported.iftypes = BIT(NL802154_IFTYPE_NODE); BIT 177 net/mac802154/main.c local->phy->supported.iftypes |= BIT(NL802154_IFTYPE_MONITOR); BIT 131 net/netfilter/nft_cmp.c flow->match.dissector.used_keys |= BIT(reg->key); BIT 83 net/netlink/genetlink.c static unsigned long mc_group_start = 0x3 | BIT(GENL_ID_CTRL) | BIT 84 net/netlink/genetlink.c BIT(GENL_ID_VFS_DQUOT) | BIT 85 net/netlink/genetlink.c BIT(GENL_ID_PMCRAID); BIT 37 net/nfc/digital_technology.c #define DIGITAL_SENSB_ADVANCED BIT(5) BIT 38 net/nfc/digital_technology.c #define DIGITAL_SENSB_EXTENDED BIT(4) BIT 39 net/nfc/digital_technology.c #define DIGITAL_SENSB_ALLB_REQ BIT(3) BIT 47 net/nfc/digital_technology.c #define DIGITAL_ATTRIB_P1_SUPRESS_EOS BIT(3) BIT 48 net/nfc/digital_technology.c #define DIGITAL_ATTRIB_P1_SUPRESS_SOS BIT(2) BIT 67 net/nfc/digital_technology.c #define DIGITAL_ISO15693_REQ_FLAG_DATA_RATE BIT(1) BIT 68 net/nfc/digital_technology.c #define DIGITAL_ISO15693_REQ_FLAG_INVENTORY BIT(2) BIT 69 net/nfc/digital_technology.c #define DIGITAL_ISO15693_REQ_FLAG_NB_SLOTS BIT(5) BIT 70 net/nfc/digital_technology.c #define DIGITAL_ISO15693_RES_FLAG_ERROR BIT(0) BIT 669 net/nfc/digital_technology.c if (!(sensb_res->proto_info[1] & BIT(0))) { BIT 675 net/nfc/digital_technology.c if (sensb_res->proto_info[1] & BIT(3)) { BIT 388 net/nfc/llcp_core.c if (local->local_wks & BIT(ssap)) { BIT 69 net/qrtr/qrtr.c #define QRTR_FLAGS_CONFIRM_RX BIT(0) BIT 29 net/rfkill/core.c #define RFKILL_BLOCK_HW BIT(0) BIT 30 net/rfkill/core.c #define RFKILL_BLOCK_SW BIT(1) BIT 31 net/rfkill/core.c #define RFKILL_BLOCK_SW_PREV BIT(2) BIT 35 net/rfkill/core.c #define RFKILL_BLOCK_SW_SETCALL BIT(31) BIT 302 net/rfkill/input.c .evbit = { BIT(EV_SW) }, BIT 260 net/sched/sch_cake.c CAKE_FLAG_OVERHEAD = BIT(0), BIT 261 net/sched/sch_cake.c CAKE_FLAG_AUTORATE_INGRESS = BIT(1), BIT 262 net/sched/sch_cake.c CAKE_FLAG_INGRESS = BIT(2), BIT 263 net/sched/sch_cake.c CAKE_FLAG_WASH = BIT(3), BIT 264 net/sched/sch_cake.c CAKE_FLAG_SPLIT_GSO = BIT(4) BIT 224 net/sched/sch_taprio.c if (!(entry->gate_mask & BIT(tc)) || BIT 476 net/sched/sch_taprio.c if (!(gate_mask & BIT(tc))) BIT 567 net/sched/sch_taprio.c if (!(gate_mask & BIT(tc))) { BIT 385 net/sunrpc/svc_xprt.c if (xpt_flags & (BIT(XPT_CONN) | BIT(XPT_CLOSE))) BIT 387 net/sunrpc/svc_xprt.c if (xpt_flags & (BIT(XPT_DATA) | BIT(XPT_DEFERRED))) { BIT 71 net/wireless/chan.c if (chandef->edmg.channels & BIT(i)) { BIT 457 net/wireless/chan.c return BIT(chandef->width); BIT 468 net/wireless/chan.c return BIT(chandef->width); BIT 842 net/wireless/chan.c if (!(edmg_channels & BIT(primary_channel - 1))) BIT 847 net/wireless/chan.c if (!(edmg_channels & BIT(i))) BIT 850 net/wireless/chan.c if (!(edmg_cap->channels & BIT(i))) BIT 1185 net/wireless/chan.c *radar_detect |= BIT(wdev->chandef.width); BIT 1202 net/wireless/chan.c *radar_detect |= BIT(wdev->chandef.width); BIT 1212 net/wireless/chan.c *radar_detect |= BIT(wdev->chandef.width); BIT 1225 net/wireless/chan.c *radar_detect |= BIT(wdev->chandef.width); BIT 600 net/wireless/core.c if (WARN_ON(types & BIT(NL80211_IFTYPE_P2P_DEVICE) && BIT 605 net/wireless/core.c if (WARN_ON(types & BIT(NL80211_IFTYPE_NAN) && BIT 619 net/wireless/core.c if (WARN_ON(types & BIT(NL80211_IFTYPE_ADHOC) && BIT 634 net/wireless/core.c if (WARN_ON(all_iftypes & BIT(NL80211_IFTYPE_WDS))) BIT 671 net/wireless/core.c if (WARN_ON((wiphy->interface_modes & BIT(NL80211_IFTYPE_NAN)) && BIT 674 net/wireless/core.c !(wiphy->nan_supported_bands & BIT(NL80211_BAND_2GHZ))))) BIT 678 net/wireless/core.c if (WARN_ON(wiphy->interface_modes & BIT(NL80211_IFTYPE_WDS))) BIT 693 net/wireless/core.c ~(BIT(NL80211_PREAMBLE_LEGACY) | BIT 694 net/wireless/core.c BIT(NL80211_PREAMBLE_HT) | BIT 695 net/wireless/core.c BIT(NL80211_PREAMBLE_VHT) | BIT 696 net/wireless/core.c BIT(NL80211_PREAMBLE_DMG)))) BIT 699 net/wireless/core.c ~(BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT 700 net/wireless/core.c BIT(NL80211_CHAN_WIDTH_20) | BIT 701 net/wireless/core.c BIT(NL80211_CHAN_WIDTH_40) | BIT 702 net/wireless/core.c BIT(NL80211_CHAN_WIDTH_80) | BIT 703 net/wireless/core.c BIT(NL80211_CHAN_WIDTH_80P80) | BIT 704 net/wireless/core.c BIT(NL80211_CHAN_WIDTH_160) | BIT 705 net/wireless/core.c BIT(NL80211_CHAN_WIDTH_5) | BIT 706 net/wireless/core.c BIT(NL80211_CHAN_WIDTH_10)))) BIT 714 net/wireless/core.c if (wiphy->interface_modes & ~(BIT(NL80211_IFTYPE_STATION) | BIT 715 net/wireless/core.c BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT 716 net/wireless/core.c BIT(NL80211_IFTYPE_AP) | BIT 717 net/wireless/core.c BIT(NL80211_IFTYPE_P2P_GO) | BIT 718 net/wireless/core.c BIT(NL80211_IFTYPE_ADHOC) | BIT 719 net/wireless/core.c BIT(NL80211_IFTYPE_P2P_DEVICE) | BIT 720 net/wireless/core.c BIT(NL80211_IFTYPE_NAN) | BIT 721 net/wireless/core.c BIT(NL80211_IFTYPE_AP_VLAN) | BIT 722 net/wireless/core.c BIT(NL80211_IFTYPE_MONITOR))) BIT 763 net/wireless/core.c (wiphy->bss_select_support & ~(BIT(__NL80211_BSS_SELECT_ATTR_AFTER_LAST) - 2)))) BIT 122 net/wireless/ibss.c params->basic_rates |= BIT(j); BIT 186 net/wireless/mesh.c setup->basic_rates = BIT(i); BIT 491 net/wireless/mlme.c if (!(wdev->wiphy->mgmt_stypes[wdev->iftype].rx & BIT(mgmt_type))) BIT 605 net/wireless/mlme.c if (!(wdev->wiphy->mgmt_stypes[wdev->iftype].tx & BIT(stype >> 4))) BIT 718 net/wireless/mlme.c if (!(stypes->rx & BIT(stype))) { BIT 999 net/wireless/nl80211.c if (txqstats->filled & BIT(NL80211_TXQ_STATS_ ## attr) && \ BIT 3450 net/wireless/nl80211.c if ((mumimo_groups[0] & BIT(0)) || BIT 3451 net/wireless/nl80211.c (mumimo_groups[VHT_MUMIMO_GROUPS_DATA_LEN - 1] & BIT(7))) BIT 4148 net/wireless/nl80211.c rbit = BIT(rates[i] % 8); BIT 4896 net/wireless/nl80211.c params->sta_flags_set) & BIT(__NL80211_STA_FLAG_INVALID)) BIT 4920 net/wireless/nl80211.c params->sta_flags_mask = BIT(NL80211_STA_FLAG_AUTHORIZED) | BIT 4921 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_SHORT_PREAMBLE) | BIT 4922 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_WME) | BIT 4923 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_MFP); BIT 4927 net/wireless/nl80211.c params->sta_flags_mask = BIT(NL80211_STA_FLAG_AUTHORIZED) | BIT 4928 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 4931 net/wireless/nl80211.c params->sta_flags_mask = BIT(NL80211_STA_FLAG_AUTHENTICATED) | BIT 4932 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_MFP) | BIT 4933 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_AUTHORIZED); BIT 5051 net/wireless/nl80211.c if (!(mask & BIT(i))) BIT 5236 net/wireless/nl80211.c if (tidstats->filled & BIT(NL80211_TID_STATS_ ## attr) && \ BIT 5249 net/wireless/nl80211.c BIT(NL80211_TID_STATS_TXQ_STATS)) && BIT 5382 net/wireless/nl80211.c !(params->sta_flags_set & BIT(NL80211_STA_FLAG_TDLS_PEER)) && BIT 5398 net/wireless/nl80211.c ~(BIT(NL80211_STA_FLAG_AUTHENTICATED) | BIT 5399 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_MFP) | BIT 5400 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_AUTHORIZED))) BIT 5405 net/wireless/nl80211.c if (!(params->sta_flags_set & BIT(NL80211_STA_FLAG_TDLS_PEER))) BIT 5408 net/wireless/nl80211.c params->sta_flags_mask &= ~BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 5423 net/wireless/nl80211.c if (params->sta_flags_set & BIT(NL80211_STA_FLAG_TDLS_PEER)) BIT 5430 net/wireless/nl80211.c params->sta_flags_mask &= ~BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 5456 net/wireless/nl80211.c if (!(params->sta_flags_mask & BIT(NL80211_STA_FLAG_AUTHORIZED))) BIT 5463 net/wireless/nl80211.c ~(BIT(NL80211_STA_FLAG_AUTHORIZED) | BIT 5464 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_AUTHENTICATED) | BIT 5465 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_ASSOCIATED) | BIT 5466 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_SHORT_PREAMBLE) | BIT 5467 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_WME) | BIT 5468 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_MFP))) BIT 5474 net/wireless/nl80211.c (BIT(NL80211_STA_FLAG_AUTHENTICATED) | BIT 5475 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_ASSOCIATED))) BIT 5481 net/wireless/nl80211.c if (params->sta_flags_mask & ~BIT(NL80211_STA_FLAG_AUTHORIZED)) BIT 5486 net/wireless/nl80211.c if (params->sta_flags_mask & ~(BIT(NL80211_STA_FLAG_AUTHORIZED) | BIT 5487 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_WME))) BIT 5490 net/wireless/nl80211.c if (params->sta_flags_set & BIT(NL80211_STA_FLAG_AUTHORIZED) && BIT 5834 net/wireless/nl80211.c u32 auth_assoc = BIT(NL80211_STA_FLAG_AUTHENTICATED) | BIT 5835 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_ASSOCIATED); BIT 5951 net/wireless/nl80211.c if (!(params.sta_flags_set & BIT(NL80211_STA_FLAG_WME))) { BIT 5969 net/wireless/nl80211.c !(params.sta_flags_set & BIT(NL80211_STA_FLAG_WME))) BIT 5973 net/wireless/nl80211.c if ((params.sta_flags_set & BIT(NL80211_STA_FLAG_TDLS_PEER)) || BIT 5977 net/wireless/nl80211.c params.sta_flags_mask &= ~BIT(NL80211_STA_FLAG_TDLS_PEER); BIT 6010 net/wireless/nl80211.c if (params.sta_flags_mask & BIT(NL80211_STA_FLAG_ASSOCIATED)) BIT 6013 net/wireless/nl80211.c if ((params.sta_flags_set & BIT(NL80211_STA_FLAG_TDLS_PEER)) || BIT 6024 net/wireless/nl80211.c (BIT(NL80211_STA_FLAG_ASSOCIATED) | BIT 6025 net/wireless/nl80211.c BIT(NL80211_STA_FLAG_AUTHENTICATED))) BIT 6028 net/wireless/nl80211.c if (!(params.sta_flags_set & BIT(NL80211_STA_FLAG_TDLS_PEER))) BIT 6040 net/wireless/nl80211.c params.sta_flags_mask &= ~BIT(NL80211_STA_FLAG_AUTHORIZED); BIT 6718 net/wireless/nl80211.c mask |= BIT((attr) - 1); \ BIT 6762 net/wireless/nl80211.c if (mask & BIT(NL80211_MESHCONF_PATH_REFRESH_TIME) && BIT 6772 net/wireless/nl80211.c if (mask & BIT(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT) && BIT 6824 net/wireless/nl80211.c if (mask & BIT(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT) && BIT 7357 net/wireless/nl80211.c if (!(wiphy->bss_select_support & BIT(bss_select->behaviour))) BIT 12250 net/wireless/nl80211.c if (bands && !(bands & BIT(NL80211_BAND_2GHZ))) BIT 12621 net/wireless/nl80211.c if (bands && !(bands & BIT(NL80211_BAND_2GHZ))) BIT 13701 net/wireless/nl80211.c do { if ((ftm_stats.filled & BIT(NL80211_FTM_STATS_ ## name)) && \ BIT 13706 net/wireless/nl80211.c do { if ((ftm_stats.filled & BIT(NL80211_FTM_STATS_ ## name)) && \ BIT 22 net/wireless/pmsr.c if (!(rdev->wiphy.pmsr_capa->ftm.bandwidths & BIT(out->chandef.width))) { BIT 49 net/wireless/pmsr.c if (!(capa->ftm.preambles & BIT(preamble))) { BIT 599 net/wireless/reg.c FWDB_FLAG_NO_OFDM = BIT(0), BIT 600 net/wireless/reg.c FWDB_FLAG_NO_OUTDOOR = BIT(1), BIT 601 net/wireless/reg.c FWDB_FLAG_DFS = BIT(2), BIT 602 net/wireless/reg.c FWDB_FLAG_NO_IR = BIT(3), BIT 603 net/wireless/reg.c FWDB_FLAG_AUTO_BW = BIT(4), BIT 35 net/wireless/util.c if (!(basic_rates & BIT(i))) BIT 70 net/wireless/util.c mandatory_rates |= BIT(i); BIT 1756 net/wireless/util.c used_iftypes |= BIT(iftype); BIT 1781 net/wireless/util.c if (!(limits[j].types & BIT(iftype))) BIT 1794 net/wireless/util.c !(c->radar_detect_regions & BIT(region))) BIT 1871 net/wireless/util.c *mask |= BIT(j); BIT 2141 net/wireless/util.c return wiphy->interface_modes & BIT(iftype); BIT 2143 net/wireless/util.c if (!(wiphy->software_iftypes & BIT(iftype)) && is_vlan) BIT 2145 net/wireless/util.c return wiphy->software_iftypes & BIT(iftype); BIT 213 scripts/asn1_compiler.c _(BIT), BIT 162 sound/ac97/bus.c if (!(ac97_ctrl->slots_available & BIT(i))) BIT 70 sound/core/pcm_drm_eld.c rate_mask |= BIT(i); BIT 92 sound/drivers/pcsp/pcsp_input.c input_dev->evbit[0] = BIT(EV_SND); BIT 93 sound/drivers/pcsp/pcsp_input.c input_dev->sndbit[0] = BIT(SND_BELL) | BIT(SND_TONE); BIT 31 sound/firewire/bebob/bebob_command.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 32 sound/firewire/bebob/bebob_command.c BIT(6) | BIT(7) | BIT(8)); BIT 69 sound/firewire/bebob/bebob_command.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 70 sound/firewire/bebob/bebob_command.c BIT(6) | BIT(8)); BIT 124 sound/firewire/bebob/bebob_command.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 125 sound/firewire/bebob/bebob_command.c BIT(6) | BIT(7) | BIT(9)); BIT 156 sound/firewire/bebob/bebob_command.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT 157 sound/firewire/bebob/bebob_command.c BIT(5) | BIT(6) | BIT(7) | BIT(9)); BIT 195 sound/firewire/bebob/bebob_command.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 196 sound/firewire/bebob/bebob_command.c BIT(6) | BIT(7) | BIT(9) | BIT(10)); BIT 231 sound/firewire/bebob/bebob_command.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 232 sound/firewire/bebob/bebob_command.c BIT(6) | BIT(7)); BIT 272 sound/firewire/bebob/bebob_command.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 273 sound/firewire/bebob/bebob_command.c BIT(6) | BIT(7) | BIT(10)); BIT 201 sound/firewire/bebob/bebob_maudio.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT 202 sound/firewire/bebob/bebob_maudio.c BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT 203 sound/firewire/bebob/bebob_maudio.c BIT(9)); BIT 48 sound/firewire/dice/dice-stream.c if (!(dice->clock_caps & BIT(i))) BIT 65 sound/firewire/fcp.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5)); BIT 110 sound/firewire/fcp.c BIT(1) | BIT(2) | BIT(3) | BIT(4)); BIT 160 sound/firewire/fcp.c err = fcp_avc_transaction(unit, buf, 8, buf, 8, BIT(1) | BIT(2)); BIT 102 sound/firewire/fireworks/fireworks.c if (hwinfo->flags & BIT(FLAG_RESP_ADDR_CHANGABLE)) BIT 34 sound/firewire/oxfw/oxfw-command.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 35 sound/firewire/oxfw/oxfw-command.c BIT(6) | BIT(7) | BIT(8)); BIT 79 sound/firewire/oxfw/oxfw-command.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT 80 sound/firewire/oxfw/oxfw-command.c BIT(6) | BIT(7)); BIT 144 sound/firewire/oxfw/oxfw-command.c BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5)); BIT 150 sound/firewire/tascam/tascam-stream.c data |= BIT(i); BIT 165 sound/firewire/tascam/tascam-stream.c data |= BIT(i); BIT 46 sound/mips/sgio2audio.c #define AUDIO_CONTROL_RESET BIT(0) /* 1: reset audio interface */ BIT 47 sound/mips/sgio2audio.c #define AUDIO_CONTROL_CODEC_PRESENT BIT(1) /* 1: codec detected */ BIT 50 sound/mips/sgio2audio.c #define CODEC_CONTROL_READ BIT(16) BIT 53 sound/mips/sgio2audio.c #define CHANNEL_CONTROL_RESET BIT(10) /* 1: reset channel */ BIT 54 sound/mips/sgio2audio.c #define CHANNEL_DMA_ENABLE BIT(9) /* 1: enable DMA transfer */ BIT 917 sound/pci/lx6464es/lx_core.c #define IRQCS_ACTIVE_PCIDB BIT(13) BIT 918 sound/pci/lx6464es/lx_core.c #define IRQCS_ENABLE_PCIIRQ BIT(8) BIT 919 sound/pci/lx6464es/lx_core.c #define IRQCS_ENABLE_PCIDB BIT(9) BIT 30 sound/soc/adi/axi-i2s.c #define AXI_I2S_RESET_GLOBAL BIT(0) BIT 31 sound/soc/adi/axi-i2s.c #define AXI_I2S_RESET_TX_FIFO BIT(1) BIT 32 sound/soc/adi/axi-i2s.c #define AXI_I2S_RESET_RX_FIFO BIT(2) BIT 34 sound/soc/adi/axi-i2s.c #define AXI_I2S_CTRL_TX_EN BIT(0) BIT 35 sound/soc/adi/axi-i2s.c #define AXI_I2S_CTRL_RX_EN BIT(1) BIT 27 sound/soc/adi/axi-spdif.c #define AXI_SPDIF_CTRL_TXDATA BIT(1) BIT 28 sound/soc/adi/axi-spdif.c #define AXI_SPDIF_CTRL_TXEN BIT(0) BIT 276 sound/soc/amd/acp-pcm-dma.c dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | BIT 284 sound/soc/amd/acp-pcm-dma.c dmadscr[i].xfer_val |= BIT(22) | BIT 322 sound/soc/amd/acp-pcm-dma.c high |= BIT(31); BIT 471 sound/soc/amd/acp-pcm-dma.c if (dma_ch_sts & BIT(ch_num)) { BIT 483 sound/soc/amd/acp-pcm-dma.c if (!(dma_ch_sts & BIT(ch_num))) { BIT 706 sound/soc/amd/acp-pcm-dma.c if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { BIT 709 sound/soc/amd/acp-pcm-dma.c acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, BIT 713 sound/soc/amd/acp-pcm-dma.c if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) { BIT 717 sound/soc/amd/acp-pcm-dma.c BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16, BIT 721 sound/soc/amd/acp-pcm-dma.c if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { BIT 733 sound/soc/amd/acp-pcm-dma.c acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, BIT 737 sound/soc/amd/acp-pcm-dma.c if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) { BIT 752 sound/soc/amd/acp-pcm-dma.c BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16, BIT 191 sound/soc/amd/raven/acp3x-pcm-dma.c if ((val & BIT(BT_TX_THRESHOLD)) && rv_i2s_data->play_stream) { BIT 192 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(BIT(BT_TX_THRESHOLD), rv_i2s_data->acp3x_base + BIT 198 sound/soc/amd/raven/acp3x-pcm-dma.c if ((val & BIT(BT_RX_THRESHOLD)) && rv_i2s_data->capture_stream) { BIT 199 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(BIT(BT_RX_THRESHOLD), rv_i2s_data->acp3x_base + BIT 224 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base + BIT 235 sound/soc/amd/raven/acp3x-pcm-dma.c high |= BIT(31); BIT 274 sound/soc/amd/raven/acp3x-pcm-dma.c rv_writel(BIT(BT_TX_THRESHOLD) | BIT(BT_RX_THRESHOLD), BIT 545 sound/soc/amd/raven/acp3x-pcm-dma.c val = val | BIT(0); BIT 551 sound/soc/amd/raven/acp3x-pcm-dma.c val = val | BIT(0); BIT 561 sound/soc/amd/raven/acp3x-pcm-dma.c val = val & ~BIT(0); BIT 565 sound/soc/amd/raven/acp3x-pcm-dma.c val = val & ~BIT(0); BIT 46 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_CR_RXEN BIT(0) /* Receiver Enable */ BIT 47 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */ BIT 48 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */ BIT 49 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */ BIT 50 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_CR_TXEN BIT(4) /* Transmitter Enable */ BIT 51 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_CR_TXDIS BIT(5) /* Transmitter Disable */ BIT 52 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_CR_SWRST BIT(7) /* Software Reset */ BIT 78 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_RXMONO BIT(8) BIT 86 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_RXLOOP BIT(10) BIT 89 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_TXMONO BIT(12) BIT 121 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_IWS BIT(31) BIT 126 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_SR_RXEN BIT(0) /* Receiver Enabled */ BIT 127 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_SR_RXRDY BIT(1) /* Receive Ready */ BIT 128 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_SR_RXOR BIT(2) /* Receive Overrun */ BIT 130 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_SR_TXEN BIT(4) /* Transmitter Enabled */ BIT 131 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_SR_TXRDY BIT(5) /* Transmit Ready */ BIT 132 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_SR_TXUR BIT(6) /* Transmit Underrun */ BIT 10 sound/soc/atmel/atmel-pdmic.h #define PDMIC_CR_SWRST_MASK BIT(0) BIT 15 sound/soc/atmel/atmel-pdmic.h #define PDMIC_CR_ENPDM_MASK BIT(4) BIT 22 sound/soc/atmel/atmel-pdmic.h #define PDMIC_MR_CLKS_MASK BIT(4) BIT 31 sound/soc/atmel/atmel-pdmic.h #define PDMIC_IER_OVRE BIT(25) BIT 34 sound/soc/atmel/atmel-pdmic.h #define PDMIC_IDR_OVRE BIT(25) BIT 39 sound/soc/atmel/atmel-pdmic.h #define PDMIC_ISR_OVRE BIT(25) BIT 45 sound/soc/atmel/atmel-pdmic.h #define PDMIC_DSPR0_HPFBYP_MASK BIT(1) BIT 50 sound/soc/atmel/atmel-pdmic.h #define PDMIC_DSPR0_SINBYP_MASK BIT(2) BIT 55 sound/soc/atmel/atmel-pdmic.h #define PDMIC_DSPR0_SIZE_MASK BIT(3) BIT 409 sound/soc/atmel/atmel_ssc_dai.c ssc_p->forced_divider |= BIT(ATMEL_SSC_CMR_DIV); BIT 414 sound/soc/atmel/atmel_ssc_dai.c ssc_p->forced_divider |= BIT(ATMEL_SSC_TCMR_PERIOD); BIT 419 sound/soc/atmel/atmel_ssc_dai.c ssc_p->forced_divider |= BIT(ATMEL_SSC_RCMR_PERIOD); BIT 486 sound/soc/atmel/atmel_ssc_dai.c if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_CMR_DIV)) && BIT 515 sound/soc/atmel/atmel_ssc_dai.c if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_TCMR_PERIOD))) BIT 517 sound/soc/atmel/atmel_ssc_dai.c if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_RCMR_PERIOD))) BIT 76 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_CR_RXEN BIT(0) /* Receiver Enable */ BIT 77 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_CR_RXDIS BIT(1) /* Receiver Disable */ BIT 78 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_CR_CKEN BIT(2) /* Clock Enable */ BIT 79 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_CR_CKDIS BIT(3) /* Clock Disable */ BIT 80 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_CR_TXEN BIT(4) /* Transmitter Enable */ BIT 81 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_CR_TXDIS BIT(5) /* Transmitter Disable */ BIT 82 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_CR_SWRST BIT(7) /* Software Reset */ BIT 115 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_RXMONO BIT(8) BIT 118 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_RXLOOP BIT(9) BIT 122 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_TXMONO BIT(10) BIT 163 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_IWS BIT(31) BIT 176 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRB_FIFOEN BIT(1) BIT 189 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_SR_RXEN BIT(0) /* Receiver Enabled */ BIT 190 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_SR_TXEN BIT(4) /* Transmitter Enabled */ BIT 196 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_TXRDYCH(ch) BIT(ch) BIT 198 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_TXUNFCH(ch) BIT((ch) + 8) BIT 200 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_RXRDYCH(ch) BIT((ch) + 16) BIT 202 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_RXOVFCH(ch) BIT((ch) + 24) BIT 207 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_WERR BIT(0) BIT 208 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_TXFFRDY BIT(8) BIT 209 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_TXFFEMP BIT(9) BIT 210 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_RXFFRDY BIT(12) BIT 211 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_RXFFFUL BIT(13) BIT 55 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_STBY BIT(25) BIT 56 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_SYNC BIT(24) BIT 57 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_RXSEX BIT(23) BIT 58 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_RXF BIT(22) BIT 59 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_TXE BIT(21) BIT 60 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_RXD BIT(20) BIT 61 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_TXD BIT(19) BIT 62 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_RXR BIT(18) BIT 63 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_TXW BIT(17) BIT 64 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_CS_RXERR BIT(16) BIT 65 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_CS_TXERR BIT(15) BIT 66 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_RXSYNC BIT(14) BIT 67 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_TXSYNC BIT(13) BIT 68 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_DMAEN BIT(9) BIT 71 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_RXCLR BIT(4) BIT 72 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_TXCLR BIT(3) BIT 73 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_TXON BIT(2) BIT 74 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_RXON BIT(1) BIT 77 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_CLKDIS BIT(28) BIT 78 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_PDMN BIT(27) BIT 79 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_PDME BIT(26) BIT 80 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_FRXP BIT(25) BIT 81 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_FTXP BIT(24) BIT 82 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_CLKM BIT(23) BIT 83 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_CLKI BIT(22) BIT 84 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_FSM BIT(21) BIT 85 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_FSI BIT(20) BIT 89 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_CHWEX BIT(15) BIT 90 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_CHEN BIT(14) BIT 103 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_INT_RXERR BIT(3) BIT 104 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_INT_TXERR BIT(2) BIT 105 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_INT_RXR BIT(1) BIT 106 sound/soc/bcm/bcm2835-i2s.c #define BCM2835_I2S_INT_TXW BIT(0) BIT 170 sound/soc/bcm/cygnus-pcm.c #define ANY_PLAYBACK_IRQ (BIT(R5F_ESR0_SHIFT) | \ BIT 171 sound/soc/bcm/cygnus-pcm.c BIT(R5F_ESR1_SHIFT) | \ BIT 172 sound/soc/bcm/cygnus-pcm.c BIT(R5F_ESR3_SHIFT)) BIT 175 sound/soc/bcm/cygnus-pcm.c #define ANY_CAPTURE_IRQ (BIT(R5F_ESR2_SHIFT) | BIT(R5F_ESR4_SHIFT)) BIT 233 sound/soc/bcm/cygnus-pcm.c initial_wr = initial_rd ^ BIT(31); BIT 328 sound/soc/bcm/cygnus-pcm.c clear_mask = BIT(aio->portnum); BIT 365 sound/soc/bcm/cygnus-pcm.c set_mask = BIT(aio->portnum); BIT 419 sound/soc/bcm/cygnus-pcm.c regval = regval ^ BIT(31); BIT 457 sound/soc/bcm/cygnus-pcm.c u32 esrmask = BIT(port); BIT 518 sound/soc/bcm/cygnus-pcm.c u32 esrmask = BIT(port); BIT 35 sound/soc/bcm/cygnus-ssp.c #define PLAYBACK_STREAM_MASK BIT(0) BIT 36 sound/soc/bcm/cygnus-ssp.c #define CAPTURE_STREAM_MASK BIT(1) BIT 276 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY); BIT 277 sound/soc/bcm/cygnus-ssp.c value |= BIT(BF_SRC_CFGX_SFIFO_SZ_DOUBLE); BIT 278 sound/soc/bcm/cygnus-ssp.c value |= BIT(BF_SRC_CFGX_PROCESS_SEQ_ID_VALID); BIT 293 sound/soc/bcm/cygnus-ssp.c value |= BIT(BF_DST_CFGX_DFIFO_SZ_DOUBLE); BIT 294 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(BF_DST_CFGX_NOT_PAUSE_WHEN_FULL); BIT 296 sound/soc/bcm/cygnus-ssp.c value |= BIT(BF_DST_CFGX_PROC_SEQ_ID_VALID); BIT 301 sound/soc/bcm/cygnus-ssp.c value &= ~BIT((aio->portnum * 4) + AUD_MISC_SEROUT_SDAT_OE); BIT 308 sound/soc/bcm/cygnus-ssp.c value |= BIT(SPDIF_0_OUT_DITHER_ENA); BIT 315 sound/soc/bcm/cygnus-ssp.c value |= BIT(SPDIF_0_OUT_STREAM_ENA); BIT 319 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY); BIT 320 sound/soc/bcm/cygnus-ssp.c value |= BIT(BF_SRC_CFGX_SFIFO_SZ_DOUBLE); BIT 321 sound/soc/bcm/cygnus-ssp.c value |= BIT(BF_SRC_CFGX_PROCESS_SEQ_ID_VALID); BIT 326 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(AUD_MISC_SEROUT_SPDIF_OE); BIT 342 sound/soc/bcm/cygnus-ssp.c value |= BIT(BF_DST_CFGX_CAP_ENA); BIT 348 sound/soc/bcm/cygnus-ssp.c value |= BIT(I2S_OUT_CFGX_CLK_ENA); BIT 349 sound/soc/bcm/cygnus-ssp.c value |= BIT(I2S_OUT_CFGX_DATA_ENABLE); BIT 353 sound/soc/bcm/cygnus-ssp.c value |= BIT(I2S_IN_STREAM_CFG_CAP_ENA); BIT 364 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(I2S_IN_STREAM_CFG_CAP_ENA); BIT 372 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(I2S_OUT_CFGX_CLK_ENA); BIT 373 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(I2S_OUT_CFGX_DATA_ENABLE); BIT 380 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(BF_DST_CFGX_CAP_ENA); BIT 392 sound/soc/bcm/cygnus-ssp.c value |= BIT(I2S_OUT_STREAM_ENA); BIT 398 sound/soc/bcm/cygnus-ssp.c value |= BIT(I2S_OUT_CFGX_CLK_ENA); BIT 399 sound/soc/bcm/cygnus-ssp.c value |= BIT(I2S_OUT_CFGX_DATA_ENABLE); BIT 403 sound/soc/bcm/cygnus-ssp.c value |= BIT(BF_SRC_CFGX_SFIFO_ENA); BIT 416 sound/soc/bcm/cygnus-ssp.c value |= BIT(BF_SRC_CFGX_SFIFO_ENA); BIT 440 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(I2S_OUT_CFGX_CLK_ENA); BIT 441 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(I2S_OUT_CFGX_DATA_ENABLE); BIT 447 sound/soc/bcm/cygnus-ssp.c value |= BIT(aio->portnum); BIT 453 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(BF_SRC_CFGX_SFIFO_ENA); BIT 458 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(aio->portnum); BIT 462 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(I2S_OUT_STREAM_ENA); BIT 467 sound/soc/bcm/cygnus-ssp.c value |= BIT(aio->portnum); BIT 469 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(aio->portnum); BIT 479 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(BF_SRC_CFGX_SFIFO_ENA); BIT 657 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(BF_SRC_CFGX_BUFFER_PAIR_ENABLE); BIT 658 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(BF_SRC_CFGX_SAMPLE_CH_MODE); BIT 686 sound/soc/bcm/cygnus-ssp.c value |= BIT(BF_DST_CFGX_CAP_MODE); BIT 694 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(BF_DST_CFGX_CAP_MODE); BIT 853 sound/soc/bcm/cygnus-ssp.c ssp_newcfg |= BIT(I2S_OUT_CFGX_SLAVE_MODE); BIT 857 sound/soc/bcm/cygnus-ssp.c ssp_newcfg &= ~BIT(I2S_OUT_CFGX_SLAVE_MODE); BIT 866 sound/soc/bcm/cygnus-ssp.c ssp_newcfg |= BIT(I2S_OUT_CFGX_DATA_ALIGNMENT); BIT 867 sound/soc/bcm/cygnus-ssp.c ssp_newcfg |= BIT(I2S_OUT_CFGX_FSYNC_WIDTH); BIT 873 sound/soc/bcm/cygnus-ssp.c ssp_newcfg |= BIT(I2S_OUT_CFGX_TDM_MODE); BIT 877 sound/soc/bcm/cygnus-ssp.c ssp_newcfg |= BIT(I2S_OUT_CFGX_DATA_ALIGNMENT); BIT 883 sound/soc/bcm/cygnus-ssp.c ssp_newcfg |= BIT(I2S_OUT_CFGX_FSYNC_WIDTH); BIT 915 sound/soc/bcm/cygnus-ssp.c mask = BIT(AUD_MISC_SEROUT_LRCK_OE) BIT 916 sound/soc/bcm/cygnus-ssp.c | BIT(AUD_MISC_SEROUT_SCLK_OE) BIT 917 sound/soc/bcm/cygnus-ssp.c | BIT(AUD_MISC_SEROUT_MCLK_OE); BIT 1039 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(I2S_OUT_CFGX_BITS_PER_SLOT); BIT 1047 sound/soc/bcm/cygnus-ssp.c value &= ~BIT(I2S_OUT_CFGX_BITS_PER_SLOT); BIT 36 sound/soc/cirrus/ep93xx-ac97.c #define AC97RXCR_REN BIT(0) BIT 37 sound/soc/cirrus/ep93xx-ac97.c #define AC97RXCR_RX3 BIT(3) BIT 38 sound/soc/cirrus/ep93xx-ac97.c #define AC97RXCR_RX4 BIT(4) BIT 39 sound/soc/cirrus/ep93xx-ac97.c #define AC97RXCR_CM BIT(15) BIT 42 sound/soc/cirrus/ep93xx-ac97.c #define AC97TXCR_TEN BIT(0) BIT 43 sound/soc/cirrus/ep93xx-ac97.c #define AC97TXCR_TX3 BIT(3) BIT 44 sound/soc/cirrus/ep93xx-ac97.c #define AC97TXCR_TX4 BIT(4) BIT 45 sound/soc/cirrus/ep93xx-ac97.c #define AC97TXCR_CM BIT(15) BIT 48 sound/soc/cirrus/ep93xx-ac97.c #define AC97SR_TXFE BIT(1) BIT 49 sound/soc/cirrus/ep93xx-ac97.c #define AC97SR_TXUE BIT(6) BIT 68 sound/soc/cirrus/ep93xx-ac97.c #define AC97_SLOT2RXVALID BIT(1) BIT 69 sound/soc/cirrus/ep93xx-ac97.c #define AC97_CODECREADY BIT(5) BIT 70 sound/soc/cirrus/ep93xx-ac97.c #define AC97_SLOT2TXCOMPLETE BIT(6) BIT 73 sound/soc/cirrus/ep93xx-ac97.c #define AC97EOI_WINT BIT(0) BIT 74 sound/soc/cirrus/ep93xx-ac97.c #define AC97EOI_CODECREADY BIT(1) BIT 77 sound/soc/cirrus/ep93xx-ac97.c #define AC97GCR_AC97IFE BIT(0) BIT 80 sound/soc/cirrus/ep93xx-ac97.c #define AC97RESET_TIMEDRESET BIT(0) BIT 83 sound/soc/cirrus/ep93xx-ac97.c #define AC97SYNC_TIMEDSYNC BIT(0) BIT 53 sound/soc/cirrus/ep93xx-i2s.c #define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */ BIT 55 sound/soc/cirrus/ep93xx-i2s.c #define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */ BIT 62 sound/soc/cirrus/ep93xx-i2s.c #define EP93XX_I2S_TXCTRL_TXEMPTY_LVL BIT(0) BIT 63 sound/soc/cirrus/ep93xx-i2s.c #define EP93XX_I2S_TXCTRL_TXUFIE BIT(1) /* Transmit interrupt enable */ BIT 71 sound/soc/cirrus/ep93xx-i2s.c #define EP93XX_I2S_GLSTS_TX0_FIFO_FULL BIT(12) BIT 1042 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ANCFIRUPDATE), BIT 1043 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ANCFIRUPDATE)); BIT 1050 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0); BIT 1060 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ANCIIRINIT), BIT 1061 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ANCIIRINIT)); BIT 1064 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ANCIIRINIT), 0); BIT 1068 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ANCIIRUPDATE), BIT 1069 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ANCIIRUPDATE)); BIT 1081 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0); BIT 1095 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ENANC), 0); BIT 1098 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC)); BIT 1157 sound/soc/codecs/ab8500-codec.c if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) { BIT 1158 sound/soc/codecs/ab8500-codec.c if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) { BIT 1177 sound/soc/codecs/ab8500-codec.c BIT(AB8500_SIDFIRADR_FIRSIDSET), BIT 1178 sound/soc/codecs/ab8500-codec.c BIT(AB8500_SIDFIRADR_FIRSIDSET)); BIT 1180 sound/soc/codecs/ab8500-codec.c BIT(AB8500_SIDFIRADR_FIRSIDSET), 0); BIT 2042 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF2_IF0DEL); BIT 2049 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0DEL); BIT 2072 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) | BIT 2073 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF1_ENFSBITCLK0); BIT 2075 sound/soc/codecs/ab8500-codec.c val = BIT(AB8500_DIGIFCONF1_ENMASTGEN); BIT 2081 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0); BIT 2108 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) | BIT 2109 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) | BIT 2110 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) | BIT 2111 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF3_IF0MASTER); BIT 2118 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF3_IF0MASTER); BIT 2150 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) | BIT 2151 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF2_IF0FORMAT1) | BIT 2152 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF2_FSYNC0P) | BIT 2153 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF2_BITCLK0P); BIT 2159 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1); BIT 2166 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0); BIT 2173 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0); BIT 2194 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_FSYNC0P); BIT 2200 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_BITCLK0P); BIT 2206 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_FSYNC0P); BIT 2207 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_BITCLK0P); BIT 2228 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF2_IF0WL0) | BIT 2229 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF2_IF0WL1); BIT 2236 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0WL0); BIT 2239 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0WL1); BIT 2242 sound/soc/codecs/ab8500-codec.c val |= BIT(AB8500_DIGIFCONF2_IF0WL1) | BIT 2243 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF2_IF0WL0); BIT 2257 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) | BIT 2258 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); BIT 2264 sound/soc/codecs/ab8500-codec.c val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0); BIT 2267 sound/soc/codecs/ab8500-codec.c val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); BIT 2270 sound/soc/codecs/ab8500-codec.c val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) | BIT 2271 sound/soc/codecs/ab8500-codec.c BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); BIT 2494 sound/soc/codecs/ab8500-codec.c BIT(AB8500_ANACONF5_HSAUTOEN)); BIT 2496 sound/soc/codecs/ab8500-codec.c BIT(AB8500_SHORTCIRCONF_HSZCDDIS)); BIT 119 sound/soc/codecs/adau1373.c #define ADAU1373_PLL_CTRL6_DPLL_BYPASS BIT(1) BIT 120 sound/soc/codecs/adau1373.c #define ADAU1373_PLL_CTRL6_PLL_EN BIT(0) BIT 122 sound/soc/codecs/adau1373.c #define ADAU1373_DAI_INVERT_BCLK BIT(7) BIT 123 sound/soc/codecs/adau1373.c #define ADAU1373_DAI_MASTER BIT(6) BIT 124 sound/soc/codecs/adau1373.c #define ADAU1373_DAI_INVERT_LRCLK BIT(4) BIT 135 sound/soc/codecs/adau1373.c #define ADAU1373_BCLKDIV_SOURCE BIT(5) BIT 143 sound/soc/codecs/adau1373.c #define ADAU1373_ADC_CTRL_PEAK_DETECT BIT(0) BIT 144 sound/soc/codecs/adau1373.c #define ADAU1373_ADC_CTRL_RESET BIT(1) BIT 145 sound/soc/codecs/adau1373.c #define ADAU1373_ADC_CTRL_RESET_FORCE BIT(2) BIT 147 sound/soc/codecs/adau1373.c #define ADAU1373_OUTPUT_CTRL_LDIFF BIT(3) BIT 148 sound/soc/codecs/adau1373.c #define ADAU1373_OUTPUT_CTRL_LNFBEN BIT(2) BIT 150 sound/soc/codecs/adau1373.c #define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0) BIT 1377 sound/soc/codecs/adau1373.c val |= BIT(i); BIT 94 sound/soc/codecs/adau1701.c #define ADAU1701_SERICTL_INV_BCLK BIT(3) BIT 95 sound/soc/codecs/adau1701.c #define ADAU1701_SERICTL_INV_LRCLK BIT(4) BIT 49 sound/soc/codecs/adau1761.c #define ADAU1761_DIGMIC_JACKDETECT_ACTIVE_LOW BIT(0) BIT 50 sound/soc/codecs/adau1761.c #define ADAU1761_DIGMIC_JACKDETECT_DIGMIC BIT(5) BIT 52 sound/soc/codecs/adau1761.c #define ADAU1761_DIFF_INPUT_VOL_LDEN BIT(0) BIT 54 sound/soc/codecs/adau1761.c #define ADAU1761_PLAY_MONO_OUTPUT_VOL_MODE_HP BIT(0) BIT 55 sound/soc/codecs/adau1761.c #define ADAU1761_PLAY_MONO_OUTPUT_VOL_UNMUTE BIT(1) BIT 57 sound/soc/codecs/adau1761.c #define ADAU1761_PLAY_HP_RIGHT_VOL_MODE_HP BIT(0) BIT 59 sound/soc/codecs/adau1761.c #define ADAU1761_PLAY_LINE_LEFT_VOL_MODE_HP BIT(0) BIT 61 sound/soc/codecs/adau1761.c #define ADAU1761_PLAY_LINE_RIGHT_VOL_MODE_HP BIT(0) BIT 38 sound/soc/codecs/adau1781.c #define ADAU1781_INPUT_DIFFERNTIAL BIT(3) BIT 96 sound/soc/codecs/adau17x1.h #define ADAU17X1_SERIAL_PORT0_BCLK_POL BIT(4) BIT 97 sound/soc/codecs/adau17x1.h #define ADAU17X1_SERIAL_PORT0_LRCLK_POL BIT(3) BIT 98 sound/soc/codecs/adau17x1.h #define ADAU17X1_SERIAL_PORT0_MASTER BIT(0) BIT 107 sound/soc/codecs/adau17x1.h #define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL BIT(3) BIT 108 sound/soc/codecs/adau17x1.h #define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN BIT(0) BIT 121 sound/soc/codecs/adau17x1.h #define ADAU17X1_SERIAL_PORT0_PULSE_MODE BIT(5) BIT 130 sound/soc/codecs/adau17x1.h #define ADAU17X1_CONVERTER0_ADOSR BIT(3) BIT 50 sound/soc/codecs/adau1977.c #define ADAU1977_POWER_RESET BIT(7) BIT 51 sound/soc/codecs/adau1977.c #define ADAU1977_POWER_PWUP BIT(0) BIT 53 sound/soc/codecs/adau1977.c #define ADAU1977_PLL_CLK_S BIT(4) BIT 59 sound/soc/codecs/adau1977.c #define ADAU1977_BLOCK_POWER_SAI_LR_POL BIT(7) BIT 60 sound/soc/codecs/adau1977.c #define ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE BIT(6) BIT 61 sound/soc/codecs/adau1977.c #define ADAU1977_BLOCK_POWER_SAI_LDO_EN BIT(5) BIT 90 sound/soc/codecs/adau1977.c #define ADAU1977_SAI_CTRL1_LRCLK_PULSE BIT(3) BIT 91 sound/soc/codecs/adau1977.c #define ADAU1977_SAI_CTRL1_MSB BIT(2) BIT 95 sound/soc/codecs/adau1977.c #define ADAU1977_SAI_CTRL1_MASTER BIT(0) BIT 97 sound/soc/codecs/adau1977.c #define ADAU1977_SAI_OVERTEMP_DRV_C(x) BIT(4 + (x)) BIT 98 sound/soc/codecs/adau1977.c #define ADAU1977_SAI_OVERTEMP_DRV_HIZ BIT(3) BIT 104 sound/soc/codecs/adau1977.c #define ADAU1977_MISC_CONTROL_MMUTE BIT(4) BIT 105 sound/soc/codecs/adau1977.c #define ADAU1977_MISC_CONTROL_DC_CAL BIT(0) BIT 113 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x)) BIT 49 sound/soc/codecs/ak4613.c #define RSTN BIT(0) BIT 50 sound/soc/codecs/ak4613.c #define PMDAC BIT(1) BIT 51 sound/soc/codecs/ak4613.c #define PMADC BIT(2) BIT 52 sound/soc/codecs/ak4613.c #define PMVR BIT(3) BIT 61 sound/soc/codecs/ak4613.c #define DIF0 BIT(3) BIT 62 sound/soc/codecs/ak4613.c #define DIF1 BIT(4) BIT 63 sound/soc/codecs/ak4613.c #define DIF2 BIT(5) BIT 64 sound/soc/codecs/ak4613.c #define TDM0 BIT(6) BIT 65 sound/soc/codecs/ak4613.c #define TDM1 BIT(7) BIT 236 sound/soc/codecs/cpcap.c { CPCAP_REG_A2LA, BIT(CPCAP_BIT_A2_FREE_RUN), BIT 237 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_A2_FREE_RUN) }, BIT 409 sound/soc/codecs/cpcap.c unsigned int mask = BIT(e->shift_l); BIT 458 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_MIC1_MUX); BIT 459 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_HS_MIC_MUX); BIT 460 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_EMU_MIC_MUX); BIT 461 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_RX_R_ENCODE); BIT 464 sound/soc/codecs/cpcap.c case BIT(CPCAP_BIT_RX_R_ENCODE): BIT 467 sound/soc/codecs/cpcap.c case BIT(CPCAP_BIT_EMU_MIC_MUX): BIT 470 sound/soc/codecs/cpcap.c case BIT(CPCAP_BIT_HS_MIC_MUX): BIT 473 sound/soc/codecs/cpcap.c case BIT(CPCAP_BIT_MIC1_MUX): BIT 497 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_MIC1_MUX); BIT 498 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_HS_MIC_MUX); BIT 499 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_EMU_MIC_MUX); BIT 500 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_RX_R_ENCODE); BIT 504 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_MIC1_MUX); BIT 507 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_HS_MIC_MUX); BIT 510 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_EMU_MIC_MUX); BIT 513 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_RX_R_ENCODE); BIT 542 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_MIC2_MUX); BIT 543 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_RX_L_ENCODE); BIT 546 sound/soc/codecs/cpcap.c case BIT(CPCAP_BIT_RX_L_ENCODE): BIT 549 sound/soc/codecs/cpcap.c case BIT(CPCAP_BIT_MIC2_MUX): BIT 573 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_MIC2_MUX); BIT 574 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_RX_L_ENCODE); BIT 578 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_MIC2_MUX); BIT 581 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_RX_L_ENCODE); BIT 981 sound/soc/codecs/cpcap.c err = regmap_update_bits(cpcap->regmap, clkidreg, BIT(clkidshift), BIT 982 sound/soc/codecs/cpcap.c clk_id ? BIT(clkidshift) : 0); BIT 988 sound/soc/codecs/cpcap.c mask = BIT(CPCAP_BIT_CDC_PLL_SEL); BIT 989 sound/soc/codecs/cpcap.c val = BIT(CPCAP_BIT_CDC_PLL_SEL); BIT 1046 sound/soc/codecs/cpcap.c sampreset = BIT(CPCAP_BIT_DF_RESET_ST_DAC) | BIT 1047 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_CLOCK_TREE_RESET); BIT 1052 sound/soc/codecs/cpcap.c sampreset = BIT(CPCAP_BIT_DF_RESET) | BIT 1053 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_CDC_CLOCK_TREE_RESET); BIT 1145 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_SMB_ST_DAC) | BIT 1146 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_CLK_INV) | BIT 1147 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_FS_INV) | BIT 1148 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_DIG_AUD_FS0) | BIT 1149 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_DIG_AUD_FS1) | BIT 1150 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_L_TIMESLOT0) | BIT 1151 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_L_TIMESLOT1) | BIT 1152 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_L_TIMESLOT2) | BIT 1153 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_R_TIMESLOT0) | BIT 1154 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_R_TIMESLOT1) | BIT 1155 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_ST_R_TIMESLOT2); BIT 1167 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_SMB_ST_DAC); BIT 1176 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_FS_INV); BIT 1177 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_CLK_INV); BIT 1180 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_FS_INV); BIT 1181 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_CLK_INV); BIT 1184 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_FS_INV); BIT 1185 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_CLK_INV); BIT 1188 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_FS_INV); BIT 1189 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_CLK_INV); BIT 1196 sound/soc/codecs/cpcap.c if (val & BIT(CPCAP_BIT_ST_CLK_INV)) BIT 1197 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_CLK_INV); BIT 1199 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_CLK_INV); BIT 1203 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0); BIT 1204 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS1); BIT 1208 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0); BIT 1209 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_ST_DIG_AUD_FS1); BIT 1211 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_ST_L_TIMESLOT0); BIT 1224 sound/soc/codecs/cpcap.c static const u16 mask = BIT(CPCAP_BIT_ST_DAC_SW); BIT 1230 sound/soc/codecs/cpcap.c val = BIT(CPCAP_BIT_ST_DAC_SW); BIT 1274 sound/soc/codecs/cpcap.c val = BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0); BIT 1299 sound/soc/codecs/cpcap.c static const u16 mask = BIT(CPCAP_BIT_SMB_CDC) | BIT 1300 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_CLK_INV) | BIT 1301 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_FS_INV) | BIT 1302 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_CDC_DIG_AUD_FS0) | BIT 1303 sound/soc/codecs/cpcap.c BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); BIT 1316 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_SMB_CDC); BIT 1320 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_SMB_CDC); BIT 1326 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CLK_INV); BIT 1327 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_FS_INV); BIT 1330 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CLK_INV); BIT 1331 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_FS_INV); BIT 1334 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_CLK_INV); BIT 1335 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_FS_INV); BIT 1338 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_CLK_INV); BIT 1339 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_FS_INV); BIT 1346 sound/soc/codecs/cpcap.c if (val & BIT(CPCAP_BIT_CLK_INV)) BIT 1347 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_CLK_INV); BIT 1349 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CLK_INV); BIT 1354 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0); BIT 1355 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); BIT 1359 sound/soc/codecs/cpcap.c val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0); BIT 1360 sound/soc/codecs/cpcap.c val &= ~BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); BIT 1378 sound/soc/codecs/cpcap.c static const u16 mask = BIT(CPCAP_BIT_CDC_SW); BIT 1384 sound/soc/codecs/cpcap.c val = BIT(CPCAP_BIT_CDC_SW); BIT 1434 sound/soc/codecs/cpcap.c u16 hifi_mask = BIT(CPCAP_BIT_DIG_AUD_IN_ST_DAC); BIT 1435 sound/soc/codecs/cpcap.c u16 voice_mask = BIT(CPCAP_BIT_DIG_AUD_IN); BIT 40 sound/soc/codecs/hdmi-codec.c FL = BIT(0), /* Front Left */ BIT 41 sound/soc/codecs/hdmi-codec.c FC = BIT(1), /* Front Center */ BIT 42 sound/soc/codecs/hdmi-codec.c FR = BIT(2), /* Front Right */ BIT 43 sound/soc/codecs/hdmi-codec.c FLC = BIT(3), /* Front Left Center */ BIT 44 sound/soc/codecs/hdmi-codec.c FRC = BIT(4), /* Front Right Center */ BIT 45 sound/soc/codecs/hdmi-codec.c RL = BIT(5), /* Rear Left */ BIT 46 sound/soc/codecs/hdmi-codec.c RC = BIT(6), /* Rear Center */ BIT 47 sound/soc/codecs/hdmi-codec.c RR = BIT(7), /* Rear Right */ BIT 48 sound/soc/codecs/hdmi-codec.c RLC = BIT(8), /* Rear Left Center */ BIT 49 sound/soc/codecs/hdmi-codec.c RRC = BIT(9), /* Rear Right Center */ BIT 50 sound/soc/codecs/hdmi-codec.c LFE = BIT(10), /* Low Frequency Effect */ BIT 402 sound/soc/codecs/inno_rk3036.c #define GRF_ACODEC_SEL (BIT(10) | BIT(16 + 10)) BIT 866 sound/soc/codecs/isabelle.c BIT(4), (mute ? BIT(4) : 0)); BIT 874 sound/soc/codecs/isabelle.c BIT(4), (mute ? BIT(4) : 0)); BIT 882 sound/soc/codecs/isabelle.c BIT(4), (mute ? BIT(4) : 0)); BIT 898 sound/soc/codecs/isabelle.c ISABELLE_CHIP_EN, BIT(0)); BIT 112 sound/soc/codecs/isabelle.h #define ISABELLE_CHIP_EN BIT(0) BIT 29 sound/soc/codecs/jz4725b.c #define ICDC_RGADW_RGWR BIT(16) BIT 38 sound/soc/codecs/jz4725b.c #define ICDC_RGDATA_IRQ BIT(8) BIT 202 sound/soc/codecs/jz4725b.c BIT(REG_IFR_RAMP_UP_DONE_OFFSET), 0); BIT 205 sound/soc/codecs/jz4725b.c val, val & BIT(REG_IFR_RAMP_UP_DONE_OFFSET), BIT 209 sound/soc/codecs/jz4725b.c BIT(REG_IFR_RAMP_DOWN_DONE_OFFSET), 0); BIT 212 sound/soc/codecs/jz4725b.c val, val & BIT(REG_IFR_RAMP_DOWN_DONE_OFFSET), BIT 307 sound/soc/codecs/jz4725b.c BIT(REG_PMR2_SB_SLEEP_OFFSET), 0); BIT 312 sound/soc/codecs/jz4725b.c BIT(REG_PMR2_SB_OFFSET), 0); BIT 317 sound/soc/codecs/jz4725b.c BIT(REG_PMR2_SB_SLEEP_OFFSET), BIT 318 sound/soc/codecs/jz4725b.c BIT(REG_PMR2_SB_SLEEP_OFFSET)); BIT 322 sound/soc/codecs/jz4725b.c BIT(REG_PMR2_SB_OFFSET), BIT 323 sound/soc/codecs/jz4725b.c BIT(REG_PMR2_SB_OFFSET)); BIT 26 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_LINE_ENABLE BIT(29) BIT 27 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_MIC_ENABLE BIT(28) BIT 28 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_SW1_ENABLE BIT(27) BIT 29 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_ADC_ENABLE BIT(26) BIT 30 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_SW2_ENABLE BIT(25) BIT 31 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_DAC_ENABLE BIT(24) BIT 32 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_VREF_DISABLE BIT(20) BIT 33 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19) BIT 34 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18) BIT 35 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17) BIT 36 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16) BIT 37 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14) BIT 38 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13) BIT 39 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12) BIT 40 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10)) BIT 41 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9) BIT 42 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8) BIT 43 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_SUSPEND BIT(1) BIT 44 sound/soc/codecs/jz4740.c #define JZ4740_CODEC_1_RESET BIT(0) BIT 1186 sound/soc/codecs/lm49453.c LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(0)|BIT(5), BIT 1210 sound/soc/codecs/lm49453.c pll_clk = BIT(4); BIT 1216 sound/soc/codecs/lm49453.c snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk); BIT 1223 sound/soc/codecs/lm49453.c snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0), BIT 1224 sound/soc/codecs/lm49453.c (mute ? (BIT(1)|BIT(0)) : 0)); BIT 1230 sound/soc/codecs/lm49453.c snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2), BIT 1231 sound/soc/codecs/lm49453.c (mute ? (BIT(3)|BIT(2)) : 0)); BIT 1237 sound/soc/codecs/lm49453.c snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4), BIT 1238 sound/soc/codecs/lm49453.c (mute ? (BIT(5)|BIT(4)) : 0)); BIT 1244 sound/soc/codecs/lm49453.c snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(4), BIT 1245 sound/soc/codecs/lm49453.c (mute ? BIT(4) : 0)); BIT 1251 sound/soc/codecs/lm49453.c snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6), BIT 1252 sound/soc/codecs/lm49453.c (mute ? (BIT(7)|BIT(6)) : 0)); BIT 246 sound/soc/codecs/lm49453.h #define LM49453_PMC_SETUP_CHIP_EN (BIT(1)|BIT(0)) BIT 247 sound/soc/codecs/lm49453.h #define LM49453_PMC_SETUP_PLL_EN BIT(2) BIT 248 sound/soc/codecs/lm49453.h #define LM49453_PMC_SETUP_PLL_P2_EN BIT(3) BIT 249 sound/soc/codecs/lm49453.h #define LM49453_PMC_SETUP_PLL_FLL BIT(4) BIT 250 sound/soc/codecs/lm49453.h #define LM49453_PMC_SETUP_MCLK_OVER BIT(5) BIT 251 sound/soc/codecs/lm49453.h #define LM49453_PMC_SETUP_RTC_CLK_OVER BIT(6) BIT 252 sound/soc/codecs/lm49453.h #define LM49453_PMC_SETUP_CHIP_ACTIVE BIT(7) BIT 276 sound/soc/codecs/lm49453.h #define LM49453_ADC_DSP_ADC_MUTEL BIT(0) BIT 277 sound/soc/codecs/lm49453.h #define LM49453_ADC_DSP_ADC_MUTER BIT(1) BIT 278 sound/soc/codecs/lm49453.h #define LM49453_ADC_DSP_DMIC1_MUTEL BIT(2) BIT 279 sound/soc/codecs/lm49453.h #define LM49453_ADC_DSP_DMIC1_MUTER BIT(3) BIT 280 sound/soc/codecs/lm49453.h #define LM49453_ADC_DSP_DMIC2_MUTEL BIT(4) BIT 281 sound/soc/codecs/lm49453.h #define LM49453_ADC_DSP_DMIC2_MUTER BIT(5) BIT 288 sound/soc/codecs/lm49453.h #define LM49453_AUDIO_PORT1_BASIC_FMT_MASK (BIT(4)|BIT(3)) BIT 289 sound/soc/codecs/lm49453.h #define LM49453_AUDIO_PORT1_BASIC_CLK_MS BIT(3) BIT 290 sound/soc/codecs/lm49453.h #define LM49453_AUDIO_PORT1_BASIC_SYNC_MS BIT(4) BIT 293 sound/soc/codecs/lm49453.h #define LM49453_RESET_REG_RST BIT(0) BIT 22 sound/soc/codecs/ml26124.c #define DVOL_CTL_DVMUTE_ON BIT(4) /* Digital volume MUTE On */ BIT 24 sound/soc/codecs/ml26124.c #define ML26124_SAI_NO_DELAY BIT(1) BIT 25 sound/soc/codecs/ml26124.c #define ML26124_SAI_FRAME_SYNC (BIT(5) | BIT(0)) /* For mono (Telecodec) */ BIT 27 sound/soc/codecs/ml26124.c #define ML26124_VMID BIT(1) BIT 342 sound/soc/codecs/ml26124.c BIT(0) | BIT(1), 1); BIT 346 sound/soc/codecs/ml26124.c BIT(0) | BIT(1), 2); BIT 350 sound/soc/codecs/ml26124.c BIT(0) | BIT(1), 3); BIT 358 sound/soc/codecs/ml26124.c BIT(0) | BIT(1), 0); BIT 382 sound/soc/codecs/ml26124.c snd_soc_component_update_bits(component, ML26124_REC_PLYBAK_RUN, BIT(0), 1); BIT 385 sound/soc/codecs/ml26124.c snd_soc_component_update_bits(component, ML26124_REC_PLYBAK_RUN, BIT(1), 2); BIT 390 sound/soc/codecs/ml26124.c snd_soc_component_update_bits(component, ML26124_DVOL_CTL, BIT(4), BIT 393 sound/soc/codecs/ml26124.c snd_soc_component_update_bits(component, ML26124_DVOL_CTL, BIT(4), BIT 416 sound/soc/codecs/ml26124.c snd_soc_component_update_bits(component, ML26124_SAI_MODE_SEL, BIT(0), mode); BIT 153 sound/soc/codecs/ml26124.h #define ML26124_MCLKEN BIT(0) BIT 154 sound/soc/codecs/ml26124.h #define ML26124_PLLEN BIT(1) BIT 155 sound/soc/codecs/ml26124.h #define ML26124_PLLOE BIT(2) BIT 156 sound/soc/codecs/ml26124.h #define ML26124_MCLKOE BIT(3) BIT 161 sound/soc/codecs/ml26124.h #define ML26124_MICBEN_ON BIT(2) BIT 24 sound/soc/codecs/msm8916-wcd-analog.c #define MBHC_SWITCH_INT BIT(7) BIT 25 sound/soc/codecs/msm8916-wcd-analog.c #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6) BIT 26 sound/soc/codecs/msm8916-wcd-analog.c #define MBHC_BUTTON_PRESS_DET BIT(5) BIT 27 sound/soc/codecs/msm8916-wcd-analog.c #define MBHC_BUTTON_RELEASE_DET BIT(4) BIT 29 sound/soc/codecs/msm8916-wcd-analog.c #define RST_CTL_DIG_SW_RST_N_MASK BIT(7) BIT 31 sound/soc/codecs/msm8916-wcd-analog.c #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7) BIT 34 sound/soc/codecs/msm8916-wcd-analog.c #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3)) BIT 35 sound/soc/codecs/msm8916-wcd-analog.c #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2) BIT 36 sound/soc/codecs/msm8916-wcd-analog.c #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3) BIT 39 sound/soc/codecs/msm8916-wcd-analog.c #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0) BIT 40 sound/soc/codecs/msm8916-wcd-analog.c #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0) BIT 41 sound/soc/codecs/msm8916-wcd-analog.c #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1) BIT 42 sound/soc/codecs/msm8916-wcd-analog.c #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4) BIT 43 sound/soc/codecs/msm8916-wcd-analog.c #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4) BIT 44 sound/soc/codecs/msm8916-wcd-analog.c #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5) BIT 47 sound/soc/codecs/msm8916-wcd-analog.c #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0) BIT 48 sound/soc/codecs/msm8916-wcd-analog.c #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1) BIT 49 sound/soc/codecs/msm8916-wcd-analog.c #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2) BIT 50 sound/soc/codecs/msm8916-wcd-analog.c #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3) BIT 51 sound/soc/codecs/msm8916-wcd-analog.c #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3) BIT 52 sound/soc/codecs/msm8916-wcd-analog.c #define DIG_CLK_CTL_TXD_CLK_EN BIT(4) BIT 53 sound/soc/codecs/msm8916-wcd-analog.c #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6) BIT 54 sound/soc/codecs/msm8916-wcd-analog.c #define DIG_CLK_CTL_NCP_CLK_EN BIT(6) BIT 55 sound/soc/codecs/msm8916-wcd-analog.c #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7) BIT 56 sound/soc/codecs/msm8916-wcd-analog.c #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7) BIT 95 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_EN_MICB_ENABLE BIT(7) BIT 96 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_EN_BYP_CAP_MASK BIT(6) BIT 97 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6) BIT 99 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5) BIT 100 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5) BIT 103 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_EN_PULL_UP_EN_MASK BIT(4) BIT 104 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0) BIT 116 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1) BIT 117 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1) BIT 118 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5) BIT 119 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5) BIT 120 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6) BIT 121 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6) BIT 124 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7) BIT 125 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7) BIT 128 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6) BIT 129 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6) BIT 132 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4) BIT 133 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4) BIT 135 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3) BIT 136 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3) BIT 139 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1) BIT 140 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1) BIT 142 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0) BIT 143 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0) BIT 147 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MICB_2_EN_ENABLE BIT(7) BIT 148 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5) BIT 149 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5) BIT 153 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7) BIT 154 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6) BIT 155 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5) BIT 157 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5) BIT 159 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4) BIT 160 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3) BIT 162 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2) BIT 164 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6)) BIT 165 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5) BIT 167 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4) BIT 168 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_GND_PLUG_TYPE_NO BIT(3) BIT 169 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0) BIT 170 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0) BIT 172 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7) BIT 173 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7) BIT 177 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3) BIT 202 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5) BIT 203 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5) BIT 212 sound/soc/codecs/msm8916-wcd-analog.c #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7) BIT 213 sound/soc/codecs/msm8916-wcd-analog.c #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7) BIT 214 sound/soc/codecs/msm8916-wcd-analog.c #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0) BIT 215 sound/soc/codecs/msm8916-wcd-analog.c #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0) BIT 222 sound/soc/codecs/msm8916-wcd-analog.c #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1) BIT 223 sound/soc/codecs/msm8916-wcd-analog.c #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1) BIT 225 sound/soc/codecs/msm8916-wcd-analog.c #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1) BIT 226 sound/soc/codecs/msm8916-wcd-analog.c #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1) BIT 229 sound/soc/codecs/msm8916-wcd-analog.c #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0) BIT 230 sound/soc/codecs/msm8916-wcd-analog.c #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0) BIT 233 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4) BIT 238 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7) BIT 239 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7) BIT 240 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_DRV_CAL_EN BIT(6) BIT 241 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_DRV_SETTLE_EN BIT(5) BIT 242 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_DRV_FW_EN BIT(3) BIT 243 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_DRV_BOOST_SET BIT(2) BIT 244 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_DRV_CMFB_SET BIT(1) BIT 245 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_DRV_GAIN_SET BIT(0) BIT 252 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0) BIT 253 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_PWRSTG_CTL_DAC_EN BIT(0) BIT 255 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7) BIT 256 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_PWRSTG_CTL_BBM_EN BIT(7) BIT 257 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6) BIT 258 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6) BIT 259 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5) BIT 260 sound/soc/codecs/msm8916-wcd-analog.c #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5) BIT 21 sound/soc/codecs/msm8916-wcd-digital.c #define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK BIT(0) BIT 22 sound/soc/codecs/msm8916-wcd-digital.c #define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK BIT(1) BIT 30 sound/soc/codecs/msm8916-wcd-digital.c #define DMIC_B1_CTL_DMIC0_CLK_EN_MASK BIT(0) BIT 31 sound/soc/codecs/msm8916-wcd-digital.c #define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE BIT(0) BIT 34 sound/soc/codecs/msm8916-wcd-digital.c #define RX_I2S_CTL_RX_I2S_MODE_MASK BIT(5) BIT 35 sound/soc/codecs/msm8916-wcd-digital.c #define RX_I2S_CTL_RX_I2S_MODE_16 BIT(5) BIT 45 sound/soc/codecs/msm8916-wcd-digital.c #define TX_I2S_CTL_TX_I2S_MODE_MASK BIT(5) BIT 46 sound/soc/codecs/msm8916-wcd-digital.c #define TX_I2S_CTL_TX_I2S_MODE_16 BIT(5) BIT 61 sound/soc/codecs/msm8916-wcd-digital.c #define MCLK_CTL_MCLK_EN_MASK BIT(0) BIT 62 sound/soc/codecs/msm8916-wcd-digital.c #define MCLK_CTL_MCLK_EN_ENABLE BIT(0) BIT 65 sound/soc/codecs/msm8916-wcd-digital.c #define LPASS_CDC_CLK_PDM_CTL_PDM_EN_MASK BIT(0) BIT 66 sound/soc/codecs/msm8916-wcd-digital.c #define LPASS_CDC_CLK_PDM_CTL_PDM_EN BIT(0) BIT 67 sound/soc/codecs/msm8916-wcd-digital.c #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK BIT(1) BIT 68 sound/soc/codecs/msm8916-wcd-digital.c #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB BIT(1) BIT 88 sound/soc/codecs/msm8916-wcd-digital.c #define RXn_B6_CTL_MUTE_MASK BIT(0) BIT 89 sound/soc/codecs/msm8916-wcd-digital.c #define RXn_B6_CTL_MUTE_ENABLE BIT(0) BIT 101 sound/soc/codecs/msm8916-wcd-digital.c #define TOP_CTL_DIG_MCLK_FREQ_MASK BIT(0) BIT 103 sound/soc/codecs/msm8916-wcd-digital.c #define TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ BIT(0) BIT 157 sound/soc/codecs/msm8916-wcd-digital.c #define TX_VOL_CTL_CFG_MUTE_EN_MASK BIT(0) BIT 158 sound/soc/codecs/msm8916-wcd-digital.c #define TX_VOL_CTL_CFG_MUTE_EN_ENABLE BIT(0) BIT 167 sound/soc/codecs/msm8916-wcd-digital.c #define TX_MUX_CTL_HPF_BP_SEL_MASK BIT(3) BIT 168 sound/soc/codecs/msm8916-wcd-digital.c #define TX_MUX_CTL_HPF_BP_SEL_BYPASS BIT(3) BIT 953 sound/soc/codecs/nau8824.c if (value & BIT(0)) BIT 955 sound/soc/codecs/nau8824.c if (value & BIT(1)) BIT 957 sound/soc/codecs/nau8824.c if (value & BIT(2)) BIT 959 sound/soc/codecs/nau8824.c if (value & BIT(3)) BIT 961 sound/soc/codecs/nau8824.c if (value & BIT(4)) BIT 963 sound/soc/codecs/nau8824.c if (value & BIT(5)) BIT 1578 sound/soc/codecs/nau8825.c if (value & BIT(0)) BIT 1580 sound/soc/codecs/nau8825.c if (value & BIT(1)) BIT 1582 sound/soc/codecs/nau8825.c if (value & BIT(2)) BIT 1584 sound/soc/codecs/nau8825.c if (value & BIT(3)) BIT 1586 sound/soc/codecs/nau8825.c if (value & BIT(4)) BIT 1588 sound/soc/codecs/nau8825.c if (value & BIT(5)) BIT 145 sound/soc/codecs/pcm186x.h #define PCM186X_ADC_INPUT_SEL_POL BIT(7) BIT 155 sound/soc/codecs/pcm186x.h #define PCM186X_PCM_CFG_TDM_LRCK_MODE BIT(4) BIT 176 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_CTRL_SCK_XI_SEL1 BIT(7) BIT 177 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_CTRL_SCK_XI_SEL0 BIT(6) BIT 178 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_CTRL_SCK_SRC_PLL BIT(5) BIT 179 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_CTRL_MST_MODE BIT(4) BIT 180 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_CTRL_ADC_SRC_PLL BIT(3) BIT 181 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_CTRL_DSP2_SRC_PLL BIT(2) BIT 182 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_CTRL_DSP1_SRC_PLL BIT(1) BIT 183 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_CTRL_CLKDET_EN BIT(0) BIT 186 sound/soc/codecs/pcm186x.h #define PCM186X_PLL_CTRL_LOCK BIT(4) BIT 187 sound/soc/codecs/pcm186x.h #define PCM186X_PLL_CTRL_REF_SEL BIT(1) BIT 188 sound/soc/codecs/pcm186x.h #define PCM186X_PLL_CTRL_EN BIT(0) BIT 191 sound/soc/codecs/pcm186x.h #define PCM186X_PWR_CTRL_PWRDN BIT(2) BIT 192 sound/soc/codecs/pcm186x.h #define PCM186X_PWR_CTRL_SLEEP BIT(1) BIT 193 sound/soc/codecs/pcm186x.h #define PCM186X_PWR_CTRL_STBY BIT(0) BIT 196 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_STATUS_LRCKHLT BIT(6) BIT 197 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_STATUS_BCKHLT BIT(5) BIT 198 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_STATUS_SCKHLT BIT(4) BIT 199 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_STATUS_LRCKERR BIT(2) BIT 200 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_STATUS_BCKERR BIT(1) BIT 201 sound/soc/codecs/pcm186x.h #define PCM186X_CLK_STATUS_SCKERR BIT(0) BIT 204 sound/soc/codecs/pcm186x.h #define PCM186X_SUPPLY_STATUS_DVDD BIT(2) BIT 205 sound/soc/codecs/pcm186x.h #define PCM186X_SUPPLY_STATUS_AVDD BIT(1) BIT 206 sound/soc/codecs/pcm186x.h #define PCM186X_SUPPLY_STATUS_LDO BIT(0) BIT 209 sound/soc/codecs/pcm186x.h #define PCM186X_MMAP_STAT_DONE BIT(4) BIT 210 sound/soc/codecs/pcm186x.h #define PCM186X_MMAP_STAT_BUSY BIT(2) BIT 211 sound/soc/codecs/pcm186x.h #define PCM186X_MMAP_STAT_R_REQ BIT(1) BIT 212 sound/soc/codecs/pcm186x.h #define PCM186X_MMAP_STAT_W_REQ BIT(0) BIT 111 sound/soc/codecs/rk3328_codec.c unsigned int val = BIT(17); BIT 114 sound/soc/codecs/rk3328_codec.c val |= BIT(1); BIT 452 sound/soc/codecs/rk3328_codec.c (BIT(14) << 16 | BIT(14))); BIT 37 sound/soc/codecs/rk3328_codec.h #define PIN_DIRECTION_MASK BIT(5) BIT 40 sound/soc/codecs/rk3328_codec.h #define DAC_I2S_MODE_MASK BIT(4) BIT 45 sound/soc/codecs/rk3328_codec.h #define DAC_I2S_LRP_MASK BIT(7) BIT 58 sound/soc/codecs/rk3328_codec.h #define DAC_LR_SWAP_MASK BIT(2) BIT 68 sound/soc/codecs/rk3328_codec.h #define DAC_RST_MASK BIT(1) BIT 71 sound/soc/codecs/rk3328_codec.h #define DAC_BCP_MASK BIT(0) BIT 76 sound/soc/codecs/rk3328_codec.h #define DAC_CHARGE_XCHARGE_MASK BIT(7) BIT 79 sound/soc/codecs/rk3328_codec.h #define DAC_CHARGE_CURRENT_64I_MASK BIT(6) BIT 81 sound/soc/codecs/rk3328_codec.h #define DAC_CHARGE_CURRENT_32I_MASK BIT(5) BIT 83 sound/soc/codecs/rk3328_codec.h #define DAC_CHARGE_CURRENT_16I_MASK BIT(4) BIT 85 sound/soc/codecs/rk3328_codec.h #define DAC_CHARGE_CURRENT_08I_MASK BIT(3) BIT 87 sound/soc/codecs/rk3328_codec.h #define DAC_CHARGE_CURRENT_04I_MASK BIT(2) BIT 89 sound/soc/codecs/rk3328_codec.h #define DAC_CHARGE_CURRENT_02I_MASK BIT(1) BIT 91 sound/soc/codecs/rk3328_codec.h #define DAC_CHARGE_CURRENT_I_MASK BIT(0) BIT 98 sound/soc/codecs/rk3328_codec.h #define DAC_PWR_MASK BIT(6) BIT 101 sound/soc/codecs/rk3328_codec.h #define DACL_PATH_REFV_MASK BIT(5) BIT 104 sound/soc/codecs/rk3328_codec.h #define HPOUTL_ZERO_CROSSING_MASK BIT(4) BIT 107 sound/soc/codecs/rk3328_codec.h #define DACR_PATH_REFV_MASK BIT(1) BIT 110 sound/soc/codecs/rk3328_codec.h #define HPOUTR_ZERO_CROSSING_MASK BIT(0) BIT 115 sound/soc/codecs/rk3328_codec.h #define DACL_REFV_MASK BIT(7) BIT 118 sound/soc/codecs/rk3328_codec.h #define DACL_CLK_MASK BIT(6) BIT 121 sound/soc/codecs/rk3328_codec.h #define DACL_MASK BIT(5) BIT 124 sound/soc/codecs/rk3328_codec.h #define DACL_INIT_MASK BIT(4) BIT 127 sound/soc/codecs/rk3328_codec.h #define DACR_REFV_MASK BIT(3) BIT 130 sound/soc/codecs/rk3328_codec.h #define DACR_CLK_MASK BIT(2) BIT 133 sound/soc/codecs/rk3328_codec.h #define DACR_MASK BIT(1) BIT 136 sound/soc/codecs/rk3328_codec.h #define DACR_INIT_MASK BIT(0) BIT 141 sound/soc/codecs/rk3328_codec.h #define HPMIXL_MASK BIT(6) BIT 144 sound/soc/codecs/rk3328_codec.h #define HPMIXL_INIT_MASK BIT(5) BIT 147 sound/soc/codecs/rk3328_codec.h #define HPMIXL_INIT2_MASK BIT(4) BIT 150 sound/soc/codecs/rk3328_codec.h #define HPMIXR_MASK BIT(2) BIT 153 sound/soc/codecs/rk3328_codec.h #define HPMIXR_INIT_MASK BIT(1) BIT 156 sound/soc/codecs/rk3328_codec.h #define HPMIXR_INIT2_MASK BIT(0) BIT 161 sound/soc/codecs/rk3328_codec.h #define DACL_SELECT_MASK BIT(4) BIT 164 sound/soc/codecs/rk3328_codec.h #define DACR_SELECT_MASK BIT(0) BIT 169 sound/soc/codecs/rk3328_codec.h #define HPOUTL_MASK BIT(7) BIT 172 sound/soc/codecs/rk3328_codec.h #define HPOUTL_INIT_MASK BIT(6) BIT 175 sound/soc/codecs/rk3328_codec.h #define HPOUTL_MUTE_MASK BIT(5) BIT 178 sound/soc/codecs/rk3328_codec.h #define HPOUTR_MASK BIT(4) BIT 181 sound/soc/codecs/rk3328_codec.h #define HPOUTR_INIT_MASK BIT(3) BIT 184 sound/soc/codecs/rk3328_codec.h #define HPOUTR_MUTE_MASK BIT(2) BIT 2061 sound/soc/codecs/rt5640.h #define RT5640_NO_JACK BIT(0) BIT 2062 sound/soc/codecs/rt5640.h #define RT5640_HEADSET_DET BIT(1) BIT 2063 sound/soc/codecs/rt5640.h #define RT5640_HEADPHO_DET BIT(2) BIT 34 sound/soc/codecs/rt5670.c #define RT5670_DEV_GPIO BIT(0) BIT 35 sound/soc/codecs/rt5670.c #define RT5670_IN2_DIFF BIT(1) BIT 36 sound/soc/codecs/rt5670.c #define RT5670_DMIC_EN BIT(2) BIT 37 sound/soc/codecs/rt5670.c #define RT5670_DMIC1_IN2P BIT(3) BIT 38 sound/soc/codecs/rt5670.c #define RT5670_DMIC1_GPIO6 BIT(4) BIT 39 sound/soc/codecs/rt5670.c #define RT5670_DMIC1_GPIO7 BIT(5) BIT 40 sound/soc/codecs/rt5670.c #define RT5670_DMIC2_INR BIT(6) BIT 41 sound/soc/codecs/rt5670.c #define RT5670_DMIC2_GPIO8 BIT(7) BIT 42 sound/soc/codecs/rt5670.c #define RT5670_DMIC3_GPIO5 BIT(8) BIT 43 sound/soc/codecs/rt5670.c #define RT5670_JD_MODE1 BIT(9) BIT 44 sound/soc/codecs/rt5670.c #define RT5670_JD_MODE2 BIT(10) BIT 45 sound/soc/codecs/rt5670.c #define RT5670_JD_MODE3 BIT(11) BIT 613 sound/soc/codecs/sigmadsp.c return BIT(samplerate_index); BIT 46 sound/soc/codecs/ssm2518.c #define SSM2518_POWER1_RESET BIT(7) BIT 47 sound/soc/codecs/ssm2518.c #define SSM2518_POWER1_NO_BCLK BIT(5) BIT 58 sound/soc/codecs/ssm2518.c #define SSM2518_POWER1_SPWDN BIT(0) BIT 60 sound/soc/codecs/ssm2518.c #define SSM2518_CLOCK_ASR BIT(0) BIT 82 sound/soc/codecs/ssm2518.c #define SSM2518_SAI_CTRL2_BCLK_INTERAL BIT(7) BIT 83 sound/soc/codecs/ssm2518.c #define SSM2518_SAI_CTRL2_LRCLK_PULSE BIT(6) BIT 84 sound/soc/codecs/ssm2518.c #define SSM2518_SAI_CTRL2_LRCLK_INVERT BIT(5) BIT 85 sound/soc/codecs/ssm2518.c #define SSM2518_SAI_CTRL2_MSB BIT(4) BIT 90 sound/soc/codecs/ssm2518.c #define SSM2518_SAI_CTRL2_BCLK_INVERT BIT(1) BIT 97 sound/soc/codecs/ssm2518.c #define SSM2518_MUTE_CTRL_ANA_GAIN BIT(5) BIT 98 sound/soc/codecs/ssm2518.c #define SSM2518_MUTE_CTRL_MUTE_MASTER BIT(0) BIT 100 sound/soc/codecs/ssm2518.c #define SSM2518_POWER2_APWDN BIT(0) BIT 102 sound/soc/codecs/ssm2518.c #define SSM2518_DAC_MUTE BIT(6) BIT 51 sound/soc/codecs/ssm4567.c #define SSM4567_POWER_APWDN_EN BIT(7) BIT 52 sound/soc/codecs/ssm4567.c #define SSM4567_POWER_BSNS_PWDN BIT(6) BIT 53 sound/soc/codecs/ssm4567.c #define SSM4567_POWER_VSNS_PWDN BIT(5) BIT 54 sound/soc/codecs/ssm4567.c #define SSM4567_POWER_ISNS_PWDN BIT(4) BIT 55 sound/soc/codecs/ssm4567.c #define SSM4567_POWER_BOOST_PWDN BIT(3) BIT 56 sound/soc/codecs/ssm4567.c #define SSM4567_POWER_AMP_PWDN BIT(2) BIT 57 sound/soc/codecs/ssm4567.c #define SSM4567_POWER_VBAT_ONLY BIT(1) BIT 58 sound/soc/codecs/ssm4567.c #define SSM4567_POWER_SPWDN BIT(0) BIT 61 sound/soc/codecs/ssm4567.c #define SSM4567_DAC_HV BIT(7) BIT 62 sound/soc/codecs/ssm4567.c #define SSM4567_DAC_MUTE BIT(6) BIT 63 sound/soc/codecs/ssm4567.c #define SSM4567_DAC_HPF BIT(5) BIT 64 sound/soc/codecs/ssm4567.c #define SSM4567_DAC_LPM BIT(4) BIT 73 sound/soc/codecs/ssm4567.c #define SSM4567_SAI_CTRL_1_BCLK BIT(6) BIT 78 sound/soc/codecs/ssm4567.c #define SSM4567_SAI_CTRL_1_FSYNC BIT(3) BIT 79 sound/soc/codecs/ssm4567.c #define SSM4567_SAI_CTRL_1_LJ BIT(2) BIT 80 sound/soc/codecs/ssm4567.c #define SSM4567_SAI_CTRL_1_TDM BIT(1) BIT 81 sound/soc/codecs/ssm4567.c #define SSM4567_SAI_CTRL_1_PDM BIT(0) BIT 84 sound/soc/codecs/ssm4567.c #define SSM4567_SAI_CTRL_2_AUTO_SLOT BIT(3) BIT 248 sound/soc/codecs/ssm4567.c if (tx_mask != BIT(slot)) BIT 96 sound/soc/codecs/sta350.h #define STA350_CONFA_TWRB BIT(5) BIT 97 sound/soc/codecs/sta350.h #define STA350_CONFA_TWAB BIT(6) BIT 98 sound/soc/codecs/sta350.h #define STA350_CONFA_FDRB BIT(7) BIT 103 sound/soc/codecs/sta350.h #define STA350_CONFB_SAIFB BIT(4) BIT 104 sound/soc/codecs/sta350.h #define STA350_CONFB_DSCKE BIT(5) BIT 105 sound/soc/codecs/sta350.h #define STA350_CONFB_C1IM BIT(6) BIT 106 sound/soc/codecs/sta350.h #define STA350_CONFB_C2IM BIT(7) BIT 113 sound/soc/codecs/sta350.h #define STA350_CONFC_OCRB BIT(7) BIT 126 sound/soc/codecs/sta350.h #define STA350_CONFE_MPCV BIT(0) BIT 128 sound/soc/codecs/sta350.h #define STA350_CONFE_MPC BIT(1) BIT 130 sound/soc/codecs/sta350.h #define STA350_CONFE_NSBW BIT(2) BIT 132 sound/soc/codecs/sta350.h #define STA350_CONFE_AME BIT(3) BIT 134 sound/soc/codecs/sta350.h #define STA350_CONFE_PWMS BIT(4) BIT 136 sound/soc/codecs/sta350.h #define STA350_CONFE_DCCV BIT(5) BIT 138 sound/soc/codecs/sta350.h #define STA350_CONFE_ZCE BIT(6) BIT 140 sound/soc/codecs/sta350.h #define STA350_CONFE_SVE BIT(7) BIT 146 sound/soc/codecs/sta350.h #define STA350_CONFF_IDE BIT(2) BIT 147 sound/soc/codecs/sta350.h #define STA350_CONFF_BCLE BIT(3) BIT 148 sound/soc/codecs/sta350.h #define STA350_CONFF_LDTE BIT(4) BIT 149 sound/soc/codecs/sta350.h #define STA350_CONFF_ECLE BIT(5) BIT 150 sound/soc/codecs/sta350.h #define STA350_CONFF_PWDN BIT(6) BIT 151 sound/soc/codecs/sta350.h #define STA350_CONFF_EAPD BIT(7) BIT 225 sound/soc/codecs/sta350.h #define STA350_MISC1_CPWMEN BIT(2) BIT 226 sound/soc/codecs/sta350.h #define STA350_MISC1_BRIDGOFF BIT(5) BIT 227 sound/soc/codecs/sta350.h #define STA350_MISC1_NSHHPEN BIT(6) BIT 228 sound/soc/codecs/sta350.h #define STA350_MISC1_RPDNEN BIT(7) BIT 30 sound/soc/codecs/sti-sas.c #define STIH407_DAC_SOFTMUTE_MASK BIT(STIH407_DAC_SOFTMUTE) BIT 31 sound/soc/codecs/sti-sas.c #define STIH407_DAC_STANDBY_ANA_MASK BIT(STIH407_DAC_STANDBY_ANA) BIT 32 sound/soc/codecs/sti-sas.c #define STIH407_DAC_STANDBY_MASK BIT(STIH407_DAC_STANDBY) BIT 38 sound/soc/codecs/sti-sas.c #define SPDIF_BIPHASE_ENABLE_MASK BIT(SPDIF_BIPHASE_ENABLE) BIT 39 sound/soc/codecs/sti-sas.c #define SPDIF_BIPHASE_IDLE_MASK BIT(SPDIF_BIPHASE_IDLE) BIT 36 sound/soc/codecs/tas5720.h #define TAS5720_SLEEP BIT(1) BIT 37 sound/soc/codecs/tas5720.h #define TAS5720_SDZ BIT(0) BIT 40 sound/soc/codecs/tas5720.h #define TAS5720_HPF_BYPASS BIT(7) BIT 41 sound/soc/codecs/tas5720.h #define TAS5720_TDM_CFG_SRC BIT(6) BIT 42 sound/soc/codecs/tas5720.h #define TAS5720_SSZ_DS BIT(3) BIT 52 sound/soc/codecs/tas5720.h #define TAS5722_VOL_RAMP_RATE BIT(6) BIT 53 sound/soc/codecs/tas5720.h #define TAS5720_MUTE BIT(4) BIT 79 sound/soc/codecs/tas5720.h #define TAS5720_CLKE BIT(3) BIT 80 sound/soc/codecs/tas5720.h #define TAS5720_OCE BIT(2) BIT 81 sound/soc/codecs/tas5720.h #define TAS5720_DCE BIT(1) BIT 82 sound/soc/codecs/tas5720.h #define TAS5720_OTE BIT(0) BIT 104 sound/soc/codecs/tas5720.h #define TAS5722_TDM_SLOT_16B BIT(2) BIT 105 sound/soc/codecs/tas5720.h #define TAS5722_MCLK_PIN_CFG BIT(1) BIT 106 sound/soc/codecs/tas5720.h #define TAS5722_VOL_CONTROL_LSB BIT(0) BIT 109 sound/soc/codecs/tas5720.h #define TAS5722_FAULTZ_PU BIT(3) BIT 110 sound/soc/codecs/tas5720.h #define TAS5722_VREG_LVL BIT(2) BIT 111 sound/soc/codecs/tas5720.h #define TAS5722_PWR_TUNE BIT(0) BIT 57 sound/soc/codecs/tas6424.h #define TAS6424_RESET BIT(7) BIT 64 sound/soc/codecs/tas6424.h #define TAS6424_SAP_TDM_SLOT_LAST BIT(5) BIT 65 sound/soc/codecs/tas6424.h #define TAS6424_SAP_TDM_SLOT_SZ_16 BIT(4) BIT 66 sound/soc/codecs/tas6424.h #define TAS6424_SAP_TDM_SLOT_SWAP BIT(3) BIT 116 sound/soc/codecs/tas6424.h #define TAS6424_LDGBYPASS_MASK BIT(TAS6424_LDGBYPASS_SHIFT) BIT 119 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_OC_CH1 BIT(7) BIT 120 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_OC_CH2 BIT(6) BIT 121 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_OC_CH3 BIT(5) BIT 122 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_OC_CH4 BIT(4) BIT 123 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_DC_CH1 BIT(3) BIT 124 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_DC_CH2 BIT(2) BIT 125 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_DC_CH3 BIT(1) BIT 126 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_DC_CH4 BIT(0) BIT 129 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_CLOCK BIT(4) BIT 130 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_PVDD_OV BIT(3) BIT 131 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_VBAT_OV BIT(2) BIT 132 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_PVDD_UV BIT(1) BIT 133 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_VBAT_UV BIT(0) BIT 136 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_OTSD BIT(4) BIT 137 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_OTSD_CH1 BIT(3) BIT 138 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_OTSD_CH2 BIT(2) BIT 139 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_OTSD_CH3 BIT(1) BIT 140 sound/soc/codecs/tas6424.h #define TAS6424_FAULT_OTSD_CH4 BIT(0) BIT 143 sound/soc/codecs/tas6424.h #define TAS6424_WARN_VDD_UV BIT(6) BIT 144 sound/soc/codecs/tas6424.h #define TAS6424_WARN_VDD_POR BIT(5) BIT 145 sound/soc/codecs/tas6424.h #define TAS6424_WARN_VDD_OTW BIT(4) BIT 146 sound/soc/codecs/tas6424.h #define TAS6424_WARN_VDD_OTW_CH1 BIT(3) BIT 147 sound/soc/codecs/tas6424.h #define TAS6424_WARN_VDD_OTW_CH2 BIT(2) BIT 148 sound/soc/codecs/tas6424.h #define TAS6424_WARN_VDD_OTW_CH3 BIT(1) BIT 149 sound/soc/codecs/tas6424.h #define TAS6424_WARN_VDD_OTW_CH4 BIT(0) BIT 152 sound/soc/codecs/tas6424.h #define TAS6424_CLEAR_FAULT BIT(7) BIT 153 sound/soc/codecs/tas6424.h #define TAS6424_PBTL_CH_SEL BIT(6) BIT 154 sound/soc/codecs/tas6424.h #define TAS6424_MASK_CBC_WARN BIT(5) BIT 155 sound/soc/codecs/tas6424.h #define TAS6424_MASK_VDD_UV BIT(4) BIT 156 sound/soc/codecs/tas6424.h #define TAS6424_OTSD_AUTO_RECOVERY BIT(3) BIT 19 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_STEREO_CLASS_D_BIT BIT(1) BIT 20 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_MINIDSP_BIT BIT(2) BIT 21 sound/soc/codecs/tlv320aic31xx.h #define DAC31XX_BIT BIT(3) BIT 138 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_PM_MASK BIT(7) BIT 154 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_BCLK_MASTER BIT(2) BIT 155 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_WCLK_MASTER BIT(3) BIT 161 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_BCLKINV_MASK BIT(3) BIT 167 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_KEEP_I2SCLK BIT(2) BIT 170 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_ADCPWRSTATUS_MASK BIT(6) BIT 173 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_LDACPWRSTATUS_MASK BIT(7) BIT 174 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_HPLDRVPWRSTATUS_MASK BIT(5) BIT 175 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_SPLDRVPWRSTATUS_MASK BIT(4) BIT 176 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_RDACPWRSTATUS_MASK BIT(3) BIT 177 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_HPRDRVPWRSTATUS_MASK BIT(1) BIT 178 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_SPRDRVPWRSTATUS_MASK BIT(0) BIT 181 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_DAC_OF_LEFT BIT(7) BIT 182 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_DAC_OF_RIGHT BIT(6) BIT 183 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_DAC_OF_SHIFTER BIT(5) BIT 184 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_ADC_OF BIT(3) BIT 185 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_ADC_OF_SHIFTER BIT(1) BIT 188 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_HPLSCDETECT BIT(7) BIT 189 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_HPRSCDETECT BIT(6) BIT 190 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_BUTTONPRESS BIT(5) BIT 191 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_HSPLUG BIT(4) BIT 192 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_LDRCTHRES BIT(3) BIT 193 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_RDRCTHRES BIT(2) BIT 194 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_DACSINT BIT(1) BIT 195 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_DACAINT BIT(0) BIT 198 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_HSPLUGDET BIT(7) BIT 199 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_BUTTONPRESSDET BIT(6) BIT 200 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_DRCTHRES BIT(5) BIT 201 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_AGCNOISE BIT(4) BIT 202 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_SC BIT(3) BIT 203 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_ENGINE BIT(2) BIT 228 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_HSD_ENABLE BIT(7) BIT 117 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_PLLEN BIT(7) BIT 123 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_NDACEN BIT(7) BIT 127 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_MDACEN BIT(7) BIT 131 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_NADCEN BIT(7) BIT 135 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_MADCEN BIT(7) BIT 139 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_BCLKEN BIT(7) BIT 156 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_BCLKMASTER BIT(2) BIT 157 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_WCLKMASTER BIT(3) BIT 163 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_BCLKINV_MASK BIT(3) BIT 173 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_LDAC2RCHN BIT(5) BIT 174 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_LDAC2LCHN BIT(4) BIT 175 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_RDAC2LCHN BIT(3) BIT 176 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_RDAC2RCHN BIT(2) BIT 182 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_LADC_EN BIT(7) BIT 183 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_RADC_EN BIT(6) BIT 186 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_AVDDWEAKDISABLE BIT(3) BIT 189 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_LDOCTLEN BIT(0) BIT 192 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_LDOIN_18_36 BIT(0) BIT 193 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_LDOIN2HP BIT(1) BIT 196 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_MICBIAS_LDOIN BIT(3) BIT 209 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_DIVEN BIT(7) BIT 24 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK BIT(6) BIT 25 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE BIT(6) BIT 34 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK BIT(1) BIT 36 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB BIT(1) BIT 37 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK BIT(2) BIT 38 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA BIT(2) BIT 40 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK BIT(3) BIT 41 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA BIT(3) BIT 43 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_RX_VNEG_EN_MASK BIT(6) BIT 45 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_RX_VNEG_ENABLE BIT(6) BIT 47 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_RX_VPOS_EN_MASK BIT(7) BIT 49 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_RX_VPOS_ENABLE BIT(7) BIT 57 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK BIT(0) BIT 58 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_CDC_CLSH_CRC_CLK_ENABLE BIT(0) BIT 63 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_FLYBACK_EN_RESET_BY_EXT_MASK BIT(4) BIT 64 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_FLYBACK_EN_PWDN_WITHOUT_DELAY BIT(4) BIT 84 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_EN_MASK BIT(0) BIT 85 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_11P3_EN_MASK BIT(1) BIT 21 sound/soc/codecs/wcd-clsh-v2.h #define WCD_CLSH_STATE_EAR BIT(0) BIT 22 sound/soc/codecs/wcd-clsh-v2.h #define WCD_CLSH_STATE_HPHL BIT(1) BIT 23 sound/soc/codecs/wcd-clsh-v2.h #define WCD_CLSH_STATE_HPHR BIT(2) BIT 24 sound/soc/codecs/wcd-clsh-v2.h #define WCD_CLSH_STATE_LO BIT(3) BIT 26 sound/soc/codecs/wcd-clsh-v2.h #define NUM_CLSH_STATES_V2 BIT(WCD_CLSH_STATE_MAX) BIT 1354 sound/soc/codecs/wcd9335.c if (enable && !(wcd->tx_port_value & BIT(port_id))) { BIT 1355 sound/soc/codecs/wcd9335.c wcd->tx_port_value |= BIT(port_id); BIT 1358 sound/soc/codecs/wcd9335.c } else if (!enable && (wcd->tx_port_value & BIT(port_id))) { BIT 1359 sound/soc/codecs/wcd9335.c wcd->tx_port_value &= ~BIT(port_id); BIT 1726 sound/soc/codecs/wcd9335.c cfg->port_mask |= BIT(ch->port); BIT 3012 sound/soc/codecs/wcd9335.c if (!(val & BIT(port_num % 8))) BIT 3014 sound/soc/codecs/wcd9335.c val | BIT(port_num % 8)); BIT 4032 sound/soc/codecs/wcd9335.c BIT(j % 8)); BIT 4993 sound/soc/codecs/wcd9335.c .mask = BIT(0), BIT 4997 sound/soc/codecs/wcd9335.c .type_reg_mask = BIT(0), BIT 20 sound/soc/codecs/wcd9335.h #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0) BIT 21 sound/soc/codecs/wcd9335.h #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ BIT(0) BIT 28 sound/soc/codecs/wcd9335.h #define WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK BIT(0) BIT 29 sound/soc/codecs/wcd9335.h #define WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE BIT(0) BIT 196 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BIAS_EN_MASK BIT(7) BIT 197 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BIAS_ENABLE BIT(7) BIT 199 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BIAS_PRECHRG_EN_MASK BIT(6) BIT 200 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BIAS_PRECHRG_ENABLE BIT(6) BIT 202 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE BIT(5) BIT 203 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_AUTO BIT(5) BIT 206 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_CLK_MCLK_EN_MASK BIT(2) BIT 207 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_CLK_MCLK_ENABLE BIT(2) BIT 209 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_CLK_MCLK_SRC_MASK BIT(3) BIT 210 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_CLK_MCLK_SRC_RCO BIT(3) BIT 212 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK BIT(7) BIT 213 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE BIT(7) BIT 216 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_RCO_BG_EN_MASK BIT(7) BIT 217 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_RCO_BG_ENABLE BIT(7) BIT 221 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK BIT(1) BIT 222 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT BIT(1) BIT 224 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK BIT(2) BIT 225 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT BIT(2) BIT 227 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BUCK_CTL_RAMP_START_MASK BIT(7) BIT 228 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE BIT(7) BIT 231 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_RX_BIAS_ENABLE_MASK BIT(0) BIT 232 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_RX_BIAS_ENABLE BIT(0) BIT 245 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_L_DET_EN_MASK BIT(7) BIT 246 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_L_DET_EN BIT(7) BIT 247 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_GND_DET_EN_MASK BIT(6) BIT 248 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_MECH_DETECT_TYPE_MASK BIT(5) BIT 250 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_HPHL_PLUG_TYPE_MASK BIT(4) BIT 251 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_HPHL_PLUG_TYPE_NO BIT(4) BIT 252 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_GND_PLUG_TYPE_MASK BIT(3) BIT 253 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_GND_PLUG_TYPE_NO BIT(3) BIT 254 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_HSL_PULLUP_COMP_EN BIT(2) BIT 255 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_HPHL_100K_TO_GND_EN BIT(0) BIT 261 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_MBHC_BIAS_EN_MASK BIT(0) BIT 262 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_MBHC_BIAS_EN BIT(0) BIT 278 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_MICB2_ENABLE BIT(6) BIT 296 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_CTL_RCO_EN_MASK BIT(7) BIT 297 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_CTL_RCO_EN BIT(7) BIT 326 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_AUTO_CHOP_MASK BIT(5) BIT 327 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE BIT(5) BIT 332 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK BIT(2) BIT 333 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE BIT(2) BIT 335 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK BIT(3) BIT 336 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE BIT(3) BIT 338 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK BIT(5) BIT 339 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE BIT(5) BIT 347 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_GAIN_SRC_SEL_MASK BIT(5) BIT 349 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_GAIN_SRC_SEL_REGISTER BIT(5) BIT 361 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_DAC_LDO_POWERMODE_MASK BIT(0) BIT 363 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_DAC_LDO_POWERMODE_UHQA BIT(0) BIT 364 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_DAC_LDO_UHQA_OV_MASK BIT(1) BIT 365 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_DAC_LDO_UHQA_OV_ENABLE BIT(1) BIT 382 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK BIT(7) BIT 383 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_TX_ADC_DMIC_SEL BIT(7) BIT 420 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_COMPANDER_CLK_EN_MASK BIT(0) BIT 421 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_COMPANDER_CLK_ENABLE BIT(0) BIT 423 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_COMPANDER_SOFT_RST_MASK BIT(1) BIT 424 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE BIT(1) BIT 426 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_COMPANDER_HALT_MASK BIT(2) BIT 427 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_COMPANDER_HALT BIT(2) BIT 434 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PGA_MUTE_EN_MASK BIT(4) BIT 435 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PGA_MUTE_ENABLE BIT(4) BIT 437 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_CLK_EN_MASK BIT(5) BIT 438 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_CLK_ENABLE BIT(5) BIT 440 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_RESET_MASK BIT(6) BIT 441 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_RESET_ENABLE BIT(6) BIT 459 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK BIT(1) BIT 460 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE BIT(1) BIT 462 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK BIT(2) BIT 463 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE BIT(2) BIT 465 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK BIT(3) BIT 466 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN BIT(3) BIT 595 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK BIT(0) BIT 596 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE BIT(0) BIT 599 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK BIT(0) BIT 600 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE BIT(0) BIT 2865 sound/soc/codecs/wm_adsp.c if (lock_regions & BIT(0)) { BIT 2869 sound/soc/codecs/wm_adsp.c if (lock_regions & BIT(1)) { BIT 23 sound/soc/codecs/wm_adsp.h #define WM_ADSP2_REGION_0 BIT(0) BIT 24 sound/soc/codecs/wm_adsp.h #define WM_ADSP2_REGION_1 BIT(1) BIT 25 sound/soc/codecs/wm_adsp.h #define WM_ADSP2_REGION_2 BIT(2) BIT 26 sound/soc/codecs/wm_adsp.h #define WM_ADSP2_REGION_3 BIT(3) BIT 27 sound/soc/codecs/wm_adsp.h #define WM_ADSP2_REGION_4 BIT(4) BIT 28 sound/soc/codecs/wm_adsp.h #define WM_ADSP2_REGION_5 BIT(5) BIT 29 sound/soc/codecs/wm_adsp.h #define WM_ADSP2_REGION_6 BIT(6) BIT 30 sound/soc/codecs/wm_adsp.h #define WM_ADSP2_REGION_7 BIT(7) BIT 31 sound/soc/codecs/wm_adsp.h #define WM_ADSP2_REGION_8 BIT(8) BIT 32 sound/soc/codecs/wm_adsp.h #define WM_ADSP2_REGION_9 BIT(9) BIT 20 sound/soc/codecs/zx_aud96p22.c #define RST_DAC_DPZ BIT(0) BIT 21 sound/soc/codecs/zx_aud96p22.c #define RST_ADC_DPZ BIT(1) BIT 23 sound/soc/codecs/zx_aud96p22.c #define I2S1_MS_MODE BIT(3) BIT 492 sound/soc/dwc/dwc-i2s.c comp1 = comp1 & ~BIT(5); BIT 496 sound/soc/dwc/dwc-i2s.c comp1 = comp1 & ~BIT(6); BIT 29 sound/soc/dwc/local.h #define ISR_TXFO BIT(5) BIT 30 sound/soc/dwc/local.h #define ISR_TXFE BIT(4) BIT 31 sound/soc/dwc/local.h #define ISR_RXFO BIT(1) BIT 32 sound/soc/dwc/local.h #define ISR_RXDA BIT(0) BIT 66 sound/soc/dwc/local.h #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6) BIT 67 sound/soc/dwc/local.h #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5) BIT 68 sound/soc/dwc/local.h #define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4) BIT 136 sound/soc/fsl/fsl_audmix.c if (!(priv->tdms & BIT(mix_clk))) { BIT 143 sound/soc/fsl/fsl_audmix.c if (!(priv->tdms & BIT(val))) { BIT 187 sound/soc/fsl/fsl_audmix.c if (!(priv->tdms & BIT(mix_clk))) { BIT 300 sound/soc/fsl/fsl_audmix.c priv->tdms |= BIT(dai->driver->id); BIT 307 sound/soc/fsl/fsl_audmix.c priv->tdms &= ~BIT(dai->driver->id); BIT 36 sound/soc/fsl/fsl_audmix.h #define FSL_AUDMIX_CTR_MIXCLK_MASK BIT(FSL_AUDMIX_CTR_MIXCLK_SHIFT) BIT 47 sound/soc/fsl/fsl_audmix.h #define FSL_AUDMIX_CTR_OUTCKPOL_MASK BIT(FSL_AUDMIX_CTR_OUTCKPOL_SHIFT) BIT 50 sound/soc/fsl/fsl_audmix.h #define FSL_AUDMIX_CTR_MASKRTDF_MASK BIT(FSL_AUDMIX_CTR_MASKRTDF_SHIFT) BIT 53 sound/soc/fsl/fsl_audmix.h #define FSL_AUDMIX_CTR_MASKCKDF_MASK BIT(FSL_AUDMIX_CTR_MASKCKDF_SHIFT) BIT 56 sound/soc/fsl/fsl_audmix.h #define FSL_AUDMIX_CTR_SYNCMODE_MASK BIT(FSL_AUDMIX_CTR_SYNCMODE_SHIFT) BIT 59 sound/soc/fsl/fsl_audmix.h #define FSL_AUDMIX_CTR_SYNCSRC_MASK BIT(FSL_AUDMIX_CTR_SYNCSRC_SHIFT) BIT 63 sound/soc/fsl/fsl_audmix.h #define FSL_AUDMIX_STR_RATEDIFF BIT(0) BIT 64 sound/soc/fsl/fsl_audmix.h #define FSL_AUDMIX_STR_CLKDIFF BIT(1) BIT 70 sound/soc/fsl/fsl_audmix.h #define FSL_AUDMIX_ATCR_AT_EN BIT(0) BIT 71 sound/soc/fsl/fsl_audmix.h #define FSL_AUDMIX_ATCR_AT_UPDN BIT(1) BIT 37 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_MDIS_MASK BIT(MICFIL_CTRL1_MDIS_SHIFT) BIT 38 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_MDIS BIT(MICFIL_CTRL1_MDIS_SHIFT) BIT 40 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_DOZEN_MASK BIT(MICFIL_CTRL1_DOZEN_SHIFT) BIT 41 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_DOZEN BIT(MICFIL_CTRL1_DOZEN_SHIFT) BIT 43 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_PDMIEN_MASK BIT(MICFIL_CTRL1_PDMIEN_SHIFT) BIT 44 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_PDMIEN BIT(MICFIL_CTRL1_PDMIEN_SHIFT) BIT 46 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_DBG_MASK BIT(MICFIL_CTRL1_DBG_SHIFT) BIT 47 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_DBG BIT(MICFIL_CTRL1_DBG_SHIFT) BIT 49 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_SRES_MASK BIT(MICFIL_CTRL1_SRES_SHIFT) BIT 50 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_SRES BIT(MICFIL_CTRL1_SRES_SHIFT) BIT 52 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_DBGE_MASK BIT(MICFIL_CTRL1_DBGE_SHIFT) BIT 53 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_DBGE BIT(MICFIL_CTRL1_DBGE_SHIFT) BIT 56 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \ BIT 61 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_ERREN_MASK BIT(MICFIL_CTRL1_ERREN_SHIFT) BIT 62 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_ERREN BIT(MICFIL_CTRL1_ERREN_SHIFT) BIT 65 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT) BIT 71 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL2_QSEL_MASK ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \ BIT 73 sound/soc/fsl/fsl_micfil.h #define MICFIL_HIGH_QUALITY BIT(MICFIL_CTRL2_QSEL_SHIFT) BIT 82 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL2_CICOSR_MASK ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \ BIT 88 sound/soc/fsl/fsl_micfil.h #define MICFIL_CTRL2_CLKDIV_MASK ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \ BIT 95 sound/soc/fsl/fsl_micfil.h #define MICFIL_STAT_BSY_FIL_MASK BIT(MICFIL_STAT_BSY_FIL_SHIFT) BIT 96 sound/soc/fsl/fsl_micfil.h #define MICFIL_STAT_BSY_FIL BIT(MICFIL_STAT_BSY_FIL_SHIFT) BIT 98 sound/soc/fsl/fsl_micfil.h #define MICFIL_STAT_FIR_RDY_MASK BIT(MICFIL_STAT_FIR_RDY_SHIFT) BIT 99 sound/soc/fsl/fsl_micfil.h #define MICFIL_STAT_FIR_RDY BIT(MICFIL_STAT_FIR_RDY_SHIFT) BIT 101 sound/soc/fsl/fsl_micfil.h #define MICFIL_STAT_LOWFREQF_MASK BIT(MICFIL_STAT_LOWFREQF_SHIFT) BIT 102 sound/soc/fsl/fsl_micfil.h #define MICFIL_STAT_LOWFREQF BIT(MICFIL_STAT_LOWFREQF_SHIFT) BIT 104 sound/soc/fsl/fsl_micfil.h #define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) BIT 105 sound/soc/fsl/fsl_micfil.h #define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) BIT 110 sound/soc/fsl/fsl_micfil.h #define MICFIL_FIFO_CTRL_FIFOWMK_MASK ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \ BIT 117 sound/soc/fsl/fsl_micfil.h #define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v)) BIT 119 sound/soc/fsl/fsl_micfil.h #define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v)) BIT 124 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_CHSEL_MASK ((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \ BIT 130 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_CICOSR_MASK ((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \ BIT 136 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_INITT_MASK ((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \ BIT 141 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_ST10_MASK BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT) BIT 142 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_ST10 BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT) BIT 144 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_ERIE_MASK BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT) BIT 145 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_ERIE BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT) BIT 147 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_IE_MASK BIT(MICFIL_VAD0_CTRL1_IE_SHIFT) BIT 148 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_IE BIT(MICFIL_VAD0_CTRL1_IE_SHIFT) BIT 150 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_RST_MASK BIT(MICFIL_VAD0_CTRL1_RST_SHIFT) BIT 151 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_RST BIT(MICFIL_VAD0_CTRL1_RST_SHIFT) BIT 153 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_EN_MASK BIT(MICFIL_VAD0_CTRL1_EN_SHIFT) BIT 154 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL1_EN BIT(MICFIL_VAD0_CTRL1_EN_SHIFT) BIT 158 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL2_FRENDIS_MASK BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT) BIT 159 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL2_FRENDIS BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT) BIT 161 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL2_PREFEN_MASK BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT) BIT 162 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL2_PREFEN BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT) BIT 164 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL2_FOUTDIS_MASK BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT) BIT 165 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL2_FOUTDIS BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT) BIT 168 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \ BIT 174 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL2_INPGAIN_MASK ((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \ BIT 180 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_CTRL2_HPF_MASK ((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \ BIT 187 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_SCONFIG_SFILEN_MASK BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT) BIT 188 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_SCONFIG_SFILEN BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT) BIT 190 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_SCONFIG_SMAXEN_MASK BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT) BIT 191 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_SCONFIG_SMAXEN BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT) BIT 194 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \ BIT 201 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_NCONFIG_NFILAUT_MASK BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT) BIT 202 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_NCONFIG_NFILAUT BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT) BIT 204 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_NCONFIG_NMINEN_MASK BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT) BIT 205 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_NCONFIG_NMINEN BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT) BIT 207 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_NCONFIG_NDECEN_MASK BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT) BIT 208 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_NCONFIG_NDECEN BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT) BIT 210 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_NCONFIG_NOREN BIT(MICFIL_VAD0_NCONFIG_NOREN_SHIFT) BIT 213 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \ BIT 219 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_NCONFIG_NGAIN_MASK ((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \ BIT 227 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_ZCD_ZCDTH_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \ BIT 233 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_ZCD_ZCDADJ_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\ BIT 238 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_ZCD_ZCDAND_MASK BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT) BIT 239 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_ZCD_ZCDAND BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT) BIT 241 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_ZCD_ZCDAUT_MASK BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT) BIT 242 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_ZCD_ZCDAUT BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT) BIT 244 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_ZCD_ZCDEN_MASK BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT) BIT 245 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_ZCD_ZCDEN BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT) BIT 249 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_STAT_INITF_MASK BIT(MICFIL_VAD0_STAT_INITF_SHIFT) BIT 250 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_STAT_INITF BIT(MICFIL_VAD0_STAT_INITF_SHIFT) BIT 252 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_STAT_INSATF_MASK BIT(MICFIL_VAD0_STAT_INSATF_SHIFT) BIT 253 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_STAT_INSATF BIT(MICFIL_VAD0_STAT_INSATF_SHIFT) BIT 255 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_STAT_EF_MASK BIT(MICFIL_VAD0_STAT_EF_SHIFT) BIT 256 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_STAT_EF BIT(MICFIL_VAD0_STAT_EF_SHIFT) BIT 258 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_STAT_IF_MASK BIT(MICFIL_VAD0_STAT_IF_SHIFT) BIT 259 sound/soc/fsl/fsl_micfil.h #define MICFIL_VAD0_STAT_IF BIT(MICFIL_VAD0_STAT_IF_SHIFT) BIT 274 sound/soc/fsl/fsl_micfil.h #define FIFO_LEN BIT(FIFO_PTRWID) BIT 448 sound/soc/fsl/fsl_sai.c if (!(sai->mclk_streams & BIT(substream->stream))) { BIT 453 sound/soc/fsl/fsl_sai.c sai->mclk_streams |= BIT(substream->stream); BIT 517 sound/soc/fsl/fsl_sai.c sai->mclk_streams & BIT(substream->stream)) { BIT 519 sound/soc/fsl/fsl_sai.c sai->mclk_streams &= ~BIT(substream->stream); BIT 1100 sound/soc/fsl/fsl_sai.c if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) BIT 1103 sound/soc/fsl/fsl_sai.c if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) BIT 1126 sound/soc/fsl/fsl_sai.c if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { BIT 1132 sound/soc/fsl/fsl_sai.c if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { BIT 1152 sound/soc/fsl/fsl_sai.c if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) BIT 1155 sound/soc/fsl/fsl_sai.c if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) BIT 75 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_TERE BIT(31) BIT 76 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_FR BIT(25) BIT 77 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_SR BIT(24) BIT 82 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_WSF BIT(20) BIT 83 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_SEF BIT(19) BIT 84 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_FEF BIT(18) BIT 85 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_FWF BIT(17) BIT 86 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_FRF BIT(16) BIT 89 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_WSIE BIT(12) BIT 90 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_SEIE BIT(11) BIT 91 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_FEIE BIT(10) BIT 92 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_FWIE BIT(9) BIT 93 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_FRIE BIT(8) BIT 94 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CSR_FRDE BIT(0) BIT 100 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR2_SYNC BIT(30) BIT 103 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26) BIT 104 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR2_MSEL_MCLK2 BIT(27) BIT 105 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27)) BIT 107 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR2_BCP BIT(25) BIT 108 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR2_BCD_MSTR BIT(24) BIT 112 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR3_TRCE BIT(16) BIT 122 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR4_MF BIT(4) BIT 123 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR4_FSE BIT(3) BIT 124 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR4_FSP BIT(1) BIT 125 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR4_FSD_MSTR BIT(0) BIT 136 sound/soc/fsl/fsl_sai.h #define FSL_SAI_DMA BIT(0) BIT 137 sound/soc/fsl/fsl_sai.h #define FSL_SAI_USE_AC97 BIT(1) BIT 138 sound/soc/fsl/fsl_sai.h #define FSL_SAI_NET BIT(2) BIT 139 sound/soc/fsl/fsl_sai.h #define FSL_SAI_TRA_SYN BIT(3) BIT 140 sound/soc/fsl/fsl_sai.h #define FSL_SAI_REC_SYN BIT(4) BIT 141 sound/soc/fsl/fsl_sai.h #define FSL_SAI_USE_I2S_SLAVE BIT(5) BIT 474 sound/soc/fsl/fsl_ssi.c ssi->streams |= BIT(dir); BIT 514 sound/soc/fsl/fsl_ssi.c aactive = ssi->streams & BIT(adir); BIT 531 sound/soc/fsl/fsl_ssi.c ssi->streams &= ~BIT(dir); BIT 711 sound/soc/fsl/fsl_ssi.c baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream)); BIT 808 sound/soc/fsl/fsl_ssi.c if (!(ssi->baudclk_streams & BIT(substream->stream))) { BIT 813 sound/soc/fsl/fsl_ssi.c ssi->baudclk_streams |= BIT(substream->stream); BIT 860 sound/soc/fsl/fsl_ssi.c ssi->baudclk_streams & BIT(substream->stream)) { BIT 862 sound/soc/fsl/fsl_ssi.c ssi->baudclk_streams &= ~BIT(substream->stream); BIT 104 sound/soc/fsl/imx-audmix.c ret = snd_soc_dai_set_tdm_slot(rtd->cpu_dai, BIT(channels) - 1, BIT 105 sound/soc/fsl/imx-audmix.c BIT(channels) - 1, 8, 32); BIT 100 sound/soc/hisilicon/hi6210-i2s.c if (val & BIT(4)) BIT 101 sound/soc/hisilicon/hi6210-i2s.c regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4)); BIT 120 sound/soc/hisilicon/hi6210-i2s.c regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9)); BIT 123 sound/soc/hisilicon/hi6210-i2s.c regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5)); BIT 126 sound/soc/hisilicon/hi6210-i2s.c regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5)); BIT 127 sound/soc/hisilicon/hi6210-i2s.c regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5)); BIT 137 sound/soc/hisilicon/hi6210-i2s.c val |= (BIT(5) | BIT(4)); BIT 141 sound/soc/hisilicon/hi6210-i2s.c val &= ~(BIT(5) | BIT(4)); BIT 179 sound/soc/hisilicon/hi6210-i2s.c regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5)); BIT 342 sound/soc/hisilicon/hi6210-i2s.c val |= (BIT(19) | BIT(18) | BIT(17) | BIT 29 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_SW_RST_N__SW_RST_N BIT(0) BIT 41 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN BIT(25) BIT 42 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN BIT(24) BIT 43 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN BIT(20) BIT 44 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN BIT(16) BIT 45 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN BIT(15) BIT 46 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN BIT(14) BIT 47 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN BIT(13) BIT 48 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__S2_IL_PGA_EN BIT(12) BIT 49 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__S1_IR_PGA_EN BIT(10) BIT 50 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__S1_IL_PGA_EN BIT(9) BIT 51 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__S1_IF_CLK_EN BIT(8) BIT 52 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_SRC_EN BIT(7) BIT 53 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_EN BIT(6) BIT 54 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__ST_DL_R_EN BIT(5) BIT 55 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__ST_DL_L_EN BIT(4) BIT 56 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_R_EN BIT(3) BIT 57 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_L_EN BIT(2) BIT 58 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_R_EN BIT(1) BIT 59 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_L_EN BIT(0) BIT 62 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN BIT(30) BIT 63 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN BIT(28) BIT 64 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN BIT(25) BIT 65 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN BIT(24) BIT 66 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN BIT(22) BIT 67 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN BIT(20) BIT 68 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN BIT(17) BIT 69 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN BIT(16) BIT 99 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S2_IF_TX_EN BIT(31) BIT 100 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S2_IF_RX_EN BIT(30) BIT 101 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S2_FRAME_MODE BIT(29) BIT 102 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S2_MST_SLV BIT(28) BIT 103 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S2_LRCK_MODE BIT(27) BIT 104 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S2_CHNNL_MODE BIT(26) BIT 109 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S2_TX_CLK_SEL BIT(21) BIT 110 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S2_RX_CLK_SEL BIT(20) BIT 111 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT BIT(19) BIT 114 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S1_IF_TX_EN BIT(15) BIT 115 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S1_IF_RX_EN BIT(14) BIT 116 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S1_FRAME_MODE BIT(13) BIT 117 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S1_MST_SLV BIT(12) BIT 118 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S1_LRCK_MODE BIT(11) BIT 119 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S1_CHNNL_MODE BIT(10) BIT 124 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S1_TX_CLK_SEL BIT(5) BIT 125 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S1_RX_CLK_SEL BIT(4) BIT 126 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_I2S_CFG__S1_CODEC_DATA_FORMAT BIT(3) BIT 142 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN4_MUTE BIT(27) BIT 143 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN3_MUTE BIT(26) BIT 144 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE BIT(25) BIT 145 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN1_MUTE BIT(24) BIT 148 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN4_MUTE BIT(19) BIT 149 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN3_MUTE BIT(18) BIT 150 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE BIT(17) BIT 151 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN1_MUTE BIT(16) BIT 152 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACR_SDM_DITHER BIT(9) BIT 153 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACL_SDM_DITHER BIT(8) BIT 169 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE BIT(13) BIT 170 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE BIT(12) BIT 173 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE BIT(9) BIT 174 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE BIT(8) BIT 175 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_RDY BIT(6) BIT 178 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_RDY BIT(3) BIT 225 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__THIRDMD_DLINK_TEST_SEL BIT(17) BIT 226 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__THIRDMD_DLINK_DIN_SEL BIT(16) BIT 227 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__S3_DOUT_RIGHT_SEL BIT(14) BIT 228 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__S3_DOUT_LEFT_SEL BIT(13) BIT 229 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__S3_DIN_TEST_SEL BIT(12) BIT 230 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__VOICE_DLINK_SRC_UP_DOUT_VLD_SEL BIT(8) BIT 231 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__VOICE_DLINK_TEST_SEL BIT(7) BIT 232 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__VOICE_DLINK_DIN_SEL BIT(6) BIT 233 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__ST_DL_TEST_SEL BIT(4) BIT 234 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL BIT(3) BIT 235 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__S2_DOUT_TEST_SEL BIT(2) BIT 236 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__S1_DOUT_TEST_SEL BIT(1) BIT 237 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_MISC_CFG__S2_DOUT_LEFT_SEL BIT(0) BIT 251 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_CLK_SEL__I2S_BT_FM_SEL BIT(0) BIT 253 sound/soc/hisilicon/hi6210-i2s.h #define HII2S_CLK_SEL__EXT_12_288MHZ_SEL BIT(1) BIT 31 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CTL_16PACK_MASK BIT(1) BIT 32 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CTL_ME_MASK BIT(0) BIT 37 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_FEN_MASK BIT(14) BIT 38 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_FMODE_MASK BIT(13) BIT 39 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_16PACK_MASK BIT(12) BIT 40 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_JUST_MASK BIT(10) BIT 41 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_PACKH_MASK BIT(9) BIT 42 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK BIT(8) BIT 43 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_BLKP_MASK BIT(7) BIT 44 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK BIT(6) BIT 45 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_LRD_MASK BIT(3) BIT 46 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_FW_MASK BIT(2) BIT 47 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_SW_MASK BIT(1) BIT 48 sound/soc/img/img-i2s-in.c #define IMG_I2S_IN_CH_CTL_ME_MASK BIT(0) BIT 29 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CTL_DATA_EN_MASK BIT(24) BIT 32 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CTL_FRM_SIZE_MASK BIT(8) BIT 33 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CTL_MASTER_MASK BIT(6) BIT 34 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CTL_CLK_MASK BIT(5) BIT 35 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CTL_CLK_EN_MASK BIT(4) BIT 36 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK BIT(3) BIT 37 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CTL_BCLK_POL_MASK BIT(2) BIT 38 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CTL_ME_MASK BIT(0) BIT 41 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CHAN_CTL_CH_MASK BIT(11) BIT 42 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CHAN_CTL_LT_MASK BIT(10) BIT 45 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CHAN_CTL_JUST_MASK BIT(3) BIT 46 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CHAN_CTL_CLKT_MASK BIT(1) BIT 47 sound/soc/img/img-i2s-out.c #define IMG_I2S_OUT_CHAN_CTL_ME_MASK BIT(0) BIT 29 sound/soc/img/img-parallel-out.c #define IMG_PRL_OUT_CTL_CH_MASK BIT(4) BIT 30 sound/soc/img/img-parallel-out.c #define IMG_PRL_OUT_CTL_PACKH_MASK BIT(3) BIT 31 sound/soc/img/img-parallel-out.c #define IMG_PRL_OUT_CTL_EDGE_MASK BIT(2) BIT 32 sound/soc/img/img-parallel-out.c #define IMG_PRL_OUT_CTL_ME_MASK BIT(1) BIT 33 sound/soc/img/img-parallel-out.c #define IMG_PRL_OUT_CTL_SRST_MASK BIT(0) BIT 37 sound/soc/img/img-spdif-in.c #define IMG_SPDIF_IN_CTL_SRT_MASK BIT(31) BIT 42 sound/soc/img/img-spdif-in.c #define IMG_SPDIF_IN_STATUS_LOCK_MASK BIT(15) BIT 58 sound/soc/img/img-spdif-in.c #define IMG_SPDIF_IN_SOFT_RESET_MASK BIT(0) BIT 29 sound/soc/img/img-spdif-out.c #define IMG_SPDIF_OUT_CTL_FS_MASK BIT(4) BIT 30 sound/soc/img/img-spdif-out.c #define IMG_SPDIF_OUT_CTL_CLK_MASK BIT(2) BIT 31 sound/soc/img/img-spdif-out.c #define IMG_SPDIF_OUT_CTL_SRT_MASK BIT(0) BIT 557 sound/soc/intel/atom/sst-atom-controls.c is_set = reg & BIT(i); BIT 60 sound/soc/intel/boards/byt-rt5640.c #define BYT_RT5640_DMIC_EN BIT(16) BIT 50 sound/soc/intel/boards/bytcht_es8316.c #define BYT_CHT_ES8316_SSP0 BIT(16) BIT 51 sound/soc/intel/boards/bytcht_es8316.c #define BYT_CHT_ES8316_MONO_SPEAKER BIT(17) BIT 52 sound/soc/intel/boards/bytcht_es8316.c #define BYT_CHT_ES8316_JD_INVERTED BIT(18) BIT 67 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_JD_NOT_INV BIT(16) BIT 68 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_MONO_SPEAKER BIT(17) BIT 69 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_DIFF_MIC BIT(18) /* default is single-ended */ BIT 70 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_SSP2_AIF2 BIT(19) /* default is using AIF1 */ BIT 71 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_SSP0_AIF1 BIT(20) BIT 72 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_SSP0_AIF2 BIT(21) BIT 73 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_MCLK_EN BIT(22) BIT 74 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_MCLK_25MHZ BIT(23) BIT 65 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_DMIC_EN BIT(16) BIT 66 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_MCLK_EN BIT(17) BIT 67 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_MCLK_25MHZ BIT(18) BIT 68 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_SSP2_AIF2 BIT(19) /* default is using AIF1 */ BIT 69 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_SSP0_AIF1 BIT(20) BIT 70 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_SSP0_AIF2 BIT(21) BIT 71 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_HP_LR_SWAPPED BIT(22) BIT 72 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_MONO_SPEAKER BIT(23) BIT 73 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_JD_NOT_INV BIT(24) BIT 48 sound/soc/intel/boards/cht_bsw_rt5645.c #define CHT_RT5645_SSP2_AIF2 BIT(16) /* default is using AIF1 */ BIT 49 sound/soc/intel/boards/cht_bsw_rt5645.c #define CHT_RT5645_SSP0_AIF1 BIT(17) BIT 50 sound/soc/intel/boards/cht_bsw_rt5645.c #define CHT_RT5645_SSP0_AIF2 BIT(18) BIT 51 sound/soc/intel/boards/cht_bsw_rt5645.c #define CHT_RT5645_PMC_PLT_CLK_0 BIT(19) BIT 29 sound/soc/intel/boards/sof_rt5682.c #define SOF_RT5682_MCLK_EN BIT(3) BIT 30 sound/soc/intel/boards/sof_rt5682.c #define SOF_RT5682_MCLK_24MHZ BIT(4) BIT 31 sound/soc/intel/boards/sof_rt5682.c #define SOF_SPEAKER_AMP_PRESENT BIT(5) BIT 36 sound/soc/intel/boards/sof_rt5682.c #define SOF_RT5682_MCLK_BYTCHT_EN BIT(9) BIT 32 sound/soc/intel/skylake/cnl-sst-dsp.h #define CNL_ADSP_REG_HIPCTDR_BUSY BIT(31) BIT 35 sound/soc/intel/skylake/cnl-sst-dsp.h #define CNL_ADSP_REG_HIPCTDA_DONE BIT(31) BIT 38 sound/soc/intel/skylake/cnl-sst-dsp.h #define CNL_ADSP_REG_HIPCIDR_BUSY BIT(31) BIT 41 sound/soc/intel/skylake/cnl-sst-dsp.h #define CNL_ADSP_REG_HIPCIDA_DONE BIT(31) BIT 44 sound/soc/intel/skylake/cnl-sst-dsp.h #define CNL_ADSP_REG_HIPCCTL_DONE BIT(1) BIT 45 sound/soc/intel/skylake/cnl-sst-dsp.h #define CNL_ADSP_REG_HIPCCTL_BUSY BIT(0) BIT 48 sound/soc/intel/skylake/cnl-sst-dsp.h #define CNL_ADSP_REG_HIPCT_BUSY BIT(31) BIT 39 sound/soc/intel/skylake/skl-sst-dsp.h #define SKL_ADSP_REG_HIPCI_BUSY BIT(31) BIT 42 sound/soc/intel/skylake/skl-sst-dsp.h #define SKL_ADSP_REG_HIPCIE_DONE BIT(30) BIT 45 sound/soc/intel/skylake/skl-sst-dsp.h #define SKL_ADSP_REG_HIPCCTL_DONE BIT(1) BIT 46 sound/soc/intel/skylake/skl-sst-dsp.h #define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0) BIT 49 sound/soc/intel/skylake/skl-sst-dsp.h #define SKL_ADSP_REG_HIPCT_BUSY BIT(31) BIT 78 sound/soc/intel/skylake/skl-sst-dsp.h #define SKL_DSP_CORE_MASK(c) BIT(c) BIT 84 sound/soc/intel/skylake/skl-sst-dsp.h #define SKL_DSP_CORE0_MASK BIT(0) BIT 30 sound/soc/intel/skylake/skl-topology.c #define SKL_IN_DIR_BIT_MASK BIT(0) BIT 28 sound/soc/intel/skylake/skl.h #define AZX_PGCTL_ADSPPGD BIT(2) BIT 31 sound/soc/intel/skylake/skl.h #define AZX_CGCTL_ADSPDCGE BIT(1) BIT 40 sound/soc/intel/skylake/skl.h #define AZX_VS_EM2_DUM BIT(23) BIT 41 sound/soc/intel/skylake/skl.h #define AZX_REG_VS_EM2_L1SEN BIT(13) BIT 42 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) BIT 43 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) BIT 44 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CONF_I2S BIT(4) BIT 45 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CONF_RESET BIT(3) BIT 46 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) BIT 47 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) BIT 48 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CONF_ENABLE BIT(0) BIT 61 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) BIT 62 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) BIT 63 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) BIT 64 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) BIT 65 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) BIT 66 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_FLUSH BIT(8) BIT 67 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) BIT 68 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) BIT 69 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) BIT 70 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) BIT 71 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) BIT 72 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) BIT 73 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) BIT 78 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) BIT 79 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) BIT 80 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) BIT 81 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_I2S_FMT_MSB BIT(0) BIT 83 sound/soc/jz4740/jz4740-i2s.c #define JZ_AIC_I2S_STATUS_BUSY BIT(2) BIT 17 sound/soc/mediatek/common/mtk-btcvsd.c #define BT_CVSD_TX_NREADY BIT(21) BIT 18 sound/soc/mediatek/common/mtk-btcvsd.c #define BT_CVSD_RX_READY BIT(22) BIT 19 sound/soc/mediatek/common/mtk-btcvsd.c #define BT_CVSD_TX_UNDERFLOW BIT(23) BIT 20 sound/soc/mediatek/common/mtk-btcvsd.c #define BT_CVSD_RX_OVERFLOW BIT(24) BIT 21 sound/soc/mediatek/common/mtk-btcvsd.c #define BT_CVSD_INTERRUPT BIT(31) BIT 37 sound/soc/meson/axg-fifo.h #define FIFO_INT_ADDR_FINISH BIT(0) BIT 38 sound/soc/meson/axg-fifo.h #define FIFO_INT_ADDR_INT BIT(1) BIT 39 sound/soc/meson/axg-fifo.h #define FIFO_INT_COUNT_REPEAT BIT(2) BIT 40 sound/soc/meson/axg-fifo.h #define FIFO_INT_COUNT_ONCE BIT(3) BIT 41 sound/soc/meson/axg-fifo.h #define FIFO_INT_FIFO_ZERO BIT(4) BIT 42 sound/soc/meson/axg-fifo.h #define FIFO_INT_FIFO_DEPTH BIT(5) BIT 46 sound/soc/meson/axg-fifo.h #define CTRL0_DMA_EN BIT(31) BIT 19 sound/soc/meson/axg-frddr.c #define CTRL0_FRDDR_PP_MODE BIT(30) BIT 25 sound/soc/meson/axg-frddr.c #define CTRL1_FRDDR_FORCE_FINISH BIT(12) BIT 16 sound/soc/meson/axg-pdm.c #define PDM_CTRL_EN BIT(31) BIT 17 sound/soc/meson/axg-pdm.c #define PDM_CTRL_OUT_MODE BIT(29) BIT 18 sound/soc/meson/axg-pdm.c #define PDM_CTRL_BYPASS_MODE BIT(28) BIT 19 sound/soc/meson/axg-pdm.c #define PDM_CTRL_RST_FIFO BIT(16) BIT 25 sound/soc/meson/axg-pdm.c #define PDM_FILTER_EN BIT(31) BIT 16 sound/soc/meson/axg-spdifin.c #define SPDIFIN_CTRL0_EN BIT(31) BIT 17 sound/soc/meson/axg-spdifin.c #define SPDIFIN_CTRL0_RST_OUT BIT(29) BIT 18 sound/soc/meson/axg-spdifin.c #define SPDIFIN_CTRL0_RST_IN BIT(28) BIT 19 sound/soc/meson/axg-spdifin.c #define SPDIFIN_CTRL0_WIDTH_SEL BIT(24) BIT 23 sound/soc/meson/axg-spdifin.c #define SPDIFIN_CTRL0_CHK_VALID BIT(3) BIT 40 sound/soc/meson/axg-spdifin.c #define SPDIFIN_IRQ_MODE_CHANGED BIT(2) BIT 26 sound/soc/meson/axg-spdifout.c #define SPDIFOUT_CTRL0_EN BIT(31) BIT 27 sound/soc/meson/axg-spdifout.c #define SPDIFOUT_CTRL0_RST_OUT BIT(29) BIT 28 sound/soc/meson/axg-spdifout.c #define SPDIFOUT_CTRL0_RST_IN BIT(28) BIT 29 sound/soc/meson/axg-spdifout.c #define SPDIFOUT_CTRL0_USEL BIT(26) BIT 30 sound/soc/meson/axg-spdifout.c #define SPDIFOUT_CTRL0_USET BIT(25) BIT 31 sound/soc/meson/axg-spdifout.c #define SPDIFOUT_CTRL0_CHSTS_SEL BIT(24) BIT 32 sound/soc/meson/axg-spdifout.c #define SPDIFOUT_CTRL0_DATA_SEL BIT(20) BIT 33 sound/soc/meson/axg-spdifout.c #define SPDIFOUT_CTRL0_MSB_FIRST BIT(19) BIT 34 sound/soc/meson/axg-spdifout.c #define SPDIFOUT_CTRL0_VSEL BIT(18) BIT 35 sound/soc/meson/axg-spdifout.c #define SPDIFOUT_CTRL0_VSET BIT(17) BIT 15 sound/soc/meson/axg-tdmin.c #define TDMIN_CTRL_ENABLE BIT(31) BIT 16 sound/soc/meson/axg-tdmin.c #define TDMIN_CTRL_I2S_MODE BIT(30) BIT 17 sound/soc/meson/axg-tdmin.c #define TDMIN_CTRL_RST_OUT BIT(29) BIT 18 sound/soc/meson/axg-tdmin.c #define TDMIN_CTRL_RST_IN BIT(28) BIT 19 sound/soc/meson/axg-tdmin.c #define TDMIN_CTRL_WS_INV BIT(25) BIT 23 sound/soc/meson/axg-tdmin.c #define TDMIN_CTRL_LSB_FIRST BIT(5) BIT 21 sound/soc/meson/axg-tdmout.c #define TDMOUT_CTRL0_ENABLE BIT(31) BIT 22 sound/soc/meson/axg-tdmout.c #define TDMOUT_CTRL0_RST_OUT BIT(29) BIT 23 sound/soc/meson/axg-tdmout.c #define TDMOUT_CTRL0_RST_IN BIT(28) BIT 32 sound/soc/meson/axg-tdmout.c #define TDMOUT_CTRL1_WS_INV BIT(28) BIT 18 sound/soc/meson/axg-toddr.c #define CTRL0_TODDR_SEL_RESAMPLE BIT(30) BIT 19 sound/soc/meson/axg-toddr.c #define CTRL0_TODDR_EXT_SIGNED BIT(29) BIT 20 sound/soc/meson/axg-toddr.c #define CTRL0_TODDR_PP_MODE BIT(28) BIT 27 sound/soc/meson/axg-toddr.c #define CTRL1_TODDR_FORCE_FINISH BIT(25) BIT 22 sound/soc/meson/g12a-tohdmitx.c #define CTRL0_I2S_BLK_CAP_INV BIT(7) BIT 23 sound/soc/meson/g12a-tohdmitx.c #define CTRL0_I2S_BCLK_O_INV BIT(6) BIT 25 sound/soc/meson/g12a-tohdmitx.c #define CTRL0_SPDIF_CLK_CAP_INV BIT(3) BIT 26 sound/soc/meson/g12a-tohdmitx.c #define CTRL0_SPDIF_CLK_O_INV BIT(2) BIT 27 sound/soc/meson/g12a-tohdmitx.c #define CTRL0_SPDIF_SEL BIT(1) BIT 28 sound/soc/meson/g12a-tohdmitx.c #define CTRL0_SPDIF_CLK_SEL BIT(0) BIT 28 sound/soc/qcom/apq8016_sbc.c #define MIC_CTRL_TER_WS_SLAVE_SEL BIT(21) BIT 29 sound/soc/qcom/apq8016_sbc.c #define MIC_CTRL_QUA_WS_SLAVE_SEL_10 BIT(17) BIT 30 sound/soc/qcom/apq8016_sbc.c #define MIC_CTRL_TLMM_SCLK_EN BIT(1) BIT 31 sound/soc/qcom/apq8016_sbc.c #define SPKR_CTL_PRI_WS_SLAVE_SEL_11 (BIT(17) | BIT(16)) BIT 164 sound/soc/qcom/lpass-lpaif-reg.h #define LPAIF_DMACTL_DYNCLK_MASK BIT(12) BIT 1398 sound/soc/qcom/qdsp6/q6afe-dai.c priv->sd_line_mask |= BIT(lines[i]); BIT 52 sound/soc/qcom/qdsp6/q6afe.c #define AFE_PORT_I2S_SD0_MASK BIT(0x0) BIT 53 sound/soc/qcom/qdsp6/q6afe.c #define AFE_PORT_I2S_SD1_MASK BIT(0x1) BIT 54 sound/soc/qcom/qdsp6/q6afe.c #define AFE_PORT_I2S_SD2_MASK BIT(0x2) BIT 55 sound/soc/qcom/qdsp6/q6afe.c #define AFE_PORT_I2S_SD3_MASK BIT(0x3) BIT 23 sound/soc/rockchip/rockchip_i2s.h #define I2S_TXCR_HWT BIT(14) BIT 53 sound/soc/rockchip/rockchip_i2s.h #define I2S_RXCR_HWT BIT(14) BIT 148 sound/soc/rockchip/rockchip_i2s.h #define I2S_INTCR_RXOIC BIT(18) BIT 158 sound/soc/rockchip/rockchip_i2s.h #define I2S_INTCR_TXUIC BIT(2) BIT 198 sound/soc/rockchip/rockchip_i2s.h #define I2S_CLR_RXC BIT(1) BIT 199 sound/soc/rockchip/rockchip_i2s.h #define I2S_CLR_TXC BIT(0) BIT 36 sound/soc/rockchip/rockchip_pdm.h #define PDM_MODE_MSK BIT(31) BIT 38 sound/soc/rockchip/rockchip_pdm.h #define PDM_MODE_LJ BIT(31) BIT 39 sound/soc/rockchip/rockchip_pdm.h #define PDM_PATH3_EN BIT(30) BIT 40 sound/soc/rockchip/rockchip_pdm.h #define PDM_PATH2_EN BIT(29) BIT 41 sound/soc/rockchip/rockchip_pdm.h #define PDM_PATH1_EN BIT(28) BIT 42 sound/soc/rockchip/rockchip_pdm.h #define PDM_PATH0_EN BIT(27) BIT 43 sound/soc/rockchip/rockchip_pdm.h #define PDM_HWT_EN BIT(26) BIT 54 sound/soc/rockchip/rockchip_pdm.h #define PDM_CLK_FD_RATIO_MSK BIT(6) BIT 56 sound/soc/rockchip/rockchip_pdm.h #define PDM_CLK_FD_RATIO_35 BIT(6) BIT 57 sound/soc/rockchip/rockchip_pdm.h #define PDM_CLK_MSK BIT(5) BIT 58 sound/soc/rockchip/rockchip_pdm.h #define PDM_CLK_EN BIT(5) BIT 60 sound/soc/rockchip/rockchip_pdm.h #define PDM_CKP_MSK BIT(3) BIT 62 sound/soc/rockchip/rockchip_pdm.h #define PDM_CKP_INVERTED BIT(3) BIT 71 sound/soc/rockchip/rockchip_pdm.h #define PDM_HPF_LE BIT(3) BIT 72 sound/soc/rockchip/rockchip_pdm.h #define PDM_HPF_RE BIT(2) BIT 80 sound/soc/rockchip/rockchip_pdm.h #define PDM_DMA_RD_MSK BIT(8) BIT 81 sound/soc/rockchip/rockchip_pdm.h #define PDM_DMA_RD_EN BIT(8) BIT 301 sound/soc/rockchip/rockchip_spdif.c regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16); BIT 22 sound/soc/soc-generic-dmaengine-pcm.c #define SND_DMAENGINE_PCM_FLAG_NO_RESIDUE BIT(31) BIT 123 sound/soc/soc-generic-dmaengine-pcm.c u32 addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT 124 sound/soc/soc-generic-dmaengine-pcm.c BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT 125 sound/soc/soc-generic-dmaengine-pcm.c BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); BIT 151 sound/soc/soc-ops.c if (!(val & BIT(sign_bit))) { BIT 164 sound/soc/soc-ops.c ret |= ~((int)(BIT(sign_bit) - 1)); BIT 261 sound/soc/soc-ops.c mask = BIT(sign_bit + 1) - 1; BIT 323 sound/soc/soc-ops.c mask = BIT(sign_bit + 1) - 1; BIT 50 sound/soc/sof/intel/hda-codec.c mask |= BIT(codec->core.addr); BIT 564 sound/soc/sof/intel/hda-stream.c if (status & BIT(s->index) && s->opened) { BIT 24 sound/soc/sof/intel/hda.h #define PCI_PGCTL_ADSPPGD BIT(2) BIT 25 sound/soc/sof/intel/hda.h #define PCI_PGCTL_LSRMD_MASK BIT(4) BIT 28 sound/soc/sof/intel/hda.h #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) BIT 29 sound/soc/sof/intel/hda.h #define PCI_CGCTL_ADSPDCGE BIT(1) BIT 35 sound/soc/sof/intel/hda.h #define SOF_HDA_GCTL_UNSOL BIT(8) BIT 44 sound/soc/sof/intel/hda.h #define SOF_HDA_GCTL_RESET BIT(0) BIT 47 sound/soc/sof/intel/hda.h #define SOF_HDA_INT_GLOBAL_EN BIT(31) BIT 48 sound/soc/sof/intel/hda.h #define SOF_HDA_INT_CTRL_EN BIT(30) BIT 64 sound/soc/sof/intel/hda.h #define SOF_HDA_PPCTL_PIE BIT(31) BIT 65 sound/soc/sof/intel/hda.h #define SOF_HDA_PPCTL_GPROCEN BIT(30) BIT 232 sound/soc/sof/intel/hda.h #define HDA_VS_INTEL_EM2_L1SEN BIT(13) BIT 235 sound/soc/sof/intel/hda.h #define HDA_DSP_REG_HIPCI_BUSY BIT(31) BIT 239 sound/soc/sof/intel/hda.h #define HDA_DSP_REG_HIPCIE_DONE BIT(30) BIT 243 sound/soc/sof/intel/hda.h #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) BIT 244 sound/soc/sof/intel/hda.h #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) BIT 247 sound/soc/sof/intel/hda.h #define HDA_DSP_REG_HIPCT_BUSY BIT(31) BIT 292 sound/soc/sof/intel/hda.h #define HDA_DSP_CORE_MASK(c) BIT(c) BIT 310 sound/soc/sof/intel/hda.h #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) BIT 314 sound/soc/sof/intel/hda.h #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) BIT 318 sound/soc/sof/intel/hda.h #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) BIT 319 sound/soc/sof/intel/hda.h #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) BIT 322 sound/soc/sof/intel/hda.h #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) BIT 326 sound/soc/sof/intel/hda.h #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) BIT 365 sound/soc/sof/intel/hda.h #define SSP_SET_SCLK_SLAVE BIT(25) BIT 366 sound/soc/sof/intel/hda.h #define SSP_SET_SFRM_SLAVE BIT(24) BIT 369 sound/soc/sof/intel/hda.h #define HDA_IDISP_CODEC(x) ((x) & BIT(2)) BIT 46 sound/soc/sof/intel/shim.h #define SHIM_CSR_RST BIT(1) BIT 47 sound/soc/sof/intel/shim.h #define SHIM_CSR_SBCS0 BIT(2) BIT 48 sound/soc/sof/intel/shim.h #define SHIM_CSR_SBCS1 BIT(3) BIT 51 sound/soc/sof/intel/shim.h #define SHIM_CSR_STALL BIT(10) BIT 52 sound/soc/sof/intel/shim.h #define SHIM_CSR_S0IOCS BIT(21) BIT 53 sound/soc/sof/intel/shim.h #define SHIM_CSR_S1IOCS BIT(23) BIT 54 sound/soc/sof/intel/shim.h #define SHIM_CSR_LPCS BIT(31) BIT 58 sound/soc/sof/intel/shim.h #define SHIM_BYT_CSR_RST BIT(0) BIT 59 sound/soc/sof/intel/shim.h #define SHIM_BYT_CSR_VECTOR_SEL BIT(1) BIT 60 sound/soc/sof/intel/shim.h #define SHIM_BYT_CSR_STALL BIT(2) BIT 61 sound/soc/sof/intel/shim.h #define SHIM_BYT_CSR_PWAITMODE BIT(3) BIT 64 sound/soc/sof/intel/shim.h #define SHIM_ISRX_BUSY BIT(1) BIT 65 sound/soc/sof/intel/shim.h #define SHIM_ISRX_DONE BIT(0) BIT 66 sound/soc/sof/intel/shim.h #define SHIM_BYT_ISRX_REQUEST BIT(1) BIT 69 sound/soc/sof/intel/shim.h #define SHIM_ISRD_BUSY BIT(1) BIT 70 sound/soc/sof/intel/shim.h #define SHIM_ISRD_DONE BIT(0) BIT 73 sound/soc/sof/intel/shim.h #define SHIM_IMRX_BUSY BIT(1) BIT 74 sound/soc/sof/intel/shim.h #define SHIM_IMRX_DONE BIT(0) BIT 75 sound/soc/sof/intel/shim.h #define SHIM_BYT_IMRX_REQUEST BIT(1) BIT 78 sound/soc/sof/intel/shim.h #define SHIM_IMRD_DONE BIT(0) BIT 79 sound/soc/sof/intel/shim.h #define SHIM_IMRD_BUSY BIT(1) BIT 80 sound/soc/sof/intel/shim.h #define SHIM_IMRD_SSP0 BIT(16) BIT 81 sound/soc/sof/intel/shim.h #define SHIM_IMRD_DMAC0 BIT(21) BIT 82 sound/soc/sof/intel/shim.h #define SHIM_IMRD_DMAC1 BIT(22) BIT 86 sound/soc/sof/intel/shim.h #define SHIM_IPCX_DONE BIT(30) BIT 87 sound/soc/sof/intel/shim.h #define SHIM_IPCX_BUSY BIT(31) BIT 92 sound/soc/sof/intel/shim.h #define SHIM_IPCD_DONE BIT(30) BIT 93 sound/soc/sof/intel/shim.h #define SHIM_IPCD_BUSY BIT(31) BIT 100 sound/soc/sof/intel/shim.h #define SHIM_CLKCTL_DCPLCG BIT(18) BIT 101 sound/soc/sof/intel/shim.h #define SHIM_CLKCTL_SCOE1 BIT(17) BIT 102 sound/soc/sof/intel/shim.h #define SHIM_CLKCTL_SCOE0 BIT(16) BIT 105 sound/soc/sof/intel/shim.h #define SHIM_CSR2_SDFD_SSP0 BIT(1) BIT 106 sound/soc/sof/intel/shim.h #define SHIM_CSR2_SDFD_SSP1 BIT(2) BIT 136 sound/soc/sof/intel/shim.h #define PCI_VDRTCL0_D3PGD BIT(0) BIT 137 sound/soc/sof/intel/shim.h #define PCI_VDRTCL0_D3SRAMPGD BIT(1) BIT 146 sound/soc/sof/intel/shim.h #define PCI_VDRTCL2_DCLCGE BIT(1) BIT 147 sound/soc/sof/intel/shim.h #define PCI_VDRTCL2_DTCGE BIT(10) BIT 148 sound/soc/sof/intel/shim.h #define PCI_VDRTCL2_APLLSE_MASK BIT(31) BIT 31 sound/soc/sof/sof-priv.h #define SOF_DBG_REGS BIT(1) BIT 32 sound/soc/sof/sof-priv.h #define SOF_DBG_MBOX BIT(2) BIT 33 sound/soc/sof/sof-priv.h #define SOF_DBG_TEXT BIT(3) BIT 34 sound/soc/sof/sof-priv.h #define SOF_DBG_PCI BIT(4) BIT 34 sound/soc/sof/topology.c #define VOL_ZERO_DB BIT(VOLUME_FWL) BIT 158 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift)); BIT 160 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift)); BIT 167 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(channel), BIT(channel)); BIT 169 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(channel)); BIT 176 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, BIT(channel), BIT 177 sound/soc/sprd/sprd-mcdt.c BIT(channel)); BIT 179 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, 0, BIT(channel)); BIT 385 sound/soc/sprd/sprd-mcdt.c return !!(readl_relaxed(mcdt->base + reg) & BIT(shift)); BIT 390 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, MCDT_FIFO_CLR, BIT(channel), BIT(channel)); BIT 397 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, MCDT_FIFO_CLR, BIT(shift), BIT(shift)); BIT 473 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, reg, BIT(shift), BIT(shift)); BIT 475 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, reg, 0, BIT(shift)); BIT 497 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, reg, BIT(shift), BIT(shift)); BIT 519 sound/soc/sprd/sprd-mcdt.c return !!(readl_relaxed(mcdt->base + reg) & BIT(shift)); BIT 118 sound/soc/sti/uniperif.h (BIT(UNIPERIF_ITS_MEM_BLK_READ_SHIFT(ip))) BIT 124 sound/soc/sti/uniperif.h (BIT(UNIPERIF_ITS_FIFO_ERROR_SHIFT(ip))) BIT 129 sound/soc/sti/uniperif.h (BIT(UNIPERIF_ITS_DMA_ERROR_SHIFT(ip))) BIT 136 sound/soc/sti/uniperif.h 0 : (BIT(UNIPERIF_ITS_UNDERFLOW_REC_DONE_SHIFT(ip)))) BIT 143 sound/soc/sti/uniperif.h 0 : (BIT(UNIPERIF_ITS_UNDERFLOW_REC_FAILED_SHIFT(ip)))) BIT 153 sound/soc/sti/uniperif.h (BIT(UNIPERIF_ITS_BCLR_FIFO_ERROR_SHIFT(ip))) BIT 174 sound/soc/sti/uniperif.h (BIT(UNIPERIF_ITM_FIFO_ERROR_SHIFT(ip))) BIT 181 sound/soc/sti/uniperif.h 0 : (BIT(UNIPERIF_ITM_UNDERFLOW_REC_DONE_SHIFT(ip)))) BIT 188 sound/soc/sti/uniperif.h 0 : (BIT(UNIPERIF_ITM_UNDERFLOW_REC_FAILED_SHIFT(ip)))) BIT 202 sound/soc/sti/uniperif.h (BIT(UNIPERIF_ITM_BCLR_FIFO_ERROR_SHIFT(ip))) BIT 210 sound/soc/sti/uniperif.h (BIT(UNIPERIF_ITM_BCLR_DMA_ERROR_SHIFT(ip))) BIT 227 sound/soc/sti/uniperif.h (BIT(UNIPERIF_ITM_BSET_FIFO_ERROR_SHIFT(ip))) BIT 235 sound/soc/sti/uniperif.h (BIT(UNIPERIF_ITM_BSET_MEM_BLK_READ_SHIFT(ip))) BIT 243 sound/soc/sti/uniperif.h (BIT(UNIPERIF_ITM_BSET_DMA_ERROR_SHIFT(ip))) BIT 253 sound/soc/sti/uniperif.h 0 : (BIT(UNIPERIF_ITM_BSET_UNDERFLOW_REC_DONE_SHIFT(ip)))) BIT 263 sound/soc/sti/uniperif.h 0 : (BIT(UNIPERIF_ITM_BSET_UNDERFLOW_REC_FAILED_SHIFT(ip)))) BIT 37 sound/soc/stm/stm32_i2s.c #define I2S_CR1_SPE BIT(0) BIT 38 sound/soc/stm/stm32_i2s.c #define I2S_CR1_CSTART BIT(9) BIT 39 sound/soc/stm/stm32_i2s.c #define I2S_CR1_CSUSP BIT(10) BIT 40 sound/soc/stm/stm32_i2s.c #define I2S_CR1_HDDIR BIT(11) BIT 41 sound/soc/stm/stm32_i2s.c #define I2S_CR1_SSI BIT(12) BIT 42 sound/soc/stm/stm32_i2s.c #define I2S_CR1_CRC33_17 BIT(13) BIT 43 sound/soc/stm/stm32_i2s.c #define I2S_CR1_RCRCI BIT(14) BIT 44 sound/soc/stm/stm32_i2s.c #define I2S_CR1_TCRCI BIT(15) BIT 48 sound/soc/stm/stm32_i2s.c #define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT) BIT 49 sound/soc/stm/stm32_i2s.c #define I2S_CFG2_LSBFRST BIT(23) BIT 50 sound/soc/stm/stm32_i2s.c #define I2S_CFG2_AFCNTR BIT(31) BIT 57 sound/soc/stm/stm32_i2s.c #define I2S_CFG1_TXDMAEN BIT(15) BIT 58 sound/soc/stm/stm32_i2s.c #define I2S_CFG1_RXDMAEN BIT(14) BIT 61 sound/soc/stm/stm32_i2s.c #define I2S_IER_RXPIE BIT(0) BIT 62 sound/soc/stm/stm32_i2s.c #define I2S_IER_TXPIE BIT(1) BIT 63 sound/soc/stm/stm32_i2s.c #define I2S_IER_DPXPIE BIT(2) BIT 64 sound/soc/stm/stm32_i2s.c #define I2S_IER_EOTIE BIT(3) BIT 65 sound/soc/stm/stm32_i2s.c #define I2S_IER_TXTFIE BIT(4) BIT 66 sound/soc/stm/stm32_i2s.c #define I2S_IER_UDRIE BIT(5) BIT 67 sound/soc/stm/stm32_i2s.c #define I2S_IER_OVRIE BIT(6) BIT 68 sound/soc/stm/stm32_i2s.c #define I2S_IER_CRCEIE BIT(7) BIT 69 sound/soc/stm/stm32_i2s.c #define I2S_IER_TIFREIE BIT(8) BIT 70 sound/soc/stm/stm32_i2s.c #define I2S_IER_MODFIE BIT(9) BIT 71 sound/soc/stm/stm32_i2s.c #define I2S_IER_TSERFIE BIT(10) BIT 74 sound/soc/stm/stm32_i2s.c #define I2S_SR_RXP BIT(0) BIT 75 sound/soc/stm/stm32_i2s.c #define I2S_SR_TXP BIT(1) BIT 76 sound/soc/stm/stm32_i2s.c #define I2S_SR_DPXP BIT(2) BIT 77 sound/soc/stm/stm32_i2s.c #define I2S_SR_EOT BIT(3) BIT 78 sound/soc/stm/stm32_i2s.c #define I2S_SR_TXTF BIT(4) BIT 79 sound/soc/stm/stm32_i2s.c #define I2S_SR_UDR BIT(5) BIT 80 sound/soc/stm/stm32_i2s.c #define I2S_SR_OVR BIT(6) BIT 81 sound/soc/stm/stm32_i2s.c #define I2S_SR_CRCERR BIT(7) BIT 82 sound/soc/stm/stm32_i2s.c #define I2S_SR_TIFRE BIT(8) BIT 83 sound/soc/stm/stm32_i2s.c #define I2S_SR_MODF BIT(9) BIT 84 sound/soc/stm/stm32_i2s.c #define I2S_SR_TSERF BIT(10) BIT 85 sound/soc/stm/stm32_i2s.c #define I2S_SR_SUSP BIT(11) BIT 86 sound/soc/stm/stm32_i2s.c #define I2S_SR_TXC BIT(12) BIT 88 sound/soc/stm/stm32_i2s.c #define I2S_SR_RXWNE BIT(15) BIT 93 sound/soc/stm/stm32_i2s.c #define I2S_IFCR_EOTC BIT(3) BIT 94 sound/soc/stm/stm32_i2s.c #define I2S_IFCR_TXTFC BIT(4) BIT 95 sound/soc/stm/stm32_i2s.c #define I2S_IFCR_UDRC BIT(5) BIT 96 sound/soc/stm/stm32_i2s.c #define I2S_IFCR_OVRC BIT(6) BIT 97 sound/soc/stm/stm32_i2s.c #define I2S_IFCR_CRCEC BIT(7) BIT 98 sound/soc/stm/stm32_i2s.c #define I2S_IFCR_TIFREC BIT(8) BIT 99 sound/soc/stm/stm32_i2s.c #define I2S_IFCR_MODFC BIT(9) BIT 100 sound/soc/stm/stm32_i2s.c #define I2S_IFCR_TSERFC BIT(10) BIT 101 sound/soc/stm/stm32_i2s.c #define I2S_IFCR_SUSPC BIT(11) BIT 106 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_I2SMOD BIT(0) BIT 116 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_PCMSYNC BIT(7) BIT 123 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT) BIT 124 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_CKPOL BIT(11) BIT 125 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_FIXCH BIT(12) BIT 126 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_WSINV BIT(13) BIT 127 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_DATFMT BIT(14) BIT 138 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT) BIT 139 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_MCKOE BIT(25) BIT 48 sound/soc/stm/stm32_sai.h #define SAI_XCR1_RX_TX BIT(SAI_XCR1_RX_TX_SHIFT) BIT 50 sound/soc/stm/stm32_sai.h #define SAI_XCR1_SLAVE BIT(SAI_XCR1_SLAVE_SHIFT) BIT 61 sound/soc/stm/stm32_sai.h #define SAI_XCR1_LSBFIRST BIT(SAI_XCR1_LSBFIRST_SHIFT) BIT 63 sound/soc/stm/stm32_sai.h #define SAI_XCR1_CKSTR BIT(SAI_XCR1_CKSTR_SHIFT) BIT 70 sound/soc/stm/stm32_sai.h #define SAI_XCR1_MONO BIT(SAI_XCR1_MONO_SHIFT) BIT 72 sound/soc/stm/stm32_sai.h #define SAI_XCR1_OUTDRIV BIT(SAI_XCR1_OUTDRIV_SHIFT) BIT 74 sound/soc/stm/stm32_sai.h #define SAI_XCR1_SAIEN BIT(SAI_XCR1_SAIEN_SHIFT) BIT 76 sound/soc/stm/stm32_sai.h #define SAI_XCR1_DMAEN BIT(SAI_XCR1_DMAEN_SHIFT) BIT 78 sound/soc/stm/stm32_sai.h #define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT) BIT 88 sound/soc/stm/stm32_sai.h #define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT) BIT 91 sound/soc/stm/stm32_sai.h #define SAI_XCR1_MCKEN BIT(SAI_XCR1_MCKEN_SHIFT) BIT 99 sound/soc/stm/stm32_sai.h #define SAI_XCR2_FFLUSH BIT(SAI_XCR2_FFLUSH_SHIFT) BIT 101 sound/soc/stm/stm32_sai.h #define SAI_XCR2_TRIS BIT(SAI_XCR2_TRIS_SHIFT) BIT 103 sound/soc/stm/stm32_sai.h #define SAI_XCR2_MUTE BIT(SAI_XCR2_MUTE_SHIFT) BIT 105 sound/soc/stm/stm32_sai.h #define SAI_XCR2_MUTEVAL BIT(SAI_XCR2_MUTEVAL_SHIFT) BIT 112 sound/soc/stm/stm32_sai.h #define SAI_XCR2_CPL BIT(SAI_XCR2_CPL_SHIFT) BIT 128 sound/soc/stm/stm32_sai.h #define SAI_XFRCR_FSDEF BIT(SAI_XFRCR_FSDEF_SHIFT) BIT 130 sound/soc/stm/stm32_sai.h #define SAI_XFRCR_FSPOL BIT(SAI_XFRCR_FSPOL_SHIFT) BIT 132 sound/soc/stm/stm32_sai.h #define SAI_XFRCR_FSOFF BIT(SAI_XFRCR_FSOFF_SHIFT) BIT 153 sound/soc/stm/stm32_sai.h #define SAI_XIMR_OVRUDRIE BIT(0) BIT 154 sound/soc/stm/stm32_sai.h #define SAI_XIMR_MUTEDETIE BIT(1) BIT 155 sound/soc/stm/stm32_sai.h #define SAI_XIMR_WCKCFGIE BIT(2) BIT 156 sound/soc/stm/stm32_sai.h #define SAI_XIMR_FREQIE BIT(3) BIT 157 sound/soc/stm/stm32_sai.h #define SAI_XIMR_CNRDYIE BIT(4) BIT 158 sound/soc/stm/stm32_sai.h #define SAI_XIMR_AFSDETIE BIT(5) BIT 159 sound/soc/stm/stm32_sai.h #define SAI_XIMR_LFSDETIE BIT(6) BIT 165 sound/soc/stm/stm32_sai.h #define SAI_XSR_OVRUDR BIT(0) BIT 166 sound/soc/stm/stm32_sai.h #define SAI_XSR_MUTEDET BIT(1) BIT 167 sound/soc/stm/stm32_sai.h #define SAI_XSR_WCKCFG BIT(2) BIT 168 sound/soc/stm/stm32_sai.h #define SAI_XSR_FREQ BIT(3) BIT 169 sound/soc/stm/stm32_sai.h #define SAI_XSR_CNRDY BIT(4) BIT 170 sound/soc/stm/stm32_sai.h #define SAI_XSR_AFSDET BIT(5) BIT 171 sound/soc/stm/stm32_sai.h #define SAI_XSR_LFSDET BIT(6) BIT 177 sound/soc/stm/stm32_sai.h #define SAI_XCLRFR_COVRUDR BIT(0) BIT 178 sound/soc/stm/stm32_sai.h #define SAI_XCLRFR_CMUTEDET BIT(1) BIT 179 sound/soc/stm/stm32_sai.h #define SAI_XCLRFR_CWCKCFG BIT(2) BIT 180 sound/soc/stm/stm32_sai.h #define SAI_XCLRFR_CFREQ BIT(3) BIT 181 sound/soc/stm/stm32_sai.h #define SAI_XCLRFR_CCNRDY BIT(4) BIT 182 sound/soc/stm/stm32_sai.h #define SAI_XCLRFR_CAFSDET BIT(5) BIT 183 sound/soc/stm/stm32_sai.h #define SAI_XCLRFR_CLFSDET BIT(6) BIT 189 sound/soc/stm/stm32_sai.h #define SAI_PDMCR_PDMEN BIT(0) BIT 195 sound/soc/stm/stm32_sai.h #define SAI_PDMCR_CKEN1 BIT(8) BIT 196 sound/soc/stm/stm32_sai.h #define SAI_PDMCR_CKEN2 BIT(9) BIT 197 sound/soc/stm/stm32_sai.h #define SAI_PDMCR_CKEN3 BIT(10) BIT 198 sound/soc/stm/stm32_sai.h #define SAI_PDMCR_CKEN4 BIT(11) BIT 253 sound/soc/stm/stm32_sai.h #define STM_SAI_STM32F4 BIT(4) BIT 38 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_RXDMAEN BIT(2) BIT 39 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_RXSTEO BIT(3) BIT 45 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_PMSK BIT(6) BIT 46 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_VMSK BIT(7) BIT 47 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_CUMSK BIT(8) BIT 48 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_PTMSK BIT(9) BIT 49 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_CBDMAEN BIT(10) BIT 51 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT) BIT 57 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_WFA BIT(14) BIT 64 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_CKSEN BIT(20) BIT 65 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_CKSBKPEN BIT(21) BIT 68 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IMR_RXNEI BIT(0) BIT 69 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IMR_CSRNEIE BIT(1) BIT 70 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IMR_PERRIE BIT(2) BIT 71 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IMR_OVRIE BIT(3) BIT 72 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IMR_SBLKIE BIT(4) BIT 73 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IMR_SYNCDIE BIT(5) BIT 74 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IMR_IFEIE BIT(6) BIT 79 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SR_RXNE BIT(0) BIT 80 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SR_CSRNE BIT(1) BIT 81 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SR_PERR BIT(2) BIT 82 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SR_OVR BIT(3) BIT 83 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SR_SBD BIT(4) BIT 84 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SR_SYNCD BIT(5) BIT 85 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SR_FERR BIT(6) BIT 86 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SR_SERR BIT(7) BIT 87 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SR_TERR BIT(8) BIT 94 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IFCR_PERRCF BIT(2) BIT 95 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IFCR_OVRCF BIT(3) BIT 96 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IFCR_SBDCF BIT(4) BIT 97 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IFCR_SYNCDCF BIT(5) BIT 106 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR0_PE BIT(24) BIT 108 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR0_V BIT(25) BIT 109 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR0_U BIT(26) BIT 110 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR0_C BIT(27) BIT 117 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR1_PE BIT(0) BIT 118 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR1_V BIT(1) BIT 119 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR1_U BIT(2) BIT 120 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR1_C BIT(3) BIT 150 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CSR_SOB BIT(24) BIT 254 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH), BIT 255 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); BIT 259 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN), BIT 260 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); BIT 267 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN), BIT 275 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN), BIT 276 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN)); BIT 283 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN), 0); BIT 327 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH), BIT 328 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH)); BIT 369 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH), BIT 370 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); BIT 382 sound/soc/sunxi/sun4i-codec.c val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION); BIT 385 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION), BIT 390 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT), BIT 489 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN), BIT 490 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); BIT 493 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN), BIT 499 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS), BIT 500 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS)); BIT 503 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE), BIT 509 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS), BIT 514 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE), BIT 515 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); BIT 536 sound/soc/sunxi/sun4i-codec.c val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN); BIT 541 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN), BIT 547 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS), BIT 548 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); BIT 552 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE), BIT 558 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS), BIT 563 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE), BIT 564 sound/soc/sunxi/sun4i-codec.c BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); BIT 26 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo)) BIT 27 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_CTRL_MODE_MASK BIT(5) BIT 30 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_CTRL_TX_EN BIT(2) BIT 31 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_CTRL_RX_EN BIT(1) BIT 32 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_CTRL_GL_EN BIT(0) BIT 35 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7) BIT 38 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6) BIT 55 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25) BIT 56 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24) BIT 57 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2) BIT 65 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7) BIT 66 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3) BIT 71 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7) BIT 91 sound/soc/sunxi/sun4i-i2s.c #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) BIT 92 sound/soc/sunxi/sun4i-i2s.c #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17) BIT 99 sound/soc/sunxi/sun4i-i2s.c #define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19) BIT 104 sound/soc/sunxi/sun4i-i2s.c #define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7) BIT 30 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2) BIT 31 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_CTL_GEN BIT(1) BIT 32 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_CTL_RESET BIT(0) BIT 35 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31) BIT 36 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_TXCFG_ASS BIT(17) BIT 37 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16) BIT 44 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1) BIT 45 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_TXCFG_TXEN BIT(0) BIT 48 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_RXCFG_LOCKFLAG BIT(4) BIT 49 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_RXCFG_CHSTSRC BIT(3) BIT 50 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_RXCFG_CHSTCP BIT(1) BIT 51 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_RXCFG_RXEN BIT(0) BIT 58 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_FCTL_FIFOSRC BIT(31) BIT 59 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_FCTL_FTX BIT(17) BIT 60 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_FCTL_FRX BIT(16) BIT 65 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_FCTL_TXIM BIT(2) BIT 70 sound/soc/sunxi/sun4i-spdif.c #define SUN50I_H6_SPDIF_FCTL_HUB_EN BIT(31) BIT 71 sound/soc/sunxi/sun4i-spdif.c #define SUN50I_H6_SPDIF_FCTL_FTX BIT(30) BIT 72 sound/soc/sunxi/sun4i-spdif.c #define SUN50I_H6_SPDIF_FCTL_FRX BIT(29) BIT 77 sound/soc/sunxi/sun4i-spdif.c #define SUN50I_H6_SPDIF_FCTL_TXIM BIT(2) BIT 82 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_FSTA_TXE BIT(14) BIT 84 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_FSTA_RXA BIT(6) BIT 88 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_INT_RXLOCKEN BIT(18) BIT 89 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_INT_RXUNLOCKEN BIT(17) BIT 90 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_INT_RXPARERREN BIT(16) BIT 91 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_INT_TXDRQEN BIT(7) BIT 92 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_INT_TXUIEN BIT(6) BIT 93 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_INT_TXOIEN BIT(5) BIT 94 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_INT_TXEIEN BIT(4) BIT 95 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_INT_RXDRQEN BIT(2) BIT 96 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_INT_RXOIEN BIT(1) BIT 97 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_INT_RXAIEN BIT(0) BIT 100 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_ISTA_RXLOCKSTA BIT(18) BIT 101 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_ISTA_RXUNLOCKSTA BIT(17) BIT 102 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_ISTA_RXPARERRSTA BIT(16) BIT 103 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_ISTA_TXUSTA BIT(6) BIT 104 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_ISTA_TXOSTA BIT(5) BIT 105 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_ISTA_TXESTA BIT(4) BIT 106 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_ISTA_RXOSTA BIT(1) BIT 107 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_ISTA_RXASTA BIT(0) BIT 125 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_TXCHSTA0_CP BIT(2) BIT 126 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_TXCHSTA0_AUDIO BIT(1) BIT 127 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_TXCHSTA0_PRO BIT(0) BIT 134 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_TXCHSTA1_MAXWORDLEN BIT(0) BIT 144 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_RXCHSTA0_CP BIT(2) BIT 145 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_RXCHSTA0_AUDIO BIT(1) BIT 146 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_RXCHSTA0_PRO BIT(0) BIT 152 sound/soc/sunxi/sun4i-spdif.c #define SUN4I_SPDIF_RXCHSTA1_MAXWORDLEN BIT(0) BIT 19 sound/soc/sunxi/sun8i-adda-pr-regmap.c #define ADDA_PR_RESET BIT(28) BIT 20 sound/soc/sunxi/sun8i-adda-pr-regmap.c #define ADDA_PR_WRITE BIT(24) BIT 351 sound/soc/sunxi/sun8i-codec-analog.c BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN), BIT 352 sound/soc/sunxi/sun8i-codec-analog.c BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN)); BIT 361 sound/soc/sunxi/sun8i-codec-analog.c BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN), BIT 194 sound/soc/sunxi/sun8i-codec.c BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD), BIT 209 sound/soc/sunxi/sun8i-codec.c BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV), BIT 223 sound/soc/sunxi/sun8i-codec.c BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV), BIT 326 sound/soc/tegra/tegra30_ahub.c #define MOD_LIST_MASK_TEGRA30 BIT(0) BIT 327 sound/soc/tegra/tegra30_ahub.c #define MOD_LIST_MASK_TEGRA114 BIT(1) BIT 328 sound/soc/tegra/tegra30_ahub.c #define MOD_LIST_MASK_TEGRA124 BIT(2) BIT 77 sound/soc/ti/davinci-i2s.c #define DAVINCI_MCBSP_RCR_RPHASE BIT(31) BIT 85 sound/soc/ti/davinci-i2s.c #define DAVINCI_MCBSP_XCR_XPHASE BIT(31) BIT 90 sound/soc/ti/davinci-i2s.c #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29) BIT 190 sound/soc/ti/davinci-mcasp.c mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); BIT 192 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); BIT 202 sound/soc/ti/davinci-mcasp.c mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); BIT 204 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); BIT 1965 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); BIT 1968 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); BIT 1980 sound/soc/ti/davinci-mcasp.c mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); BIT 1982 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); BIT 1985 sound/soc/ti/davinci-mcasp.c if (!(val & BIT(offset))) { BIT 1987 sound/soc/ti/davinci-mcasp.c mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); BIT 1990 sound/soc/ti/davinci-mcasp.c mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); BIT 2002 sound/soc/ti/davinci-mcasp.c mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); BIT 2004 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); BIT 2014 sound/soc/ti/davinci-mcasp.c if (!(val & BIT(offset))) { BIT 2016 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); BIT 2019 sound/soc/ti/davinci-mcasp.c mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); BIT 2031 sound/soc/ti/davinci-mcasp.c if (val & BIT(offset)) BIT 2044 sound/soc/ti/davinci-mcasp.c if (val & BIT(offset)) BIT 103 sound/soc/ti/davinci-mcasp.h #define MCASP_FREE BIT(0) BIT 104 sound/soc/ti/davinci-mcasp.h #define MCASP_SOFT BIT(1) BIT 124 sound/soc/ti/davinci-mcasp.h #define DITEN BIT(0) /* Transmit DIT mode enable/disable */ BIT 125 sound/soc/ti/davinci-mcasp.h #define VA BIT(2) BIT 126 sound/soc/ti/davinci-mcasp.h #define VB BIT(3) BIT 132 sound/soc/ti/davinci-mcasp.h #define TXSEL BIT(3) BIT 136 sound/soc/ti/davinci-mcasp.h #define TXORD BIT(15) BIT 143 sound/soc/ti/davinci-mcasp.h #define RXSEL BIT(3) BIT 147 sound/soc/ti/davinci-mcasp.h #define RXORD BIT(15) BIT 153 sound/soc/ti/davinci-mcasp.h #define FSXPOL BIT(0) BIT 154 sound/soc/ti/davinci-mcasp.h #define AFSXE BIT(1) BIT 155 sound/soc/ti/davinci-mcasp.h #define FSXDUR BIT(4) BIT 161 sound/soc/ti/davinci-mcasp.h #define FSRPOL BIT(0) BIT 162 sound/soc/ti/davinci-mcasp.h #define AFSRE BIT(1) BIT 163 sound/soc/ti/davinci-mcasp.h #define FSRDUR BIT(4) BIT 170 sound/soc/ti/davinci-mcasp.h #define ACLKXE BIT(5) BIT 171 sound/soc/ti/davinci-mcasp.h #define TX_ASYNC BIT(6) BIT 172 sound/soc/ti/davinci-mcasp.h #define ACLKXPOL BIT(7) BIT 179 sound/soc/ti/davinci-mcasp.h #define ACLKRE BIT(5) BIT 180 sound/soc/ti/davinci-mcasp.h #define RX_ASYNC BIT(6) BIT 181 sound/soc/ti/davinci-mcasp.h #define ACLKRPOL BIT(7) BIT 189 sound/soc/ti/davinci-mcasp.h #define AHCLKXPOL BIT(14) BIT 190 sound/soc/ti/davinci-mcasp.h #define AHCLKXE BIT(15) BIT 198 sound/soc/ti/davinci-mcasp.h #define AHCLKRPOL BIT(14) BIT 199 sound/soc/ti/davinci-mcasp.h #define AHCLKRE BIT(15) BIT 211 sound/soc/ti/davinci-mcasp.h #define TXSTATE BIT(4) BIT 212 sound/soc/ti/davinci-mcasp.h #define RXSTATE BIT(5) BIT 219 sound/soc/ti/davinci-mcasp.h #define LBEN BIT(0) BIT 220 sound/soc/ti/davinci-mcasp.h #define LBORD BIT(1) BIT 236 sound/soc/ti/davinci-mcasp.h #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */ BIT 237 sound/soc/ti/davinci-mcasp.h #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */ BIT 238 sound/soc/ti/davinci-mcasp.h #define RXSERCLR BIT(2) /* Receiver Serializer Clear */ BIT 239 sound/soc/ti/davinci-mcasp.h #define RXSMRST BIT(3) /* Receiver State Machine Reset */ BIT 240 sound/soc/ti/davinci-mcasp.h #define RXFSRST BIT(4) /* Frame Sync Generator Reset */ BIT 241 sound/soc/ti/davinci-mcasp.h #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */ BIT 242 sound/soc/ti/davinci-mcasp.h #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/ BIT 243 sound/soc/ti/davinci-mcasp.h #define TXSERCLR BIT(10) /* Transmit Serializer Clear */ BIT 244 sound/soc/ti/davinci-mcasp.h #define TXSMRST BIT(11) /* Transmitter State Machine Reset */ BIT 245 sound/soc/ti/davinci-mcasp.h #define TXFSRST BIT(12) /* Frame Sync Generator Reset */ BIT 251 sound/soc/ti/davinci-mcasp.h #define XRERR BIT(8) /* Transmit/Receive error */ BIT 252 sound/soc/ti/davinci-mcasp.h #define XRDATA BIT(5) /* Transmit/Receive data ready */ BIT 258 sound/soc/ti/davinci-mcasp.h #define MUTEINPOL BIT(2) BIT 259 sound/soc/ti/davinci-mcasp.h #define MUTEINENA BIT(3) BIT 260 sound/soc/ti/davinci-mcasp.h #define MUTEIN BIT(4) BIT 261 sound/soc/ti/davinci-mcasp.h #define MUTER BIT(5) BIT 262 sound/soc/ti/davinci-mcasp.h #define MUTEX BIT(6) BIT 263 sound/soc/ti/davinci-mcasp.h #define MUTEFSR BIT(7) BIT 264 sound/soc/ti/davinci-mcasp.h #define MUTEFSX BIT(8) BIT 265 sound/soc/ti/davinci-mcasp.h #define MUTEBADCLKR BIT(9) BIT 266 sound/soc/ti/davinci-mcasp.h #define MUTEBADCLKX BIT(10) BIT 267 sound/soc/ti/davinci-mcasp.h #define MUTERXDMAERR BIT(11) BIT 268 sound/soc/ti/davinci-mcasp.h #define MUTETXDMAERR BIT(12) BIT 273 sound/soc/ti/davinci-mcasp.h #define RXDATADMADIS BIT(0) BIT 278 sound/soc/ti/davinci-mcasp.h #define TXDATADMADIS BIT(0) BIT 283 sound/soc/ti/davinci-mcasp.h #define ROVRN BIT(0) BIT 288 sound/soc/ti/davinci-mcasp.h #define XUNDRN BIT(0) BIT 293 sound/soc/ti/davinci-mcasp.h #define FIFO_ENABLE BIT(16) BIT 74 sound/soc/ti/omap-mcbsp-priv.h #define RRST BIT(0) BIT 75 sound/soc/ti/omap-mcbsp-priv.h #define RRDY BIT(1) BIT 76 sound/soc/ti/omap-mcbsp-priv.h #define RFULL BIT(2) BIT 77 sound/soc/ti/omap-mcbsp-priv.h #define RSYNC_ERR BIT(3) BIT 79 sound/soc/ti/omap-mcbsp-priv.h #define ABIS BIT(6) BIT 80 sound/soc/ti/omap-mcbsp-priv.h #define DXENA BIT(7) BIT 83 sound/soc/ti/omap-mcbsp-priv.h #define ALB BIT(15) BIT 84 sound/soc/ti/omap-mcbsp-priv.h #define DLB BIT(15) BIT 87 sound/soc/ti/omap-mcbsp-priv.h #define XRST BIT(0) BIT 88 sound/soc/ti/omap-mcbsp-priv.h #define XRDY BIT(1) BIT 89 sound/soc/ti/omap-mcbsp-priv.h #define XEMPTY BIT(2) BIT 90 sound/soc/ti/omap-mcbsp-priv.h #define XSYNC_ERR BIT(3) BIT 92 sound/soc/ti/omap-mcbsp-priv.h #define GRST BIT(6) BIT 93 sound/soc/ti/omap-mcbsp-priv.h #define FRST BIT(7) BIT 94 sound/soc/ti/omap-mcbsp-priv.h #define SOFT BIT(8) BIT 95 sound/soc/ti/omap-mcbsp-priv.h #define FREE BIT(9) BIT 98 sound/soc/ti/omap-mcbsp-priv.h #define CLKRP BIT(0) BIT 99 sound/soc/ti/omap-mcbsp-priv.h #define CLKXP BIT(1) BIT 100 sound/soc/ti/omap-mcbsp-priv.h #define FSRP BIT(2) BIT 101 sound/soc/ti/omap-mcbsp-priv.h #define FSXP BIT(3) BIT 102 sound/soc/ti/omap-mcbsp-priv.h #define DR_STAT BIT(4) BIT 103 sound/soc/ti/omap-mcbsp-priv.h #define DX_STAT BIT(5) BIT 104 sound/soc/ti/omap-mcbsp-priv.h #define CLKS_STAT BIT(6) BIT 105 sound/soc/ti/omap-mcbsp-priv.h #define SCLKME BIT(7) BIT 106 sound/soc/ti/omap-mcbsp-priv.h #define CLKRM BIT(8) BIT 107 sound/soc/ti/omap-mcbsp-priv.h #define CLKXM BIT(9) BIT 108 sound/soc/ti/omap-mcbsp-priv.h #define FSRM BIT(10) BIT 109 sound/soc/ti/omap-mcbsp-priv.h #define FSXM BIT(11) BIT 110 sound/soc/ti/omap-mcbsp-priv.h #define RIOEN BIT(12) BIT 111 sound/soc/ti/omap-mcbsp-priv.h #define XIOEN BIT(13) BIT 112 sound/soc/ti/omap-mcbsp-priv.h #define IDLE_EN BIT(14) BIT 124 sound/soc/ti/omap-mcbsp-priv.h #define RFIG BIT(2) BIT 128 sound/soc/ti/omap-mcbsp-priv.h #define RPHASE BIT(15) BIT 132 sound/soc/ti/omap-mcbsp-priv.h #define XFIG BIT(2) BIT 136 sound/soc/ti/omap-mcbsp-priv.h #define XPHASE BIT(15) BIT 144 sound/soc/ti/omap-mcbsp-priv.h #define FSGM BIT(12) BIT 145 sound/soc/ti/omap-mcbsp-priv.h #define CLKSM BIT(13) BIT 146 sound/soc/ti/omap-mcbsp-priv.h #define CLKSP BIT(14) BIT 147 sound/soc/ti/omap-mcbsp-priv.h #define GSYNC BIT(15) BIT 150 sound/soc/ti/omap-mcbsp-priv.h #define RMCM BIT(0) BIT 162 sound/soc/ti/omap-mcbsp-priv.h #define XDISABLE BIT(0) BIT 163 sound/soc/ti/omap-mcbsp-priv.h #define XDMAEN BIT(3) BIT 164 sound/soc/ti/omap-mcbsp-priv.h #define DILB BIT(5) BIT 165 sound/soc/ti/omap-mcbsp-priv.h #define XFULL_CYCLE BIT(11) BIT 167 sound/soc/ti/omap-mcbsp-priv.h #define PPCONNECT BIT(14) BIT 168 sound/soc/ti/omap-mcbsp-priv.h #define EXTCLKGATE BIT(15) BIT 171 sound/soc/ti/omap-mcbsp-priv.h #define RDISABLE BIT(0) BIT 172 sound/soc/ti/omap-mcbsp-priv.h #define RDMAEN BIT(3) BIT 173 sound/soc/ti/omap-mcbsp-priv.h #define RFULL_CYCLE BIT(11) BIT 176 sound/soc/ti/omap-mcbsp-priv.h #define SOFTRST BIT(1) BIT 177 sound/soc/ti/omap-mcbsp-priv.h #define ENAWAKEUP BIT(2) BIT 186 sound/soc/ti/omap-mcbsp-priv.h #define RSYNCERREN BIT(0) BIT 187 sound/soc/ti/omap-mcbsp-priv.h #define RFSREN BIT(1) BIT 188 sound/soc/ti/omap-mcbsp-priv.h #define REOFEN BIT(2) BIT 189 sound/soc/ti/omap-mcbsp-priv.h #define RRDYEN BIT(3) BIT 190 sound/soc/ti/omap-mcbsp-priv.h #define RUNDFLEN BIT(4) BIT 191 sound/soc/ti/omap-mcbsp-priv.h #define ROVFLEN BIT(5) BIT 192 sound/soc/ti/omap-mcbsp-priv.h #define XSYNCERREN BIT(7) BIT 193 sound/soc/ti/omap-mcbsp-priv.h #define XFSXEN BIT(8) BIT 194 sound/soc/ti/omap-mcbsp-priv.h #define XEOFEN BIT(9) BIT 195 sound/soc/ti/omap-mcbsp-priv.h #define XRDYEN BIT(10) BIT 196 sound/soc/ti/omap-mcbsp-priv.h #define XUNDFLEN BIT(11) BIT 197 sound/soc/ti/omap-mcbsp-priv.h #define XOVFLEN BIT(12) BIT 198 sound/soc/ti/omap-mcbsp-priv.h #define XEMPTYEOFEN BIT(14) BIT 37 sound/soc/ti/omap-mcbsp-st.c #define SIDETONEEN BIT(10) BIT 40 sound/soc/ti/omap-mcbsp-st.c #define ST_AUTOIDLE BIT(0) BIT 50 sound/soc/ti/omap-mcbsp-st.c #define ST_SIDETONEEN BIT(0) BIT 51 sound/soc/ti/omap-mcbsp-st.c #define ST_COEFFWREN BIT(1) BIT 52 sound/soc/ti/omap-mcbsp-st.c #define ST_COEFFWRDONE BIT(2) BIT 255 sound/soc/uniphier/aio-core.c regmap_write(r, AOUTRSTCTR0, BIT(sub->swm->oport.map)); BIT 256 sound/soc/uniphier/aio-core.c regmap_write(r, AOUTRSTCTR1, BIT(sub->swm->oport.map)); BIT 694 sound/soc/uniphier/aio-core.c regmap_write(r, AOUTENCTR0, BIT(sub->swm->oport.map)); BIT 696 sound/soc/uniphier/aio-core.c regmap_write(r, AOUTENCTR1, BIT(sub->swm->oport.map)); BIT 772 sound/soc/uniphier/aio-core.c regmap_write(r, AOUTFADECTR0, BIT(oport_map)); BIT 904 sound/soc/uniphier/aio-core.c regmap_write(r, AOUTSRCRSTCTR0, BIT(sub->swm->oport.map)); BIT 905 sound/soc/uniphier/aio-core.c regmap_write(r, AOUTSRCRSTCTR1, BIT(sub->swm->oport.map)); BIT 1010 sound/soc/uniphier/aio-core.c v | BIT(sub->swm->och.map)); BIT 1039 sound/soc/uniphier/aio-core.c CDA2D_STRT0_STOP_START | BIT(sub->swm->ch.map)); BIT 1042 sound/soc/uniphier/aio-core.c BIT(sub->swm->rb.map), BIT 1043 sound/soc/uniphier/aio-core.c BIT(sub->swm->rb.map)); BIT 1046 sound/soc/uniphier/aio-core.c CDA2D_STRT0_STOP_STOP | BIT(sub->swm->ch.map)); BIT 1049 sound/soc/uniphier/aio-core.c BIT(sub->swm->rb.map), BIT 1061 sound/soc/uniphier/aio-core.c CDA2D_RDPTRLOAD_LSFLAG_STORE | BIT(sub->swm->rb.map)); BIT 1081 sound/soc/uniphier/aio-core.c regmap_write(r, CDA2D_RDPTRLOAD, BIT(sub->swm->rb.map)); BIT 1094 sound/soc/uniphier/aio-core.c CDA2D_WRPTRLOAD_LSFLAG_STORE | BIT(sub->swm->rb.map)); BIT 1116 sound/soc/uniphier/aio-core.c regmap_write(r, CDA2D_WRPTRLOAD, BIT(sub->swm->rb.map)); BIT 1155 sound/soc/uniphier/aio-core.c regmap_write(r, CDA2D_RBADRSLOAD, BIT(sub->swm->rb.map)); BIT 106 sound/soc/uniphier/aio-reg.h #define IPORTMXCTR2_MSSEL_MASK BIT(15) BIT 109 sound/soc/uniphier/aio-reg.h #define IPORTMXCTR2_EXTLSIFSSEL_MASK BIT(14) BIT 117 sound/soc/uniphier/aio-reg.h #define IPORTMXCTR2_REQEN_MASK BIT(0) BIT 128 sound/soc/uniphier/aio-reg.h #define IPORTMXEXNOE_PCMINOE_MASK BIT(0) BIT 139 sound/soc/uniphier/aio-reg.h #define IPORTMXRSTCTR_RSTPI_MASK BIT(7) BIT 145 sound/soc/uniphier/aio-reg.h #define PBINMXCTR_NCONNECT_MASK BIT(15) BIT 148 sound/soc/uniphier/aio-reg.h #define PBINMXCTR_INOUTSEL_MASK BIT(14) BIT 220 sound/soc/uniphier/aio-reg.h #define OPORTMXCTR2_MSSEL_MASK BIT(15) BIT 223 sound/soc/uniphier/aio-reg.h #define OPORTMXCTR2_EXTLSIFSSEL_MASK BIT(14) BIT 232 sound/soc/uniphier/aio-reg.h #define OPORTMXCTR3_IECTHUR_MASK BIT(19) BIT 239 sound/soc/uniphier/aio-reg.h #define OPORTMXCTR3_VALID_MASK BIT(12) BIT 242 sound/soc/uniphier/aio-reg.h #define OPORTMXCTR3_PMSEL_MASK BIT(3) BIT 245 sound/soc/uniphier/aio-reg.h #define OPORTMXCTR3_PMSW_MASK BIT(2) BIT 250 sound/soc/uniphier/aio-reg.h #define OPORTMXSRC1CTR_THMODE_MASK BIT(23) BIT 253 sound/soc/uniphier/aio-reg.h #define OPORTMXSRC1CTR_LOCK_MASK BIT(16) BIT 256 sound/soc/uniphier/aio-reg.h #define OPORTMXSRC1CTR_SRCPATH_MASK BIT(15) BIT 259 sound/soc/uniphier/aio-reg.h #define OPORTMXSRC1CTR_SYNC_MASK BIT(14) BIT 308 sound/soc/uniphier/aio-reg.h #define OPORTMXRATE_I_EQU_MASK BIT(31) BIT 311 sound/soc/uniphier/aio-reg.h #define OPORTMXRATE_I_SRCBPMD_MASK BIT(29) BIT 314 sound/soc/uniphier/aio-reg.h #define OPORTMXRATE_I_LRCKSTP_MASK BIT(24) BIT 377 sound/soc/uniphier/aio-reg.h #define OPORTMXTYSLOTCTR_MODE BIT(15) BIT 384 sound/soc/uniphier/aio-reg.h #define OPORTMXT0SLOTCTR_MUTEOFF_MASK BIT(1) BIT 388 sound/soc/uniphier/aio-reg.h #define OPORTMXT0RSTCTR_RST_MASK BIT(1) BIT 414 sound/soc/uniphier/aio-reg.h #define CDA2D_STRT0_STOP_MASK BIT(31) BIT 425 sound/soc/uniphier/aio-reg.h #define CDA2D_CHMXCTRL1_INDSIZE_MASK BIT(0) BIT 473 sound/soc/uniphier/aio-reg.h #define CDA2D_RBMXIX_SPACE BIT(3) BIT 474 sound/soc/uniphier/aio-reg.h #define CDA2D_RBMXIX_REMAIN BIT(4) BIT 20 sound/soc/uniphier/evea.c #define AADCPOW_AADC_POWD BIT(0) BIT 24 sound/soc/uniphier/evea.c #define AHPOUTPOW_HP_ON BIT(4) BIT 26 sound/soc/uniphier/evea.c #define ALINEPOW_LIN2_POWD BIT(3) BIT 27 sound/soc/uniphier/evea.c #define ALINEPOW_LIN1_POWD BIT(4) BIT 29 sound/soc/uniphier/evea.c #define ALO1OUTPOW_LO1_ON BIT(4) BIT 31 sound/soc/uniphier/evea.c #define ALO2OUTPOW_ADAC2_MUTE BIT(0) BIT 32 sound/soc/uniphier/evea.c #define ALO2OUTPOW_LO2_ON BIT(4) BIT 34 sound/soc/uniphier/evea.c #define AANAPOW_A_POWD BIT(4) BIT 36 sound/soc/uniphier/evea.c #define ADACSEQ1_MMUTE BIT(1) BIT 38 sound/soc/uniphier/evea.c #define ADACSEQ2_ADACIN_FIX BIT(0) BIT 106 sound/soc/ux500/ux500_msp_i2s.h #define RX_ENABLE_MASK BIT(0) BIT 107 sound/soc/ux500/ux500_msp_i2s.h #define RX_FIFO_ENABLE_MASK BIT(1) BIT 108 sound/soc/ux500/ux500_msp_i2s.h #define RX_FSYNC_MASK BIT(2) BIT 109 sound/soc/ux500/ux500_msp_i2s.h #define DIRECT_COMPANDING_MASK BIT(3) BIT 110 sound/soc/ux500/ux500_msp_i2s.h #define RX_SYNC_SEL_MASK BIT(4) BIT 111 sound/soc/ux500/ux500_msp_i2s.h #define RX_CLK_POL_MASK BIT(5) BIT 112 sound/soc/ux500/ux500_msp_i2s.h #define RX_CLK_SEL_MASK BIT(6) BIT 113 sound/soc/ux500/ux500_msp_i2s.h #define LOOPBACK_MASK BIT(7) BIT 114 sound/soc/ux500/ux500_msp_i2s.h #define TX_ENABLE_MASK BIT(8) BIT 115 sound/soc/ux500/ux500_msp_i2s.h #define TX_FIFO_ENABLE_MASK BIT(9) BIT 116 sound/soc/ux500/ux500_msp_i2s.h #define TX_FSYNC_MASK BIT(10) BIT 117 sound/soc/ux500/ux500_msp_i2s.h #define TX_MSP_TDR_TSR BIT(11) BIT 118 sound/soc/ux500/ux500_msp_i2s.h #define TX_SYNC_SEL_MASK (BIT(12) | BIT(11)) BIT 119 sound/soc/ux500/ux500_msp_i2s.h #define TX_CLK_POL_MASK BIT(13) BIT 120 sound/soc/ux500/ux500_msp_i2s.h #define TX_CLK_SEL_MASK BIT(14) BIT 121 sound/soc/ux500/ux500_msp_i2s.h #define TX_EXTRA_DELAY_MASK BIT(15) BIT 122 sound/soc/ux500/ux500_msp_i2s.h #define SRG_ENABLE_MASK BIT(16) BIT 123 sound/soc/ux500/ux500_msp_i2s.h #define SRG_CLK_POL_MASK BIT(17) BIT 124 sound/soc/ux500/ux500_msp_i2s.h #define SRG_CLK_SEL_MASK (BIT(19) | BIT(18)) BIT 125 sound/soc/ux500/ux500_msp_i2s.h #define FRAME_GEN_EN_MASK BIT(20) BIT 126 sound/soc/ux500/ux500_msp_i2s.h #define SPI_CLK_MODE_MASK (BIT(22) | BIT(21)) BIT 127 sound/soc/ux500/ux500_msp_i2s.h #define SPI_BURST_MODE_MASK BIT(23) BIT 151 sound/soc/ux500/ux500_msp_i2s.h #define RCKPOL_MASK BIT(0) BIT 152 sound/soc/ux500/ux500_msp_i2s.h #define TCKPOL_MASK BIT(0) BIT 153 sound/soc/ux500/ux500_msp_i2s.h #define SPICKM_MASK (BIT(1) | BIT(0)) BIT 199 sound/soc/ux500/ux500_msp_i2s.h #define RX_BUSY BIT(0) BIT 200 sound/soc/ux500/ux500_msp_i2s.h #define RX_FIFO_EMPTY BIT(1) BIT 201 sound/soc/ux500/ux500_msp_i2s.h #define RX_FIFO_FULL BIT(2) BIT 202 sound/soc/ux500/ux500_msp_i2s.h #define TX_BUSY BIT(3) BIT 203 sound/soc/ux500/ux500_msp_i2s.h #define TX_FIFO_EMPTY BIT(4) BIT 204 sound/soc/ux500/ux500_msp_i2s.h #define TX_FIFO_FULL BIT(5) BIT 230 sound/soc/ux500/ux500_msp_i2s.h #define RX_DMA_ENABLE BIT(0) BIT 231 sound/soc/ux500/ux500_msp_i2s.h #define TX_DMA_ENABLE BIT(1) BIT 237 sound/soc/ux500/ux500_msp_i2s.h #define RX_SERVICE_INT BIT(0) BIT 238 sound/soc/ux500/ux500_msp_i2s.h #define RX_OVERRUN_ERROR_INT BIT(1) BIT 239 sound/soc/ux500/ux500_msp_i2s.h #define RX_FSYNC_ERR_INT BIT(2) BIT 240 sound/soc/ux500/ux500_msp_i2s.h #define RX_FSYNC_INT BIT(3) BIT 241 sound/soc/ux500/ux500_msp_i2s.h #define TX_SERVICE_INT BIT(4) BIT 242 sound/soc/ux500/ux500_msp_i2s.h #define TX_UNDERRUN_ERR_INT BIT(5) BIT 243 sound/soc/ux500/ux500_msp_i2s.h #define TX_FSYNC_ERR_INT BIT(6) BIT 244 sound/soc/ux500/ux500_msp_i2s.h #define TX_FSYNC_INT BIT(7) BIT 248 sound/soc/ux500/ux500_msp_i2s.h #define MSP_ITCR_ITEN BIT(0) BIT 249 sound/soc/ux500/ux500_msp_i2s.h #define MSP_ITCR_TESTFIFO BIT(1) BIT 29 sound/soc/xilinx/xlnx_formatter_pcm.c #define AUD_CTRL_RESET_MASK BIT(1) BIT 30 sound/soc/xilinx/xlnx_formatter_pcm.c #define AUD_CFG_MM2S_MASK BIT(15) BIT 31 sound/soc/xilinx/xlnx_formatter_pcm.c #define AUD_CFG_S2MM_MASK BIT(31) BIT 41 sound/soc/xilinx/xlnx_formatter_pcm.c #define AUD_STS_IOC_IRQ_MASK BIT(31) BIT 42 sound/soc/xilinx/xlnx_formatter_pcm.c #define AUD_STS_CH_STS_MASK BIT(29) BIT 43 sound/soc/xilinx/xlnx_formatter_pcm.c #define AUD_CTRL_IOC_IRQ_MASK BIT(13) BIT 44 sound/soc/xilinx/xlnx_formatter_pcm.c #define AUD_CTRL_TOUT_IRQ_MASK BIT(14) BIT 45 sound/soc/xilinx/xlnx_formatter_pcm.c #define AUD_CTRL_DMA_EN_MASK BIT(0) BIT 51 sound/soc/xilinx/xlnx_formatter_pcm.c #define CFG_MM2S_PKG_MASK BIT(12) BIT 57 sound/soc/xilinx/xlnx_formatter_pcm.c #define CFG_S2MM_PKG_MASK BIT(28) BIT 34 sound/soc/xilinx/xlnx_spdif.c #define XSPDIF_CORE_ENABLE_MASK BIT(0) BIT 35 sound/soc/xilinx/xlnx_spdif.c #define XSPDIF_FIFO_FLUSH_MASK BIT(1) BIT 36 sound/soc/xilinx/xlnx_spdif.c #define XSPDIF_CH_STS_MASK BIT(5) BIT 37 sound/soc/xilinx/xlnx_spdif.c #define XSPDIF_GLOBAL_IRQ_ENABLE BIT(31) BIT 39 sound/soc/zte/zx-spdif.c #define ZX_CTRL_MODA_18 BIT(6) BIT 44 sound/soc/zte/zx-spdif.c #define ZX_CTRL_ENB BIT(4) BIT 46 sound/soc/zte/zx-spdif.c #define ZX_CTRL_ENB_MASK BIT(4) BIT 48 sound/soc/zte/zx-spdif.c #define ZX_CTRL_TX_OPEN BIT(0) BIT 50 sound/soc/zte/zx-spdif.c #define ZX_CTRL_TX_MASK BIT(0) BIT 56 sound/soc/zte/zx-spdif.c #define ZX_CTRL_LEFT_TRACK BIT(8) BIT 62 sound/soc/zte/zx-spdif.c #define ZX_FIFOCTRL_TX_DMA_EN BIT(2) BIT 64 sound/soc/zte/zx-spdif.c #define ZX_FIFOCTRL_TX_DMA_EN_MASK BIT(2) BIT 65 sound/soc/zte/zx-spdif.c #define ZX_FIFOCTRL_TX_FIFO_RST BIT(0) BIT 66 sound/soc/zte/zx-spdif.c #define ZX_FIFOCTRL_TX_FIFO_RST_MASK BIT(0) BIT 69 sound/soc/zte/zx-spdif.c #define ZX_VALID_LEFT_TRACK BIT(1) BIT 28 sound/soc/zte/zx-tdm.c #define FIFO_CTRL_TX_RST BIT(0) BIT 29 sound/soc/zte/zx-tdm.c #define FIFO_CTRL_RX_RST BIT(0) BIT 32 sound/soc/zte/zx-tdm.c #define FIFO_CTRL_TX_DMA_EN BIT(1) BIT 33 sound/soc/zte/zx-tdm.c #define FIFO_CTRL_RX_DMA_EN BIT(1) BIT 35 sound/soc/zte/zx-tdm.c #define TX_FIFO_RST_MASK BIT(0) BIT 36 sound/soc/zte/zx-tdm.c #define RX_FIFO_RST_MASK BIT(0) BIT 38 sound/soc/zte/zx-tdm.c #define FIFOCTRL_TX_FIFO_RST BIT(0) BIT 39 sound/soc/zte/zx-tdm.c #define FIFOCTRL_RX_FIFO_RST BIT(0) BIT 46 sound/soc/zte/zx-tdm.c #define TIMING_MS_MASK BIT(1) BIT 58 sound/soc/zte/zx-tdm.c #define TIMING_MASTER_MODE BIT(21) BIT 59 sound/soc/zte/zx-tdm.c #define TIMING_LSB_FIRST BIT(20) BIT 62 sound/soc/zte/zx-tdm.c #define TIMING_CLK_SEL_DEF BIT(2) BIT 64 sound/soc/zte/zx-tdm.c #define PROCESS_TX_EN BIT(0) BIT 65 sound/soc/zte/zx-tdm.c #define PROCESS_RX_EN BIT(1) BIT 66 sound/soc/zte/zx-tdm.c #define PROCESS_TDM_EN BIT(2) BIT 676 sound/usb/quirks.c #define CM6206_REG0_DMA_MASTER BIT(15) BIT 681 sound/usb/quirks.c #define CM6206_REG0_SPDIFO_EMPHASIS_CD BIT(3) BIT 682 sound/usb/quirks.c #define CM6206_REG0_SPDIFO_COPYRIGHT_NA BIT(2) BIT 683 sound/usb/quirks.c #define CM6206_REG0_SPDIFO_NON_AUDIO BIT(1) BIT 684 sound/usb/quirks.c #define CM6206_REG0_SPDIFO_PRO_FORMAT BIT(0) BIT 686 sound/usb/quirks.c #define CM6206_REG1_TEST_SEL_CLK BIT(14) BIT 687 sound/usb/quirks.c #define CM6206_REG1_PLLBIN_EN BIT(13) BIT 688 sound/usb/quirks.c #define CM6206_REG1_SOFT_MUTE_EN BIT(12) BIT 689 sound/usb/quirks.c #define CM6206_REG1_GPIO4_OUT BIT(11) BIT 690 sound/usb/quirks.c #define CM6206_REG1_GPIO4_OE BIT(10) BIT 691 sound/usb/quirks.c #define CM6206_REG1_GPIO3_OUT BIT(9) BIT 692 sound/usb/quirks.c #define CM6206_REG1_GPIO3_OE BIT(8) BIT 693 sound/usb/quirks.c #define CM6206_REG1_GPIO2_OUT BIT(7) BIT 694 sound/usb/quirks.c #define CM6206_REG1_GPIO2_OE BIT(6) BIT 695 sound/usb/quirks.c #define CM6206_REG1_GPIO1_OUT BIT(5) BIT 696 sound/usb/quirks.c #define CM6206_REG1_GPIO1_OE BIT(4) BIT 697 sound/usb/quirks.c #define CM6206_REG1_SPDIFO_INVALID BIT(3) BIT 698 sound/usb/quirks.c #define CM6206_REG1_SPDIF_LOOP_EN BIT(2) BIT 699 sound/usb/quirks.c #define CM6206_REG1_SPDIFO_DIS BIT(1) BIT 700 sound/usb/quirks.c #define CM6206_REG1_SPDIFI_MIX BIT(0) BIT 702 sound/usb/quirks.c #define CM6206_REG2_DRIVER_ON BIT(15) BIT 707 sound/usb/quirks.c #define CM6206_REG2_MUTE_HEADPHONE_RIGHT BIT(12) BIT 708 sound/usb/quirks.c #define CM6206_REG2_MUTE_HEADPHONE_LEFT BIT(11) BIT 709 sound/usb/quirks.c #define CM6206_REG2_MUTE_REAR_SURROUND_RIGHT BIT(10) BIT 710 sound/usb/quirks.c #define CM6206_REG2_MUTE_REAR_SURROUND_LEFT BIT(9) BIT 711 sound/usb/quirks.c #define CM6206_REG2_MUTE_SIDE_SURROUND_RIGHT BIT(8) BIT 712 sound/usb/quirks.c #define CM6206_REG2_MUTE_SIDE_SURROUND_LEFT BIT(7) BIT 713 sound/usb/quirks.c #define CM6206_REG2_MUTE_SUBWOOFER BIT(6) BIT 714 sound/usb/quirks.c #define CM6206_REG2_MUTE_CENTER BIT(5) BIT 715 sound/usb/quirks.c #define CM6206_REG2_MUTE_RIGHT_FRONT BIT(3) BIT 716 sound/usb/quirks.c #define CM6206_REG2_MUTE_LEFT_FRONT BIT(3) BIT 717 sound/usb/quirks.c #define CM6206_REG2_EN_BTL BIT(2) BIT 725 sound/usb/quirks.c #define CM6206_REG3_VRAP25EN BIT(10) BIT 726 sound/usb/quirks.c #define CM6206_REG3_MSEL1 BIT(9) BIT 727 sound/usb/quirks.c #define CM6206_REG3_SPDIFI_RATE_44_1K BIT(0 << 7) BIT 728 sound/usb/quirks.c #define CM6206_REG3_SPDIFI_RATE_48K BIT(2 << 7) BIT 729 sound/usb/quirks.c #define CM6206_REG3_SPDIFI_RATE_32K BIT(3 << 7) BIT 730 sound/usb/quirks.c #define CM6206_REG3_PINSEL BIT(6) BIT 731 sound/usb/quirks.c #define CM6206_REG3_FOE BIT(5) BIT 732 sound/usb/quirks.c #define CM6206_REG3_ROE BIT(4) BIT 733 sound/usb/quirks.c #define CM6206_REG3_CBOE BIT(3) BIT 734 sound/usb/quirks.c #define CM6206_REG3_LOSE BIT(2) BIT 735 sound/usb/quirks.c #define CM6206_REG3_HPOE BIT(1) BIT 736 sound/usb/quirks.c #define CM6206_REG3_SPDIFI_CANREC BIT(0) BIT 738 sound/usb/quirks.c #define CM6206_REG5_DA_RSTN BIT(13) BIT 739 sound/usb/quirks.c #define CM6206_REG5_AD_RSTN BIT(12) BIT 740 sound/usb/quirks.c #define CM6206_REG5_SPDIFO_AD2SPDO BIT(12) BIT 745 sound/usb/quirks.c #define CM6206_REG5_CODECM BIT(8) BIT 746 sound/usb/quirks.c #define CM6206_REG5_EN_HPF BIT(7) BIT 747 sound/usb/quirks.c #define CM6206_REG5_T_SEL_DSDA4 BIT(6) BIT 748 sound/usb/quirks.c #define CM6206_REG5_T_SEL_DSDA3 BIT(5) BIT 749 sound/usb/quirks.c #define CM6206_REG5_T_SEL_DSDA2 BIT(4) BIT 750 sound/usb/quirks.c #define CM6206_REG5_T_SEL_DSDA1 BIT(3) BIT 37 sound/usb/usx2y/us122l.c #define US122L_FLAG_US144 BIT(0) BIT 745 sound/x86/intel_hdmi_audio.c had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val)); BIT 820 sound/x86/intel_hdmi_audio.c had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val)); BIT 991 tools/include/uapi/linux/pkt_sched.h #define TC_ETF_DEADLINE_MODE_ON BIT(0) BIT 992 tools/include/uapi/linux/pkt_sched.h #define TC_ETF_OFFLOAD_ON BIT(1) BIT 462 tools/perf/arch/arm/util/cs-etm.c #ifndef BIT BIT 478 tools/perf/arch/arm/util/cs-etm.c if (config_opts & BIT(ETM_OPT_CYCACC)) BIT 479 tools/perf/arch/arm/util/cs-etm.c config |= BIT(ETM4_CFG_BIT_CYCACC); BIT 480 tools/perf/arch/arm/util/cs-etm.c if (config_opts & BIT(ETM_OPT_CTXTID)) BIT 481 tools/perf/arch/arm/util/cs-etm.c config |= BIT(ETM4_CFG_BIT_CTXTID); BIT 482 tools/perf/arch/arm/util/cs-etm.c if (config_opts & BIT(ETM_OPT_TS)) BIT 483 tools/perf/arch/arm/util/cs-etm.c config |= BIT(ETM4_CFG_BIT_TS); BIT 484 tools/perf/arch/arm/util/cs-etm.c if (config_opts & BIT(ETM_OPT_RETSTK)) BIT 485 tools/perf/arch/arm/util/cs-etm.c config |= BIT(ETM4_CFG_BIT_RETSTK); BIT 740 tools/perf/bench/numa.c const uint32_t taps = BIT(1) | BIT(5) | BIT(6) | BIT(31); BIT 16 tools/perf/util/arm-spe-pkt-decoder.c #define NS_FLAG BIT(63) BIT 17 tools/perf/util/arm-spe-pkt-decoder.c #define EL_FLAG (BIT(62) | BIT(61)) BIT 187 tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c packet->count = buf[5] | ((buf[6] & BIT(0)) << 8); BIT 226 tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c packet->type = buf[1] & BIT(7) ? INTEL_PT_PTWRITE_IP : BIT 393 tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c if (byte & BIT(7)) BIT 557 tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c if (!(byte & BIT(0))) { BIT 425 tools/power/x86/intel-speed-select/isst-config.c if (core_mask & BIT(i)) { BIT 516 tools/power/x86/intel-speed-select/isst-config.c if (parameter & BIT(MBOX_CMD_WRITE_BIT)) { BIT 24 tools/power/x86/intel-speed-select/isst-core.c pkg_dev->locked = !!(resp & BIT(24)); BIT 25 tools/power/x86/intel-speed-select/isst-core.c pkg_dev->enabled = !!(resp & BIT(31)); BIT 42 tools/power/x86/intel-speed-select/isst-core.c ctdp_level->fact_support = resp & BIT(0); BIT 43 tools/power/x86/intel-speed-select/isst-core.c ctdp_level->pbf_support = !!(resp & BIT(1)); BIT 44 tools/power/x86/intel-speed-select/isst-core.c ctdp_level->fact_enabled = !!(resp & BIT(16)); BIT 45 tools/power/x86/intel-speed-select/isst-core.c ctdp_level->pbf_enabled = !!(resp & BIT(17)); BIT 173 tools/power/x86/intel-speed-select/isst-core.c req = level | BIT(8) | (avx_level << 16); BIT 336 tools/power/x86/intel-speed-select/isst-core.c req = BIT(16); BIT 339 tools/power/x86/intel-speed-select/isst-core.c req |= BIT(17); BIT 341 tools/power/x86/intel-speed-select/isst-core.c req &= ~BIT(17); BIT 344 tools/power/x86/intel-speed-select/isst-core.c req = BIT(17); BIT 347 tools/power/x86/intel-speed-select/isst-core.c req |= BIT(16); BIT 349 tools/power/x86/intel-speed-select/isst-core.c req &= ~BIT(16); BIT 509 tools/power/x86/intel-speed-select/isst-core.c ret = !!(tdp_control & BIT(31)); BIT 634 tools/power/x86/intel-speed-select/isst-core.c if (resp & BIT(1)) BIT 639 tools/power/x86/intel-speed-select/isst-core.c if (resp & BIT(2)) BIT 662 tools/power/x86/intel-speed-select/isst-core.c req = req | BIT(1); BIT 664 tools/power/x86/intel-speed-select/isst-core.c req = req & ~BIT(1); BIT 667 tools/power/x86/intel-speed-select/isst-core.c req = req | BIT(2); BIT 669 tools/power/x86/intel-speed-select/isst-core.c req = req & ~BIT(2); BIT 672 tools/power/x86/intel-speed-select/isst-core.c BIT(MBOX_CMD_WRITE_BIT), req, &resp); BIT 716 tools/power/x86/intel-speed-select/isst-core.c param = BIT(MBOX_CMD_WRITE_BIT) | clos; BIT 757 tools/power/x86/intel-speed-select/isst-core.c param = BIT(MBOX_CMD_WRITE_BIT) | core_id; BIT 61 tools/power/x86/intel-speed-select/isst-display.c mask[mask_index] |= BIT(bit_index); BIT 97 tools/vm/page-types.c #define BITS_COMPOUND (BIT(COMPOUND_HEAD) | BIT(COMPOUND_TAIL)) BIT 474 tools/vm/page-types.c if (flags & BIT(SLAB)) { BIT 475 tools/vm/page-types.c if (flags & BIT(PRIVATE)) BIT 476 tools/vm/page-types.c flags ^= BIT(PRIVATE) | BIT(SLOB_FREE); BIT 477 tools/vm/page-types.c if (flags & BIT(ACTIVE)) BIT 478 tools/vm/page-types.c flags ^= BIT(ACTIVE) | BIT(SLUB_FROZEN); BIT 479 tools/vm/page-types.c if (flags & BIT(ERROR)) BIT 480 tools/vm/page-types.c flags ^= BIT(ERROR) | BIT(SLUB_DEBUG); BIT 484 tools/vm/page-types.c if ((flags & (BIT(RECLAIM) | BIT(WRITEBACK))) == BIT(RECLAIM)) BIT 485 tools/vm/page-types.c flags ^= BIT(RECLAIM) | BIT(READAHEAD); BIT 488 tools/vm/page-types.c flags |= BIT(SOFTDIRTY); BIT 490 tools/vm/page-types.c flags |= BIT(FILE); BIT 492 tools/vm/page-types.c flags |= BIT(SWAP); BIT 494 tools/vm/page-types.c flags |= BIT(MMAP_EXCLUSIVE); BIT 505 tools/vm/page-types.c if ((flags & BITS_COMPOUND) && !(flags & BIT(HUGE))) BIT 20 virt/kvm/arm/aarch32.c #define DFSR_LPAE BIT(9) BIT 96 virt/kvm/arm/aarch32.c if (sctlr & BIT(31)) BIT 103 virt/kvm/arm/aarch32.c if (!(sctlr & BIT(23))) BIT 119 virt/kvm/arm/aarch32.c if (sctlr & BIT(25)) BIT 146 virt/kvm/arm/aarch32.c if (sctlr & BIT(30)) BIT 598 virt/kvm/arm/hyp/vgic-v3-sr.c __vgic_v3_write_ap0rn(val | BIT(ap % 32), apr); BIT 601 virt/kvm/arm/hyp/vgic-v3-sr.c __vgic_v3_write_ap1rn(val | BIT(ap % 32), apr); BIT 627 virt/kvm/arm/hyp/vgic-v3-sr.c ap0 &= ~BIT(c0); BIT 631 virt/kvm/arm/hyp/vgic-v3-sr.c ap1 &= ~BIT(c1); BIT 803 virt/kvm/arm/mmu.c if ((base ^ io_map_base) & BIT(VA_BITS - 1)) BIT 270 virt/kvm/arm/pmu.c return BIT(ARMV8_PMU_CYCLE_IDX); BIT 272 virt/kvm/arm/pmu.c return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX); BIT 292 virt/kvm/arm/pmu.c if (!(val & BIT(i))) BIT 333 virt/kvm/arm/pmu.c if (!(val & BIT(i))) BIT 466 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(idx); BIT 495 virt/kvm/arm/pmu.c if (!(val & BIT(i))) BIT 518 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i + 1); BIT 521 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i); BIT 556 virt/kvm/arm/pmu.c (__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(select_idx)); BIT 459 virt/kvm/arm/psci.c #define KVM_REG_FEATURE_LEVEL_MASK (BIT(KVM_REG_FEATURE_LEVEL_WIDTH) - 1) BIT 245 virt/kvm/arm/vgic/vgic-its.c #define VITS_DTE_MAX_DEVID_OFFSET (BIT(14) - 1) BIT 246 virt/kvm/arm/vgic/vgic-its.c #define VITS_ITE_MAX_EVENTID_OFFSET (BIT(16) - 1) BIT 857 virt/kvm/arm/vgic/vgic-mmio-v3.c if (!(sgi_cpu_mask & BIT(level0))) BIT 929 virt/kvm/arm/vgic/vgic-mmio-v3.c target_cpus &= ~BIT(level0); BIT 54 virt/kvm/arm/vgic/vgic-mmio.c value |= BIT(i); BIT 73 virt/kvm/arm/vgic/vgic-mmio.c irq->group = !!(val & BIT(i));