TTM_PL_FLAG_VRAM  139 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 			TTM_PL_FLAG_VRAM;
TTM_PL_FLAG_VRAM  590 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 	    bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
TTM_PL_FLAG_VRAM   54 drivers/gpu/drm/drm_gem_vram_helper.c 	if (pl_flag & TTM_PL_FLAG_VRAM)
TTM_PL_FLAG_VRAM   57 drivers/gpu/drm/drm_gem_vram_helper.c 					     TTM_PL_FLAG_VRAM;
TTM_PL_FLAG_VRAM   95 drivers/gpu/drm/drm_gem_vram_helper.c 	drm_gem_vram_placement(gbo, TTM_PL_FLAG_VRAM | TTM_PL_FLAG_SYSTEM);
TTM_PL_FLAG_VRAM  612 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, false);
TTM_PL_FLAG_VRAM 1166 drivers/gpu/drm/nouveau/dispnv04/crtc.c 		ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM, true);
TTM_PL_FLAG_VRAM 1320 drivers/gpu/drm/nouveau/dispnv04/crtc.c 			     TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL,
TTM_PL_FLAG_VRAM 1323 drivers/gpu/drm/nouveau/dispnv04/crtc.c 		ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false);
TTM_PL_FLAG_VRAM  113 drivers/gpu/drm/nouveau/dispnv04/disp.c 		ret = nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM, true);
TTM_PL_FLAG_VRAM  123 drivers/gpu/drm/nouveau/dispnv04/disp.c 		ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, true);
TTM_PL_FLAG_VRAM  143 drivers/gpu/drm/nouveau/dispnv04/overlay.c 	ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false);
TTM_PL_FLAG_VRAM  387 drivers/gpu/drm/nouveau/dispnv04/overlay.c 	ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false);
TTM_PL_FLAG_VRAM 2343 drivers/gpu/drm/nouveau/dispnv50/disp.c 	ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
TTM_PL_FLAG_VRAM 2346 drivers/gpu/drm/nouveau/dispnv50/disp.c 		ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
TTM_PL_FLAG_VRAM  492 drivers/gpu/drm/nouveau/dispnv50/wndw.c 	ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
TTM_PL_FLAG_VRAM  261 drivers/gpu/drm/nouveau/nouveau_bo.c 		    (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram)
TTM_PL_FLAG_VRAM  346 drivers/gpu/drm/nouveau/nouveau_bo.c 	if (type & TTM_PL_FLAG_VRAM)
TTM_PL_FLAG_VRAM  347 drivers/gpu/drm/nouveau/nouveau_bo.c 		pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
TTM_PL_FLAG_VRAM  362 drivers/gpu/drm/nouveau/nouveau_bo.c 	    nvbo->mode && (type & TTM_PL_FLAG_VRAM) &&
TTM_PL_FLAG_VRAM  420 drivers/gpu/drm/nouveau/nouveau_bo.c 	    memtype == TTM_PL_FLAG_VRAM && contig) {
TTM_PL_FLAG_VRAM 1579 drivers/gpu/drm/nouveau/nouveau_bo.c 	nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
TTM_PL_FLAG_VRAM  144 drivers/gpu/drm/nouveau/nouveau_chan.c 		target = TTM_PL_FLAG_VRAM;
TTM_PL_FLAG_VRAM  231 drivers/gpu/drm/nouveau/nouveau_dmem.c 			     TTM_PL_FLAG_VRAM, 0, 0, NULL, NULL,
TTM_PL_FLAG_VRAM  236 drivers/gpu/drm/nouveau/nouveau_dmem.c 	ret = nouveau_bo_pin(chunk->bo, TTM_PL_FLAG_VRAM, false);
TTM_PL_FLAG_VRAM  358 drivers/gpu/drm/nouveau/nouveau_dmem.c 		ret = nouveau_bo_pin(chunk->bo, TTM_PL_FLAG_VRAM, false);
TTM_PL_FLAG_VRAM  363 drivers/gpu/drm/nouveau/nouveau_dmem.c 		ret = nouveau_bo_pin(chunk->bo, TTM_PL_FLAG_VRAM, false);
TTM_PL_FLAG_VRAM  342 drivers/gpu/drm/nouveau/nouveau_fbcon.c 	ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, false);
TTM_PL_FLAG_VRAM  178 drivers/gpu/drm/nouveau/nouveau_gem.c 		flags |= TTM_PL_FLAG_VRAM;
TTM_PL_FLAG_VRAM  300 drivers/gpu/drm/nouveau/nouveau_gem.c 		valid_flags |= TTM_PL_FLAG_VRAM;
TTM_PL_FLAG_VRAM  307 drivers/gpu/drm/nouveau/nouveau_gem.c 		pref_flags |= TTM_PL_FLAG_VRAM;
TTM_PL_FLAG_VRAM  314 drivers/gpu/drm/nouveau/nouveau_gem.c 		pref_flags |= TTM_PL_FLAG_VRAM;
TTM_PL_FLAG_VRAM  130 drivers/gpu/drm/nouveau/nv17_fence.c 	ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
TTM_PL_FLAG_VRAM  133 drivers/gpu/drm/nouveau/nv17_fence.c 		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false);
TTM_PL_FLAG_VRAM   83 drivers/gpu/drm/nouveau/nv50_fence.c 	ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
TTM_PL_FLAG_VRAM   86 drivers/gpu/drm/nouveau/nv50_fence.c 		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false);
TTM_PL_FLAG_VRAM  200 drivers/gpu/drm/nouveau/nv84_fence.c 	domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
TTM_PL_FLAG_VRAM   63 drivers/gpu/drm/qxl/qxl_object.c 		qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_VRAM | pflag;
TTM_PL_FLAG_VRAM   66 drivers/gpu/drm/qxl/qxl_object.c 		qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_VRAM | pflag;
TTM_PL_FLAG_VRAM  117 drivers/gpu/drm/radeon/radeon_object.c 						     TTM_PL_FLAG_VRAM;
TTM_PL_FLAG_VRAM  123 drivers/gpu/drm/radeon/radeon_object.c 					     TTM_PL_FLAG_VRAM;
TTM_PL_FLAG_VRAM  174 drivers/gpu/drm/radeon/radeon_object.c 		    (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
TTM_PL_FLAG_VRAM  363 drivers/gpu/drm/radeon/radeon_object.c 		if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
TTM_PL_FLAG_VRAM  827 drivers/gpu/drm/radeon/radeon_object.c 		if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
TTM_PL_FLAG_VRAM  162 drivers/gpu/drm/radeon/radeon_ttm.c 				if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
TTM_PL_FLAG_VRAM  357 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c 	pl.flags = TTM_PL_FLAG_VRAM | VMW_PL_FLAG_GMR | VMW_PL_FLAG_MOB
TTM_PL_FLAG_VRAM   36 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c 	.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED
TTM_PL_FLAG_VRAM   42 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c 	.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT
TTM_PL_FLAG_VRAM   92 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c 		.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED
TTM_PL_FLAG_VRAM  108 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c 		.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED
TTM_PL_FLAG_VRAM  123 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c 		.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED |
TTM_PL_FLAG_VRAM  176 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c 		.flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED
TTM_PL_FLAG_VRAM   16 include/drm/drm_gem_vram_helper.h #define DRM_GEM_VRAM_PL_FLAG_VRAM	TTM_PL_FLAG_VRAM