TSUNAMI_cchip     227 arch/alpha/kernel/core_tsunami.c 	TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */
TSUNAMI_cchip     231 arch/alpha/kernel/core_tsunami.c 	if (TSUNAMI_cchip->misc.csr & (1L << 28)) {
TSUNAMI_cchip     232 arch/alpha/kernel/core_tsunami.c 		int source = (TSUNAMI_cchip->misc.csr >> 29) & 7;
TSUNAMI_cchip     233 arch/alpha/kernel/core_tsunami.c 		TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */
TSUNAMI_cchip     387 arch/alpha/kernel/core_tsunami.c 	tmp = (unsigned long)(TSUNAMI_cchip - 1);
TSUNAMI_cchip     396 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr);
TSUNAMI_cchip     397 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr);
TSUNAMI_cchip     398 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr);
TSUNAMI_cchip     399 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr);
TSUNAMI_cchip     400 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr);
TSUNAMI_cchip     401 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr);
TSUNAMI_cchip     402 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr);
TSUNAMI_cchip     403 arch/alpha/kernel/core_tsunami.c 	printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr);
TSUNAMI_cchip     417 arch/alpha/kernel/core_tsunami.c 	if (TSUNAMI_cchip->csc.csr & 1L<<14)
TSUNAMI_cchip     448 arch/alpha/kernel/core_tsunami.c 	if (TSUNAMI_cchip->csc.csr & 1L<<14)
TSUNAMI_cchip     467 arch/alpha/kernel/core_tsunami.c 	if (TSUNAMI_cchip->csc.csr & 1L<<14)
TSUNAMI_cchip      50 arch/alpha/kernel/sys_dp264.c 	register tsunami_cchip *cchip = TSUNAMI_cchip;
TSUNAMI_cchip     198 arch/alpha/kernel/sys_dp264.c 	pld = TSUNAMI_cchip->dir0.csr;