TRANSCODER_A     17217 drivers/gpu/drm/i915/display/intel_display.c 		TRANSCODER_A,
TRANSCODER_A      121 drivers/gpu/drm/i915/display/intel_display.h 	case TRANSCODER_A:
TRANSCODER_A     1838 drivers/gpu/drm/i915/display/intel_dp.c 		pipe_config->cpu_transcoder != TRANSCODER_A;
TRANSCODER_A     1854 drivers/gpu/drm/i915/display/intel_dp.c 		pipe_config->cpu_transcoder != TRANSCODER_A;
TRANSCODER_A       94 drivers/gpu/drm/i915/display/intel_psr.c 	case TRANSCODER_A:
TRANSCODER_A      115 drivers/gpu/drm/i915/display/intel_psr.c 		transcoders |= BIT(TRANSCODER_A) |
TRANSCODER_A      180 drivers/gpu/drm/i915/display/intel_psr.c 		transcoders |= BIT(TRANSCODER_A) |
TRANSCODER_A      670 drivers/gpu/drm/i915/display/intel_psr.c 		[TRANSCODER_A] = CHICKEN_TRANS_A,
TRANSCODER_A      680 drivers/gpu/drm/i915/display/intel_psr.c 		cpu_transcoder = TRANSCODER_A;
TRANSCODER_A      475 drivers/gpu/drm/i915/display/intel_vdsc.c 	if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
TRANSCODER_A      231 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
TRANSCODER_A      232 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
TRANSCODER_A      233 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
TRANSCODER_A      234 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
TRANSCODER_A      235 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
TRANSCODER_A      246 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
TRANSCODER_A      249 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
TRANSCODER_A      272 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
TRANSCODER_A      275 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
TRANSCODER_A      298 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
TRANSCODER_A      301 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
TRANSCODER_A     2087 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
TRANSCODER_A     2088 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
TRANSCODER_A     2089 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
TRANSCODER_A     2090 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
TRANSCODER_A     2091 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
TRANSCODER_A     2092 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
TRANSCODER_A     2093 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
TRANSCODER_A     2094 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
TRANSCODER_A     2095 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
TRANSCODER_A     2126 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
TRANSCODER_A     2127 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
TRANSCODER_A     2128 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
TRANSCODER_A     2129 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
TRANSCODER_A     2130 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
TRANSCODER_A     2131 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
TRANSCODER_A     2132 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
TRANSCODER_A     2133 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
TRANSCODER_A     2411 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
TRANSCODER_A     2434 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
TRANSCODER_A     3270 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
TRANSCODER_A       42 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
TRANSCODER_A       45 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
TRANSCODER_A       50 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
TRANSCODER_A       54 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
TRANSCODER_A       60 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
TRANSCODER_A       65 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
TRANSCODER_A       72 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
TRANSCODER_A       78 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
TRANSCODER_A       86 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = PIPE_A_OFFSET, \
TRANSCODER_A       91 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
TRANSCODER_A      736 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = PIPE_A_OFFSET, \
TRANSCODER_A      744 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
TRANSCODER_A      775 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = PIPE_A_OFFSET, \
TRANSCODER_A      783 drivers/gpu/drm/i915/i915_pci.c 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
TRANSCODER_A      255 drivers/gpu/drm/i915/i915_reg.h 					 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \