TPU               256 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	INTC_VECT(SIOF1, 0xd20),      INTC_VECT(TPU, 0xd80),
TPU               257 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	INTC_VECT(TPU, 0xda0),        INTC_VECT(TPU, 0xdc0),
TPU               258 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	INTC_VECT(TPU, 0xde0),        INTC_VECT(IIC, 0xe00),
TPU               273 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	{ 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
TPU               343 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
TPU               402 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	  { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
TPU               417 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
TPU               559 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
TPU               616 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	  { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
TPU               633 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
TPU               923 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 	INTC_VECT(TPU,    0x9A0),
TPU              1048 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 	    0, TPU, 0, TSIF } },
TPU              1071 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 	{ 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
TPU               280 arch/sh/kernel/cpu/sh4a/setup-sh7763.c 	INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
TPU               309 arch/sh/kernel/cpu/sh4a/setup-sh7763.c 	    PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
TPU               327 arch/sh/kernel/cpu/sh4a/setup-sh7763.c 	{ 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
TPU               377 drivers/gpu/drm/radeon/r600_dpm.c 	WREG32_P(CG_TPC, TPU(u), ~TPU_MASK);