TO_DCN20_DPP       54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP       79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      324 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP       53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP       70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP       93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      320 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      386 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      412 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      578 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      731 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      767 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      813 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      832 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      848 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      882 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      901 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      992 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
TO_DCN20_DPP      968 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	kfree(TO_DCN20_DPP(*dpp));