TMU1               46 arch/sh/kernel/cpu/sh3/setup-sh7705.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1               55 arch/sh/kernel/cpu/sh3/setup-sh7705.c 	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
TMU1               35 arch/sh/kernel/cpu/sh3/setup-sh770x.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1               67 arch/sh/kernel/cpu/sh3/setup-sh770x.c 	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
TMU1               48 arch/sh/kernel/cpu/sh3/setup-sh7710.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1               57 arch/sh/kernel/cpu/sh3/setup-sh7710.c 	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
TMU1              237 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	INTC_VECT(TMU0, 0x400),       INTC_VECT(TMU1, 0x420),
TMU1              266 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	{ 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
TMU1               93 arch/sh/kernel/cpu/sh4/setup-sh4-202.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1              103 arch/sh/kernel/cpu/sh4/setup-sh4-202.c 	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
TMU1              192 arch/sh/kernel/cpu/sh4/setup-sh7750.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1              205 arch/sh/kernel/cpu/sh4/setup-sh7750.c 	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
TMU1               71 arch/sh/kernel/cpu/sh4/setup-sh7760.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1              103 arch/sh/kernel/cpu/sh4/setup-sh7760.c 	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
TMU1              361 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1              387 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
TMU1              408 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
TMU1              299 arch/sh/kernel/cpu/sh4a/setup-sh7366.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1              324 arch/sh/kernel/cpu/sh4a/setup-sh7366.c 	  { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
TMU1              345 arch/sh/kernel/cpu/sh4a/setup-sh7366.c 	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
TMU1              574 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1              601 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
TMU1              622 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
TMU1              846 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 	INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
TMU1              945 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 	INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
TMU1             1060 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 	{ INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
TMU1              256 arch/sh/kernel/cpu/sh4a/setup-sh7763.c 	INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
TMU1              296 arch/sh/kernel/cpu/sh4a/setup-sh7763.c 	INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
TMU1              314 arch/sh/kernel/cpu/sh4a/setup-sh7763.c 	{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
TMU1              358 arch/sh/kernel/cpu/sh4a/setup-sh7770.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1              406 arch/sh/kernel/cpu/sh4a/setup-sh7770.c 	INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
TMU1              443 arch/sh/kernel/cpu/sh4a/setup-sh7770.c 	  { TMU1, TMU2, TMU2_TICPI, TMU3 } },
TMU1              317 arch/sh/kernel/cpu/sh4a/setup-sh7780.c 	INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
TMU1              350 arch/sh/kernel/cpu/sh4a/setup-sh7780.c 	INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
TMU1              363 arch/sh/kernel/cpu/sh4a/setup-sh7780.c 	{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
TMU1              393 arch/sh/kernel/cpu/sh4a/setup-sh7785.c 	INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
TMU1              433 arch/sh/kernel/cpu/sh4a/setup-sh7785.c 	INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
TMU1              461 arch/sh/kernel/cpu/sh4a/setup-sh7785.c 	{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
TMU1              196 arch/sh/kernel/cpu/sh4a/setup-shx3.c 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
TMU1              268 arch/sh/kernel/cpu/sh4a/setup-shx3.c 	    0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
TMU1              291 arch/sh/kernel/cpu/sh4a/setup-shx3.c 						 TMU3, TMU2, TMU1, TMU0 } },