TMDS_PIXEL_ENCODING  529 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
TMDS_PIXEL_ENCODING  532 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
TMDS_PIXEL_ENCODING  539 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
TMDS_PIXEL_ENCODING  542 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
TMDS_PIXEL_ENCODING  285 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
TMDS_PIXEL_ENCODING  296 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
TMDS_PIXEL_ENCODING  304 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
TMDS_PIXEL_ENCODING  314 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
TMDS_PIXEL_ENCODING  480 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint8_t TMDS_PIXEL_ENCODING;
TMDS_PIXEL_ENCODING  611 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t TMDS_PIXEL_ENCODING;
TMDS_PIXEL_ENCODING  482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
TMDS_PIXEL_ENCODING  485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
TMDS_PIXEL_ENCODING  257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
TMDS_PIXEL_ENCODING  447 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	type TMDS_PIXEL_ENCODING;\