TLB_V4_D_PAGE     102 arch/arm/include/asm/tlbflush.h 			 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
TLB_V4_D_PAGE     119 arch/arm/include/asm/tlbflush.h 			 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
TLB_V4_D_PAGE     136 arch/arm/include/asm/tlbflush.h 			 TLB_V4_D_PAGE)
TLB_V4_D_PAGE     427 arch/arm/include/asm/tlbflush.h 	if (possible_tlb_flags & (TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&
TLB_V4_D_PAGE     430 arch/arm/include/asm/tlbflush.h 		tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
TLB_V4_D_PAGE     485 arch/arm/include/asm/tlbflush.h 	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);