TITAN             114 arch/alpha/kernel/machvec_impl.h #define DO_TITAN_IO	IO(TITAN,titan)
TITAN            3001 arch/powerpc/xmon/ppc-opc.c #define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
TITAN            4785 arch/powerpc/xmon/ppc-opc.c {"isel",	XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0,		{RT, RA0, RB, CRB}},
TITAN            4842 arch/powerpc/xmon/ppc-opc.c {"dlmzb",	XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0,		{RA, RS, RB}},
TITAN            4843 arch/powerpc/xmon/ppc-opc.c {"dlmzb.",	XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0,		{RA, RS, RB}},
TITAN            4896 arch/powerpc/xmon/ppc-opc.c {"dcbtstls",	X(31,134),	X_MASK, PPCCHLK|PPC476|TITAN, 0,	{CT, RA0, RB}},
TITAN            4948 arch/powerpc/xmon/ppc-opc.c {"dcbtls",	X(31,166),	X_MASK,	 PPCCHLK|PPC476|TITAN, 0,	{CT, RA0, RB}},
TITAN            5020 arch/powerpc/xmon/ppc-opc.c {"icblc",	X(31,230),	X_MASK,	PPCCHLK|PPC476|TITAN, 0,	{CT, RA0, RB}},
TITAN            5066 arch/powerpc/xmon/ppc-opc.c {"mfdcrx",	X(31,259),	X_MASK, BOOKE|PPCA2|PPC476, TITAN,	{RS, RA}},
TITAN            5096 arch/powerpc/xmon/ppc-opc.c {"mfapidi",	X(31,275),	X_MASK,	     BOOKE,	E500|TITAN,	{RT, RA}},
TITAN            5126 arch/powerpc/xmon/ppc-opc.c {"tlbie",	X(31,306),	X_MASK|1<<20,POWER9,	TITAN,		{RB, RS, RIC, PRS, X_R}},
TITAN            5127 arch/powerpc/xmon/ppc-opc.c {"tlbie",	X(31,306),	XRA_MASK,    POWER7,	POWER9|TITAN,	{RB, RS}},
TITAN            5128 arch/powerpc/xmon/ppc-opc.c {"tlbie",	X(31,306),	XRTLRA_MASK, PPC,    E500|POWER7|TITAN,	{RB, LOPT}},
TITAN            5135 arch/powerpc/xmon/ppc-opc.c {"eciwx",	X(31,310),	X_MASK,	     PPC,	E500|TITAN,	{RT, RA0, RB}},
TITAN            5180 arch/powerpc/xmon/ppc-opc.c {"mfdcr",	X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
TITAN            5185 arch/powerpc/xmon/ppc-opc.c {"dcread",	X(31,326),	X_MASK,	  PPC476|TITAN,	0,		{RT, RA0, RB}},
TITAN            5199 arch/powerpc/xmon/ppc-opc.c {"mfrtcu",	XSPR(31,339,  4), XSPR_MASK, COM,	TITAN,		{RT}},
TITAN            5200 arch/powerpc/xmon/ppc-opc.c {"mfrtcl",	XSPR(31,339,  5), XSPR_MASK, COM,	TITAN,		{RT}},
TITAN            5206 arch/powerpc/xmon/ppc-opc.c {"mfdsisr",	XSPR(31,339, 18), XSPR_MASK, COM,	TITAN,		{RT}},
TITAN            5207 arch/powerpc/xmon/ppc-opc.c {"mfdar",	XSPR(31,339, 19), XSPR_MASK, COM,	TITAN,		{RT}},
TITAN            5210 arch/powerpc/xmon/ppc-opc.c {"mfsdr1",	XSPR(31,339, 25), XSPR_MASK, COM,	TITAN,		{RT}},
TITAN            5252 arch/powerpc/xmon/ppc-opc.c {"mfear",	XSPR(31,339,282), XSPR_MASK, PPC,	TITAN,		{RT}},
TITAN            5289 arch/powerpc/xmon/ppc-opc.c {"mfibatu",	XSPR(31,339,528), XSPRBAT_MASK, PPC,	TITAN,		{RT, SPRBAT}},
TITAN            5291 arch/powerpc/xmon/ppc-opc.c {"mfibatl",	XSPR(31,339,529), XSPRBAT_MASK, PPC,	TITAN,		{RT, SPRBAT}},
TITAN            5294 arch/powerpc/xmon/ppc-opc.c {"mfdbatu",	XSPR(31,339,536), XSPRBAT_MASK, PPC,	TITAN,		{RT, SPRBAT}},
TITAN            5295 arch/powerpc/xmon/ppc-opc.c {"mfdbatl",	XSPR(31,339,537), XSPRBAT_MASK, PPC,	TITAN,		{RT, SPRBAT}},
TITAN            5305 arch/powerpc/xmon/ppc-opc.c {"mfmcar",	XSPR(31,339,573), XSPR_MASK, PPCRFMCI,	TITAN,		{RT}},
TITAN            5328 arch/powerpc/xmon/ppc-opc.c {"mfivndx",	XSPR(31,339,880), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5329 arch/powerpc/xmon/ppc-opc.c {"mfdvndx",	XSPR(31,339,881), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5330 arch/powerpc/xmon/ppc-opc.c {"mfivlim",	XSPR(31,339,882), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5331 arch/powerpc/xmon/ppc-opc.c {"mfdvlim",	XSPR(31,339,883), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5332 arch/powerpc/xmon/ppc-opc.c {"mfclcsr",	XSPR(31,339,884), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5333 arch/powerpc/xmon/ppc-opc.c {"mfccr1",	XSPR(31,339,888), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5336 arch/powerpc/xmon/ppc-opc.c {"mfrstcfg",	XSPR(31,339,923), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5337 arch/powerpc/xmon/ppc-opc.c {"mfdcdbtrl",	XSPR(31,339,924), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5338 arch/powerpc/xmon/ppc-opc.c {"mfdcdbtrh",	XSPR(31,339,925), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5339 arch/powerpc/xmon/ppc-opc.c {"mficdbtr",	XSPR(31,339,927), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5349 arch/powerpc/xmon/ppc-opc.c {"mfmmucr",	XSPR(31,339,946), XSPR_MASK, TITAN,	0,		{RT}},
TITAN            5350 arch/powerpc/xmon/ppc-opc.c {"mfccr0",	XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0,		{RT}},
TITAN            5367 arch/powerpc/xmon/ppc-opc.c {"mficdbdr",	XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0,		{RT}},
TITAN            5381 arch/powerpc/xmon/ppc-opc.c {"mfdbdr",	XSPR(31,339,1011), XSPR_MASK, TITAN,	0,		{RS}},
TITAN            5415 arch/powerpc/xmon/ppc-opc.c {"tlbia",	X(31,370),	0xffffffff,  PPC,	E500|TITAN,	{0}},
TITAN            5429 arch/powerpc/xmon/ppc-opc.c {"mtdcrx",	X(31,387),	X_MASK,	     BOOKE|PPCA2|PPC476, TITAN,	{RA, RS}},
TITAN            5434 arch/powerpc/xmon/ppc-opc.c {"dcblc",	X(31,390),	X_MASK,	 PPCCHLK|PPC476|TITAN, 0,	{CT, RA0, RB}},
TITAN            5482 arch/powerpc/xmon/ppc-opc.c {"ecowx",	X(31,438),	X_MASK,	     PPC,	E500|TITAN,	{RT, RA0, RB}},
TITAN            5534 arch/powerpc/xmon/ppc-opc.c {"mtdcr",	X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
TITAN            5539 arch/powerpc/xmon/ppc-opc.c {"dccci",	X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0,	{RAOPT, RBOPT}},
TITAN            5559 arch/powerpc/xmon/ppc-opc.c {"mtdsisr",	XSPR(31,467, 18), XSPR_MASK, COM,	TITAN,		{RS}},
TITAN            5560 arch/powerpc/xmon/ppc-opc.c {"mtdar",	XSPR(31,467, 19), XSPR_MASK, COM,	TITAN,		{RS}},
TITAN            5561 arch/powerpc/xmon/ppc-opc.c {"mtrtcu",	XSPR(31,467, 20), XSPR_MASK, COM,	TITAN,		{RS}},
TITAN            5562 arch/powerpc/xmon/ppc-opc.c {"mtrtcl",	XSPR(31,467, 21), XSPR_MASK, COM,	TITAN,		{RS}},
TITAN            5565 arch/powerpc/xmon/ppc-opc.c {"mtsdr1",	XSPR(31,467, 25), XSPR_MASK, COM,	TITAN,		{RS}},
TITAN            5605 arch/powerpc/xmon/ppc-opc.c {"mtear",	XSPR(31,467,282), XSPR_MASK, PPC,	TITAN,		{RS}},
TITAN            5642 arch/powerpc/xmon/ppc-opc.c {"mtibatu",	XSPR(31,467,528), XSPRBAT_MASK, PPC,	TITAN,		{SPRBAT, RS}},
TITAN            5644 arch/powerpc/xmon/ppc-opc.c {"mtibatl",	XSPR(31,467,529), XSPRBAT_MASK, PPC,	TITAN,		{SPRBAT, RS}},
TITAN            5647 arch/powerpc/xmon/ppc-opc.c {"mtdbatu",	XSPR(31,467,536), XSPRBAT_MASK, PPC,	TITAN,		{SPRBAT, RS}},
TITAN            5648 arch/powerpc/xmon/ppc-opc.c {"mtdbatl",	XSPR(31,467,537), XSPRBAT_MASK, PPC,	TITAN,		{SPRBAT, RS}},
TITAN            5652 arch/powerpc/xmon/ppc-opc.c {"mtivndx",	XSPR(31,467,880), XSPR_MASK, TITAN,	0,		{RS}},
TITAN            5653 arch/powerpc/xmon/ppc-opc.c {"mtdvndx",	XSPR(31,467,881), XSPR_MASK, TITAN,	0,		{RS}},
TITAN            5654 arch/powerpc/xmon/ppc-opc.c {"mtivlim",	XSPR(31,467,882), XSPR_MASK, TITAN,	0,		{RS}},
TITAN            5655 arch/powerpc/xmon/ppc-opc.c {"mtdvlim",	XSPR(31,467,883), XSPR_MASK, TITAN,	0,		{RS}},
TITAN            5656 arch/powerpc/xmon/ppc-opc.c {"mtclcsr",	XSPR(31,467,884), XSPR_MASK, TITAN,	0,		{RS}},
TITAN            5657 arch/powerpc/xmon/ppc-opc.c {"mtccr1",	XSPR(31,467,888), XSPR_MASK, TITAN,	0,		{RS}},
TITAN            5669 arch/powerpc/xmon/ppc-opc.c {"mtrmmucr",	XSPR(31,467,946), XSPR_MASK, TITAN,	0,		{RS}},
TITAN            5670 arch/powerpc/xmon/ppc-opc.c {"mtccr0",	XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0,		{RS}},
TITAN            5700 arch/powerpc/xmon/ppc-opc.c {"mtdbdr",	XSPR(31,467,1011), XSPR_MASK, TITAN,	0,		{RS}},
TITAN            5728 arch/powerpc/xmon/ppc-opc.c {"icbtls",	X(31,486),	X_MASK,	 PPCCHLK|PPC476|TITAN, 0,	{CT, RA0, RB}},
TITAN            6213 arch/powerpc/xmon/ppc-opc.c {"iccci",	X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0,	 {RAOPT, RBOPT}},
TITAN            6245 arch/powerpc/xmon/ppc-opc.c {"icread",	X(31,998),     XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0,	{RA0, RB}},
TITAN            6260 arch/powerpc/xmon/ppc-opc.c {"tlbli",	X(31,1010),	XRTRA_MASK,  PPC,	TITAN,		{RB}},
TITAN            6367 arch/powerpc/xmon/ppc-opc.c {"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	TITAN|PPCVLE,	{FRT, FRB}},
TITAN            6368 arch/powerpc/xmon/ppc-opc.c {"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	TITAN|PPCVLE,	{FRT, FRB}},
TITAN            6722 arch/powerpc/xmon/ppc-opc.c {"fsqrt",	A(63,22,0),    AFRAFRC_MASK, PPCPWR2,	TITAN|PPCVLE,	{FRT, FRB}},
TITAN            6723 arch/powerpc/xmon/ppc-opc.c {"fsqrt.",	A(63,22,1),    AFRAFRC_MASK, PPCPWR2,	TITAN|PPCVLE,	{FRT, FRB}},