TIMER1_2_CONTROL_OFFSET  115 arch/arm/mach-cns3xxx/core.c 	writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  121 arch/arm/mach-cns3xxx/core.c 	unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  125 arch/arm/mach-cns3xxx/core.c 	writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  131 arch/arm/mach-cns3xxx/core.c 	unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  138 arch/arm/mach-cns3xxx/core.c 	writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  145 arch/arm/mach-cns3xxx/core.c 	unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  148 arch/arm/mach-cns3xxx/core.c 	writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  211 arch/arm/mach-cns3xxx/core.c 	writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  229 arch/arm/mach-cns3xxx/core.c 	val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  231 arch/arm/mach-cns3xxx/core.c 	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  243 arch/arm/mach-cns3xxx/core.c 	val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
TIMER1_2_CONTROL_OFFSET  245 arch/arm/mach-cns3xxx/core.c 	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);