TF_SF 182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\ TF_SF 183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\ TF_SF 184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\ TF_SF 185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\ TF_SF 186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\ TF_SF 187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\ TF_SF 188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\ TF_SF 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\ TF_SF 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\ TF_SF 191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\ TF_SF 192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\ TF_SF 193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\ TF_SF 194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\ TF_SF 195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\ TF_SF 196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\ TF_SF 197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\ TF_SF 198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\ TF_SF 199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\ TF_SF 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\ TF_SF 201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\ TF_SF 202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\ TF_SF 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\ TF_SF 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\ TF_SF 206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\ TF_SF 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\ TF_SF 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\ TF_SF 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\ TF_SF 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\ TF_SF 211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\ TF_SF 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\ TF_SF 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\ TF_SF 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\ TF_SF 215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\ TF_SF 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ TF_SF 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\ TF_SF 218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\ TF_SF 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ TF_SF 220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ TF_SF 221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ TF_SF 222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ TF_SF 223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\ TF_SF 224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\ TF_SF 225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\ TF_SF 226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\ TF_SF 227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\ TF_SF 228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\ TF_SF 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\ TF_SF 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\ TF_SF 231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\ TF_SF 232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\ TF_SF 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\ TF_SF 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\ TF_SF 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\ TF_SF 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\ TF_SF 237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\ TF_SF 238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\ TF_SF 239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\ TF_SF 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\ TF_SF 241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\ TF_SF 242 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\ TF_SF 243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\ TF_SF 244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\ TF_SF 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\ TF_SF 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\ TF_SF 247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\ TF_SF 248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\ TF_SF 249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\ TF_SF 250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\ TF_SF 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\ TF_SF 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\ TF_SF 253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ TF_SF 254 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ TF_SF 255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ TF_SF 256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ TF_SF 257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ TF_SF 258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ TF_SF 259 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ TF_SF 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \ TF_SF 261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF 262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \ TF_SF 263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ TF_SF 264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \ TF_SF 265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ TF_SF 266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ TF_SF 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ TF_SF 268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ TF_SF 269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \ TF_SF 270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ TF_SF 271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ TF_SF 272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \ TF_SF 273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ TF_SF 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ TF_SF 275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \ TF_SF 276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ TF_SF 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ TF_SF 278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ TF_SF 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ TF_SF 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ TF_SF 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ TF_SF 282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ TF_SF 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ TF_SF 284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ TF_SF 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ TF_SF 286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \ TF_SF 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF 288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \ TF_SF 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ TF_SF 290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \ TF_SF 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ TF_SF 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ TF_SF 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ TF_SF 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ TF_SF 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \ TF_SF 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ TF_SF 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ TF_SF 298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \ TF_SF 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ TF_SF 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ TF_SF 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \ TF_SF 302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ TF_SF 303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ TF_SF 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ TF_SF 305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ TF_SF 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ TF_SF 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ TF_SF 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ TF_SF 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ TF_SF 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ TF_SF 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ TF_SF 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \ TF_SF 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \ TF_SF 314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \ TF_SF 315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \ TF_SF 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \ TF_SF 317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \ TF_SF 318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \ TF_SF 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ TF_SF 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ TF_SF 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ TF_SF 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ TF_SF 324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ TF_SF 325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \ TF_SF 326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \ TF_SF 327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \ TF_SF 328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \ TF_SF 329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \ TF_SF 330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ TF_SF 331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh) TF_SF 335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\ TF_SF 336 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\ TF_SF 337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\ TF_SF 338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\ TF_SF 339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\ TF_SF 340 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\ TF_SF 341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\ TF_SF 342 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\ TF_SF 343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\ TF_SF 344 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\ TF_SF 345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\ TF_SF 346 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\ TF_SF 347 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\ TF_SF 348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \ TF_SF 349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \ TF_SF 350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ TF_SF 351 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ TF_SF 352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ TF_SF 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \ TF_SF 354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \ TF_SF 355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \ TF_SF 356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \ TF_SF 357 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \ TF_SF 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \ TF_SF 359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \ TF_SF 360 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \ TF_SF 361 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \ TF_SF 362 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \ TF_SF 363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \ TF_SF 364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \ TF_SF 365 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF 366 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \ TF_SF 367 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ TF_SF 368 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \ TF_SF 369 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ TF_SF 370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ TF_SF 371 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ TF_SF 372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ TF_SF 373 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \ TF_SF 374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ TF_SF 375 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ TF_SF 376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \ TF_SF 377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ TF_SF 378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ TF_SF 379 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \ TF_SF 380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ TF_SF 381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ TF_SF 382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ TF_SF 383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ TF_SF 384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ TF_SF 385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ TF_SF 386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ TF_SF 387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ TF_SF 388 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ TF_SF 389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ TF_SF 390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \ TF_SF 391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF 392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \ TF_SF 393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ TF_SF 394 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \ TF_SF 395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ TF_SF 396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ TF_SF 397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ TF_SF 398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ TF_SF 399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \ TF_SF 400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ TF_SF 401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ TF_SF 402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \ TF_SF 403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ TF_SF 404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ TF_SF 405 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \ TF_SF 406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ TF_SF 407 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ TF_SF 408 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ TF_SF 409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ TF_SF 410 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ TF_SF 411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ TF_SF 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ TF_SF 413 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ TF_SF 414 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ TF_SF 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ TF_SF 416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ TF_SF 417 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \ TF_SF 418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \ TF_SF 419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \ TF_SF 420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \ TF_SF 421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \ TF_SF 422 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \ TF_SF 423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \ TF_SF 424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \ TF_SF 425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \ TF_SF 426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \ TF_SF 427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \ TF_SF 428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \ TF_SF 429 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \ TF_SF 430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \ TF_SF 431 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, mask_sh), \ TF_SF 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ TF_SF 433 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ TF_SF 434 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ TF_SF 435 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ TF_SF 436 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh) TF_SF 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_LUT_MODE, mask_sh), \ TF_SF 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_B, mask_sh), \ TF_SF 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_G, mask_sh), \ TF_SF 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ TF_SF 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_R, mask_sh), \ TF_SF 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ TF_SF 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ TF_SF 179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ TF_SF 180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ TF_SF 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \ TF_SF 182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ TF_SF 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ TF_SF 184 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \ TF_SF 185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ TF_SF 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ TF_SF 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \ TF_SF 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ TF_SF 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ TF_SF 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ TF_SF 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ TF_SF 192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ TF_SF 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ TF_SF 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ TF_SF 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ TF_SF 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ TF_SF 197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ TF_SF 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ TF_SF 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ TF_SF 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ TF_SF 201 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ TF_SF 202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ TF_SF 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ TF_SF 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ TF_SF 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ TF_SF 206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ TF_SF 207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ TF_SF 208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ TF_SF 209 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ TF_SF 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ TF_SF 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ TF_SF 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ TF_SF 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ TF_SF 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ TF_SF 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ TF_SF 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ TF_SF 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ TF_SF 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ TF_SF 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ TF_SF 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ TF_SF 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ TF_SF 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ TF_SF 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ TF_SF 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ TF_SF 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ TF_SF 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ TF_SF 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ TF_SF 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ TF_SF 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ TF_SF 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ TF_SF 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ TF_SF 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ TF_SF 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ TF_SF 234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ TF_SF 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ TF_SF 236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ TF_SF 237 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ TF_SF 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ TF_SF 239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ TF_SF 240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ TF_SF 241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ TF_SF 242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ TF_SF 243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ TF_SF 244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ TF_SF 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ TF_SF 246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ TF_SF 247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ TF_SF 248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ TF_SF 249 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ TF_SF 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ TF_SF 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ TF_SF 252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ TF_SF 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ TF_SF 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ TF_SF 255 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ TF_SF 256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ TF_SF 257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ TF_SF 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_B, mask_sh), \ TF_SF 259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF 260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_G, mask_sh), \ TF_SF 261 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ TF_SF 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_R, mask_sh), \ TF_SF 263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ TF_SF 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ TF_SF 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ TF_SF 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ TF_SF 267 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \ TF_SF 268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ TF_SF 269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ TF_SF 270 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \ TF_SF 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ TF_SF 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ TF_SF 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \ TF_SF 274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ TF_SF 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ TF_SF 276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ TF_SF 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ TF_SF 278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ TF_SF 279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ TF_SF 280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ TF_SF 281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ TF_SF 282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ TF_SF 283 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ TF_SF 284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ TF_SF 285 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ TF_SF 286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ TF_SF 287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ TF_SF 288 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ TF_SF 289 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ TF_SF 290 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ TF_SF 291 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ TF_SF 292 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ TF_SF 293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ TF_SF 294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ TF_SF 295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ TF_SF 296 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ TF_SF 297 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ TF_SF 298 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ TF_SF 299 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ TF_SF 300 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ TF_SF 301 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ TF_SF 302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ TF_SF 303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ TF_SF 304 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ TF_SF 305 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ TF_SF 306 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ TF_SF 307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ TF_SF 308 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ TF_SF 309 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ TF_SF 310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ TF_SF 311 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ TF_SF 312 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ TF_SF 313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ TF_SF 314 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ TF_SF 315 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ TF_SF 316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ TF_SF 317 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ TF_SF 318 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ TF_SF 319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ TF_SF 320 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ TF_SF 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ TF_SF 322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ TF_SF 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ TF_SF 324 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ TF_SF 325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ TF_SF 326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ TF_SF 327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ TF_SF 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ TF_SF 329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ TF_SF 330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ TF_SF 331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ TF_SF 332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ TF_SF 333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ TF_SF 334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ TF_SF 335 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ TF_SF 336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ TF_SF 337 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ TF_SF 338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ TF_SF 339 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ TF_SF 340 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ TF_SF 341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ TF_SF 342 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ TF_SF 343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ TF_SF 344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \ TF_SF 345 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \ TF_SF 346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \ TF_SF 347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_LUT_INDEX, CM_BLNDGAM_LUT_INDEX, mask_sh), \ TF_SF 348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_LUT_DATA, CM_BLNDGAM_LUT_DATA, mask_sh), \ TF_SF 349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, mask_sh), \ TF_SF 350 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \ TF_SF 351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_SIZE, mask_sh), \ TF_SF 352 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_INDEX, CM_3DLUT_INDEX, mask_sh), \ TF_SF 353 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA0, mask_sh), \ TF_SF 354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA1, mask_sh), \ TF_SF 355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_DATA_30BIT, CM_3DLUT_DATA_30BIT, mask_sh), \ TF_SF 356 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, mask_sh), \ TF_SF 357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_RAM_SEL, mask_sh), \ TF_SF 358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, mask_sh), \ TF_SF 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_CONFIG_STATUS, mask_sh), \ TF_SF 360 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_READ_SEL, mask_sh), \ TF_SF 361 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh), \ TF_SF 362 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh), \ TF_SF 363 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF 364 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_G, mask_sh), \ TF_SF 365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ TF_SF 366 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_R, mask_sh), \ TF_SF 367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ TF_SF 368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_B, mask_sh), \ TF_SF 369 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ TF_SF 370 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_G, mask_sh), \ TF_SF 371 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ TF_SF 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_R, mask_sh), \ TF_SF 373 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ TF_SF 374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ TF_SF 375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ TF_SF 376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ TF_SF 377 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ TF_SF 378 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ TF_SF 379 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ TF_SF 380 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ TF_SF 381 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ TF_SF 382 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ TF_SF 383 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ TF_SF 384 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ TF_SF 385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ TF_SF 386 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ TF_SF 387 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ TF_SF 388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ TF_SF 389 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ TF_SF 390 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ TF_SF 391 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ TF_SF 392 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ TF_SF 393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ TF_SF 394 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ TF_SF 395 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ TF_SF 396 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ TF_SF 397 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ TF_SF 398 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ TF_SF 399 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ TF_SF 400 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ TF_SF 401 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ TF_SF 402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ TF_SF 403 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ TF_SF 404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ TF_SF 405 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ TF_SF 406 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ TF_SF 407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ TF_SF 408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ TF_SF 409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ TF_SF 410 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ TF_SF 411 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ TF_SF 412 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ TF_SF 413 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ TF_SF 414 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ TF_SF 415 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ TF_SF 416 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ TF_SF 417 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ TF_SF 418 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ TF_SF 419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ TF_SF 420 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ TF_SF 421 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ TF_SF 422 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ TF_SF 423 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ TF_SF 424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ TF_SF 425 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ TF_SF 426 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ TF_SF 427 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ TF_SF 428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ TF_SF 429 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ TF_SF 430 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ TF_SF 431 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ TF_SF 432 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ TF_SF 433 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ TF_SF 434 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ TF_SF 435 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ TF_SF 436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ TF_SF 437 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ TF_SF 438 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ TF_SF 439 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ TF_SF 440 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ TF_SF 441 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ TF_SF 442 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh), \ TF_SF 443 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF 444 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_G, mask_sh), \ TF_SF 445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ TF_SF 446 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_R, mask_sh), \ TF_SF 447 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ TF_SF 448 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh), \ TF_SF 449 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ TF_SF 450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_G, mask_sh), \ TF_SF 451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ TF_SF 452 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_R, mask_sh), \ TF_SF 453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ TF_SF 454 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ TF_SF 455 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ TF_SF 456 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ TF_SF 457 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ TF_SF 458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ TF_SF 459 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ TF_SF 460 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ TF_SF 461 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ TF_SF 462 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ TF_SF 463 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ TF_SF 464 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ TF_SF 465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ TF_SF 466 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ TF_SF 467 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ TF_SF 468 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ TF_SF 469 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ TF_SF 470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ TF_SF 471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ TF_SF 472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ TF_SF 473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ TF_SF 474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ TF_SF 475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ TF_SF 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ TF_SF 477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ TF_SF 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ TF_SF 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ TF_SF 480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ TF_SF 481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ TF_SF 482 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ TF_SF 483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ TF_SF 484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ TF_SF 485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ TF_SF 486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ TF_SF 487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ TF_SF 488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ TF_SF 489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ TF_SF 490 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ TF_SF 491 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ TF_SF 492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ TF_SF 493 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ TF_SF 494 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ TF_SF 495 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ TF_SF 496 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ TF_SF 497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ TF_SF 498 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ TF_SF 499 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ TF_SF 500 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ TF_SF 501 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ TF_SF 502 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ TF_SF 503 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ TF_SF 504 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ TF_SF 505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ TF_SF 506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ TF_SF 507 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ TF_SF 508 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ TF_SF 509 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ TF_SF 510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ TF_SF 511 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ TF_SF 512 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ TF_SF 513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ TF_SF 514 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ TF_SF 515 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ TF_SF 516 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ TF_SF 517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ TF_SF 518 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ TF_SF 519 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ TF_SF 520 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ TF_SF 521 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ TF_SF 522 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_EN_MASK, mask_sh), \ TF_SF 523 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_SEL, mask_sh), \ TF_SF 524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS, mask_sh), \ TF_SF 525 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_LUT_INDEX, CM_SHAPER_LUT_INDEX, mask_sh), \ TF_SF 526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh), \ TF_SF 527 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, mask_sh), \ TF_SF 528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \ TF_SF 529 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ TF_SF 530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ TF_SF 531 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ TF_SF 532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ TF_SF 533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \ TF_SF 534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \ TF_SF 535 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \ TF_SF 536 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \ TF_SF 537 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \ TF_SF 538 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \ TF_SF 539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \ TF_SF 540 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \ TF_SF 541 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \ TF_SF 542 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \ TF_SF 543 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \ TF_SF 544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \ TF_SF 545 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \ TF_SF 546 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \ TF_SF 547 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \ TF_SF 548 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \ TF_SF 549 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \ TF_SF 550 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \ TF_SF 551 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \ TF_SF 552 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \ TF_SF 553 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \ TF_SF 554 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \ TF_SF 555 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \ TF_SF 556 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \ TF_SF 557 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \ TF_SF 558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \ TF_SF 559 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\ TF_SF 560 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\ TF_SF 561 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)