TEGRA_INIT_DATA_NODIV 781 drivers/clk/tegra/clk-tegra20.c TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA), TEGRA_INIT_DATA_NODIV 782 drivers/clk/tegra/clk-tegra20.c TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB), TEGRA_INIT_DATA_NODIV 783 drivers/clk/tegra/clk-tegra20.c TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC), TEGRA_INIT_DATA_NODIV 784 drivers/clk/tegra/clk-tegra20.c TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD), TEGRA_INIT_DATA_NODIV 785 drivers/clk/tegra/clk-tegra20.c TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE), TEGRA_INIT_DATA_NODIV 786 drivers/clk/tegra/clk-tegra20.c TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1), TEGRA_INIT_DATA_NODIV 787 drivers/clk/tegra/clk-tegra20.c TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2), TEGRA_INIT_DATA_NODIV 1022 drivers/clk/tegra/clk-tegra30.c TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),