TARGET_OFFSET      75 drivers/net/ethernet/mscc/ocelot.h #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
TARGET_OFFSET      91 drivers/net/ethernet/mscc/ocelot.h 	ANA_ADVLEARN = ANA << TARGET_OFFSET,
TARGET_OFFSET     190 drivers/net/ethernet/mscc/ocelot.h 	QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
TARGET_OFFSET     202 drivers/net/ethernet/mscc/ocelot.h 	QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
TARGET_OFFSET     273 drivers/net/ethernet/mscc/ocelot.h 	REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
TARGET_OFFSET     286 drivers/net/ethernet/mscc/ocelot.h 	SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
TARGET_OFFSET     352 drivers/net/ethernet/mscc/ocelot.h 	S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
TARGET_OFFSET     359 drivers/net/ethernet/mscc/ocelot.h 	PTP_PIN_CFG = PTP << TARGET_OFFSET,
TARGET_OFFSET      15 drivers/net/ethernet/mscc/ocelot_io.c 	u16 target = reg >> TARGET_OFFSET;
TARGET_OFFSET      28 drivers/net/ethernet/mscc/ocelot_io.c 	u16 target = reg >> TARGET_OFFSET;
TARGET_OFFSET      40 drivers/net/ethernet/mscc/ocelot_io.c 	u16 target = reg >> TARGET_OFFSET;
TARGET_OFFSET      75 drivers/net/ethernet/mscc/ocelot_io.c 		target = regfields[i].reg >> TARGET_OFFSET;