T4 320 crypto/anubis.c static const u32 T4[256] = { T4 497 crypto/anubis.c K0 = T4[(kappa[N - 1] >> 24) ]; T4 498 crypto/anubis.c K1 = T4[(kappa[N - 1] >> 16) & 0xff]; T4 499 crypto/anubis.c K2 = T4[(kappa[N - 1] >> 8) & 0xff]; T4 500 crypto/anubis.c K3 = T4[(kappa[N - 1] ) & 0xff]; T4 502 crypto/anubis.c K0 = T4[(kappa[i] >> 24) ] ^ T4 507 crypto/anubis.c K1 = T4[(kappa[i] >> 16) & 0xff] ^ T4 512 crypto/anubis.c K2 = T4[(kappa[i] >> 8) & 0xff] ^ T4 517 crypto/anubis.c K3 = T4[(kappa[i] ) & 0xff] ^ T4 564 crypto/anubis.c T0[T4[(v >> 24) ] & 0xff] ^ T4 565 crypto/anubis.c T1[T4[(v >> 16) & 0xff] & 0xff] ^ T4 566 crypto/anubis.c T2[T4[(v >> 8) & 0xff] & 0xff] ^ T4 567 crypto/anubis.c T3[T4[(v ) & 0xff] & 0xff]; T4 394 crypto/khazad.c static const u64 T4[256] = { T4 775 crypto/khazad.c T4[(int)(K1 >> 24) & 0xff] ^ T4 791 crypto/khazad.c T4[(int)S[(int)(K1 >> 24) & 0xff] & 0xff] ^ T4 817 crypto/khazad.c T4[(int)(state >> 24) & 0xff] ^ T4 828 crypto/khazad.c (T4[(int)(state >> 24) & 0xff] & 0x00000000ff000000ULL) ^ T4 456 drivers/hid/hid-alps.c case T4: T4 690 drivers/hid/hid-alps.c case T4: T4 801 drivers/hid/hid-alps.c data->dev_type = T4; T4 4234 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c .fw_ver = __cpu_to_be32(FW_VERSION(T4)), T4 4235 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c .intfver_nic = FW_INTFVER(T4, NIC), T4 4236 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c .intfver_vnic = FW_INTFVER(T4, VNIC), T4 4237 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c .intfver_ri = FW_INTFVER(T4, RI), T4 4238 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c .intfver_iscsi = FW_INTFVER(T4, ISCSI), T4 4239 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c .intfver_fcoe = FW_INTFVER(T4, FCOE), T4 628 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12)); T4 2089 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c ASPEED_PINCTRL_PIN(T4), T4 864 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c SIG_EXPR_LIST_DECL_SINGLE(T4, VPIG7, VPI24, VPI24_DESC, T4_DESC); T4 865 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c SIG_EXPR_LIST_DECL_SINGLE(T4, PWM7, PWM7, T4_DESC, COND2); T4 866 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c PIN_DECL_2(T4, GPION7, VPIG7, PWM7); T4 867 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c FUNC_GROUP_DECL(PWM7, T4); T4 930 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5, T4 2094 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c ASPEED_PINCTRL_PIN(T4), T4 2537 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c { PIN_CONFIG_BIAS_PULL_DOWN, { V2, T4 }, SCU8C, 29 }, T4 2538 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c { PIN_CONFIG_BIAS_DISABLE, { V2, T4 }, SCU8C, 29 }, T4 609 lib/crypto/des.c #define DES_PC2(a, b, c, d) (T4(d) | T3(c) | T2(b) | T1(a)) T4 50 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[29] = REG(T4);