Ser4SSSR           27 arch/arm/mach-sa1100/ssp.c 	unsigned int status = Ser4SSSR;
Ser4SSSR           32 arch/arm/mach-sa1100/ssp.c 	Ser4SSSR = SSSR_ROR;
Ser4SSSR           55 arch/arm/mach-sa1100/ssp.c 	while (!(Ser4SSSR & SSSR_TNF)) {
Ser4SSSR           64 arch/arm/mach-sa1100/ssp.c 	while (!(Ser4SSSR & SSSR_BSY)) {
Ser4SSSR           92 arch/arm/mach-sa1100/ssp.c 	while (!(Ser4SSSR & SSSR_RNE)) {
Ser4SSSR          120 arch/arm/mach-sa1100/ssp.c 		while (Ser4SSSR & SSSR_RNE) {
Ser4SSSR          127 arch/arm/mach-sa1100/ssp.c 	} while (Ser4SSSR & SSSR_BSY);
Ser4SSSR          174 arch/arm/mach-sa1100/ssp.c 	Ser4SSSR = SSSR_ROR;
Ser4SSSR          202 arch/arm/mach-sa1100/ssp.c 	Ser4SSSR = SSSR_ROR;