S_MI0_PHY_REG_ADDR   90 drivers/net/ethernet/chelsio/cxgb/fpga_defs.h #define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)
S_MI0_PHY_REG_ADDR   91 drivers/net/ethernet/chelsio/cxgb/fpga_defs.h #define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)