S_MI0_CLK_DIV      56 drivers/net/ethernet/chelsio/cxgb/fpga_defs.h #define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)
S_MI0_CLK_DIV      57 drivers/net/ethernet/chelsio/cxgb/fpga_defs.h #define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)