SZ_64K 97 arch/arm/include/uapi/asm/kvm.h #define KVM_VGIC_V3_DIST_SIZE SZ_64K SZ_64K 98 arch/arm/include/uapi/asm/kvm.h #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) SZ_64K 99 arch/arm/include/uapi/asm/kvm.h #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) SZ_64K 437 arch/arm/kernel/bios32.c sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; SZ_64K 438 arch/arm/kernel/bios32.c sys->io_res.end = (busnr + 1) * SZ_64K - 1; SZ_64K 618 arch/arm/kernel/bios32.c .length = SZ_64K, SZ_64K 56 arch/arm/mach-cns3xxx/core.c .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ SZ_64K 71 arch/arm/mach-cns3xxx/core.c .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ SZ_64K 70 arch/arm/mach-davinci/board-da850-evm.c .size = SZ_64K, SZ_64K 82 arch/arm/mach-davinci/board-da850-evm.c .size = SZ_64K, SZ_64K 99 arch/arm/mach-davinci/board-da850-evm.c .offset = SZ_8M - SZ_64K, SZ_64K 100 arch/arm/mach-davinci/board-da850-evm.c .size = SZ_64K, SZ_64K 376 arch/arm/mach-davinci/board-dm355-evm.c .byte_len = SZ_64K / 8, SZ_64K 215 arch/arm/mach-davinci/board-dm355-leopard.c .byte_len = SZ_64K / 8, SZ_64K 776 arch/arm/mach-davinci/board-dm365-evm.c .byte_len = SZ_64K / 8, SZ_64K 61 arch/arm/mach-davinci/board-dm644x-evm.c .size = 5 * SZ_64K, SZ_64K 68 arch/arm/mach-davinci/board-dm644x-evm.c .size = SZ_64K, SZ_64K 344 arch/arm/mach-davinci/board-mityomapl138.c .size = SZ_64K, SZ_64K 356 arch/arm/mach-davinci/board-mityomapl138.c .size = SZ_64K, SZ_64K 362 arch/arm/mach-davinci/board-mityomapl138.c .size = SZ_64K, SZ_64K 368 arch/arm/mach-davinci/board-mityomapl138.c .size = SZ_256K + SZ_64K, SZ_64K 262 arch/arm/mach-davinci/dm355.c .end = 0x01c00000 + SZ_64K - 1, SZ_64K 494 arch/arm/mach-davinci/dm365.c .end = 0x01c00000 + SZ_64K - 1, SZ_64K 249 arch/arm/mach-davinci/dm644x.c .end = 0x01c00000 + SZ_64K - 1, SZ_64K 250 arch/arm/mach-davinci/dm646x.c .end = 0x01c00000 + SZ_64K - 1, SZ_64K 70 arch/arm/mach-davinci/usb-da8xx.c .end = DA8XX_USB0_BASE + SZ_64K - 1, SZ_64K 54 arch/arm/mach-dove/dove.h #define DOVE_PCIE0_IO_SIZE SZ_64K SZ_64K 58 arch/arm/mach-dove/dove.h #define DOVE_PCIE1_IO_SIZE SZ_64K SZ_64K 57 arch/arm/mach-dove/pcie.c pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); SZ_64K 59 arch/arm/mach-dove/pcie.c pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); SZ_64K 101 arch/arm/mach-imx/mach-mx31ads.c DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K), SZ_64K 197 arch/arm/mach-imx/mach-pcm037.c .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1, SZ_64K 104 arch/arm/mach-imx/mx31.h #define MX31_X_MEMC_SIZE SZ_64K SZ_64K 108 arch/arm/mach-imx/mx35.h #define MX35_X_MEMC_SIZE SZ_64K SZ_64K 130 arch/arm/mach-imx/mx3x.h #define MX3x_X_MEMC_SIZE SZ_64K SZ_64K 97 arch/arm/mach-mv78xx0/pcie.c i * SZ_64K, SZ_64K, 0); SZ_64K 118 arch/arm/mach-mv78xx0/pcie.c pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr)); SZ_64K 137 arch/arm/mach-mvebu/pmsu.c SRAM_PHYS_BASE, SZ_64K); SZ_64K 139 arch/arm/mach-mvebu/pmsu.c sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K); SZ_64K 88 arch/arm/mach-omap1/board-palmtt.c .size = 7 * SZ_1M + 4 * SZ_64K - 16 * SZ_8K, SZ_64K 45 arch/arm/mach-orion5x/orion5x.h #define ORION5X_PCIE_IO_SIZE SZ_64K SZ_64K 49 arch/arm/mach-orion5x/orion5x.h #define ORION5X_PCI_IO_SIZE SZ_64K SZ_64K 167 arch/arm/mach-orion5x/pci.c pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE); SZ_64K 485 arch/arm/mach-orion5x/pci.c pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE); SZ_64K 227 arch/arm/mach-pxa/csb726.c .end = PXA_CS3_PHYS + SZ_64K - 1, SZ_64K 191 arch/arm/mach-s3c64xx/mach-anw6410.c .length = SZ_64K, SZ_64K 184 arch/arm/mach-s3c64xx/mach-smdk6410.c [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, SZ_64K), SZ_64K 36 arch/arm/mach-sa1100/cerf.c [0] = DEFINE_RES_MEM(0x80030000, SZ_64K), SZ_64K 122 arch/arm/mach-sa1100/generic.c [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K), SZ_64K 140 arch/arm/mach-sa1100/generic.c [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K), SZ_64K 152 arch/arm/mach-sa1100/generic.c [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K), SZ_64K 164 arch/arm/mach-sa1100/generic.c [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K), SZ_64K 198 arch/arm/mach-sa1100/generic.c [0] = DEFINE_RES_MEM(0x80070000, SZ_64K), SZ_64K 216 arch/arm/mach-sa1100/generic.c [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K), SZ_64K 415 arch/arm/mach-sa1100/generic.c DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); SZ_64K 45 arch/arm/mach-sa1100/include/mach/nanoengine.h #define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K SZ_64K 173 arch/arm/mach-u300/core.c .length = SZ_64K, SZ_64K 477 arch/arm/mm/ioremap.c BUG_ON(offset + SZ_64K - 1 > IO_SPACE_LIMIT); SZ_64K 480 arch/arm/mm/ioremap.c PCI_IO_VIRT_BASE + offset + SZ_64K, SZ_64K 116 arch/arm64/crypto/ghash-ce-glue.c #define MAX_BLOCKS (SZ_64K / GHASH_BLOCK_SIZE) SZ_64K 121 arch/arm64/include/asm/efi.h #define EFI_ALLOC_ALIGN SZ_64K SZ_64K 142 arch/arm64/include/asm/memory.h #define SEGMENT_ALIGN SZ_64K SZ_64K 24 arch/arm64/include/asm/pgtable.h #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K) SZ_64K 98 arch/arm64/include/uapi/asm/kvm.h #define KVM_VGIC_V3_DIST_SIZE SZ_64K SZ_64K 99 arch/arm64/include/uapi/asm/kvm.h #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) SZ_64K 100 arch/arm64/include/uapi/asm/kvm.h #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) SZ_64K 974 arch/arm64/kernel/insn.c if (imm & ~(SZ_64K - 1)) { SZ_64K 93 arch/arm64/kernel/signal.c #define SIGFRAME_MAXSZ SZ_64K SZ_64K 49 arch/mips/boot/compressed/calc_vmlinuz_load_addr.c vmlinuz_load_addr += (SZ_64K - vmlinux_size % SZ_64K); SZ_64K 165 arch/mips/loongson32/common/platform.c .end = LS1X_GMAC0_BASE + SZ_64K - 1, SZ_64K 202 arch/mips/loongson32/common/platform.c .end = LS1X_GMAC1_BASE + SZ_64K - 1, SZ_64K 2693 arch/powerpc/platforms/powernv/pci-ioda.c mask = SZ_4K | SZ_64K; SZ_64K 837 drivers/acpi/arm64/iort.c region = iommu_alloc_resv_region(base + SZ_64K, SZ_64K, SZ_64K 1180 drivers/acpi/arm64/iort.c return SZ_64K; SZ_64K 3532 drivers/clk/tegra/clk-tegra210.c ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K); SZ_64K 29 drivers/cpufreq/tegra186-cpufreq.c .offset = SZ_64K * 7, SZ_64K 35 drivers/cpufreq/tegra186-cpufreq.c .offset = SZ_64K * 6, SZ_64K 1682 drivers/crypto/picoxcell_crypto.c MAX_DDT_LEN * sizeof(struct spacc_ddt), 8, SZ_64K); SZ_64K 175 drivers/dma/bcm2835-dma.c #define MAX_LITE_DMA_LEN (SZ_64K - 4) SZ_64K 99 drivers/dma/mmp_tdma.c #define TDMA_MAX_XFER_BYTES SZ_64K SZ_64K 974 drivers/dma/ti/edma.c ccnt = dma_length / acnt / (SZ_64K - 1); SZ_64K 975 drivers/dma/ti/edma.c bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); SZ_64K 983 drivers/dma/ti/edma.c bcnt = SZ_64K - 1; SZ_64K 998 drivers/dma/ti/edma.c if (ccnt > (SZ_64K - 1)) { SZ_64K 1175 drivers/dma/ti/edma.c if (len < SZ_64K) { SZ_64K 381 drivers/firmware/efi/libstub/arm-stub.c paddr = round_down(in->phys_addr, SZ_64K); SZ_64K 393 drivers/firmware/efi/libstub/arm-stub.c efi_virt_base = round_up(efi_virt_base, SZ_64K); SZ_64K 64 drivers/gpu/drm/arm/malidp_planes.c #define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES (SZ_4K | SZ_64K) SZ_64K 481 drivers/gpu/drm/arm/malidp_planes.c if (pgsize == SZ_64K || pgsize == SZ_2M) { SZ_64K 76 drivers/gpu/drm/armada/armada_drv.c if (resource_size(r) > SZ_64K) SZ_64K 380 drivers/gpu/drm/exynos/exynos_drm_rotator.c { IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_64K }, .v = { 32, SZ_64K }) }, SZ_64K 385 drivers/gpu/drm/exynos/exynos_drm_rotator.c { IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_64K }, .v = { 32, SZ_64K }) }, SZ_64K 731 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .size = SZ_64K, SZ_64K 736 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .size = SZ_64K + SZ_4K, SZ_64K 741 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .size = SZ_64K - SZ_4K, SZ_64K 761 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .size = SZ_2M + SZ_64K, SZ_64K 766 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .size = SZ_2M - SZ_64K, SZ_64K 772 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .size = SZ_64K, SZ_64K 778 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .offset = SZ_2M - SZ_64K, SZ_64K 1189 drivers/gpu/drm/i915/gem/selftests/huge_pages.c SZ_64K, SZ_64K 99 drivers/gpu/drm/i915/i915_gpu_error.c e->size = ALIGN(len + 1, SZ_64K); SZ_64K 916 drivers/gpu/drm/msm/adreno/adreno_gpu.c adreno_gpu_config.va_end = SZ_16M + 0xfff * SZ_64K; SZ_64K 20 drivers/gpu/drm/msm/msm_gpummu.c #define GPUMMU_VA_RANGE (0xfff * SZ_64K) SZ_64K 713 drivers/gpu/ipu-v3/ipu-ic.c priv->tpmem_base = devm_ioremap(dev, tpmem_base, SZ_64K); SZ_64K 126 drivers/i2c/busses/i2c-qup.c #define MX_TX_RX_LEN SZ_64K SZ_64K 1313 drivers/i2c/busses/i2c-tegra.c .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, SZ_64K 685 drivers/iommu/arm-smmu-v3.c if ((offset > SZ_64K) && SZ_64K 687 drivers/iommu/arm-smmu-v3.c offset -= SZ_64K; SZ_64K 3447 drivers/iommu/arm-smmu-v3.c smmu->pgsize_bitmap |= SZ_64K | SZ_512M; SZ_64K 3570 drivers/iommu/arm-smmu-v3.c return SZ_64K; SZ_64K 1825 drivers/iommu/arm-smmu.c smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M; SZ_64K 1832 drivers/iommu/arm-smmu.c smmu->pgsize_bitmap |= SZ_64K | SZ_512M; SZ_64K 799 drivers/iommu/io-pgtable-arm-v7s.c cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M; SZ_64K 891 drivers/iommu/io-pgtable-arm-v7s.c .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, SZ_64K 728 drivers/iommu/io-pgtable-arm.c case SZ_64K: SZ_64K 730 drivers/iommu/io-pgtable-arm.c page_sizes = (SZ_64K | SZ_512M); SZ_64K 751 drivers/iommu/io-pgtable-arm.c if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K))) SZ_64K 820 drivers/iommu/io-pgtable-arm.c case SZ_64K: SZ_64K 932 drivers/iommu/io-pgtable-arm.c case SZ_64K: SZ_64K 1250 drivers/iommu/io-pgtable-arm.c SZ_64K | SZ_512M, SZ_64K 35 drivers/iommu/msm_iommu.c #define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) SZ_64K 587 drivers/iommu/mtk_iommu.c .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, SZ_64K 50 drivers/iommu/omap-iommu.c #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) SZ_64K 214 drivers/iommu/omap-iommu.h ((bytes) >= SZ_64K) ? SZ_64K : \ SZ_64K 220 drivers/iommu/omap-iommu.h ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ SZ_64K 226 drivers/iommu/omap-iommu.h ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ SZ_64K 616 drivers/iommu/qcom_iommu.c .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, SZ_64K 56 drivers/irqchip/irq-gic-v3-its.c #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) SZ_64K 57 drivers/irqchip/irq-gic-v3-its.c #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) SZ_64K 311 drivers/irqchip/irq-gic-v3-its.c #define ITS_CMD_QUEUE_SZ SZ_64K SZ_64K 1787 drivers/irqchip/irq-gic-v3-its.c if (psz != SZ_64K) { SZ_64K 1815 drivers/irqchip/irq-gic-v3-its.c case SZ_64K: SZ_64K 1852 drivers/irqchip/irq-gic-v3-its.c case SZ_64K: SZ_64K 1952 drivers/irqchip/irq-gic-v3-its.c u32 psz = SZ_64K; SZ_64K 99 drivers/irqchip/irq-gic-v3.c #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) SZ_64K 794 drivers/irqchip/irq-gic-v3.c ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ SZ_64K 796 drivers/irqchip/irq-gic-v3.c ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ SZ_64K 1846 drivers/irqchip/irq-gic-v3.c u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; SZ_64K 2005 drivers/irqchip/irq-gic-v3.c #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) SZ_64K 150 drivers/irqchip/irq-sa11x0.c iobase = ioremap(io_start, SZ_64K); SZ_64K 280 drivers/mailbox/tegra-hsp.c offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; SZ_64K 587 drivers/mailbox/tegra-hsp.c mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K; SZ_64K 125 drivers/media/platform/rcar_drif.c #define RCAR_SDR_BUFFER_SIZE SZ_64K SZ_64K 42 drivers/media/platform/s5p-mfc/s5p_mfc_opr.c unsigned int align = (SZ_64K >> PAGE_SHIFT) - 1; SZ_64K 794 drivers/misc/pci_endpoint_test.c .alignment = SZ_64K, SZ_64K 49 drivers/mmc/core/sd.c 0, SZ_16K / 512, SZ_32K / 512, SZ_64K / 512, SZ_64K 3660 drivers/mmc/host/sdhci.c bounce_size = SZ_64K; SZ_64K 707 drivers/mmc/host/tmio_mmc_core.c if (host->mmc->max_blk_count >= SZ_64K) SZ_64K 25 drivers/mtd/parsers/bcm63xxpart.c #define BCM963XX_CFE_BLOCK_SIZE SZ_64K /* always at least 64KiB */ SZ_64K 748 drivers/mtd/spi-nor/intel-spi.c if (len >= SZ_64K && ispi->erase_64k) { SZ_64K 750 drivers/mtd/spi-nor/intel-spi.c erase_size = SZ_64K; SZ_64K 2924 drivers/net/ethernet/marvell/mvneta.c mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? SZ_64K 704 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP22_ADDR_SPACE_SZ SZ_64K SZ_64K 20 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define MBOX_SIZE SZ_64K SZ_64K 1232 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c nfp_cpp_area_cache_add(cpp, SZ_64K); SZ_64K 1233 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c nfp_cpp_area_cache_add(cpp, SZ_64K); SZ_64K 149 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_arm.h #define NFP_ARM_GCSR_SIZE SZ_64K SZ_64K 214 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_arm.h #define NFP_ARM_PCSR_SIZE SZ_64K SZ_64K 35 drivers/net/thunderbolt.c #define TBNET_MAX_MTU SZ_64K SZ_64K 43 drivers/ntb/hw/mscc/ntb_hw_switchtec.c #define LUT_SIZE SZ_64K SZ_64K 104 drivers/pci/controller/dwc/pci-keystone.c #define AM654_WIN_SIZE SZ_64K SZ_64K 977 drivers/pci/controller/dwc/pci-keystone.c .bar_fixed_size[3] = SZ_64K, SZ_64K 698 drivers/pci/controller/pci-mvebu.c return round_up(start, max_t(resource_size_t, SZ_64K, SZ_64K 993 drivers/pci/controller/pci-mvebu.c IO_SPACE_LIMIT - SZ_64K, SZ_64K 1026 drivers/pci/controller/pci-mvebu.c for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K) SZ_64K 394 drivers/pci/controller/pci-thunder-pem.c res_pem->end = res_pem->start + SZ_64K - 1; SZ_64K 1508 drivers/perf/arm-cci.c .cntr_size = SZ_64K, SZ_64K 1532 drivers/perf/arm-cci.c .cntr_size = SZ_64K, SZ_64K 127 drivers/spi/spi-pxa2xx.h #define MAX_DMA_LEN SZ_64K SZ_64K 116 drivers/spi/spi-qup.c #define SPI_MAX_XFER (SZ_64K - 64) SZ_64K 128 drivers/spi/spi-ti-qspi.c #define QSPI_DMA_BUFFER_SIZE SZ_64K SZ_64K 37 drivers/staging/media/meson/vdec/vdec.c return ALIGN(width * height, SZ_64K); SZ_64K 447 drivers/vfio/pci/vfio_pci_nvlink2.c data->base = memremap(data->mmio_atsd, SZ_64K, MEMREMAP_WT); SZ_64K 9 fs/btrfs/disk-io.h #define BTRFS_SUPER_INFO_OFFSET SZ_64K SZ_64K 2774 fs/btrfs/extent-tree.c *empty_cluster = SZ_64K; SZ_64K 995 fs/btrfs/inode.c inode_should_defrag(BTRFS_I(inode), start, end, num_bytes, SZ_64K); SZ_64K 1456 fs/btrfs/ioctl.c &newer_off, SZ_64K); SZ_64K 1551 fs/btrfs/ioctl.c &newer_off, SZ_64K); SZ_64K 4478 fs/btrfs/ioctl.c size = min_t(u32, loi->size, SZ_64K); SZ_64K 5267 fs/btrfs/send.c const u64 sectorsize = SZ_64K; SZ_64K 15 fs/btrfs/send.h #define BTRFS_SEND_BUF_SIZE SZ_64K SZ_64K 18 fs/btrfs/volumes.h #define BTRFS_STRIPE_LEN SZ_64K SZ_64K 726 include/linux/dma-mapping.h return SZ_64K; SZ_64K 74 lib/logic_pio.c if (mmio_end + SZ_64K - 1 > MMIO_UPPER_LIMIT) { SZ_64K 78 lib/logic_pio.c new_range->size = SZ_64K; SZ_64K 97 tools/arch/arm/include/uapi/asm/kvm.h #define KVM_VGIC_V3_DIST_SIZE SZ_64K SZ_64K 98 tools/arch/arm/include/uapi/asm/kvm.h #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) SZ_64K 99 tools/arch/arm/include/uapi/asm/kvm.h #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) SZ_64K 98 tools/arch/arm64/include/uapi/asm/kvm.h #define KVM_VGIC_V3_DIST_SIZE SZ_64K SZ_64K 99 tools/arch/arm64/include/uapi/asm/kvm.h #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) SZ_64K 100 tools/arch/arm64/include/uapi/asm/kvm.h #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) SZ_64K 899 virt/kvm/arm/vgic/vgic-its.c int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K; SZ_64K 937 virt/kvm/arm/vgic/vgic-its.c index = id / (SZ_64K / esz); SZ_64K 957 virt/kvm/arm/vgic/vgic-its.c index = id % (SZ_64K / esz); SZ_64K 2390 virt/kvm/arm/vgic/vgic-its.c int l2_start_id = id * (SZ_64K / abi->dte_esz); SZ_64K 2403 virt/kvm/arm/vgic/vgic-its.c ret = scan_its_table(its, gpa, SZ_64K, dte_esz, SZ_64K 2418 virt/kvm/arm/vgic/vgic-its.c int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K; SZ_64K 2506 virt/kvm/arm/vgic/vgic-its.c max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K; SZ_64K 2548 virt/kvm/arm/vgic/vgic-its.c max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K; SZ_64K 2706 virt/kvm/arm/vgic/vgic-its.c addr, SZ_64K); SZ_64K 78 virt/kvm/arm/vgic/vgic-kvm-device.c alignment = SZ_64K; SZ_64K 547 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0, SZ_64K 550 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ISENABLER0, SZ_64K 553 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICENABLER0, SZ_64K 556 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0, SZ_64K 560 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0, SZ_64K 564 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0, SZ_64K 568 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0, SZ_64K 572 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0, SZ_64K 575 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0, SZ_64K 578 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0, SZ_64K 581 virt/kvm/arm/vgic/vgic-mmio-v3.c REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR, SZ_64K 593 virt/kvm/arm/vgic/vgic-mmio-v3.c return SZ_64K; SZ_64K 644 virt/kvm/arm/vgic/vgic-mmio-v3.c 2 * SZ_64K, &rd_dev->dev); SZ_64K 750 virt/kvm/arm/vgic/vgic-mmio-v3.c ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K);