SZ_4K 33 arch/arm/crypto/nhpoly1305-neon-glue.c unsigned int n = min_t(unsigned int, srclen, SZ_4K); SZ_4K 231 arch/arm/mach-cns3xxx/cns3420vb.c .length = SZ_4K, SZ_4K 35 arch/arm/mach-cns3xxx/core.c .length = SZ_4K, SZ_4K 40 arch/arm/mach-cns3xxx/core.c .length = SZ_4K, SZ_4K 45 arch/arm/mach-cns3xxx/core.c .length = SZ_4K, SZ_4K 51 arch/arm/mach-cns3xxx/core.c .length = SZ_4K, SZ_4K 66 arch/arm/mach-cns3xxx/core.c .length = SZ_4K, SZ_4K 264 arch/arm/mach-cns3xxx/core.c void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); SZ_4K 78 arch/arm/mach-cns3xxx/devices.c .end = CNS3XXX_SDIO_BASE + SZ_4K - 1, SZ_4K 97 arch/arm/mach-davinci/board-dm355-evm.c .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, SZ_4K 91 arch/arm/mach-davinci/board-dm355-leopard.c .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, SZ_4K 159 arch/arm/mach-davinci/board-dm365-evm.c .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, SZ_4K 179 arch/arm/mach-davinci/board-dm365-evm.c .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, SZ_4K 176 arch/arm/mach-davinci/board-dm644x-evm.c .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, SZ_4K 184 arch/arm/mach-davinci/board-dm644x-evm.c .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, SZ_4K 106 arch/arm/mach-davinci/board-dm646x-evm.c .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, SZ_4K 126 arch/arm/mach-davinci/board-dm646x-evm.c .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, SZ_4K 105 arch/arm/mach-davinci/board-neuros-osd2.c .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, SZ_4K 67 arch/arm/mach-davinci/board-sffsdr.c .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, SZ_4K 34 arch/arm/mach-davinci/common.c base = ioremap(soc_info->jtag_id_reg, SZ_4K); SZ_4K 685 arch/arm/mach-davinci/da830.c .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), SZ_4K 709 arch/arm/mach-davinci/da830.c da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); SZ_4K 735 arch/arm/mach-davinci/da830.c pll = ioremap(DA8XX_PLL0_BASE, SZ_4K); SZ_4K 752 arch/arm/mach-davinci/da830.c .end = DA8XX_PSC0_BASE + SZ_4K - 1, SZ_4K 767 arch/arm/mach-davinci/da830.c .end = DA8XX_PSC1_BASE + SZ_4K - 1, SZ_4K 342 arch/arm/mach-davinci/da850.c .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), SZ_4K 626 arch/arm/mach-davinci/da850.c da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); SZ_4K 630 arch/arm/mach-davinci/da850.c da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); SZ_4K 657 arch/arm/mach-davinci/da850.c pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); SZ_4K 675 arch/arm/mach-davinci/da850.c .end = DA850_PLL1_BASE + SZ_4K - 1, SZ_4K 695 arch/arm/mach-davinci/da850.c .end = DA8XX_PSC0_BASE + SZ_4K - 1, SZ_4K 710 arch/arm/mach-davinci/da850.c .end = DA8XX_PSC1_BASE + SZ_4K - 1, SZ_4K 303 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_I2C0_BASE + SZ_4K - 1, SZ_4K 323 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_I2C1_BASE + SZ_4K - 1, SZ_4K 359 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_WDOG_BASE + SZ_4K - 1, SZ_4K 425 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, SZ_4K 671 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, SZ_4K 700 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_GPIO_BASE + SZ_4K - 1, SZ_4K 766 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, SZ_4K 793 arch/arm/mach-davinci/devices-da8xx.c .end = DA850_MMCSD1_BASE + SZ_4K - 1, SZ_4K 936 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_RTC_BASE + SZ_4K - 1, SZ_4K 1009 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_SPI0_BASE + SZ_4K - 1, SZ_4K 1022 arch/arm/mach-davinci/devices-da8xx.c .end = DA830_SPI1_BASE + SZ_4K - 1, SZ_4K 1077 arch/arm/mach-davinci/devices-da8xx.c da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; SZ_4K 126 arch/arm/mach-davinci/devices.c .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1, SZ_4K 156 arch/arm/mach-davinci/devices.c .end = DM355_MMCSD1_BASE + SZ_4K - 1, SZ_4K 216 arch/arm/mach-davinci/devices.c SZ_4K - 1; SZ_4K 228 arch/arm/mach-davinci/devices.c mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1; SZ_4K 240 arch/arm/mach-davinci/devices.c SZ_4K - 1; SZ_4K 549 arch/arm/mach-davinci/dm355.c .end = DAVINCI_GPIO_BASE + SZ_4K - 1, SZ_4K 628 arch/arm/mach-davinci/dm355.c .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), SZ_4K 743 arch/arm/mach-davinci/dm355.c psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); SZ_4K 803 arch/arm/mach-davinci/dm355.c .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, SZ_4K 267 arch/arm/mach-davinci/dm365.c .end = DAVINCI_GPIO_BASE + SZ_4K - 1, SZ_4K 375 arch/arm/mach-davinci/dm365.c .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1, SZ_4K 783 arch/arm/mach-davinci/dm365.c psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); SZ_4K 1060 arch/arm/mach-davinci/dm365.c .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, SZ_4K 84 arch/arm/mach-davinci/dm644x.c .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1, SZ_4K 493 arch/arm/mach-davinci/dm644x.c .end = DAVINCI_GPIO_BASE + SZ_4K - 1, SZ_4K 569 arch/arm/mach-davinci/dm644x.c .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), SZ_4K 679 arch/arm/mach-davinci/dm644x.c psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); SZ_4K 739 arch/arm/mach-davinci/dm644x.c .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, SZ_4K 102 arch/arm/mach-davinci/dm646x.c .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1, SZ_4K 443 arch/arm/mach-davinci/dm646x.c .end = DAVINCI_GPIO_BASE + SZ_4K - 1, SZ_4K 509 arch/arm/mach-davinci/dm646x.c .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), SZ_4K 663 arch/arm/mach-davinci/dm646x.c psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); SZ_4K 700 arch/arm/mach-davinci/dm646x.c .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, SZ_4K 54 arch/arm/mach-davinci/include/mach/da8xx.h #define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) SZ_4K 46 arch/arm/mach-davinci/mux.c pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K); SZ_4K 134 arch/arm/mach-davinci/pm.c pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K); SZ_4K 138 arch/arm/mach-davinci/pm.c pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); SZ_4K 144 arch/arm/mach-davinci/pm.c pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K); SZ_4K 80 arch/arm/mach-davinci/serial.c p->membase = ioremap(p->mapbase, SZ_4K); SZ_4K 202 arch/arm/mach-davinci/time.c base[i] = ioremap(dtip[i].base, SZ_4K); SZ_4K 105 arch/arm/mach-davinci/usb-da8xx.c .end = DA8XX_USB1_BASE + SZ_4K - 1, SZ_4K 104 arch/arm/mach-ep93xx/snappercl15.c .end = SNAPPERCL15_NAND_BASE + SZ_4K - 1, SZ_4K 224 arch/arm/mach-ep93xx/ts72xx.c void __iomem *pwr_sd = ioremap(BK3_EN_SDCARD_PHYS_BASE, SZ_4K); SZ_4K 51 arch/arm/mach-ep93xx/vision_ep9307.c .length = SZ_4K, SZ_4K 177 arch/arm/mach-ep93xx/vision_ep9307.c .size = SZ_4K, SZ_4K 181 arch/arm/mach-ep93xx/vision_ep9307.c .size = SZ_4K, SZ_4K 183 arch/arm/mach-exynos/platsmp.c scu_base = ioremap(scu_a9_get_base(), SZ_4K); SZ_4K 76 arch/arm/mach-footbridge/ebsa285.c xbus = ioremap(XBUS_CS2, SZ_4K); SZ_4K 20 arch/arm/mach-gemini/board-dt.c .length = SZ_4K, SZ_4K 38 arch/arm/mach-highbank/highbank.c scu_base_addr = ioremap(base, SZ_4K); SZ_4K 46 arch/arm/mach-hisi/platsmp.c scu_base = ioremap(base, SZ_4K); SZ_4K 155 arch/arm/mach-imx/3ds_debugboard.c brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K); SZ_4K 37 arch/arm/mach-imx/devices/platform-fec.c .end = data->iobase + SZ_4K - 1, SZ_4K 14 arch/arm/mach-imx/devices/platform-imx-dma.c .end = iobase + SZ_4K - 1, SZ_4K 21 arch/arm/mach-imx/devices/platform-imx-fb.c imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K); SZ_4K 26 arch/arm/mach-imx/devices/platform-imx-fb.c imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K); SZ_4K 23 arch/arm/mach-imx/devices/platform-imx-i2c.c imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K); SZ_4K 29 arch/arm/mach-imx/devices/platform-imx-i2c.c imx_imx_i2c_data_entry(MX27, "imx21-i2c", _id, _hwid, SZ_4K) SZ_4K 38 arch/arm/mach-imx/devices/platform-imx-i2c.c imx_imx_i2c_data_entry(MX31, "imx21-i2c", _id, _hwid, SZ_4K) SZ_4K 48 arch/arm/mach-imx/devices/platform-imx-i2c.c imx_imx_i2c_data_entry(MX35, "imx21-i2c", _id, _hwid, SZ_4K) SZ_4K 24 arch/arm/mach-imx/devices/platform-imx-ssi.c imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K) SZ_4K 33 arch/arm/mach-imx/devices/platform-imx-ssi.c imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K) SZ_4K 42 arch/arm/mach-imx/devices/platform-imx-ssi.c imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) SZ_4K 51 arch/arm/mach-imx/devices/platform-imx-ssi.c imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) SZ_4K 30 arch/arm/mach-imx/devices/platform-imx-uart.c imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K) SZ_4K 41 arch/arm/mach-imx/devices/platform-imx-uart.c imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K) SZ_4K 54 arch/arm/mach-imx/devices/platform-imx-uart.c imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) SZ_4K 22 arch/arm/mach-imx/devices/platform-imx2-wdt.c imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K); SZ_4K 27 arch/arm/mach-imx/devices/platform-imx2-wdt.c imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K); SZ_4K 13 arch/arm/mach-imx/devices/platform-mx2-camera.c .iosizecsi = SZ_4K, \ SZ_4K 26 arch/arm/mach-imx/devices/platform-mxc-mmc.c imx_mxc_mmc_data_entry(MX21, "imx21-mmc", _id, _hwid, SZ_4K) SZ_4K 35 arch/arm/mach-imx/devices/platform-mxc-mmc.c imx_mxc_mmc_data_entry(MX27, "imx21-mmc", _id, _hwid, SZ_4K) SZ_4K 31 arch/arm/mach-imx/devices/platform-mxc_nand.c imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K); SZ_4K 36 arch/arm/mach-imx/devices/platform-mxc_nand.c imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K); SZ_4K 41 arch/arm/mach-imx/devices/platform-mxc_nand.c imx_mxc_nand_data_entry_single(MX31, "imx27-nand", SZ_4K); SZ_4K 40 arch/arm/mach-imx/devices/platform-mxc_w1.c .end = data->iobase + SZ_4K - 1, SZ_4K 14 arch/arm/mach-imx/devices/platform-pata_imx.c imx_pata_imx_data_entry_single(MX27, SZ_4K); SZ_4K 24 arch/arm/mach-imx/devices/platform-spi_imx.c imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K) SZ_4K 33 arch/arm/mach-imx/devices/platform-spi_imx.c imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K) SZ_4K 43 arch/arm/mach-imx/devices/platform-spi_imx.c imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) SZ_4K 53 arch/arm/mach-imx/devices/platform-spi_imx.c imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) SZ_4K 24 arch/arm/mach-imx/mach-imx1.c avic_addr = ioremap(MX1_AVIC_ADDR, SZ_4K); SZ_4K 66 arch/arm/mach-imx/mm-imx21.c DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K), SZ_4K 66 arch/arm/mach-imx/mm-imx27.c DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K), SZ_4K 25 arch/arm/mach-imx/platsmp.c .length = SZ_4K, SZ_4K 333 arch/arm/mach-integrator/impd1.c SZ_4K, "LM registers")) SZ_4K 341 arch/arm/mach-integrator/impd1.c impd1->base = devm_ioremap(&dev->dev, dev->resource.start, SZ_4K); SZ_4K 349 arch/arm/mach-integrator/impd1.c SZ_4K, "VIC")) SZ_4K 354 arch/arm/mach-integrator/impd1.c SZ_4K); SZ_4K 423 arch/arm/mach-integrator/impd1.c d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K, SZ_4K 50 arch/arm/mach-integrator/integrator_ap.c .length = SZ_4K, SZ_4K 55 arch/arm/mach-integrator/integrator_ap.c .length = SZ_4K, SZ_4K 43 arch/arm/mach-integrator/integrator_cp.c .length = SZ_4K, SZ_4K 48 arch/arm/mach-integrator/integrator_cp.c .length = SZ_4K, SZ_4K 53 arch/arm/mach-integrator/integrator_cp.c .length = SZ_4K, SZ_4K 25 arch/arm/mach-ixp4xx/ixp4xx-of.c .length = SZ_4K, SZ_4K 33 arch/arm/mach-ixp4xx/ixp4xx-of.c .length = SZ_4K, SZ_4K 77 arch/arm/mach-nomadik/cpu-8815.c .length = SZ_4K, SZ_4K 89 arch/arm/mach-nomadik/cpu-8815.c void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K); SZ_4K 32 arch/arm/mach-nspire/nspire.c void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K); SZ_4K 43 arch/arm/mach-omap1/board-fsample.c #define FSAMPLE_CPLD_SIZE SZ_4K SZ_4K 204 arch/arm/mach-omap1/board-fsample.c .end = OMAP_CS3_PHYS + SZ_4K - 1, SZ_4K 377 arch/arm/mach-omap1/board-h2.c h2_nand_resource.end += SZ_4K - 1; SZ_4K 405 arch/arm/mach-omap1/board-h3.c nand_resource.end += SZ_4K - 1; SZ_4K 162 arch/arm/mach-omap1/board-perseus2.c .end = OMAP_CS3_PHYS + SZ_4K - 1, SZ_4K 24 arch/arm/mach-omap1/fpga.h #define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ SZ_4K 54 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_SIZE SZ_4K SZ_4K 89 arch/arm/mach-omap2/iomap.h #define DSP_IPI_2420_SIZE SZ_4K SZ_4K 93 arch/arm/mach-omap2/iomap.h #define DSP_MMU_2420_SIZE SZ_4K SZ_4K 255 arch/arm/mach-omap2/omap4-common.c l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); SZ_4K 817 arch/arm/mach-pxa/spitz.c .end = PXA_CS3_PHYS + SZ_4K - 1, SZ_4K 55 arch/arm/mach-rockchip/pm.c rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8); SZ_4K 56 arch/arm/mach-s3c24xx/include/mach/map.h #define S3C2416_SZ_HSUDC (SZ_4K) SZ_4K 80 arch/arm/mach-s3c24xx/mach-anubis.c .length = SZ_4K, SZ_4K 85 arch/arm/mach-s3c24xx/mach-anubis.c .length = SZ_4K, SZ_4K 107 arch/arm/mach-s3c64xx/common.c .length = SZ_4K, SZ_4K 112 arch/arm/mach-s3c64xx/common.c .length = SZ_4K, SZ_4K 117 arch/arm/mach-s3c64xx/common.c .length = SZ_4K, SZ_4K 137 arch/arm/mach-s3c64xx/common.c .length = SZ_4K, SZ_4K 142 arch/arm/mach-s3c64xx/common.c .length = SZ_4K, SZ_4K 147 arch/arm/mach-s3c64xx/common.c .length = SZ_4K, SZ_4K 83 arch/arm/mach-s3c64xx/include/mach/map.h #define S3C64XX_SZ_GPIO SZ_4K SZ_4K 26 arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c .length = SZ_4K, SZ_4K 57 arch/arm/mach-sa1100/collie.c [0] = DEFINE_RES_MEM(0x40800000, SZ_4K), SZ_4K 203 arch/arm/mach-sa1100/h3xxx.c DEFINE_RES_MEM(0x80010000, SZ_4K), SZ_4K 204 arch/arm/mach-sa1100/h3xxx.c DEFINE_RES_MEM(0x80020000, SZ_4K), SZ_4K 285 arch/arm/mach-sa1100/neponset.c d->base = ioremap(nep_res->start, SZ_4K); SZ_4K 79 arch/arm/mach-spear/spear13xx.c .length = SZ_4K, SZ_4K 23 arch/arm/mach-tegra/iomap.h #define TEGRA_ARM_INT_DIST_SIZE SZ_4K SZ_4K 41 arch/arm/mach-tegra/iomap.h #define TEGRA_CLK_RESET_SIZE SZ_4K SZ_4K 50 arch/arm/mach-tegra/iomap.h #define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K SZ_4K 53 arch/arm/mach-tegra/iomap.h #define TEGRA_APB_MISC_SIZE SZ_4K SZ_4K 19 arch/arm/mach-tegra/irammap.h #define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K) SZ_4K 98 arch/arm/mach-versatile/versatile_dt.c .length = SZ_4K * 9, SZ_4K 172 arch/arm/mach-versatile/versatile_dt.c versatile_ib2_ctrl = ioremap(VERSATILE_IB2_CTL_BASE, SZ_4K); SZ_4K 1515 arch/arm/mm/cache-l2x0.c .way_size_0 = SZ_4K, SZ_4K 1536 arch/arm/mm/cache-l2x0.c .way_size_0 = SZ_4K, SZ_4K 742 arch/arm/plat-orion/common.c fill_resources_irq(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, SZ_4K 767 arch/arm/plat-orion/common.c mapbase, SZ_4K - 1, irq); SZ_4K 791 arch/arm/plat-orion/common.c mapbase, SZ_4K - 1, irq); SZ_4K 187 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K), SZ_4K 217 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K), SZ_4K 249 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K), SZ_4K 279 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K), SZ_4K 310 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K), SZ_4K 345 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K), SZ_4K 374 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K), SZ_4K 403 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K), SZ_4K 432 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K), SZ_4K 461 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K), SZ_4K 490 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K), SZ_4K 519 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K), SZ_4K 785 arch/arm/plat-samsung/devs.c DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K), SZ_4K 33 arch/arm64/crypto/nhpoly1305-neon-glue.c unsigned int n = min_t(unsigned int, srclen, SZ_4K); SZ_4K 124 arch/arm64/include/asm/memory.h #define OVERFLOW_STACK_SIZE SZ_4K SZ_4K 95 arch/arm64/kernel/alternative.c target = align_down(altinsnptr, SZ_4K) + orig_offset; SZ_4K 96 arch/arm64/kernel/alternative.c new_offset = target - align_down(insnptr, SZ_4K); SZ_4K 877 arch/arm64/kernel/insn.c if (imm & ~(SZ_4K - 1)) { SZ_4K 879 arch/arm64/kernel/insn.c if (imm & (SZ_4K - 1)) SZ_4K 1285 arch/arm64/kernel/insn.c offset = (addr - ALIGN_DOWN(pc, SZ_4K)) >> 12; SZ_4K 17 arch/arm64/kernel/module-plts.c add = aarch64_insn_gen_add_sub_imm(reg, reg, dst % SZ_4K, SZ_4K 52 arch/arm64/kernel/module-plts.c p = ALIGN_DOWN((u64)a, SZ_4K); SZ_4K 53 arch/arm64/kernel/module-plts.c q = ALIGN_DOWN((u64)b, SZ_4K); SZ_4K 235 arch/arm64/kernel/module-plts.c if (min_align > SZ_4K) SZ_4K 250 arch/arm64/kernel/module-plts.c ret += DIV_ROUND_UP(ret, (SZ_4K / sizeof(struct plt_entry))); SZ_4K 623 arch/powerpc/kvm/book3s_64_vio.c if (tce_list & (SZ_4K - 1)) SZ_4K 504 arch/powerpc/kvm/book3s_64_vio_hv.c if (tce_list & (SZ_4K - 1)) SZ_4K 845 arch/powerpc/kvm/book3s_hv.c u64 pg_sz = SZ_4K; /* 4K page size */ SZ_4K 846 arch/powerpc/kvm/book3s_hv.c u64 pg_mask = SZ_4K - 1; SZ_4K 958 arch/powerpc/kvm/book3s_hv_rm_mmu.c for (i = 0; i < SZ_4K; i += L1_CACHE_BYTES, pa += L1_CACHE_BYTES) SZ_4K 994 arch/powerpc/kvm/book3s_hv_rm_mmu.c memcpy((void *)dest_pa, (void *)src_pa, SZ_4K); SZ_4K 1007 arch/powerpc/kvm/book3s_hv_rm_mmu.c u64 pg_mask = SZ_4K - 1; /* 4K page size */ SZ_4K 25 arch/powerpc/mm/book3s64/iommu_api.c #define MM_IOMMU_TABLE_GROUP_PAGE_MASK ~(SZ_4K - 1) SZ_4K 2693 arch/powerpc/platforms/powernv/pci-ioda.c mask = SZ_4K | SZ_64K; SZ_4K 23 arch/sh/boards/mach-microdev/setup.c .end = 0x300 + SZ_4K - 1, SZ_4K 44 arch/sh/boards/mach-sdk7786/sram.c phys = (area << 26) + SZ_64M - SZ_4K; SZ_4K 32 arch/x86/crypto/nhpoly1305-avx2-glue.c unsigned int n = min_t(unsigned int, srclen, SZ_4K); SZ_4K 32 arch/x86/crypto/nhpoly1305-sse2-glue.c unsigned int n = min_t(unsigned int, srclen, SZ_4K); SZ_4K 215 drivers/acpi/arm64/gtdt.c timer_mem->size = SZ_4K; SZ_4K 265 drivers/acpi/arm64/gtdt.c frame->size = SZ_4K; SZ_4K 339 drivers/acpi/arm64/gtdt.c DEFINE_RES_MEM(wd->control_frame_address, SZ_4K), SZ_4K 340 drivers/acpi/arm64/gtdt.c DEFINE_RES_MEM(wd->refresh_frame_address, SZ_4K), SZ_4K 1369 drivers/acpi/arm64/iort.c res[0].end = pmcg->page0_base_address + SZ_4K - 1; SZ_4K 1372 drivers/acpi/arm64/iort.c res[1].end = pmcg->page1_base_address + SZ_4K - 1; SZ_4K 326 drivers/auxdisplay/arm-charlcd.c release_mem_region(lcd->phybase, SZ_4K); SZ_4K 186 drivers/clk/imx/clk-imx27.c ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K); SZ_4K 139 drivers/clk/imx/clk-imx31.c base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K); SZ_4K 100 drivers/clk/imx/clk-imx35.c base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K); SZ_4K 85 drivers/clk/mmp/clk-mmp2.c mpmu_base = ioremap(mpmu_phys, SZ_4K); SZ_4K 91 drivers/clk/mmp/clk-mmp2.c apmu_base = ioremap(apmu_phys, SZ_4K); SZ_4K 97 drivers/clk/mmp/clk-mmp2.c apbc_base = ioremap(apbc_phys, SZ_4K); SZ_4K 77 drivers/clk/mmp/clk-pxa168.c mpmu_base = ioremap(mpmu_phys, SZ_4K); SZ_4K 83 drivers/clk/mmp/clk-pxa168.c apmu_base = ioremap(apmu_phys, SZ_4K); SZ_4K 89 drivers/clk/mmp/clk-pxa168.c apbc_base = ioremap(apbc_phys, SZ_4K); SZ_4K 76 drivers/clk/mmp/clk-pxa910.c mpmu_base = ioremap(mpmu_phys, SZ_4K); SZ_4K 82 drivers/clk/mmp/clk-pxa910.c apmu_base = ioremap(apmu_phys, SZ_4K); SZ_4K 88 drivers/clk/mmp/clk-pxa910.c apbcp_base = ioremap(apbcp_phys, SZ_4K); SZ_4K 94 drivers/clk/mmp/clk-pxa910.c apbc_base = ioremap(apbc_phys, SZ_4K); SZ_4K 113 drivers/clk/ux500/clk-prcc.c clk->base = ioremap(phy_base, SZ_4K); SZ_4K 439 drivers/clocksource/timer-imx-gpt.c imxtm->base = ioremap(pbase, SZ_4K); SZ_4K 1025 drivers/firmware/efi/efi.c rc = efi_mem_reserve_iomem(__pa(rsv), SZ_4K); SZ_4K 1037 drivers/firmware/efi/efi.c rsv->size = EFI_MEMRESERVE_COUNT(SZ_4K); SZ_4K 39 drivers/firmware/meson/meson_sm.c .shmem_size = SZ_4K, SZ_4K 471 drivers/fpga/altera-cvp.c if (altera_cvp_chkcfg && !(done % SZ_4K)) { SZ_4K 184 drivers/fpga/altera-ps-spi.c size_t stride = min_t(size_t, fw_data_end - fw_data, SZ_4K); SZ_4K 80 drivers/fpga/xilinx-spi.c stride = min_t(size_t, remaining, SZ_4K); SZ_4K 577 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = SZ_4K; SZ_4K 913 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = SZ_4K; SZ_4K 64 drivers/gpu/drm/arm/malidp_planes.c #define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES (SZ_4K | SZ_64K) SZ_4K 17 drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c #define SUBALLOC_GRANULE SZ_4K SZ_4K 52 drivers/gpu/drm/etnaviv/etnaviv_iommu.c unsigned int index = (iova - GPU_MEM_START) / SZ_4K; SZ_4K 54 drivers/gpu/drm/etnaviv/etnaviv_iommu.c if (size != SZ_4K) SZ_4K 66 drivers/gpu/drm/etnaviv/etnaviv_iommu.c unsigned int index = (iova - GPU_MEM_START) / SZ_4K; SZ_4K 68 drivers/gpu/drm/etnaviv/etnaviv_iommu.c if (size != SZ_4K) SZ_4K 73 drivers/gpu/drm/etnaviv/etnaviv_iommu.c return SZ_4K; SZ_4K 161 drivers/gpu/drm/etnaviv/etnaviv_iommu.c drm_mm_init(&context->mm, GPU_MEM_START, PT_ENTRIES * SZ_4K); SZ_4K 56 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c dma_free_wc(context->global->dev, SZ_4K, SZ_4K 61 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c dma_free_wc(context->global->dev, SZ_4K, v2_context->mtlb_cpu, SZ_4K 76 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c dma_alloc_wc(v2_context->base.global->dev, SZ_4K, SZ_4K 84 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c SZ_4K / sizeof(u32)); SZ_4K 100 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c if (size != SZ_4K) SZ_4K 127 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c if (size != SZ_4K) SZ_4K 135 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c return SZ_4K; SZ_4K 141 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c size_t dump_size = SZ_4K; SZ_4K 146 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c dump_size += SZ_4K; SZ_4K 156 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c memcpy(buf, v2_context->mtlb_cpu, SZ_4K); SZ_4K 157 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c buf += SZ_4K; SZ_4K 160 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c memcpy(buf, v2_context->stlb_cpu[i], SZ_4K); SZ_4K 161 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c buf += SZ_4K; SZ_4K 282 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c v2_context->mtlb_cpu = dma_alloc_wc(global->dev, SZ_4K, SZ_4K 297 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c drm_mm_init(&context->mm, SZ_4K, (u64)SZ_1G * 4 - SZ_4K); SZ_4K 20 drivers/gpu/drm/etnaviv/etnaviv_mmu.c size_t pgsize = SZ_4K; SZ_4K 44 drivers/gpu/drm/etnaviv/etnaviv_mmu.c size_t pgsize = SZ_4K; SZ_4K 460 drivers/gpu/drm/etnaviv/etnaviv_mmu.c global->bad_page_cpu = dma_alloc_wc(dev, SZ_4K, &global->bad_page_dma, SZ_4K 465 drivers/gpu/drm/etnaviv/etnaviv_mmu.c memset32(global->bad_page_cpu, 0xdead55aa, SZ_4K / sizeof(u32)); SZ_4K 489 drivers/gpu/drm/etnaviv/etnaviv_mmu.c dma_free_wc(dev, SZ_4K, global->bad_page_cpu, global->bad_page_dma); SZ_4K 509 drivers/gpu/drm/etnaviv/etnaviv_mmu.c dma_free_wc(global->dev, SZ_4K, SZ_4K 37 drivers/gpu/drm/etnaviv/etnaviv_mmu.h #define ETNAVIV_PTA_SIZE SZ_4K SZ_4K 736 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .size = SZ_64K + SZ_4K, SZ_4K 741 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .size = SZ_64K - SZ_4K, SZ_4K 751 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .size = SZ_2M - SZ_4K, SZ_4K 756 drivers/gpu/drm/i915/gem/selftests/huge_pages.c .size = SZ_2M + SZ_4K, SZ_4K 740 drivers/gpu/drm/i915/gt/intel_engine_cs.c ce->ring = __intel_context_ring_size(SZ_4K); SZ_4K 161 drivers/gpu/drm/i915/gt/uc/intel_guc.c #define UNIT SZ_4K SZ_4K 1268 drivers/gpu/drm/i915/gvt/scheduler.c const unsigned int ring_size = 512 * SZ_4K; SZ_4K 870 drivers/gpu/drm/i915/i915_gem_gtt.c #define GEN8_PAGE_SIZE (SZ_4K) /* page and page-directory sizes are the same */ SZ_4K 60 drivers/gpu/drm/i915/intel_wopcm.c #define CNL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K) SZ_4K 324 drivers/gpu/drm/mediatek/mtk_disp_rdma.c .fifo_size = SZ_4K, SZ_4K 340 drivers/gpu/drm/msm/adreno/a6xx_hfi.c header->size = SZ_4K >> 2; SZ_4K 376 drivers/gpu/drm/msm/adreno/a6xx_hfi.c offset = SZ_4K; SZ_4K 381 drivers/gpu/drm/msm/adreno/a6xx_hfi.c offset += SZ_4K; SZ_4K 1859 drivers/gpu/drm/msm/dsi/dsi_host.c msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); SZ_4K 1929 drivers/gpu/drm/msm/dsi/dsi_host.c ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); SZ_4K 21 drivers/gpu/drm/msm/msm_gpummu.c #define GPUMMU_PAGE_SIZE SZ_4K SZ_4K 42 drivers/gpu/drm/omapdrm/dss/dispc.c #define DISPC_SZ_REGS SZ_4K SZ_4K 227 drivers/gpu/drm/panfrost/panfrost_mmu.c return SZ_4K; SZ_4K 371 drivers/gpu/drm/panfrost/panfrost_mmu.c .pgsize_bitmap = SZ_4K | SZ_2M, SZ_4K 1307 drivers/i2c/busses/i2c-tegra.c .max_read_len = SZ_4K, SZ_4K 1308 drivers/i2c/busses/i2c-tegra.c .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, SZ_4K 422 drivers/infiniband/core/rw.c prot_sg_cnt, NULL, SZ_4K); SZ_4K 1789 drivers/infiniband/hw/i40iw/i40iw_verbs.c iwmr->page_size = ib_umem_find_best_pgsz(region, SZ_4K | SZ_2M, SZ_4K 406 drivers/infiniband/ulp/iser/iser_memory.c sig_mem->sg, sig_mem->dma_nents, NULL, SZ_4K); SZ_4K 3451 drivers/iommu/arm-smmu-v3.c smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; SZ_4K 1825 drivers/iommu/arm-smmu.c smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M; SZ_4K 1828 drivers/iommu/arm-smmu.c smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; SZ_4K 799 drivers/iommu/io-pgtable-arm-v7s.c cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M; SZ_4K 891 drivers/iommu/io-pgtable-arm-v7s.c .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, SZ_4K 722 drivers/iommu/io-pgtable-arm.c case SZ_4K: SZ_4K 723 drivers/iommu/io-pgtable-arm.c page_sizes = (SZ_4K | SZ_2M | SZ_1G); SZ_4K 751 drivers/iommu/io-pgtable-arm.c if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K))) SZ_4K 814 drivers/iommu/io-pgtable-arm.c case SZ_4K: SZ_4K 925 drivers/iommu/io-pgtable-arm.c case SZ_4K: SZ_4K 992 drivers/iommu/io-pgtable-arm.c cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); SZ_4K 1010 drivers/iommu/io-pgtable-arm.c cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); SZ_4K 1030 drivers/iommu/io-pgtable-arm.c cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); SZ_4K 1248 drivers/iommu/io-pgtable-arm.c SZ_4K | SZ_2M | SZ_1G, SZ_4K 482 drivers/iommu/ipmmu-vmsa.c domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; SZ_4K 974 drivers/iommu/ipmmu-vmsa.c .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K, SZ_4K 35 drivers/iommu/msm_iommu.c #define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) SZ_4K 587 drivers/iommu/mtk_iommu.c .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, SZ_4K 50 drivers/iommu/omap-iommu.c #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) SZ_4K 215 drivers/iommu/omap-iommu.h ((bytes) >= SZ_4K) ? SZ_4K : 0) SZ_4K 221 drivers/iommu/omap-iommu.h ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) SZ_4K 227 drivers/iommu/omap-iommu.h ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) SZ_4K 616 drivers/iommu/qcom_iommu.c .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, SZ_4K 900 drivers/iommu/tegra-smmu.c .pgsize_bitmap = SZ_4K, SZ_4K 510 drivers/irqchip/irq-gic-v2m.c res.end = m->base_address + SZ_4K - 1; SZ_4K 1809 drivers/irqchip/irq-gic-v3-its.c case SZ_4K: SZ_4K 1850 drivers/irqchip/irq-gic-v3-its.c psz = SZ_4K; SZ_4K 3658 drivers/irqchip/irq-gic-v3-its.c (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | SZ_4K 2006 drivers/irqchip/irq-gic-v3.c #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) SZ_4K 1300 drivers/irqchip/irq-gic.c if (!gic_check_gicv2(alt + SZ_4K)) { SZ_4K 1558 drivers/irqchip/irq-gic.c #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) SZ_4K 1560 drivers/irqchip/irq-gic.c #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) SZ_4K 267 drivers/irqchip/irq-omap-intc.c omap_irq_base = ioremap(base, SZ_4K); SZ_4K 44 drivers/media/i2c/s5c73m3/s5c73m3-core.c #define S5C73M3_EMBEDDED_DATA_MAXLEN SZ_4K SZ_4K 111 drivers/media/pci/tw686x/tw686x-regs.h #define AUDIO_DMA_SIZE_MAX SZ_4K SZ_4K 112 drivers/media/platform/exynos4-is/mipi-csis.c #define S5PCSIS_PKTDATA_SIZE SZ_4K SZ_4K 678 drivers/media/platform/qcom/venus/helpers.c uv_plane = uv_stride * uv_sclines + SZ_4K; SZ_4K 681 drivers/media/platform/qcom/venus/helpers.c return ALIGN(size, SZ_4K); SZ_4K 694 drivers/media/platform/qcom/venus/helpers.c y_meta_plane = ALIGN(y_meta_plane, SZ_4K); SZ_4K 697 drivers/media/platform/qcom/venus/helpers.c y_plane = ALIGN(y_stride * ALIGN(height, 32), SZ_4K); SZ_4K 701 drivers/media/platform/qcom/venus/helpers.c uv_meta_plane = ALIGN(uv_meta_plane, SZ_4K); SZ_4K 704 drivers/media/platform/qcom/venus/helpers.c uv_plane = ALIGN(uv_stride * ALIGN(height / 2, 32), SZ_4K); SZ_4K 707 drivers/media/platform/qcom/venus/helpers.c max(extradata, y_stride * 48), SZ_4K); SZ_4K 753 drivers/media/platform/qcom/venus/helpers.c return ALIGN(sz, SZ_4K); SZ_4K 86 drivers/media/platform/qcom/venus/hfi_venus.c #define QDSS_SIZE SZ_4K SZ_4K 87 drivers/media/platform/qcom/venus/hfi_venus.c #define SFR_SIZE SZ_4K SZ_4K 91 drivers/media/platform/qcom/venus/hfi_venus.c #define ALIGNED_QDSS_SIZE ALIGN(QDSS_SIZE, SZ_4K) SZ_4K 92 drivers/media/platform/qcom/venus/hfi_venus.c #define ALIGNED_SFR_SIZE ALIGN(SFR_SIZE, SZ_4K) SZ_4K 93 drivers/media/platform/qcom/venus/hfi_venus.c #define ALIGNED_QUEUE_SIZE ALIGN(QUEUE_SIZE, SZ_4K) SZ_4K 331 drivers/media/platform/qcom/venus/hfi_venus.c desc->size = ALIGN(size, SZ_4K); SZ_4K 332 drivers/media/platform/qcom/venus/venc.c pfmt[0].sizeimage = max(ALIGN(pfmt[0].sizeimage, SZ_4K), sizeimage); SZ_4K 883 drivers/mtd/nand/onenand/samsung.c onenand->page_buf = devm_kzalloc(&pdev->dev, SZ_4K, SZ_4K 2153 drivers/mtd/nand/raw/marvell_nand.c if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) SZ_4K 35 drivers/mtd/nand/raw/nand_ids.c SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) }, SZ_4K 38 drivers/mtd/nand/raw/nand_ids.c SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) }, SZ_4K 41 drivers/mtd/nand/raw/nand_ids.c SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) }, SZ_4K 44 drivers/mtd/nand/raw/nand_ids.c SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, SZ_4K 636 drivers/mtd/spi-nor/intel-spi.c round_up(from + 1, SZ_4K)) - from; SZ_4K 693 drivers/mtd/spi-nor/intel-spi.c round_up(to + 1, SZ_4K)) - to; SZ_4K 753 drivers/mtd/spi-nor/intel-spi.c erase_size = SZ_4K; SZ_4K 2682 drivers/net/ethernet/amazon/ena/ena_com.c dma_alloc_coherent(ena_dev->dmadev, SZ_4K, SZ_4K 2718 drivers/net/ethernet/amazon/ena/ena_com.c dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info, SZ_4K 1827 drivers/net/ethernet/atheros/ag71xx.c .desc_pktlen_mask = SZ_4K - 1, SZ_4K 1835 drivers/net/ethernet/atheros/ag71xx.c .desc_pktlen_mask = SZ_4K - 1, SZ_4K 1843 drivers/net/ethernet/atheros/ag71xx.c .desc_pktlen_mask = SZ_4K - 1, SZ_4K 1851 drivers/net/ethernet/atheros/ag71xx.c .desc_pktlen_mask = SZ_4K - 1, SZ_4K 65 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c #define CMDQ_DEPTH SZ_4K SZ_4K 67 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c #define CMDQ_WQ_PAGE_SIZE SZ_4K SZ_4K 136 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h #define HINIC_EQ_PAGE_SIZE SZ_4K SZ_4K 21 drivers/net/ethernet/huawei/hinic/hinic_hw_io.h #define HINIC_DB_PAGE_SIZE SZ_4K SZ_4K 41 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h #define HINIC_SQ_PAGE_SIZE SZ_4K SZ_4K 42 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h #define HINIC_RQ_PAGE_SIZE SZ_4K SZ_4K 44 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h #define HINIC_SQ_DEPTH SZ_4K SZ_4K 45 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h #define HINIC_RQ_DEPTH SZ_4K SZ_4K 683 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c FIELD_GET(NSP_DFLT_BUFFER_SIZE_4KB, reg) * SZ_4K; SZ_4K 36 drivers/net/thunderbolt.c #define TBNET_FRAME_SIZE SZ_4K SZ_4K 62 drivers/net/wireless/ti/wlcore/spi.c #define SPI_AGGR_BUFFER_SIZE (13 * SZ_4K) SZ_4K 108 drivers/ntb/hw/amd/ntb_hw_amd.c *addr_align = SZ_4K; SZ_4K 210 drivers/ntb/hw/mscc/ntb_hw_switchtec.c *addr_align = lut ? size : SZ_4K; SZ_4K 213 drivers/ntb/hw/mscc/ntb_hw_switchtec.c *size_align = lut ? size : SZ_4K; SZ_4K 453 drivers/nvdimm/btt.c size_t chunk_size = SZ_4K, offset = 0; SZ_4K 291 drivers/nvdimm/btt_devs.c nd_btt->initial_offset = SZ_4K; SZ_4K 294 drivers/nvdimm/btt_devs.c if (nvdimm_read_bytes(ndns, SZ_4K, btt_sb, sizeof(*btt_sb), 0)) SZ_4K 239 drivers/nvdimm/claim.c BUILD_BUG_ON(sizeof(struct btt_sb) != SZ_4K); SZ_4K 240 drivers/nvdimm/claim.c BUILD_BUG_ON(sizeof(struct nd_pfn_sb) != SZ_4K); SZ_4K 241 drivers/nvdimm/claim.c BUILD_BUG_ON(sizeof(struct nd_gen_sb) != SZ_4K); SZ_4K 262 drivers/nvdimm/nd.h char reserved[SZ_4K - 8]; SZ_4K 382 drivers/nvdimm/pfn_devs.c meta_start = (SZ_4K + sizeof(*pfn_sb)) >> 9; SZ_4K 461 drivers/nvdimm/pfn_devs.c if (nvdimm_read_bytes(ndns, SZ_4K, pfn_sb, sizeof(*pfn_sb), 0)) SZ_4K 799 drivers/nvdimm/pfn_devs.c return nvdimm_write_bytes(ndns, SZ_4K, pfn_sb, sizeof(*pfn_sb), 0); SZ_4K 831 drivers/nvme/host/rdma.c ctrl->ctrl.max_hw_sectors = ctrl->max_fr_pages << (ilog2(SZ_4K) - 9); SZ_4K 1233 drivers/nvme/host/rdma.c nr = ib_map_mr_sg(req->mr, req->sg_table.sgl, count, NULL, SZ_4K); SZ_4K 482 drivers/pci/controller/dwc/pci-keystone.c dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); SZ_4K 486 drivers/pci/controller/pci-tegra.c base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8); SZ_4K 490 drivers/pci/controller/pci-tegra.c addr = pcie->cfg + (offset & (SZ_4K - 1)); SZ_4K 1542 drivers/pci/controller/pci-tegra.c pcie->cs.end = pcie->cs.start + SZ_4K - 1; SZ_4K 32 drivers/pci/controller/pcie-iproc-msi.c #define EQ_MEM_REGION_SIZE SZ_4K SZ_4K 35 drivers/pci/controller/pcie-iproc-msi.c #define MSI_MEM_REGION_SIZE SZ_4K SZ_4K 166 drivers/pcmcia/omap_cf.c io->start = cf->phys_cf + SZ_4K; SZ_4K 254 drivers/pcmcia/omap_cf.c ioremap(cf->phys_cf + SZ_4K, SZ_2K); SZ_4K 1466 drivers/perf/arm-cci.c .cntr_size = SZ_4K, SZ_4K 1486 drivers/perf/arm-cci.c .cntr_size = SZ_4K, SZ_4K 376 drivers/remoteproc/qcom_q6v5_mss.c return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K), SZ_4K 981 drivers/remoteproc/qcom_q6v5_mss.c max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); SZ_4K 825 drivers/rpmsg/qcom_smd.c bb_size = min(channel->fifo_size, SZ_4K); SZ_4K 76 drivers/sh/intc/userimask.c uimask = ioremap_nocache(addr, SZ_4K); SZ_4K 561 drivers/soc/imx/gpcv2.c .max_register = SZ_4K, SZ_4K 42 drivers/soc/qcom/llcc-slice.c #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) SZ_4K 43 drivers/soc/qcom/llcc-slice.c #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) SZ_4K 62 drivers/soc/qcom/mdt_loader.c max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); SZ_4K 194 drivers/soc/qcom/mdt_loader.c max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); SZ_4K 690 drivers/soc/qcom/smem.c ptable = smem->regions[0].virt_base + smem->regions[0].size - SZ_4K; SZ_4K 135 drivers/soc/ti/pm33xx.c gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K); SZ_4K 57 drivers/spi/spi-sprd-adi.c #define ADI_SLAVE_ADDR_SIZE SZ_4K SZ_4K 172 drivers/staging/media/imx/imx7-mipi-csis.c #define MIPI_CSIS_PKTDATA_SIZE SZ_4K SZ_4K 30 drivers/staging/media/meson/vdec/esparser.h #define ESPARSER_MIN_PACKET_SIZE SZ_4K SZ_4K 344 drivers/staging/media/meson/vdec/vdec_helpers.c if (delta > (-1 * (s32)SZ_4K) && delta < SZ_4K) { SZ_4K 130 drivers/thunderbolt/switch.c if (!IS_ALIGNED(hdr_size, SZ_4K)) SZ_4K 2099 drivers/tty/serial/amba-pl011.c release_mem_region(port->mapbase, SZ_4K); SZ_4K 2107 drivers/tty/serial/amba-pl011.c return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") SZ_4K 253 drivers/tty/serial/earlycon.c port->membase = earlycon_map(port->mapbase, SZ_4K); SZ_4K 553 drivers/tty/serial/lpc32xx_hs.c release_mem_region(port->mapbase, SZ_4K); SZ_4K 564 drivers/tty/serial/lpc32xx_hs.c if (!request_mem_region(port->mapbase, SZ_4K, MODNAME)) SZ_4K 567 drivers/tty/serial/lpc32xx_hs.c port->membase = ioremap(port->mapbase, SZ_4K); SZ_4K 569 drivers/tty/serial/lpc32xx_hs.c release_mem_region(port->mapbase, SZ_4K); SZ_4K 2092 drivers/usb/gadget/udc/renesas_usb3.c else if (ram_size <= SZ_4K) SZ_4K 2675 drivers/usb/gadget/udc/renesas_usb3.c .ramsize_per_pipe = SZ_4K, SZ_4K 2682 drivers/usb/gadget/udc/renesas_usb3.c .ramsize_per_pipe = SZ_4K, SZ_4K 2688 drivers/usb/gadget/udc/renesas_usb3.c .ramsize_per_pipe = SZ_4K, SZ_4K 40 drivers/video/fbdev/omap2/omapfb/dss/dispc.c #define DISPC_SZ_REGS SZ_4K SZ_4K 87 fs/btrfs/tests/extent-map-tests.c em->len = SZ_4K; SZ_4K 89 fs/btrfs/tests/extent-map-tests.c em->block_len = SZ_4K; SZ_4K 174 fs/btrfs/tests/extent-map-tests.c em->start = SZ_4K; SZ_4K 175 fs/btrfs/tests/extent-map-tests.c em->len = SZ_4K; SZ_4K 176 fs/btrfs/tests/extent-map-tests.c em->block_start = SZ_4K; SZ_4K 177 fs/btrfs/tests/extent-map-tests.c em->block_len = SZ_4K; SZ_4K 226 fs/btrfs/tests/extent-map-tests.c u64 len = SZ_4K; SZ_4K 236 fs/btrfs/tests/extent-map-tests.c em->start = SZ_4K; SZ_4K 237 fs/btrfs/tests/extent-map-tests.c em->len = SZ_4K; SZ_4K 238 fs/btrfs/tests/extent-map-tests.c em->block_start = SZ_4K; SZ_4K 239 fs/btrfs/tests/extent-map-tests.c em->block_len = SZ_4K; SZ_4K 325 fs/btrfs/tests/extent-map-tests.c u64 len = SZ_4K; SZ_4K 435 fs/btrfs/tests/extent-map-tests.c ret = __test_case_4(fs_info, em_tree, SZ_4K); SZ_4K 183 include/linux/amba/bus.h .res = DEFINE_RES_MEM(base, SZ_4K), \ SZ_4K 194 include/linux/amba/bus.h .res = DEFINE_RES_MEM(base, SZ_4K), \ SZ_4K 217 sound/soc/amd/acp-pcm-dma.c + (pte_offset * SZ_4K) + (i * (size / 2)); SZ_4K 234 sound/soc/amd/acp-pcm-dma.c (pte_offset * SZ_4K) + (i * (size / 2)); SZ_4K 457 tools/testing/nvdimm/test/nfit.c nd_cmd->max_xfer = SZ_4K; SZ_4K 517 tools/testing/nvdimm/test/nfit.c ars_recs = SZ_4K / sizeof(struct nd_ars_record); SZ_4K 883 tools/testing/nvdimm/test/nfit.c int max = SZ_4K / sizeof(struct nd_error_stat_query_record); SZ_4K 1514 tools/testing/nvdimm/test/nfit.c sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL); SZ_4K 2773 tools/testing/nvdimm/test/nfit.c .max_xfer = SZ_4K, SZ_4K 2783 tools/testing/nvdimm/test/nfit.c || cmds.cfg_size.max_xfer != SZ_4K) { SZ_4K 68 virt/kvm/arm/vgic/vgic-kvm-device.c alignment = SZ_4K; SZ_4K 73 virt/kvm/arm/vgic/vgic-kvm-device.c alignment = SZ_4K; SZ_4K 479 virt/kvm/arm/vgic/vgic-mmio-v2.c return SZ_4K;