SZ_32M 78 arch/arm/include/asm/efi.h #define MAX_UNCOMP_KERNEL_SIZE SZ_32M SZ_32M 185 arch/arm/mach-davinci/board-da850-evm.c .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1, SZ_32M 93 arch/arm/mach-davinci/board-dm355-evm.c .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, SZ_32M 87 arch/arm/mach-davinci/board-dm355-leopard.c .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, SZ_32M 155 arch/arm/mach-davinci/board-dm365-evm.c .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, SZ_32M 102 arch/arm/mach-davinci/board-dm646x-evm.c .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1, SZ_32M 222 arch/arm/mach-davinci/board-omapl138-hawk.c .end = DA8XX_AEMIF_CS3_BASE + SZ_32M, SZ_32M 28 arch/arm/mach-ep93xx/adssphere.c ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); SZ_32M 46 arch/arm/mach-ep93xx/edb93xx.c ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); SZ_32M 432 arch/arm/mach-imx/mach-armadillo5x0.c .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, SZ_32M 134 arch/arm/mach-imx/mach-mx21ads.c DEFINE_RES_MEM(MX21_CS0_BASE_ADDR, SZ_32M); SZ_32M 166 arch/arm/mach-imx/mach-qong.c .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, SZ_32M 97 arch/arm/mach-imx/mx31.h #define MX31_CS4_SIZE SZ_32M SZ_32M 101 arch/arm/mach-imx/mx31.h #define MX31_CS5_SIZE SZ_32M SZ_32M 98 arch/arm/mach-imx/mx35.h #define MX35_CS4_SIZE SZ_32M SZ_32M 102 arch/arm/mach-imx/mx35.h #define MX35_CS5_SIZE SZ_32M SZ_32M 120 arch/arm/mach-imx/mx3x.h #define MX3x_CS4_SIZE SZ_32M SZ_32M 124 arch/arm/mach-imx/mx3x.h #define MX3x_CS5_SIZE SZ_32M SZ_32M 50 arch/arm/mach-integrator/hardware.h #define INTEGRATOR_FLASH_SIZE SZ_32M SZ_32M 368 arch/arm/mach-ixp4xx/common-pci.c local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M); SZ_32M 370 arch/arm/mach-ixp4xx/common-pci.c PHYS_OFFSET + SZ_32M + SZ_16M); SZ_32M 250 arch/arm/mach-ixp4xx/common.c ixp4xx_exp_bus_size = SZ_32M; SZ_32M 97 arch/arm/mach-ixp4xx/coyote-setup.c coyote_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; SZ_32M 91 arch/arm/mach-ixp4xx/gateway7001-setup.c gateway7001_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; SZ_32M 204 arch/arm/mach-ixp4xx/vulcan-setup.c vulcan_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; SZ_32M 92 arch/arm/mach-ixp4xx/wg302v2-setup.c wg302v2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; SZ_32M 167 arch/arm/mach-mmp/aspenite.c .size = SZ_32M + SZ_16M, SZ_32M 104 arch/arm/mach-mmp/ttc_dkb.c .size = SZ_32M + SZ_16M, SZ_32M 169 arch/arm/mach-omap1/board-fsample.c .end = OMAP_CS0_PHYS + SZ_32M - 1, SZ_32M 374 arch/arm/mach-omap1/board-h2.c h2_nor_resource.end += SZ_32M - 1; SZ_32M 402 arch/arm/mach-omap1/board-h3.c nor_resource.end += SZ_32M - 1; SZ_32M 105 arch/arm/mach-omap1/board-innovator.c .end = OMAP_CS0_PHYS + SZ_32M - 1, SZ_32M 573 arch/arm/mach-omap1/board-osk.c osk_flash_resource.end += SZ_32M - 1; SZ_32M 127 arch/arm/mach-omap1/board-perseus2.c .end = OMAP_CS0_PHYS + SZ_32M - 1, SZ_32M 269 arch/arm/mach-omap1/board-sx1.c .end = OMAP_CS0_PHYS + SZ_32M - 1, SZ_32M 45 arch/arm/mach-omap1/include/mach/tc.h #define OMAP_CS1A_SIZE SZ_32M SZ_32M 48 arch/arm/mach-omap1/include/mach/tc.h #define OMAP_CS1B_SIZE SZ_32M SZ_32M 54 arch/arm/mach-omap1/include/mach/tc.h #define OMAP_CS2A_SIZE SZ_32M SZ_32M 57 arch/arm/mach-omap1/include/mach/tc.h #define OMAP_CS2B_SIZE SZ_32M SZ_32M 54 arch/arm/mach-orion5x/db88f5281-setup.c #define DB88F5281_NOR_SIZE SZ_32M SZ_32M 181 arch/arm/mach-pxa/colibri-pxa270.c .end = PXA_CS0_PHYS + SZ_32M - 1, SZ_32M 760 arch/arm/mach-pxa/corgi.c memblock_add(0xa0000000, SZ_32M); SZ_32M 82 arch/arm/mach-pxa/h5000.c .end = PXA_CS0_PHYS + SZ_32M - 1, SZ_32M 87 arch/arm/mach-pxa/h5000.c .start = PXA_CS0_PHYS + SZ_32M, SZ_32M 88 arch/arm/mach-pxa/h5000.c .end = PXA_CS0_PHYS + SZ_32M + SZ_16M - 1, SZ_32M 459 arch/arm/mach-pxa/poodle.c memblock_add(0xa0000000, SZ_32M); SZ_32M 540 arch/arm/mach-pxa/saar.c .size = SZ_32M + SZ_16M, SZ_32M 315 arch/arm/mach-pxa/stargate2.c .end = PXA_CS0_PHYS + SZ_32M - 1, SZ_32M 765 arch/arm/mach-pxa/stargate2.c .end = PXA_CS1_PHYS + SZ_32M-1, SZ_32M 183 arch/arm/mach-pxa/trizeps4.c .end = PXA_CS0_PHYS + SZ_32M - 1, SZ_32M 651 arch/arm/mach-pxa/viper.c .end = VIPER_FLASH_PHYS + SZ_32M - 1, SZ_32M 82 arch/arm/mach-pxa/xcep.c .end = PXA_CS0_PHYS + SZ_32M - 1, SZ_32M 133 arch/arm/mach-s3c24xx/mach-anubis.c .size = SZ_32M - SZ_4M, SZ_32M 137 arch/arm/mach-s3c24xx/mach-anubis.c .offset = SZ_32M, SZ_32M 156 arch/arm/mach-s3c24xx/mach-anubis.c .size = SZ_32M - SZ_4M, SZ_32M 160 arch/arm/mach-s3c24xx/mach-anubis.c .offset = SZ_32M, SZ_32M 147 arch/arm/mach-s3c24xx/mach-osiris.c .size = SZ_32M - SZ_4M, SZ_32M 151 arch/arm/mach-s3c24xx/mach-osiris.c .offset = SZ_32M, SZ_32M 170 arch/arm/mach-s3c24xx/mach-osiris.c .size = SZ_32M - SZ_4M, SZ_32M 174 arch/arm/mach-s3c24xx/mach-osiris.c .offset = SZ_32M, SZ_32M 298 arch/arm/mach-sa1100/assabet.c DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), SZ_32M 299 arch/arm/mach-sa1100/assabet.c DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M), SZ_32M 130 arch/arm/mach-sa1100/cerf.c DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); SZ_32M 335 arch/arm/mach-sa1100/collie.c DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), SZ_32M 80 arch/arm/mach-sa1100/h3xxx.c DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); SZ_32M 136 arch/arm/mach-sa1100/hackkit.c DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); SZ_32M 360 arch/arm/mach-sa1100/jornada720.c DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); SZ_32M 59 arch/arm/mach-sa1100/nanoengine.c DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), SZ_32M 60 arch/arm/mach-sa1100/nanoengine.c DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M), SZ_32M 1151 arch/arm/mm/mmu.c if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { SZ_32M 1152 arch/arm/mm/mmu.c vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); SZ_32M 22 arch/nds32/include/asm/memory.h #define TASK_SIZE ((CONFIG_PAGE_OFFSET) - (SZ_32M)) SZ_32M 23 arch/nds32/include/asm/memory.h #define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_32M) SZ_32M 41 arch/nds32/include/asm/memory.h #define MODULES_VADDR (MODULES_END - SZ_32M) SZ_32M 2957 arch/powerpc/platforms/powernv/pci-ioda.c if (pdn->m64_single_mode && (size < SZ_32M)) SZ_32M 63 arch/sh/boards/board-edosk7760.c .end = 0x00000000 + SZ_32M - 1, SZ_32M 266 arch/unicore32/mm/mmu.c if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { SZ_32M 267 arch/unicore32/mm/mmu.c vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); SZ_32M 106 drivers/bus/imx-weim.c val = (val / SZ_32M) | 1; SZ_32M 20 drivers/crypto/hisilicon/sec/sec_algs.c #define SEC_REQ_LIMIT SZ_32M SZ_32M 1258 drivers/gpu/drm/i915/gem/selftests/huge_pages.c SZ_32M, SZ_32M 496 drivers/gpu/drm/panfrost/panfrost_drv.c drm_mm_init(&panfrost_priv->mm, SZ_32M >> PAGE_SHIFT, (SZ_4G - SZ_32M) >> PAGE_SHIFT); SZ_32M 3449 drivers/iommu/arm-smmu-v3.c smmu->pgsize_bitmap |= SZ_16K | SZ_32M; SZ_32M 1830 drivers/iommu/arm-smmu.c smmu->pgsize_bitmap |= SZ_16K | SZ_32M; SZ_32M 726 drivers/iommu/io-pgtable-arm.c page_sizes = (SZ_16K | SZ_32M); SZ_32M 1249 drivers/iommu/io-pgtable-arm.c SZ_16K | SZ_32M, SZ_32M 52 drivers/mmc/core/sd.c SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512, SZ_32M 151 drivers/pci/controller/pci-ftpci100.c case SZ_32M: SZ_32M 653 drivers/pci/controller/pci-v3-semi.c case SZ_32M: SZ_32M 204 drivers/staging/sm750fb/ddk750_chip.c data = SZ_32M; break; /* 32 Mega byte */ SZ_32M 91 fs/btrfs/ctree.h #define BTRFS_DIRTY_METADATA_THRESH SZ_32M SZ_32M 4789 fs/btrfs/inode.c if (be_nice && bytes_deleted > SZ_32M && SZ_32M 2836 fs/btrfs/qgroup.c #define QGROUP_FREE_SIZE SZ_32M SZ_32M 472 fs/btrfs/tests/extent-io-tests.c set_extent_bits(&tree, SZ_32M, SZ_64M - 1, SZ_32M 481 fs/btrfs/tests/extent-io-tests.c if (start != SZ_4M || end != SZ_32M - 1) { SZ_32M 494 fs/btrfs/tests/extent-io-tests.c if (start != SZ_4M || end != SZ_32M - 1) { SZ_32M 733 fs/btrfs/tests/free-space-tests.c ret = btrfs_add_free_space(cache, SZ_32M, 2 * sectorsize); SZ_32M 813 fs/btrfs/tests/free-space-tests.c if (offset != SZ_32M) { SZ_32M 5017 fs/btrfs/volumes.c max_stripe_size = SZ_32M; SZ_32M 328 mm/util.c return randomize_page(mm->brk, SZ_32M); SZ_32M 105 tools/testing/nvdimm/test/nfit.c DIMM_SIZE = SZ_32M,