SZ_2K 82 arch/arm/mach-omap1/dma.c .end = OMAP1_DMA_BASE + SZ_2K - 1, SZ_2K 31 arch/arm/mach-omap1/gpio15xx.c .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, SZ_2K 72 arch/arm/mach-omap1/gpio15xx.c .end = OMAP1510_GPIO_BASE + SZ_2K - 1, SZ_2K 39 arch/arm/mach-omap1/gpio16xx.c .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, SZ_2K 80 arch/arm/mach-omap1/gpio16xx.c .end = OMAP1610_GPIO1_BASE + SZ_2K - 1, SZ_2K 124 arch/arm/mach-omap1/gpio16xx.c .end = OMAP1610_GPIO2_BASE + SZ_2K - 1, SZ_2K 152 arch/arm/mach-omap1/gpio16xx.c .end = OMAP1610_GPIO3_BASE + SZ_2K - 1, SZ_2K 180 arch/arm/mach-omap1/gpio16xx.c .end = OMAP1610_GPIO4_BASE + SZ_2K - 1, SZ_2K 38 arch/arm/mach-omap1/gpio7xx.c .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, SZ_2K 79 arch/arm/mach-omap1/gpio7xx.c .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1, SZ_2K 118 arch/arm/mach-omap1/gpio7xx.c .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1, SZ_2K 146 arch/arm/mach-omap1/gpio7xx.c .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1, SZ_2K 174 arch/arm/mach-omap1/gpio7xx.c .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1, SZ_2K 202 arch/arm/mach-omap1/gpio7xx.c .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1, SZ_2K 230 arch/arm/mach-omap1/gpio7xx.c .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1, SZ_2K 133 arch/arm/mach-omap1/serial.c ioremap(serial_platform_data[i].mapbase, SZ_2K); SZ_2K 77 arch/arm/mach-tegra/iomap.h #define TEGRA_EMC0_SIZE SZ_2K SZ_2K 80 arch/arm/mach-tegra/iomap.h #define TEGRA_EMC1_SIZE SZ_2K SZ_2K 83 arch/arm/mach-tegra/iomap.h #define TEGRA124_EMC_SIZE SZ_2K SZ_2K 493 arch/arm64/include/asm/kvm_mmu.h vect += slot * SZ_2K; SZ_2K 123 arch/arm64/kernel/cpu_errata.c void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K); SZ_2K 126 arch/arm64/kernel/cpu_errata.c for (i = 0; i < SZ_2K; i += 0x80) SZ_2K 129 arch/arm64/kernel/cpu_errata.c __flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); SZ_2K 50 arch/sh/boards/mach-sdk7786/sram.c vaddr = ioremap(phys, SZ_2K); SZ_2K 58 arch/sh/boards/mach-sdk7786/sram.c SZ_2K >> 10, phys, phys + SZ_2K - 1, area); SZ_2K 60 arch/sh/boards/mach-sdk7786/sram.c ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1); SZ_2K 124 drivers/clk/imx/clk-imx21.c ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K); SZ_2K 277 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = SZ_2K * ln_size_mult; SZ_2K 572 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = SZ_2K; SZ_2K 817 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c omap_dmm->base = ioremap(mem->start, SZ_2K); SZ_2K 36 drivers/iio/adc/ti_am335x_adc.c #define DMA_BUFFER_SIZE SZ_2K SZ_2K 252 drivers/memory/pl353-smc.c case SZ_2K: SZ_2K 2153 drivers/mtd/nand/raw/marvell_nand.c if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) SZ_2K 2272 drivers/mtd/nand/raw/marvell_nand.c mtd->writesize != SZ_2K) { SZ_2K 31 drivers/mtd/nand/raw/nand_ids.c SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), SZ_2K 61 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c #define CMDQ_DB_OFF SZ_2K SZ_2K 29 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c #define SQ_DB_OFF SZ_2K SZ_2K 176 drivers/pcmcia/at91_cf.c io->stop = io->start + SZ_2K - 1; SZ_2K 341 drivers/pcmcia/at91_cf.c cf->socket.map_size = SZ_2K; SZ_2K 167 drivers/pcmcia/omap_cf.c io->stop = io->start + SZ_2K - 1; SZ_2K 182 drivers/pcmcia/omap_cf.c map->static_start += SZ_2K; SZ_2K 254 drivers/pcmcia/omap_cf.c ioremap(cf->phys_cf + SZ_4K, SZ_2K); SZ_2K 294 drivers/pcmcia/omap_cf.c cf->socket.map_size = SZ_2K; SZ_2K 952 drivers/perf/arm_spe_pmu.c if (spe_pmu->align > SZ_2K) { SZ_2K 1013 drivers/perf/arm_spe_pmu.c if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { SZ_2K 322 drivers/spi/spi-nxp-fspi.c .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ SZ_2K 2090 drivers/usb/gadget/udc/renesas_usb3.c else if (ram_size <= SZ_2K)