SZ_1K 413 arch/arc/kernel/setup.c if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz) SZ_1K 418 arch/arc/kernel/setup.c if (CONFIG_ARC_ICCM_SZ * SZ_1K != cpu->iccm.sz) SZ_1K 32 arch/arm/mach-clps711x/board-dt.c .length = 48 * SZ_1K, SZ_1K 251 arch/arm/mach-davinci/board-da850-evm.c .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, SZ_1K 444 arch/arm/mach-davinci/board-mityomapl138.c .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, SZ_1K 161 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_TPTC0_BASE + SZ_1K - 1, SZ_1K 167 arch/arm/mach-davinci/devices-da8xx.c .end = DA8XX_TPTC1_BASE + SZ_1K - 1, SZ_1K 192 arch/arm/mach-davinci/devices-da8xx.c .end = DA850_TPTC2_BASE + SZ_1K - 1, SZ_1K 452 arch/arm/mach-davinci/devices-da8xx.c .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, SZ_1K 487 arch/arm/mach-davinci/devices-da8xx.c .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1, SZ_1K 522 arch/arm/mach-davinci/devices-da8xx.c .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, SZ_1K 277 arch/arm/mach-davinci/devices.c .end = DAVINCI_WDOG_BASE + SZ_1K - 1, SZ_1K 268 arch/arm/mach-davinci/dm355.c .end = 0x01c10000 + SZ_1K - 1, SZ_1K 274 arch/arm/mach-davinci/dm355.c .end = 0x01c10400 + SZ_1K - 1, SZ_1K 740 arch/arm/mach-davinci/dm355.c pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); SZ_1K 759 arch/arm/mach-davinci/dm355.c .end = DAVINCI_PLL2_BASE + SZ_1K - 1, SZ_1K 500 arch/arm/mach-davinci/dm365.c .end = 0x01c10000 + SZ_1K - 1, SZ_1K 506 arch/arm/mach-davinci/dm365.c .end = 0x01c10400 + SZ_1K - 1, SZ_1K 512 arch/arm/mach-davinci/dm365.c .end = 0x01c10800 + SZ_1K - 1, SZ_1K 518 arch/arm/mach-davinci/dm365.c .end = 0x01c10c00 + SZ_1K - 1, SZ_1K 573 arch/arm/mach-davinci/dm365.c .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1, SZ_1K 598 arch/arm/mach-davinci/dm365.c .end = DM365_RTC_BASE + SZ_1K - 1, SZ_1K 627 arch/arm/mach-davinci/dm365.c .end = DM365_KEYSCAN_BASE + SZ_1K - 1, SZ_1K 777 arch/arm/mach-davinci/dm365.c pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); SZ_1K 780 arch/arm/mach-davinci/dm365.c pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K); SZ_1K 255 arch/arm/mach-davinci/dm644x.c .end = 0x01c10000 + SZ_1K - 1, SZ_1K 261 arch/arm/mach-davinci/dm644x.c .end = 0x01c10400 + SZ_1K - 1, SZ_1K 676 arch/arm/mach-davinci/dm644x.c pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); SZ_1K 695 arch/arm/mach-davinci/dm644x.c .end = DAVINCI_PLL2_BASE + SZ_1K - 1, SZ_1K 256 arch/arm/mach-davinci/dm646x.c .end = 0x01c10000 + SZ_1K - 1, SZ_1K 262 arch/arm/mach-davinci/dm646x.c .end = 0x01c10400 + SZ_1K - 1, SZ_1K 268 arch/arm/mach-davinci/dm646x.c .end = 0x01c10800 + SZ_1K - 1, SZ_1K 274 arch/arm/mach-davinci/dm646x.c .end = 0x01c10c00 + SZ_1K - 1, SZ_1K 304 arch/arm/mach-davinci/dm646x.c .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, SZ_1K 336 arch/arm/mach-davinci/dm646x.c .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, SZ_1K 660 arch/arm/mach-davinci/dm646x.c pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); SZ_1K 679 arch/arm/mach-davinci/dm646x.c .end = DAVINCI_PLL2_BASE + SZ_1K - 1, SZ_1K 147 arch/arm/mach-imx/mach-mx21ads.c DEFINE_RES_MEM(MX21ADS_CS8900A_REG, SZ_1K), SZ_1K 68 arch/arm/mach-mvebu/board-v7.c #define MVEBU_DDR_TRAINING_AREA_SZ (10 * SZ_1K) SZ_1K 179 arch/arm/mach-omap1/timer32k.c base = ioremap(OMAP1_32KSYNC_TIMER_BASE, SZ_1K); SZ_1K 29 arch/arm/mach-omap2/omap-secure.h #define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K) SZ_1K 41 arch/arm/mach-omap2/omap_phy_internal.c ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K); SZ_1K 47 arch/arm/mach-orion5x/db88f5281-setup.c #define DB88F5281_7SEG_SIZE SZ_1K SZ_1K 61 arch/arm/mach-orion5x/db88f5281-setup.c #define DB88F5281_NAND_SIZE SZ_1K SZ_1K 105 arch/arm/mach-s3c24xx/mach-jive.c .size = (160 * SZ_1K), SZ_1K 112 arch/arm/mach-s3c24xx/mach-jive.c .offset = (176 * SZ_1K), SZ_1K 113 arch/arm/mach-s3c24xx/mach-jive.c .size = (16 * SZ_1K), SZ_1K 120 arch/arm/mach-s3c24xx/mach-jive.c .offset = (192 * SZ_1K), SZ_1K 121 arch/arm/mach-s3c24xx/mach-jive.c .size = (SZ_2M) - (192 * SZ_1K), SZ_1K 140 arch/arm/mach-s3c24xx/mach-jive.c .offset = (160 * SZ_1K), SZ_1K 141 arch/arm/mach-s3c24xx/mach-jive.c .size = (16 * SZ_1K), SZ_1K 148 arch/arm/mach-s3c24xx/mach-jive.c .size = (2 * SZ_1M) - (192 * SZ_1K), SZ_1K 151 arch/arm/mach-s3c24xx/mach-jive.c .offset = (24 * SZ_1M) - (192*SZ_1K), SZ_1K 163 arch/arm/mach-s3c24xx/mach-jive.c .size = (160 * SZ_1K), SZ_1K 170 arch/arm/mach-s3c24xx/mach-jive.c .offset = (176 * SZ_1K), SZ_1K 171 arch/arm/mach-s3c24xx/mach-jive.c .size = (16 * SZ_1K), SZ_1K 179 arch/arm/mach-s3c24xx/mach-jive.c .size = (2 * SZ_1M) - (192 * SZ_1K), SZ_1K 184 arch/arm/mach-s3c24xx/mach-jive.c .offset = (24 * SZ_1M) - (192 * SZ_1K), SZ_1K 199 arch/arm/mach-s3c24xx/mach-jive.c .offset = (160 * SZ_1K), SZ_1K 200 arch/arm/mach-s3c24xx/mach-jive.c .size = (16 * SZ_1K), SZ_1K 206 arch/arm/mach-s3c24xx/mach-jive.c .offset = (192 * SZ_1K), SZ_1K 207 arch/arm/mach-s3c24xx/mach-jive.c .size = (2 * SZ_1M) - (192 * SZ_1K), SZ_1K 152 arch/arm/mach-s3c64xx/common.c .length = SZ_1K, SZ_1K 74 arch/arm/mach-tegra/iomap.h #define TEGRA_EMC_SIZE SZ_1K SZ_1K 13 arch/arm/mach-tegra/irammap.h #define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K SZ_1K 747 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K), SZ_1K 762 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K), SZ_1K 1048 arch/arm/plat-samsung/devs.c [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K), SZ_1K 164 arch/arm64/kernel/smp.c pr_crit("CPU%u: does not support %luK granule \n", cpu, PAGE_SIZE / SZ_1K); SZ_1K 152 arch/arm64/mm/fault.c mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, SZ_1K 96 drivers/android/binder.c #ifndef SZ_1K SZ_1K 5140 drivers/android/binder.c (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, SZ_1K 5151 drivers/android/binder.c (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, SZ_1K 5179 drivers/android/binder.c (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, SZ_1K 766 drivers/bus/ti-sysc.c if (size < SZ_1K) SZ_1K 767 drivers/bus/ti-sysc.c size = SZ_1K; SZ_1K 3392 drivers/dma/ste_dma40.c base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; SZ_1K 3426 drivers/dma/ste_dma40.c base->lcla_pool.base_unaligned = kmalloc(SZ_1K * SZ_1K 3440 drivers/dma/ste_dma40.c SZ_1K * base->num_phy_chans, SZ_1K 3672 drivers/dma/ste_dma40.c SZ_1K * base->num_phy_chans, SZ_1K 1071 drivers/edac/thunderx_edac.c #define OCX_MESSAGE_SIZE SZ_1K SZ_1K 1735 drivers/edac/thunderx_edac.c #define L2C_MESSAGE_SIZE SZ_1K SZ_1K 278 drivers/gpu/drm/arm/malidp_hw.c hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult; SZ_1K 592 drivers/gpu/drm/arm/malidp_hw.c hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K; SZ_1K 923 drivers/gpu/drm/arm/malidp_hw.c hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K; SZ_1K 117 drivers/gpu/drm/i915/intel_wopcm.c guc_wopcm_size / SZ_1K, SZ_1K 118 drivers/gpu/drm/i915/intel_wopcm.c (u32)(offset + sizeof(u32)) / SZ_1K); SZ_1K 136 drivers/gpu/drm/i915/intel_wopcm.c (guc_wopcm_size - GUC_WOPCM_RESERVED) / SZ_1K, SZ_1K 171 drivers/gpu/drm/i915/intel_wopcm.c guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K, SZ_1K 172 drivers/gpu/drm/i915/intel_wopcm.c size / SZ_1K); SZ_1K 180 drivers/gpu/drm/i915/intel_wopcm.c guc_wopcm_size / SZ_1K, size / SZ_1K); SZ_1K 188 drivers/gpu/drm/i915/intel_wopcm.c guc_wopcm_base / SZ_1K, size / SZ_1K); SZ_1K 247 drivers/gpu/drm/i915/intel_wopcm.c guc_wopcm_base / SZ_1K, SZ_1K 248 drivers/gpu/drm/i915/intel_wopcm.c guc_wopcm_size / SZ_1K); SZ_1K 270 drivers/gpu/drm/i915/intel_wopcm.c guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K); SZ_1K 1218 drivers/gpu/drm/msm/adreno/a5xx_gpu.c offset = dumper.iova + (256 * SZ_1K); SZ_1K 1256 drivers/gpu/drm/msm/adreno/a5xx_gpu.c memcpy(a5xx_state->hlsqregs, dumper.ptr + (256 * SZ_1K), SZ_1K 1876 drivers/irqchip/irq-gic-v3-its.c psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); SZ_1K 33 drivers/media/platform/mtk-vpu/mtk_vpu.c #define VPU_PTCM_SIZE (96 * SZ_1K) SZ_1K 34 drivers/media/platform/mtk-vpu/mtk_vpu.c #define VPU_DTCM_SIZE (32 * SZ_1K) SZ_1K 45 drivers/media/platform/s5p-mfc/regs-mfc-v10.h #define MFC_CTX_BUF_SIZE_V10 (30 * SZ_1K) SZ_1K 47 drivers/media/platform/s5p-mfc/regs-mfc-v10.h #define MFC_OTHER_DEC_CTX_BUF_SIZE_V10 (20 * SZ_1K) SZ_1K 48 drivers/media/platform/s5p-mfc/regs-mfc-v10.h #define MFC_H264_ENC_CTX_BUF_SIZE_V10 (100 * SZ_1K) SZ_1K 49 drivers/media/platform/s5p-mfc/regs-mfc-v10.h #define MFC_HEVC_ENC_CTX_BUF_SIZE_V10 (30 * SZ_1K) SZ_1K 50 drivers/media/platform/s5p-mfc/regs-mfc-v10.h #define MFC_OTHER_ENC_CTX_BUF_SIZE_V10 (15 * SZ_1K) SZ_1K 396 drivers/media/platform/s5p-mfc/regs-mfc-v6.h #define MFC_CTX_BUF_SIZE_V6 (28 * SZ_1K) /* 28KB */ SZ_1K 398 drivers/media/platform/s5p-mfc/regs-mfc-v6.h #define MFC_OTHER_DEC_CTX_BUF_SIZE_V6 (20 * SZ_1K) /* 20KB */ SZ_1K 399 drivers/media/platform/s5p-mfc/regs-mfc-v6.h #define MFC_H264_ENC_CTX_BUF_SIZE_V6 (100 * SZ_1K) /* 100KB */ SZ_1K 400 drivers/media/platform/s5p-mfc/regs-mfc-v6.h #define MFC_OTHER_ENC_CTX_BUF_SIZE_V6 (12 * SZ_1K) /* 12KB */ SZ_1K 43 drivers/media/platform/s5p-mfc/regs-mfc-v7.h #define MFC_CTX_BUF_SIZE_V7 (30 * SZ_1K) /* 30KB */ SZ_1K 45 drivers/media/platform/s5p-mfc/regs-mfc-v7.h #define MFC_OTHER_DEC_CTX_BUF_SIZE_V7 (20 * SZ_1K) /* 20KB */ SZ_1K 46 drivers/media/platform/s5p-mfc/regs-mfc-v7.h #define MFC_H264_ENC_CTX_BUF_SIZE_V7 (100 * SZ_1K) /* 100KB */ SZ_1K 47 drivers/media/platform/s5p-mfc/regs-mfc-v7.h #define MFC_OTHER_ENC_CTX_BUF_SIZE_V7 (10 * SZ_1K) /* 10KB */ SZ_1K 92 drivers/media/platform/s5p-mfc/regs-mfc-v8.h #define MFC_CTX_BUF_SIZE_V8 (36 * SZ_1K) /* 36KB */ SZ_1K 94 drivers/media/platform/s5p-mfc/regs-mfc-v8.h #define MFC_OTHER_DEC_CTX_BUF_SIZE_V8 (20 * SZ_1K) /* 20KB */ SZ_1K 95 drivers/media/platform/s5p-mfc/regs-mfc-v8.h #define MFC_H264_ENC_CTX_BUF_SIZE_V8 (100 * SZ_1K) /* 100KB */ SZ_1K 96 drivers/media/platform/s5p-mfc/regs-mfc-v8.h #define MFC_OTHER_ENC_CTX_BUF_SIZE_V8 (10 * SZ_1K) /* 10KB */ SZ_1K 437 drivers/media/platform/s5p-mfc/regs-mfc.h #define FIRMWARE_ALIGN (128 * SZ_1K) /* 128KB */ SZ_1K 438 drivers/media/platform/s5p-mfc/regs-mfc.h #define MFC_H264_CTX_BUF_SIZE (600 * SZ_1K) /* 600KB per H264 instance */ SZ_1K 439 drivers/media/platform/s5p-mfc/regs-mfc.h #define MFC_CTX_BUF_SIZE (10 * SZ_1K) /* 10KB per instance */ SZ_1K 440 drivers/media/platform/s5p-mfc/regs-mfc.h #define DESC_BUF_SIZE (128 * SZ_1K) /* 128KB for DESC buffer */ SZ_1K 441 drivers/media/platform/s5p-mfc/regs-mfc.h #define SHARED_BUF_SIZE (8 * SZ_1K) /* 8KB for shared buffer */ SZ_1K 443 drivers/media/platform/s5p-mfc/regs-mfc.h #define DEF_CPB_SIZE (256 * SZ_1K) /* 256KB */ SZ_1K 445 drivers/media/platform/s5p-mfc/regs-mfc.h #define MAX_FW_SIZE (384 * SZ_1K) SZ_1K 249 drivers/memory/pl353-smc.c case SZ_1K: SZ_1K 269 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c case SZ_1K: SZ_1K 41 drivers/mtd/nand/raw/nand_ids.c SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) }, SZ_1K 44 drivers/mtd/nand/raw/nand_ids.c SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, SZ_1K 47 drivers/mtd/nand/raw/nand_ids.c SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, SZ_1K 50 drivers/mtd/nand/raw/nand_ids.c SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, SZ_1K 54 drivers/mtd/nand/raw/nand_ids.c NAND_ECC_INFO(40, SZ_1K), 4 }, SZ_1K 101 drivers/mtd/parsers/bcm63xxpart.c nvramlen = nvram->psi_size * SZ_1K; SZ_1K 24 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) SZ_1K 26 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) SZ_1K 29 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define MBOX_UP_RX_SIZE SZ_1K SZ_1K 31 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define MBOX_UP_TX_SIZE SZ_1K SZ_1K 1012 drivers/nvdimm/namespace_devs.c (PAGE_SIZE * nd_region->ndr_mappings) / SZ_1K); SZ_1K 106 drivers/pci/controller/dwc/pci-keystone.c #define APP_ADDR_SPACE_0 (16 * SZ_1K) SZ_1K 474 drivers/pci/controller/pci-xgene.c if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) { SZ_1K 187 drivers/pci/controller/pcie-iproc.c .size_unit = SZ_1K, SZ_1K 27 drivers/platform/mellanox/mlxbf-tmfifo.c #define MLXBF_TMFIFO_VRING_SIZE SZ_1K SZ_1K 80 drivers/remoteproc/keystone_remoteproc.c if (boot_addr & (SZ_1K - 1)) { SZ_1K 1175 drivers/rpmsg/qcom_glink_native.c __be32 defaults[] = { cpu_to_be32(SZ_1K), cpu_to_be32(5) }; SZ_1K 41 drivers/soc/qcom/llcc-slice.c #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) SZ_1K 44 drivers/soc/ti/knav_qmss.h #define ACC_DESCS_MAX SZ_1K SZ_1K 206 drivers/spi/spi-fsl-qspi.c .ahb_buf_size = SZ_1K, SZ_1K 214 drivers/spi/spi-fsl-qspi.c .ahb_buf_size = SZ_1K, SZ_1K 222 drivers/spi/spi-fsl-qspi.c .ahb_buf_size = SZ_1K, SZ_1K 231 drivers/spi/spi-fsl-qspi.c .ahb_buf_size = SZ_1K, SZ_1K 240 drivers/spi/spi-fsl-qspi.c .ahb_buf_size = SZ_1K, SZ_1K 248 drivers/spi/spi-fsl-qspi.c .ahb_buf_size = SZ_1K, SZ_1K 321 drivers/spi/spi-nxp-fspi.c .txfifo = SZ_1K, /* (128 * 64 bits) */ SZ_1K 16 drivers/staging/media/meson/vdec/codec_mpeg12.c #define WORKSPACE_OFFSET (5 * SZ_1K) SZ_1K 45 drivers/staging/media/meson/vdec/codec_mpeg12.c static const u8 eos_sequence[SZ_1K] = { 0x00, 0x00, 0x01, 0xB7 }; SZ_1K 130 drivers/staging/media/meson/vdec/esparser.c vififo_usage += (6 * SZ_1K); // 6 KiB internal fifo SZ_1K 40 drivers/staging/media/sunxi/cedrus/cedrus_h264.c #define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) SZ_1K 41 drivers/staging/media/sunxi/cedrus/cedrus_h264.c #define CEDRUS_PIC_INFO_BUF_SIZE (128 * SZ_1K) SZ_1K 238 drivers/staging/media/sunxi/cedrus/cedrus_video.c f->fmt.pix.sizeimage = SZ_1K; SZ_1K 2088 drivers/usb/gadget/udc/renesas_usb3.c if (ram_size <= SZ_1K) SZ_1K 565 drivers/video/fbdev/omap/sossi.c sossi.base = ioremap(OMAP_SOSSI_BASE, SZ_1K); SZ_1K 16 fs/btrfs/send.h #define BTRFS_SEND_READ_SIZE (48 * SZ_1K) SZ_1K 154 fs/btrfs/tests/extent-map-tests.c em->len = SZ_1K; SZ_1K 196 fs/btrfs/tests/extent-map-tests.c em->len = SZ_1K; SZ_1K 207 fs/btrfs/tests/extent-map-tests.c (em->start != 0 || extent_map_end(em) != SZ_1K || SZ_1K 316 fs/btrfs/tests/extent-map-tests.c ret = __test_case_3(fs_info, em_tree, (12 * SZ_1K)); SZ_1K 357 fs/btrfs/tests/extent-map-tests.c em->len = 24 * SZ_1K; SZ_1K 359 fs/btrfs/tests/extent-map-tests.c em->block_len = 24 * SZ_1K; SZ_1K 460 fs/btrfs/tests/free-space-tests.c SZ_128M + 768 * SZ_1K, SZ_1K 461 fs/btrfs/tests/free-space-tests.c SZ_128M - 768 * SZ_1K); SZ_1K 481 fs/btrfs/tests/free-space-tests.c if (test_check_exists(cache, SZ_128M + 768 * SZ_1K, SZ_1K 482 fs/btrfs/tests/free-space-tests.c SZ_128M - 768 * SZ_1K)) { SZ_1K 669 fs/btrfs/tests/free-space-tests.c ret = btrfs_remove_free_space(cache, 0, SZ_128M - 768 * SZ_1K); SZ_1K 680 fs/btrfs/tests/free-space-tests.c if (!test_check_exists(cache, SZ_128M - 768 * SZ_1K, SZ_256K)) { SZ_1K 689 fs/btrfs/tests/free-space-tests.c if (test_check_exists(cache, 0, SZ_128M - 768 * SZ_1K)) { SZ_1K 778 fs/btrfs/tests/free-space-tests.c if (!test_check_exists(cache, SZ_128M - 768 * SZ_1K, SZ_1M)) { SZ_1K 790 fs/btrfs/tests/free-space-tests.c if (offset != (SZ_128M - 768 * SZ_1K)) { SZ_1K 19 include/linux/bcm963xx_nvram.h #define BCM963XX_NVRAM_V5_SIZE (1 * SZ_1K) SZ_1K 58 include/linux/bcm963xx_nvram.h return nvram->nand_part_offset[part] * SZ_1K; SZ_1K 68 include/linux/bcm963xx_nvram.h return nvram->nand_part_size[part] * SZ_1K; SZ_1K 30 lib/test_firmware.c #define TEST_FIRMWARE_BUF_SIZE SZ_1K SZ_1K 198 net/rds/ib_recv.c atomic_add(RDS_FRAG_SIZE / SZ_1K, &ic->i_cache_allocs); SZ_1K 285 net/rds/ib_recv.c atomic_sub(RDS_FRAG_SIZE / SZ_1K, &ic->i_cache_allocs); SZ_1K 55 net/rds/send.c static int send_batch_count = SZ_1K;