SYS_GPCPLL_CFG_BASE   35 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPCPLL_CFG		(SYS_GPCPLL_CFG_BASE + 0)
SYS_GPCPLL_CFG_BASE   41 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPCPLL_CFG2		(SYS_GPCPLL_CFG_BASE + 0xc)
SYS_GPCPLL_CFG_BASE   45 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPCPLL_CFG3			(SYS_GPCPLL_CFG_BASE + 0x18)
SYS_GPCPLL_CFG_BASE   53 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPCPLL_COEFF		(SYS_GPCPLL_CFG_BASE + 4)
SYS_GPCPLL_CFG_BASE   63 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPCPLL_NDIV_SLOWDOWN			(SYS_GPCPLL_CFG_BASE + 0x1c)
SYS_GPCPLL_CFG_BASE   76 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define SEL_VCO				(SYS_GPCPLL_CFG_BASE + 0x100)
SYS_GPCPLL_CFG_BASE   79 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPC2CLK_OUT			(SYS_GPCPLL_CFG_BASE + 0x250)
SYS_GPCPLL_CFG_BASE   34 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define BYPASSCTRL_SYS	(SYS_GPCPLL_CFG_BASE + 0x340)
SYS_GPCPLL_CFG_BASE   49 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define GPCPLL_DVFS0	(SYS_GPCPLL_CFG_BASE + 0x10)
SYS_GPCPLL_CFG_BASE   59 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define GPCPLL_DVFS1		(SYS_GPCPLL_CFG_BASE + 0x14)