SUN8I_HDMI_PHY_PLL_CFG1_REG  307 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c 	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
SUN8I_HDMI_PHY_PLL_CFG1_REG  316 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c 	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
SUN8I_HDMI_PHY_PLL_CFG1_REG  327 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c 	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
SUN8I_HDMI_PHY_PLL_CFG1_REG  332 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c 	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
SUN8I_HDMI_PHY_PLL_CFG1_REG  381 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c 	regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0);
SUN8I_HDMI_PHY_PLL_CFG1_REG  504 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c 	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
SUN8I_HDMI_PHY_PLL_CFG1_REG  113 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c 	regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, &reg);
SUN8I_HDMI_PHY_PLL_CFG1_REG  127 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c 	regmap_update_bits(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,