SUN4I_HDMI_DDC_CTRL_REG  355 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 	.field_ddc_en		= REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
SUN4I_HDMI_DDC_CTRL_REG  356 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 	.field_ddc_start	= REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
SUN4I_HDMI_DDC_CTRL_REG  357 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 	.field_ddc_reset	= REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
SUN4I_HDMI_DDC_CTRL_REG  406 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 	.field_ddc_en		= REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
SUN4I_HDMI_DDC_CTRL_REG  407 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 	.field_ddc_start	= REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
SUN4I_HDMI_DDC_CTRL_REG  408 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 	.field_ddc_reset	= REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
SUN4I_HDMI_DDC_CTRL_REG   77 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c 		reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
SUN4I_HDMI_DDC_CTRL_REG   82 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c 		writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);