STMP_OFFSET_REG_SET   77 drivers/clocksource/mxs_timer.c 		     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  221 drivers/dma/mxs-dma.c 			mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  246 drivers/dma/mxs-dma.c 			mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  291 drivers/dma/mxs-dma.c 			mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  294 drivers/dma/mxs-dma.c 			mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  707 drivers/dma/mxs-dma.c 			mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  709 drivers/dma/mxs-dma.c 			mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  714 drivers/dma/mxs-dma.c 		mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  162 drivers/iio/adc/mxs-lradc-adc.c 		       adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  170 drivers/iio/adc/mxs-lradc-adc.c 	writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  176 drivers/iio/adc/mxs-lradc-adc.c 	       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  177 drivers/iio/adc/mxs-lradc-adc.c 	writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  440 drivers/iio/adc/mxs-lradc-adc.c 	const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
STMP_OFFSET_REG_SET  512 drivers/iio/adc/mxs-lradc-adc.c 	writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  513 drivers/iio/adc/mxs-lradc-adc.c 	writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  515 drivers/iio/adc/mxs-lradc-adc.c 	       adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  103 drivers/input/touchscreen/mxs-lradc-ts.c 	       ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  285 drivers/input/touchscreen/mxs-lradc-ts.c 	       ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  307 drivers/input/touchscreen/mxs-lradc-ts.c 	       ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  333 drivers/input/touchscreen/mxs-lradc-ts.c 	       ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  359 drivers/input/touchscreen/mxs-lradc-ts.c 	       ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  376 drivers/input/touchscreen/mxs-lradc-ts.c 	       ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  384 drivers/input/touchscreen/mxs-lradc-ts.c 	       ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  452 drivers/input/touchscreen/mxs-lradc-ts.c 	       ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  572 drivers/input/touchscreen/mxs-lradc-ts.c 			       ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  522 drivers/mmc/host/mxs-mmc.c 		       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  524 drivers/mmc/host/mxs-mmc.c 		       ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET   76 drivers/nvmem/mxs-ocotp.c 	writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET   85 drivers/rtc/rtc-stmp3xxx.c 		       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET   87 drivers/rtc/rtc-stmp3xxx.c 		       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  191 drivers/rtc/rtc-stmp3xxx.c 				STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  193 drivers/rtc/rtc-stmp3xxx.c 			rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  343 drivers/rtc/rtc-stmp3xxx.c 			STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET   91 drivers/spi/spi-mxs.c 		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  311 drivers/spi/spi-mxs.c 			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  317 drivers/spi/spi-mxs.c 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  327 drivers/spi/spi-mxs.c 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  330 drivers/spi/spi-mxs.c 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  339 drivers/spi/spi-mxs.c 			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  374 drivers/spi/spi-mxs.c 	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET  413 drivers/spi/spi-mxs.c 				STMP_OFFSET_REG_SET);
STMP_OFFSET_REG_SET   52 lib/stmp_device.c 	writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET);