BCS0             2135 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	[I915_EXEC_BLT]		= BCS0,
BCS0               18 drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
BCS0              115 drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 	if (!HAS_ENGINE(i915, BCS0))
BCS0               18 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c 	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
BCS0              109 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c 	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
BCS0              221 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c 	if (!HAS_ENGINE(i915, BCS0))
BCS0               79 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	[BCS0] = {
BCS0              157 drivers/gpu/drm/i915/gt/intel_engine_user.c 		[COPY_ENGINE_CLASS] = { BCS0, 1 },
BCS0             3066 drivers/gpu/drm/i915/gt/intel_lrc.c 			[BCS0]  = GEN8_BCS_IRQ_SHIFT,
BCS0              333 drivers/gpu/drm/i915/gt/intel_mocs.c 	case BCS0:
BCS0              288 drivers/gpu/drm/i915/gt/intel_reset.c 		[BCS0]  = GEN6_GRDOM_BLT,
BCS0              411 drivers/gpu/drm/i915/gt/intel_reset.c 		[BCS0]  = GEN11_GRDOM_BLT,
BCS0              552 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		case BCS0:
BCS0             1768 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915))
BCS0              414 drivers/gpu/drm/i915/gvt/cmd_parser.c #define R_BCS	BIT(BCS0)
BCS0              602 drivers/gpu/drm/i915/gvt/cmd_parser.c 	[BCS0] = {
BCS0              981 drivers/gpu/drm/i915/gvt/cmd_parser.c 			if (s->ring_id == BCS0 &&
BCS0             1086 drivers/gpu/drm/i915/gvt/cmd_parser.c 	[BCS0] = {
BCS0               51 drivers/gpu/drm/i915/gvt/execlist.c 	[BCS0]  = BCS_AS_CONTEXT_SWITCH,
BCS0              334 drivers/gpu/drm/i915/gvt/handlers.c 			engine_mask |= BIT(BCS0);
BCS0             1765 drivers/gpu/drm/i915/gvt/handlers.c 		id = BCS0;
BCS0               68 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
BCS0               69 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
BCS0               70 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
BCS0               71 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
BCS0               72 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
BCS0              120 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
BCS0              121 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
BCS0              122 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
BCS0              123 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
BCS0              124 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
BCS0              155 drivers/gpu/drm/i915/gvt/mmio_context.c 	[BCS0]  = 0xcc00,
BCS0              342 drivers/gpu/drm/i915/gvt/mmio_context.c 	[BCS0]  = 0x426c,
BCS0              402 drivers/gpu/drm/i915/gvt/mmio_context.c 		[BCS0]  = 0xcc00,
BCS0             1118 drivers/gpu/drm/i915/i915_gpu_error.c 			case BCS0:
BCS0              369 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
BCS0              417 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
BCS0              483 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
BCS0              493 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
BCS0              557 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
BCS0              566 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
BCS0              616 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
BCS0              633 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
BCS0              690 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
BCS0              711 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
BCS0              760 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
BCS0              767 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
BCS0              799 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),