STAGE_MAX         218 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
STAGE_MAX         227 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
STAGE_MAX         228 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
STAGE_MAX         286 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	for (i = STAGE0; i <= STAGE_MAX; i++) {
STAGE_MAX         616 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct plane_state pstates[STAGE_MAX + 1];
STAGE_MAX         370 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	for (i = start_stage; stage_cnt && i <= STAGE_MAX; i++) {