SSPP_VIG2         192 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
SSPP_VIG2         127 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	case SSPP_VIG2:
SSPP_VIG2         342 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 			case SSPP_VIG2:
SSPP_VIG2         386 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2},
SSPP_VIG2         387 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2,
SSPP_VIG2         141 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_VIG2] = (value >> 8) & 0x3;
SSPP_VIG2         238 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_VIG2] = (value >> 8) & 0x1;
SSPP_VIG2         541 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
SSPP_VIG2          28 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
SSPP_VIG2         112 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
SSPP_VIG2         196 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
SSPP_VIG2         358 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
SSPP_VIG2         292 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage);
SSPP_VIG2         315 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3;
SSPP_VIG2         443 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2;
SSPP_VIG2         831 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,